1 /*- 2 * Copyright (c) 1995, David Greenman 3 * Copyright (c) 2001 Jonathan Lemon <jlemon@freebsd.org> 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice unmodified, this list of conditions, and the following 11 * disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 * 28 * $FreeBSD$ 29 */ 30 31 /* 32 * Intel EtherExpress Pro/100B PCI Fast Ethernet driver 33 */ 34 35 #include "vlan.h" 36 37 #include <sys/param.h> 38 #include <sys/systm.h> 39 #include <sys/mbuf.h> 40 #include <sys/malloc.h> 41 /* #include <sys/mutex.h> */ 42 #include <sys/kernel.h> 43 #include <sys/socket.h> 44 45 #include <net/if.h> 46 #include <net/if_dl.h> 47 #include <net/if_media.h> 48 49 #ifdef NS 50 #include <netns/ns.h> 51 #include <netns/ns_if.h> 52 #endif 53 54 #include <net/bpf.h> 55 #include <sys/sockio.h> 56 #include <sys/bus.h> 57 #include <machine/bus.h> 58 #include <sys/rman.h> 59 #include <machine/resource.h> 60 61 #include <net/ethernet.h> 62 #include <net/if_arp.h> 63 64 #include <vm/vm.h> /* for vtophys */ 65 #include <vm/pmap.h> /* for vtophys */ 66 #include <machine/clock.h> /* for DELAY */ 67 68 #if NVLAN > 0 69 #include <net/if_types.h> 70 #include <net/if_vlan_var.h> 71 #endif 72 73 #include <pci/pcivar.h> 74 #include <pci/pcireg.h> /* for PCIM_CMD_xxx */ 75 76 #include <dev/mii/mii.h> 77 #include <dev/mii/miivar.h> 78 79 #include <dev/fxp/if_fxpreg.h> 80 #include <dev/fxp/if_fxpvar.h> 81 82 MODULE_DEPEND(fxp, miibus, 1, 1, 1); 83 #include "miibus_if.h" 84 85 /* 86 * NOTE! On the Alpha, we have an alignment constraint. The 87 * card DMAs the packet immediately following the RFA. However, 88 * the first thing in the packet is a 14-byte Ethernet header. 89 * This means that the packet is misaligned. To compensate, 90 * we actually offset the RFA 2 bytes into the cluster. This 91 * alignes the packet after the Ethernet header at a 32-bit 92 * boundary. HOWEVER! This means that the RFA is misaligned! 93 */ 94 #define RFA_ALIGNMENT_FUDGE 2 95 96 /* 97 * Set initial transmit threshold at 64 (512 bytes). This is 98 * increased by 64 (512 bytes) at a time, to maximum of 192 99 * (1536 bytes), if an underrun occurs. 100 */ 101 static int tx_threshold = 64; 102 103 /* 104 * The configuration byte map has several undefined fields which 105 * must be one or must be zero. Set up a template for these bits 106 * only, (assuming a 82557 chip) leaving the actual configuration 107 * to fxp_init. 108 * 109 * See struct fxp_cb_config for the bit definitions. 110 */ 111 static u_char fxp_cb_config_template[] = { 112 0x0, 0x0, /* cb_status */ 113 0x0, 0x0, /* cb_command */ 114 0x0, 0x0, 0x0, 0x0, /* link_addr */ 115 0x0, /* 0 */ 116 0x0, /* 1 */ 117 0x0, /* 2 */ 118 0x0, /* 3 */ 119 0x0, /* 4 */ 120 0x0, /* 5 */ 121 0x32, /* 6 */ 122 0x0, /* 7 */ 123 0x0, /* 8 */ 124 0x0, /* 9 */ 125 0x6, /* 10 */ 126 0x0, /* 11 */ 127 0x0, /* 12 */ 128 0x0, /* 13 */ 129 0xf2, /* 14 */ 130 0x48, /* 15 */ 131 0x0, /* 16 */ 132 0x40, /* 17 */ 133 0xf0, /* 18 */ 134 0x0, /* 19 */ 135 0x3f, /* 20 */ 136 0x5 /* 21 */ 137 }; 138 139 struct fxp_ident { 140 u_int16_t devid; 141 char *name; 142 }; 143 144 /* 145 * Claim various Intel PCI device identifiers for this driver. The 146 * sub-vendor and sub-device field are extensively used to identify 147 * particular variants, but we don't currently differentiate between 148 * them. 149 */ 150 static struct fxp_ident fxp_ident_table[] = { 151 { 0x1229, "Intel Pro 10/100B/100+ Ethernet" }, 152 { 0x2449, "Intel Pro/100 Ethernet" }, 153 { 0x1209, "Intel Embedded 10/100 Ethernet" }, 154 { 0x1029, "Intel Pro/100 Ethernet" }, 155 { 0x1030, "Intel Pro/100 Ethernet" }, 156 { 0x1031, "Intel Pro/100 Ethernet" }, 157 { 0x1032, "Intel Pro/100 Ethernet" }, 158 { 0x1033, "Intel Pro/100 Ethernet" }, 159 { 0x1034, "Intel Pro/100 Ethernet" }, 160 { 0x1035, "Intel Pro/100 Ethernet" }, 161 { 0x1036, "Intel Pro/100 Ethernet" }, 162 { 0x1037, "Intel Pro/100 Ethernet" }, 163 { 0x1038, "Intel Pro/100 Ethernet" }, 164 { 0, NULL }, 165 }; 166 167 static int fxp_probe(device_t dev); 168 static int fxp_attach(device_t dev); 169 static int fxp_detach(device_t dev); 170 static int fxp_shutdown(device_t dev); 171 static int fxp_suspend(device_t dev); 172 static int fxp_resume(device_t dev); 173 174 static void fxp_intr(void *xsc); 175 static void fxp_init(void *xsc); 176 static void fxp_tick(void *xsc); 177 static void fxp_start(struct ifnet *ifp); 178 static void fxp_stop(struct fxp_softc *sc); 179 static void fxp_release(struct fxp_softc *sc); 180 static int fxp_ioctl(struct ifnet *ifp, u_long command, 181 caddr_t data); 182 static void fxp_watchdog(struct ifnet *ifp); 183 static int fxp_add_rfabuf(struct fxp_softc *sc, struct mbuf *oldm); 184 static void fxp_mc_setup(struct fxp_softc *sc); 185 static u_int16_t fxp_eeprom_getword(struct fxp_softc *sc, int offset, 186 int autosize); 187 static void fxp_autosize_eeprom(struct fxp_softc *sc); 188 static void fxp_read_eeprom(struct fxp_softc *sc, u_short *data, 189 int offset, int words); 190 static int fxp_ifmedia_upd(struct ifnet *ifp); 191 static void fxp_ifmedia_sts(struct ifnet *ifp, 192 struct ifmediareq *ifmr); 193 static int fxp_serial_ifmedia_upd(struct ifnet *ifp); 194 static void fxp_serial_ifmedia_sts(struct ifnet *ifp, 195 struct ifmediareq *ifmr); 196 static volatile int fxp_miibus_readreg(device_t dev, int phy, int reg); 197 static void fxp_miibus_writereg(device_t dev, int phy, int reg, 198 int value); 199 static __inline void fxp_lwcopy(volatile u_int32_t *src, 200 volatile u_int32_t *dst); 201 static __inline void fxp_scb_wait(struct fxp_softc *sc); 202 static __inline void fxp_scb_cmd(struct fxp_softc *sc, int cmd); 203 static __inline void fxp_dma_wait(volatile u_int16_t *status, 204 struct fxp_softc *sc); 205 206 static device_method_t fxp_methods[] = { 207 /* Device interface */ 208 DEVMETHOD(device_probe, fxp_probe), 209 DEVMETHOD(device_attach, fxp_attach), 210 DEVMETHOD(device_detach, fxp_detach), 211 DEVMETHOD(device_shutdown, fxp_shutdown), 212 DEVMETHOD(device_suspend, fxp_suspend), 213 DEVMETHOD(device_resume, fxp_resume), 214 215 /* MII interface */ 216 DEVMETHOD(miibus_readreg, fxp_miibus_readreg), 217 DEVMETHOD(miibus_writereg, fxp_miibus_writereg), 218 219 { 0, 0 } 220 }; 221 222 static driver_t fxp_driver = { 223 "fxp", 224 fxp_methods, 225 sizeof(struct fxp_softc), 226 }; 227 228 static devclass_t fxp_devclass; 229 230 DRIVER_MODULE(if_fxp, pci, fxp_driver, fxp_devclass, 0, 0); 231 DRIVER_MODULE(if_fxp, cardbus, fxp_driver, fxp_devclass, 0, 0); 232 DRIVER_MODULE(miibus, fxp, miibus_driver, miibus_devclass, 0, 0); 233 234 /* 235 * Inline function to copy a 16-bit aligned 32-bit quantity. 236 */ 237 static __inline void 238 fxp_lwcopy(volatile u_int32_t *src, volatile u_int32_t *dst) 239 { 240 #ifdef __i386__ 241 *dst = *src; 242 #else 243 volatile u_int16_t *a = (volatile u_int16_t *)src; 244 volatile u_int16_t *b = (volatile u_int16_t *)dst; 245 246 b[0] = a[0]; 247 b[1] = a[1]; 248 #endif 249 } 250 251 /* 252 * Wait for the previous command to be accepted (but not necessarily 253 * completed). 254 */ 255 static __inline void 256 fxp_scb_wait(struct fxp_softc *sc) 257 { 258 int i = 10000; 259 260 while (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) && --i) 261 DELAY(2); 262 if (i == 0) 263 device_printf(sc->dev, "SCB timeout: 0x%x, 0x%x, 0x%x 0x%x\n", 264 CSR_READ_1(sc, FXP_CSR_SCB_COMMAND), 265 CSR_READ_1(sc, FXP_CSR_SCB_STATACK), 266 CSR_READ_1(sc, FXP_CSR_SCB_RUSCUS), 267 CSR_READ_2(sc, FXP_CSR_FLOWCONTROL)); 268 } 269 270 static __inline void 271 fxp_scb_cmd(struct fxp_softc *sc, int cmd) 272 { 273 274 if (cmd == FXP_SCB_COMMAND_CU_RESUME && sc->cu_resume_bug) { 275 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_CB_COMMAND_NOP); 276 fxp_scb_wait(sc); 277 } 278 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, cmd); 279 } 280 281 static __inline void 282 fxp_dma_wait(volatile u_int16_t *status, struct fxp_softc *sc) 283 { 284 int i = 10000; 285 286 while (!(*status & FXP_CB_STATUS_C) && --i) 287 DELAY(2); 288 if (i == 0) 289 device_printf(sc->dev, "DMA timeout\n"); 290 } 291 292 /* 293 * Return identification string if this is device is ours. 294 */ 295 static int 296 fxp_probe(device_t dev) 297 { 298 u_int16_t devid; 299 struct fxp_ident *ident; 300 301 if (pci_get_vendor(dev) == FXP_VENDORID_INTEL) { 302 devid = pci_get_device(dev); 303 for (ident = fxp_ident_table; ident->name != NULL; ident++) { 304 if (ident->devid == devid) { 305 device_set_desc(dev, ident->name); 306 return (0); 307 } 308 } 309 } 310 return (ENXIO); 311 } 312 313 static int 314 fxp_attach(device_t dev) 315 { 316 int error = 0; 317 struct fxp_softc *sc = device_get_softc(dev); 318 struct ifnet *ifp; 319 u_int32_t val; 320 u_int16_t data; 321 int i, rid, m1, m2, prefer_iomap; 322 int s; 323 324 bzero(sc, sizeof(*sc)); 325 sc->dev = dev; 326 callout_handle_init(&sc->stat_ch); 327 mtx_init(&sc->sc_mtx, device_get_nameunit(dev), MTX_DEF | MTX_RECURSE); 328 329 s = splimp(); 330 331 /* 332 * Enable bus mastering. Enable memory space too, in case 333 * BIOS/Prom forgot about it. 334 */ 335 val = pci_read_config(dev, PCIR_COMMAND, 2); 336 val |= (PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN); 337 pci_write_config(dev, PCIR_COMMAND, val, 2); 338 val = pci_read_config(dev, PCIR_COMMAND, 2); 339 340 #if __FreeBSD_version >= 500000 341 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 342 u_int32_t iobase, membase, irq; 343 344 /* Save important PCI config data. */ 345 iobase = pci_read_config(dev, FXP_PCI_IOBA, 4); 346 membase = pci_read_config(dev, FXP_PCI_MMBA, 4); 347 irq = pci_read_config(dev, PCIR_INTLINE, 4); 348 349 /* Reset the power state. */ 350 device_printf(dev, "chip is in D%d power mode " 351 "-- setting to D0\n", pci_get_powerstate(dev)); 352 353 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 354 355 /* Restore PCI config data. */ 356 pci_write_config(dev, FXP_PCI_IOBA, iobase, 4); 357 pci_write_config(dev, FXP_PCI_MMBA, membase, 4); 358 pci_write_config(dev, PCIR_INTLINE, irq, 4); 359 } 360 #endif 361 362 /* 363 * Figure out which we should try first - memory mapping or i/o mapping? 364 * We default to memory mapping. Then we accept an override from the 365 * command line. Then we check to see which one is enabled. 366 */ 367 m1 = PCIM_CMD_MEMEN; 368 m2 = PCIM_CMD_PORTEN; 369 prefer_iomap = 0; 370 if (resource_int_value(device_get_name(dev), device_get_unit(dev), 371 "prefer_iomap", &prefer_iomap) == 0 && prefer_iomap != 0) { 372 m1 = PCIM_CMD_PORTEN; 373 m2 = PCIM_CMD_MEMEN; 374 } 375 376 if (val & m1) { 377 sc->rtp = 378 (m1 == PCIM_CMD_MEMEN)? SYS_RES_MEMORY : SYS_RES_IOPORT; 379 sc->rgd = (m1 == PCIM_CMD_MEMEN)? FXP_PCI_MMBA : FXP_PCI_IOBA; 380 sc->mem = bus_alloc_resource(dev, sc->rtp, &sc->rgd, 381 0, ~0, 1, RF_ACTIVE); 382 } 383 if (sc->mem == NULL && (val & m2)) { 384 sc->rtp = 385 (m2 == PCIM_CMD_MEMEN)? SYS_RES_MEMORY : SYS_RES_IOPORT; 386 sc->rgd = (m2 == PCIM_CMD_MEMEN)? FXP_PCI_MMBA : FXP_PCI_IOBA; 387 sc->mem = bus_alloc_resource(dev, sc->rtp, &sc->rgd, 388 0, ~0, 1, RF_ACTIVE); 389 } 390 391 if (!sc->mem) { 392 device_printf(dev, "could not map device registers\n"); 393 error = ENXIO; 394 goto fail; 395 } 396 if (bootverbose) { 397 device_printf(dev, "using %s space register mapping\n", 398 sc->rtp == SYS_RES_MEMORY? "memory" : "I/O"); 399 } 400 401 sc->sc_st = rman_get_bustag(sc->mem); 402 sc->sc_sh = rman_get_bushandle(sc->mem); 403 404 /* 405 * Allocate our interrupt. 406 */ 407 rid = 0; 408 sc->irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 409 RF_SHAREABLE | RF_ACTIVE); 410 if (sc->irq == NULL) { 411 device_printf(dev, "could not map interrupt\n"); 412 error = ENXIO; 413 goto fail; 414 } 415 416 error = bus_setup_intr(dev, sc->irq, INTR_TYPE_NET, 417 fxp_intr, sc, &sc->ih); 418 if (error) { 419 device_printf(dev, "could not setup irq\n"); 420 goto fail; 421 } 422 423 /* 424 * Reset to a stable state. 425 */ 426 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET); 427 DELAY(10); 428 429 sc->cbl_base = malloc(sizeof(struct fxp_cb_tx) * FXP_NTXCB, 430 M_DEVBUF, M_NOWAIT | M_ZERO); 431 if (sc->cbl_base == NULL) 432 goto failmem; 433 434 sc->fxp_stats = malloc(sizeof(struct fxp_stats), M_DEVBUF, 435 M_NOWAIT | M_ZERO); 436 if (sc->fxp_stats == NULL) 437 goto failmem; 438 439 sc->mcsp = malloc(sizeof(struct fxp_cb_mcs), M_DEVBUF, M_NOWAIT); 440 if (sc->mcsp == NULL) 441 goto failmem; 442 443 /* 444 * Pre-allocate our receive buffers. 445 */ 446 for (i = 0; i < FXP_NRFABUFS; i++) { 447 if (fxp_add_rfabuf(sc, NULL) != 0) { 448 goto failmem; 449 } 450 } 451 452 /* 453 * Find out how large of an SEEPROM we have. 454 */ 455 fxp_autosize_eeprom(sc); 456 457 /* 458 * Determine whether we must use the 503 serial interface. 459 */ 460 fxp_read_eeprom(sc, &data, 6, 1); 461 if ((data & FXP_PHY_DEVICE_MASK) != 0 && 462 (data & FXP_PHY_SERIAL_ONLY)) 463 sc->flags |= FXP_FLAG_SERIAL_MEDIA; 464 465 /* 466 * Find out the basic controller type; we currently only 467 * differentiate between a 82557 and greater. 468 */ 469 fxp_read_eeprom(sc, &data, 5, 1); 470 if ((data >> 8) == 1) 471 sc->chip = FXP_CHIP_82557; 472 473 /* 474 * Enable workarounds for certain chip revision deficiencies. 475 */ 476 i = pci_get_device(dev); 477 if (i == 0x2449 || (i > 0x1030 && i < 0x1039)) 478 sc->flags |= FXP_FLAG_CU_RESUME_BUG; 479 480 /* 481 * If we are not a 82557 chip, we can enable extended features. 482 */ 483 if (sc->chip != FXP_CHIP_82557) { 484 /* 485 * If there is a valid cacheline size (8 or 16 dwords), 486 * then turn on MWI. 487 */ 488 if (pci_read_config(dev, PCIR_CACHELNSZ, 1) != 0) 489 sc->flags |= FXP_FLAG_MWI_ENABLE; 490 491 /* turn on the extended TxCB feature */ 492 sc->flags |= FXP_FLAG_EXT_TXCB; 493 #if NVLAN > 0 494 /* enable reception of long frames for VLAN */ 495 sc->flags |= FXP_FLAG_LONG_PKT_EN; 496 #endif 497 } 498 499 /* 500 * Read MAC address. 501 */ 502 fxp_read_eeprom(sc, (u_int16_t *)sc->arpcom.ac_enaddr, 0, 3); 503 device_printf(dev, "Ethernet address %6D%s\n", 504 sc->arpcom.ac_enaddr, ":", 505 sc->flags & FXP_FLAG_SERIAL_MEDIA ? ", 10Mbps" : ""); 506 if (bootverbose) { 507 device_printf(dev, "PCI IDs: %04x %04x %04x %04x %04x\n", 508 pci_get_vendor(dev), pci_get_device(dev), 509 pci_get_subvendor(dev), pci_get_subdevice(dev), 510 pci_get_revid(dev)); 511 device_printf(dev, "Chip Type: %d\n", sc->chip); 512 } 513 514 /* 515 * If this is only a 10Mbps device, then there is no MII, and 516 * the PHY will use a serial interface instead. 517 * 518 * The Seeq 80c24 AutoDUPLEX(tm) Ethernet Interface Adapter 519 * doesn't have a programming interface of any sort. The 520 * media is sensed automatically based on how the link partner 521 * is configured. This is, in essence, manual configuration. 522 */ 523 if (sc->flags & FXP_FLAG_SERIAL_MEDIA) { 524 ifmedia_init(&sc->sc_media, 0, fxp_serial_ifmedia_upd, 525 fxp_serial_ifmedia_sts); 526 ifmedia_add(&sc->sc_media, IFM_ETHER|IFM_MANUAL, 0, NULL); 527 ifmedia_set(&sc->sc_media, IFM_ETHER|IFM_MANUAL); 528 } else { 529 if (mii_phy_probe(dev, &sc->miibus, fxp_ifmedia_upd, 530 fxp_ifmedia_sts)) { 531 device_printf(dev, "MII without any PHY!\n"); 532 error = ENXIO; 533 goto fail; 534 } 535 } 536 537 ifp = &sc->arpcom.ac_if; 538 ifp->if_unit = device_get_unit(dev); 539 ifp->if_name = "fxp"; 540 ifp->if_output = ether_output; 541 ifp->if_baudrate = 100000000; 542 ifp->if_init = fxp_init; 543 ifp->if_softc = sc; 544 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 545 ifp->if_ioctl = fxp_ioctl; 546 ifp->if_start = fxp_start; 547 ifp->if_watchdog = fxp_watchdog; 548 549 /* 550 * Attach the interface. 551 */ 552 ether_ifattach(ifp, ETHER_BPF_SUPPORTED); 553 554 #if NVLAN > 0 555 /* 556 * Tell the upper layer(s) we support long frames. 557 */ 558 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 559 #endif 560 561 /* 562 * Let the system queue as many packets as we have available 563 * TX descriptors. 564 */ 565 ifp->if_snd.ifq_maxlen = FXP_NTXCB - 1; 566 567 splx(s); 568 return (0); 569 570 failmem: 571 device_printf(dev, "Failed to malloc memory\n"); 572 error = ENOMEM; 573 fail: 574 splx(s); 575 fxp_release(sc); 576 return (error); 577 } 578 579 /* 580 * release all resources 581 */ 582 static void 583 fxp_release(struct fxp_softc *sc) 584 { 585 586 bus_generic_detach(sc->dev); 587 if (sc->miibus) 588 device_delete_child(sc->dev, sc->miibus); 589 590 if (sc->cbl_base) 591 free(sc->cbl_base, M_DEVBUF); 592 if (sc->fxp_stats) 593 free(sc->fxp_stats, M_DEVBUF); 594 if (sc->mcsp) 595 free(sc->mcsp, M_DEVBUF); 596 if (sc->rfa_headm) 597 m_freem(sc->rfa_headm); 598 599 if (sc->ih) 600 bus_teardown_intr(sc->dev, sc->irq, sc->ih); 601 if (sc->irq) 602 bus_release_resource(sc->dev, SYS_RES_IRQ, 0, sc->irq); 603 if (sc->mem) 604 bus_release_resource(sc->dev, sc->rtp, sc->rgd, sc->mem); 605 mtx_destroy(&sc->sc_mtx); 606 } 607 608 /* 609 * Detach interface. 610 */ 611 static int 612 fxp_detach(device_t dev) 613 { 614 struct fxp_softc *sc = device_get_softc(dev); 615 int s; 616 617 /* disable interrupts */ 618 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE); 619 620 s = splimp(); 621 622 /* 623 * Stop DMA and drop transmit queue. 624 */ 625 fxp_stop(sc); 626 627 /* 628 * Close down routes etc. 629 */ 630 ether_ifdetach(&sc->arpcom.ac_if, ETHER_BPF_SUPPORTED); 631 632 /* 633 * Free all media structures. 634 */ 635 ifmedia_removeall(&sc->sc_media); 636 637 splx(s); 638 639 /* Release our allocated resources. */ 640 fxp_release(sc); 641 642 return (0); 643 } 644 645 /* 646 * Device shutdown routine. Called at system shutdown after sync. The 647 * main purpose of this routine is to shut off receiver DMA so that 648 * kernel memory doesn't get clobbered during warmboot. 649 */ 650 static int 651 fxp_shutdown(device_t dev) 652 { 653 /* 654 * Make sure that DMA is disabled prior to reboot. Not doing 655 * do could allow DMA to corrupt kernel memory during the 656 * reboot before the driver initializes. 657 */ 658 fxp_stop((struct fxp_softc *) device_get_softc(dev)); 659 return (0); 660 } 661 662 /* 663 * Device suspend routine. Stop the interface and save some PCI 664 * settings in case the BIOS doesn't restore them properly on 665 * resume. 666 */ 667 static int 668 fxp_suspend(device_t dev) 669 { 670 struct fxp_softc *sc = device_get_softc(dev); 671 int i, s; 672 673 s = splimp(); 674 675 fxp_stop(sc); 676 677 for (i=0; i<5; i++) 678 sc->saved_maps[i] = pci_read_config(dev, PCIR_MAPS + i*4, 4); 679 sc->saved_biosaddr = pci_read_config(dev, PCIR_BIOS, 4); 680 sc->saved_intline = pci_read_config(dev, PCIR_INTLINE, 1); 681 sc->saved_cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1); 682 sc->saved_lattimer = pci_read_config(dev, PCIR_LATTIMER, 1); 683 684 sc->suspended = 1; 685 686 splx(s); 687 return (0); 688 } 689 690 /* 691 * Device resume routine. Restore some PCI settings in case the BIOS 692 * doesn't, re-enable busmastering, and restart the interface if 693 * appropriate. 694 */ 695 static int 696 fxp_resume(device_t dev) 697 { 698 struct fxp_softc *sc = device_get_softc(dev); 699 struct ifnet *ifp = &sc->sc_if; 700 u_int16_t pci_command; 701 int i, s; 702 703 s = splimp(); 704 705 /* better way to do this? */ 706 for (i=0; i<5; i++) 707 pci_write_config(dev, PCIR_MAPS + i*4, sc->saved_maps[i], 4); 708 pci_write_config(dev, PCIR_BIOS, sc->saved_biosaddr, 4); 709 pci_write_config(dev, PCIR_INTLINE, sc->saved_intline, 1); 710 pci_write_config(dev, PCIR_CACHELNSZ, sc->saved_cachelnsz, 1); 711 pci_write_config(dev, PCIR_LATTIMER, sc->saved_lattimer, 1); 712 713 /* reenable busmastering */ 714 pci_command = pci_read_config(dev, PCIR_COMMAND, 2); 715 pci_command |= (PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN); 716 pci_write_config(dev, PCIR_COMMAND, pci_command, 2); 717 718 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET); 719 DELAY(10); 720 721 /* reinitialize interface if necessary */ 722 if (ifp->if_flags & IFF_UP) 723 fxp_init(sc); 724 725 sc->suspended = 0; 726 727 splx(s); 728 return (0); 729 } 730 731 /* 732 * Read from the serial EEPROM. Basically, you manually shift in 733 * the read opcode (one bit at a time) and then shift in the address, 734 * and then you shift out the data (all of this one bit at a time). 735 * The word size is 16 bits, so you have to provide the address for 736 * every 16 bits of data. 737 */ 738 static u_int16_t 739 fxp_eeprom_getword(struct fxp_softc *sc, int offset, int autosize) 740 { 741 u_int16_t reg, data; 742 int x; 743 744 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 745 /* 746 * Shift in read opcode. 747 */ 748 for (x = 1 << 2; x; x >>= 1) { 749 if (FXP_EEPROM_OPC_READ & x) 750 reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI; 751 else 752 reg = FXP_EEPROM_EECS; 753 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 754 DELAY(1); 755 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK); 756 DELAY(1); 757 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 758 DELAY(1); 759 } 760 /* 761 * Shift in address. 762 */ 763 data = 0; 764 for (x = 1 << (sc->eeprom_size - 1); x; x >>= 1) { 765 if (offset & x) 766 reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI; 767 else 768 reg = FXP_EEPROM_EECS; 769 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 770 DELAY(1); 771 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK); 772 DELAY(1); 773 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 774 DELAY(1); 775 reg = CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO; 776 data++; 777 if (autosize && reg == 0) { 778 sc->eeprom_size = data; 779 break; 780 } 781 } 782 /* 783 * Shift out data. 784 */ 785 data = 0; 786 reg = FXP_EEPROM_EECS; 787 for (x = 1 << 15; x; x >>= 1) { 788 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK); 789 DELAY(1); 790 if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO) 791 data |= x; 792 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 793 DELAY(1); 794 } 795 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 796 DELAY(1); 797 798 return (data); 799 } 800 801 /* 802 * From NetBSD: 803 * 804 * Figure out EEPROM size. 805 * 806 * 559's can have either 64-word or 256-word EEPROMs, the 558 807 * datasheet only talks about 64-word EEPROMs, and the 557 datasheet 808 * talks about the existance of 16 to 256 word EEPROMs. 809 * 810 * The only known sizes are 64 and 256, where the 256 version is used 811 * by CardBus cards to store CIS information. 812 * 813 * The address is shifted in msb-to-lsb, and after the last 814 * address-bit the EEPROM is supposed to output a `dummy zero' bit, 815 * after which follows the actual data. We try to detect this zero, by 816 * probing the data-out bit in the EEPROM control register just after 817 * having shifted in a bit. If the bit is zero, we assume we've 818 * shifted enough address bits. The data-out should be tri-state, 819 * before this, which should translate to a logical one. 820 * 821 * Other ways to do this would be to try to read a register with known 822 * contents with a varying number of address bits, but no such 823 * register seem to be available. The high bits of register 10 are 01 824 * on the 558 and 559, but apparently not on the 557. 825 * 826 * The Linux driver computes a checksum on the EEPROM data, but the 827 * value of this checksum is not very well documented. 828 */ 829 static void 830 fxp_autosize_eeprom(struct fxp_softc *sc) 831 { 832 833 /* guess maximum size of 256 words */ 834 sc->eeprom_size = 8; 835 836 /* autosize */ 837 (void) fxp_eeprom_getword(sc, 0, 1); 838 } 839 840 static void 841 fxp_read_eeprom(struct fxp_softc *sc, u_short *data, int offset, int words) 842 { 843 int i; 844 845 for (i = 0; i < words; i++) 846 data[i] = fxp_eeprom_getword(sc, offset + i, 0); 847 } 848 849 /* 850 * Start packet transmission on the interface. 851 */ 852 static void 853 fxp_start(struct ifnet *ifp) 854 { 855 struct fxp_softc *sc = ifp->if_softc; 856 struct fxp_cb_tx *txp; 857 858 /* 859 * See if we need to suspend xmit until the multicast filter 860 * has been reprogrammed (which can only be done at the head 861 * of the command chain). 862 */ 863 if (sc->need_mcsetup) { 864 return; 865 } 866 867 txp = NULL; 868 869 /* 870 * We're finished if there is nothing more to add to the list or if 871 * we're all filled up with buffers to transmit. 872 * NOTE: One TxCB is reserved to guarantee that fxp_mc_setup() can add 873 * a NOP command when needed. 874 */ 875 while (ifp->if_snd.ifq_head != NULL && sc->tx_queued < FXP_NTXCB - 1) { 876 struct mbuf *m, *mb_head; 877 int segment; 878 879 /* 880 * Grab a packet to transmit. 881 */ 882 IF_DEQUEUE(&ifp->if_snd, mb_head); 883 884 /* 885 * Get pointer to next available tx desc. 886 */ 887 txp = sc->cbl_last->next; 888 889 /* 890 * Go through each of the mbufs in the chain and initialize 891 * the transmit buffer descriptors with the physical address 892 * and size of the mbuf. 893 */ 894 tbdinit: 895 for (m = mb_head, segment = 0; m != NULL; m = m->m_next) { 896 if (m->m_len != 0) { 897 if (segment == FXP_NTXSEG) 898 break; 899 txp->tbd[segment].tb_addr = 900 vtophys(mtod(m, vm_offset_t)); 901 txp->tbd[segment].tb_size = m->m_len; 902 segment++; 903 } 904 } 905 if (m != NULL) { 906 struct mbuf *mn; 907 908 /* 909 * We ran out of segments. We have to recopy this 910 * mbuf chain first. Bail out if we can't get the 911 * new buffers. 912 */ 913 MGETHDR(mn, M_DONTWAIT, MT_DATA); 914 if (mn == NULL) { 915 m_freem(mb_head); 916 break; 917 } 918 if (mb_head->m_pkthdr.len > MHLEN) { 919 MCLGET(mn, M_DONTWAIT); 920 if ((mn->m_flags & M_EXT) == 0) { 921 m_freem(mn); 922 m_freem(mb_head); 923 break; 924 } 925 } 926 m_copydata(mb_head, 0, mb_head->m_pkthdr.len, 927 mtod(mn, caddr_t)); 928 mn->m_pkthdr.len = mn->m_len = mb_head->m_pkthdr.len; 929 m_freem(mb_head); 930 mb_head = mn; 931 goto tbdinit; 932 } 933 934 txp->tbd_number = segment; 935 txp->mb_head = mb_head; 936 txp->cb_status = 0; 937 if (sc->tx_queued != FXP_CXINT_THRESH - 1) { 938 txp->cb_command = 939 FXP_CB_COMMAND_XMIT | FXP_CB_COMMAND_SF | 940 FXP_CB_COMMAND_S; 941 } else { 942 txp->cb_command = 943 FXP_CB_COMMAND_XMIT | FXP_CB_COMMAND_SF | 944 FXP_CB_COMMAND_S | FXP_CB_COMMAND_I; 945 /* 946 * Set a 5 second timer just in case we don't hear 947 * from the card again. 948 */ 949 ifp->if_timer = 5; 950 } 951 txp->tx_threshold = tx_threshold; 952 953 /* 954 * Advance the end of list forward. 955 */ 956 957 #ifdef __alpha__ 958 /* 959 * On platforms which can't access memory in 16-bit 960 * granularities, we must prevent the card from DMA'ing 961 * up the status while we update the command field. 962 * This could cause us to overwrite the completion status. 963 */ 964 atomic_clear_short(&sc->cbl_last->cb_command, 965 FXP_CB_COMMAND_S); 966 #else 967 sc->cbl_last->cb_command &= ~FXP_CB_COMMAND_S; 968 #endif /*__alpha__*/ 969 sc->cbl_last = txp; 970 971 /* 972 * Advance the beginning of the list forward if there are 973 * no other packets queued (when nothing is queued, cbl_first 974 * sits on the last TxCB that was sent out). 975 */ 976 if (sc->tx_queued == 0) 977 sc->cbl_first = txp; 978 979 sc->tx_queued++; 980 981 /* 982 * Pass packet to bpf if there is a listener. 983 */ 984 if (ifp->if_bpf) 985 bpf_mtap(ifp, mb_head); 986 } 987 988 /* 989 * We're finished. If we added to the list, issue a RESUME to get DMA 990 * going again if suspended. 991 */ 992 if (txp != NULL) { 993 fxp_scb_wait(sc); 994 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_RESUME); 995 } 996 } 997 998 /* 999 * Process interface interrupts. 1000 */ 1001 static void 1002 fxp_intr(void *xsc) 1003 { 1004 struct fxp_softc *sc = xsc; 1005 struct ifnet *ifp = &sc->sc_if; 1006 u_int8_t statack; 1007 1008 if (sc->suspended) { 1009 return; 1010 } 1011 1012 while ((statack = CSR_READ_1(sc, FXP_CSR_SCB_STATACK)) != 0) { 1013 /* 1014 * First ACK all the interrupts in this pass. 1015 */ 1016 CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, statack); 1017 1018 /* 1019 * Free any finished transmit mbuf chains. 1020 * 1021 * Handle the CNA event likt a CXTNO event. It used to 1022 * be that this event (control unit not ready) was not 1023 * encountered, but it is now with the SMPng modifications. 1024 * The exact sequence of events that occur when the interface 1025 * is brought up are different now, and if this event 1026 * goes unhandled, the configuration/rxfilter setup sequence 1027 * can stall for several seconds. The result is that no 1028 * packets go out onto the wire for about 5 to 10 seconds 1029 * after the interface is ifconfig'ed for the first time. 1030 */ 1031 if (statack & (FXP_SCB_STATACK_CXTNO | FXP_SCB_STATACK_CNA)) { 1032 struct fxp_cb_tx *txp; 1033 1034 for (txp = sc->cbl_first; sc->tx_queued && 1035 (txp->cb_status & FXP_CB_STATUS_C) != 0; 1036 txp = txp->next) { 1037 if (txp->mb_head != NULL) { 1038 m_freem(txp->mb_head); 1039 txp->mb_head = NULL; 1040 } 1041 sc->tx_queued--; 1042 } 1043 sc->cbl_first = txp; 1044 ifp->if_timer = 0; 1045 if (sc->tx_queued == 0) { 1046 if (sc->need_mcsetup) 1047 fxp_mc_setup(sc); 1048 } 1049 /* 1050 * Try to start more packets transmitting. 1051 */ 1052 if (ifp->if_snd.ifq_head != NULL) 1053 fxp_start(ifp); 1054 } 1055 /* 1056 * Process receiver interrupts. If a no-resource (RNR) 1057 * condition exists, get whatever packets we can and 1058 * re-start the receiver. 1059 */ 1060 if (statack & (FXP_SCB_STATACK_FR | FXP_SCB_STATACK_RNR)) { 1061 struct mbuf *m; 1062 struct fxp_rfa *rfa; 1063 rcvloop: 1064 m = sc->rfa_headm; 1065 rfa = (struct fxp_rfa *)(m->m_ext.ext_buf + 1066 RFA_ALIGNMENT_FUDGE); 1067 1068 if (rfa->rfa_status & FXP_RFA_STATUS_C) { 1069 /* 1070 * Remove first packet from the chain. 1071 */ 1072 sc->rfa_headm = m->m_next; 1073 m->m_next = NULL; 1074 1075 /* 1076 * Add a new buffer to the receive chain. 1077 * If this fails, the old buffer is recycled 1078 * instead. 1079 */ 1080 if (fxp_add_rfabuf(sc, m) == 0) { 1081 struct ether_header *eh; 1082 int total_len; 1083 1084 total_len = rfa->actual_size & 1085 (MCLBYTES - 1); 1086 if (total_len < 1087 sizeof(struct ether_header)) { 1088 m_freem(m); 1089 goto rcvloop; 1090 } 1091 #if NVLAN > 0 1092 /* 1093 * Drop the packet if it has CRC 1094 * errors. This test is only needed 1095 * when doing 802.1q VLAN on the 82557 1096 * chip. 1097 */ 1098 if (rfa->rfa_status & 1099 FXP_RFA_STATUS_CRC) { 1100 m_freem(m); 1101 goto rcvloop; 1102 } 1103 #endif 1104 m->m_pkthdr.rcvif = ifp; 1105 m->m_pkthdr.len = m->m_len = total_len; 1106 eh = mtod(m, struct ether_header *); 1107 m->m_data += 1108 sizeof(struct ether_header); 1109 m->m_len -= 1110 sizeof(struct ether_header); 1111 m->m_pkthdr.len = m->m_len; 1112 ether_input(ifp, eh, m); 1113 } 1114 goto rcvloop; 1115 } 1116 if (statack & FXP_SCB_STATACK_RNR) { 1117 fxp_scb_wait(sc); 1118 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 1119 vtophys(sc->rfa_headm->m_ext.ext_buf) + 1120 RFA_ALIGNMENT_FUDGE); 1121 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_START); 1122 } 1123 } 1124 } 1125 } 1126 1127 /* 1128 * Update packet in/out/collision statistics. The i82557 doesn't 1129 * allow you to access these counters without doing a fairly 1130 * expensive DMA to get _all_ of the statistics it maintains, so 1131 * we do this operation here only once per second. The statistics 1132 * counters in the kernel are updated from the previous dump-stats 1133 * DMA and then a new dump-stats DMA is started. The on-chip 1134 * counters are zeroed when the DMA completes. If we can't start 1135 * the DMA immediately, we don't wait - we just prepare to read 1136 * them again next time. 1137 */ 1138 static void 1139 fxp_tick(void *xsc) 1140 { 1141 struct fxp_softc *sc = xsc; 1142 struct ifnet *ifp = &sc->sc_if; 1143 struct fxp_stats *sp = sc->fxp_stats; 1144 struct fxp_cb_tx *txp; 1145 int s; 1146 1147 ifp->if_opackets += sp->tx_good; 1148 ifp->if_collisions += sp->tx_total_collisions; 1149 if (sp->rx_good) { 1150 ifp->if_ipackets += sp->rx_good; 1151 sc->rx_idle_secs = 0; 1152 } else { 1153 /* 1154 * Receiver's been idle for another second. 1155 */ 1156 sc->rx_idle_secs++; 1157 } 1158 ifp->if_ierrors += 1159 sp->rx_crc_errors + 1160 sp->rx_alignment_errors + 1161 sp->rx_rnr_errors + 1162 sp->rx_overrun_errors; 1163 /* 1164 * If any transmit underruns occured, bump up the transmit 1165 * threshold by another 512 bytes (64 * 8). 1166 */ 1167 if (sp->tx_underruns) { 1168 ifp->if_oerrors += sp->tx_underruns; 1169 if (tx_threshold < 192) 1170 tx_threshold += 64; 1171 } 1172 s = splimp(); 1173 /* 1174 * Release any xmit buffers that have completed DMA. This isn't 1175 * strictly necessary to do here, but it's advantagous for mbufs 1176 * with external storage to be released in a timely manner rather 1177 * than being defered for a potentially long time. This limits 1178 * the delay to a maximum of one second. 1179 */ 1180 for (txp = sc->cbl_first; sc->tx_queued && 1181 (txp->cb_status & FXP_CB_STATUS_C) != 0; 1182 txp = txp->next) { 1183 if (txp->mb_head != NULL) { 1184 m_freem(txp->mb_head); 1185 txp->mb_head = NULL; 1186 } 1187 sc->tx_queued--; 1188 } 1189 sc->cbl_first = txp; 1190 /* 1191 * If we haven't received any packets in FXP_MAC_RX_IDLE seconds, 1192 * then assume the receiver has locked up and attempt to clear 1193 * the condition by reprogramming the multicast filter. This is 1194 * a work-around for a bug in the 82557 where the receiver locks 1195 * up if it gets certain types of garbage in the syncronization 1196 * bits prior to the packet header. This bug is supposed to only 1197 * occur in 10Mbps mode, but has been seen to occur in 100Mbps 1198 * mode as well (perhaps due to a 10/100 speed transition). 1199 */ 1200 if (sc->rx_idle_secs > FXP_MAX_RX_IDLE) { 1201 sc->rx_idle_secs = 0; 1202 fxp_mc_setup(sc); 1203 } 1204 /* 1205 * If there is no pending command, start another stats 1206 * dump. Otherwise punt for now. 1207 */ 1208 if (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) == 0) { 1209 /* 1210 * Start another stats dump. 1211 */ 1212 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_DUMPRESET); 1213 } else { 1214 /* 1215 * A previous command is still waiting to be accepted. 1216 * Just zero our copy of the stats and wait for the 1217 * next timer event to update them. 1218 */ 1219 sp->tx_good = 0; 1220 sp->tx_underruns = 0; 1221 sp->tx_total_collisions = 0; 1222 1223 sp->rx_good = 0; 1224 sp->rx_crc_errors = 0; 1225 sp->rx_alignment_errors = 0; 1226 sp->rx_rnr_errors = 0; 1227 sp->rx_overrun_errors = 0; 1228 } 1229 1230 if (sc->miibus != NULL) 1231 mii_tick(device_get_softc(sc->miibus)); 1232 1233 /* 1234 * Schedule another timeout one second from now. 1235 */ 1236 sc->stat_ch = timeout(fxp_tick, sc, hz); 1237 } 1238 1239 /* 1240 * Stop the interface. Cancels the statistics updater and resets 1241 * the interface. 1242 */ 1243 static void 1244 fxp_stop(struct fxp_softc *sc) 1245 { 1246 struct ifnet *ifp = &sc->sc_if; 1247 struct fxp_cb_tx *txp; 1248 int i; 1249 1250 1251 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1252 ifp->if_timer = 0; 1253 1254 /* 1255 * Cancel stats updater. 1256 */ 1257 untimeout(fxp_tick, sc, sc->stat_ch); 1258 1259 /* 1260 * Issue software reset 1261 */ 1262 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET); 1263 DELAY(10); 1264 1265 /* 1266 * Release any xmit buffers. 1267 */ 1268 txp = sc->cbl_base; 1269 if (txp != NULL) { 1270 for (i = 0; i < FXP_NTXCB; i++) { 1271 if (txp[i].mb_head != NULL) { 1272 m_freem(txp[i].mb_head); 1273 txp[i].mb_head = NULL; 1274 } 1275 } 1276 } 1277 sc->tx_queued = 0; 1278 1279 /* 1280 * Free all the receive buffers then reallocate/reinitialize 1281 */ 1282 if (sc->rfa_headm != NULL) 1283 m_freem(sc->rfa_headm); 1284 sc->rfa_headm = NULL; 1285 sc->rfa_tailm = NULL; 1286 for (i = 0; i < FXP_NRFABUFS; i++) { 1287 if (fxp_add_rfabuf(sc, NULL) != 0) { 1288 /* 1289 * This "can't happen" - we're at splimp() 1290 * and we just freed all the buffers we need 1291 * above. 1292 */ 1293 panic("fxp_stop: no buffers!"); 1294 } 1295 } 1296 } 1297 1298 /* 1299 * Watchdog/transmission transmit timeout handler. Called when a 1300 * transmission is started on the interface, but no interrupt is 1301 * received before the timeout. This usually indicates that the 1302 * card has wedged for some reason. 1303 */ 1304 static void 1305 fxp_watchdog(struct ifnet *ifp) 1306 { 1307 struct fxp_softc *sc = ifp->if_softc; 1308 1309 device_printf(sc->dev, "device timeout\n"); 1310 ifp->if_oerrors++; 1311 1312 fxp_init(sc); 1313 } 1314 1315 static void 1316 fxp_init(void *xsc) 1317 { 1318 struct fxp_softc *sc = xsc; 1319 struct ifnet *ifp = &sc->sc_if; 1320 struct fxp_cb_config *cbp; 1321 struct fxp_cb_ias *cb_ias; 1322 struct fxp_cb_tx *txp; 1323 int i, prm, s; 1324 1325 s = splimp(); 1326 /* 1327 * Cancel any pending I/O 1328 */ 1329 fxp_stop(sc); 1330 1331 prm = (ifp->if_flags & IFF_PROMISC) ? 1 : 0; 1332 1333 /* 1334 * Initialize base of CBL and RFA memory. Loading with zero 1335 * sets it up for regular linear addressing. 1336 */ 1337 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 0); 1338 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_BASE); 1339 1340 fxp_scb_wait(sc); 1341 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_BASE); 1342 1343 /* 1344 * Initialize base of dump-stats buffer. 1345 */ 1346 fxp_scb_wait(sc); 1347 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, vtophys(sc->fxp_stats)); 1348 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_DUMP_ADR); 1349 1350 /* 1351 * We temporarily use memory that contains the TxCB list to 1352 * construct the config CB. The TxCB list memory is rebuilt 1353 * later. 1354 */ 1355 cbp = (struct fxp_cb_config *) sc->cbl_base; 1356 1357 /* 1358 * This bcopy is kind of disgusting, but there are a bunch of must be 1359 * zero and must be one bits in this structure and this is the easiest 1360 * way to initialize them all to proper values. 1361 */ 1362 bcopy(fxp_cb_config_template, 1363 (void *)(uintptr_t)(volatile void *)&cbp->cb_status, 1364 sizeof(fxp_cb_config_template)); 1365 1366 cbp->cb_status = 0; 1367 cbp->cb_command = FXP_CB_COMMAND_CONFIG | FXP_CB_COMMAND_EL; 1368 cbp->link_addr = -1; /* (no) next command */ 1369 cbp->byte_count = 22; /* (22) bytes to config */ 1370 cbp->rx_fifo_limit = 8; /* rx fifo threshold (32 bytes) */ 1371 cbp->tx_fifo_limit = 0; /* tx fifo threshold (0 bytes) */ 1372 cbp->adaptive_ifs = 0; /* (no) adaptive interframe spacing */ 1373 cbp->mwi_enable = sc->flags & FXP_FLAG_MWI_ENABLE ? 1 : 0; 1374 cbp->type_enable = 0; /* actually reserved */ 1375 cbp->read_align_en = sc->flags & FXP_FLAG_READ_ALIGN ? 1 : 0; 1376 cbp->end_wr_on_cl = sc->flags & FXP_FLAG_WRITE_ALIGN ? 1 : 0; 1377 cbp->rx_dma_bytecount = 0; /* (no) rx DMA max */ 1378 cbp->tx_dma_bytecount = 0; /* (no) tx DMA max */ 1379 cbp->dma_mbce = 0; /* (disable) dma max counters */ 1380 cbp->late_scb = 0; /* (don't) defer SCB update */ 1381 cbp->direct_dma_dis = 1; /* disable direct rcv dma mode */ 1382 cbp->tno_int_or_tco_en =0; /* (disable) tx not okay interrupt */ 1383 cbp->ci_int = 1; /* interrupt on CU idle */ 1384 cbp->ext_txcb_dis = sc->flags & FXP_FLAG_EXT_TXCB ? 0 : 1; 1385 cbp->ext_stats_dis = 1; /* disable extended counters */ 1386 cbp->keep_overrun_rx = 0; /* don't pass overrun frames to host */ 1387 #if NVLAN > 0 1388 cbp->save_bf = sc->chip == FXP_CHIP_82557 ? 1 : prm; 1389 #else 1390 cbp->save_bf = prm; /* save bad frames */ 1391 #endif 1392 cbp->disc_short_rx = !prm; /* discard short packets */ 1393 cbp->underrun_retry = 1; /* retry mode (once) on DMA underrun */ 1394 cbp->two_frames = 0; /* do not limit FIFO to 2 frames */ 1395 cbp->dyn_tbd = 0; /* (no) dynamic TBD mode */ 1396 cbp->mediatype = sc->flags & FXP_FLAG_SERIAL_MEDIA ? 0 : 1; 1397 cbp->csma_dis = 0; /* (don't) disable link */ 1398 cbp->tcp_udp_cksum = 0; /* (don't) enable checksum */ 1399 cbp->vlan_tco = 0; /* (don't) enable vlan wakeup */ 1400 cbp->link_wake_en = 0; /* (don't) assert PME# on link change */ 1401 cbp->arp_wake_en = 0; /* (don't) assert PME# on arp */ 1402 cbp->mc_wake_en = 0; /* (don't) enable PME# on mcmatch */ 1403 cbp->nsai = 1; /* (don't) disable source addr insert */ 1404 cbp->preamble_length = 2; /* (7 byte) preamble */ 1405 cbp->loopback = 0; /* (don't) loopback */ 1406 cbp->linear_priority = 0; /* (normal CSMA/CD operation) */ 1407 cbp->linear_pri_mode = 0; /* (wait after xmit only) */ 1408 cbp->interfrm_spacing = 6; /* (96 bits of) interframe spacing */ 1409 cbp->promiscuous = prm; /* promiscuous mode */ 1410 cbp->bcast_disable = 0; /* (don't) disable broadcasts */ 1411 cbp->wait_after_win = 0; /* (don't) enable modified backoff alg*/ 1412 cbp->ignore_ul = 0; /* consider U/L bit in IA matching */ 1413 cbp->crc16_en = 0; /* (don't) enable crc-16 algorithm */ 1414 cbp->crscdt = sc->flags & FXP_FLAG_SERIAL_MEDIA ? 1 : 0; 1415 1416 cbp->stripping = !prm; /* truncate rx packet to byte count */ 1417 cbp->padding = 1; /* (do) pad short tx packets */ 1418 cbp->rcv_crc_xfer = 0; /* (don't) xfer CRC to host */ 1419 cbp->long_rx_en = sc->flags & FXP_FLAG_LONG_PKT_EN ? 1 : 0; 1420 cbp->ia_wake_en = 0; /* (don't) wake up on address match */ 1421 cbp->magic_pkt_dis = 0; /* (don't) disable magic packet */ 1422 /* must set wake_en in PMCSR also */ 1423 cbp->force_fdx = 0; /* (don't) force full duplex */ 1424 cbp->fdx_pin_en = 1; /* (enable) FDX# pin */ 1425 cbp->multi_ia = 0; /* (don't) accept multiple IAs */ 1426 cbp->mc_all = sc->flags & FXP_FLAG_ALL_MCAST ? 1 : 0; 1427 1428 if (sc->chip == FXP_CHIP_82557) { 1429 /* 1430 * The 82557 has no hardware flow control, the values 1431 * below are the defaults for the chip. 1432 */ 1433 cbp->fc_delay_lsb = 0; 1434 cbp->fc_delay_msb = 0x40; 1435 cbp->pri_fc_thresh = 3; 1436 cbp->tx_fc_dis = 0; 1437 cbp->rx_fc_restop = 0; 1438 cbp->rx_fc_restart = 0; 1439 cbp->fc_filter = 0; 1440 cbp->pri_fc_loc = 1; 1441 } else { 1442 cbp->fc_delay_lsb = 0x1f; 1443 cbp->fc_delay_msb = 0x01; 1444 cbp->pri_fc_thresh = 3; 1445 cbp->tx_fc_dis = 0; /* enable transmit FC */ 1446 cbp->rx_fc_restop = 1; /* enable FC restop frames */ 1447 cbp->rx_fc_restart = 1; /* enable FC restart frames */ 1448 cbp->fc_filter = !prm; /* drop FC frames to host */ 1449 cbp->pri_fc_loc = 1; /* FC pri location (byte31) */ 1450 } 1451 1452 /* 1453 * Start the config command/DMA. 1454 */ 1455 fxp_scb_wait(sc); 1456 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, vtophys(&cbp->cb_status)); 1457 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 1458 /* ...and wait for it to complete. */ 1459 fxp_dma_wait(&cbp->cb_status, sc); 1460 1461 /* 1462 * Now initialize the station address. Temporarily use the TxCB 1463 * memory area like we did above for the config CB. 1464 */ 1465 cb_ias = (struct fxp_cb_ias *) sc->cbl_base; 1466 cb_ias->cb_status = 0; 1467 cb_ias->cb_command = FXP_CB_COMMAND_IAS | FXP_CB_COMMAND_EL; 1468 cb_ias->link_addr = -1; 1469 bcopy(sc->arpcom.ac_enaddr, 1470 (void *)(uintptr_t)(volatile void *)cb_ias->macaddr, 1471 sizeof(sc->arpcom.ac_enaddr)); 1472 1473 /* 1474 * Start the IAS (Individual Address Setup) command/DMA. 1475 */ 1476 fxp_scb_wait(sc); 1477 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 1478 /* ...and wait for it to complete. */ 1479 fxp_dma_wait(&cb_ias->cb_status, sc); 1480 1481 /* 1482 * Initialize transmit control block (TxCB) list. 1483 */ 1484 1485 txp = sc->cbl_base; 1486 bzero(txp, sizeof(struct fxp_cb_tx) * FXP_NTXCB); 1487 for (i = 0; i < FXP_NTXCB; i++) { 1488 txp[i].cb_status = FXP_CB_STATUS_C | FXP_CB_STATUS_OK; 1489 txp[i].cb_command = FXP_CB_COMMAND_NOP; 1490 txp[i].link_addr = 1491 vtophys(&txp[(i + 1) & FXP_TXCB_MASK].cb_status); 1492 if (sc->flags & FXP_FLAG_EXT_TXCB) 1493 txp[i].tbd_array_addr = vtophys(&txp[i].tbd[2]); 1494 else 1495 txp[i].tbd_array_addr = vtophys(&txp[i].tbd[0]); 1496 txp[i].next = &txp[(i + 1) & FXP_TXCB_MASK]; 1497 } 1498 /* 1499 * Set the suspend flag on the first TxCB and start the control 1500 * unit. It will execute the NOP and then suspend. 1501 */ 1502 txp->cb_command = FXP_CB_COMMAND_NOP | FXP_CB_COMMAND_S; 1503 sc->cbl_first = sc->cbl_last = txp; 1504 sc->tx_queued = 1; 1505 1506 fxp_scb_wait(sc); 1507 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 1508 1509 /* 1510 * Initialize receiver buffer area - RFA. 1511 */ 1512 fxp_scb_wait(sc); 1513 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 1514 vtophys(sc->rfa_headm->m_ext.ext_buf) + RFA_ALIGNMENT_FUDGE); 1515 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_START); 1516 1517 /* 1518 * Set current media. 1519 */ 1520 if (sc->miibus != NULL) 1521 mii_mediachg(device_get_softc(sc->miibus)); 1522 1523 ifp->if_flags |= IFF_RUNNING; 1524 ifp->if_flags &= ~IFF_OACTIVE; 1525 1526 /* 1527 * Enable interrupts. 1528 */ 1529 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, 0); 1530 splx(s); 1531 1532 /* 1533 * Start stats updater. 1534 */ 1535 sc->stat_ch = timeout(fxp_tick, sc, hz); 1536 } 1537 1538 static int 1539 fxp_serial_ifmedia_upd(struct ifnet *ifp) 1540 { 1541 1542 return (0); 1543 } 1544 1545 static void 1546 fxp_serial_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 1547 { 1548 1549 ifmr->ifm_active = IFM_ETHER|IFM_MANUAL; 1550 } 1551 1552 /* 1553 * Change media according to request. 1554 */ 1555 static int 1556 fxp_ifmedia_upd(struct ifnet *ifp) 1557 { 1558 struct fxp_softc *sc = ifp->if_softc; 1559 struct mii_data *mii; 1560 1561 mii = device_get_softc(sc->miibus); 1562 mii_mediachg(mii); 1563 return (0); 1564 } 1565 1566 /* 1567 * Notify the world which media we're using. 1568 */ 1569 static void 1570 fxp_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 1571 { 1572 struct fxp_softc *sc = ifp->if_softc; 1573 struct mii_data *mii; 1574 1575 mii = device_get_softc(sc->miibus); 1576 mii_pollstat(mii); 1577 ifmr->ifm_active = mii->mii_media_active; 1578 ifmr->ifm_status = mii->mii_media_status; 1579 1580 if (ifmr->ifm_status & IFM_10_T && sc->flags & FXP_FLAG_CU_RESUME_BUG) 1581 sc->cu_resume_bug = 1; 1582 else 1583 sc->cu_resume_bug = 0; 1584 } 1585 1586 /* 1587 * Add a buffer to the end of the RFA buffer list. 1588 * Return 0 if successful, 1 for failure. A failure results in 1589 * adding the 'oldm' (if non-NULL) on to the end of the list - 1590 * tossing out its old contents and recycling it. 1591 * The RFA struct is stuck at the beginning of mbuf cluster and the 1592 * data pointer is fixed up to point just past it. 1593 */ 1594 static int 1595 fxp_add_rfabuf(struct fxp_softc *sc, struct mbuf *oldm) 1596 { 1597 u_int32_t v; 1598 struct mbuf *m; 1599 struct fxp_rfa *rfa, *p_rfa; 1600 1601 MGETHDR(m, M_DONTWAIT, MT_DATA); 1602 if (m != NULL) { 1603 MCLGET(m, M_DONTWAIT); 1604 if ((m->m_flags & M_EXT) == 0) { 1605 m_freem(m); 1606 if (oldm == NULL) 1607 return 1; 1608 m = oldm; 1609 m->m_data = m->m_ext.ext_buf; 1610 } 1611 } else { 1612 if (oldm == NULL) 1613 return 1; 1614 m = oldm; 1615 m->m_data = m->m_ext.ext_buf; 1616 } 1617 1618 /* 1619 * Move the data pointer up so that the incoming data packet 1620 * will be 32-bit aligned. 1621 */ 1622 m->m_data += RFA_ALIGNMENT_FUDGE; 1623 1624 /* 1625 * Get a pointer to the base of the mbuf cluster and move 1626 * data start past it. 1627 */ 1628 rfa = mtod(m, struct fxp_rfa *); 1629 m->m_data += sizeof(struct fxp_rfa); 1630 rfa->size = (u_int16_t)(MCLBYTES - sizeof(struct fxp_rfa) - RFA_ALIGNMENT_FUDGE); 1631 1632 /* 1633 * Initialize the rest of the RFA. Note that since the RFA 1634 * is misaligned, we cannot store values directly. Instead, 1635 * we use an optimized, inline copy. 1636 */ 1637 1638 rfa->rfa_status = 0; 1639 rfa->rfa_control = FXP_RFA_CONTROL_EL; 1640 rfa->actual_size = 0; 1641 1642 v = -1; 1643 fxp_lwcopy(&v, (volatile u_int32_t *) rfa->link_addr); 1644 fxp_lwcopy(&v, (volatile u_int32_t *) rfa->rbd_addr); 1645 1646 /* 1647 * If there are other buffers already on the list, attach this 1648 * one to the end by fixing up the tail to point to this one. 1649 */ 1650 if (sc->rfa_headm != NULL) { 1651 p_rfa = (struct fxp_rfa *) (sc->rfa_tailm->m_ext.ext_buf + 1652 RFA_ALIGNMENT_FUDGE); 1653 sc->rfa_tailm->m_next = m; 1654 v = vtophys(rfa); 1655 fxp_lwcopy(&v, (volatile u_int32_t *) p_rfa->link_addr); 1656 p_rfa->rfa_control = 0; 1657 } else { 1658 sc->rfa_headm = m; 1659 } 1660 sc->rfa_tailm = m; 1661 1662 return (m == oldm); 1663 } 1664 1665 static volatile int 1666 fxp_miibus_readreg(device_t dev, int phy, int reg) 1667 { 1668 struct fxp_softc *sc = device_get_softc(dev); 1669 int count = 10000; 1670 int value; 1671 1672 CSR_WRITE_4(sc, FXP_CSR_MDICONTROL, 1673 (FXP_MDI_READ << 26) | (reg << 16) | (phy << 21)); 1674 1675 while (((value = CSR_READ_4(sc, FXP_CSR_MDICONTROL)) & 0x10000000) == 0 1676 && count--) 1677 DELAY(10); 1678 1679 if (count <= 0) 1680 device_printf(dev, "fxp_miibus_readreg: timed out\n"); 1681 1682 return (value & 0xffff); 1683 } 1684 1685 static void 1686 fxp_miibus_writereg(device_t dev, int phy, int reg, int value) 1687 { 1688 struct fxp_softc *sc = device_get_softc(dev); 1689 int count = 10000; 1690 1691 CSR_WRITE_4(sc, FXP_CSR_MDICONTROL, 1692 (FXP_MDI_WRITE << 26) | (reg << 16) | (phy << 21) | 1693 (value & 0xffff)); 1694 1695 while ((CSR_READ_4(sc, FXP_CSR_MDICONTROL) & 0x10000000) == 0 && 1696 count--) 1697 DELAY(10); 1698 1699 if (count <= 0) 1700 device_printf(dev, "fxp_miibus_writereg: timed out\n"); 1701 } 1702 1703 static int 1704 fxp_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 1705 { 1706 struct fxp_softc *sc = ifp->if_softc; 1707 struct ifreq *ifr = (struct ifreq *)data; 1708 struct mii_data *mii; 1709 int s, error = 0; 1710 1711 s = splimp(); 1712 1713 switch (command) { 1714 case SIOCSIFADDR: 1715 case SIOCGIFADDR: 1716 case SIOCSIFMTU: 1717 error = ether_ioctl(ifp, command, data); 1718 break; 1719 1720 case SIOCSIFFLAGS: 1721 if (ifp->if_flags & IFF_ALLMULTI) 1722 sc->flags |= FXP_FLAG_ALL_MCAST; 1723 else 1724 sc->flags &= ~FXP_FLAG_ALL_MCAST; 1725 1726 /* 1727 * If interface is marked up and not running, then start it. 1728 * If it is marked down and running, stop it. 1729 * XXX If it's up then re-initialize it. This is so flags 1730 * such as IFF_PROMISC are handled. 1731 */ 1732 if (ifp->if_flags & IFF_UP) { 1733 fxp_init(sc); 1734 } else { 1735 if (ifp->if_flags & IFF_RUNNING) 1736 fxp_stop(sc); 1737 } 1738 break; 1739 1740 case SIOCADDMULTI: 1741 case SIOCDELMULTI: 1742 if (ifp->if_flags & IFF_ALLMULTI) 1743 sc->flags |= FXP_FLAG_ALL_MCAST; 1744 else 1745 sc->flags &= ~FXP_FLAG_ALL_MCAST; 1746 /* 1747 * Multicast list has changed; set the hardware filter 1748 * accordingly. 1749 */ 1750 if ((sc->flags & FXP_FLAG_ALL_MCAST) == 0) 1751 fxp_mc_setup(sc); 1752 /* 1753 * fxp_mc_setup() can set FXP_FLAG_ALL_MCAST, so check it 1754 * again rather than else {}. 1755 */ 1756 if (sc->flags & FXP_FLAG_ALL_MCAST) 1757 fxp_init(sc); 1758 error = 0; 1759 break; 1760 1761 case SIOCSIFMEDIA: 1762 case SIOCGIFMEDIA: 1763 if (sc->miibus != NULL) { 1764 mii = device_get_softc(sc->miibus); 1765 error = ifmedia_ioctl(ifp, ifr, 1766 &mii->mii_media, command); 1767 } else { 1768 error = ifmedia_ioctl(ifp, ifr, &sc->sc_media, command); 1769 } 1770 break; 1771 1772 default: 1773 error = EINVAL; 1774 } 1775 splx(s); 1776 return (error); 1777 } 1778 1779 /* 1780 * Program the multicast filter. 1781 * 1782 * We have an artificial restriction that the multicast setup command 1783 * must be the first command in the chain, so we take steps to ensure 1784 * this. By requiring this, it allows us to keep up the performance of 1785 * the pre-initialized command ring (esp. link pointers) by not actually 1786 * inserting the mcsetup command in the ring - i.e. its link pointer 1787 * points to the TxCB ring, but the mcsetup descriptor itself is not part 1788 * of it. We then can do 'CU_START' on the mcsetup descriptor and have it 1789 * lead into the regular TxCB ring when it completes. 1790 * 1791 * This function must be called at splimp. 1792 */ 1793 static void 1794 fxp_mc_setup(struct fxp_softc *sc) 1795 { 1796 struct fxp_cb_mcs *mcsp = sc->mcsp; 1797 struct ifnet *ifp = &sc->sc_if; 1798 struct ifmultiaddr *ifma; 1799 int nmcasts; 1800 int count; 1801 1802 /* 1803 * If there are queued commands, we must wait until they are all 1804 * completed. If we are already waiting, then add a NOP command 1805 * with interrupt option so that we're notified when all commands 1806 * have been completed - fxp_start() ensures that no additional 1807 * TX commands will be added when need_mcsetup is true. 1808 */ 1809 if (sc->tx_queued) { 1810 struct fxp_cb_tx *txp; 1811 1812 /* 1813 * need_mcsetup will be true if we are already waiting for the 1814 * NOP command to be completed (see below). In this case, bail. 1815 */ 1816 if (sc->need_mcsetup) 1817 return; 1818 sc->need_mcsetup = 1; 1819 1820 /* 1821 * Add a NOP command with interrupt so that we are notified when all 1822 * TX commands have been processed. 1823 */ 1824 txp = sc->cbl_last->next; 1825 txp->mb_head = NULL; 1826 txp->cb_status = 0; 1827 txp->cb_command = FXP_CB_COMMAND_NOP | 1828 FXP_CB_COMMAND_S | FXP_CB_COMMAND_I; 1829 /* 1830 * Advance the end of list forward. 1831 */ 1832 sc->cbl_last->cb_command &= ~FXP_CB_COMMAND_S; 1833 sc->cbl_last = txp; 1834 sc->tx_queued++; 1835 /* 1836 * Issue a resume in case the CU has just suspended. 1837 */ 1838 fxp_scb_wait(sc); 1839 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_RESUME); 1840 /* 1841 * Set a 5 second timer just in case we don't hear from the 1842 * card again. 1843 */ 1844 ifp->if_timer = 5; 1845 1846 return; 1847 } 1848 sc->need_mcsetup = 0; 1849 1850 /* 1851 * Initialize multicast setup descriptor. 1852 */ 1853 mcsp->next = sc->cbl_base; 1854 mcsp->mb_head = NULL; 1855 mcsp->cb_status = 0; 1856 mcsp->cb_command = FXP_CB_COMMAND_MCAS | 1857 FXP_CB_COMMAND_S | FXP_CB_COMMAND_I; 1858 mcsp->link_addr = vtophys(&sc->cbl_base->cb_status); 1859 1860 nmcasts = 0; 1861 if ((sc->flags & FXP_FLAG_ALL_MCAST) == 0) { 1862 #if __FreeBSD_version < 500000 1863 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1864 #else 1865 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1866 #endif 1867 if (ifma->ifma_addr->sa_family != AF_LINK) 1868 continue; 1869 if (nmcasts >= MAXMCADDR) { 1870 sc->flags |= FXP_FLAG_ALL_MCAST; 1871 nmcasts = 0; 1872 break; 1873 } 1874 bcopy(LLADDR((struct sockaddr_dl *)ifma->ifma_addr), 1875 (void *)(uintptr_t)(volatile void *) 1876 &sc->mcsp->mc_addr[nmcasts][0], 6); 1877 nmcasts++; 1878 } 1879 } 1880 mcsp->mc_cnt = nmcasts * 6; 1881 sc->cbl_first = sc->cbl_last = (struct fxp_cb_tx *) mcsp; 1882 sc->tx_queued = 1; 1883 1884 /* 1885 * Wait until command unit is not active. This should never 1886 * be the case when nothing is queued, but make sure anyway. 1887 */ 1888 count = 100; 1889 while ((CSR_READ_1(sc, FXP_CSR_SCB_RUSCUS) >> 6) == 1890 FXP_SCB_CUS_ACTIVE && --count) 1891 DELAY(10); 1892 if (count == 0) { 1893 device_printf(sc->dev, "command queue timeout\n"); 1894 return; 1895 } 1896 1897 /* 1898 * Start the multicast setup command. 1899 */ 1900 fxp_scb_wait(sc); 1901 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, vtophys(&mcsp->cb_status)); 1902 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 1903 1904 ifp->if_timer = 2; 1905 return; 1906 } 1907