1 /*- 2 * Copyright (c) 1995, David Greenman 3 * Copyright (c) 2001 Jonathan Lemon <jlemon@freebsd.org> 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice unmodified, this list of conditions, and the following 11 * disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 * 28 */ 29 30 #include <sys/cdefs.h> 31 __FBSDID("$FreeBSD$"); 32 33 /* 34 * Intel EtherExpress Pro/100B PCI Fast Ethernet driver 35 */ 36 37 #ifdef HAVE_KERNEL_OPTION_HEADERS 38 #include "opt_device_polling.h" 39 #endif 40 41 #include <sys/param.h> 42 #include <sys/systm.h> 43 #include <sys/endian.h> 44 #include <sys/mbuf.h> 45 /* #include <sys/mutex.h> */ 46 #include <sys/kernel.h> 47 #include <sys/module.h> 48 #include <sys/socket.h> 49 #include <sys/sysctl.h> 50 51 #include <net/if.h> 52 #include <net/if_dl.h> 53 #include <net/if_media.h> 54 55 #include <net/bpf.h> 56 #include <sys/sockio.h> 57 #include <sys/bus.h> 58 #include <machine/bus.h> 59 #include <sys/rman.h> 60 #include <machine/resource.h> 61 62 #include <net/ethernet.h> 63 #include <net/if_arp.h> 64 65 #include <machine/clock.h> /* for DELAY */ 66 67 #include <net/if_types.h> 68 #include <net/if_vlan_var.h> 69 70 #ifdef FXP_IP_CSUM_WAR 71 #include <netinet/in.h> 72 #include <netinet/in_systm.h> 73 #include <netinet/ip.h> 74 #include <machine/in_cksum.h> 75 #endif 76 77 #include <dev/pci/pcivar.h> 78 #include <dev/pci/pcireg.h> /* for PCIM_CMD_xxx */ 79 80 #include <dev/mii/mii.h> 81 #include <dev/mii/miivar.h> 82 83 #include <dev/fxp/if_fxpreg.h> 84 #include <dev/fxp/if_fxpvar.h> 85 #include <dev/fxp/rcvbundl.h> 86 87 MODULE_DEPEND(fxp, pci, 1, 1, 1); 88 MODULE_DEPEND(fxp, ether, 1, 1, 1); 89 MODULE_DEPEND(fxp, miibus, 1, 1, 1); 90 #include "miibus_if.h" 91 92 /* 93 * NOTE! On the Alpha, we have an alignment constraint. The 94 * card DMAs the packet immediately following the RFA. However, 95 * the first thing in the packet is a 14-byte Ethernet header. 96 * This means that the packet is misaligned. To compensate, 97 * we actually offset the RFA 2 bytes into the cluster. This 98 * alignes the packet after the Ethernet header at a 32-bit 99 * boundary. HOWEVER! This means that the RFA is misaligned! 100 */ 101 #define RFA_ALIGNMENT_FUDGE 2 102 103 /* 104 * Set initial transmit threshold at 64 (512 bytes). This is 105 * increased by 64 (512 bytes) at a time, to maximum of 192 106 * (1536 bytes), if an underrun occurs. 107 */ 108 static int tx_threshold = 64; 109 110 /* 111 * The configuration byte map has several undefined fields which 112 * must be one or must be zero. Set up a template for these bits 113 * only, (assuming a 82557 chip) leaving the actual configuration 114 * to fxp_init. 115 * 116 * See struct fxp_cb_config for the bit definitions. 117 */ 118 static u_char fxp_cb_config_template[] = { 119 0x0, 0x0, /* cb_status */ 120 0x0, 0x0, /* cb_command */ 121 0x0, 0x0, 0x0, 0x0, /* link_addr */ 122 0x0, /* 0 */ 123 0x0, /* 1 */ 124 0x0, /* 2 */ 125 0x0, /* 3 */ 126 0x0, /* 4 */ 127 0x0, /* 5 */ 128 0x32, /* 6 */ 129 0x0, /* 7 */ 130 0x0, /* 8 */ 131 0x0, /* 9 */ 132 0x6, /* 10 */ 133 0x0, /* 11 */ 134 0x0, /* 12 */ 135 0x0, /* 13 */ 136 0xf2, /* 14 */ 137 0x48, /* 15 */ 138 0x0, /* 16 */ 139 0x40, /* 17 */ 140 0xf0, /* 18 */ 141 0x0, /* 19 */ 142 0x3f, /* 20 */ 143 0x5 /* 21 */ 144 }; 145 146 struct fxp_ident { 147 uint16_t devid; 148 int16_t revid; /* -1 matches anything */ 149 char *name; 150 }; 151 152 /* 153 * Claim various Intel PCI device identifiers for this driver. The 154 * sub-vendor and sub-device field are extensively used to identify 155 * particular variants, but we don't currently differentiate between 156 * them. 157 */ 158 static struct fxp_ident fxp_ident_table[] = { 159 { 0x1029, -1, "Intel 82559 PCI/CardBus Pro/100" }, 160 { 0x1030, -1, "Intel 82559 Pro/100 Ethernet" }, 161 { 0x1031, -1, "Intel 82801CAM (ICH3) Pro/100 VE Ethernet" }, 162 { 0x1032, -1, "Intel 82801CAM (ICH3) Pro/100 VE Ethernet" }, 163 { 0x1033, -1, "Intel 82801CAM (ICH3) Pro/100 VM Ethernet" }, 164 { 0x1034, -1, "Intel 82801CAM (ICH3) Pro/100 VM Ethernet" }, 165 { 0x1035, -1, "Intel 82801CAM (ICH3) Pro/100 Ethernet" }, 166 { 0x1036, -1, "Intel 82801CAM (ICH3) Pro/100 Ethernet" }, 167 { 0x1037, -1, "Intel 82801CAM (ICH3) Pro/100 Ethernet" }, 168 { 0x1038, -1, "Intel 82801CAM (ICH3) Pro/100 VM Ethernet" }, 169 { 0x1039, -1, "Intel 82801DB (ICH4) Pro/100 VE Ethernet" }, 170 { 0x103A, -1, "Intel 82801DB (ICH4) Pro/100 Ethernet" }, 171 { 0x103B, -1, "Intel 82801DB (ICH4) Pro/100 VM Ethernet" }, 172 { 0x103C, -1, "Intel 82801DB (ICH4) Pro/100 Ethernet" }, 173 { 0x103D, -1, "Intel 82801DB (ICH4) Pro/100 VE Ethernet" }, 174 { 0x103E, -1, "Intel 82801DB (ICH4) Pro/100 VM Ethernet" }, 175 { 0x1050, -1, "Intel 82801BA (D865) Pro/100 VE Ethernet" }, 176 { 0x1051, -1, "Intel 82562ET (ICH5/ICH5R) Pro/100 VE Ethernet" }, 177 { 0x1059, -1, "Intel 82551QM Pro/100 M Mobile Connection" }, 178 { 0x1064, -1, "Intel 82562EZ (ICH6)" }, 179 { 0x1068, -1, "Intel 82801FBM (ICH6-M) Pro/100 VE Ethernet" }, 180 { 0x1069, -1, "Intel 82562EM/EX/GX Pro/100 Ethernet" }, 181 { 0x1092, -1, "Intel Pro/100 VE Network Connection" }, 182 { 0x1209, -1, "Intel 82559ER Embedded 10/100 Ethernet" }, 183 { 0x1229, 0x01, "Intel 82557 Pro/100 Ethernet" }, 184 { 0x1229, 0x02, "Intel 82557 Pro/100 Ethernet" }, 185 { 0x1229, 0x03, "Intel 82557 Pro/100 Ethernet" }, 186 { 0x1229, 0x04, "Intel 82558 Pro/100 Ethernet" }, 187 { 0x1229, 0x05, "Intel 82558 Pro/100 Ethernet" }, 188 { 0x1229, 0x06, "Intel 82559 Pro/100 Ethernet" }, 189 { 0x1229, 0x07, "Intel 82559 Pro/100 Ethernet" }, 190 { 0x1229, 0x08, "Intel 82559 Pro/100 Ethernet" }, 191 { 0x1229, 0x09, "Intel 82559ER Pro/100 Ethernet" }, 192 { 0x1229, 0x0c, "Intel 82550 Pro/100 Ethernet" }, 193 { 0x1229, 0x0d, "Intel 82550 Pro/100 Ethernet" }, 194 { 0x1229, 0x0e, "Intel 82550 Pro/100 Ethernet" }, 195 { 0x1229, 0x0f, "Intel 82551 Pro/100 Ethernet" }, 196 { 0x1229, 0x10, "Intel 82551 Pro/100 Ethernet" }, 197 { 0x1229, -1, "Intel 82557/8/9 Pro/100 Ethernet" }, 198 { 0x2449, -1, "Intel 82801BA/CAM (ICH2/3) Pro/100 Ethernet" }, 199 { 0x27dc, -1, "Intel 82801GB (ICH7) 10/100 Ethernet" }, 200 { 0, -1, NULL }, 201 }; 202 203 #ifdef FXP_IP_CSUM_WAR 204 #define FXP_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 205 #else 206 #define FXP_CSUM_FEATURES (CSUM_TCP | CSUM_UDP) 207 #endif 208 209 static int fxp_probe(device_t dev); 210 static int fxp_attach(device_t dev); 211 static int fxp_detach(device_t dev); 212 static int fxp_shutdown(device_t dev); 213 static int fxp_suspend(device_t dev); 214 static int fxp_resume(device_t dev); 215 216 static void fxp_intr(void *xsc); 217 static void fxp_intr_body(struct fxp_softc *sc, struct ifnet *ifp, 218 uint8_t statack, int count); 219 static void fxp_init(void *xsc); 220 static void fxp_init_body(struct fxp_softc *sc); 221 static void fxp_tick(void *xsc); 222 static void fxp_start(struct ifnet *ifp); 223 static void fxp_start_body(struct ifnet *ifp); 224 static int fxp_encap(struct fxp_softc *sc, struct mbuf *m_head); 225 static void fxp_stop(struct fxp_softc *sc); 226 static void fxp_release(struct fxp_softc *sc); 227 static int fxp_ioctl(struct ifnet *ifp, u_long command, 228 caddr_t data); 229 static void fxp_watchdog(struct ifnet *ifp); 230 static int fxp_add_rfabuf(struct fxp_softc *sc, 231 struct fxp_rx *rxp); 232 static int fxp_mc_addrs(struct fxp_softc *sc); 233 static void fxp_mc_setup(struct fxp_softc *sc); 234 static uint16_t fxp_eeprom_getword(struct fxp_softc *sc, int offset, 235 int autosize); 236 static void fxp_eeprom_putword(struct fxp_softc *sc, int offset, 237 uint16_t data); 238 static void fxp_autosize_eeprom(struct fxp_softc *sc); 239 static void fxp_read_eeprom(struct fxp_softc *sc, u_short *data, 240 int offset, int words); 241 static void fxp_write_eeprom(struct fxp_softc *sc, u_short *data, 242 int offset, int words); 243 static int fxp_ifmedia_upd(struct ifnet *ifp); 244 static void fxp_ifmedia_sts(struct ifnet *ifp, 245 struct ifmediareq *ifmr); 246 static int fxp_serial_ifmedia_upd(struct ifnet *ifp); 247 static void fxp_serial_ifmedia_sts(struct ifnet *ifp, 248 struct ifmediareq *ifmr); 249 static volatile int fxp_miibus_readreg(device_t dev, int phy, int reg); 250 static void fxp_miibus_writereg(device_t dev, int phy, int reg, 251 int value); 252 static void fxp_load_ucode(struct fxp_softc *sc); 253 static int sysctl_int_range(SYSCTL_HANDLER_ARGS, 254 int low, int high); 255 static int sysctl_hw_fxp_bundle_max(SYSCTL_HANDLER_ARGS); 256 static int sysctl_hw_fxp_int_delay(SYSCTL_HANDLER_ARGS); 257 static void fxp_scb_wait(struct fxp_softc *sc); 258 static void fxp_scb_cmd(struct fxp_softc *sc, int cmd); 259 static void fxp_dma_wait(struct fxp_softc *sc, 260 volatile uint16_t *status, bus_dma_tag_t dmat, 261 bus_dmamap_t map); 262 263 static device_method_t fxp_methods[] = { 264 /* Device interface */ 265 DEVMETHOD(device_probe, fxp_probe), 266 DEVMETHOD(device_attach, fxp_attach), 267 DEVMETHOD(device_detach, fxp_detach), 268 DEVMETHOD(device_shutdown, fxp_shutdown), 269 DEVMETHOD(device_suspend, fxp_suspend), 270 DEVMETHOD(device_resume, fxp_resume), 271 272 /* MII interface */ 273 DEVMETHOD(miibus_readreg, fxp_miibus_readreg), 274 DEVMETHOD(miibus_writereg, fxp_miibus_writereg), 275 276 { 0, 0 } 277 }; 278 279 static driver_t fxp_driver = { 280 "fxp", 281 fxp_methods, 282 sizeof(struct fxp_softc), 283 }; 284 285 static devclass_t fxp_devclass; 286 287 DRIVER_MODULE(fxp, pci, fxp_driver, fxp_devclass, 0, 0); 288 DRIVER_MODULE(fxp, cardbus, fxp_driver, fxp_devclass, 0, 0); 289 DRIVER_MODULE(miibus, fxp, miibus_driver, miibus_devclass, 0, 0); 290 291 static struct resource_spec fxp_res_spec_mem[] = { 292 { SYS_RES_MEMORY, FXP_PCI_MMBA, RF_ACTIVE }, 293 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE }, 294 { -1, 0 } 295 }; 296 297 static struct resource_spec fxp_res_spec_io[] = { 298 { SYS_RES_IOPORT, FXP_PCI_IOBA, RF_ACTIVE }, 299 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE }, 300 { -1, 0 } 301 }; 302 303 /* 304 * Wait for the previous command to be accepted (but not necessarily 305 * completed). 306 */ 307 static void 308 fxp_scb_wait(struct fxp_softc *sc) 309 { 310 union { 311 uint16_t w; 312 uint8_t b[2]; 313 } flowctl; 314 int i = 10000; 315 316 while (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) && --i) 317 DELAY(2); 318 if (i == 0) { 319 flowctl.b[0] = CSR_READ_1(sc, FXP_CSR_FLOWCONTROL); 320 flowctl.b[1] = CSR_READ_1(sc, FXP_CSR_FLOWCONTROL + 1); 321 device_printf(sc->dev, "SCB timeout: 0x%x 0x%x 0x%x 0x%x\n", 322 CSR_READ_1(sc, FXP_CSR_SCB_COMMAND), 323 CSR_READ_1(sc, FXP_CSR_SCB_STATACK), 324 CSR_READ_1(sc, FXP_CSR_SCB_RUSCUS), flowctl.w); 325 } 326 } 327 328 static void 329 fxp_scb_cmd(struct fxp_softc *sc, int cmd) 330 { 331 332 if (cmd == FXP_SCB_COMMAND_CU_RESUME && sc->cu_resume_bug) { 333 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_CB_COMMAND_NOP); 334 fxp_scb_wait(sc); 335 } 336 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, cmd); 337 } 338 339 static void 340 fxp_dma_wait(struct fxp_softc *sc, volatile uint16_t *status, 341 bus_dma_tag_t dmat, bus_dmamap_t map) 342 { 343 int i = 10000; 344 345 bus_dmamap_sync(dmat, map, BUS_DMASYNC_POSTREAD); 346 while (!(le16toh(*status) & FXP_CB_STATUS_C) && --i) { 347 DELAY(2); 348 bus_dmamap_sync(dmat, map, BUS_DMASYNC_POSTREAD); 349 } 350 if (i == 0) 351 device_printf(sc->dev, "DMA timeout\n"); 352 } 353 354 /* 355 * Return identification string if this device is ours. 356 */ 357 static int 358 fxp_probe(device_t dev) 359 { 360 uint16_t devid; 361 uint8_t revid; 362 struct fxp_ident *ident; 363 364 if (pci_get_vendor(dev) == FXP_VENDORID_INTEL) { 365 devid = pci_get_device(dev); 366 revid = pci_get_revid(dev); 367 for (ident = fxp_ident_table; ident->name != NULL; ident++) { 368 if (ident->devid == devid && 369 (ident->revid == revid || ident->revid == -1)) { 370 device_set_desc(dev, ident->name); 371 return (BUS_PROBE_DEFAULT); 372 } 373 } 374 } 375 return (ENXIO); 376 } 377 378 static void 379 fxp_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error) 380 { 381 uint32_t *addr; 382 383 if (error) 384 return; 385 386 KASSERT(nseg == 1, ("too many DMA segments, %d should be 1", nseg)); 387 addr = arg; 388 *addr = segs->ds_addr; 389 } 390 391 static int 392 fxp_attach(device_t dev) 393 { 394 struct fxp_softc *sc; 395 struct fxp_cb_tx *tcbp; 396 struct fxp_tx *txp; 397 struct fxp_rx *rxp; 398 struct ifnet *ifp; 399 uint32_t val; 400 uint16_t data, myea[ETHER_ADDR_LEN / 2]; 401 u_char eaddr[ETHER_ADDR_LEN]; 402 int i, prefer_iomap; 403 int error; 404 405 error = 0; 406 sc = device_get_softc(dev); 407 sc->dev = dev; 408 mtx_init(&sc->sc_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 409 MTX_DEF); 410 callout_init_mtx(&sc->stat_ch, &sc->sc_mtx, 0); 411 ifmedia_init(&sc->sc_media, 0, fxp_serial_ifmedia_upd, 412 fxp_serial_ifmedia_sts); 413 414 ifp = sc->ifp = if_alloc(IFT_ETHER); 415 if (ifp == NULL) { 416 device_printf(dev, "can not if_alloc()\n"); 417 error = ENOSPC; 418 goto fail; 419 } 420 421 /* 422 * Enable bus mastering. 423 */ 424 pci_enable_busmaster(dev); 425 val = pci_read_config(dev, PCIR_COMMAND, 2); 426 427 /* 428 * Figure out which we should try first - memory mapping or i/o mapping? 429 * We default to memory mapping. Then we accept an override from the 430 * command line. Then we check to see which one is enabled. 431 */ 432 prefer_iomap = 0; 433 resource_int_value(device_get_name(dev), device_get_unit(dev), 434 "prefer_iomap", &prefer_iomap); 435 if (prefer_iomap) 436 sc->fxp_spec = fxp_res_spec_io; 437 else 438 sc->fxp_spec = fxp_res_spec_mem; 439 440 error = bus_alloc_resources(dev, sc->fxp_spec, sc->fxp_res); 441 if (error) { 442 if (sc->fxp_spec == fxp_res_spec_mem) 443 sc->fxp_spec = fxp_res_spec_io; 444 else 445 sc->fxp_spec = fxp_res_spec_mem; 446 error = bus_alloc_resources(dev, sc->fxp_spec, sc->fxp_res); 447 } 448 if (error) { 449 device_printf(dev, "could not allocate resources\n"); 450 error = ENXIO; 451 goto fail; 452 } 453 454 if (bootverbose) { 455 device_printf(dev, "using %s space register mapping\n", 456 sc->fxp_spec == fxp_res_spec_mem ? "memory" : "I/O"); 457 } 458 459 /* 460 * Reset to a stable state. 461 */ 462 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET); 463 DELAY(10); 464 465 /* 466 * Find out how large of an SEEPROM we have. 467 */ 468 fxp_autosize_eeprom(sc); 469 470 /* 471 * Find out the chip revision; lump all 82557 revs together. 472 */ 473 fxp_read_eeprom(sc, &data, 5, 1); 474 if ((data >> 8) == 1) 475 sc->revision = FXP_REV_82557; 476 else 477 sc->revision = pci_get_revid(dev); 478 479 /* 480 * Determine whether we must use the 503 serial interface. 481 */ 482 fxp_read_eeprom(sc, &data, 6, 1); 483 if (sc->revision == FXP_REV_82557 && (data & FXP_PHY_DEVICE_MASK) != 0 484 && (data & FXP_PHY_SERIAL_ONLY)) 485 sc->flags |= FXP_FLAG_SERIAL_MEDIA; 486 487 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 488 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 489 OID_AUTO, "int_delay", CTLTYPE_INT | CTLFLAG_RW, 490 &sc->tunable_int_delay, 0, sysctl_hw_fxp_int_delay, "I", 491 "FXP driver receive interrupt microcode bundling delay"); 492 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 493 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 494 OID_AUTO, "bundle_max", CTLTYPE_INT | CTLFLAG_RW, 495 &sc->tunable_bundle_max, 0, sysctl_hw_fxp_bundle_max, "I", 496 "FXP driver receive interrupt microcode bundle size limit"); 497 SYSCTL_ADD_INT(device_get_sysctl_ctx(dev), 498 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 499 OID_AUTO, "rnr", CTLFLAG_RD, &sc->rnr, 0, 500 "FXP RNR events"); 501 SYSCTL_ADD_INT(device_get_sysctl_ctx(dev), 502 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 503 OID_AUTO, "noflow", CTLFLAG_RW, &sc->tunable_noflow, 0, 504 "FXP flow control disabled"); 505 506 /* 507 * Pull in device tunables. 508 */ 509 sc->tunable_int_delay = TUNABLE_INT_DELAY; 510 sc->tunable_bundle_max = TUNABLE_BUNDLE_MAX; 511 sc->tunable_noflow = 1; 512 (void) resource_int_value(device_get_name(dev), device_get_unit(dev), 513 "int_delay", &sc->tunable_int_delay); 514 (void) resource_int_value(device_get_name(dev), device_get_unit(dev), 515 "bundle_max", &sc->tunable_bundle_max); 516 (void) resource_int_value(device_get_name(dev), device_get_unit(dev), 517 "noflow", &sc->tunable_noflow); 518 sc->rnr = 0; 519 520 /* 521 * Enable workarounds for certain chip revision deficiencies. 522 * 523 * Systems based on the ICH2/ICH2-M chip from Intel, and possibly 524 * some systems based a normal 82559 design, have a defect where 525 * the chip can cause a PCI protocol violation if it receives 526 * a CU_RESUME command when it is entering the IDLE state. The 527 * workaround is to disable Dynamic Standby Mode, so the chip never 528 * deasserts CLKRUN#, and always remains in an active state. 529 * 530 * See Intel 82801BA/82801BAM Specification Update, Errata #30. 531 */ 532 i = pci_get_device(dev); 533 if (i == 0x2449 || (i > 0x1030 && i < 0x1039) || 534 sc->revision >= FXP_REV_82559_A0) { 535 fxp_read_eeprom(sc, &data, 10, 1); 536 if (data & 0x02) { /* STB enable */ 537 uint16_t cksum; 538 int i; 539 540 device_printf(dev, 541 "Disabling dynamic standby mode in EEPROM\n"); 542 data &= ~0x02; 543 fxp_write_eeprom(sc, &data, 10, 1); 544 device_printf(dev, "New EEPROM ID: 0x%x\n", data); 545 cksum = 0; 546 for (i = 0; i < (1 << sc->eeprom_size) - 1; i++) { 547 fxp_read_eeprom(sc, &data, i, 1); 548 cksum += data; 549 } 550 i = (1 << sc->eeprom_size) - 1; 551 cksum = 0xBABA - cksum; 552 fxp_read_eeprom(sc, &data, i, 1); 553 fxp_write_eeprom(sc, &cksum, i, 1); 554 device_printf(dev, 555 "EEPROM checksum @ 0x%x: 0x%x -> 0x%x\n", 556 i, data, cksum); 557 #if 1 558 /* 559 * If the user elects to continue, try the software 560 * workaround, as it is better than nothing. 561 */ 562 sc->flags |= FXP_FLAG_CU_RESUME_BUG; 563 #endif 564 } 565 } 566 567 /* 568 * If we are not a 82557 chip, we can enable extended features. 569 */ 570 if (sc->revision != FXP_REV_82557) { 571 /* 572 * If MWI is enabled in the PCI configuration, and there 573 * is a valid cacheline size (8 or 16 dwords), then tell 574 * the board to turn on MWI. 575 */ 576 if (val & PCIM_CMD_MWRICEN && 577 pci_read_config(dev, PCIR_CACHELNSZ, 1) != 0) 578 sc->flags |= FXP_FLAG_MWI_ENABLE; 579 580 /* turn on the extended TxCB feature */ 581 sc->flags |= FXP_FLAG_EXT_TXCB; 582 583 /* enable reception of long frames for VLAN */ 584 sc->flags |= FXP_FLAG_LONG_PKT_EN; 585 } else { 586 /* a hack to get long VLAN frames on a 82557 */ 587 sc->flags |= FXP_FLAG_SAVE_BAD; 588 } 589 590 /* 591 * Enable use of extended RFDs and TCBs for 82550 592 * and later chips. Note: we need extended TXCB support 593 * too, but that's already enabled by the code above. 594 * Be careful to do this only on the right devices. 595 */ 596 if (sc->revision == FXP_REV_82550 || sc->revision == FXP_REV_82550_C || 597 sc->revision == FXP_REV_82551_E || sc->revision == FXP_REV_82551_F 598 || sc->revision == FXP_REV_82551_10) { 599 sc->rfa_size = sizeof (struct fxp_rfa); 600 sc->tx_cmd = FXP_CB_COMMAND_IPCBXMIT; 601 sc->flags |= FXP_FLAG_EXT_RFA; 602 } else { 603 sc->rfa_size = sizeof (struct fxp_rfa) - FXP_RFAX_LEN; 604 sc->tx_cmd = FXP_CB_COMMAND_XMIT; 605 } 606 607 /* 608 * Allocate DMA tags and DMA safe memory. 609 */ 610 sc->maxtxseg = FXP_NTXSEG; 611 if (sc->flags & FXP_FLAG_EXT_RFA) 612 sc->maxtxseg--; 613 error = bus_dma_tag_create(NULL, 2, 0, BUS_SPACE_MAXADDR_32BIT, 614 BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES * sc->maxtxseg, 615 sc->maxtxseg, MCLBYTES, 0, busdma_lock_mutex, &Giant, 616 &sc->fxp_mtag); 617 if (error) { 618 device_printf(dev, "could not allocate dma tag\n"); 619 goto fail; 620 } 621 622 error = bus_dma_tag_create(NULL, 4, 0, BUS_SPACE_MAXADDR_32BIT, 623 BUS_SPACE_MAXADDR, NULL, NULL, sizeof(struct fxp_stats), 1, 624 sizeof(struct fxp_stats), 0, busdma_lock_mutex, &Giant, 625 &sc->fxp_stag); 626 if (error) { 627 device_printf(dev, "could not allocate dma tag\n"); 628 goto fail; 629 } 630 631 error = bus_dmamem_alloc(sc->fxp_stag, (void **)&sc->fxp_stats, 632 BUS_DMA_NOWAIT | BUS_DMA_ZERO, &sc->fxp_smap); 633 if (error) 634 goto fail; 635 error = bus_dmamap_load(sc->fxp_stag, sc->fxp_smap, sc->fxp_stats, 636 sizeof(struct fxp_stats), fxp_dma_map_addr, &sc->stats_addr, 0); 637 if (error) { 638 device_printf(dev, "could not map the stats buffer\n"); 639 goto fail; 640 } 641 642 error = bus_dma_tag_create(NULL, 4, 0, BUS_SPACE_MAXADDR_32BIT, 643 BUS_SPACE_MAXADDR, NULL, NULL, FXP_TXCB_SZ, 1, 644 FXP_TXCB_SZ, 0, busdma_lock_mutex, &Giant, &sc->cbl_tag); 645 if (error) { 646 device_printf(dev, "could not allocate dma tag\n"); 647 goto fail; 648 } 649 650 error = bus_dmamem_alloc(sc->cbl_tag, (void **)&sc->fxp_desc.cbl_list, 651 BUS_DMA_NOWAIT | BUS_DMA_ZERO, &sc->cbl_map); 652 if (error) 653 goto fail; 654 655 error = bus_dmamap_load(sc->cbl_tag, sc->cbl_map, 656 sc->fxp_desc.cbl_list, FXP_TXCB_SZ, fxp_dma_map_addr, 657 &sc->fxp_desc.cbl_addr, 0); 658 if (error) { 659 device_printf(dev, "could not map DMA memory\n"); 660 goto fail; 661 } 662 663 error = bus_dma_tag_create(NULL, 4, 0, BUS_SPACE_MAXADDR_32BIT, 664 BUS_SPACE_MAXADDR, NULL, NULL, sizeof(struct fxp_cb_mcs), 1, 665 sizeof(struct fxp_cb_mcs), 0, busdma_lock_mutex, &Giant, 666 &sc->mcs_tag); 667 if (error) { 668 device_printf(dev, "could not allocate dma tag\n"); 669 goto fail; 670 } 671 672 error = bus_dmamem_alloc(sc->mcs_tag, (void **)&sc->mcsp, 673 BUS_DMA_NOWAIT, &sc->mcs_map); 674 if (error) 675 goto fail; 676 error = bus_dmamap_load(sc->mcs_tag, sc->mcs_map, sc->mcsp, 677 sizeof(struct fxp_cb_mcs), fxp_dma_map_addr, &sc->mcs_addr, 0); 678 if (error) { 679 device_printf(dev, "can't map the multicast setup command\n"); 680 goto fail; 681 } 682 683 /* 684 * Pre-allocate the TX DMA maps and setup the pointers to 685 * the TX command blocks. 686 */ 687 txp = sc->fxp_desc.tx_list; 688 tcbp = sc->fxp_desc.cbl_list; 689 for (i = 0; i < FXP_NTXCB; i++) { 690 txp[i].tx_cb = tcbp + i; 691 error = bus_dmamap_create(sc->fxp_mtag, 0, &txp[i].tx_map); 692 if (error) { 693 device_printf(dev, "can't create DMA map for TX\n"); 694 goto fail; 695 } 696 } 697 error = bus_dmamap_create(sc->fxp_mtag, 0, &sc->spare_map); 698 if (error) { 699 device_printf(dev, "can't create spare DMA map\n"); 700 goto fail; 701 } 702 703 /* 704 * Pre-allocate our receive buffers. 705 */ 706 sc->fxp_desc.rx_head = sc->fxp_desc.rx_tail = NULL; 707 for (i = 0; i < FXP_NRFABUFS; i++) { 708 rxp = &sc->fxp_desc.rx_list[i]; 709 error = bus_dmamap_create(sc->fxp_mtag, 0, &rxp->rx_map); 710 if (error) { 711 device_printf(dev, "can't create DMA map for RX\n"); 712 goto fail; 713 } 714 if (fxp_add_rfabuf(sc, rxp) != 0) { 715 error = ENOMEM; 716 goto fail; 717 } 718 } 719 720 /* 721 * Read MAC address. 722 */ 723 fxp_read_eeprom(sc, myea, 0, 3); 724 eaddr[0] = myea[0] & 0xff; 725 eaddr[1] = myea[0] >> 8; 726 eaddr[2] = myea[1] & 0xff; 727 eaddr[3] = myea[1] >> 8; 728 eaddr[4] = myea[2] & 0xff; 729 eaddr[5] = myea[2] >> 8; 730 if (bootverbose) { 731 device_printf(dev, "PCI IDs: %04x %04x %04x %04x %04x\n", 732 pci_get_vendor(dev), pci_get_device(dev), 733 pci_get_subvendor(dev), pci_get_subdevice(dev), 734 pci_get_revid(dev)); 735 fxp_read_eeprom(sc, &data, 10, 1); 736 device_printf(dev, "Dynamic Standby mode is %s\n", 737 data & 0x02 ? "enabled" : "disabled"); 738 } 739 740 /* 741 * If this is only a 10Mbps device, then there is no MII, and 742 * the PHY will use a serial interface instead. 743 * 744 * The Seeq 80c24 AutoDUPLEX(tm) Ethernet Interface Adapter 745 * doesn't have a programming interface of any sort. The 746 * media is sensed automatically based on how the link partner 747 * is configured. This is, in essence, manual configuration. 748 */ 749 if (sc->flags & FXP_FLAG_SERIAL_MEDIA) { 750 ifmedia_add(&sc->sc_media, IFM_ETHER|IFM_MANUAL, 0, NULL); 751 ifmedia_set(&sc->sc_media, IFM_ETHER|IFM_MANUAL); 752 } else { 753 if (mii_phy_probe(dev, &sc->miibus, fxp_ifmedia_upd, 754 fxp_ifmedia_sts)) { 755 device_printf(dev, "MII without any PHY!\n"); 756 error = ENXIO; 757 goto fail; 758 } 759 } 760 761 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 762 ifp->if_init = fxp_init; 763 ifp->if_softc = sc; 764 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 765 ifp->if_ioctl = fxp_ioctl; 766 ifp->if_start = fxp_start; 767 ifp->if_watchdog = fxp_watchdog; 768 769 ifp->if_capabilities = ifp->if_capenable = 0; 770 771 /* Enable checksum offload for 82550 or better chips */ 772 if (sc->flags & FXP_FLAG_EXT_RFA) { 773 ifp->if_hwassist = FXP_CSUM_FEATURES; 774 ifp->if_capabilities |= IFCAP_HWCSUM; 775 ifp->if_capenable |= IFCAP_HWCSUM; 776 } 777 778 #ifdef DEVICE_POLLING 779 /* Inform the world we support polling. */ 780 ifp->if_capabilities |= IFCAP_POLLING; 781 #endif 782 783 /* 784 * Attach the interface. 785 */ 786 ether_ifattach(ifp, eaddr); 787 788 /* 789 * Tell the upper layer(s) we support long frames. 790 * Must appear after the call to ether_ifattach() because 791 * ether_ifattach() sets ifi_hdrlen to the default value. 792 */ 793 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 794 ifp->if_capabilities |= IFCAP_VLAN_MTU; 795 ifp->if_capenable |= IFCAP_VLAN_MTU; /* the hw bits already set */ 796 797 /* 798 * Let the system queue as many packets as we have available 799 * TX descriptors. 800 */ 801 IFQ_SET_MAXLEN(&ifp->if_snd, FXP_NTXCB - 1); 802 ifp->if_snd.ifq_drv_maxlen = FXP_NTXCB - 1; 803 IFQ_SET_READY(&ifp->if_snd); 804 805 /* 806 * Hook our interrupt after all initialization is complete. 807 */ 808 error = bus_setup_intr(dev, sc->fxp_res[1], INTR_TYPE_NET | INTR_MPSAFE, 809 fxp_intr, sc, &sc->ih); 810 if (error) { 811 device_printf(dev, "could not setup irq\n"); 812 ether_ifdetach(sc->ifp); 813 goto fail; 814 } 815 816 fail: 817 if (error) 818 fxp_release(sc); 819 return (error); 820 } 821 822 /* 823 * Release all resources. The softc lock should not be held and the 824 * interrupt should already be torn down. 825 */ 826 static void 827 fxp_release(struct fxp_softc *sc) 828 { 829 struct fxp_rx *rxp; 830 struct fxp_tx *txp; 831 int i; 832 833 FXP_LOCK_ASSERT(sc, MA_NOTOWNED); 834 KASSERT(sc->ih == NULL, 835 ("fxp_release() called with intr handle still active")); 836 if (sc->miibus) 837 device_delete_child(sc->dev, sc->miibus); 838 bus_generic_detach(sc->dev); 839 ifmedia_removeall(&sc->sc_media); 840 if (sc->fxp_desc.cbl_list) { 841 bus_dmamap_unload(sc->cbl_tag, sc->cbl_map); 842 bus_dmamem_free(sc->cbl_tag, sc->fxp_desc.cbl_list, 843 sc->cbl_map); 844 } 845 if (sc->fxp_stats) { 846 bus_dmamap_unload(sc->fxp_stag, sc->fxp_smap); 847 bus_dmamem_free(sc->fxp_stag, sc->fxp_stats, sc->fxp_smap); 848 } 849 if (sc->mcsp) { 850 bus_dmamap_unload(sc->mcs_tag, sc->mcs_map); 851 bus_dmamem_free(sc->mcs_tag, sc->mcsp, sc->mcs_map); 852 } 853 bus_release_resources(sc->dev, sc->fxp_spec, sc->fxp_res); 854 if (sc->fxp_mtag) { 855 for (i = 0; i < FXP_NRFABUFS; i++) { 856 rxp = &sc->fxp_desc.rx_list[i]; 857 if (rxp->rx_mbuf != NULL) { 858 bus_dmamap_sync(sc->fxp_mtag, rxp->rx_map, 859 BUS_DMASYNC_POSTREAD); 860 bus_dmamap_unload(sc->fxp_mtag, rxp->rx_map); 861 m_freem(rxp->rx_mbuf); 862 } 863 bus_dmamap_destroy(sc->fxp_mtag, rxp->rx_map); 864 } 865 bus_dmamap_destroy(sc->fxp_mtag, sc->spare_map); 866 for (i = 0; i < FXP_NTXCB; i++) { 867 txp = &sc->fxp_desc.tx_list[i]; 868 if (txp->tx_mbuf != NULL) { 869 bus_dmamap_sync(sc->fxp_mtag, txp->tx_map, 870 BUS_DMASYNC_POSTWRITE); 871 bus_dmamap_unload(sc->fxp_mtag, txp->tx_map); 872 m_freem(txp->tx_mbuf); 873 } 874 bus_dmamap_destroy(sc->fxp_mtag, txp->tx_map); 875 } 876 bus_dma_tag_destroy(sc->fxp_mtag); 877 } 878 if (sc->fxp_stag) 879 bus_dma_tag_destroy(sc->fxp_stag); 880 if (sc->cbl_tag) 881 bus_dma_tag_destroy(sc->cbl_tag); 882 if (sc->mcs_tag) 883 bus_dma_tag_destroy(sc->mcs_tag); 884 if (sc->ifp) 885 if_free(sc->ifp); 886 887 mtx_destroy(&sc->sc_mtx); 888 } 889 890 /* 891 * Detach interface. 892 */ 893 static int 894 fxp_detach(device_t dev) 895 { 896 struct fxp_softc *sc = device_get_softc(dev); 897 898 #ifdef DEVICE_POLLING 899 if (sc->ifp->if_capenable & IFCAP_POLLING) 900 ether_poll_deregister(sc->ifp); 901 #endif 902 903 FXP_LOCK(sc); 904 sc->suspended = 1; /* Do same thing as we do for suspend */ 905 /* 906 * Stop DMA and drop transmit queue, but disable interrupts first. 907 */ 908 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE); 909 fxp_stop(sc); 910 FXP_UNLOCK(sc); 911 callout_drain(&sc->stat_ch); 912 913 /* 914 * Close down routes etc. 915 */ 916 ether_ifdetach(sc->ifp); 917 918 /* 919 * Unhook interrupt before dropping lock. This is to prevent 920 * races with fxp_intr(). 921 */ 922 bus_teardown_intr(sc->dev, sc->fxp_res[1], sc->ih); 923 sc->ih = NULL; 924 925 /* Release our allocated resources. */ 926 fxp_release(sc); 927 return (0); 928 } 929 930 /* 931 * Device shutdown routine. Called at system shutdown after sync. The 932 * main purpose of this routine is to shut off receiver DMA so that 933 * kernel memory doesn't get clobbered during warmboot. 934 */ 935 static int 936 fxp_shutdown(device_t dev) 937 { 938 struct fxp_softc *sc = device_get_softc(dev); 939 940 /* 941 * Make sure that DMA is disabled prior to reboot. Not doing 942 * do could allow DMA to corrupt kernel memory during the 943 * reboot before the driver initializes. 944 */ 945 FXP_LOCK(sc); 946 fxp_stop(sc); 947 FXP_UNLOCK(sc); 948 return (0); 949 } 950 951 /* 952 * Device suspend routine. Stop the interface and save some PCI 953 * settings in case the BIOS doesn't restore them properly on 954 * resume. 955 */ 956 static int 957 fxp_suspend(device_t dev) 958 { 959 struct fxp_softc *sc = device_get_softc(dev); 960 961 FXP_LOCK(sc); 962 963 fxp_stop(sc); 964 965 sc->suspended = 1; 966 967 FXP_UNLOCK(sc); 968 return (0); 969 } 970 971 /* 972 * Device resume routine. re-enable busmastering, and restart the interface if 973 * appropriate. 974 */ 975 static int 976 fxp_resume(device_t dev) 977 { 978 struct fxp_softc *sc = device_get_softc(dev); 979 struct ifnet *ifp = sc->ifp; 980 981 FXP_LOCK(sc); 982 983 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET); 984 DELAY(10); 985 986 /* reinitialize interface if necessary */ 987 if (ifp->if_flags & IFF_UP) 988 fxp_init_body(sc); 989 990 sc->suspended = 0; 991 992 FXP_UNLOCK(sc); 993 return (0); 994 } 995 996 static void 997 fxp_eeprom_shiftin(struct fxp_softc *sc, int data, int length) 998 { 999 uint16_t reg; 1000 int x; 1001 1002 /* 1003 * Shift in data. 1004 */ 1005 for (x = 1 << (length - 1); x; x >>= 1) { 1006 if (data & x) 1007 reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI; 1008 else 1009 reg = FXP_EEPROM_EECS; 1010 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 1011 DELAY(1); 1012 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK); 1013 DELAY(1); 1014 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 1015 DELAY(1); 1016 } 1017 } 1018 1019 /* 1020 * Read from the serial EEPROM. Basically, you manually shift in 1021 * the read opcode (one bit at a time) and then shift in the address, 1022 * and then you shift out the data (all of this one bit at a time). 1023 * The word size is 16 bits, so you have to provide the address for 1024 * every 16 bits of data. 1025 */ 1026 static uint16_t 1027 fxp_eeprom_getword(struct fxp_softc *sc, int offset, int autosize) 1028 { 1029 uint16_t reg, data; 1030 int x; 1031 1032 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 1033 /* 1034 * Shift in read opcode. 1035 */ 1036 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_READ, 3); 1037 /* 1038 * Shift in address. 1039 */ 1040 data = 0; 1041 for (x = 1 << (sc->eeprom_size - 1); x; x >>= 1) { 1042 if (offset & x) 1043 reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI; 1044 else 1045 reg = FXP_EEPROM_EECS; 1046 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 1047 DELAY(1); 1048 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK); 1049 DELAY(1); 1050 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 1051 DELAY(1); 1052 reg = CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO; 1053 data++; 1054 if (autosize && reg == 0) { 1055 sc->eeprom_size = data; 1056 break; 1057 } 1058 } 1059 /* 1060 * Shift out data. 1061 */ 1062 data = 0; 1063 reg = FXP_EEPROM_EECS; 1064 for (x = 1 << 15; x; x >>= 1) { 1065 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK); 1066 DELAY(1); 1067 if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO) 1068 data |= x; 1069 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 1070 DELAY(1); 1071 } 1072 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 1073 DELAY(1); 1074 1075 return (data); 1076 } 1077 1078 static void 1079 fxp_eeprom_putword(struct fxp_softc *sc, int offset, uint16_t data) 1080 { 1081 int i; 1082 1083 /* 1084 * Erase/write enable. 1085 */ 1086 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 1087 fxp_eeprom_shiftin(sc, 0x4, 3); 1088 fxp_eeprom_shiftin(sc, 0x03 << (sc->eeprom_size - 2), sc->eeprom_size); 1089 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 1090 DELAY(1); 1091 /* 1092 * Shift in write opcode, address, data. 1093 */ 1094 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 1095 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_WRITE, 3); 1096 fxp_eeprom_shiftin(sc, offset, sc->eeprom_size); 1097 fxp_eeprom_shiftin(sc, data, 16); 1098 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 1099 DELAY(1); 1100 /* 1101 * Wait for EEPROM to finish up. 1102 */ 1103 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 1104 DELAY(1); 1105 for (i = 0; i < 1000; i++) { 1106 if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO) 1107 break; 1108 DELAY(50); 1109 } 1110 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 1111 DELAY(1); 1112 /* 1113 * Erase/write disable. 1114 */ 1115 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 1116 fxp_eeprom_shiftin(sc, 0x4, 3); 1117 fxp_eeprom_shiftin(sc, 0, sc->eeprom_size); 1118 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 1119 DELAY(1); 1120 } 1121 1122 /* 1123 * From NetBSD: 1124 * 1125 * Figure out EEPROM size. 1126 * 1127 * 559's can have either 64-word or 256-word EEPROMs, the 558 1128 * datasheet only talks about 64-word EEPROMs, and the 557 datasheet 1129 * talks about the existance of 16 to 256 word EEPROMs. 1130 * 1131 * The only known sizes are 64 and 256, where the 256 version is used 1132 * by CardBus cards to store CIS information. 1133 * 1134 * The address is shifted in msb-to-lsb, and after the last 1135 * address-bit the EEPROM is supposed to output a `dummy zero' bit, 1136 * after which follows the actual data. We try to detect this zero, by 1137 * probing the data-out bit in the EEPROM control register just after 1138 * having shifted in a bit. If the bit is zero, we assume we've 1139 * shifted enough address bits. The data-out should be tri-state, 1140 * before this, which should translate to a logical one. 1141 */ 1142 static void 1143 fxp_autosize_eeprom(struct fxp_softc *sc) 1144 { 1145 1146 /* guess maximum size of 256 words */ 1147 sc->eeprom_size = 8; 1148 1149 /* autosize */ 1150 (void) fxp_eeprom_getword(sc, 0, 1); 1151 } 1152 1153 static void 1154 fxp_read_eeprom(struct fxp_softc *sc, u_short *data, int offset, int words) 1155 { 1156 int i; 1157 1158 for (i = 0; i < words; i++) 1159 data[i] = fxp_eeprom_getword(sc, offset + i, 0); 1160 } 1161 1162 static void 1163 fxp_write_eeprom(struct fxp_softc *sc, u_short *data, int offset, int words) 1164 { 1165 int i; 1166 1167 for (i = 0; i < words; i++) 1168 fxp_eeprom_putword(sc, offset + i, data[i]); 1169 } 1170 1171 /* 1172 * Grab the softc lock and call the real fxp_start_body() routine 1173 */ 1174 static void 1175 fxp_start(struct ifnet *ifp) 1176 { 1177 struct fxp_softc *sc = ifp->if_softc; 1178 1179 FXP_LOCK(sc); 1180 fxp_start_body(ifp); 1181 FXP_UNLOCK(sc); 1182 } 1183 1184 /* 1185 * Start packet transmission on the interface. 1186 * This routine must be called with the softc lock held, and is an 1187 * internal entry point only. 1188 */ 1189 static void 1190 fxp_start_body(struct ifnet *ifp) 1191 { 1192 struct fxp_softc *sc = ifp->if_softc; 1193 struct mbuf *mb_head; 1194 int error, txqueued; 1195 1196 FXP_LOCK_ASSERT(sc, MA_OWNED); 1197 1198 /* 1199 * See if we need to suspend xmit until the multicast filter 1200 * has been reprogrammed (which can only be done at the head 1201 * of the command chain). 1202 */ 1203 if (sc->need_mcsetup) 1204 return; 1205 1206 /* 1207 * We're finished if there is nothing more to add to the list or if 1208 * we're all filled up with buffers to transmit. 1209 * NOTE: One TxCB is reserved to guarantee that fxp_mc_setup() can add 1210 * a NOP command when needed. 1211 */ 1212 txqueued = 0; 1213 while (!IFQ_DRV_IS_EMPTY(&ifp->if_snd) && 1214 sc->tx_queued < FXP_NTXCB - 1) { 1215 1216 /* 1217 * Grab a packet to transmit. 1218 */ 1219 IFQ_DRV_DEQUEUE(&ifp->if_snd, mb_head); 1220 if (mb_head == NULL) 1221 break; 1222 1223 error = fxp_encap(sc, mb_head); 1224 if (error) 1225 break; 1226 txqueued = 1; 1227 } 1228 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE); 1229 1230 /* 1231 * We're finished. If we added to the list, issue a RESUME to get DMA 1232 * going again if suspended. 1233 */ 1234 if (txqueued) { 1235 fxp_scb_wait(sc); 1236 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_RESUME); 1237 } 1238 } 1239 1240 static int 1241 fxp_encap(struct fxp_softc *sc, struct mbuf *m_head) 1242 { 1243 struct ifnet *ifp; 1244 struct mbuf *m; 1245 struct fxp_tx *txp; 1246 struct fxp_cb_tx *cbp; 1247 bus_dma_segment_t segs[FXP_NTXSEG]; 1248 int chainlen, error, i, nseg; 1249 1250 FXP_LOCK_ASSERT(sc, MA_OWNED); 1251 ifp = sc->ifp; 1252 1253 /* 1254 * Get pointer to next available tx desc. 1255 */ 1256 txp = sc->fxp_desc.tx_last->tx_next; 1257 1258 /* 1259 * A note in Appendix B of the Intel 8255x 10/100 Mbps 1260 * Ethernet Controller Family Open Source Software 1261 * Developer Manual says: 1262 * Using software parsing is only allowed with legal 1263 * TCP/IP or UDP/IP packets. 1264 * ... 1265 * For all other datagrams, hardware parsing must 1266 * be used. 1267 * Software parsing appears to truncate ICMP and 1268 * fragmented UDP packets that contain one to three 1269 * bytes in the second (and final) mbuf of the packet. 1270 */ 1271 if (sc->flags & FXP_FLAG_EXT_RFA) 1272 txp->tx_cb->ipcb_ip_activation_high = 1273 FXP_IPCB_HARDWAREPARSING_ENABLE; 1274 1275 /* 1276 * Deal with TCP/IP checksum offload. Note that 1277 * in order for TCP checksum offload to work, 1278 * the pseudo header checksum must have already 1279 * been computed and stored in the checksum field 1280 * in the TCP header. The stack should have 1281 * already done this for us. 1282 */ 1283 if (m_head->m_pkthdr.csum_flags) { 1284 if (m_head->m_pkthdr.csum_flags & CSUM_DELAY_DATA) { 1285 txp->tx_cb->ipcb_ip_schedule = 1286 FXP_IPCB_TCPUDP_CHECKSUM_ENABLE; 1287 if (m_head->m_pkthdr.csum_flags & CSUM_TCP) 1288 txp->tx_cb->ipcb_ip_schedule |= 1289 FXP_IPCB_TCP_PACKET; 1290 } 1291 1292 #ifdef FXP_IP_CSUM_WAR 1293 /* 1294 * XXX The 82550 chip appears to have trouble 1295 * dealing with IP header checksums in very small 1296 * datagrams, namely fragments from 1 to 3 bytes 1297 * in size. For example, say you want to transmit 1298 * a UDP packet of 1473 bytes. The packet will be 1299 * fragmented over two IP datagrams, the latter 1300 * containing only one byte of data. The 82550 will 1301 * botch the header checksum on the 1-byte fragment. 1302 * As long as the datagram contains 4 or more bytes 1303 * of data, you're ok. 1304 * 1305 * The following code attempts to work around this 1306 * problem: if the datagram is less than 38 bytes 1307 * in size (14 bytes ether header, 20 bytes IP header, 1308 * plus 4 bytes of data), we punt and compute the IP 1309 * header checksum by hand. This workaround doesn't 1310 * work very well, however, since it can be fooled 1311 * by things like VLAN tags and IP options that make 1312 * the header sizes/offsets vary. 1313 */ 1314 1315 if (m_head->m_pkthdr.csum_flags & CSUM_IP) { 1316 if (m_head->m_pkthdr.len < 38) { 1317 struct ip *ip; 1318 m_head->m_data += ETHER_HDR_LEN; 1319 ip = mtod(mb_head, struct ip *); 1320 ip->ip_sum = in_cksum(mb_head, ip->ip_hl << 2); 1321 m_head->m_data -= ETHER_HDR_LEN; 1322 } else { 1323 txp->tx_cb->ipcb_ip_activation_high = 1324 FXP_IPCB_HARDWAREPARSING_ENABLE; 1325 txp->tx_cb->ipcb_ip_schedule |= 1326 FXP_IPCB_IP_CHECKSUM_ENABLE; 1327 } 1328 } 1329 #endif 1330 } 1331 1332 chainlen = 0; 1333 for (m = m_head; m != NULL && chainlen <= sc->maxtxseg; m = m->m_next) 1334 chainlen++; 1335 if (chainlen > sc->maxtxseg) { 1336 struct mbuf *mn; 1337 1338 /* 1339 * We ran out of segments. We have to recopy this 1340 * mbuf chain first. Bail out if we can't get the 1341 * new buffers. 1342 */ 1343 mn = m_defrag(m_head, M_DONTWAIT); 1344 if (mn == NULL) { 1345 m_freem(m_head); 1346 return (-1); 1347 } else { 1348 m_head = mn; 1349 } 1350 } 1351 1352 /* 1353 * Go through each of the mbufs in the chain and initialize 1354 * the transmit buffer descriptors with the physical address 1355 * and size of the mbuf. 1356 */ 1357 error = bus_dmamap_load_mbuf_sg(sc->fxp_mtag, txp->tx_map, 1358 m_head, segs, &nseg, 0); 1359 if (error) { 1360 device_printf(sc->dev, "can't map mbuf (error %d)\n", error); 1361 m_freem(m_head); 1362 return (-1); 1363 } 1364 1365 KASSERT(nseg <= sc->maxtxseg, ("too many DMA segments")); 1366 1367 cbp = txp->tx_cb; 1368 for (i = 0; i < nseg; i++) { 1369 KASSERT(segs[i].ds_len <= MCLBYTES, ("segment size too large")); 1370 /* 1371 * If this is an 82550/82551, then we're using extended 1372 * TxCBs _and_ we're using checksum offload. This means 1373 * that the TxCB is really an IPCB. One major difference 1374 * between the two is that with plain extended TxCBs, 1375 * the bottom half of the TxCB contains two entries from 1376 * the TBD array, whereas IPCBs contain just one entry: 1377 * one entry (8 bytes) has been sacrificed for the TCP/IP 1378 * checksum offload control bits. So to make things work 1379 * right, we have to start filling in the TBD array 1380 * starting from a different place depending on whether 1381 * the chip is an 82550/82551 or not. 1382 */ 1383 if (sc->flags & FXP_FLAG_EXT_RFA) { 1384 cbp->tbd[i + 1].tb_addr = htole32(segs[i].ds_addr); 1385 cbp->tbd[i + 1].tb_size = htole32(segs[i].ds_len); 1386 } else { 1387 cbp->tbd[i].tb_addr = htole32(segs[i].ds_addr); 1388 cbp->tbd[i].tb_size = htole32(segs[i].ds_len); 1389 } 1390 } 1391 cbp->tbd_number = nseg; 1392 1393 bus_dmamap_sync(sc->fxp_mtag, txp->tx_map, BUS_DMASYNC_PREWRITE); 1394 txp->tx_mbuf = m_head; 1395 txp->tx_cb->cb_status = 0; 1396 txp->tx_cb->byte_count = 0; 1397 if (sc->tx_queued != FXP_CXINT_THRESH - 1) { 1398 txp->tx_cb->cb_command = 1399 htole16(sc->tx_cmd | FXP_CB_COMMAND_SF | 1400 FXP_CB_COMMAND_S); 1401 } else { 1402 txp->tx_cb->cb_command = 1403 htole16(sc->tx_cmd | FXP_CB_COMMAND_SF | 1404 FXP_CB_COMMAND_S | FXP_CB_COMMAND_I); 1405 /* 1406 * Set a 5 second timer just in case we don't hear 1407 * from the card again. 1408 */ 1409 ifp->if_timer = 5; 1410 } 1411 txp->tx_cb->tx_threshold = tx_threshold; 1412 1413 /* 1414 * Advance the end of list forward. 1415 */ 1416 1417 #ifdef __alpha__ 1418 /* 1419 * On platforms which can't access memory in 16-bit 1420 * granularities, we must prevent the card from DMA'ing 1421 * up the status while we update the command field. 1422 * This could cause us to overwrite the completion status. 1423 * XXX This is probably bogus and we're _not_ looking 1424 * for atomicity here. 1425 */ 1426 atomic_clear_16(&sc->fxp_desc.tx_last->tx_cb->cb_command, 1427 htole16(FXP_CB_COMMAND_S)); 1428 #else 1429 sc->fxp_desc.tx_last->tx_cb->cb_command &= htole16(~FXP_CB_COMMAND_S); 1430 #endif /*__alpha__*/ 1431 sc->fxp_desc.tx_last = txp; 1432 1433 /* 1434 * Advance the beginning of the list forward if there are 1435 * no other packets queued (when nothing is queued, tx_first 1436 * sits on the last TxCB that was sent out). 1437 */ 1438 if (sc->tx_queued == 0) 1439 sc->fxp_desc.tx_first = txp; 1440 1441 sc->tx_queued++; 1442 1443 /* 1444 * Pass packet to bpf if there is a listener. 1445 */ 1446 BPF_MTAP(ifp, m_head); 1447 return (0); 1448 } 1449 1450 #ifdef DEVICE_POLLING 1451 static poll_handler_t fxp_poll; 1452 1453 static void 1454 fxp_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 1455 { 1456 struct fxp_softc *sc = ifp->if_softc; 1457 uint8_t statack; 1458 1459 FXP_LOCK(sc); 1460 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) { 1461 FXP_UNLOCK(sc); 1462 return; 1463 } 1464 1465 statack = FXP_SCB_STATACK_CXTNO | FXP_SCB_STATACK_CNA | 1466 FXP_SCB_STATACK_FR; 1467 if (cmd == POLL_AND_CHECK_STATUS) { 1468 uint8_t tmp; 1469 1470 tmp = CSR_READ_1(sc, FXP_CSR_SCB_STATACK); 1471 if (tmp == 0xff || tmp == 0) { 1472 FXP_UNLOCK(sc); 1473 return; /* nothing to do */ 1474 } 1475 tmp &= ~statack; 1476 /* ack what we can */ 1477 if (tmp != 0) 1478 CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, tmp); 1479 statack |= tmp; 1480 } 1481 fxp_intr_body(sc, ifp, statack, count); 1482 FXP_UNLOCK(sc); 1483 } 1484 #endif /* DEVICE_POLLING */ 1485 1486 /* 1487 * Process interface interrupts. 1488 */ 1489 static void 1490 fxp_intr(void *xsc) 1491 { 1492 struct fxp_softc *sc = xsc; 1493 struct ifnet *ifp = sc->ifp; 1494 uint8_t statack; 1495 1496 FXP_LOCK(sc); 1497 if (sc->suspended) { 1498 FXP_UNLOCK(sc); 1499 return; 1500 } 1501 1502 #ifdef DEVICE_POLLING 1503 if (ifp->if_capenable & IFCAP_POLLING) { 1504 FXP_UNLOCK(sc); 1505 return; 1506 } 1507 #endif 1508 while ((statack = CSR_READ_1(sc, FXP_CSR_SCB_STATACK)) != 0) { 1509 /* 1510 * It should not be possible to have all bits set; the 1511 * FXP_SCB_INTR_SWI bit always returns 0 on a read. If 1512 * all bits are set, this may indicate that the card has 1513 * been physically ejected, so ignore it. 1514 */ 1515 if (statack == 0xff) { 1516 FXP_UNLOCK(sc); 1517 return; 1518 } 1519 1520 /* 1521 * First ACK all the interrupts in this pass. 1522 */ 1523 CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, statack); 1524 fxp_intr_body(sc, ifp, statack, -1); 1525 } 1526 FXP_UNLOCK(sc); 1527 } 1528 1529 static void 1530 fxp_txeof(struct fxp_softc *sc) 1531 { 1532 struct fxp_tx *txp; 1533 1534 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREREAD); 1535 for (txp = sc->fxp_desc.tx_first; sc->tx_queued && 1536 (le16toh(txp->tx_cb->cb_status) & FXP_CB_STATUS_C) != 0; 1537 txp = txp->tx_next) { 1538 if (txp->tx_mbuf != NULL) { 1539 bus_dmamap_sync(sc->fxp_mtag, txp->tx_map, 1540 BUS_DMASYNC_POSTWRITE); 1541 bus_dmamap_unload(sc->fxp_mtag, txp->tx_map); 1542 m_freem(txp->tx_mbuf); 1543 txp->tx_mbuf = NULL; 1544 /* clear this to reset csum offload bits */ 1545 txp->tx_cb->tbd[0].tb_addr = 0; 1546 } 1547 sc->tx_queued--; 1548 } 1549 sc->fxp_desc.tx_first = txp; 1550 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE); 1551 } 1552 1553 static void 1554 fxp_intr_body(struct fxp_softc *sc, struct ifnet *ifp, uint8_t statack, 1555 int count) 1556 { 1557 struct mbuf *m; 1558 struct fxp_rx *rxp; 1559 struct fxp_rfa *rfa; 1560 int rnr = (statack & FXP_SCB_STATACK_RNR) ? 1 : 0; 1561 int fxp_rc = 0; 1562 1563 FXP_LOCK_ASSERT(sc, MA_OWNED); 1564 if (rnr) 1565 sc->rnr++; 1566 #ifdef DEVICE_POLLING 1567 /* Pick up a deferred RNR condition if `count' ran out last time. */ 1568 if (sc->flags & FXP_FLAG_DEFERRED_RNR) { 1569 sc->flags &= ~FXP_FLAG_DEFERRED_RNR; 1570 rnr = 1; 1571 } 1572 #endif 1573 1574 /* 1575 * Free any finished transmit mbuf chains. 1576 * 1577 * Handle the CNA event likt a CXTNO event. It used to 1578 * be that this event (control unit not ready) was not 1579 * encountered, but it is now with the SMPng modifications. 1580 * The exact sequence of events that occur when the interface 1581 * is brought up are different now, and if this event 1582 * goes unhandled, the configuration/rxfilter setup sequence 1583 * can stall for several seconds. The result is that no 1584 * packets go out onto the wire for about 5 to 10 seconds 1585 * after the interface is ifconfig'ed for the first time. 1586 */ 1587 if (statack & (FXP_SCB_STATACK_CXTNO | FXP_SCB_STATACK_CNA)) { 1588 fxp_txeof(sc); 1589 1590 ifp->if_timer = 0; 1591 if (sc->tx_queued == 0) { 1592 if (sc->need_mcsetup) 1593 fxp_mc_setup(sc); 1594 } 1595 /* 1596 * Try to start more packets transmitting. 1597 */ 1598 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1599 fxp_start_body(ifp); 1600 } 1601 1602 /* 1603 * Just return if nothing happened on the receive side. 1604 */ 1605 if (!rnr && (statack & FXP_SCB_STATACK_FR) == 0) 1606 return; 1607 1608 /* 1609 * Process receiver interrupts. If a no-resource (RNR) 1610 * condition exists, get whatever packets we can and 1611 * re-start the receiver. 1612 * 1613 * When using polling, we do not process the list to completion, 1614 * so when we get an RNR interrupt we must defer the restart 1615 * until we hit the last buffer with the C bit set. 1616 * If we run out of cycles and rfa_headm has the C bit set, 1617 * record the pending RNR in the FXP_FLAG_DEFERRED_RNR flag so 1618 * that the info will be used in the subsequent polling cycle. 1619 */ 1620 for (;;) { 1621 rxp = sc->fxp_desc.rx_head; 1622 m = rxp->rx_mbuf; 1623 rfa = (struct fxp_rfa *)(m->m_ext.ext_buf + 1624 RFA_ALIGNMENT_FUDGE); 1625 bus_dmamap_sync(sc->fxp_mtag, rxp->rx_map, 1626 BUS_DMASYNC_POSTREAD); 1627 1628 #ifdef DEVICE_POLLING /* loop at most count times if count >=0 */ 1629 if (count >= 0 && count-- == 0) { 1630 if (rnr) { 1631 /* Defer RNR processing until the next time. */ 1632 sc->flags |= FXP_FLAG_DEFERRED_RNR; 1633 rnr = 0; 1634 } 1635 break; 1636 } 1637 #endif /* DEVICE_POLLING */ 1638 1639 if ((le16toh(rfa->rfa_status) & FXP_RFA_STATUS_C) == 0) 1640 break; 1641 1642 /* 1643 * Advance head forward. 1644 */ 1645 sc->fxp_desc.rx_head = rxp->rx_next; 1646 1647 /* 1648 * Add a new buffer to the receive chain. 1649 * If this fails, the old buffer is recycled 1650 * instead. 1651 */ 1652 fxp_rc = fxp_add_rfabuf(sc, rxp); 1653 if (fxp_rc == 0) { 1654 int total_len; 1655 1656 /* 1657 * Fetch packet length (the top 2 bits of 1658 * actual_size are flags set by the controller 1659 * upon completion), and drop the packet in case 1660 * of bogus length or CRC errors. 1661 */ 1662 total_len = le16toh(rfa->actual_size) & 0x3fff; 1663 if (total_len < sizeof(struct ether_header) || 1664 total_len > MCLBYTES - RFA_ALIGNMENT_FUDGE - 1665 sc->rfa_size || 1666 le16toh(rfa->rfa_status) & FXP_RFA_STATUS_CRC) { 1667 m_freem(m); 1668 continue; 1669 } 1670 1671 /* Do IP checksum checking. */ 1672 if (le16toh(rfa->rfa_status) & FXP_RFA_STATUS_PARSE) { 1673 if (rfa->rfax_csum_sts & 1674 FXP_RFDX_CS_IP_CSUM_BIT_VALID) 1675 m->m_pkthdr.csum_flags |= 1676 CSUM_IP_CHECKED; 1677 if (rfa->rfax_csum_sts & 1678 FXP_RFDX_CS_IP_CSUM_VALID) 1679 m->m_pkthdr.csum_flags |= 1680 CSUM_IP_VALID; 1681 if ((rfa->rfax_csum_sts & 1682 FXP_RFDX_CS_TCPUDP_CSUM_BIT_VALID) && 1683 (rfa->rfax_csum_sts & 1684 FXP_RFDX_CS_TCPUDP_CSUM_VALID)) { 1685 m->m_pkthdr.csum_flags |= 1686 CSUM_DATA_VALID|CSUM_PSEUDO_HDR; 1687 m->m_pkthdr.csum_data = 0xffff; 1688 } 1689 } 1690 1691 m->m_pkthdr.len = m->m_len = total_len; 1692 m->m_pkthdr.rcvif = ifp; 1693 1694 /* 1695 * Drop locks before calling if_input() since it 1696 * may re-enter fxp_start() in the netisr case. 1697 * This would result in a lock reversal. Better 1698 * performance might be obtained by chaining all 1699 * packets received, dropping the lock, and then 1700 * calling if_input() on each one. 1701 */ 1702 FXP_UNLOCK(sc); 1703 (*ifp->if_input)(ifp, m); 1704 FXP_LOCK(sc); 1705 } else if (fxp_rc == ENOBUFS) { 1706 rnr = 0; 1707 break; 1708 } 1709 } 1710 if (rnr) { 1711 fxp_scb_wait(sc); 1712 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 1713 sc->fxp_desc.rx_head->rx_addr); 1714 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_START); 1715 } 1716 } 1717 1718 /* 1719 * Update packet in/out/collision statistics. The i82557 doesn't 1720 * allow you to access these counters without doing a fairly 1721 * expensive DMA to get _all_ of the statistics it maintains, so 1722 * we do this operation here only once per second. The statistics 1723 * counters in the kernel are updated from the previous dump-stats 1724 * DMA and then a new dump-stats DMA is started. The on-chip 1725 * counters are zeroed when the DMA completes. If we can't start 1726 * the DMA immediately, we don't wait - we just prepare to read 1727 * them again next time. 1728 */ 1729 static void 1730 fxp_tick(void *xsc) 1731 { 1732 struct fxp_softc *sc = xsc; 1733 struct ifnet *ifp = sc->ifp; 1734 struct fxp_stats *sp = sc->fxp_stats; 1735 1736 FXP_LOCK_ASSERT(sc, MA_OWNED); 1737 bus_dmamap_sync(sc->fxp_stag, sc->fxp_smap, BUS_DMASYNC_POSTREAD); 1738 ifp->if_opackets += le32toh(sp->tx_good); 1739 ifp->if_collisions += le32toh(sp->tx_total_collisions); 1740 if (sp->rx_good) { 1741 ifp->if_ipackets += le32toh(sp->rx_good); 1742 sc->rx_idle_secs = 0; 1743 } else { 1744 /* 1745 * Receiver's been idle for another second. 1746 */ 1747 sc->rx_idle_secs++; 1748 } 1749 ifp->if_ierrors += 1750 le32toh(sp->rx_crc_errors) + 1751 le32toh(sp->rx_alignment_errors) + 1752 le32toh(sp->rx_rnr_errors) + 1753 le32toh(sp->rx_overrun_errors); 1754 /* 1755 * If any transmit underruns occured, bump up the transmit 1756 * threshold by another 512 bytes (64 * 8). 1757 */ 1758 if (sp->tx_underruns) { 1759 ifp->if_oerrors += le32toh(sp->tx_underruns); 1760 if (tx_threshold < 192) 1761 tx_threshold += 64; 1762 } 1763 1764 /* 1765 * Release any xmit buffers that have completed DMA. This isn't 1766 * strictly necessary to do here, but it's advantagous for mbufs 1767 * with external storage to be released in a timely manner rather 1768 * than being defered for a potentially long time. This limits 1769 * the delay to a maximum of one second. 1770 */ 1771 fxp_txeof(sc); 1772 1773 /* 1774 * If we haven't received any packets in FXP_MAC_RX_IDLE seconds, 1775 * then assume the receiver has locked up and attempt to clear 1776 * the condition by reprogramming the multicast filter. This is 1777 * a work-around for a bug in the 82557 where the receiver locks 1778 * up if it gets certain types of garbage in the syncronization 1779 * bits prior to the packet header. This bug is supposed to only 1780 * occur in 10Mbps mode, but has been seen to occur in 100Mbps 1781 * mode as well (perhaps due to a 10/100 speed transition). 1782 */ 1783 if (sc->rx_idle_secs > FXP_MAX_RX_IDLE) { 1784 sc->rx_idle_secs = 0; 1785 fxp_mc_setup(sc); 1786 } 1787 /* 1788 * If there is no pending command, start another stats 1789 * dump. Otherwise punt for now. 1790 */ 1791 if (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) == 0) { 1792 /* 1793 * Start another stats dump. 1794 */ 1795 bus_dmamap_sync(sc->fxp_stag, sc->fxp_smap, 1796 BUS_DMASYNC_PREREAD); 1797 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_DUMPRESET); 1798 } else { 1799 /* 1800 * A previous command is still waiting to be accepted. 1801 * Just zero our copy of the stats and wait for the 1802 * next timer event to update them. 1803 */ 1804 sp->tx_good = 0; 1805 sp->tx_underruns = 0; 1806 sp->tx_total_collisions = 0; 1807 1808 sp->rx_good = 0; 1809 sp->rx_crc_errors = 0; 1810 sp->rx_alignment_errors = 0; 1811 sp->rx_rnr_errors = 0; 1812 sp->rx_overrun_errors = 0; 1813 } 1814 if (sc->miibus != NULL) 1815 mii_tick(device_get_softc(sc->miibus)); 1816 1817 /* 1818 * Schedule another timeout one second from now. 1819 */ 1820 callout_reset(&sc->stat_ch, hz, fxp_tick, sc); 1821 } 1822 1823 /* 1824 * Stop the interface. Cancels the statistics updater and resets 1825 * the interface. 1826 */ 1827 static void 1828 fxp_stop(struct fxp_softc *sc) 1829 { 1830 struct ifnet *ifp = sc->ifp; 1831 struct fxp_tx *txp; 1832 int i; 1833 1834 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 1835 ifp->if_timer = 0; 1836 1837 /* 1838 * Cancel stats updater. 1839 */ 1840 callout_stop(&sc->stat_ch); 1841 1842 /* 1843 * Issue software reset, which also unloads the microcode. 1844 */ 1845 sc->flags &= ~FXP_FLAG_UCODE; 1846 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SOFTWARE_RESET); 1847 DELAY(50); 1848 1849 /* 1850 * Release any xmit buffers. 1851 */ 1852 txp = sc->fxp_desc.tx_list; 1853 if (txp != NULL) { 1854 for (i = 0; i < FXP_NTXCB; i++) { 1855 if (txp[i].tx_mbuf != NULL) { 1856 bus_dmamap_sync(sc->fxp_mtag, txp[i].tx_map, 1857 BUS_DMASYNC_POSTWRITE); 1858 bus_dmamap_unload(sc->fxp_mtag, txp[i].tx_map); 1859 m_freem(txp[i].tx_mbuf); 1860 txp[i].tx_mbuf = NULL; 1861 /* clear this to reset csum offload bits */ 1862 txp[i].tx_cb->tbd[0].tb_addr = 0; 1863 } 1864 } 1865 } 1866 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE); 1867 sc->tx_queued = 0; 1868 } 1869 1870 /* 1871 * Watchdog/transmission transmit timeout handler. Called when a 1872 * transmission is started on the interface, but no interrupt is 1873 * received before the timeout. This usually indicates that the 1874 * card has wedged for some reason. 1875 */ 1876 static void 1877 fxp_watchdog(struct ifnet *ifp) 1878 { 1879 struct fxp_softc *sc = ifp->if_softc; 1880 1881 FXP_LOCK(sc); 1882 device_printf(sc->dev, "device timeout\n"); 1883 ifp->if_oerrors++; 1884 1885 fxp_init_body(sc); 1886 FXP_UNLOCK(sc); 1887 } 1888 1889 /* 1890 * Acquire locks and then call the real initialization function. This 1891 * is necessary because ether_ioctl() calls if_init() and this would 1892 * result in mutex recursion if the mutex was held. 1893 */ 1894 static void 1895 fxp_init(void *xsc) 1896 { 1897 struct fxp_softc *sc = xsc; 1898 1899 FXP_LOCK(sc); 1900 fxp_init_body(sc); 1901 FXP_UNLOCK(sc); 1902 } 1903 1904 /* 1905 * Perform device initialization. This routine must be called with the 1906 * softc lock held. 1907 */ 1908 static void 1909 fxp_init_body(struct fxp_softc *sc) 1910 { 1911 struct ifnet *ifp = sc->ifp; 1912 struct fxp_cb_config *cbp; 1913 struct fxp_cb_ias *cb_ias; 1914 struct fxp_cb_tx *tcbp; 1915 struct fxp_tx *txp; 1916 struct fxp_cb_mcs *mcsp; 1917 int i, prm; 1918 1919 FXP_LOCK_ASSERT(sc, MA_OWNED); 1920 /* 1921 * Cancel any pending I/O 1922 */ 1923 fxp_stop(sc); 1924 1925 prm = (ifp->if_flags & IFF_PROMISC) ? 1 : 0; 1926 1927 /* 1928 * Initialize base of CBL and RFA memory. Loading with zero 1929 * sets it up for regular linear addressing. 1930 */ 1931 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 0); 1932 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_BASE); 1933 1934 fxp_scb_wait(sc); 1935 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_BASE); 1936 1937 /* 1938 * Initialize base of dump-stats buffer. 1939 */ 1940 fxp_scb_wait(sc); 1941 bus_dmamap_sync(sc->fxp_stag, sc->fxp_smap, BUS_DMASYNC_PREREAD); 1942 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->stats_addr); 1943 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_DUMP_ADR); 1944 1945 /* 1946 * Attempt to load microcode if requested. 1947 */ 1948 if (ifp->if_flags & IFF_LINK0 && (sc->flags & FXP_FLAG_UCODE) == 0) 1949 fxp_load_ucode(sc); 1950 1951 /* 1952 * Initialize the multicast address list. 1953 */ 1954 if (fxp_mc_addrs(sc)) { 1955 mcsp = sc->mcsp; 1956 mcsp->cb_status = 0; 1957 mcsp->cb_command = 1958 htole16(FXP_CB_COMMAND_MCAS | FXP_CB_COMMAND_EL); 1959 mcsp->link_addr = 0xffffffff; 1960 /* 1961 * Start the multicast setup command. 1962 */ 1963 fxp_scb_wait(sc); 1964 bus_dmamap_sync(sc->mcs_tag, sc->mcs_map, BUS_DMASYNC_PREWRITE); 1965 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->mcs_addr); 1966 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 1967 /* ...and wait for it to complete. */ 1968 fxp_dma_wait(sc, &mcsp->cb_status, sc->mcs_tag, sc->mcs_map); 1969 bus_dmamap_sync(sc->mcs_tag, sc->mcs_map, 1970 BUS_DMASYNC_POSTWRITE); 1971 } 1972 1973 /* 1974 * We temporarily use memory that contains the TxCB list to 1975 * construct the config CB. The TxCB list memory is rebuilt 1976 * later. 1977 */ 1978 cbp = (struct fxp_cb_config *)sc->fxp_desc.cbl_list; 1979 1980 /* 1981 * This bcopy is kind of disgusting, but there are a bunch of must be 1982 * zero and must be one bits in this structure and this is the easiest 1983 * way to initialize them all to proper values. 1984 */ 1985 bcopy(fxp_cb_config_template, cbp, sizeof(fxp_cb_config_template)); 1986 1987 cbp->cb_status = 0; 1988 cbp->cb_command = htole16(FXP_CB_COMMAND_CONFIG | 1989 FXP_CB_COMMAND_EL); 1990 cbp->link_addr = 0xffffffff; /* (no) next command */ 1991 cbp->byte_count = sc->flags & FXP_FLAG_EXT_RFA ? 32 : 22; 1992 cbp->rx_fifo_limit = 8; /* rx fifo threshold (32 bytes) */ 1993 cbp->tx_fifo_limit = 0; /* tx fifo threshold (0 bytes) */ 1994 cbp->adaptive_ifs = 0; /* (no) adaptive interframe spacing */ 1995 cbp->mwi_enable = sc->flags & FXP_FLAG_MWI_ENABLE ? 1 : 0; 1996 cbp->type_enable = 0; /* actually reserved */ 1997 cbp->read_align_en = sc->flags & FXP_FLAG_READ_ALIGN ? 1 : 0; 1998 cbp->end_wr_on_cl = sc->flags & FXP_FLAG_WRITE_ALIGN ? 1 : 0; 1999 cbp->rx_dma_bytecount = 0; /* (no) rx DMA max */ 2000 cbp->tx_dma_bytecount = 0; /* (no) tx DMA max */ 2001 cbp->dma_mbce = 0; /* (disable) dma max counters */ 2002 cbp->late_scb = 0; /* (don't) defer SCB update */ 2003 cbp->direct_dma_dis = 1; /* disable direct rcv dma mode */ 2004 cbp->tno_int_or_tco_en =0; /* (disable) tx not okay interrupt */ 2005 cbp->ci_int = 1; /* interrupt on CU idle */ 2006 cbp->ext_txcb_dis = sc->flags & FXP_FLAG_EXT_TXCB ? 0 : 1; 2007 cbp->ext_stats_dis = 1; /* disable extended counters */ 2008 cbp->keep_overrun_rx = 0; /* don't pass overrun frames to host */ 2009 cbp->save_bf = sc->flags & FXP_FLAG_SAVE_BAD ? 1 : prm; 2010 cbp->disc_short_rx = !prm; /* discard short packets */ 2011 cbp->underrun_retry = 1; /* retry mode (once) on DMA underrun */ 2012 cbp->two_frames = 0; /* do not limit FIFO to 2 frames */ 2013 cbp->dyn_tbd = 0; /* (no) dynamic TBD mode */ 2014 cbp->ext_rfa = sc->flags & FXP_FLAG_EXT_RFA ? 1 : 0; 2015 cbp->mediatype = sc->flags & FXP_FLAG_SERIAL_MEDIA ? 0 : 1; 2016 cbp->csma_dis = 0; /* (don't) disable link */ 2017 cbp->tcp_udp_cksum = 0; /* (don't) enable checksum */ 2018 cbp->vlan_tco = 0; /* (don't) enable vlan wakeup */ 2019 cbp->link_wake_en = 0; /* (don't) assert PME# on link change */ 2020 cbp->arp_wake_en = 0; /* (don't) assert PME# on arp */ 2021 cbp->mc_wake_en = 0; /* (don't) enable PME# on mcmatch */ 2022 cbp->nsai = 1; /* (don't) disable source addr insert */ 2023 cbp->preamble_length = 2; /* (7 byte) preamble */ 2024 cbp->loopback = 0; /* (don't) loopback */ 2025 cbp->linear_priority = 0; /* (normal CSMA/CD operation) */ 2026 cbp->linear_pri_mode = 0; /* (wait after xmit only) */ 2027 cbp->interfrm_spacing = 6; /* (96 bits of) interframe spacing */ 2028 cbp->promiscuous = prm; /* promiscuous mode */ 2029 cbp->bcast_disable = 0; /* (don't) disable broadcasts */ 2030 cbp->wait_after_win = 0; /* (don't) enable modified backoff alg*/ 2031 cbp->ignore_ul = 0; /* consider U/L bit in IA matching */ 2032 cbp->crc16_en = 0; /* (don't) enable crc-16 algorithm */ 2033 cbp->crscdt = sc->flags & FXP_FLAG_SERIAL_MEDIA ? 1 : 0; 2034 2035 cbp->stripping = !prm; /* truncate rx packet to byte count */ 2036 cbp->padding = 1; /* (do) pad short tx packets */ 2037 cbp->rcv_crc_xfer = 0; /* (don't) xfer CRC to host */ 2038 cbp->long_rx_en = sc->flags & FXP_FLAG_LONG_PKT_EN ? 1 : 0; 2039 cbp->ia_wake_en = 0; /* (don't) wake up on address match */ 2040 cbp->magic_pkt_dis = 0; /* (don't) disable magic packet */ 2041 /* must set wake_en in PMCSR also */ 2042 cbp->force_fdx = 0; /* (don't) force full duplex */ 2043 cbp->fdx_pin_en = 1; /* (enable) FDX# pin */ 2044 cbp->multi_ia = 0; /* (don't) accept multiple IAs */ 2045 cbp->mc_all = sc->flags & FXP_FLAG_ALL_MCAST ? 1 : 0; 2046 cbp->gamla_rx = sc->flags & FXP_FLAG_EXT_RFA ? 1 : 0; 2047 2048 if (sc->tunable_noflow || sc->revision == FXP_REV_82557) { 2049 /* 2050 * The 82557 has no hardware flow control, the values 2051 * below are the defaults for the chip. 2052 */ 2053 cbp->fc_delay_lsb = 0; 2054 cbp->fc_delay_msb = 0x40; 2055 cbp->pri_fc_thresh = 3; 2056 cbp->tx_fc_dis = 0; 2057 cbp->rx_fc_restop = 0; 2058 cbp->rx_fc_restart = 0; 2059 cbp->fc_filter = 0; 2060 cbp->pri_fc_loc = 1; 2061 } else { 2062 cbp->fc_delay_lsb = 0x1f; 2063 cbp->fc_delay_msb = 0x01; 2064 cbp->pri_fc_thresh = 3; 2065 cbp->tx_fc_dis = 0; /* enable transmit FC */ 2066 cbp->rx_fc_restop = 1; /* enable FC restop frames */ 2067 cbp->rx_fc_restart = 1; /* enable FC restart frames */ 2068 cbp->fc_filter = !prm; /* drop FC frames to host */ 2069 cbp->pri_fc_loc = 1; /* FC pri location (byte31) */ 2070 } 2071 2072 /* 2073 * Start the config command/DMA. 2074 */ 2075 fxp_scb_wait(sc); 2076 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE); 2077 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->fxp_desc.cbl_addr); 2078 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2079 /* ...and wait for it to complete. */ 2080 fxp_dma_wait(sc, &cbp->cb_status, sc->cbl_tag, sc->cbl_map); 2081 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_POSTWRITE); 2082 2083 /* 2084 * Now initialize the station address. Temporarily use the TxCB 2085 * memory area like we did above for the config CB. 2086 */ 2087 cb_ias = (struct fxp_cb_ias *)sc->fxp_desc.cbl_list; 2088 cb_ias->cb_status = 0; 2089 cb_ias->cb_command = htole16(FXP_CB_COMMAND_IAS | FXP_CB_COMMAND_EL); 2090 cb_ias->link_addr = 0xffffffff; 2091 bcopy(IF_LLADDR(sc->ifp), cb_ias->macaddr, ETHER_ADDR_LEN); 2092 2093 /* 2094 * Start the IAS (Individual Address Setup) command/DMA. 2095 */ 2096 fxp_scb_wait(sc); 2097 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE); 2098 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2099 /* ...and wait for it to complete. */ 2100 fxp_dma_wait(sc, &cb_ias->cb_status, sc->cbl_tag, sc->cbl_map); 2101 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_POSTWRITE); 2102 2103 /* 2104 * Initialize transmit control block (TxCB) list. 2105 */ 2106 txp = sc->fxp_desc.tx_list; 2107 tcbp = sc->fxp_desc.cbl_list; 2108 bzero(tcbp, FXP_TXCB_SZ); 2109 for (i = 0; i < FXP_NTXCB; i++) { 2110 txp[i].tx_mbuf = NULL; 2111 tcbp[i].cb_status = htole16(FXP_CB_STATUS_C | FXP_CB_STATUS_OK); 2112 tcbp[i].cb_command = htole16(FXP_CB_COMMAND_NOP); 2113 tcbp[i].link_addr = htole32(sc->fxp_desc.cbl_addr + 2114 (((i + 1) & FXP_TXCB_MASK) * sizeof(struct fxp_cb_tx))); 2115 if (sc->flags & FXP_FLAG_EXT_TXCB) 2116 tcbp[i].tbd_array_addr = 2117 htole32(FXP_TXCB_DMA_ADDR(sc, &tcbp[i].tbd[2])); 2118 else 2119 tcbp[i].tbd_array_addr = 2120 htole32(FXP_TXCB_DMA_ADDR(sc, &tcbp[i].tbd[0])); 2121 txp[i].tx_next = &txp[(i + 1) & FXP_TXCB_MASK]; 2122 } 2123 /* 2124 * Set the suspend flag on the first TxCB and start the control 2125 * unit. It will execute the NOP and then suspend. 2126 */ 2127 tcbp->cb_command = htole16(FXP_CB_COMMAND_NOP | FXP_CB_COMMAND_S); 2128 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE); 2129 sc->fxp_desc.tx_first = sc->fxp_desc.tx_last = txp; 2130 sc->tx_queued = 1; 2131 2132 fxp_scb_wait(sc); 2133 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2134 2135 /* 2136 * Initialize receiver buffer area - RFA. 2137 */ 2138 fxp_scb_wait(sc); 2139 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->fxp_desc.rx_head->rx_addr); 2140 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_START); 2141 2142 /* 2143 * Set current media. 2144 */ 2145 if (sc->miibus != NULL) 2146 mii_mediachg(device_get_softc(sc->miibus)); 2147 2148 ifp->if_drv_flags |= IFF_DRV_RUNNING; 2149 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 2150 2151 /* 2152 * Enable interrupts. 2153 */ 2154 #ifdef DEVICE_POLLING 2155 /* 2156 * ... but only do that if we are not polling. And because (presumably) 2157 * the default is interrupts on, we need to disable them explicitly! 2158 */ 2159 if (ifp->if_capenable & IFCAP_POLLING ) 2160 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE); 2161 else 2162 #endif /* DEVICE_POLLING */ 2163 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, 0); 2164 2165 /* 2166 * Start stats updater. 2167 */ 2168 callout_reset(&sc->stat_ch, hz, fxp_tick, sc); 2169 } 2170 2171 static int 2172 fxp_serial_ifmedia_upd(struct ifnet *ifp) 2173 { 2174 2175 return (0); 2176 } 2177 2178 static void 2179 fxp_serial_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 2180 { 2181 2182 ifmr->ifm_active = IFM_ETHER|IFM_MANUAL; 2183 } 2184 2185 /* 2186 * Change media according to request. 2187 */ 2188 static int 2189 fxp_ifmedia_upd(struct ifnet *ifp) 2190 { 2191 struct fxp_softc *sc = ifp->if_softc; 2192 struct mii_data *mii; 2193 2194 mii = device_get_softc(sc->miibus); 2195 FXP_LOCK(sc); 2196 mii_mediachg(mii); 2197 FXP_UNLOCK(sc); 2198 return (0); 2199 } 2200 2201 /* 2202 * Notify the world which media we're using. 2203 */ 2204 static void 2205 fxp_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 2206 { 2207 struct fxp_softc *sc = ifp->if_softc; 2208 struct mii_data *mii; 2209 2210 mii = device_get_softc(sc->miibus); 2211 FXP_LOCK(sc); 2212 mii_pollstat(mii); 2213 ifmr->ifm_active = mii->mii_media_active; 2214 ifmr->ifm_status = mii->mii_media_status; 2215 2216 if (IFM_SUBTYPE(ifmr->ifm_active) == IFM_10_T && 2217 sc->flags & FXP_FLAG_CU_RESUME_BUG) 2218 sc->cu_resume_bug = 1; 2219 else 2220 sc->cu_resume_bug = 0; 2221 FXP_UNLOCK(sc); 2222 } 2223 2224 /* 2225 * Add a buffer to the end of the RFA buffer list. 2226 * Return 0 if successful, 1 for failure. A failure results in 2227 * adding the 'oldm' (if non-NULL) on to the end of the list - 2228 * tossing out its old contents and recycling it. 2229 * The RFA struct is stuck at the beginning of mbuf cluster and the 2230 * data pointer is fixed up to point just past it. 2231 */ 2232 static int 2233 fxp_add_rfabuf(struct fxp_softc *sc, struct fxp_rx *rxp) 2234 { 2235 struct mbuf *m; 2236 struct fxp_rfa *rfa, *p_rfa; 2237 struct fxp_rx *p_rx; 2238 bus_dmamap_t tmp_map; 2239 int error; 2240 2241 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 2242 if (m == NULL) 2243 return (ENOBUFS); 2244 2245 /* 2246 * Move the data pointer up so that the incoming data packet 2247 * will be 32-bit aligned. 2248 */ 2249 m->m_data += RFA_ALIGNMENT_FUDGE; 2250 2251 /* 2252 * Get a pointer to the base of the mbuf cluster and move 2253 * data start past it. 2254 */ 2255 rfa = mtod(m, struct fxp_rfa *); 2256 m->m_data += sc->rfa_size; 2257 rfa->size = htole16(MCLBYTES - sc->rfa_size - RFA_ALIGNMENT_FUDGE); 2258 2259 rfa->rfa_status = 0; 2260 rfa->rfa_control = htole16(FXP_RFA_CONTROL_EL); 2261 rfa->actual_size = 0; 2262 2263 /* 2264 * Initialize the rest of the RFA. Note that since the RFA 2265 * is misaligned, we cannot store values directly. We're thus 2266 * using the le32enc() function which handles endianness and 2267 * is also alignment-safe. 2268 */ 2269 le32enc(&rfa->link_addr, 0xffffffff); 2270 le32enc(&rfa->rbd_addr, 0xffffffff); 2271 2272 /* Map the RFA into DMA memory. */ 2273 error = bus_dmamap_load(sc->fxp_mtag, sc->spare_map, rfa, 2274 MCLBYTES - RFA_ALIGNMENT_FUDGE, fxp_dma_map_addr, 2275 &rxp->rx_addr, 0); 2276 if (error) { 2277 m_freem(m); 2278 return (error); 2279 } 2280 2281 bus_dmamap_unload(sc->fxp_mtag, rxp->rx_map); 2282 tmp_map = sc->spare_map; 2283 sc->spare_map = rxp->rx_map; 2284 rxp->rx_map = tmp_map; 2285 rxp->rx_mbuf = m; 2286 2287 bus_dmamap_sync(sc->fxp_mtag, rxp->rx_map, 2288 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2289 2290 /* 2291 * If there are other buffers already on the list, attach this 2292 * one to the end by fixing up the tail to point to this one. 2293 */ 2294 if (sc->fxp_desc.rx_head != NULL) { 2295 p_rx = sc->fxp_desc.rx_tail; 2296 p_rfa = (struct fxp_rfa *) 2297 (p_rx->rx_mbuf->m_ext.ext_buf + RFA_ALIGNMENT_FUDGE); 2298 p_rx->rx_next = rxp; 2299 le32enc(&p_rfa->link_addr, rxp->rx_addr); 2300 p_rfa->rfa_control = 0; 2301 bus_dmamap_sync(sc->fxp_mtag, p_rx->rx_map, 2302 BUS_DMASYNC_PREWRITE); 2303 } else { 2304 rxp->rx_next = NULL; 2305 sc->fxp_desc.rx_head = rxp; 2306 } 2307 sc->fxp_desc.rx_tail = rxp; 2308 return (0); 2309 } 2310 2311 static volatile int 2312 fxp_miibus_readreg(device_t dev, int phy, int reg) 2313 { 2314 struct fxp_softc *sc = device_get_softc(dev); 2315 int count = 10000; 2316 int value; 2317 2318 CSR_WRITE_4(sc, FXP_CSR_MDICONTROL, 2319 (FXP_MDI_READ << 26) | (reg << 16) | (phy << 21)); 2320 2321 while (((value = CSR_READ_4(sc, FXP_CSR_MDICONTROL)) & 0x10000000) == 0 2322 && count--) 2323 DELAY(10); 2324 2325 if (count <= 0) 2326 device_printf(dev, "fxp_miibus_readreg: timed out\n"); 2327 2328 return (value & 0xffff); 2329 } 2330 2331 static void 2332 fxp_miibus_writereg(device_t dev, int phy, int reg, int value) 2333 { 2334 struct fxp_softc *sc = device_get_softc(dev); 2335 int count = 10000; 2336 2337 CSR_WRITE_4(sc, FXP_CSR_MDICONTROL, 2338 (FXP_MDI_WRITE << 26) | (reg << 16) | (phy << 21) | 2339 (value & 0xffff)); 2340 2341 while ((CSR_READ_4(sc, FXP_CSR_MDICONTROL) & 0x10000000) == 0 && 2342 count--) 2343 DELAY(10); 2344 2345 if (count <= 0) 2346 device_printf(dev, "fxp_miibus_writereg: timed out\n"); 2347 } 2348 2349 static int 2350 fxp_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 2351 { 2352 struct fxp_softc *sc = ifp->if_softc; 2353 struct ifreq *ifr = (struct ifreq *)data; 2354 struct mii_data *mii; 2355 int flag, mask, error = 0; 2356 2357 switch (command) { 2358 case SIOCSIFFLAGS: 2359 FXP_LOCK(sc); 2360 if (ifp->if_flags & IFF_ALLMULTI) 2361 sc->flags |= FXP_FLAG_ALL_MCAST; 2362 else 2363 sc->flags &= ~FXP_FLAG_ALL_MCAST; 2364 2365 /* 2366 * If interface is marked up and not running, then start it. 2367 * If it is marked down and running, stop it. 2368 * XXX If it's up then re-initialize it. This is so flags 2369 * such as IFF_PROMISC are handled. 2370 */ 2371 if (ifp->if_flags & IFF_UP) { 2372 fxp_init_body(sc); 2373 } else { 2374 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 2375 fxp_stop(sc); 2376 } 2377 FXP_UNLOCK(sc); 2378 break; 2379 2380 case SIOCADDMULTI: 2381 case SIOCDELMULTI: 2382 FXP_LOCK(sc); 2383 if (ifp->if_flags & IFF_ALLMULTI) 2384 sc->flags |= FXP_FLAG_ALL_MCAST; 2385 else 2386 sc->flags &= ~FXP_FLAG_ALL_MCAST; 2387 /* 2388 * Multicast list has changed; set the hardware filter 2389 * accordingly. 2390 */ 2391 if ((sc->flags & FXP_FLAG_ALL_MCAST) == 0) 2392 fxp_mc_setup(sc); 2393 /* 2394 * fxp_mc_setup() can set FXP_FLAG_ALL_MCAST, so check it 2395 * again rather than else {}. 2396 */ 2397 if (sc->flags & FXP_FLAG_ALL_MCAST) 2398 fxp_init_body(sc); 2399 FXP_UNLOCK(sc); 2400 error = 0; 2401 break; 2402 2403 case SIOCSIFMEDIA: 2404 case SIOCGIFMEDIA: 2405 if (sc->miibus != NULL) { 2406 mii = device_get_softc(sc->miibus); 2407 error = ifmedia_ioctl(ifp, ifr, 2408 &mii->mii_media, command); 2409 } else { 2410 error = ifmedia_ioctl(ifp, ifr, &sc->sc_media, command); 2411 } 2412 break; 2413 2414 case SIOCSIFCAP: 2415 mask = ifp->if_capenable ^ ifr->ifr_reqcap; 2416 #ifdef DEVICE_POLLING 2417 if (mask & IFCAP_POLLING) { 2418 if (ifr->ifr_reqcap & IFCAP_POLLING) { 2419 error = ether_poll_register(fxp_poll, ifp); 2420 if (error) 2421 return(error); 2422 FXP_LOCK(sc); 2423 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, 2424 FXP_SCB_INTR_DISABLE); 2425 ifp->if_capenable |= IFCAP_POLLING; 2426 FXP_UNLOCK(sc); 2427 } else { 2428 error = ether_poll_deregister(ifp); 2429 /* Enable interrupts in any case */ 2430 FXP_LOCK(sc); 2431 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, 0); 2432 ifp->if_capenable &= ~IFCAP_POLLING; 2433 FXP_UNLOCK(sc); 2434 } 2435 } 2436 #endif 2437 if (mask & IFCAP_VLAN_MTU) { 2438 FXP_LOCK(sc); 2439 ifp->if_capenable ^= IFCAP_VLAN_MTU; 2440 if (sc->revision != FXP_REV_82557) 2441 flag = FXP_FLAG_LONG_PKT_EN; 2442 else /* a hack to get long frames on the old chip */ 2443 flag = FXP_FLAG_SAVE_BAD; 2444 sc->flags ^= flag; 2445 if (ifp->if_flags & IFF_UP) 2446 fxp_init_body(sc); 2447 FXP_UNLOCK(sc); 2448 } 2449 break; 2450 2451 default: 2452 error = ether_ioctl(ifp, command, data); 2453 } 2454 return (error); 2455 } 2456 2457 /* 2458 * Fill in the multicast address list and return number of entries. 2459 */ 2460 static int 2461 fxp_mc_addrs(struct fxp_softc *sc) 2462 { 2463 struct fxp_cb_mcs *mcsp = sc->mcsp; 2464 struct ifnet *ifp = sc->ifp; 2465 struct ifmultiaddr *ifma; 2466 int nmcasts; 2467 2468 nmcasts = 0; 2469 if ((sc->flags & FXP_FLAG_ALL_MCAST) == 0) { 2470 IF_ADDR_LOCK(ifp); 2471 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 2472 if (ifma->ifma_addr->sa_family != AF_LINK) 2473 continue; 2474 if (nmcasts >= MAXMCADDR) { 2475 sc->flags |= FXP_FLAG_ALL_MCAST; 2476 nmcasts = 0; 2477 break; 2478 } 2479 bcopy(LLADDR((struct sockaddr_dl *)ifma->ifma_addr), 2480 &sc->mcsp->mc_addr[nmcasts][0], ETHER_ADDR_LEN); 2481 nmcasts++; 2482 } 2483 IF_ADDR_UNLOCK(ifp); 2484 } 2485 mcsp->mc_cnt = htole16(nmcasts * ETHER_ADDR_LEN); 2486 return (nmcasts); 2487 } 2488 2489 /* 2490 * Program the multicast filter. 2491 * 2492 * We have an artificial restriction that the multicast setup command 2493 * must be the first command in the chain, so we take steps to ensure 2494 * this. By requiring this, it allows us to keep up the performance of 2495 * the pre-initialized command ring (esp. link pointers) by not actually 2496 * inserting the mcsetup command in the ring - i.e. its link pointer 2497 * points to the TxCB ring, but the mcsetup descriptor itself is not part 2498 * of it. We then can do 'CU_START' on the mcsetup descriptor and have it 2499 * lead into the regular TxCB ring when it completes. 2500 * 2501 * This function must be called at splimp. 2502 */ 2503 static void 2504 fxp_mc_setup(struct fxp_softc *sc) 2505 { 2506 struct fxp_cb_mcs *mcsp = sc->mcsp; 2507 struct ifnet *ifp = sc->ifp; 2508 struct fxp_tx *txp; 2509 int count; 2510 2511 FXP_LOCK_ASSERT(sc, MA_OWNED); 2512 /* 2513 * If there are queued commands, we must wait until they are all 2514 * completed. If we are already waiting, then add a NOP command 2515 * with interrupt option so that we're notified when all commands 2516 * have been completed - fxp_start() ensures that no additional 2517 * TX commands will be added when need_mcsetup is true. 2518 */ 2519 if (sc->tx_queued) { 2520 /* 2521 * need_mcsetup will be true if we are already waiting for the 2522 * NOP command to be completed (see below). In this case, bail. 2523 */ 2524 if (sc->need_mcsetup) 2525 return; 2526 sc->need_mcsetup = 1; 2527 2528 /* 2529 * Add a NOP command with interrupt so that we are notified 2530 * when all TX commands have been processed. 2531 */ 2532 txp = sc->fxp_desc.tx_last->tx_next; 2533 txp->tx_mbuf = NULL; 2534 txp->tx_cb->cb_status = 0; 2535 txp->tx_cb->cb_command = htole16(FXP_CB_COMMAND_NOP | 2536 FXP_CB_COMMAND_S | FXP_CB_COMMAND_I); 2537 /* 2538 * Advance the end of list forward. 2539 */ 2540 sc->fxp_desc.tx_last->tx_cb->cb_command &= 2541 htole16(~FXP_CB_COMMAND_S); 2542 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE); 2543 sc->fxp_desc.tx_last = txp; 2544 sc->tx_queued++; 2545 /* 2546 * Issue a resume in case the CU has just suspended. 2547 */ 2548 fxp_scb_wait(sc); 2549 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_RESUME); 2550 /* 2551 * Set a 5 second timer just in case we don't hear from the 2552 * card again. 2553 */ 2554 ifp->if_timer = 5; 2555 2556 return; 2557 } 2558 sc->need_mcsetup = 0; 2559 2560 /* 2561 * Initialize multicast setup descriptor. 2562 */ 2563 mcsp->cb_status = 0; 2564 mcsp->cb_command = htole16(FXP_CB_COMMAND_MCAS | 2565 FXP_CB_COMMAND_S | FXP_CB_COMMAND_I); 2566 mcsp->link_addr = htole32(sc->fxp_desc.cbl_addr); 2567 txp = &sc->fxp_desc.mcs_tx; 2568 txp->tx_mbuf = NULL; 2569 txp->tx_cb = (struct fxp_cb_tx *)sc->mcsp; 2570 txp->tx_next = sc->fxp_desc.tx_list; 2571 (void) fxp_mc_addrs(sc); 2572 sc->fxp_desc.tx_first = sc->fxp_desc.tx_last = txp; 2573 sc->tx_queued = 1; 2574 2575 /* 2576 * Wait until command unit is not active. This should never 2577 * be the case when nothing is queued, but make sure anyway. 2578 */ 2579 count = 100; 2580 while ((CSR_READ_1(sc, FXP_CSR_SCB_RUSCUS) >> 6) == 2581 FXP_SCB_CUS_ACTIVE && --count) 2582 DELAY(10); 2583 if (count == 0) { 2584 device_printf(sc->dev, "command queue timeout\n"); 2585 return; 2586 } 2587 2588 /* 2589 * Start the multicast setup command. 2590 */ 2591 fxp_scb_wait(sc); 2592 bus_dmamap_sync(sc->mcs_tag, sc->mcs_map, BUS_DMASYNC_PREWRITE); 2593 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->mcs_addr); 2594 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2595 2596 ifp->if_timer = 2; 2597 return; 2598 } 2599 2600 static uint32_t fxp_ucode_d101a[] = D101_A_RCVBUNDLE_UCODE; 2601 static uint32_t fxp_ucode_d101b0[] = D101_B0_RCVBUNDLE_UCODE; 2602 static uint32_t fxp_ucode_d101ma[] = D101M_B_RCVBUNDLE_UCODE; 2603 static uint32_t fxp_ucode_d101s[] = D101S_RCVBUNDLE_UCODE; 2604 static uint32_t fxp_ucode_d102[] = D102_B_RCVBUNDLE_UCODE; 2605 static uint32_t fxp_ucode_d102c[] = D102_C_RCVBUNDLE_UCODE; 2606 static uint32_t fxp_ucode_d102e[] = D102_E_RCVBUNDLE_UCODE; 2607 2608 #define UCODE(x) x, sizeof(x)/sizeof(uint32_t) 2609 2610 struct ucode { 2611 uint32_t revision; 2612 uint32_t *ucode; 2613 int length; 2614 u_short int_delay_offset; 2615 u_short bundle_max_offset; 2616 } ucode_table[] = { 2617 { FXP_REV_82558_A4, UCODE(fxp_ucode_d101a), D101_CPUSAVER_DWORD, 0 }, 2618 { FXP_REV_82558_B0, UCODE(fxp_ucode_d101b0), D101_CPUSAVER_DWORD, 0 }, 2619 { FXP_REV_82559_A0, UCODE(fxp_ucode_d101ma), 2620 D101M_CPUSAVER_DWORD, D101M_CPUSAVER_BUNDLE_MAX_DWORD }, 2621 { FXP_REV_82559S_A, UCODE(fxp_ucode_d101s), 2622 D101S_CPUSAVER_DWORD, D101S_CPUSAVER_BUNDLE_MAX_DWORD }, 2623 { FXP_REV_82550, UCODE(fxp_ucode_d102), 2624 D102_B_CPUSAVER_DWORD, D102_B_CPUSAVER_BUNDLE_MAX_DWORD }, 2625 { FXP_REV_82550_C, UCODE(fxp_ucode_d102c), 2626 D102_C_CPUSAVER_DWORD, D102_C_CPUSAVER_BUNDLE_MAX_DWORD }, 2627 { FXP_REV_82551_F, UCODE(fxp_ucode_d102e), 2628 D102_E_CPUSAVER_DWORD, D102_E_CPUSAVER_BUNDLE_MAX_DWORD }, 2629 { 0, NULL, 0, 0, 0 } 2630 }; 2631 2632 static void 2633 fxp_load_ucode(struct fxp_softc *sc) 2634 { 2635 struct ucode *uc; 2636 struct fxp_cb_ucode *cbp; 2637 int i; 2638 2639 for (uc = ucode_table; uc->ucode != NULL; uc++) 2640 if (sc->revision == uc->revision) 2641 break; 2642 if (uc->ucode == NULL) 2643 return; 2644 cbp = (struct fxp_cb_ucode *)sc->fxp_desc.cbl_list; 2645 cbp->cb_status = 0; 2646 cbp->cb_command = htole16(FXP_CB_COMMAND_UCODE | FXP_CB_COMMAND_EL); 2647 cbp->link_addr = 0xffffffff; /* (no) next command */ 2648 for (i = 0; i < uc->length; i++) 2649 cbp->ucode[i] = htole32(uc->ucode[i]); 2650 if (uc->int_delay_offset) 2651 *(uint16_t *)&cbp->ucode[uc->int_delay_offset] = 2652 htole16(sc->tunable_int_delay + sc->tunable_int_delay / 2); 2653 if (uc->bundle_max_offset) 2654 *(uint16_t *)&cbp->ucode[uc->bundle_max_offset] = 2655 htole16(sc->tunable_bundle_max); 2656 /* 2657 * Download the ucode to the chip. 2658 */ 2659 fxp_scb_wait(sc); 2660 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE); 2661 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->fxp_desc.cbl_addr); 2662 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2663 /* ...and wait for it to complete. */ 2664 fxp_dma_wait(sc, &cbp->cb_status, sc->cbl_tag, sc->cbl_map); 2665 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_POSTWRITE); 2666 device_printf(sc->dev, 2667 "Microcode loaded, int_delay: %d usec bundle_max: %d\n", 2668 sc->tunable_int_delay, 2669 uc->bundle_max_offset == 0 ? 0 : sc->tunable_bundle_max); 2670 sc->flags |= FXP_FLAG_UCODE; 2671 } 2672 2673 static int 2674 sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high) 2675 { 2676 int error, value; 2677 2678 value = *(int *)arg1; 2679 error = sysctl_handle_int(oidp, &value, 0, req); 2680 if (error || !req->newptr) 2681 return (error); 2682 if (value < low || value > high) 2683 return (EINVAL); 2684 *(int *)arg1 = value; 2685 return (0); 2686 } 2687 2688 /* 2689 * Interrupt delay is expressed in microseconds, a multiplier is used 2690 * to convert this to the appropriate clock ticks before using. 2691 */ 2692 static int 2693 sysctl_hw_fxp_int_delay(SYSCTL_HANDLER_ARGS) 2694 { 2695 return (sysctl_int_range(oidp, arg1, arg2, req, 300, 3000)); 2696 } 2697 2698 static int 2699 sysctl_hw_fxp_bundle_max(SYSCTL_HANDLER_ARGS) 2700 { 2701 return (sysctl_int_range(oidp, arg1, arg2, req, 1, 0xffff)); 2702 } 2703