1 /*- 2 * Copyright (c) 1995, David Greenman 3 * Copyright (c) 2001 Jonathan Lemon <jlemon@freebsd.org> 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice unmodified, this list of conditions, and the following 11 * disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 * 28 */ 29 30 #include <sys/cdefs.h> 31 __FBSDID("$FreeBSD$"); 32 33 /* 34 * Intel EtherExpress Pro/100B PCI Fast Ethernet driver 35 */ 36 37 #include <sys/param.h> 38 #include <sys/systm.h> 39 #include <sys/endian.h> 40 #include <sys/mbuf.h> 41 /* #include <sys/mutex.h> */ 42 #include <sys/kernel.h> 43 #include <sys/module.h> 44 #include <sys/socket.h> 45 #include <sys/sysctl.h> 46 47 #include <net/if.h> 48 #include <net/if_dl.h> 49 #include <net/if_media.h> 50 51 #include <net/bpf.h> 52 #include <sys/sockio.h> 53 #include <sys/bus.h> 54 #include <machine/bus.h> 55 #include <sys/rman.h> 56 #include <machine/resource.h> 57 58 #include <net/ethernet.h> 59 #include <net/if_arp.h> 60 61 #include <machine/clock.h> /* for DELAY */ 62 63 #include <net/if_types.h> 64 #include <net/if_vlan_var.h> 65 66 #ifdef FXP_IP_CSUM_WAR 67 #include <netinet/in.h> 68 #include <netinet/in_systm.h> 69 #include <netinet/ip.h> 70 #include <machine/in_cksum.h> 71 #endif 72 73 #include <dev/pci/pcivar.h> 74 #include <dev/pci/pcireg.h> /* for PCIM_CMD_xxx */ 75 76 #include <dev/mii/mii.h> 77 #include <dev/mii/miivar.h> 78 79 #include <dev/fxp/if_fxpreg.h> 80 #include <dev/fxp/if_fxpvar.h> 81 #include <dev/fxp/rcvbundl.h> 82 83 MODULE_DEPEND(fxp, pci, 1, 1, 1); 84 MODULE_DEPEND(fxp, ether, 1, 1, 1); 85 MODULE_DEPEND(fxp, miibus, 1, 1, 1); 86 #include "miibus_if.h" 87 88 /* 89 * NOTE! On the Alpha, we have an alignment constraint. The 90 * card DMAs the packet immediately following the RFA. However, 91 * the first thing in the packet is a 14-byte Ethernet header. 92 * This means that the packet is misaligned. To compensate, 93 * we actually offset the RFA 2 bytes into the cluster. This 94 * alignes the packet after the Ethernet header at a 32-bit 95 * boundary. HOWEVER! This means that the RFA is misaligned! 96 */ 97 #define RFA_ALIGNMENT_FUDGE 2 98 99 /* 100 * Set initial transmit threshold at 64 (512 bytes). This is 101 * increased by 64 (512 bytes) at a time, to maximum of 192 102 * (1536 bytes), if an underrun occurs. 103 */ 104 static int tx_threshold = 64; 105 106 /* 107 * The configuration byte map has several undefined fields which 108 * must be one or must be zero. Set up a template for these bits 109 * only, (assuming a 82557 chip) leaving the actual configuration 110 * to fxp_init. 111 * 112 * See struct fxp_cb_config for the bit definitions. 113 */ 114 static u_char fxp_cb_config_template[] = { 115 0x0, 0x0, /* cb_status */ 116 0x0, 0x0, /* cb_command */ 117 0x0, 0x0, 0x0, 0x0, /* link_addr */ 118 0x0, /* 0 */ 119 0x0, /* 1 */ 120 0x0, /* 2 */ 121 0x0, /* 3 */ 122 0x0, /* 4 */ 123 0x0, /* 5 */ 124 0x32, /* 6 */ 125 0x0, /* 7 */ 126 0x0, /* 8 */ 127 0x0, /* 9 */ 128 0x6, /* 10 */ 129 0x0, /* 11 */ 130 0x0, /* 12 */ 131 0x0, /* 13 */ 132 0xf2, /* 14 */ 133 0x48, /* 15 */ 134 0x0, /* 16 */ 135 0x40, /* 17 */ 136 0xf0, /* 18 */ 137 0x0, /* 19 */ 138 0x3f, /* 20 */ 139 0x5 /* 21 */ 140 }; 141 142 struct fxp_ident { 143 uint16_t devid; 144 int16_t revid; /* -1 matches anything */ 145 char *name; 146 }; 147 148 /* 149 * Claim various Intel PCI device identifiers for this driver. The 150 * sub-vendor and sub-device field are extensively used to identify 151 * particular variants, but we don't currently differentiate between 152 * them. 153 */ 154 static struct fxp_ident fxp_ident_table[] = { 155 { 0x1029, -1, "Intel 82559 PCI/CardBus Pro/100" }, 156 { 0x1030, -1, "Intel 82559 Pro/100 Ethernet" }, 157 { 0x1031, -1, "Intel 82801CAM (ICH3) Pro/100 VE Ethernet" }, 158 { 0x1032, -1, "Intel 82801CAM (ICH3) Pro/100 VE Ethernet" }, 159 { 0x1033, -1, "Intel 82801CAM (ICH3) Pro/100 VM Ethernet" }, 160 { 0x1034, -1, "Intel 82801CAM (ICH3) Pro/100 VM Ethernet" }, 161 { 0x1035, -1, "Intel 82801CAM (ICH3) Pro/100 Ethernet" }, 162 { 0x1036, -1, "Intel 82801CAM (ICH3) Pro/100 Ethernet" }, 163 { 0x1037, -1, "Intel 82801CAM (ICH3) Pro/100 Ethernet" }, 164 { 0x1038, -1, "Intel 82801CAM (ICH3) Pro/100 VM Ethernet" }, 165 { 0x1039, -1, "Intel 82801DB (ICH4) Pro/100 VE Ethernet" }, 166 { 0x103A, -1, "Intel 82801DB (ICH4) Pro/100 Ethernet" }, 167 { 0x103B, -1, "Intel 82801DB (ICH4) Pro/100 VM Ethernet" }, 168 { 0x103C, -1, "Intel 82801DB (ICH4) Pro/100 Ethernet" }, 169 { 0x103D, -1, "Intel 82801DB (ICH4) Pro/100 VE Ethernet" }, 170 { 0x103E, -1, "Intel 82801DB (ICH4) Pro/100 VM Ethernet" }, 171 { 0x1050, -1, "Intel 82801BA (D865) Pro/100 VE Ethernet" }, 172 { 0x1051, -1, "Intel 82562ET (ICH5/ICH5R) Pro/100 VE Ethernet" }, 173 { 0x1059, -1, "Intel 82551QM Pro/100 M Mobile Connection" }, 174 { 0x1064, -1, "Intel 82562EZ (ICH6)" }, 175 { 0x1068, -1, "Intel 82801FBM (ICH6-M) Pro/100 VE Ethernet" }, 176 { 0x1209, -1, "Intel 82559ER Embedded 10/100 Ethernet" }, 177 { 0x1229, 0x01, "Intel 82557 Pro/100 Ethernet" }, 178 { 0x1229, 0x02, "Intel 82557 Pro/100 Ethernet" }, 179 { 0x1229, 0x03, "Intel 82557 Pro/100 Ethernet" }, 180 { 0x1229, 0x04, "Intel 82558 Pro/100 Ethernet" }, 181 { 0x1229, 0x05, "Intel 82558 Pro/100 Ethernet" }, 182 { 0x1229, 0x06, "Intel 82559 Pro/100 Ethernet" }, 183 { 0x1229, 0x07, "Intel 82559 Pro/100 Ethernet" }, 184 { 0x1229, 0x08, "Intel 82559 Pro/100 Ethernet" }, 185 { 0x1229, 0x09, "Intel 82559ER Pro/100 Ethernet" }, 186 { 0x1229, 0x0c, "Intel 82550 Pro/100 Ethernet" }, 187 { 0x1229, 0x0d, "Intel 82550 Pro/100 Ethernet" }, 188 { 0x1229, 0x0e, "Intel 82550 Pro/100 Ethernet" }, 189 { 0x1229, 0x0f, "Intel 82551 Pro/100 Ethernet" }, 190 { 0x1229, 0x10, "Intel 82551 Pro/100 Ethernet" }, 191 { 0x1229, -1, "Intel 82557/8/9 Pro/100 Ethernet" }, 192 { 0x2449, -1, "Intel 82801BA/CAM (ICH2/3) Pro/100 Ethernet" }, 193 { 0, -1, NULL }, 194 }; 195 196 #ifdef FXP_IP_CSUM_WAR 197 #define FXP_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 198 #else 199 #define FXP_CSUM_FEATURES (CSUM_TCP | CSUM_UDP) 200 #endif 201 202 static int fxp_probe(device_t dev); 203 static int fxp_attach(device_t dev); 204 static int fxp_detach(device_t dev); 205 static int fxp_shutdown(device_t dev); 206 static int fxp_suspend(device_t dev); 207 static int fxp_resume(device_t dev); 208 209 static void fxp_intr(void *xsc); 210 static void fxp_intr_body(struct fxp_softc *sc, struct ifnet *ifp, 211 uint8_t statack, int count); 212 static void fxp_init(void *xsc); 213 static void fxp_init_body(struct fxp_softc *sc); 214 static void fxp_tick(void *xsc); 215 static void fxp_start(struct ifnet *ifp); 216 static void fxp_start_body(struct ifnet *ifp); 217 static int fxp_encap(struct fxp_softc *sc, struct mbuf *m_head); 218 static void fxp_stop(struct fxp_softc *sc); 219 static void fxp_release(struct fxp_softc *sc); 220 static int fxp_ioctl(struct ifnet *ifp, u_long command, 221 caddr_t data); 222 static void fxp_watchdog(struct ifnet *ifp); 223 static int fxp_add_rfabuf(struct fxp_softc *sc, 224 struct fxp_rx *rxp); 225 static int fxp_mc_addrs(struct fxp_softc *sc); 226 static void fxp_mc_setup(struct fxp_softc *sc); 227 static uint16_t fxp_eeprom_getword(struct fxp_softc *sc, int offset, 228 int autosize); 229 static void fxp_eeprom_putword(struct fxp_softc *sc, int offset, 230 uint16_t data); 231 static void fxp_autosize_eeprom(struct fxp_softc *sc); 232 static void fxp_read_eeprom(struct fxp_softc *sc, u_short *data, 233 int offset, int words); 234 static void fxp_write_eeprom(struct fxp_softc *sc, u_short *data, 235 int offset, int words); 236 static int fxp_ifmedia_upd(struct ifnet *ifp); 237 static void fxp_ifmedia_sts(struct ifnet *ifp, 238 struct ifmediareq *ifmr); 239 static int fxp_serial_ifmedia_upd(struct ifnet *ifp); 240 static void fxp_serial_ifmedia_sts(struct ifnet *ifp, 241 struct ifmediareq *ifmr); 242 static volatile int fxp_miibus_readreg(device_t dev, int phy, int reg); 243 static void fxp_miibus_writereg(device_t dev, int phy, int reg, 244 int value); 245 static void fxp_load_ucode(struct fxp_softc *sc); 246 static int sysctl_int_range(SYSCTL_HANDLER_ARGS, 247 int low, int high); 248 static int sysctl_hw_fxp_bundle_max(SYSCTL_HANDLER_ARGS); 249 static int sysctl_hw_fxp_int_delay(SYSCTL_HANDLER_ARGS); 250 static void fxp_scb_wait(struct fxp_softc *sc); 251 static void fxp_scb_cmd(struct fxp_softc *sc, int cmd); 252 static void fxp_dma_wait(struct fxp_softc *sc, 253 volatile uint16_t *status, bus_dma_tag_t dmat, 254 bus_dmamap_t map); 255 256 static device_method_t fxp_methods[] = { 257 /* Device interface */ 258 DEVMETHOD(device_probe, fxp_probe), 259 DEVMETHOD(device_attach, fxp_attach), 260 DEVMETHOD(device_detach, fxp_detach), 261 DEVMETHOD(device_shutdown, fxp_shutdown), 262 DEVMETHOD(device_suspend, fxp_suspend), 263 DEVMETHOD(device_resume, fxp_resume), 264 265 /* MII interface */ 266 DEVMETHOD(miibus_readreg, fxp_miibus_readreg), 267 DEVMETHOD(miibus_writereg, fxp_miibus_writereg), 268 269 { 0, 0 } 270 }; 271 272 static driver_t fxp_driver = { 273 "fxp", 274 fxp_methods, 275 sizeof(struct fxp_softc), 276 }; 277 278 static devclass_t fxp_devclass; 279 280 DRIVER_MODULE(fxp, pci, fxp_driver, fxp_devclass, 0, 0); 281 DRIVER_MODULE(fxp, cardbus, fxp_driver, fxp_devclass, 0, 0); 282 DRIVER_MODULE(miibus, fxp, miibus_driver, miibus_devclass, 0, 0); 283 284 /* 285 * Wait for the previous command to be accepted (but not necessarily 286 * completed). 287 */ 288 static void 289 fxp_scb_wait(struct fxp_softc *sc) 290 { 291 int i = 10000; 292 293 while (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) && --i) 294 DELAY(2); 295 if (i == 0) 296 device_printf(sc->dev, "SCB timeout: 0x%x 0x%x 0x%x 0x%x\n", 297 CSR_READ_1(sc, FXP_CSR_SCB_COMMAND), 298 CSR_READ_1(sc, FXP_CSR_SCB_STATACK), 299 CSR_READ_1(sc, FXP_CSR_SCB_RUSCUS), 300 CSR_READ_2(sc, FXP_CSR_FLOWCONTROL)); 301 } 302 303 static void 304 fxp_scb_cmd(struct fxp_softc *sc, int cmd) 305 { 306 307 if (cmd == FXP_SCB_COMMAND_CU_RESUME && sc->cu_resume_bug) { 308 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_CB_COMMAND_NOP); 309 fxp_scb_wait(sc); 310 } 311 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, cmd); 312 } 313 314 static void 315 fxp_dma_wait(struct fxp_softc *sc, volatile uint16_t *status, 316 bus_dma_tag_t dmat, bus_dmamap_t map) 317 { 318 int i = 10000; 319 320 bus_dmamap_sync(dmat, map, BUS_DMASYNC_POSTREAD); 321 while (!(le16toh(*status) & FXP_CB_STATUS_C) && --i) { 322 DELAY(2); 323 bus_dmamap_sync(dmat, map, BUS_DMASYNC_POSTREAD); 324 } 325 if (i == 0) 326 device_printf(sc->dev, "DMA timeout\n"); 327 } 328 329 /* 330 * Return identification string if this device is ours. 331 */ 332 static int 333 fxp_probe(device_t dev) 334 { 335 uint16_t devid; 336 uint8_t revid; 337 struct fxp_ident *ident; 338 339 if (pci_get_vendor(dev) == FXP_VENDORID_INTEL) { 340 devid = pci_get_device(dev); 341 revid = pci_get_revid(dev); 342 for (ident = fxp_ident_table; ident->name != NULL; ident++) { 343 if (ident->devid == devid && 344 (ident->revid == revid || ident->revid == -1)) { 345 device_set_desc(dev, ident->name); 346 return (BUS_PROBE_DEFAULT); 347 } 348 } 349 } 350 return (ENXIO); 351 } 352 353 static void 354 fxp_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error) 355 { 356 uint32_t *addr; 357 358 if (error) 359 return; 360 361 KASSERT(nseg == 1, ("too many DMA segments, %d should be 1", nseg)); 362 addr = arg; 363 *addr = segs->ds_addr; 364 } 365 366 static int 367 fxp_attach(device_t dev) 368 { 369 struct fxp_softc *sc; 370 struct fxp_cb_tx *tcbp; 371 struct fxp_tx *txp; 372 struct fxp_rx *rxp; 373 struct ifnet *ifp; 374 uint32_t val; 375 uint16_t data, myea[ETHER_ADDR_LEN / 2]; 376 int i, rid, m1, m2, prefer_iomap; 377 int error, s; 378 379 error = 0; 380 sc = device_get_softc(dev); 381 sc->dev = dev; 382 callout_init(&sc->stat_ch, CALLOUT_MPSAFE); 383 mtx_init(&sc->sc_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 384 MTX_DEF); 385 ifmedia_init(&sc->sc_media, 0, fxp_serial_ifmedia_upd, 386 fxp_serial_ifmedia_sts); 387 388 s = splimp(); 389 390 /* 391 * Enable bus mastering. 392 */ 393 pci_enable_busmaster(dev); 394 val = pci_read_config(dev, PCIR_COMMAND, 2); 395 396 /* 397 * Figure out which we should try first - memory mapping or i/o mapping? 398 * We default to memory mapping. Then we accept an override from the 399 * command line. Then we check to see which one is enabled. 400 */ 401 m1 = PCIM_CMD_MEMEN; 402 m2 = PCIM_CMD_PORTEN; 403 prefer_iomap = 0; 404 if (resource_int_value(device_get_name(dev), device_get_unit(dev), 405 "prefer_iomap", &prefer_iomap) == 0 && prefer_iomap != 0) { 406 m1 = PCIM_CMD_PORTEN; 407 m2 = PCIM_CMD_MEMEN; 408 } 409 410 sc->rtp = (m1 == PCIM_CMD_MEMEN)? SYS_RES_MEMORY : SYS_RES_IOPORT; 411 sc->rgd = (m1 == PCIM_CMD_MEMEN)? FXP_PCI_MMBA : FXP_PCI_IOBA; 412 sc->mem = bus_alloc_resource_any(dev, sc->rtp, &sc->rgd, RF_ACTIVE); 413 if (sc->mem == NULL) { 414 sc->rtp = 415 (m2 == PCIM_CMD_MEMEN)? SYS_RES_MEMORY : SYS_RES_IOPORT; 416 sc->rgd = (m2 == PCIM_CMD_MEMEN)? FXP_PCI_MMBA : FXP_PCI_IOBA; 417 sc->mem = bus_alloc_resource_any(dev, sc->rtp, &sc->rgd, 418 RF_ACTIVE); 419 } 420 421 if (!sc->mem) { 422 error = ENXIO; 423 goto fail; 424 } 425 if (bootverbose) { 426 device_printf(dev, "using %s space register mapping\n", 427 sc->rtp == SYS_RES_MEMORY? "memory" : "I/O"); 428 } 429 430 sc->sc_st = rman_get_bustag(sc->mem); 431 sc->sc_sh = rman_get_bushandle(sc->mem); 432 433 /* 434 * Allocate our interrupt. 435 */ 436 rid = 0; 437 sc->irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 438 RF_SHAREABLE | RF_ACTIVE); 439 if (sc->irq == NULL) { 440 device_printf(dev, "could not map interrupt\n"); 441 error = ENXIO; 442 goto fail; 443 } 444 445 /* 446 * Reset to a stable state. 447 */ 448 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET); 449 DELAY(10); 450 451 /* 452 * Find out how large of an SEEPROM we have. 453 */ 454 fxp_autosize_eeprom(sc); 455 456 /* 457 * Find out the chip revision; lump all 82557 revs together. 458 */ 459 fxp_read_eeprom(sc, &data, 5, 1); 460 if ((data >> 8) == 1) 461 sc->revision = FXP_REV_82557; 462 else 463 sc->revision = pci_get_revid(dev); 464 465 /* 466 * Determine whether we must use the 503 serial interface. 467 */ 468 fxp_read_eeprom(sc, &data, 6, 1); 469 if (sc->revision == FXP_REV_82557 && (data & FXP_PHY_DEVICE_MASK) != 0 470 && (data & FXP_PHY_SERIAL_ONLY)) 471 sc->flags |= FXP_FLAG_SERIAL_MEDIA; 472 473 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 474 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 475 OID_AUTO, "int_delay", CTLTYPE_INT | CTLFLAG_RW, 476 &sc->tunable_int_delay, 0, sysctl_hw_fxp_int_delay, "I", 477 "FXP driver receive interrupt microcode bundling delay"); 478 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 479 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 480 OID_AUTO, "bundle_max", CTLTYPE_INT | CTLFLAG_RW, 481 &sc->tunable_bundle_max, 0, sysctl_hw_fxp_bundle_max, "I", 482 "FXP driver receive interrupt microcode bundle size limit"); 483 SYSCTL_ADD_INT(device_get_sysctl_ctx(dev), 484 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 485 OID_AUTO, "rnr", CTLFLAG_RD, &sc->rnr, 0, 486 "FXP RNR events"); 487 SYSCTL_ADD_INT(device_get_sysctl_ctx(dev), 488 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 489 OID_AUTO, "noflow", CTLFLAG_RW, &sc->tunable_noflow, 0, 490 "FXP flow control disabled"); 491 492 /* 493 * Pull in device tunables. 494 */ 495 sc->tunable_int_delay = TUNABLE_INT_DELAY; 496 sc->tunable_bundle_max = TUNABLE_BUNDLE_MAX; 497 sc->tunable_noflow = 1; 498 (void) resource_int_value(device_get_name(dev), device_get_unit(dev), 499 "int_delay", &sc->tunable_int_delay); 500 (void) resource_int_value(device_get_name(dev), device_get_unit(dev), 501 "bundle_max", &sc->tunable_bundle_max); 502 (void) resource_int_value(device_get_name(dev), device_get_unit(dev), 503 "noflow", &sc->tunable_noflow); 504 sc->rnr = 0; 505 506 /* 507 * Enable workarounds for certain chip revision deficiencies. 508 * 509 * Systems based on the ICH2/ICH2-M chip from Intel, and possibly 510 * some systems based a normal 82559 design, have a defect where 511 * the chip can cause a PCI protocol violation if it receives 512 * a CU_RESUME command when it is entering the IDLE state. The 513 * workaround is to disable Dynamic Standby Mode, so the chip never 514 * deasserts CLKRUN#, and always remains in an active state. 515 * 516 * See Intel 82801BA/82801BAM Specification Update, Errata #30. 517 */ 518 i = pci_get_device(dev); 519 if (i == 0x2449 || (i > 0x1030 && i < 0x1039) || 520 sc->revision >= FXP_REV_82559_A0) { 521 fxp_read_eeprom(sc, &data, 10, 1); 522 if (data & 0x02) { /* STB enable */ 523 uint16_t cksum; 524 int i; 525 526 device_printf(dev, 527 "Disabling dynamic standby mode in EEPROM\n"); 528 data &= ~0x02; 529 fxp_write_eeprom(sc, &data, 10, 1); 530 device_printf(dev, "New EEPROM ID: 0x%x\n", data); 531 cksum = 0; 532 for (i = 0; i < (1 << sc->eeprom_size) - 1; i++) { 533 fxp_read_eeprom(sc, &data, i, 1); 534 cksum += data; 535 } 536 i = (1 << sc->eeprom_size) - 1; 537 cksum = 0xBABA - cksum; 538 fxp_read_eeprom(sc, &data, i, 1); 539 fxp_write_eeprom(sc, &cksum, i, 1); 540 device_printf(dev, 541 "EEPROM checksum @ 0x%x: 0x%x -> 0x%x\n", 542 i, data, cksum); 543 #if 1 544 /* 545 * If the user elects to continue, try the software 546 * workaround, as it is better than nothing. 547 */ 548 sc->flags |= FXP_FLAG_CU_RESUME_BUG; 549 #endif 550 } 551 } 552 553 /* 554 * If we are not a 82557 chip, we can enable extended features. 555 */ 556 if (sc->revision != FXP_REV_82557) { 557 /* 558 * If MWI is enabled in the PCI configuration, and there 559 * is a valid cacheline size (8 or 16 dwords), then tell 560 * the board to turn on MWI. 561 */ 562 if (val & PCIM_CMD_MWRICEN && 563 pci_read_config(dev, PCIR_CACHELNSZ, 1) != 0) 564 sc->flags |= FXP_FLAG_MWI_ENABLE; 565 566 /* turn on the extended TxCB feature */ 567 sc->flags |= FXP_FLAG_EXT_TXCB; 568 569 /* enable reception of long frames for VLAN */ 570 sc->flags |= FXP_FLAG_LONG_PKT_EN; 571 } else { 572 /* a hack to get long VLAN frames on a 82557 */ 573 sc->flags |= FXP_FLAG_SAVE_BAD; 574 } 575 576 /* 577 * Enable use of extended RFDs and TCBs for 82550 578 * and later chips. Note: we need extended TXCB support 579 * too, but that's already enabled by the code above. 580 * Be careful to do this only on the right devices. 581 */ 582 if (sc->revision == FXP_REV_82550 || sc->revision == FXP_REV_82550_C || 583 sc->revision == FXP_REV_82551_E || sc->revision == FXP_REV_82551_F 584 || sc->revision == FXP_REV_82551_10) { 585 sc->rfa_size = sizeof (struct fxp_rfa); 586 sc->tx_cmd = FXP_CB_COMMAND_IPCBXMIT; 587 sc->flags |= FXP_FLAG_EXT_RFA; 588 } else { 589 sc->rfa_size = sizeof (struct fxp_rfa) - FXP_RFAX_LEN; 590 sc->tx_cmd = FXP_CB_COMMAND_XMIT; 591 } 592 593 /* 594 * Allocate DMA tags and DMA safe memory. 595 */ 596 sc->maxtxseg = FXP_NTXSEG; 597 if (sc->flags & FXP_FLAG_EXT_RFA) 598 sc->maxtxseg--; 599 error = bus_dma_tag_create(NULL, 2, 0, BUS_SPACE_MAXADDR_32BIT, 600 BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES * sc->maxtxseg, 601 sc->maxtxseg, MCLBYTES, 0, busdma_lock_mutex, &Giant, 602 &sc->fxp_mtag); 603 if (error) { 604 device_printf(dev, "could not allocate dma tag\n"); 605 goto fail; 606 } 607 608 error = bus_dma_tag_create(NULL, 4, 0, BUS_SPACE_MAXADDR_32BIT, 609 BUS_SPACE_MAXADDR, NULL, NULL, sizeof(struct fxp_stats), 1, 610 sizeof(struct fxp_stats), 0, busdma_lock_mutex, &Giant, 611 &sc->fxp_stag); 612 if (error) { 613 device_printf(dev, "could not allocate dma tag\n"); 614 goto fail; 615 } 616 617 error = bus_dmamem_alloc(sc->fxp_stag, (void **)&sc->fxp_stats, 618 BUS_DMA_NOWAIT | BUS_DMA_ZERO, &sc->fxp_smap); 619 if (error) 620 goto fail; 621 error = bus_dmamap_load(sc->fxp_stag, sc->fxp_smap, sc->fxp_stats, 622 sizeof(struct fxp_stats), fxp_dma_map_addr, &sc->stats_addr, 0); 623 if (error) { 624 device_printf(dev, "could not map the stats buffer\n"); 625 goto fail; 626 } 627 628 error = bus_dma_tag_create(NULL, 4, 0, BUS_SPACE_MAXADDR_32BIT, 629 BUS_SPACE_MAXADDR, NULL, NULL, FXP_TXCB_SZ, 1, 630 FXP_TXCB_SZ, 0, busdma_lock_mutex, &Giant, &sc->cbl_tag); 631 if (error) { 632 device_printf(dev, "could not allocate dma tag\n"); 633 goto fail; 634 } 635 636 error = bus_dmamem_alloc(sc->cbl_tag, (void **)&sc->fxp_desc.cbl_list, 637 BUS_DMA_NOWAIT | BUS_DMA_ZERO, &sc->cbl_map); 638 if (error) 639 goto fail; 640 641 error = bus_dmamap_load(sc->cbl_tag, sc->cbl_map, 642 sc->fxp_desc.cbl_list, FXP_TXCB_SZ, fxp_dma_map_addr, 643 &sc->fxp_desc.cbl_addr, 0); 644 if (error) { 645 device_printf(dev, "could not map DMA memory\n"); 646 goto fail; 647 } 648 649 error = bus_dma_tag_create(NULL, 4, 0, BUS_SPACE_MAXADDR_32BIT, 650 BUS_SPACE_MAXADDR, NULL, NULL, sizeof(struct fxp_cb_mcs), 1, 651 sizeof(struct fxp_cb_mcs), 0, busdma_lock_mutex, &Giant, 652 &sc->mcs_tag); 653 if (error) { 654 device_printf(dev, "could not allocate dma tag\n"); 655 goto fail; 656 } 657 658 error = bus_dmamem_alloc(sc->mcs_tag, (void **)&sc->mcsp, 659 BUS_DMA_NOWAIT, &sc->mcs_map); 660 if (error) 661 goto fail; 662 error = bus_dmamap_load(sc->mcs_tag, sc->mcs_map, sc->mcsp, 663 sizeof(struct fxp_cb_mcs), fxp_dma_map_addr, &sc->mcs_addr, 0); 664 if (error) { 665 device_printf(dev, "can't map the multicast setup command\n"); 666 goto fail; 667 } 668 669 /* 670 * Pre-allocate the TX DMA maps and setup the pointers to 671 * the TX command blocks. 672 */ 673 txp = sc->fxp_desc.tx_list; 674 tcbp = sc->fxp_desc.cbl_list; 675 for (i = 0; i < FXP_NTXCB; i++) { 676 txp[i].tx_cb = tcbp + i; 677 error = bus_dmamap_create(sc->fxp_mtag, 0, &txp[i].tx_map); 678 if (error) { 679 device_printf(dev, "can't create DMA map for TX\n"); 680 goto fail; 681 } 682 } 683 error = bus_dmamap_create(sc->fxp_mtag, 0, &sc->spare_map); 684 if (error) { 685 device_printf(dev, "can't create spare DMA map\n"); 686 goto fail; 687 } 688 689 /* 690 * Pre-allocate our receive buffers. 691 */ 692 sc->fxp_desc.rx_head = sc->fxp_desc.rx_tail = NULL; 693 for (i = 0; i < FXP_NRFABUFS; i++) { 694 rxp = &sc->fxp_desc.rx_list[i]; 695 error = bus_dmamap_create(sc->fxp_mtag, 0, &rxp->rx_map); 696 if (error) { 697 device_printf(dev, "can't create DMA map for RX\n"); 698 goto fail; 699 } 700 if (fxp_add_rfabuf(sc, rxp) != 0) { 701 error = ENOMEM; 702 goto fail; 703 } 704 } 705 706 /* 707 * Read MAC address. 708 */ 709 fxp_read_eeprom(sc, myea, 0, 3); 710 sc->arpcom.ac_enaddr[0] = myea[0] & 0xff; 711 sc->arpcom.ac_enaddr[1] = myea[0] >> 8; 712 sc->arpcom.ac_enaddr[2] = myea[1] & 0xff; 713 sc->arpcom.ac_enaddr[3] = myea[1] >> 8; 714 sc->arpcom.ac_enaddr[4] = myea[2] & 0xff; 715 sc->arpcom.ac_enaddr[5] = myea[2] >> 8; 716 if (bootverbose) { 717 device_printf(dev, "PCI IDs: %04x %04x %04x %04x %04x\n", 718 pci_get_vendor(dev), pci_get_device(dev), 719 pci_get_subvendor(dev), pci_get_subdevice(dev), 720 pci_get_revid(dev)); 721 fxp_read_eeprom(sc, &data, 10, 1); 722 device_printf(dev, "Dynamic Standby mode is %s\n", 723 data & 0x02 ? "enabled" : "disabled"); 724 } 725 726 /* 727 * If this is only a 10Mbps device, then there is no MII, and 728 * the PHY will use a serial interface instead. 729 * 730 * The Seeq 80c24 AutoDUPLEX(tm) Ethernet Interface Adapter 731 * doesn't have a programming interface of any sort. The 732 * media is sensed automatically based on how the link partner 733 * is configured. This is, in essence, manual configuration. 734 */ 735 if (sc->flags & FXP_FLAG_SERIAL_MEDIA) { 736 ifmedia_add(&sc->sc_media, IFM_ETHER|IFM_MANUAL, 0, NULL); 737 ifmedia_set(&sc->sc_media, IFM_ETHER|IFM_MANUAL); 738 } else { 739 if (mii_phy_probe(dev, &sc->miibus, fxp_ifmedia_upd, 740 fxp_ifmedia_sts)) { 741 device_printf(dev, "MII without any PHY!\n"); 742 error = ENXIO; 743 goto fail; 744 } 745 } 746 747 ifp = &sc->arpcom.ac_if; 748 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 749 ifp->if_baudrate = 100000000; 750 ifp->if_init = fxp_init; 751 ifp->if_softc = sc; 752 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 753 ifp->if_ioctl = fxp_ioctl; 754 ifp->if_start = fxp_start; 755 ifp->if_watchdog = fxp_watchdog; 756 757 ifp->if_capabilities = ifp->if_capenable = 0; 758 759 /* Enable checksum offload for 82550 or better chips */ 760 if (sc->flags & FXP_FLAG_EXT_RFA) { 761 ifp->if_hwassist = FXP_CSUM_FEATURES; 762 ifp->if_capabilities |= IFCAP_HWCSUM; 763 ifp->if_capenable |= IFCAP_HWCSUM; 764 } 765 766 #ifdef DEVICE_POLLING 767 /* Inform the world we support polling. */ 768 ifp->if_capabilities |= IFCAP_POLLING; 769 ifp->if_capenable |= IFCAP_POLLING; 770 #endif 771 772 /* 773 * Attach the interface. 774 */ 775 ether_ifattach(ifp, sc->arpcom.ac_enaddr); 776 777 /* 778 * Tell the upper layer(s) we support long frames. 779 * Must appear after the call to ether_ifattach() because 780 * ether_ifattach() sets ifi_hdrlen to the default value. 781 */ 782 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 783 ifp->if_capabilities |= IFCAP_VLAN_MTU; 784 ifp->if_capenable |= IFCAP_VLAN_MTU; /* the hw bits already set */ 785 786 /* 787 * Let the system queue as many packets as we have available 788 * TX descriptors. 789 */ 790 IFQ_SET_MAXLEN(&ifp->if_snd, FXP_NTXCB - 1); 791 ifp->if_snd.ifq_drv_maxlen = FXP_NTXCB - 1; 792 IFQ_SET_READY(&ifp->if_snd); 793 794 /* 795 * Hook our interrupt after all initialization is complete. 796 */ 797 error = bus_setup_intr(dev, sc->irq, INTR_TYPE_NET | INTR_MPSAFE, 798 fxp_intr, sc, &sc->ih); 799 if (error) { 800 device_printf(dev, "could not setup irq\n"); 801 ether_ifdetach(&sc->arpcom.ac_if); 802 goto fail; 803 } 804 805 fail: 806 splx(s); 807 if (error) 808 fxp_release(sc); 809 return (error); 810 } 811 812 /* 813 * Release all resources. The softc lock should not be held and the 814 * interrupt should already be torn down. 815 */ 816 static void 817 fxp_release(struct fxp_softc *sc) 818 { 819 struct fxp_rx *rxp; 820 struct fxp_tx *txp; 821 int i; 822 823 FXP_LOCK_ASSERT(sc, MA_NOTOWNED); 824 KASSERT(sc->ih == NULL, 825 ("fxp_release() called with intr handle still active")); 826 if (sc->miibus) 827 device_delete_child(sc->dev, sc->miibus); 828 bus_generic_detach(sc->dev); 829 ifmedia_removeall(&sc->sc_media); 830 if (sc->fxp_desc.cbl_list) { 831 bus_dmamap_unload(sc->cbl_tag, sc->cbl_map); 832 bus_dmamem_free(sc->cbl_tag, sc->fxp_desc.cbl_list, 833 sc->cbl_map); 834 } 835 if (sc->fxp_stats) { 836 bus_dmamap_unload(sc->fxp_stag, sc->fxp_smap); 837 bus_dmamem_free(sc->fxp_stag, sc->fxp_stats, sc->fxp_smap); 838 } 839 if (sc->mcsp) { 840 bus_dmamap_unload(sc->mcs_tag, sc->mcs_map); 841 bus_dmamem_free(sc->mcs_tag, sc->mcsp, sc->mcs_map); 842 } 843 if (sc->irq) 844 bus_release_resource(sc->dev, SYS_RES_IRQ, 0, sc->irq); 845 if (sc->mem) 846 bus_release_resource(sc->dev, sc->rtp, sc->rgd, sc->mem); 847 if (sc->fxp_mtag) { 848 for (i = 0; i < FXP_NRFABUFS; i++) { 849 rxp = &sc->fxp_desc.rx_list[i]; 850 if (rxp->rx_mbuf != NULL) { 851 bus_dmamap_sync(sc->fxp_mtag, rxp->rx_map, 852 BUS_DMASYNC_POSTREAD); 853 bus_dmamap_unload(sc->fxp_mtag, rxp->rx_map); 854 m_freem(rxp->rx_mbuf); 855 } 856 bus_dmamap_destroy(sc->fxp_mtag, rxp->rx_map); 857 } 858 bus_dmamap_destroy(sc->fxp_mtag, sc->spare_map); 859 for (i = 0; i < FXP_NTXCB; i++) { 860 txp = &sc->fxp_desc.tx_list[i]; 861 if (txp->tx_mbuf != NULL) { 862 bus_dmamap_sync(sc->fxp_mtag, txp->tx_map, 863 BUS_DMASYNC_POSTWRITE); 864 bus_dmamap_unload(sc->fxp_mtag, txp->tx_map); 865 m_freem(txp->tx_mbuf); 866 } 867 bus_dmamap_destroy(sc->fxp_mtag, txp->tx_map); 868 } 869 bus_dma_tag_destroy(sc->fxp_mtag); 870 } 871 if (sc->fxp_stag) 872 bus_dma_tag_destroy(sc->fxp_stag); 873 if (sc->cbl_tag) 874 bus_dma_tag_destroy(sc->cbl_tag); 875 if (sc->mcs_tag) 876 bus_dma_tag_destroy(sc->mcs_tag); 877 878 mtx_destroy(&sc->sc_mtx); 879 } 880 881 /* 882 * Detach interface. 883 */ 884 static int 885 fxp_detach(device_t dev) 886 { 887 struct fxp_softc *sc = device_get_softc(dev); 888 int s; 889 890 FXP_LOCK(sc); 891 s = splimp(); 892 893 sc->suspended = 1; /* Do same thing as we do for suspend */ 894 /* 895 * Close down routes etc. 896 */ 897 ether_ifdetach(&sc->arpcom.ac_if); 898 899 /* 900 * Stop DMA and drop transmit queue, but disable interrupts first. 901 */ 902 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE); 903 fxp_stop(sc); 904 FXP_UNLOCK(sc); 905 906 /* 907 * Unhook interrupt before dropping lock. This is to prevent 908 * races with fxp_intr(). 909 */ 910 bus_teardown_intr(sc->dev, sc->irq, sc->ih); 911 sc->ih = NULL; 912 913 splx(s); 914 915 /* Release our allocated resources. */ 916 fxp_release(sc); 917 return (0); 918 } 919 920 /* 921 * Device shutdown routine. Called at system shutdown after sync. The 922 * main purpose of this routine is to shut off receiver DMA so that 923 * kernel memory doesn't get clobbered during warmboot. 924 */ 925 static int 926 fxp_shutdown(device_t dev) 927 { 928 /* 929 * Make sure that DMA is disabled prior to reboot. Not doing 930 * do could allow DMA to corrupt kernel memory during the 931 * reboot before the driver initializes. 932 */ 933 fxp_stop((struct fxp_softc *) device_get_softc(dev)); 934 return (0); 935 } 936 937 /* 938 * Device suspend routine. Stop the interface and save some PCI 939 * settings in case the BIOS doesn't restore them properly on 940 * resume. 941 */ 942 static int 943 fxp_suspend(device_t dev) 944 { 945 struct fxp_softc *sc = device_get_softc(dev); 946 int i, s; 947 948 FXP_LOCK(sc); 949 s = splimp(); 950 951 fxp_stop(sc); 952 953 for (i = 0; i < 5; i++) 954 sc->saved_maps[i] = pci_read_config(dev, PCIR_BAR(i), 4); 955 sc->saved_biosaddr = pci_read_config(dev, PCIR_BIOS, 4); 956 sc->saved_intline = pci_read_config(dev, PCIR_INTLINE, 1); 957 sc->saved_cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1); 958 sc->saved_lattimer = pci_read_config(dev, PCIR_LATTIMER, 1); 959 960 sc->suspended = 1; 961 962 FXP_UNLOCK(sc); 963 splx(s); 964 return (0); 965 } 966 967 /* 968 * Device resume routine. Restore some PCI settings in case the BIOS 969 * doesn't, re-enable busmastering, and restart the interface if 970 * appropriate. 971 */ 972 static int 973 fxp_resume(device_t dev) 974 { 975 struct fxp_softc *sc = device_get_softc(dev); 976 struct ifnet *ifp = &sc->sc_if; 977 uint16_t pci_command; 978 int i, s; 979 980 FXP_LOCK(sc); 981 s = splimp(); 982 983 /* better way to do this? */ 984 for (i = 0; i < 5; i++) 985 pci_write_config(dev, PCIR_BAR(i), sc->saved_maps[i], 4); 986 pci_write_config(dev, PCIR_BIOS, sc->saved_biosaddr, 4); 987 pci_write_config(dev, PCIR_INTLINE, sc->saved_intline, 1); 988 pci_write_config(dev, PCIR_CACHELNSZ, sc->saved_cachelnsz, 1); 989 pci_write_config(dev, PCIR_LATTIMER, sc->saved_lattimer, 1); 990 991 /* reenable busmastering */ 992 pci_command = pci_read_config(dev, PCIR_COMMAND, 2); 993 pci_command |= (PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN); 994 pci_write_config(dev, PCIR_COMMAND, pci_command, 2); 995 996 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET); 997 DELAY(10); 998 999 /* reinitialize interface if necessary */ 1000 if (ifp->if_flags & IFF_UP) 1001 fxp_init_body(sc); 1002 1003 sc->suspended = 0; 1004 1005 FXP_UNLOCK(sc); 1006 splx(s); 1007 return (0); 1008 } 1009 1010 static void 1011 fxp_eeprom_shiftin(struct fxp_softc *sc, int data, int length) 1012 { 1013 uint16_t reg; 1014 int x; 1015 1016 /* 1017 * Shift in data. 1018 */ 1019 for (x = 1 << (length - 1); x; x >>= 1) { 1020 if (data & x) 1021 reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI; 1022 else 1023 reg = FXP_EEPROM_EECS; 1024 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 1025 DELAY(1); 1026 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK); 1027 DELAY(1); 1028 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 1029 DELAY(1); 1030 } 1031 } 1032 1033 /* 1034 * Read from the serial EEPROM. Basically, you manually shift in 1035 * the read opcode (one bit at a time) and then shift in the address, 1036 * and then you shift out the data (all of this one bit at a time). 1037 * The word size is 16 bits, so you have to provide the address for 1038 * every 16 bits of data. 1039 */ 1040 static uint16_t 1041 fxp_eeprom_getword(struct fxp_softc *sc, int offset, int autosize) 1042 { 1043 uint16_t reg, data; 1044 int x; 1045 1046 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 1047 /* 1048 * Shift in read opcode. 1049 */ 1050 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_READ, 3); 1051 /* 1052 * Shift in address. 1053 */ 1054 data = 0; 1055 for (x = 1 << (sc->eeprom_size - 1); x; x >>= 1) { 1056 if (offset & x) 1057 reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI; 1058 else 1059 reg = FXP_EEPROM_EECS; 1060 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 1061 DELAY(1); 1062 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK); 1063 DELAY(1); 1064 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 1065 DELAY(1); 1066 reg = CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO; 1067 data++; 1068 if (autosize && reg == 0) { 1069 sc->eeprom_size = data; 1070 break; 1071 } 1072 } 1073 /* 1074 * Shift out data. 1075 */ 1076 data = 0; 1077 reg = FXP_EEPROM_EECS; 1078 for (x = 1 << 15; x; x >>= 1) { 1079 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK); 1080 DELAY(1); 1081 if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO) 1082 data |= x; 1083 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 1084 DELAY(1); 1085 } 1086 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 1087 DELAY(1); 1088 1089 return (data); 1090 } 1091 1092 static void 1093 fxp_eeprom_putword(struct fxp_softc *sc, int offset, uint16_t data) 1094 { 1095 int i; 1096 1097 /* 1098 * Erase/write enable. 1099 */ 1100 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 1101 fxp_eeprom_shiftin(sc, 0x4, 3); 1102 fxp_eeprom_shiftin(sc, 0x03 << (sc->eeprom_size - 2), sc->eeprom_size); 1103 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 1104 DELAY(1); 1105 /* 1106 * Shift in write opcode, address, data. 1107 */ 1108 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 1109 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_WRITE, 3); 1110 fxp_eeprom_shiftin(sc, offset, sc->eeprom_size); 1111 fxp_eeprom_shiftin(sc, data, 16); 1112 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 1113 DELAY(1); 1114 /* 1115 * Wait for EEPROM to finish up. 1116 */ 1117 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 1118 DELAY(1); 1119 for (i = 0; i < 1000; i++) { 1120 if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO) 1121 break; 1122 DELAY(50); 1123 } 1124 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 1125 DELAY(1); 1126 /* 1127 * Erase/write disable. 1128 */ 1129 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 1130 fxp_eeprom_shiftin(sc, 0x4, 3); 1131 fxp_eeprom_shiftin(sc, 0, sc->eeprom_size); 1132 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 1133 DELAY(1); 1134 } 1135 1136 /* 1137 * From NetBSD: 1138 * 1139 * Figure out EEPROM size. 1140 * 1141 * 559's can have either 64-word or 256-word EEPROMs, the 558 1142 * datasheet only talks about 64-word EEPROMs, and the 557 datasheet 1143 * talks about the existance of 16 to 256 word EEPROMs. 1144 * 1145 * The only known sizes are 64 and 256, where the 256 version is used 1146 * by CardBus cards to store CIS information. 1147 * 1148 * The address is shifted in msb-to-lsb, and after the last 1149 * address-bit the EEPROM is supposed to output a `dummy zero' bit, 1150 * after which follows the actual data. We try to detect this zero, by 1151 * probing the data-out bit in the EEPROM control register just after 1152 * having shifted in a bit. If the bit is zero, we assume we've 1153 * shifted enough address bits. The data-out should be tri-state, 1154 * before this, which should translate to a logical one. 1155 */ 1156 static void 1157 fxp_autosize_eeprom(struct fxp_softc *sc) 1158 { 1159 1160 /* guess maximum size of 256 words */ 1161 sc->eeprom_size = 8; 1162 1163 /* autosize */ 1164 (void) fxp_eeprom_getword(sc, 0, 1); 1165 } 1166 1167 static void 1168 fxp_read_eeprom(struct fxp_softc *sc, u_short *data, int offset, int words) 1169 { 1170 int i; 1171 1172 for (i = 0; i < words; i++) 1173 data[i] = fxp_eeprom_getword(sc, offset + i, 0); 1174 } 1175 1176 static void 1177 fxp_write_eeprom(struct fxp_softc *sc, u_short *data, int offset, int words) 1178 { 1179 int i; 1180 1181 for (i = 0; i < words; i++) 1182 fxp_eeprom_putword(sc, offset + i, data[i]); 1183 } 1184 1185 /* 1186 * Grab the softc lock and call the real fxp_start_body() routine 1187 */ 1188 static void 1189 fxp_start(struct ifnet *ifp) 1190 { 1191 struct fxp_softc *sc = ifp->if_softc; 1192 1193 FXP_LOCK(sc); 1194 fxp_start_body(ifp); 1195 FXP_UNLOCK(sc); 1196 } 1197 1198 /* 1199 * Start packet transmission on the interface. 1200 * This routine must be called with the softc lock held, and is an 1201 * internal entry point only. 1202 */ 1203 static void 1204 fxp_start_body(struct ifnet *ifp) 1205 { 1206 struct fxp_softc *sc = ifp->if_softc; 1207 struct mbuf *mb_head; 1208 int error, txqueued; 1209 1210 FXP_LOCK_ASSERT(sc, MA_OWNED); 1211 1212 /* 1213 * See if we need to suspend xmit until the multicast filter 1214 * has been reprogrammed (which can only be done at the head 1215 * of the command chain). 1216 */ 1217 if (sc->need_mcsetup) 1218 return; 1219 1220 /* 1221 * We're finished if there is nothing more to add to the list or if 1222 * we're all filled up with buffers to transmit. 1223 * NOTE: One TxCB is reserved to guarantee that fxp_mc_setup() can add 1224 * a NOP command when needed. 1225 */ 1226 txqueued = 0; 1227 while (!IFQ_DRV_IS_EMPTY(&ifp->if_snd) && 1228 sc->tx_queued < FXP_NTXCB - 1) { 1229 1230 /* 1231 * Grab a packet to transmit. 1232 */ 1233 IFQ_DRV_DEQUEUE(&ifp->if_snd, mb_head); 1234 if (mb_head == NULL) 1235 break; 1236 1237 error = fxp_encap(sc, mb_head); 1238 if (error) 1239 break; 1240 txqueued = 1; 1241 } 1242 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE); 1243 1244 /* 1245 * We're finished. If we added to the list, issue a RESUME to get DMA 1246 * going again if suspended. 1247 */ 1248 if (txqueued) { 1249 fxp_scb_wait(sc); 1250 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_RESUME); 1251 } 1252 } 1253 1254 static int 1255 fxp_encap(struct fxp_softc *sc, struct mbuf *m_head) 1256 { 1257 struct ifnet *ifp; 1258 struct mbuf *m; 1259 struct fxp_tx *txp; 1260 struct fxp_cb_tx *cbp; 1261 bus_dma_segment_t segs[FXP_NTXSEG]; 1262 int chainlen, error, i, nseg; 1263 1264 FXP_LOCK_ASSERT(sc, MA_OWNED); 1265 ifp = &sc->sc_if; 1266 1267 /* 1268 * Get pointer to next available tx desc. 1269 */ 1270 txp = sc->fxp_desc.tx_last->tx_next; 1271 1272 /* 1273 * A note in Appendix B of the Intel 8255x 10/100 Mbps 1274 * Ethernet Controller Family Open Source Software 1275 * Developer Manual says: 1276 * Using software parsing is only allowed with legal 1277 * TCP/IP or UDP/IP packets. 1278 * ... 1279 * For all other datagrams, hardware parsing must 1280 * be used. 1281 * Software parsing appears to truncate ICMP and 1282 * fragmented UDP packets that contain one to three 1283 * bytes in the second (and final) mbuf of the packet. 1284 */ 1285 if (sc->flags & FXP_FLAG_EXT_RFA) 1286 txp->tx_cb->ipcb_ip_activation_high = 1287 FXP_IPCB_HARDWAREPARSING_ENABLE; 1288 1289 /* 1290 * Deal with TCP/IP checksum offload. Note that 1291 * in order for TCP checksum offload to work, 1292 * the pseudo header checksum must have already 1293 * been computed and stored in the checksum field 1294 * in the TCP header. The stack should have 1295 * already done this for us. 1296 */ 1297 if (m_head->m_pkthdr.csum_flags) { 1298 if (m_head->m_pkthdr.csum_flags & CSUM_DELAY_DATA) { 1299 txp->tx_cb->ipcb_ip_schedule = 1300 FXP_IPCB_TCPUDP_CHECKSUM_ENABLE; 1301 if (m_head->m_pkthdr.csum_flags & CSUM_TCP) 1302 txp->tx_cb->ipcb_ip_schedule |= 1303 FXP_IPCB_TCP_PACKET; 1304 } 1305 1306 #ifdef FXP_IP_CSUM_WAR 1307 /* 1308 * XXX The 82550 chip appears to have trouble 1309 * dealing with IP header checksums in very small 1310 * datagrams, namely fragments from 1 to 3 bytes 1311 * in size. For example, say you want to transmit 1312 * a UDP packet of 1473 bytes. The packet will be 1313 * fragmented over two IP datagrams, the latter 1314 * containing only one byte of data. The 82550 will 1315 * botch the header checksum on the 1-byte fragment. 1316 * As long as the datagram contains 4 or more bytes 1317 * of data, you're ok. 1318 * 1319 * The following code attempts to work around this 1320 * problem: if the datagram is less than 38 bytes 1321 * in size (14 bytes ether header, 20 bytes IP header, 1322 * plus 4 bytes of data), we punt and compute the IP 1323 * header checksum by hand. This workaround doesn't 1324 * work very well, however, since it can be fooled 1325 * by things like VLAN tags and IP options that make 1326 * the header sizes/offsets vary. 1327 */ 1328 1329 if (m_head->m_pkthdr.csum_flags & CSUM_IP) { 1330 if (m_head->m_pkthdr.len < 38) { 1331 struct ip *ip; 1332 m_head->m_data += ETHER_HDR_LEN; 1333 ip = mtod(mb_head, struct ip *); 1334 ip->ip_sum = in_cksum(mb_head, ip->ip_hl << 2); 1335 m_head->m_data -= ETHER_HDR_LEN; 1336 } else { 1337 txp->tx_cb->ipcb_ip_activation_high = 1338 FXP_IPCB_HARDWAREPARSING_ENABLE; 1339 txp->tx_cb->ipcb_ip_schedule |= 1340 FXP_IPCB_IP_CHECKSUM_ENABLE; 1341 } 1342 } 1343 #endif 1344 } 1345 1346 chainlen = 0; 1347 for (m = m_head; m != NULL && chainlen <= sc->maxtxseg; m = m->m_next) 1348 chainlen++; 1349 if (chainlen > sc->maxtxseg) { 1350 struct mbuf *mn; 1351 1352 /* 1353 * We ran out of segments. We have to recopy this 1354 * mbuf chain first. Bail out if we can't get the 1355 * new buffers. 1356 */ 1357 mn = m_defrag(m_head, M_DONTWAIT); 1358 if (mn == NULL) { 1359 m_freem(m_head); 1360 return (-1); 1361 } else { 1362 m_head = mn; 1363 } 1364 } 1365 1366 /* 1367 * Go through each of the mbufs in the chain and initialize 1368 * the transmit buffer descriptors with the physical address 1369 * and size of the mbuf. 1370 */ 1371 error = bus_dmamap_load_mbuf_sg(sc->fxp_mtag, txp->tx_map, 1372 m_head, segs, &nseg, 0); 1373 if (error) { 1374 device_printf(sc->dev, "can't map mbuf (error %d)\n", error); 1375 m_freem(m_head); 1376 return (-1); 1377 } 1378 1379 KASSERT(nseg <= sc->maxtxseg, ("too many DMA segments")); 1380 1381 cbp = txp->tx_cb; 1382 for (i = 0; i < nseg; i++) { 1383 KASSERT(segs[i].ds_len <= MCLBYTES, ("segment size too large")); 1384 /* 1385 * If this is an 82550/82551, then we're using extended 1386 * TxCBs _and_ we're using checksum offload. This means 1387 * that the TxCB is really an IPCB. One major difference 1388 * between the two is that with plain extended TxCBs, 1389 * the bottom half of the TxCB contains two entries from 1390 * the TBD array, whereas IPCBs contain just one entry: 1391 * one entry (8 bytes) has been sacrificed for the TCP/IP 1392 * checksum offload control bits. So to make things work 1393 * right, we have to start filling in the TBD array 1394 * starting from a different place depending on whether 1395 * the chip is an 82550/82551 or not. 1396 */ 1397 if (sc->flags & FXP_FLAG_EXT_RFA) { 1398 cbp->tbd[i + 1].tb_addr = htole32(segs[i].ds_addr); 1399 cbp->tbd[i + 1].tb_size = htole32(segs[i].ds_len); 1400 } else { 1401 cbp->tbd[i].tb_addr = htole32(segs[i].ds_addr); 1402 cbp->tbd[i].tb_size = htole32(segs[i].ds_len); 1403 } 1404 } 1405 cbp->tbd_number = nseg; 1406 1407 bus_dmamap_sync(sc->fxp_mtag, txp->tx_map, BUS_DMASYNC_PREWRITE); 1408 txp->tx_mbuf = m_head; 1409 txp->tx_cb->cb_status = 0; 1410 txp->tx_cb->byte_count = 0; 1411 if (sc->tx_queued != FXP_CXINT_THRESH - 1) { 1412 txp->tx_cb->cb_command = 1413 htole16(sc->tx_cmd | FXP_CB_COMMAND_SF | 1414 FXP_CB_COMMAND_S); 1415 } else { 1416 txp->tx_cb->cb_command = 1417 htole16(sc->tx_cmd | FXP_CB_COMMAND_SF | 1418 FXP_CB_COMMAND_S | FXP_CB_COMMAND_I); 1419 /* 1420 * Set a 5 second timer just in case we don't hear 1421 * from the card again. 1422 */ 1423 ifp->if_timer = 5; 1424 } 1425 txp->tx_cb->tx_threshold = tx_threshold; 1426 1427 /* 1428 * Advance the end of list forward. 1429 */ 1430 1431 #ifdef __alpha__ 1432 /* 1433 * On platforms which can't access memory in 16-bit 1434 * granularities, we must prevent the card from DMA'ing 1435 * up the status while we update the command field. 1436 * This could cause us to overwrite the completion status. 1437 * XXX This is probably bogus and we're _not_ looking 1438 * for atomicity here. 1439 */ 1440 atomic_clear_16(&sc->fxp_desc.tx_last->tx_cb->cb_command, 1441 htole16(FXP_CB_COMMAND_S)); 1442 #else 1443 sc->fxp_desc.tx_last->tx_cb->cb_command &= htole16(~FXP_CB_COMMAND_S); 1444 #endif /*__alpha__*/ 1445 sc->fxp_desc.tx_last = txp; 1446 1447 /* 1448 * Advance the beginning of the list forward if there are 1449 * no other packets queued (when nothing is queued, tx_first 1450 * sits on the last TxCB that was sent out). 1451 */ 1452 if (sc->tx_queued == 0) 1453 sc->fxp_desc.tx_first = txp; 1454 1455 sc->tx_queued++; 1456 1457 /* 1458 * Pass packet to bpf if there is a listener. 1459 */ 1460 BPF_MTAP(ifp, m_head); 1461 return (0); 1462 } 1463 1464 #ifdef DEVICE_POLLING 1465 static poll_handler_t fxp_poll; 1466 1467 static void 1468 fxp_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 1469 { 1470 struct fxp_softc *sc = ifp->if_softc; 1471 uint8_t statack; 1472 1473 FXP_LOCK(sc); 1474 if (!(ifp->if_capenable & IFCAP_POLLING)) { 1475 ether_poll_deregister(ifp); 1476 cmd = POLL_DEREGISTER; 1477 } 1478 if (cmd == POLL_DEREGISTER) { /* final call, enable interrupts */ 1479 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, 0); 1480 FXP_UNLOCK(sc); 1481 return; 1482 } 1483 statack = FXP_SCB_STATACK_CXTNO | FXP_SCB_STATACK_CNA | 1484 FXP_SCB_STATACK_FR; 1485 if (cmd == POLL_AND_CHECK_STATUS) { 1486 uint8_t tmp; 1487 1488 tmp = CSR_READ_1(sc, FXP_CSR_SCB_STATACK); 1489 if (tmp == 0xff || tmp == 0) { 1490 FXP_UNLOCK(sc); 1491 return; /* nothing to do */ 1492 } 1493 tmp &= ~statack; 1494 /* ack what we can */ 1495 if (tmp != 0) 1496 CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, tmp); 1497 statack |= tmp; 1498 } 1499 fxp_intr_body(sc, ifp, statack, count); 1500 FXP_UNLOCK(sc); 1501 } 1502 #endif /* DEVICE_POLLING */ 1503 1504 /* 1505 * Process interface interrupts. 1506 */ 1507 static void 1508 fxp_intr(void *xsc) 1509 { 1510 struct fxp_softc *sc = xsc; 1511 struct ifnet *ifp = &sc->sc_if; 1512 uint8_t statack; 1513 1514 FXP_LOCK(sc); 1515 if (sc->suspended) { 1516 FXP_UNLOCK(sc); 1517 return; 1518 } 1519 1520 #ifdef DEVICE_POLLING 1521 if (ifp->if_flags & IFF_POLLING) { 1522 FXP_UNLOCK(sc); 1523 return; 1524 } 1525 if ((ifp->if_capenable & IFCAP_POLLING) && 1526 ether_poll_register(fxp_poll, ifp)) { 1527 /* disable interrupts */ 1528 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE); 1529 FXP_UNLOCK(sc); 1530 fxp_poll(ifp, 0, 1); 1531 return; 1532 } 1533 #endif 1534 while ((statack = CSR_READ_1(sc, FXP_CSR_SCB_STATACK)) != 0) { 1535 /* 1536 * It should not be possible to have all bits set; the 1537 * FXP_SCB_INTR_SWI bit always returns 0 on a read. If 1538 * all bits are set, this may indicate that the card has 1539 * been physically ejected, so ignore it. 1540 */ 1541 if (statack == 0xff) { 1542 FXP_UNLOCK(sc); 1543 return; 1544 } 1545 1546 /* 1547 * First ACK all the interrupts in this pass. 1548 */ 1549 CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, statack); 1550 fxp_intr_body(sc, ifp, statack, -1); 1551 } 1552 FXP_UNLOCK(sc); 1553 } 1554 1555 static void 1556 fxp_txeof(struct fxp_softc *sc) 1557 { 1558 struct fxp_tx *txp; 1559 1560 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREREAD); 1561 for (txp = sc->fxp_desc.tx_first; sc->tx_queued && 1562 (le16toh(txp->tx_cb->cb_status) & FXP_CB_STATUS_C) != 0; 1563 txp = txp->tx_next) { 1564 if (txp->tx_mbuf != NULL) { 1565 bus_dmamap_sync(sc->fxp_mtag, txp->tx_map, 1566 BUS_DMASYNC_POSTWRITE); 1567 bus_dmamap_unload(sc->fxp_mtag, txp->tx_map); 1568 m_freem(txp->tx_mbuf); 1569 txp->tx_mbuf = NULL; 1570 /* clear this to reset csum offload bits */ 1571 txp->tx_cb->tbd[0].tb_addr = 0; 1572 } 1573 sc->tx_queued--; 1574 } 1575 sc->fxp_desc.tx_first = txp; 1576 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE); 1577 } 1578 1579 static void 1580 fxp_intr_body(struct fxp_softc *sc, struct ifnet *ifp, uint8_t statack, 1581 int count) 1582 { 1583 struct mbuf *m; 1584 struct fxp_rx *rxp; 1585 struct fxp_rfa *rfa; 1586 int rnr = (statack & FXP_SCB_STATACK_RNR) ? 1 : 0; 1587 1588 FXP_LOCK_ASSERT(sc, MA_OWNED); 1589 if (rnr) 1590 sc->rnr++; 1591 #ifdef DEVICE_POLLING 1592 /* Pick up a deferred RNR condition if `count' ran out last time. */ 1593 if (sc->flags & FXP_FLAG_DEFERRED_RNR) { 1594 sc->flags &= ~FXP_FLAG_DEFERRED_RNR; 1595 rnr = 1; 1596 } 1597 #endif 1598 1599 /* 1600 * Free any finished transmit mbuf chains. 1601 * 1602 * Handle the CNA event likt a CXTNO event. It used to 1603 * be that this event (control unit not ready) was not 1604 * encountered, but it is now with the SMPng modifications. 1605 * The exact sequence of events that occur when the interface 1606 * is brought up are different now, and if this event 1607 * goes unhandled, the configuration/rxfilter setup sequence 1608 * can stall for several seconds. The result is that no 1609 * packets go out onto the wire for about 5 to 10 seconds 1610 * after the interface is ifconfig'ed for the first time. 1611 */ 1612 if (statack & (FXP_SCB_STATACK_CXTNO | FXP_SCB_STATACK_CNA)) { 1613 fxp_txeof(sc); 1614 1615 ifp->if_timer = 0; 1616 if (sc->tx_queued == 0) { 1617 if (sc->need_mcsetup) 1618 fxp_mc_setup(sc); 1619 } 1620 /* 1621 * Try to start more packets transmitting. 1622 */ 1623 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1624 fxp_start_body(ifp); 1625 } 1626 1627 /* 1628 * Just return if nothing happened on the receive side. 1629 */ 1630 if (!rnr && (statack & FXP_SCB_STATACK_FR) == 0) 1631 return; 1632 1633 /* 1634 * Process receiver interrupts. If a no-resource (RNR) 1635 * condition exists, get whatever packets we can and 1636 * re-start the receiver. 1637 * 1638 * When using polling, we do not process the list to completion, 1639 * so when we get an RNR interrupt we must defer the restart 1640 * until we hit the last buffer with the C bit set. 1641 * If we run out of cycles and rfa_headm has the C bit set, 1642 * record the pending RNR in the FXP_FLAG_DEFERRED_RNR flag so 1643 * that the info will be used in the subsequent polling cycle. 1644 */ 1645 for (;;) { 1646 rxp = sc->fxp_desc.rx_head; 1647 m = rxp->rx_mbuf; 1648 rfa = (struct fxp_rfa *)(m->m_ext.ext_buf + 1649 RFA_ALIGNMENT_FUDGE); 1650 bus_dmamap_sync(sc->fxp_mtag, rxp->rx_map, 1651 BUS_DMASYNC_POSTREAD); 1652 1653 #ifdef DEVICE_POLLING /* loop at most count times if count >=0 */ 1654 if (count >= 0 && count-- == 0) { 1655 if (rnr) { 1656 /* Defer RNR processing until the next time. */ 1657 sc->flags |= FXP_FLAG_DEFERRED_RNR; 1658 rnr = 0; 1659 } 1660 break; 1661 } 1662 #endif /* DEVICE_POLLING */ 1663 1664 if ((le16toh(rfa->rfa_status) & FXP_RFA_STATUS_C) == 0) 1665 break; 1666 1667 /* 1668 * Advance head forward. 1669 */ 1670 sc->fxp_desc.rx_head = rxp->rx_next; 1671 1672 /* 1673 * Add a new buffer to the receive chain. 1674 * If this fails, the old buffer is recycled 1675 * instead. 1676 */ 1677 if (fxp_add_rfabuf(sc, rxp) == 0) { 1678 int total_len; 1679 1680 /* 1681 * Fetch packet length (the top 2 bits of 1682 * actual_size are flags set by the controller 1683 * upon completion), and drop the packet in case 1684 * of bogus length or CRC errors. 1685 */ 1686 total_len = le16toh(rfa->actual_size) & 0x3fff; 1687 if (total_len < sizeof(struct ether_header) || 1688 total_len > MCLBYTES - RFA_ALIGNMENT_FUDGE - 1689 sc->rfa_size || 1690 le16toh(rfa->rfa_status) & FXP_RFA_STATUS_CRC) { 1691 m_freem(m); 1692 continue; 1693 } 1694 1695 /* Do IP checksum checking. */ 1696 if (le16toh(rfa->rfa_status) & FXP_RFA_STATUS_PARSE) { 1697 if (rfa->rfax_csum_sts & 1698 FXP_RFDX_CS_IP_CSUM_BIT_VALID) 1699 m->m_pkthdr.csum_flags |= 1700 CSUM_IP_CHECKED; 1701 if (rfa->rfax_csum_sts & 1702 FXP_RFDX_CS_IP_CSUM_VALID) 1703 m->m_pkthdr.csum_flags |= 1704 CSUM_IP_VALID; 1705 if ((rfa->rfax_csum_sts & 1706 FXP_RFDX_CS_TCPUDP_CSUM_BIT_VALID) && 1707 (rfa->rfax_csum_sts & 1708 FXP_RFDX_CS_TCPUDP_CSUM_VALID)) { 1709 m->m_pkthdr.csum_flags |= 1710 CSUM_DATA_VALID|CSUM_PSEUDO_HDR; 1711 m->m_pkthdr.csum_data = 0xffff; 1712 } 1713 } 1714 1715 m->m_pkthdr.len = m->m_len = total_len; 1716 m->m_pkthdr.rcvif = ifp; 1717 1718 /* 1719 * Drop locks before calling if_input() since it 1720 * may re-enter fxp_start() in the netisr case. 1721 * This would result in a lock reversal. Better 1722 * performance might be obtained by chaining all 1723 * packets received, dropping the lock, and then 1724 * calling if_input() on each one. 1725 */ 1726 FXP_UNLOCK(sc); 1727 (*ifp->if_input)(ifp, m); 1728 FXP_LOCK(sc); 1729 } 1730 } 1731 if (rnr) { 1732 fxp_scb_wait(sc); 1733 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 1734 sc->fxp_desc.rx_head->rx_addr); 1735 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_START); 1736 } 1737 } 1738 1739 /* 1740 * Update packet in/out/collision statistics. The i82557 doesn't 1741 * allow you to access these counters without doing a fairly 1742 * expensive DMA to get _all_ of the statistics it maintains, so 1743 * we do this operation here only once per second. The statistics 1744 * counters in the kernel are updated from the previous dump-stats 1745 * DMA and then a new dump-stats DMA is started. The on-chip 1746 * counters are zeroed when the DMA completes. If we can't start 1747 * the DMA immediately, we don't wait - we just prepare to read 1748 * them again next time. 1749 */ 1750 static void 1751 fxp_tick(void *xsc) 1752 { 1753 struct fxp_softc *sc = xsc; 1754 struct ifnet *ifp = &sc->sc_if; 1755 struct fxp_stats *sp = sc->fxp_stats; 1756 int s; 1757 1758 FXP_LOCK(sc); 1759 s = splimp(); 1760 bus_dmamap_sync(sc->fxp_stag, sc->fxp_smap, BUS_DMASYNC_POSTREAD); 1761 ifp->if_opackets += le32toh(sp->tx_good); 1762 ifp->if_collisions += le32toh(sp->tx_total_collisions); 1763 if (sp->rx_good) { 1764 ifp->if_ipackets += le32toh(sp->rx_good); 1765 sc->rx_idle_secs = 0; 1766 } else { 1767 /* 1768 * Receiver's been idle for another second. 1769 */ 1770 sc->rx_idle_secs++; 1771 } 1772 ifp->if_ierrors += 1773 le32toh(sp->rx_crc_errors) + 1774 le32toh(sp->rx_alignment_errors) + 1775 le32toh(sp->rx_rnr_errors) + 1776 le32toh(sp->rx_overrun_errors); 1777 /* 1778 * If any transmit underruns occured, bump up the transmit 1779 * threshold by another 512 bytes (64 * 8). 1780 */ 1781 if (sp->tx_underruns) { 1782 ifp->if_oerrors += le32toh(sp->tx_underruns); 1783 if (tx_threshold < 192) 1784 tx_threshold += 64; 1785 } 1786 1787 /* 1788 * Release any xmit buffers that have completed DMA. This isn't 1789 * strictly necessary to do here, but it's advantagous for mbufs 1790 * with external storage to be released in a timely manner rather 1791 * than being defered for a potentially long time. This limits 1792 * the delay to a maximum of one second. 1793 */ 1794 fxp_txeof(sc); 1795 1796 /* 1797 * If we haven't received any packets in FXP_MAC_RX_IDLE seconds, 1798 * then assume the receiver has locked up and attempt to clear 1799 * the condition by reprogramming the multicast filter. This is 1800 * a work-around for a bug in the 82557 where the receiver locks 1801 * up if it gets certain types of garbage in the syncronization 1802 * bits prior to the packet header. This bug is supposed to only 1803 * occur in 10Mbps mode, but has been seen to occur in 100Mbps 1804 * mode as well (perhaps due to a 10/100 speed transition). 1805 */ 1806 if (sc->rx_idle_secs > FXP_MAX_RX_IDLE) { 1807 sc->rx_idle_secs = 0; 1808 fxp_mc_setup(sc); 1809 } 1810 /* 1811 * If there is no pending command, start another stats 1812 * dump. Otherwise punt for now. 1813 */ 1814 if (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) == 0) { 1815 /* 1816 * Start another stats dump. 1817 */ 1818 bus_dmamap_sync(sc->fxp_stag, sc->fxp_smap, 1819 BUS_DMASYNC_PREREAD); 1820 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_DUMPRESET); 1821 } else { 1822 /* 1823 * A previous command is still waiting to be accepted. 1824 * Just zero our copy of the stats and wait for the 1825 * next timer event to update them. 1826 */ 1827 sp->tx_good = 0; 1828 sp->tx_underruns = 0; 1829 sp->tx_total_collisions = 0; 1830 1831 sp->rx_good = 0; 1832 sp->rx_crc_errors = 0; 1833 sp->rx_alignment_errors = 0; 1834 sp->rx_rnr_errors = 0; 1835 sp->rx_overrun_errors = 0; 1836 } 1837 if (sc->miibus != NULL) 1838 mii_tick(device_get_softc(sc->miibus)); 1839 1840 /* 1841 * Schedule another timeout one second from now. 1842 */ 1843 callout_reset(&sc->stat_ch, hz, fxp_tick, sc); 1844 FXP_UNLOCK(sc); 1845 splx(s); 1846 } 1847 1848 /* 1849 * Stop the interface. Cancels the statistics updater and resets 1850 * the interface. 1851 */ 1852 static void 1853 fxp_stop(struct fxp_softc *sc) 1854 { 1855 struct ifnet *ifp = &sc->sc_if; 1856 struct fxp_tx *txp; 1857 int i; 1858 1859 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1860 ifp->if_timer = 0; 1861 1862 #ifdef DEVICE_POLLING 1863 ether_poll_deregister(ifp); 1864 #endif 1865 /* 1866 * Cancel stats updater. 1867 */ 1868 callout_stop(&sc->stat_ch); 1869 1870 /* 1871 * Issue software reset, which also unloads the microcode. 1872 */ 1873 sc->flags &= ~FXP_FLAG_UCODE; 1874 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SOFTWARE_RESET); 1875 DELAY(50); 1876 1877 /* 1878 * Release any xmit buffers. 1879 */ 1880 txp = sc->fxp_desc.tx_list; 1881 if (txp != NULL) { 1882 for (i = 0; i < FXP_NTXCB; i++) { 1883 if (txp[i].tx_mbuf != NULL) { 1884 bus_dmamap_sync(sc->fxp_mtag, txp[i].tx_map, 1885 BUS_DMASYNC_POSTWRITE); 1886 bus_dmamap_unload(sc->fxp_mtag, txp[i].tx_map); 1887 m_freem(txp[i].tx_mbuf); 1888 txp[i].tx_mbuf = NULL; 1889 /* clear this to reset csum offload bits */ 1890 txp[i].tx_cb->tbd[0].tb_addr = 0; 1891 } 1892 } 1893 } 1894 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE); 1895 sc->tx_queued = 0; 1896 } 1897 1898 /* 1899 * Watchdog/transmission transmit timeout handler. Called when a 1900 * transmission is started on the interface, but no interrupt is 1901 * received before the timeout. This usually indicates that the 1902 * card has wedged for some reason. 1903 */ 1904 static void 1905 fxp_watchdog(struct ifnet *ifp) 1906 { 1907 struct fxp_softc *sc = ifp->if_softc; 1908 1909 FXP_LOCK(sc); 1910 device_printf(sc->dev, "device timeout\n"); 1911 ifp->if_oerrors++; 1912 1913 fxp_init_body(sc); 1914 FXP_UNLOCK(sc); 1915 } 1916 1917 /* 1918 * Acquire locks and then call the real initialization function. This 1919 * is necessary because ether_ioctl() calls if_init() and this would 1920 * result in mutex recursion if the mutex was held. 1921 */ 1922 static void 1923 fxp_init(void *xsc) 1924 { 1925 struct fxp_softc *sc = xsc; 1926 1927 FXP_LOCK(sc); 1928 fxp_init_body(sc); 1929 FXP_UNLOCK(sc); 1930 } 1931 1932 /* 1933 * Perform device initialization. This routine must be called with the 1934 * softc lock held. 1935 */ 1936 static void 1937 fxp_init_body(struct fxp_softc *sc) 1938 { 1939 struct ifnet *ifp = &sc->sc_if; 1940 struct fxp_cb_config *cbp; 1941 struct fxp_cb_ias *cb_ias; 1942 struct fxp_cb_tx *tcbp; 1943 struct fxp_tx *txp; 1944 struct fxp_cb_mcs *mcsp; 1945 int i, prm, s; 1946 1947 FXP_LOCK_ASSERT(sc, MA_OWNED); 1948 s = splimp(); 1949 /* 1950 * Cancel any pending I/O 1951 */ 1952 fxp_stop(sc); 1953 1954 prm = (ifp->if_flags & IFF_PROMISC) ? 1 : 0; 1955 1956 /* 1957 * Initialize base of CBL and RFA memory. Loading with zero 1958 * sets it up for regular linear addressing. 1959 */ 1960 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 0); 1961 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_BASE); 1962 1963 fxp_scb_wait(sc); 1964 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_BASE); 1965 1966 /* 1967 * Initialize base of dump-stats buffer. 1968 */ 1969 fxp_scb_wait(sc); 1970 bus_dmamap_sync(sc->fxp_stag, sc->fxp_smap, BUS_DMASYNC_PREREAD); 1971 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->stats_addr); 1972 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_DUMP_ADR); 1973 1974 /* 1975 * Attempt to load microcode if requested. 1976 */ 1977 if (ifp->if_flags & IFF_LINK0 && (sc->flags & FXP_FLAG_UCODE) == 0) 1978 fxp_load_ucode(sc); 1979 1980 /* 1981 * Initialize the multicast address list. 1982 */ 1983 if (fxp_mc_addrs(sc)) { 1984 mcsp = sc->mcsp; 1985 mcsp->cb_status = 0; 1986 mcsp->cb_command = 1987 htole16(FXP_CB_COMMAND_MCAS | FXP_CB_COMMAND_EL); 1988 mcsp->link_addr = 0xffffffff; 1989 /* 1990 * Start the multicast setup command. 1991 */ 1992 fxp_scb_wait(sc); 1993 bus_dmamap_sync(sc->mcs_tag, sc->mcs_map, BUS_DMASYNC_PREWRITE); 1994 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->mcs_addr); 1995 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 1996 /* ...and wait for it to complete. */ 1997 fxp_dma_wait(sc, &mcsp->cb_status, sc->mcs_tag, sc->mcs_map); 1998 bus_dmamap_sync(sc->mcs_tag, sc->mcs_map, 1999 BUS_DMASYNC_POSTWRITE); 2000 } 2001 2002 /* 2003 * We temporarily use memory that contains the TxCB list to 2004 * construct the config CB. The TxCB list memory is rebuilt 2005 * later. 2006 */ 2007 cbp = (struct fxp_cb_config *)sc->fxp_desc.cbl_list; 2008 2009 /* 2010 * This bcopy is kind of disgusting, but there are a bunch of must be 2011 * zero and must be one bits in this structure and this is the easiest 2012 * way to initialize them all to proper values. 2013 */ 2014 bcopy(fxp_cb_config_template, cbp, sizeof(fxp_cb_config_template)); 2015 2016 cbp->cb_status = 0; 2017 cbp->cb_command = htole16(FXP_CB_COMMAND_CONFIG | 2018 FXP_CB_COMMAND_EL); 2019 cbp->link_addr = 0xffffffff; /* (no) next command */ 2020 cbp->byte_count = sc->flags & FXP_FLAG_EXT_RFA ? 32 : 22; 2021 cbp->rx_fifo_limit = 8; /* rx fifo threshold (32 bytes) */ 2022 cbp->tx_fifo_limit = 0; /* tx fifo threshold (0 bytes) */ 2023 cbp->adaptive_ifs = 0; /* (no) adaptive interframe spacing */ 2024 cbp->mwi_enable = sc->flags & FXP_FLAG_MWI_ENABLE ? 1 : 0; 2025 cbp->type_enable = 0; /* actually reserved */ 2026 cbp->read_align_en = sc->flags & FXP_FLAG_READ_ALIGN ? 1 : 0; 2027 cbp->end_wr_on_cl = sc->flags & FXP_FLAG_WRITE_ALIGN ? 1 : 0; 2028 cbp->rx_dma_bytecount = 0; /* (no) rx DMA max */ 2029 cbp->tx_dma_bytecount = 0; /* (no) tx DMA max */ 2030 cbp->dma_mbce = 0; /* (disable) dma max counters */ 2031 cbp->late_scb = 0; /* (don't) defer SCB update */ 2032 cbp->direct_dma_dis = 1; /* disable direct rcv dma mode */ 2033 cbp->tno_int_or_tco_en =0; /* (disable) tx not okay interrupt */ 2034 cbp->ci_int = 1; /* interrupt on CU idle */ 2035 cbp->ext_txcb_dis = sc->flags & FXP_FLAG_EXT_TXCB ? 0 : 1; 2036 cbp->ext_stats_dis = 1; /* disable extended counters */ 2037 cbp->keep_overrun_rx = 0; /* don't pass overrun frames to host */ 2038 cbp->save_bf = sc->flags & FXP_FLAG_SAVE_BAD ? 1 : prm; 2039 cbp->disc_short_rx = !prm; /* discard short packets */ 2040 cbp->underrun_retry = 1; /* retry mode (once) on DMA underrun */ 2041 cbp->two_frames = 0; /* do not limit FIFO to 2 frames */ 2042 cbp->dyn_tbd = 0; /* (no) dynamic TBD mode */ 2043 cbp->ext_rfa = sc->flags & FXP_FLAG_EXT_RFA ? 1 : 0; 2044 cbp->mediatype = sc->flags & FXP_FLAG_SERIAL_MEDIA ? 0 : 1; 2045 cbp->csma_dis = 0; /* (don't) disable link */ 2046 cbp->tcp_udp_cksum = 0; /* (don't) enable checksum */ 2047 cbp->vlan_tco = 0; /* (don't) enable vlan wakeup */ 2048 cbp->link_wake_en = 0; /* (don't) assert PME# on link change */ 2049 cbp->arp_wake_en = 0; /* (don't) assert PME# on arp */ 2050 cbp->mc_wake_en = 0; /* (don't) enable PME# on mcmatch */ 2051 cbp->nsai = 1; /* (don't) disable source addr insert */ 2052 cbp->preamble_length = 2; /* (7 byte) preamble */ 2053 cbp->loopback = 0; /* (don't) loopback */ 2054 cbp->linear_priority = 0; /* (normal CSMA/CD operation) */ 2055 cbp->linear_pri_mode = 0; /* (wait after xmit only) */ 2056 cbp->interfrm_spacing = 6; /* (96 bits of) interframe spacing */ 2057 cbp->promiscuous = prm; /* promiscuous mode */ 2058 cbp->bcast_disable = 0; /* (don't) disable broadcasts */ 2059 cbp->wait_after_win = 0; /* (don't) enable modified backoff alg*/ 2060 cbp->ignore_ul = 0; /* consider U/L bit in IA matching */ 2061 cbp->crc16_en = 0; /* (don't) enable crc-16 algorithm */ 2062 cbp->crscdt = sc->flags & FXP_FLAG_SERIAL_MEDIA ? 1 : 0; 2063 2064 cbp->stripping = !prm; /* truncate rx packet to byte count */ 2065 cbp->padding = 1; /* (do) pad short tx packets */ 2066 cbp->rcv_crc_xfer = 0; /* (don't) xfer CRC to host */ 2067 cbp->long_rx_en = sc->flags & FXP_FLAG_LONG_PKT_EN ? 1 : 0; 2068 cbp->ia_wake_en = 0; /* (don't) wake up on address match */ 2069 cbp->magic_pkt_dis = 0; /* (don't) disable magic packet */ 2070 /* must set wake_en in PMCSR also */ 2071 cbp->force_fdx = 0; /* (don't) force full duplex */ 2072 cbp->fdx_pin_en = 1; /* (enable) FDX# pin */ 2073 cbp->multi_ia = 0; /* (don't) accept multiple IAs */ 2074 cbp->mc_all = sc->flags & FXP_FLAG_ALL_MCAST ? 1 : 0; 2075 cbp->gamla_rx = sc->flags & FXP_FLAG_EXT_RFA ? 1 : 0; 2076 2077 if (sc->tunable_noflow || sc->revision == FXP_REV_82557) { 2078 /* 2079 * The 82557 has no hardware flow control, the values 2080 * below are the defaults for the chip. 2081 */ 2082 cbp->fc_delay_lsb = 0; 2083 cbp->fc_delay_msb = 0x40; 2084 cbp->pri_fc_thresh = 3; 2085 cbp->tx_fc_dis = 0; 2086 cbp->rx_fc_restop = 0; 2087 cbp->rx_fc_restart = 0; 2088 cbp->fc_filter = 0; 2089 cbp->pri_fc_loc = 1; 2090 } else { 2091 cbp->fc_delay_lsb = 0x1f; 2092 cbp->fc_delay_msb = 0x01; 2093 cbp->pri_fc_thresh = 3; 2094 cbp->tx_fc_dis = 0; /* enable transmit FC */ 2095 cbp->rx_fc_restop = 1; /* enable FC restop frames */ 2096 cbp->rx_fc_restart = 1; /* enable FC restart frames */ 2097 cbp->fc_filter = !prm; /* drop FC frames to host */ 2098 cbp->pri_fc_loc = 1; /* FC pri location (byte31) */ 2099 } 2100 2101 /* 2102 * Start the config command/DMA. 2103 */ 2104 fxp_scb_wait(sc); 2105 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE); 2106 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->fxp_desc.cbl_addr); 2107 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2108 /* ...and wait for it to complete. */ 2109 fxp_dma_wait(sc, &cbp->cb_status, sc->cbl_tag, sc->cbl_map); 2110 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_POSTWRITE); 2111 2112 /* 2113 * Now initialize the station address. Temporarily use the TxCB 2114 * memory area like we did above for the config CB. 2115 */ 2116 cb_ias = (struct fxp_cb_ias *)sc->fxp_desc.cbl_list; 2117 cb_ias->cb_status = 0; 2118 cb_ias->cb_command = htole16(FXP_CB_COMMAND_IAS | FXP_CB_COMMAND_EL); 2119 cb_ias->link_addr = 0xffffffff; 2120 bcopy(sc->arpcom.ac_enaddr, cb_ias->macaddr, 2121 sizeof(sc->arpcom.ac_enaddr)); 2122 2123 /* 2124 * Start the IAS (Individual Address Setup) command/DMA. 2125 */ 2126 fxp_scb_wait(sc); 2127 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE); 2128 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2129 /* ...and wait for it to complete. */ 2130 fxp_dma_wait(sc, &cb_ias->cb_status, sc->cbl_tag, sc->cbl_map); 2131 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_POSTWRITE); 2132 2133 /* 2134 * Initialize transmit control block (TxCB) list. 2135 */ 2136 txp = sc->fxp_desc.tx_list; 2137 tcbp = sc->fxp_desc.cbl_list; 2138 bzero(tcbp, FXP_TXCB_SZ); 2139 for (i = 0; i < FXP_NTXCB; i++) { 2140 txp[i].tx_mbuf = NULL; 2141 tcbp[i].cb_status = htole16(FXP_CB_STATUS_C | FXP_CB_STATUS_OK); 2142 tcbp[i].cb_command = htole16(FXP_CB_COMMAND_NOP); 2143 tcbp[i].link_addr = htole32(sc->fxp_desc.cbl_addr + 2144 (((i + 1) & FXP_TXCB_MASK) * sizeof(struct fxp_cb_tx))); 2145 if (sc->flags & FXP_FLAG_EXT_TXCB) 2146 tcbp[i].tbd_array_addr = 2147 htole32(FXP_TXCB_DMA_ADDR(sc, &tcbp[i].tbd[2])); 2148 else 2149 tcbp[i].tbd_array_addr = 2150 htole32(FXP_TXCB_DMA_ADDR(sc, &tcbp[i].tbd[0])); 2151 txp[i].tx_next = &txp[(i + 1) & FXP_TXCB_MASK]; 2152 } 2153 /* 2154 * Set the suspend flag on the first TxCB and start the control 2155 * unit. It will execute the NOP and then suspend. 2156 */ 2157 tcbp->cb_command = htole16(FXP_CB_COMMAND_NOP | FXP_CB_COMMAND_S); 2158 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE); 2159 sc->fxp_desc.tx_first = sc->fxp_desc.tx_last = txp; 2160 sc->tx_queued = 1; 2161 2162 fxp_scb_wait(sc); 2163 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2164 2165 /* 2166 * Initialize receiver buffer area - RFA. 2167 */ 2168 fxp_scb_wait(sc); 2169 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->fxp_desc.rx_head->rx_addr); 2170 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_START); 2171 2172 /* 2173 * Set current media. 2174 */ 2175 if (sc->miibus != NULL) 2176 mii_mediachg(device_get_softc(sc->miibus)); 2177 2178 ifp->if_flags |= IFF_RUNNING; 2179 ifp->if_flags &= ~IFF_OACTIVE; 2180 2181 /* 2182 * Enable interrupts. 2183 */ 2184 #ifdef DEVICE_POLLING 2185 /* 2186 * ... but only do that if we are not polling. And because (presumably) 2187 * the default is interrupts on, we need to disable them explicitly! 2188 */ 2189 if ( ifp->if_flags & IFF_POLLING ) 2190 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE); 2191 else 2192 #endif /* DEVICE_POLLING */ 2193 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, 0); 2194 2195 /* 2196 * Start stats updater. 2197 */ 2198 callout_reset(&sc->stat_ch, hz, fxp_tick, sc); 2199 splx(s); 2200 } 2201 2202 static int 2203 fxp_serial_ifmedia_upd(struct ifnet *ifp) 2204 { 2205 2206 return (0); 2207 } 2208 2209 static void 2210 fxp_serial_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 2211 { 2212 2213 ifmr->ifm_active = IFM_ETHER|IFM_MANUAL; 2214 } 2215 2216 /* 2217 * Change media according to request. 2218 */ 2219 static int 2220 fxp_ifmedia_upd(struct ifnet *ifp) 2221 { 2222 struct fxp_softc *sc = ifp->if_softc; 2223 struct mii_data *mii; 2224 2225 mii = device_get_softc(sc->miibus); 2226 mii_mediachg(mii); 2227 return (0); 2228 } 2229 2230 /* 2231 * Notify the world which media we're using. 2232 */ 2233 static void 2234 fxp_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 2235 { 2236 struct fxp_softc *sc = ifp->if_softc; 2237 struct mii_data *mii; 2238 2239 mii = device_get_softc(sc->miibus); 2240 mii_pollstat(mii); 2241 ifmr->ifm_active = mii->mii_media_active; 2242 ifmr->ifm_status = mii->mii_media_status; 2243 2244 if (ifmr->ifm_status & IFM_10_T && sc->flags & FXP_FLAG_CU_RESUME_BUG) 2245 sc->cu_resume_bug = 1; 2246 else 2247 sc->cu_resume_bug = 0; 2248 } 2249 2250 /* 2251 * Add a buffer to the end of the RFA buffer list. 2252 * Return 0 if successful, 1 for failure. A failure results in 2253 * adding the 'oldm' (if non-NULL) on to the end of the list - 2254 * tossing out its old contents and recycling it. 2255 * The RFA struct is stuck at the beginning of mbuf cluster and the 2256 * data pointer is fixed up to point just past it. 2257 */ 2258 static int 2259 fxp_add_rfabuf(struct fxp_softc *sc, struct fxp_rx *rxp) 2260 { 2261 struct mbuf *m; 2262 struct fxp_rfa *rfa, *p_rfa; 2263 struct fxp_rx *p_rx; 2264 bus_dmamap_t tmp_map; 2265 int error; 2266 2267 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 2268 if (m == NULL) 2269 return (ENOBUFS); 2270 2271 /* 2272 * Move the data pointer up so that the incoming data packet 2273 * will be 32-bit aligned. 2274 */ 2275 m->m_data += RFA_ALIGNMENT_FUDGE; 2276 2277 /* 2278 * Get a pointer to the base of the mbuf cluster and move 2279 * data start past it. 2280 */ 2281 rfa = mtod(m, struct fxp_rfa *); 2282 m->m_data += sc->rfa_size; 2283 rfa->size = htole16(MCLBYTES - sc->rfa_size - RFA_ALIGNMENT_FUDGE); 2284 2285 rfa->rfa_status = 0; 2286 rfa->rfa_control = htole16(FXP_RFA_CONTROL_EL); 2287 rfa->actual_size = 0; 2288 2289 /* 2290 * Initialize the rest of the RFA. Note that since the RFA 2291 * is misaligned, we cannot store values directly. We're thus 2292 * using the le32enc() function which handles endianness and 2293 * is also alignment-safe. 2294 */ 2295 le32enc(&rfa->link_addr, 0xffffffff); 2296 le32enc(&rfa->rbd_addr, 0xffffffff); 2297 2298 /* Map the RFA into DMA memory. */ 2299 error = bus_dmamap_load(sc->fxp_mtag, sc->spare_map, rfa, 2300 MCLBYTES - RFA_ALIGNMENT_FUDGE, fxp_dma_map_addr, 2301 &rxp->rx_addr, 0); 2302 if (error) { 2303 m_freem(m); 2304 return (error); 2305 } 2306 2307 bus_dmamap_unload(sc->fxp_mtag, rxp->rx_map); 2308 tmp_map = sc->spare_map; 2309 sc->spare_map = rxp->rx_map; 2310 rxp->rx_map = tmp_map; 2311 rxp->rx_mbuf = m; 2312 2313 bus_dmamap_sync(sc->fxp_mtag, rxp->rx_map, 2314 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2315 2316 /* 2317 * If there are other buffers already on the list, attach this 2318 * one to the end by fixing up the tail to point to this one. 2319 */ 2320 if (sc->fxp_desc.rx_head != NULL) { 2321 p_rx = sc->fxp_desc.rx_tail; 2322 p_rfa = (struct fxp_rfa *) 2323 (p_rx->rx_mbuf->m_ext.ext_buf + RFA_ALIGNMENT_FUDGE); 2324 p_rx->rx_next = rxp; 2325 le32enc(&p_rfa->link_addr, rxp->rx_addr); 2326 p_rfa->rfa_control = 0; 2327 bus_dmamap_sync(sc->fxp_mtag, p_rx->rx_map, 2328 BUS_DMASYNC_PREWRITE); 2329 } else { 2330 rxp->rx_next = NULL; 2331 sc->fxp_desc.rx_head = rxp; 2332 } 2333 sc->fxp_desc.rx_tail = rxp; 2334 return (0); 2335 } 2336 2337 static volatile int 2338 fxp_miibus_readreg(device_t dev, int phy, int reg) 2339 { 2340 struct fxp_softc *sc = device_get_softc(dev); 2341 int count = 10000; 2342 int value; 2343 2344 CSR_WRITE_4(sc, FXP_CSR_MDICONTROL, 2345 (FXP_MDI_READ << 26) | (reg << 16) | (phy << 21)); 2346 2347 while (((value = CSR_READ_4(sc, FXP_CSR_MDICONTROL)) & 0x10000000) == 0 2348 && count--) 2349 DELAY(10); 2350 2351 if (count <= 0) 2352 device_printf(dev, "fxp_miibus_readreg: timed out\n"); 2353 2354 return (value & 0xffff); 2355 } 2356 2357 static void 2358 fxp_miibus_writereg(device_t dev, int phy, int reg, int value) 2359 { 2360 struct fxp_softc *sc = device_get_softc(dev); 2361 int count = 10000; 2362 2363 CSR_WRITE_4(sc, FXP_CSR_MDICONTROL, 2364 (FXP_MDI_WRITE << 26) | (reg << 16) | (phy << 21) | 2365 (value & 0xffff)); 2366 2367 while ((CSR_READ_4(sc, FXP_CSR_MDICONTROL) & 0x10000000) == 0 && 2368 count--) 2369 DELAY(10); 2370 2371 if (count <= 0) 2372 device_printf(dev, "fxp_miibus_writereg: timed out\n"); 2373 } 2374 2375 static int 2376 fxp_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 2377 { 2378 struct fxp_softc *sc = ifp->if_softc; 2379 struct ifreq *ifr = (struct ifreq *)data; 2380 struct mii_data *mii; 2381 int flag, mask, s, error = 0; 2382 2383 /* 2384 * Detaching causes us to call ioctl with the mutex owned. Preclude 2385 * that by saying we're busy if the lock is already held. 2386 */ 2387 if (FXP_LOCKED(sc)) 2388 return (EBUSY); 2389 2390 FXP_LOCK(sc); 2391 s = splimp(); 2392 2393 switch (command) { 2394 case SIOCSIFFLAGS: 2395 if (ifp->if_flags & IFF_ALLMULTI) 2396 sc->flags |= FXP_FLAG_ALL_MCAST; 2397 else 2398 sc->flags &= ~FXP_FLAG_ALL_MCAST; 2399 2400 /* 2401 * If interface is marked up and not running, then start it. 2402 * If it is marked down and running, stop it. 2403 * XXX If it's up then re-initialize it. This is so flags 2404 * such as IFF_PROMISC are handled. 2405 */ 2406 if (ifp->if_flags & IFF_UP) { 2407 fxp_init_body(sc); 2408 } else { 2409 if (ifp->if_flags & IFF_RUNNING) 2410 fxp_stop(sc); 2411 } 2412 break; 2413 2414 case SIOCADDMULTI: 2415 case SIOCDELMULTI: 2416 if (ifp->if_flags & IFF_ALLMULTI) 2417 sc->flags |= FXP_FLAG_ALL_MCAST; 2418 else 2419 sc->flags &= ~FXP_FLAG_ALL_MCAST; 2420 /* 2421 * Multicast list has changed; set the hardware filter 2422 * accordingly. 2423 */ 2424 if ((sc->flags & FXP_FLAG_ALL_MCAST) == 0) 2425 fxp_mc_setup(sc); 2426 /* 2427 * fxp_mc_setup() can set FXP_FLAG_ALL_MCAST, so check it 2428 * again rather than else {}. 2429 */ 2430 if (sc->flags & FXP_FLAG_ALL_MCAST) 2431 fxp_init_body(sc); 2432 error = 0; 2433 break; 2434 2435 case SIOCSIFMEDIA: 2436 case SIOCGIFMEDIA: 2437 if (sc->miibus != NULL) { 2438 mii = device_get_softc(sc->miibus); 2439 error = ifmedia_ioctl(ifp, ifr, 2440 &mii->mii_media, command); 2441 } else { 2442 error = ifmedia_ioctl(ifp, ifr, &sc->sc_media, command); 2443 } 2444 break; 2445 2446 case SIOCSIFCAP: 2447 mask = ifp->if_capenable ^ ifr->ifr_reqcap; 2448 if (mask & IFCAP_POLLING) 2449 ifp->if_capenable ^= IFCAP_POLLING; 2450 if (mask & IFCAP_VLAN_MTU) { 2451 ifp->if_capenable ^= IFCAP_VLAN_MTU; 2452 if (sc->revision != FXP_REV_82557) 2453 flag = FXP_FLAG_LONG_PKT_EN; 2454 else /* a hack to get long frames on the old chip */ 2455 flag = FXP_FLAG_SAVE_BAD; 2456 sc->flags ^= flag; 2457 if (ifp->if_flags & IFF_UP) 2458 fxp_init_body(sc); 2459 } 2460 break; 2461 2462 default: 2463 /* 2464 * ether_ioctl() will eventually call fxp_start() which 2465 * will result in mutex recursion so drop it first. 2466 */ 2467 FXP_UNLOCK(sc); 2468 error = ether_ioctl(ifp, command, data); 2469 } 2470 if (FXP_LOCKED(sc)) 2471 FXP_UNLOCK(sc); 2472 splx(s); 2473 return (error); 2474 } 2475 2476 /* 2477 * Fill in the multicast address list and return number of entries. 2478 */ 2479 static int 2480 fxp_mc_addrs(struct fxp_softc *sc) 2481 { 2482 struct fxp_cb_mcs *mcsp = sc->mcsp; 2483 struct ifnet *ifp = &sc->sc_if; 2484 struct ifmultiaddr *ifma; 2485 int nmcasts; 2486 2487 nmcasts = 0; 2488 if ((sc->flags & FXP_FLAG_ALL_MCAST) == 0) { 2489 #if __FreeBSD_version < 500000 2490 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 2491 #else 2492 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 2493 #endif 2494 if (ifma->ifma_addr->sa_family != AF_LINK) 2495 continue; 2496 if (nmcasts >= MAXMCADDR) { 2497 sc->flags |= FXP_FLAG_ALL_MCAST; 2498 nmcasts = 0; 2499 break; 2500 } 2501 bcopy(LLADDR((struct sockaddr_dl *)ifma->ifma_addr), 2502 &sc->mcsp->mc_addr[nmcasts][0], ETHER_ADDR_LEN); 2503 nmcasts++; 2504 } 2505 } 2506 mcsp->mc_cnt = htole16(nmcasts * ETHER_ADDR_LEN); 2507 return (nmcasts); 2508 } 2509 2510 /* 2511 * Program the multicast filter. 2512 * 2513 * We have an artificial restriction that the multicast setup command 2514 * must be the first command in the chain, so we take steps to ensure 2515 * this. By requiring this, it allows us to keep up the performance of 2516 * the pre-initialized command ring (esp. link pointers) by not actually 2517 * inserting the mcsetup command in the ring - i.e. its link pointer 2518 * points to the TxCB ring, but the mcsetup descriptor itself is not part 2519 * of it. We then can do 'CU_START' on the mcsetup descriptor and have it 2520 * lead into the regular TxCB ring when it completes. 2521 * 2522 * This function must be called at splimp. 2523 */ 2524 static void 2525 fxp_mc_setup(struct fxp_softc *sc) 2526 { 2527 struct fxp_cb_mcs *mcsp = sc->mcsp; 2528 struct ifnet *ifp = &sc->sc_if; 2529 struct fxp_tx *txp; 2530 int count; 2531 2532 FXP_LOCK_ASSERT(sc, MA_OWNED); 2533 /* 2534 * If there are queued commands, we must wait until they are all 2535 * completed. If we are already waiting, then add a NOP command 2536 * with interrupt option so that we're notified when all commands 2537 * have been completed - fxp_start() ensures that no additional 2538 * TX commands will be added when need_mcsetup is true. 2539 */ 2540 if (sc->tx_queued) { 2541 /* 2542 * need_mcsetup will be true if we are already waiting for the 2543 * NOP command to be completed (see below). In this case, bail. 2544 */ 2545 if (sc->need_mcsetup) 2546 return; 2547 sc->need_mcsetup = 1; 2548 2549 /* 2550 * Add a NOP command with interrupt so that we are notified 2551 * when all TX commands have been processed. 2552 */ 2553 txp = sc->fxp_desc.tx_last->tx_next; 2554 txp->tx_mbuf = NULL; 2555 txp->tx_cb->cb_status = 0; 2556 txp->tx_cb->cb_command = htole16(FXP_CB_COMMAND_NOP | 2557 FXP_CB_COMMAND_S | FXP_CB_COMMAND_I); 2558 /* 2559 * Advance the end of list forward. 2560 */ 2561 sc->fxp_desc.tx_last->tx_cb->cb_command &= 2562 htole16(~FXP_CB_COMMAND_S); 2563 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE); 2564 sc->fxp_desc.tx_last = txp; 2565 sc->tx_queued++; 2566 /* 2567 * Issue a resume in case the CU has just suspended. 2568 */ 2569 fxp_scb_wait(sc); 2570 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_RESUME); 2571 /* 2572 * Set a 5 second timer just in case we don't hear from the 2573 * card again. 2574 */ 2575 ifp->if_timer = 5; 2576 2577 return; 2578 } 2579 sc->need_mcsetup = 0; 2580 2581 /* 2582 * Initialize multicast setup descriptor. 2583 */ 2584 mcsp->cb_status = 0; 2585 mcsp->cb_command = htole16(FXP_CB_COMMAND_MCAS | 2586 FXP_CB_COMMAND_S | FXP_CB_COMMAND_I); 2587 mcsp->link_addr = htole32(sc->fxp_desc.cbl_addr); 2588 txp = &sc->fxp_desc.mcs_tx; 2589 txp->tx_mbuf = NULL; 2590 txp->tx_cb = (struct fxp_cb_tx *)sc->mcsp; 2591 txp->tx_next = sc->fxp_desc.tx_list; 2592 (void) fxp_mc_addrs(sc); 2593 sc->fxp_desc.tx_first = sc->fxp_desc.tx_last = txp; 2594 sc->tx_queued = 1; 2595 2596 /* 2597 * Wait until command unit is not active. This should never 2598 * be the case when nothing is queued, but make sure anyway. 2599 */ 2600 count = 100; 2601 while ((CSR_READ_1(sc, FXP_CSR_SCB_RUSCUS) >> 6) == 2602 FXP_SCB_CUS_ACTIVE && --count) 2603 DELAY(10); 2604 if (count == 0) { 2605 device_printf(sc->dev, "command queue timeout\n"); 2606 return; 2607 } 2608 2609 /* 2610 * Start the multicast setup command. 2611 */ 2612 fxp_scb_wait(sc); 2613 bus_dmamap_sync(sc->mcs_tag, sc->mcs_map, BUS_DMASYNC_PREWRITE); 2614 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->mcs_addr); 2615 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2616 2617 ifp->if_timer = 2; 2618 return; 2619 } 2620 2621 static uint32_t fxp_ucode_d101a[] = D101_A_RCVBUNDLE_UCODE; 2622 static uint32_t fxp_ucode_d101b0[] = D101_B0_RCVBUNDLE_UCODE; 2623 static uint32_t fxp_ucode_d101ma[] = D101M_B_RCVBUNDLE_UCODE; 2624 static uint32_t fxp_ucode_d101s[] = D101S_RCVBUNDLE_UCODE; 2625 static uint32_t fxp_ucode_d102[] = D102_B_RCVBUNDLE_UCODE; 2626 static uint32_t fxp_ucode_d102c[] = D102_C_RCVBUNDLE_UCODE; 2627 static uint32_t fxp_ucode_d102e[] = D102_E_RCVBUNDLE_UCODE; 2628 2629 #define UCODE(x) x, sizeof(x)/sizeof(uint32_t) 2630 2631 struct ucode { 2632 uint32_t revision; 2633 uint32_t *ucode; 2634 int length; 2635 u_short int_delay_offset; 2636 u_short bundle_max_offset; 2637 } ucode_table[] = { 2638 { FXP_REV_82558_A4, UCODE(fxp_ucode_d101a), D101_CPUSAVER_DWORD, 0 }, 2639 { FXP_REV_82558_B0, UCODE(fxp_ucode_d101b0), D101_CPUSAVER_DWORD, 0 }, 2640 { FXP_REV_82559_A0, UCODE(fxp_ucode_d101ma), 2641 D101M_CPUSAVER_DWORD, D101M_CPUSAVER_BUNDLE_MAX_DWORD }, 2642 { FXP_REV_82559S_A, UCODE(fxp_ucode_d101s), 2643 D101S_CPUSAVER_DWORD, D101S_CPUSAVER_BUNDLE_MAX_DWORD }, 2644 { FXP_REV_82550, UCODE(fxp_ucode_d102), 2645 D102_B_CPUSAVER_DWORD, D102_B_CPUSAVER_BUNDLE_MAX_DWORD }, 2646 { FXP_REV_82550_C, UCODE(fxp_ucode_d102c), 2647 D102_C_CPUSAVER_DWORD, D102_C_CPUSAVER_BUNDLE_MAX_DWORD }, 2648 { FXP_REV_82551_F, UCODE(fxp_ucode_d102e), 2649 D102_E_CPUSAVER_DWORD, D102_E_CPUSAVER_BUNDLE_MAX_DWORD }, 2650 { 0, NULL, 0, 0, 0 } 2651 }; 2652 2653 static void 2654 fxp_load_ucode(struct fxp_softc *sc) 2655 { 2656 struct ucode *uc; 2657 struct fxp_cb_ucode *cbp; 2658 int i; 2659 2660 for (uc = ucode_table; uc->ucode != NULL; uc++) 2661 if (sc->revision == uc->revision) 2662 break; 2663 if (uc->ucode == NULL) 2664 return; 2665 cbp = (struct fxp_cb_ucode *)sc->fxp_desc.cbl_list; 2666 cbp->cb_status = 0; 2667 cbp->cb_command = htole16(FXP_CB_COMMAND_UCODE | FXP_CB_COMMAND_EL); 2668 cbp->link_addr = 0xffffffff; /* (no) next command */ 2669 for (i = 0; i < uc->length; i++) 2670 cbp->ucode[i] = htole32(uc->ucode[i]); 2671 if (uc->int_delay_offset) 2672 *(uint16_t *)&cbp->ucode[uc->int_delay_offset] = 2673 htole16(sc->tunable_int_delay + sc->tunable_int_delay / 2); 2674 if (uc->bundle_max_offset) 2675 *(uint16_t *)&cbp->ucode[uc->bundle_max_offset] = 2676 htole16(sc->tunable_bundle_max); 2677 /* 2678 * Download the ucode to the chip. 2679 */ 2680 fxp_scb_wait(sc); 2681 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE); 2682 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->fxp_desc.cbl_addr); 2683 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2684 /* ...and wait for it to complete. */ 2685 fxp_dma_wait(sc, &cbp->cb_status, sc->cbl_tag, sc->cbl_map); 2686 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_POSTWRITE); 2687 device_printf(sc->dev, 2688 "Microcode loaded, int_delay: %d usec bundle_max: %d\n", 2689 sc->tunable_int_delay, 2690 uc->bundle_max_offset == 0 ? 0 : sc->tunable_bundle_max); 2691 sc->flags |= FXP_FLAG_UCODE; 2692 } 2693 2694 static int 2695 sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high) 2696 { 2697 int error, value; 2698 2699 value = *(int *)arg1; 2700 error = sysctl_handle_int(oidp, &value, 0, req); 2701 if (error || !req->newptr) 2702 return (error); 2703 if (value < low || value > high) 2704 return (EINVAL); 2705 *(int *)arg1 = value; 2706 return (0); 2707 } 2708 2709 /* 2710 * Interrupt delay is expressed in microseconds, a multiplier is used 2711 * to convert this to the appropriate clock ticks before using. 2712 */ 2713 static int 2714 sysctl_hw_fxp_int_delay(SYSCTL_HANDLER_ARGS) 2715 { 2716 return (sysctl_int_range(oidp, arg1, arg2, req, 300, 3000)); 2717 } 2718 2719 static int 2720 sysctl_hw_fxp_bundle_max(SYSCTL_HANDLER_ARGS) 2721 { 2722 return (sysctl_int_range(oidp, arg1, arg2, req, 1, 0xffff)); 2723 } 2724