1 /*- 2 * Copyright (c) 1995, David Greenman 3 * Copyright (c) 2001 Jonathan Lemon <jlemon@freebsd.org> 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice unmodified, this list of conditions, and the following 11 * disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 * 28 */ 29 30 #include <sys/cdefs.h> 31 __FBSDID("$FreeBSD$"); 32 33 /* 34 * Intel EtherExpress Pro/100B PCI Fast Ethernet driver 35 */ 36 37 #include <sys/cdefs.h> 38 __FBSDID("$FreeBSD$"); 39 40 #include <sys/param.h> 41 #include <sys/systm.h> 42 #include <sys/endian.h> 43 #include <sys/mbuf.h> 44 /* #include <sys/mutex.h> */ 45 #include <sys/kernel.h> 46 #include <sys/socket.h> 47 #include <sys/sysctl.h> 48 49 #include <net/if.h> 50 #include <net/if_dl.h> 51 #include <net/if_media.h> 52 53 #include <net/bpf.h> 54 #include <sys/sockio.h> 55 #include <sys/bus.h> 56 #include <machine/bus.h> 57 #include <sys/rman.h> 58 #include <machine/resource.h> 59 60 #include <net/ethernet.h> 61 #include <net/if_arp.h> 62 63 #include <machine/clock.h> /* for DELAY */ 64 65 #include <net/if_types.h> 66 #include <net/if_vlan_var.h> 67 68 #ifdef FXP_IP_CSUM_WAR 69 #include <netinet/in.h> 70 #include <netinet/in_systm.h> 71 #include <netinet/ip.h> 72 #include <machine/in_cksum.h> 73 #endif 74 75 #include <dev/pci/pcivar.h> 76 #include <dev/pci/pcireg.h> /* for PCIM_CMD_xxx */ 77 78 #include <dev/mii/mii.h> 79 #include <dev/mii/miivar.h> 80 81 #include <dev/fxp/if_fxpreg.h> 82 #include <dev/fxp/if_fxpvar.h> 83 #include <dev/fxp/rcvbundl.h> 84 85 MODULE_DEPEND(fxp, pci, 1, 1, 1); 86 MODULE_DEPEND(fxp, ether, 1, 1, 1); 87 MODULE_DEPEND(fxp, miibus, 1, 1, 1); 88 #include "miibus_if.h" 89 90 /* 91 * NOTE! On the Alpha, we have an alignment constraint. The 92 * card DMAs the packet immediately following the RFA. However, 93 * the first thing in the packet is a 14-byte Ethernet header. 94 * This means that the packet is misaligned. To compensate, 95 * we actually offset the RFA 2 bytes into the cluster. This 96 * alignes the packet after the Ethernet header at a 32-bit 97 * boundary. HOWEVER! This means that the RFA is misaligned! 98 */ 99 #define RFA_ALIGNMENT_FUDGE 2 100 101 /* 102 * Set initial transmit threshold at 64 (512 bytes). This is 103 * increased by 64 (512 bytes) at a time, to maximum of 192 104 * (1536 bytes), if an underrun occurs. 105 */ 106 static int tx_threshold = 64; 107 108 /* 109 * The configuration byte map has several undefined fields which 110 * must be one or must be zero. Set up a template for these bits 111 * only, (assuming a 82557 chip) leaving the actual configuration 112 * to fxp_init. 113 * 114 * See struct fxp_cb_config for the bit definitions. 115 */ 116 static u_char fxp_cb_config_template[] = { 117 0x0, 0x0, /* cb_status */ 118 0x0, 0x0, /* cb_command */ 119 0x0, 0x0, 0x0, 0x0, /* link_addr */ 120 0x0, /* 0 */ 121 0x0, /* 1 */ 122 0x0, /* 2 */ 123 0x0, /* 3 */ 124 0x0, /* 4 */ 125 0x0, /* 5 */ 126 0x32, /* 6 */ 127 0x0, /* 7 */ 128 0x0, /* 8 */ 129 0x0, /* 9 */ 130 0x6, /* 10 */ 131 0x0, /* 11 */ 132 0x0, /* 12 */ 133 0x0, /* 13 */ 134 0xf2, /* 14 */ 135 0x48, /* 15 */ 136 0x0, /* 16 */ 137 0x40, /* 17 */ 138 0xf0, /* 18 */ 139 0x0, /* 19 */ 140 0x3f, /* 20 */ 141 0x5 /* 21 */ 142 }; 143 144 struct fxp_ident { 145 u_int16_t devid; 146 int16_t revid; /* -1 matches anything */ 147 char *name; 148 }; 149 150 /* 151 * Claim various Intel PCI device identifiers for this driver. The 152 * sub-vendor and sub-device field are extensively used to identify 153 * particular variants, but we don't currently differentiate between 154 * them. 155 */ 156 static struct fxp_ident fxp_ident_table[] = { 157 { 0x1029, -1, "Intel 82559 PCI/CardBus Pro/100" }, 158 { 0x1030, -1, "Intel 82559 Pro/100 Ethernet" }, 159 { 0x1031, -1, "Intel 82801CAM (ICH3) Pro/100 VE Ethernet" }, 160 { 0x1032, -1, "Intel 82801CAM (ICH3) Pro/100 VE Ethernet" }, 161 { 0x1033, -1, "Intel 82801CAM (ICH3) Pro/100 VM Ethernet" }, 162 { 0x1034, -1, "Intel 82801CAM (ICH3) Pro/100 VM Ethernet" }, 163 { 0x1035, -1, "Intel 82801CAM (ICH3) Pro/100 Ethernet" }, 164 { 0x1036, -1, "Intel 82801CAM (ICH3) Pro/100 Ethernet" }, 165 { 0x1037, -1, "Intel 82801CAM (ICH3) Pro/100 Ethernet" }, 166 { 0x1038, -1, "Intel 82801CAM (ICH3) Pro/100 VM Ethernet" }, 167 { 0x1039, -1, "Intel 82801DB (ICH4) Pro/100 VE Ethernet" }, 168 { 0x103A, -1, "Intel 82801DB (ICH4) Pro/100 Ethernet" }, 169 { 0x103B, -1, "Intel 82801DB (ICH4) Pro/100 VM Ethernet" }, 170 { 0x103C, -1, "Intel 82801DB (ICH4) Pro/100 Ethernet" }, 171 { 0x103D, -1, "Intel 82801DB (ICH4) Pro/100 VE Ethernet" }, 172 { 0x103E, -1, "Intel 82801DB (ICH4) Pro/100 VM Ethernet" }, 173 { 0x1050, -1, "Intel 82801BA (D865) Pro/100 VE Ethernet" }, 174 { 0x1059, -1, "Intel 82551QM Pro/100 M Mobile Connection" }, 175 { 0x1209, -1, "Intel 82559ER Embedded 10/100 Ethernet" }, 176 { 0x1229, 0x01, "Intel 82557 Pro/100 Ethernet" }, 177 { 0x1229, 0x02, "Intel 82557 Pro/100 Ethernet" }, 178 { 0x1229, 0x03, "Intel 82557 Pro/100 Ethernet" }, 179 { 0x1229, 0x04, "Intel 82558 Pro/100 Ethernet" }, 180 { 0x1229, 0x05, "Intel 82558 Pro/100 Ethernet" }, 181 { 0x1229, 0x06, "Intel 82559 Pro/100 Ethernet" }, 182 { 0x1229, 0x07, "Intel 82559 Pro/100 Ethernet" }, 183 { 0x1229, 0x08, "Intel 82559 Pro/100 Ethernet" }, 184 { 0x1229, 0x09, "Intel 82559ER Pro/100 Ethernet" }, 185 { 0x1229, 0x0c, "Intel 82550 Pro/100 Ethernet" }, 186 { 0x1229, 0x0d, "Intel 82550 Pro/100 Ethernet" }, 187 { 0x1229, 0x0e, "Intel 82550 Pro/100 Ethernet" }, 188 { 0x1229, 0x0f, "Intel 82551 Pro/100 Ethernet" }, 189 { 0x1229, 0x10, "Intel 82551 Pro/100 Ethernet" }, 190 { 0x1229, -1, "Intel 82557/8/9 Pro/100 Ethernet" }, 191 { 0x2449, -1, "Intel 82801BA/CAM (ICH2/3) Pro/100 Ethernet" }, 192 { 0, -1, NULL }, 193 }; 194 195 #ifdef FXP_IP_CSUM_WAR 196 #define FXP_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 197 #else 198 #define FXP_CSUM_FEATURES (CSUM_TCP | CSUM_UDP) 199 #endif 200 201 static int fxp_probe(device_t dev); 202 static int fxp_attach(device_t dev); 203 static int fxp_detach(device_t dev); 204 static int fxp_shutdown(device_t dev); 205 static int fxp_suspend(device_t dev); 206 static int fxp_resume(device_t dev); 207 208 static void fxp_intr(void *xsc); 209 static void fxp_intr_body(struct fxp_softc *sc, struct ifnet *ifp, 210 u_int8_t statack, int count); 211 static void fxp_init(void *xsc); 212 static void fxp_init_body(struct fxp_softc *sc); 213 static void fxp_tick(void *xsc); 214 #ifndef BURN_BRIDGES 215 static void fxp_powerstate_d0(device_t dev); 216 #endif 217 static void fxp_start(struct ifnet *ifp); 218 static void fxp_start_body(struct ifnet *ifp); 219 static void fxp_stop(struct fxp_softc *sc); 220 static void fxp_release(struct fxp_softc *sc); 221 static int fxp_ioctl(struct ifnet *ifp, u_long command, 222 caddr_t data); 223 static void fxp_watchdog(struct ifnet *ifp); 224 static int fxp_add_rfabuf(struct fxp_softc *sc, 225 struct fxp_rx *rxp); 226 static int fxp_mc_addrs(struct fxp_softc *sc); 227 static void fxp_mc_setup(struct fxp_softc *sc); 228 static u_int16_t fxp_eeprom_getword(struct fxp_softc *sc, int offset, 229 int autosize); 230 static void fxp_eeprom_putword(struct fxp_softc *sc, int offset, 231 u_int16_t data); 232 static void fxp_autosize_eeprom(struct fxp_softc *sc); 233 static void fxp_read_eeprom(struct fxp_softc *sc, u_short *data, 234 int offset, int words); 235 static void fxp_write_eeprom(struct fxp_softc *sc, u_short *data, 236 int offset, int words); 237 static int fxp_ifmedia_upd(struct ifnet *ifp); 238 static void fxp_ifmedia_sts(struct ifnet *ifp, 239 struct ifmediareq *ifmr); 240 static int fxp_serial_ifmedia_upd(struct ifnet *ifp); 241 static void fxp_serial_ifmedia_sts(struct ifnet *ifp, 242 struct ifmediareq *ifmr); 243 static volatile int fxp_miibus_readreg(device_t dev, int phy, int reg); 244 static void fxp_miibus_writereg(device_t dev, int phy, int reg, 245 int value); 246 static void fxp_load_ucode(struct fxp_softc *sc); 247 static int sysctl_int_range(SYSCTL_HANDLER_ARGS, 248 int low, int high); 249 static int sysctl_hw_fxp_bundle_max(SYSCTL_HANDLER_ARGS); 250 static int sysctl_hw_fxp_int_delay(SYSCTL_HANDLER_ARGS); 251 static void fxp_scb_wait(struct fxp_softc *sc); 252 static void fxp_scb_cmd(struct fxp_softc *sc, int cmd); 253 static void fxp_dma_wait(struct fxp_softc *sc, 254 volatile u_int16_t *status, bus_dma_tag_t dmat, 255 bus_dmamap_t map); 256 257 static device_method_t fxp_methods[] = { 258 /* Device interface */ 259 DEVMETHOD(device_probe, fxp_probe), 260 DEVMETHOD(device_attach, fxp_attach), 261 DEVMETHOD(device_detach, fxp_detach), 262 DEVMETHOD(device_shutdown, fxp_shutdown), 263 DEVMETHOD(device_suspend, fxp_suspend), 264 DEVMETHOD(device_resume, fxp_resume), 265 266 /* MII interface */ 267 DEVMETHOD(miibus_readreg, fxp_miibus_readreg), 268 DEVMETHOD(miibus_writereg, fxp_miibus_writereg), 269 270 { 0, 0 } 271 }; 272 273 static driver_t fxp_driver = { 274 "fxp", 275 fxp_methods, 276 sizeof(struct fxp_softc), 277 }; 278 279 static devclass_t fxp_devclass; 280 281 DRIVER_MODULE(fxp, pci, fxp_driver, fxp_devclass, 0, 0); 282 DRIVER_MODULE(miibus, fxp, miibus_driver, miibus_devclass, 0, 0); 283 284 static int fxp_rnr; 285 SYSCTL_INT(_hw, OID_AUTO, fxp_rnr, CTLFLAG_RW, &fxp_rnr, 0, "fxp rnr events"); 286 287 static int fxp_noflow; 288 SYSCTL_INT(_hw, OID_AUTO, fxp_noflow, CTLFLAG_RW, &fxp_noflow, 0, "fxp flow control disabled"); 289 TUNABLE_INT("hw.fxp_noflow", &fxp_noflow); 290 291 /* 292 * Wait for the previous command to be accepted (but not necessarily 293 * completed). 294 */ 295 static void 296 fxp_scb_wait(struct fxp_softc *sc) 297 { 298 int i = 10000; 299 300 while (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) && --i) 301 DELAY(2); 302 if (i == 0) 303 device_printf(sc->dev, "SCB timeout: 0x%x 0x%x 0x%x 0x%x\n", 304 CSR_READ_1(sc, FXP_CSR_SCB_COMMAND), 305 CSR_READ_1(sc, FXP_CSR_SCB_STATACK), 306 CSR_READ_1(sc, FXP_CSR_SCB_RUSCUS), 307 CSR_READ_2(sc, FXP_CSR_FLOWCONTROL)); 308 } 309 310 static void 311 fxp_scb_cmd(struct fxp_softc *sc, int cmd) 312 { 313 314 if (cmd == FXP_SCB_COMMAND_CU_RESUME && sc->cu_resume_bug) { 315 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_CB_COMMAND_NOP); 316 fxp_scb_wait(sc); 317 } 318 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, cmd); 319 } 320 321 static void 322 fxp_dma_wait(struct fxp_softc *sc, volatile u_int16_t *status, 323 bus_dma_tag_t dmat, bus_dmamap_t map) 324 { 325 int i = 10000; 326 327 bus_dmamap_sync(dmat, map, BUS_DMASYNC_POSTREAD); 328 while (!(le16toh(*status) & FXP_CB_STATUS_C) && --i) { 329 DELAY(2); 330 bus_dmamap_sync(dmat, map, BUS_DMASYNC_POSTREAD); 331 } 332 if (i == 0) 333 device_printf(sc->dev, "DMA timeout\n"); 334 } 335 336 /* 337 * Return identification string if this device is ours. 338 */ 339 static int 340 fxp_probe(device_t dev) 341 { 342 u_int16_t devid; 343 u_int8_t revid; 344 struct fxp_ident *ident; 345 346 if (pci_get_vendor(dev) == FXP_VENDORID_INTEL) { 347 devid = pci_get_device(dev); 348 revid = pci_get_revid(dev); 349 for (ident = fxp_ident_table; ident->name != NULL; ident++) { 350 if (ident->devid == devid && 351 (ident->revid == revid || ident->revid == -1)) { 352 device_set_desc(dev, ident->name); 353 return (0); 354 } 355 } 356 } 357 return (ENXIO); 358 } 359 360 #ifndef BURN_BRIDGES 361 static void 362 fxp_powerstate_d0(device_t dev) 363 { 364 #if __FreeBSD_version >= 430002 365 u_int32_t iobase, membase, irq; 366 367 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 368 /* Save important PCI config data. */ 369 iobase = pci_read_config(dev, FXP_PCI_IOBA, 4); 370 membase = pci_read_config(dev, FXP_PCI_MMBA, 4); 371 irq = pci_read_config(dev, PCIR_INTLINE, 4); 372 373 /* Reset the power state. */ 374 device_printf(dev, "chip is in D%d power mode " 375 "-- setting to D0\n", pci_get_powerstate(dev)); 376 377 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 378 379 /* Restore PCI config data. */ 380 pci_write_config(dev, FXP_PCI_IOBA, iobase, 4); 381 pci_write_config(dev, FXP_PCI_MMBA, membase, 4); 382 pci_write_config(dev, PCIR_INTLINE, irq, 4); 383 } 384 #endif 385 } 386 #endif 387 388 static void 389 fxp_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error) 390 { 391 u_int32_t *addr; 392 393 if (error) 394 return; 395 396 KASSERT(nseg == 1, ("too many DMA segments, %d should be 1", nseg)); 397 addr = arg; 398 *addr = segs->ds_addr; 399 } 400 401 static int 402 fxp_attach(device_t dev) 403 { 404 int error = 0; 405 struct fxp_softc *sc = device_get_softc(dev); 406 struct ifnet *ifp; 407 struct fxp_rx *rxp; 408 u_int32_t val; 409 u_int16_t data, myea[ETHER_ADDR_LEN / 2]; 410 int i, rid, m1, m2, prefer_iomap, maxtxseg; 411 int s, ipcbxmit_disable; 412 413 sc->dev = dev; 414 callout_init(&sc->stat_ch, CALLOUT_MPSAFE); 415 sysctl_ctx_init(&sc->sysctl_ctx); 416 mtx_init(&sc->sc_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 417 MTX_DEF); 418 ifmedia_init(&sc->sc_media, 0, fxp_serial_ifmedia_upd, 419 fxp_serial_ifmedia_sts); 420 421 s = splimp(); 422 423 /* 424 * Enable bus mastering. 425 */ 426 pci_enable_busmaster(dev); 427 val = pci_read_config(dev, PCIR_COMMAND, 2); 428 #ifndef BURN_BRIDGES 429 fxp_powerstate_d0(dev); 430 #endif 431 /* 432 * Figure out which we should try first - memory mapping or i/o mapping? 433 * We default to memory mapping. Then we accept an override from the 434 * command line. Then we check to see which one is enabled. 435 */ 436 m1 = PCIM_CMD_MEMEN; 437 m2 = PCIM_CMD_PORTEN; 438 prefer_iomap = 0; 439 if (resource_int_value(device_get_name(dev), device_get_unit(dev), 440 "prefer_iomap", &prefer_iomap) == 0 && prefer_iomap != 0) { 441 m1 = PCIM_CMD_PORTEN; 442 m2 = PCIM_CMD_MEMEN; 443 } 444 445 sc->rtp = (m1 == PCIM_CMD_MEMEN)? SYS_RES_MEMORY : SYS_RES_IOPORT; 446 sc->rgd = (m1 == PCIM_CMD_MEMEN)? FXP_PCI_MMBA : FXP_PCI_IOBA; 447 sc->mem = bus_alloc_resource(dev, sc->rtp, &sc->rgd, 448 0, ~0, 1, RF_ACTIVE); 449 if (sc->mem == NULL) { 450 sc->rtp = 451 (m2 == PCIM_CMD_MEMEN)? SYS_RES_MEMORY : SYS_RES_IOPORT; 452 sc->rgd = (m2 == PCIM_CMD_MEMEN)? FXP_PCI_MMBA : FXP_PCI_IOBA; 453 sc->mem = bus_alloc_resource(dev, sc->rtp, &sc->rgd, 454 0, ~0, 1, RF_ACTIVE); 455 } 456 457 if (!sc->mem) { 458 error = ENXIO; 459 goto fail; 460 } 461 if (bootverbose) { 462 device_printf(dev, "using %s space register mapping\n", 463 sc->rtp == SYS_RES_MEMORY? "memory" : "I/O"); 464 } 465 466 sc->sc_st = rman_get_bustag(sc->mem); 467 sc->sc_sh = rman_get_bushandle(sc->mem); 468 469 /* 470 * Allocate our interrupt. 471 */ 472 rid = 0; 473 sc->irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 474 RF_SHAREABLE | RF_ACTIVE); 475 if (sc->irq == NULL) { 476 device_printf(dev, "could not map interrupt\n"); 477 error = ENXIO; 478 goto fail; 479 } 480 481 /* 482 * Reset to a stable state. 483 */ 484 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET); 485 DELAY(10); 486 487 /* 488 * Find out how large of an SEEPROM we have. 489 */ 490 fxp_autosize_eeprom(sc); 491 492 /* 493 * Determine whether we must use the 503 serial interface. 494 */ 495 fxp_read_eeprom(sc, &data, 6, 1); 496 if ((data & FXP_PHY_DEVICE_MASK) != 0 && 497 (data & FXP_PHY_SERIAL_ONLY)) 498 sc->flags |= FXP_FLAG_SERIAL_MEDIA; 499 500 /* 501 * Create the sysctl tree 502 */ 503 sc->sysctl_tree = SYSCTL_ADD_NODE(&sc->sysctl_ctx, 504 SYSCTL_STATIC_CHILDREN(_hw), OID_AUTO, 505 device_get_nameunit(dev), CTLFLAG_RD, 0, ""); 506 if (sc->sysctl_tree == NULL) { 507 error = ENXIO; 508 goto fail; 509 } 510 SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree), 511 OID_AUTO, "int_delay", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_PRISON, 512 &sc->tunable_int_delay, 0, sysctl_hw_fxp_int_delay, "I", 513 "FXP driver receive interrupt microcode bundling delay"); 514 SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree), 515 OID_AUTO, "bundle_max", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_PRISON, 516 &sc->tunable_bundle_max, 0, sysctl_hw_fxp_bundle_max, "I", 517 "FXP driver receive interrupt microcode bundle size limit"); 518 519 /* 520 * Pull in device tunables. 521 */ 522 sc->tunable_int_delay = TUNABLE_INT_DELAY; 523 sc->tunable_bundle_max = TUNABLE_BUNDLE_MAX; 524 (void) resource_int_value(device_get_name(dev), device_get_unit(dev), 525 "int_delay", &sc->tunable_int_delay); 526 (void) resource_int_value(device_get_name(dev), device_get_unit(dev), 527 "bundle_max", &sc->tunable_bundle_max); 528 529 /* 530 * Find out the chip revision; lump all 82557 revs together. 531 */ 532 fxp_read_eeprom(sc, &data, 5, 1); 533 if ((data >> 8) == 1) 534 sc->revision = FXP_REV_82557; 535 else 536 sc->revision = pci_get_revid(dev); 537 538 /* 539 * Enable workarounds for certain chip revision deficiencies. 540 * 541 * Systems based on the ICH2/ICH2-M chip from Intel, and possibly 542 * some systems based a normal 82559 design, have a defect where 543 * the chip can cause a PCI protocol violation if it receives 544 * a CU_RESUME command when it is entering the IDLE state. The 545 * workaround is to disable Dynamic Standby Mode, so the chip never 546 * deasserts CLKRUN#, and always remains in an active state. 547 * 548 * See Intel 82801BA/82801BAM Specification Update, Errata #30. 549 */ 550 i = pci_get_device(dev); 551 if (i == 0x2449 || (i > 0x1030 && i < 0x1039) || 552 sc->revision >= FXP_REV_82559_A0) { 553 fxp_read_eeprom(sc, &data, 10, 1); 554 if (data & 0x02) { /* STB enable */ 555 u_int16_t cksum; 556 int i; 557 558 device_printf(dev, 559 "Disabling dynamic standby mode in EEPROM\n"); 560 data &= ~0x02; 561 fxp_write_eeprom(sc, &data, 10, 1); 562 device_printf(dev, "New EEPROM ID: 0x%x\n", data); 563 cksum = 0; 564 for (i = 0; i < (1 << sc->eeprom_size) - 1; i++) { 565 fxp_read_eeprom(sc, &data, i, 1); 566 cksum += data; 567 } 568 i = (1 << sc->eeprom_size) - 1; 569 cksum = 0xBABA - cksum; 570 fxp_read_eeprom(sc, &data, i, 1); 571 fxp_write_eeprom(sc, &cksum, i, 1); 572 device_printf(dev, 573 "EEPROM checksum @ 0x%x: 0x%x -> 0x%x\n", 574 i, data, cksum); 575 #if 1 576 /* 577 * If the user elects to continue, try the software 578 * workaround, as it is better than nothing. 579 */ 580 sc->flags |= FXP_FLAG_CU_RESUME_BUG; 581 #endif 582 } 583 } 584 585 /* 586 * If we are not a 82557 chip, we can enable extended features. 587 */ 588 if (sc->revision != FXP_REV_82557) { 589 /* 590 * If MWI is enabled in the PCI configuration, and there 591 * is a valid cacheline size (8 or 16 dwords), then tell 592 * the board to turn on MWI. 593 */ 594 if (val & PCIM_CMD_MWRICEN && 595 pci_read_config(dev, PCIR_CACHELNSZ, 1) != 0) 596 sc->flags |= FXP_FLAG_MWI_ENABLE; 597 598 /* turn on the extended TxCB feature */ 599 sc->flags |= FXP_FLAG_EXT_TXCB; 600 601 /* enable reception of long frames for VLAN */ 602 sc->flags |= FXP_FLAG_LONG_PKT_EN; 603 } 604 605 /* 606 * Enable use of extended RFDs and TCBs for 82550 607 * and later chips. Note: we need extended TXCB support 608 * too, but that's already enabled by the code above. 609 * Be careful to do this only on the right devices. 610 * 611 * At least some 82550 cards probed as "chip=0x12298086 rev=0x0d" 612 * truncate packets that end with an mbuf containing 1 to 3 bytes 613 * when used with this feature enabled in the previous version of the 614 * driver. This problem appears to be fixed now that the driver 615 * always sets the hardware parse bit in the IPCB structure, which 616 * the "Intel 8255x 10/100 Mbps Ethernet Controller Family Open 617 * Source Software Developer Manual" says is necessary in the 618 * cases where packet truncation was observed. 619 * 620 * The device hint "hint.fxp.UNIT_NUMBER.ipcbxmit_disable" 621 * allows this feature to be disabled at boot time. 622 * 623 * If fxp is not compiled into the kernel, this feature may also 624 * be disabled at run time: 625 * # kldunload fxp 626 * # kenv hint.fxp.0.ipcbxmit_disable=1 627 * # kldload fxp 628 */ 629 630 if (resource_int_value("fxp", device_get_unit(dev), "ipcbxmit_disable", 631 &ipcbxmit_disable) != 0) 632 ipcbxmit_disable = 0; 633 if (ipcbxmit_disable == 0 && (sc->revision == FXP_REV_82550 || 634 sc->revision == FXP_REV_82550_C)) { 635 sc->rfa_size = sizeof (struct fxp_rfa); 636 sc->tx_cmd = FXP_CB_COMMAND_IPCBXMIT; 637 sc->flags |= FXP_FLAG_EXT_RFA; 638 } else { 639 sc->rfa_size = sizeof (struct fxp_rfa) - FXP_RFAX_LEN; 640 sc->tx_cmd = FXP_CB_COMMAND_XMIT; 641 } 642 643 /* 644 * Allocate DMA tags and DMA safe memory. 645 */ 646 maxtxseg = sc->flags & FXP_FLAG_EXT_RFA ? FXP_NTXSEG - 1 : FXP_NTXSEG; 647 error = bus_dma_tag_create(NULL, 2, 0, BUS_SPACE_MAXADDR_32BIT, 648 BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES * maxtxseg, 649 maxtxseg, MCLBYTES, 0, busdma_lock_mutex, &Giant, &sc->fxp_mtag); 650 if (error) { 651 device_printf(dev, "could not allocate dma tag\n"); 652 goto fail; 653 } 654 655 error = bus_dma_tag_create(NULL, 4, 0, BUS_SPACE_MAXADDR_32BIT, 656 BUS_SPACE_MAXADDR, NULL, NULL, sizeof(struct fxp_stats), 1, 657 sizeof(struct fxp_stats), 0, busdma_lock_mutex, &Giant, 658 &sc->fxp_stag); 659 if (error) { 660 device_printf(dev, "could not allocate dma tag\n"); 661 goto fail; 662 } 663 664 error = bus_dmamem_alloc(sc->fxp_stag, (void **)&sc->fxp_stats, 665 BUS_DMA_NOWAIT | BUS_DMA_ZERO, &sc->fxp_smap); 666 if (error) 667 goto fail; 668 error = bus_dmamap_load(sc->fxp_stag, sc->fxp_smap, sc->fxp_stats, 669 sizeof(struct fxp_stats), fxp_dma_map_addr, &sc->stats_addr, 0); 670 if (error) { 671 device_printf(dev, "could not map the stats buffer\n"); 672 goto fail; 673 } 674 675 error = bus_dma_tag_create(NULL, 4, 0, BUS_SPACE_MAXADDR_32BIT, 676 BUS_SPACE_MAXADDR, NULL, NULL, FXP_TXCB_SZ, 1, 677 FXP_TXCB_SZ, 0, busdma_lock_mutex, &Giant, &sc->cbl_tag); 678 if (error) { 679 device_printf(dev, "could not allocate dma tag\n"); 680 goto fail; 681 } 682 683 error = bus_dmamem_alloc(sc->cbl_tag, (void **)&sc->fxp_desc.cbl_list, 684 BUS_DMA_NOWAIT | BUS_DMA_ZERO, &sc->cbl_map); 685 if (error) 686 goto fail; 687 688 error = bus_dmamap_load(sc->cbl_tag, sc->cbl_map, 689 sc->fxp_desc.cbl_list, FXP_TXCB_SZ, fxp_dma_map_addr, 690 &sc->fxp_desc.cbl_addr, 0); 691 if (error) { 692 device_printf(dev, "could not map DMA memory\n"); 693 goto fail; 694 } 695 696 error = bus_dma_tag_create(NULL, 4, 0, BUS_SPACE_MAXADDR_32BIT, 697 BUS_SPACE_MAXADDR, NULL, NULL, sizeof(struct fxp_cb_mcs), 1, 698 sizeof(struct fxp_cb_mcs), 0, busdma_lock_mutex, &Giant, 699 &sc->mcs_tag); 700 if (error) { 701 device_printf(dev, "could not allocate dma tag\n"); 702 goto fail; 703 } 704 705 error = bus_dmamem_alloc(sc->mcs_tag, (void **)&sc->mcsp, 706 BUS_DMA_NOWAIT, &sc->mcs_map); 707 if (error) 708 goto fail; 709 error = bus_dmamap_load(sc->mcs_tag, sc->mcs_map, sc->mcsp, 710 sizeof(struct fxp_cb_mcs), fxp_dma_map_addr, &sc->mcs_addr, 0); 711 if (error) { 712 device_printf(dev, "can't map the multicast setup command\n"); 713 goto fail; 714 } 715 716 /* 717 * Pre-allocate the TX DMA maps. 718 */ 719 for (i = 0; i < FXP_NTXCB; i++) { 720 error = bus_dmamap_create(sc->fxp_mtag, 0, 721 &sc->fxp_desc.tx_list[i].tx_map); 722 if (error) { 723 device_printf(dev, "can't create DMA map for TX\n"); 724 goto fail; 725 } 726 } 727 error = bus_dmamap_create(sc->fxp_mtag, 0, &sc->spare_map); 728 if (error) { 729 device_printf(dev, "can't create spare DMA map\n"); 730 goto fail; 731 } 732 733 /* 734 * Pre-allocate our receive buffers. 735 */ 736 sc->fxp_desc.rx_head = sc->fxp_desc.rx_tail = NULL; 737 for (i = 0; i < FXP_NRFABUFS; i++) { 738 rxp = &sc->fxp_desc.rx_list[i]; 739 error = bus_dmamap_create(sc->fxp_mtag, 0, &rxp->rx_map); 740 if (error) { 741 device_printf(dev, "can't create DMA map for RX\n"); 742 goto fail; 743 } 744 if (fxp_add_rfabuf(sc, rxp) != 0) { 745 error = ENOMEM; 746 goto fail; 747 } 748 } 749 750 /* 751 * Read MAC address. 752 */ 753 fxp_read_eeprom(sc, myea, 0, 3); 754 sc->arpcom.ac_enaddr[0] = myea[0] & 0xff; 755 sc->arpcom.ac_enaddr[1] = myea[0] >> 8; 756 sc->arpcom.ac_enaddr[2] = myea[1] & 0xff; 757 sc->arpcom.ac_enaddr[3] = myea[1] >> 8; 758 sc->arpcom.ac_enaddr[4] = myea[2] & 0xff; 759 sc->arpcom.ac_enaddr[5] = myea[2] >> 8; 760 device_printf(dev, "Ethernet address %6D%s\n", 761 sc->arpcom.ac_enaddr, ":", 762 sc->flags & FXP_FLAG_SERIAL_MEDIA ? ", 10Mbps" : ""); 763 if (bootverbose) { 764 device_printf(dev, "PCI IDs: %04x %04x %04x %04x %04x\n", 765 pci_get_vendor(dev), pci_get_device(dev), 766 pci_get_subvendor(dev), pci_get_subdevice(dev), 767 pci_get_revid(dev)); 768 fxp_read_eeprom(sc, &data, 10, 1); 769 device_printf(dev, "Dynamic Standby mode is %s\n", 770 data & 0x02 ? "enabled" : "disabled"); 771 } 772 773 /* 774 * If this is only a 10Mbps device, then there is no MII, and 775 * the PHY will use a serial interface instead. 776 * 777 * The Seeq 80c24 AutoDUPLEX(tm) Ethernet Interface Adapter 778 * doesn't have a programming interface of any sort. The 779 * media is sensed automatically based on how the link partner 780 * is configured. This is, in essence, manual configuration. 781 */ 782 if (sc->flags & FXP_FLAG_SERIAL_MEDIA) { 783 ifmedia_add(&sc->sc_media, IFM_ETHER|IFM_MANUAL, 0, NULL); 784 ifmedia_set(&sc->sc_media, IFM_ETHER|IFM_MANUAL); 785 } else { 786 if (mii_phy_probe(dev, &sc->miibus, fxp_ifmedia_upd, 787 fxp_ifmedia_sts)) { 788 device_printf(dev, "MII without any PHY!\n"); 789 error = ENXIO; 790 goto fail; 791 } 792 } 793 794 ifp = &sc->arpcom.ac_if; 795 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 796 ifp->if_output = ether_output; 797 ifp->if_baudrate = 100000000; 798 ifp->if_init = fxp_init; 799 ifp->if_softc = sc; 800 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 801 ifp->if_ioctl = fxp_ioctl; 802 ifp->if_start = fxp_start; 803 ifp->if_watchdog = fxp_watchdog; 804 805 /* Enable checksum offload for 82550 or better chips */ 806 if (sc->flags & FXP_FLAG_EXT_RFA) { 807 ifp->if_hwassist = FXP_CSUM_FEATURES; 808 ifp->if_capabilities = IFCAP_HWCSUM; 809 ifp->if_capenable = ifp->if_capabilities; 810 } 811 812 /* 813 * Attach the interface. 814 */ 815 ether_ifattach(ifp, sc->arpcom.ac_enaddr); 816 817 /* 818 * Tell the upper layer(s) we support long frames. 819 */ 820 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 821 ifp->if_capabilities |= IFCAP_VLAN_MTU; 822 823 /* 824 * Let the system queue as many packets as we have available 825 * TX descriptors. 826 */ 827 ifp->if_snd.ifq_maxlen = FXP_NTXCB - 1; 828 829 /* 830 * Hook our interrupt after all initialization is complete. 831 * XXX This driver has been tested with the INTR_MPSAFFE flag set 832 * however, ifp and its functions are not fully locked so MPSAFE 833 * should not be used unless you can handle potential data loss. 834 */ 835 error = bus_setup_intr(dev, sc->irq, INTR_TYPE_NET | INTR_MPSAFE, 836 fxp_intr, sc, &sc->ih); 837 if (error) { 838 device_printf(dev, "could not setup irq\n"); 839 ether_ifdetach(&sc->arpcom.ac_if); 840 goto fail; 841 } 842 843 fail: 844 splx(s); 845 if (error) 846 fxp_release(sc); 847 return (error); 848 } 849 850 /* 851 * Release all resources. The softc lock should not be held and the 852 * interrupt should already be torn down. 853 */ 854 static void 855 fxp_release(struct fxp_softc *sc) 856 { 857 struct fxp_rx *rxp; 858 struct fxp_tx *txp; 859 int i; 860 861 mtx_assert(&sc->sc_mtx, MA_NOTOWNED); 862 if (sc->ih) 863 panic("fxp_release() called with intr handle still active"); 864 if (sc->miibus) 865 device_delete_child(sc->dev, sc->miibus); 866 bus_generic_detach(sc->dev); 867 ifmedia_removeall(&sc->sc_media); 868 if (sc->fxp_desc.cbl_list) { 869 bus_dmamap_unload(sc->cbl_tag, sc->cbl_map); 870 bus_dmamem_free(sc->cbl_tag, sc->fxp_desc.cbl_list, 871 sc->cbl_map); 872 } 873 if (sc->fxp_stats) { 874 bus_dmamap_unload(sc->fxp_stag, sc->fxp_smap); 875 bus_dmamem_free(sc->fxp_stag, sc->fxp_stats, sc->fxp_smap); 876 } 877 if (sc->mcsp) { 878 bus_dmamap_unload(sc->mcs_tag, sc->mcs_map); 879 bus_dmamem_free(sc->mcs_tag, sc->mcsp, sc->mcs_map); 880 } 881 if (sc->irq) 882 bus_release_resource(sc->dev, SYS_RES_IRQ, 0, sc->irq); 883 if (sc->mem) 884 bus_release_resource(sc->dev, sc->rtp, sc->rgd, sc->mem); 885 if (sc->fxp_mtag) { 886 for (i = 0; i < FXP_NRFABUFS; i++) { 887 rxp = &sc->fxp_desc.rx_list[i]; 888 if (rxp->rx_mbuf != NULL) { 889 bus_dmamap_sync(sc->fxp_mtag, rxp->rx_map, 890 BUS_DMASYNC_POSTREAD); 891 bus_dmamap_unload(sc->fxp_mtag, rxp->rx_map); 892 m_freem(rxp->rx_mbuf); 893 } 894 bus_dmamap_destroy(sc->fxp_mtag, rxp->rx_map); 895 } 896 bus_dmamap_destroy(sc->fxp_mtag, sc->spare_map); 897 bus_dma_tag_destroy(sc->fxp_mtag); 898 } 899 if (sc->fxp_stag) { 900 for (i = 0; i < FXP_NTXCB; i++) { 901 txp = &sc->fxp_desc.tx_list[i]; 902 if (txp->tx_mbuf != NULL) { 903 bus_dmamap_sync(sc->fxp_mtag, txp->tx_map, 904 BUS_DMASYNC_POSTWRITE); 905 bus_dmamap_unload(sc->fxp_mtag, txp->tx_map); 906 m_freem(txp->tx_mbuf); 907 } 908 bus_dmamap_destroy(sc->fxp_mtag, txp->tx_map); 909 } 910 bus_dma_tag_destroy(sc->fxp_stag); 911 } 912 if (sc->cbl_tag) 913 bus_dma_tag_destroy(sc->cbl_tag); 914 if (sc->mcs_tag) 915 bus_dma_tag_destroy(sc->mcs_tag); 916 917 sysctl_ctx_free(&sc->sysctl_ctx); 918 919 mtx_destroy(&sc->sc_mtx); 920 } 921 922 /* 923 * Detach interface. 924 */ 925 static int 926 fxp_detach(device_t dev) 927 { 928 struct fxp_softc *sc = device_get_softc(dev); 929 int s; 930 931 FXP_LOCK(sc); 932 s = splimp(); 933 934 sc->suspended = 1; /* Do same thing as we do for suspend */ 935 /* 936 * Close down routes etc. 937 */ 938 ether_ifdetach(&sc->arpcom.ac_if); 939 940 /* 941 * Stop DMA and drop transmit queue, but disable interrupts first. 942 */ 943 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE); 944 fxp_stop(sc); 945 FXP_UNLOCK(sc); 946 947 /* 948 * Unhook interrupt before dropping lock. This is to prevent 949 * races with fxp_intr(). 950 */ 951 bus_teardown_intr(sc->dev, sc->irq, sc->ih); 952 sc->ih = NULL; 953 954 splx(s); 955 956 /* Release our allocated resources. */ 957 fxp_release(sc); 958 return (0); 959 } 960 961 /* 962 * Device shutdown routine. Called at system shutdown after sync. The 963 * main purpose of this routine is to shut off receiver DMA so that 964 * kernel memory doesn't get clobbered during warmboot. 965 */ 966 static int 967 fxp_shutdown(device_t dev) 968 { 969 /* 970 * Make sure that DMA is disabled prior to reboot. Not doing 971 * do could allow DMA to corrupt kernel memory during the 972 * reboot before the driver initializes. 973 */ 974 fxp_stop((struct fxp_softc *) device_get_softc(dev)); 975 return (0); 976 } 977 978 /* 979 * Device suspend routine. Stop the interface and save some PCI 980 * settings in case the BIOS doesn't restore them properly on 981 * resume. 982 */ 983 static int 984 fxp_suspend(device_t dev) 985 { 986 struct fxp_softc *sc = device_get_softc(dev); 987 int i, s; 988 989 FXP_LOCK(sc); 990 s = splimp(); 991 992 fxp_stop(sc); 993 994 for (i = 0; i < 5; i++) 995 sc->saved_maps[i] = pci_read_config(dev, PCIR_BAR(i), 4); 996 sc->saved_biosaddr = pci_read_config(dev, PCIR_BIOS, 4); 997 sc->saved_intline = pci_read_config(dev, PCIR_INTLINE, 1); 998 sc->saved_cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1); 999 sc->saved_lattimer = pci_read_config(dev, PCIR_LATTIMER, 1); 1000 1001 sc->suspended = 1; 1002 1003 FXP_UNLOCK(sc); 1004 splx(s); 1005 return (0); 1006 } 1007 1008 /* 1009 * Device resume routine. Restore some PCI settings in case the BIOS 1010 * doesn't, re-enable busmastering, and restart the interface if 1011 * appropriate. 1012 */ 1013 static int 1014 fxp_resume(device_t dev) 1015 { 1016 struct fxp_softc *sc = device_get_softc(dev); 1017 struct ifnet *ifp = &sc->sc_if; 1018 u_int16_t pci_command; 1019 int i, s; 1020 1021 FXP_LOCK(sc); 1022 s = splimp(); 1023 #ifndef BURN_BRIDGES 1024 fxp_powerstate_d0(dev); 1025 #endif 1026 /* better way to do this? */ 1027 for (i = 0; i < 5; i++) 1028 pci_write_config(dev, PCIR_BAR(i), sc->saved_maps[i], 4); 1029 pci_write_config(dev, PCIR_BIOS, sc->saved_biosaddr, 4); 1030 pci_write_config(dev, PCIR_INTLINE, sc->saved_intline, 1); 1031 pci_write_config(dev, PCIR_CACHELNSZ, sc->saved_cachelnsz, 1); 1032 pci_write_config(dev, PCIR_LATTIMER, sc->saved_lattimer, 1); 1033 1034 /* reenable busmastering */ 1035 pci_command = pci_read_config(dev, PCIR_COMMAND, 2); 1036 pci_command |= (PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN); 1037 pci_write_config(dev, PCIR_COMMAND, pci_command, 2); 1038 1039 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET); 1040 DELAY(10); 1041 1042 /* reinitialize interface if necessary */ 1043 if (ifp->if_flags & IFF_UP) 1044 fxp_init_body(sc); 1045 1046 sc->suspended = 0; 1047 1048 FXP_UNLOCK(sc); 1049 splx(s); 1050 return (0); 1051 } 1052 1053 static void 1054 fxp_eeprom_shiftin(struct fxp_softc *sc, int data, int length) 1055 { 1056 u_int16_t reg; 1057 int x; 1058 1059 /* 1060 * Shift in data. 1061 */ 1062 for (x = 1 << (length - 1); x; x >>= 1) { 1063 if (data & x) 1064 reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI; 1065 else 1066 reg = FXP_EEPROM_EECS; 1067 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 1068 DELAY(1); 1069 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK); 1070 DELAY(1); 1071 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 1072 DELAY(1); 1073 } 1074 } 1075 1076 /* 1077 * Read from the serial EEPROM. Basically, you manually shift in 1078 * the read opcode (one bit at a time) and then shift in the address, 1079 * and then you shift out the data (all of this one bit at a time). 1080 * The word size is 16 bits, so you have to provide the address for 1081 * every 16 bits of data. 1082 */ 1083 static u_int16_t 1084 fxp_eeprom_getword(struct fxp_softc *sc, int offset, int autosize) 1085 { 1086 u_int16_t reg, data; 1087 int x; 1088 1089 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 1090 /* 1091 * Shift in read opcode. 1092 */ 1093 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_READ, 3); 1094 /* 1095 * Shift in address. 1096 */ 1097 data = 0; 1098 for (x = 1 << (sc->eeprom_size - 1); x; x >>= 1) { 1099 if (offset & x) 1100 reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI; 1101 else 1102 reg = FXP_EEPROM_EECS; 1103 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 1104 DELAY(1); 1105 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK); 1106 DELAY(1); 1107 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 1108 DELAY(1); 1109 reg = CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO; 1110 data++; 1111 if (autosize && reg == 0) { 1112 sc->eeprom_size = data; 1113 break; 1114 } 1115 } 1116 /* 1117 * Shift out data. 1118 */ 1119 data = 0; 1120 reg = FXP_EEPROM_EECS; 1121 for (x = 1 << 15; x; x >>= 1) { 1122 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK); 1123 DELAY(1); 1124 if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO) 1125 data |= x; 1126 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 1127 DELAY(1); 1128 } 1129 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 1130 DELAY(1); 1131 1132 return (data); 1133 } 1134 1135 static void 1136 fxp_eeprom_putword(struct fxp_softc *sc, int offset, u_int16_t data) 1137 { 1138 int i; 1139 1140 /* 1141 * Erase/write enable. 1142 */ 1143 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 1144 fxp_eeprom_shiftin(sc, 0x4, 3); 1145 fxp_eeprom_shiftin(sc, 0x03 << (sc->eeprom_size - 2), sc->eeprom_size); 1146 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 1147 DELAY(1); 1148 /* 1149 * Shift in write opcode, address, data. 1150 */ 1151 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 1152 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_WRITE, 3); 1153 fxp_eeprom_shiftin(sc, offset, sc->eeprom_size); 1154 fxp_eeprom_shiftin(sc, data, 16); 1155 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 1156 DELAY(1); 1157 /* 1158 * Wait for EEPROM to finish up. 1159 */ 1160 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 1161 DELAY(1); 1162 for (i = 0; i < 1000; i++) { 1163 if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO) 1164 break; 1165 DELAY(50); 1166 } 1167 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 1168 DELAY(1); 1169 /* 1170 * Erase/write disable. 1171 */ 1172 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 1173 fxp_eeprom_shiftin(sc, 0x4, 3); 1174 fxp_eeprom_shiftin(sc, 0, sc->eeprom_size); 1175 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 1176 DELAY(1); 1177 } 1178 1179 /* 1180 * From NetBSD: 1181 * 1182 * Figure out EEPROM size. 1183 * 1184 * 559's can have either 64-word or 256-word EEPROMs, the 558 1185 * datasheet only talks about 64-word EEPROMs, and the 557 datasheet 1186 * talks about the existance of 16 to 256 word EEPROMs. 1187 * 1188 * The only known sizes are 64 and 256, where the 256 version is used 1189 * by CardBus cards to store CIS information. 1190 * 1191 * The address is shifted in msb-to-lsb, and after the last 1192 * address-bit the EEPROM is supposed to output a `dummy zero' bit, 1193 * after which follows the actual data. We try to detect this zero, by 1194 * probing the data-out bit in the EEPROM control register just after 1195 * having shifted in a bit. If the bit is zero, we assume we've 1196 * shifted enough address bits. The data-out should be tri-state, 1197 * before this, which should translate to a logical one. 1198 */ 1199 static void 1200 fxp_autosize_eeprom(struct fxp_softc *sc) 1201 { 1202 1203 /* guess maximum size of 256 words */ 1204 sc->eeprom_size = 8; 1205 1206 /* autosize */ 1207 (void) fxp_eeprom_getword(sc, 0, 1); 1208 } 1209 1210 static void 1211 fxp_read_eeprom(struct fxp_softc *sc, u_short *data, int offset, int words) 1212 { 1213 int i; 1214 1215 for (i = 0; i < words; i++) 1216 data[i] = fxp_eeprom_getword(sc, offset + i, 0); 1217 } 1218 1219 static void 1220 fxp_write_eeprom(struct fxp_softc *sc, u_short *data, int offset, int words) 1221 { 1222 int i; 1223 1224 for (i = 0; i < words; i++) 1225 fxp_eeprom_putword(sc, offset + i, data[i]); 1226 } 1227 1228 static void 1229 fxp_dma_map_txbuf(void *arg, bus_dma_segment_t *segs, int nseg, 1230 bus_size_t mapsize, int error) 1231 { 1232 struct fxp_softc *sc; 1233 struct fxp_cb_tx *txp; 1234 int i; 1235 1236 if (error) 1237 return; 1238 1239 KASSERT(nseg <= FXP_NTXSEG, ("too many DMA segments")); 1240 1241 sc = arg; 1242 txp = sc->fxp_desc.tx_last->tx_next->tx_cb; 1243 for (i = 0; i < nseg; i++) { 1244 KASSERT(segs[i].ds_len <= MCLBYTES, ("segment size too large")); 1245 /* 1246 * If this is an 82550/82551, then we're using extended 1247 * TxCBs _and_ we're using checksum offload. This means 1248 * that the TxCB is really an IPCB. One major difference 1249 * between the two is that with plain extended TxCBs, 1250 * the bottom half of the TxCB contains two entries from 1251 * the TBD array, whereas IPCBs contain just one entry: 1252 * one entry (8 bytes) has been sacrificed for the TCP/IP 1253 * checksum offload control bits. So to make things work 1254 * right, we have to start filling in the TBD array 1255 * starting from a different place depending on whether 1256 * the chip is an 82550/82551 or not. 1257 */ 1258 if (sc->flags & FXP_FLAG_EXT_RFA) { 1259 txp->tbd[i + 1].tb_addr = htole32(segs[i].ds_addr); 1260 txp->tbd[i + 1].tb_size = htole32(segs[i].ds_len); 1261 } else { 1262 txp->tbd[i].tb_addr = htole32(segs[i].ds_addr); 1263 txp->tbd[i].tb_size = htole32(segs[i].ds_len); 1264 } 1265 } 1266 txp->tbd_number = nseg; 1267 } 1268 1269 /* 1270 * Grab the softc lock and call the real fxp_start_body() routine 1271 */ 1272 static void 1273 fxp_start(struct ifnet *ifp) 1274 { 1275 struct fxp_softc *sc = ifp->if_softc; 1276 1277 FXP_LOCK(sc); 1278 fxp_start_body(ifp); 1279 FXP_UNLOCK(sc); 1280 } 1281 1282 /* 1283 * Start packet transmission on the interface. 1284 * This routine must be called with the softc lock held, and is an 1285 * internal entry point only. 1286 */ 1287 static void 1288 fxp_start_body(struct ifnet *ifp) 1289 { 1290 struct fxp_softc *sc = ifp->if_softc; 1291 struct fxp_tx *txp; 1292 struct mbuf *mb_head; 1293 int error; 1294 1295 mtx_assert(&sc->sc_mtx, MA_OWNED); 1296 /* 1297 * See if we need to suspend xmit until the multicast filter 1298 * has been reprogrammed (which can only be done at the head 1299 * of the command chain). 1300 */ 1301 if (sc->need_mcsetup) { 1302 return; 1303 } 1304 1305 txp = NULL; 1306 1307 /* 1308 * We're finished if there is nothing more to add to the list or if 1309 * we're all filled up with buffers to transmit. 1310 * NOTE: One TxCB is reserved to guarantee that fxp_mc_setup() can add 1311 * a NOP command when needed. 1312 */ 1313 while (ifp->if_snd.ifq_head != NULL && sc->tx_queued < FXP_NTXCB - 1) { 1314 1315 /* 1316 * Grab a packet to transmit. 1317 */ 1318 IF_DEQUEUE(&ifp->if_snd, mb_head); 1319 1320 /* 1321 * Get pointer to next available tx desc. 1322 */ 1323 txp = sc->fxp_desc.tx_last->tx_next; 1324 1325 /* 1326 * A note in Appendix B of the Intel 8255x 10/100 Mbps 1327 * Ethernet Controller Family Open Source Software 1328 * Developer Manual says: 1329 * Using software parsing is only allowed with legal 1330 * TCP/IP or UDP/IP packets. 1331 * ... 1332 * For all other datagrams, hardware parsing must 1333 * be used. 1334 * Software parsing appears to truncate ICMP and 1335 * fragmented UDP packets that contain one to three 1336 * bytes in the second (and final) mbuf of the packet. 1337 */ 1338 if (sc->flags & FXP_FLAG_EXT_RFA) 1339 txp->tx_cb->ipcb_ip_activation_high = 1340 FXP_IPCB_HARDWAREPARSING_ENABLE; 1341 1342 /* 1343 * Deal with TCP/IP checksum offload. Note that 1344 * in order for TCP checksum offload to work, 1345 * the pseudo header checksum must have already 1346 * been computed and stored in the checksum field 1347 * in the TCP header. The stack should have 1348 * already done this for us. 1349 */ 1350 1351 if (mb_head->m_pkthdr.csum_flags) { 1352 if (mb_head->m_pkthdr.csum_flags & CSUM_DELAY_DATA) { 1353 txp->tx_cb->ipcb_ip_schedule = 1354 FXP_IPCB_TCPUDP_CHECKSUM_ENABLE; 1355 if (mb_head->m_pkthdr.csum_flags & CSUM_TCP) 1356 txp->tx_cb->ipcb_ip_schedule |= 1357 FXP_IPCB_TCP_PACKET; 1358 } 1359 #ifdef FXP_IP_CSUM_WAR 1360 /* 1361 * XXX The 82550 chip appears to have trouble 1362 * dealing with IP header checksums in very small 1363 * datagrams, namely fragments from 1 to 3 bytes 1364 * in size. For example, say you want to transmit 1365 * a UDP packet of 1473 bytes. The packet will be 1366 * fragmented over two IP datagrams, the latter 1367 * containing only one byte of data. The 82550 will 1368 * botch the header checksum on the 1-byte fragment. 1369 * As long as the datagram contains 4 or more bytes 1370 * of data, you're ok. 1371 * 1372 * The following code attempts to work around this 1373 * problem: if the datagram is less than 38 bytes 1374 * in size (14 bytes ether header, 20 bytes IP header, 1375 * plus 4 bytes of data), we punt and compute the IP 1376 * header checksum by hand. This workaround doesn't 1377 * work very well, however, since it can be fooled 1378 * by things like VLAN tags and IP options that make 1379 * the header sizes/offsets vary. 1380 */ 1381 1382 if (mb_head->m_pkthdr.csum_flags & CSUM_IP) { 1383 if (mb_head->m_pkthdr.len < 38) { 1384 struct ip *ip; 1385 mb_head->m_data += ETHER_HDR_LEN; 1386 ip = mtod(mb_head, struct ip *); 1387 ip->ip_sum = in_cksum(mb_head, 1388 ip->ip_hl << 2); 1389 mb_head->m_data -= ETHER_HDR_LEN; 1390 } else { 1391 txp->tx_cb->ipcb_ip_activation_high = 1392 FXP_IPCB_HARDWAREPARSING_ENABLE; 1393 txp->tx_cb->ipcb_ip_schedule |= 1394 FXP_IPCB_IP_CHECKSUM_ENABLE; 1395 } 1396 } 1397 #endif 1398 } 1399 1400 /* 1401 * Go through each of the mbufs in the chain and initialize 1402 * the transmit buffer descriptors with the physical address 1403 * and size of the mbuf. 1404 */ 1405 error = bus_dmamap_load_mbuf(sc->fxp_mtag, txp->tx_map, 1406 mb_head, fxp_dma_map_txbuf, sc, 0); 1407 1408 if (error && error != EFBIG) { 1409 device_printf(sc->dev, "can't map mbuf (error %d)\n", 1410 error); 1411 m_freem(mb_head); 1412 break; 1413 } 1414 1415 if (error) { 1416 struct mbuf *mn; 1417 1418 /* 1419 * We ran out of segments. We have to recopy this 1420 * mbuf chain first. Bail out if we can't get the 1421 * new buffers. 1422 */ 1423 mn = m_defrag(mb_head, M_DONTWAIT); 1424 if (mn == NULL) { 1425 m_freem(mb_head); 1426 break; 1427 } else { 1428 mb_head = mn; 1429 } 1430 error = bus_dmamap_load_mbuf(sc->fxp_mtag, txp->tx_map, 1431 mb_head, fxp_dma_map_txbuf, sc, 0); 1432 if (error) { 1433 device_printf(sc->dev, 1434 "can't map mbuf (error %d)\n", error); 1435 m_freem(mb_head); 1436 break; 1437 } 1438 } 1439 1440 bus_dmamap_sync(sc->fxp_mtag, txp->tx_map, 1441 BUS_DMASYNC_PREWRITE); 1442 1443 txp->tx_mbuf = mb_head; 1444 txp->tx_cb->cb_status = 0; 1445 txp->tx_cb->byte_count = 0; 1446 if (sc->tx_queued != FXP_CXINT_THRESH - 1) { 1447 txp->tx_cb->cb_command = 1448 htole16(sc->tx_cmd | FXP_CB_COMMAND_SF | 1449 FXP_CB_COMMAND_S); 1450 } else { 1451 txp->tx_cb->cb_command = 1452 htole16(sc->tx_cmd | FXP_CB_COMMAND_SF | 1453 FXP_CB_COMMAND_S | FXP_CB_COMMAND_I); 1454 /* 1455 * Set a 5 second timer just in case we don't hear 1456 * from the card again. 1457 */ 1458 ifp->if_timer = 5; 1459 } 1460 txp->tx_cb->tx_threshold = tx_threshold; 1461 1462 /* 1463 * Advance the end of list forward. 1464 */ 1465 1466 #ifdef __alpha__ 1467 /* 1468 * On platforms which can't access memory in 16-bit 1469 * granularities, we must prevent the card from DMA'ing 1470 * up the status while we update the command field. 1471 * This could cause us to overwrite the completion status. 1472 * XXX This is probably bogus and we're _not_ looking 1473 * for atomicity here. 1474 */ 1475 atomic_clear_16(&sc->fxp_desc.tx_last->tx_cb->cb_command, 1476 htole16(FXP_CB_COMMAND_S)); 1477 #else 1478 sc->fxp_desc.tx_last->tx_cb->cb_command &= 1479 htole16(~FXP_CB_COMMAND_S); 1480 #endif /*__alpha__*/ 1481 sc->fxp_desc.tx_last = txp; 1482 1483 /* 1484 * Advance the beginning of the list forward if there are 1485 * no other packets queued (when nothing is queued, tx_first 1486 * sits on the last TxCB that was sent out). 1487 */ 1488 if (sc->tx_queued == 0) 1489 sc->fxp_desc.tx_first = txp; 1490 1491 sc->tx_queued++; 1492 1493 /* 1494 * Pass packet to bpf if there is a listener. 1495 */ 1496 BPF_MTAP(ifp, mb_head); 1497 } 1498 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE); 1499 1500 /* 1501 * We're finished. If we added to the list, issue a RESUME to get DMA 1502 * going again if suspended. 1503 */ 1504 if (txp != NULL) { 1505 fxp_scb_wait(sc); 1506 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_RESUME); 1507 } 1508 } 1509 1510 #ifdef DEVICE_POLLING 1511 static poll_handler_t fxp_poll; 1512 1513 static void 1514 fxp_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 1515 { 1516 struct fxp_softc *sc = ifp->if_softc; 1517 u_int8_t statack; 1518 1519 FXP_LOCK(sc); 1520 if (cmd == POLL_DEREGISTER) { /* final call, enable interrupts */ 1521 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, 0); 1522 FXP_UNLOCK(sc); 1523 return; 1524 } 1525 statack = FXP_SCB_STATACK_CXTNO | FXP_SCB_STATACK_CNA | 1526 FXP_SCB_STATACK_FR; 1527 if (cmd == POLL_AND_CHECK_STATUS) { 1528 u_int8_t tmp; 1529 1530 tmp = CSR_READ_1(sc, FXP_CSR_SCB_STATACK); 1531 if (tmp == 0xff || tmp == 0) { 1532 FXP_UNLOCK(sc); 1533 return; /* nothing to do */ 1534 } 1535 tmp &= ~statack; 1536 /* ack what we can */ 1537 if (tmp != 0) 1538 CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, tmp); 1539 statack |= tmp; 1540 } 1541 fxp_intr_body(sc, ifp, statack, count); 1542 FXP_UNLOCK(sc); 1543 } 1544 #endif /* DEVICE_POLLING */ 1545 1546 /* 1547 * Process interface interrupts. 1548 */ 1549 static void 1550 fxp_intr(void *xsc) 1551 { 1552 struct fxp_softc *sc = xsc; 1553 struct ifnet *ifp = &sc->sc_if; 1554 u_int8_t statack; 1555 1556 FXP_LOCK(sc); 1557 if (sc->suspended) { 1558 FXP_UNLOCK(sc); 1559 return; 1560 } 1561 1562 #ifdef DEVICE_POLLING 1563 if (ifp->if_flags & IFF_POLLING) { 1564 FXP_UNLOCK(sc); 1565 return; 1566 } 1567 if (ether_poll_register(fxp_poll, ifp)) { 1568 /* disable interrupts */ 1569 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE); 1570 FXP_UNLOCK(sc); 1571 fxp_poll(ifp, 0, 1); 1572 return; 1573 } 1574 #endif 1575 while ((statack = CSR_READ_1(sc, FXP_CSR_SCB_STATACK)) != 0) { 1576 /* 1577 * It should not be possible to have all bits set; the 1578 * FXP_SCB_INTR_SWI bit always returns 0 on a read. If 1579 * all bits are set, this may indicate that the card has 1580 * been physically ejected, so ignore it. 1581 */ 1582 if (statack == 0xff) { 1583 FXP_UNLOCK(sc); 1584 return; 1585 } 1586 1587 /* 1588 * First ACK all the interrupts in this pass. 1589 */ 1590 CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, statack); 1591 fxp_intr_body(sc, ifp, statack, -1); 1592 } 1593 FXP_UNLOCK(sc); 1594 } 1595 1596 static void 1597 fxp_txeof(struct fxp_softc *sc) 1598 { 1599 struct fxp_tx *txp; 1600 1601 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREREAD); 1602 for (txp = sc->fxp_desc.tx_first; sc->tx_queued && 1603 (le16toh(txp->tx_cb->cb_status) & FXP_CB_STATUS_C) != 0; 1604 txp = txp->tx_next) { 1605 if (txp->tx_mbuf != NULL) { 1606 bus_dmamap_sync(sc->fxp_mtag, txp->tx_map, 1607 BUS_DMASYNC_POSTWRITE); 1608 bus_dmamap_unload(sc->fxp_mtag, txp->tx_map); 1609 m_freem(txp->tx_mbuf); 1610 txp->tx_mbuf = NULL; 1611 /* clear this to reset csum offload bits */ 1612 txp->tx_cb->tbd[0].tb_addr = 0; 1613 } 1614 sc->tx_queued--; 1615 } 1616 sc->fxp_desc.tx_first = txp; 1617 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE); 1618 } 1619 1620 static void 1621 fxp_intr_body(struct fxp_softc *sc, struct ifnet *ifp, u_int8_t statack, 1622 int count) 1623 { 1624 struct mbuf *m; 1625 struct fxp_rx *rxp; 1626 struct fxp_rfa *rfa; 1627 int rnr = (statack & FXP_SCB_STATACK_RNR) ? 1 : 0; 1628 1629 mtx_assert(&sc->sc_mtx, MA_OWNED); 1630 if (rnr) 1631 fxp_rnr++; 1632 #ifdef DEVICE_POLLING 1633 /* Pick up a deferred RNR condition if `count' ran out last time. */ 1634 if (sc->flags & FXP_FLAG_DEFERRED_RNR) { 1635 sc->flags &= ~FXP_FLAG_DEFERRED_RNR; 1636 rnr = 1; 1637 } 1638 #endif 1639 1640 /* 1641 * Free any finished transmit mbuf chains. 1642 * 1643 * Handle the CNA event likt a CXTNO event. It used to 1644 * be that this event (control unit not ready) was not 1645 * encountered, but it is now with the SMPng modifications. 1646 * The exact sequence of events that occur when the interface 1647 * is brought up are different now, and if this event 1648 * goes unhandled, the configuration/rxfilter setup sequence 1649 * can stall for several seconds. The result is that no 1650 * packets go out onto the wire for about 5 to 10 seconds 1651 * after the interface is ifconfig'ed for the first time. 1652 */ 1653 if (statack & (FXP_SCB_STATACK_CXTNO | FXP_SCB_STATACK_CNA)) { 1654 fxp_txeof(sc); 1655 1656 ifp->if_timer = 0; 1657 if (sc->tx_queued == 0) { 1658 if (sc->need_mcsetup) 1659 fxp_mc_setup(sc); 1660 } 1661 /* 1662 * Try to start more packets transmitting. 1663 */ 1664 if (ifp->if_snd.ifq_head != NULL) 1665 fxp_start_body(ifp); 1666 } 1667 1668 /* 1669 * Just return if nothing happened on the receive side. 1670 */ 1671 if (!rnr && (statack & FXP_SCB_STATACK_FR) == 0) 1672 return; 1673 1674 /* 1675 * Process receiver interrupts. If a no-resource (RNR) 1676 * condition exists, get whatever packets we can and 1677 * re-start the receiver. 1678 * 1679 * When using polling, we do not process the list to completion, 1680 * so when we get an RNR interrupt we must defer the restart 1681 * until we hit the last buffer with the C bit set. 1682 * If we run out of cycles and rfa_headm has the C bit set, 1683 * record the pending RNR in the FXP_FLAG_DEFERRED_RNR flag so 1684 * that the info will be used in the subsequent polling cycle. 1685 */ 1686 for (;;) { 1687 rxp = sc->fxp_desc.rx_head; 1688 m = rxp->rx_mbuf; 1689 rfa = (struct fxp_rfa *)(m->m_ext.ext_buf + 1690 RFA_ALIGNMENT_FUDGE); 1691 bus_dmamap_sync(sc->fxp_mtag, rxp->rx_map, 1692 BUS_DMASYNC_POSTREAD); 1693 1694 #ifdef DEVICE_POLLING /* loop at most count times if count >=0 */ 1695 if (count >= 0 && count-- == 0) { 1696 if (rnr) { 1697 /* Defer RNR processing until the next time. */ 1698 sc->flags |= FXP_FLAG_DEFERRED_RNR; 1699 rnr = 0; 1700 } 1701 break; 1702 } 1703 #endif /* DEVICE_POLLING */ 1704 1705 if ((le16toh(rfa->rfa_status) & FXP_RFA_STATUS_C) == 0) 1706 break; 1707 1708 /* 1709 * Advance head forward. 1710 */ 1711 sc->fxp_desc.rx_head = rxp->rx_next; 1712 1713 /* 1714 * Add a new buffer to the receive chain. 1715 * If this fails, the old buffer is recycled 1716 * instead. 1717 */ 1718 if (fxp_add_rfabuf(sc, rxp) == 0) { 1719 int total_len; 1720 1721 /* 1722 * Fetch packet length (the top 2 bits of 1723 * actual_size are flags set by the controller 1724 * upon completion), and drop the packet in case 1725 * of bogus length or CRC errors. 1726 */ 1727 total_len = le16toh(rfa->actual_size) & 0x3fff; 1728 if (total_len < sizeof(struct ether_header) || 1729 total_len > MCLBYTES - RFA_ALIGNMENT_FUDGE - 1730 sc->rfa_size || 1731 le16toh(rfa->rfa_status) & FXP_RFA_STATUS_CRC) { 1732 m_freem(m); 1733 continue; 1734 } 1735 1736 /* Do IP checksum checking. */ 1737 if (le16toh(rfa->rfa_status) & FXP_RFA_STATUS_PARSE) { 1738 if (rfa->rfax_csum_sts & 1739 FXP_RFDX_CS_IP_CSUM_BIT_VALID) 1740 m->m_pkthdr.csum_flags |= 1741 CSUM_IP_CHECKED; 1742 if (rfa->rfax_csum_sts & 1743 FXP_RFDX_CS_IP_CSUM_VALID) 1744 m->m_pkthdr.csum_flags |= 1745 CSUM_IP_VALID; 1746 if ((rfa->rfax_csum_sts & 1747 FXP_RFDX_CS_TCPUDP_CSUM_BIT_VALID) && 1748 (rfa->rfax_csum_sts & 1749 FXP_RFDX_CS_TCPUDP_CSUM_VALID)) { 1750 m->m_pkthdr.csum_flags |= 1751 CSUM_DATA_VALID|CSUM_PSEUDO_HDR; 1752 m->m_pkthdr.csum_data = 0xffff; 1753 } 1754 } 1755 1756 m->m_pkthdr.len = m->m_len = total_len; 1757 m->m_pkthdr.rcvif = ifp; 1758 1759 /* 1760 * Drop locks before calling if_input() since it 1761 * may re-enter fxp_start() in the netisr case. 1762 * This would result in a lock reversal. Better 1763 * performance might be obtained by chaining all 1764 * packets received, dropping the lock, and then 1765 * calling if_input() on each one. 1766 */ 1767 FXP_UNLOCK(sc); 1768 (*ifp->if_input)(ifp, m); 1769 FXP_LOCK(sc); 1770 } 1771 } 1772 if (rnr) { 1773 fxp_scb_wait(sc); 1774 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 1775 sc->fxp_desc.rx_head->rx_addr); 1776 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_START); 1777 } 1778 } 1779 1780 /* 1781 * Update packet in/out/collision statistics. The i82557 doesn't 1782 * allow you to access these counters without doing a fairly 1783 * expensive DMA to get _all_ of the statistics it maintains, so 1784 * we do this operation here only once per second. The statistics 1785 * counters in the kernel are updated from the previous dump-stats 1786 * DMA and then a new dump-stats DMA is started. The on-chip 1787 * counters are zeroed when the DMA completes. If we can't start 1788 * the DMA immediately, we don't wait - we just prepare to read 1789 * them again next time. 1790 */ 1791 static void 1792 fxp_tick(void *xsc) 1793 { 1794 struct fxp_softc *sc = xsc; 1795 struct ifnet *ifp = &sc->sc_if; 1796 struct fxp_stats *sp = sc->fxp_stats; 1797 int s; 1798 1799 FXP_LOCK(sc); 1800 s = splimp(); 1801 bus_dmamap_sync(sc->fxp_stag, sc->fxp_smap, BUS_DMASYNC_POSTREAD); 1802 ifp->if_opackets += le32toh(sp->tx_good); 1803 ifp->if_collisions += le32toh(sp->tx_total_collisions); 1804 if (sp->rx_good) { 1805 ifp->if_ipackets += le32toh(sp->rx_good); 1806 sc->rx_idle_secs = 0; 1807 } else { 1808 /* 1809 * Receiver's been idle for another second. 1810 */ 1811 sc->rx_idle_secs++; 1812 } 1813 ifp->if_ierrors += 1814 le32toh(sp->rx_crc_errors) + 1815 le32toh(sp->rx_alignment_errors) + 1816 le32toh(sp->rx_rnr_errors) + 1817 le32toh(sp->rx_overrun_errors); 1818 /* 1819 * If any transmit underruns occured, bump up the transmit 1820 * threshold by another 512 bytes (64 * 8). 1821 */ 1822 if (sp->tx_underruns) { 1823 ifp->if_oerrors += le32toh(sp->tx_underruns); 1824 if (tx_threshold < 192) 1825 tx_threshold += 64; 1826 } 1827 1828 /* 1829 * Release any xmit buffers that have completed DMA. This isn't 1830 * strictly necessary to do here, but it's advantagous for mbufs 1831 * with external storage to be released in a timely manner rather 1832 * than being defered for a potentially long time. This limits 1833 * the delay to a maximum of one second. 1834 */ 1835 fxp_txeof(sc); 1836 1837 /* 1838 * If we haven't received any packets in FXP_MAC_RX_IDLE seconds, 1839 * then assume the receiver has locked up and attempt to clear 1840 * the condition by reprogramming the multicast filter. This is 1841 * a work-around for a bug in the 82557 where the receiver locks 1842 * up if it gets certain types of garbage in the syncronization 1843 * bits prior to the packet header. This bug is supposed to only 1844 * occur in 10Mbps mode, but has been seen to occur in 100Mbps 1845 * mode as well (perhaps due to a 10/100 speed transition). 1846 */ 1847 if (sc->rx_idle_secs > FXP_MAX_RX_IDLE) { 1848 sc->rx_idle_secs = 0; 1849 fxp_mc_setup(sc); 1850 } 1851 /* 1852 * If there is no pending command, start another stats 1853 * dump. Otherwise punt for now. 1854 */ 1855 if (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) == 0) { 1856 /* 1857 * Start another stats dump. 1858 */ 1859 bus_dmamap_sync(sc->fxp_stag, sc->fxp_smap, 1860 BUS_DMASYNC_PREREAD); 1861 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_DUMPRESET); 1862 } else { 1863 /* 1864 * A previous command is still waiting to be accepted. 1865 * Just zero our copy of the stats and wait for the 1866 * next timer event to update them. 1867 */ 1868 sp->tx_good = 0; 1869 sp->tx_underruns = 0; 1870 sp->tx_total_collisions = 0; 1871 1872 sp->rx_good = 0; 1873 sp->rx_crc_errors = 0; 1874 sp->rx_alignment_errors = 0; 1875 sp->rx_rnr_errors = 0; 1876 sp->rx_overrun_errors = 0; 1877 } 1878 if (sc->miibus != NULL) 1879 mii_tick(device_get_softc(sc->miibus)); 1880 1881 /* 1882 * Schedule another timeout one second from now. 1883 */ 1884 callout_reset(&sc->stat_ch, hz, fxp_tick, sc); 1885 FXP_UNLOCK(sc); 1886 splx(s); 1887 } 1888 1889 /* 1890 * Stop the interface. Cancels the statistics updater and resets 1891 * the interface. 1892 */ 1893 static void 1894 fxp_stop(struct fxp_softc *sc) 1895 { 1896 struct ifnet *ifp = &sc->sc_if; 1897 struct fxp_tx *txp; 1898 int i; 1899 1900 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1901 ifp->if_timer = 0; 1902 1903 #ifdef DEVICE_POLLING 1904 ether_poll_deregister(ifp); 1905 #endif 1906 /* 1907 * Cancel stats updater. 1908 */ 1909 callout_stop(&sc->stat_ch); 1910 1911 /* 1912 * Issue software reset, which also unloads the microcode. 1913 */ 1914 sc->flags &= ~FXP_FLAG_UCODE; 1915 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SOFTWARE_RESET); 1916 DELAY(50); 1917 1918 /* 1919 * Release any xmit buffers. 1920 */ 1921 txp = sc->fxp_desc.tx_list; 1922 if (txp != NULL) { 1923 for (i = 0; i < FXP_NTXCB; i++) { 1924 if (txp[i].tx_mbuf != NULL) { 1925 bus_dmamap_sync(sc->fxp_mtag, txp[i].tx_map, 1926 BUS_DMASYNC_POSTWRITE); 1927 bus_dmamap_unload(sc->fxp_mtag, txp[i].tx_map); 1928 m_freem(txp[i].tx_mbuf); 1929 txp[i].tx_mbuf = NULL; 1930 /* clear this to reset csum offload bits */ 1931 txp[i].tx_cb->tbd[0].tb_addr = 0; 1932 } 1933 } 1934 } 1935 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE); 1936 sc->tx_queued = 0; 1937 } 1938 1939 /* 1940 * Watchdog/transmission transmit timeout handler. Called when a 1941 * transmission is started on the interface, but no interrupt is 1942 * received before the timeout. This usually indicates that the 1943 * card has wedged for some reason. 1944 */ 1945 static void 1946 fxp_watchdog(struct ifnet *ifp) 1947 { 1948 struct fxp_softc *sc = ifp->if_softc; 1949 1950 FXP_LOCK(sc); 1951 device_printf(sc->dev, "device timeout\n"); 1952 ifp->if_oerrors++; 1953 1954 fxp_init_body(sc); 1955 FXP_UNLOCK(sc); 1956 } 1957 1958 /* 1959 * Acquire locks and then call the real initialization function. This 1960 * is necessary because ether_ioctl() calls if_init() and this would 1961 * result in mutex recursion if the mutex was held. 1962 */ 1963 static void 1964 fxp_init(void *xsc) 1965 { 1966 struct fxp_softc *sc = xsc; 1967 1968 FXP_LOCK(sc); 1969 fxp_init_body(sc); 1970 FXP_UNLOCK(sc); 1971 } 1972 1973 /* 1974 * Perform device initialization. This routine must be called with the 1975 * softc lock held. 1976 */ 1977 static void 1978 fxp_init_body(struct fxp_softc *sc) 1979 { 1980 struct ifnet *ifp = &sc->sc_if; 1981 struct fxp_cb_config *cbp; 1982 struct fxp_cb_ias *cb_ias; 1983 struct fxp_cb_tx *tcbp; 1984 struct fxp_tx *txp; 1985 struct fxp_cb_mcs *mcsp; 1986 int i, prm, s; 1987 1988 mtx_assert(&sc->sc_mtx, MA_OWNED); 1989 s = splimp(); 1990 /* 1991 * Cancel any pending I/O 1992 */ 1993 fxp_stop(sc); 1994 1995 prm = (ifp->if_flags & IFF_PROMISC) ? 1 : 0; 1996 1997 /* 1998 * Initialize base of CBL and RFA memory. Loading with zero 1999 * sets it up for regular linear addressing. 2000 */ 2001 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 0); 2002 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_BASE); 2003 2004 fxp_scb_wait(sc); 2005 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_BASE); 2006 2007 /* 2008 * Initialize base of dump-stats buffer. 2009 */ 2010 fxp_scb_wait(sc); 2011 bus_dmamap_sync(sc->fxp_stag, sc->fxp_smap, BUS_DMASYNC_PREREAD); 2012 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->stats_addr); 2013 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_DUMP_ADR); 2014 2015 /* 2016 * Attempt to load microcode if requested. 2017 */ 2018 if (ifp->if_flags & IFF_LINK0 && (sc->flags & FXP_FLAG_UCODE) == 0) 2019 fxp_load_ucode(sc); 2020 2021 /* 2022 * Initialize the multicast address list. 2023 */ 2024 if (fxp_mc_addrs(sc)) { 2025 mcsp = sc->mcsp; 2026 mcsp->cb_status = 0; 2027 mcsp->cb_command = 2028 htole16(FXP_CB_COMMAND_MCAS | FXP_CB_COMMAND_EL); 2029 mcsp->link_addr = 0xffffffff; 2030 /* 2031 * Start the multicast setup command. 2032 */ 2033 fxp_scb_wait(sc); 2034 bus_dmamap_sync(sc->mcs_tag, sc->mcs_map, BUS_DMASYNC_PREWRITE); 2035 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->mcs_addr); 2036 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2037 /* ...and wait for it to complete. */ 2038 fxp_dma_wait(sc, &mcsp->cb_status, sc->mcs_tag, sc->mcs_map); 2039 bus_dmamap_sync(sc->mcs_tag, sc->mcs_map, 2040 BUS_DMASYNC_POSTWRITE); 2041 } 2042 2043 /* 2044 * We temporarily use memory that contains the TxCB list to 2045 * construct the config CB. The TxCB list memory is rebuilt 2046 * later. 2047 */ 2048 cbp = (struct fxp_cb_config *)sc->fxp_desc.cbl_list; 2049 2050 /* 2051 * This bcopy is kind of disgusting, but there are a bunch of must be 2052 * zero and must be one bits in this structure and this is the easiest 2053 * way to initialize them all to proper values. 2054 */ 2055 bcopy(fxp_cb_config_template, cbp, sizeof(fxp_cb_config_template)); 2056 2057 cbp->cb_status = 0; 2058 cbp->cb_command = htole16(FXP_CB_COMMAND_CONFIG | 2059 FXP_CB_COMMAND_EL); 2060 cbp->link_addr = 0xffffffff; /* (no) next command */ 2061 cbp->byte_count = sc->flags & FXP_FLAG_EXT_RFA ? 32 : 22; 2062 cbp->rx_fifo_limit = 8; /* rx fifo threshold (32 bytes) */ 2063 cbp->tx_fifo_limit = 0; /* tx fifo threshold (0 bytes) */ 2064 cbp->adaptive_ifs = 0; /* (no) adaptive interframe spacing */ 2065 cbp->mwi_enable = sc->flags & FXP_FLAG_MWI_ENABLE ? 1 : 0; 2066 cbp->type_enable = 0; /* actually reserved */ 2067 cbp->read_align_en = sc->flags & FXP_FLAG_READ_ALIGN ? 1 : 0; 2068 cbp->end_wr_on_cl = sc->flags & FXP_FLAG_WRITE_ALIGN ? 1 : 0; 2069 cbp->rx_dma_bytecount = 0; /* (no) rx DMA max */ 2070 cbp->tx_dma_bytecount = 0; /* (no) tx DMA max */ 2071 cbp->dma_mbce = 0; /* (disable) dma max counters */ 2072 cbp->late_scb = 0; /* (don't) defer SCB update */ 2073 cbp->direct_dma_dis = 1; /* disable direct rcv dma mode */ 2074 cbp->tno_int_or_tco_en =0; /* (disable) tx not okay interrupt */ 2075 cbp->ci_int = 1; /* interrupt on CU idle */ 2076 cbp->ext_txcb_dis = sc->flags & FXP_FLAG_EXT_TXCB ? 0 : 1; 2077 cbp->ext_stats_dis = 1; /* disable extended counters */ 2078 cbp->keep_overrun_rx = 0; /* don't pass overrun frames to host */ 2079 cbp->save_bf = sc->revision == FXP_REV_82557 ? 1 : prm; 2080 cbp->disc_short_rx = !prm; /* discard short packets */ 2081 cbp->underrun_retry = 1; /* retry mode (once) on DMA underrun */ 2082 cbp->two_frames = 0; /* do not limit FIFO to 2 frames */ 2083 cbp->dyn_tbd = 0; /* (no) dynamic TBD mode */ 2084 cbp->ext_rfa = sc->flags & FXP_FLAG_EXT_RFA ? 1 : 0; 2085 cbp->mediatype = sc->flags & FXP_FLAG_SERIAL_MEDIA ? 0 : 1; 2086 cbp->csma_dis = 0; /* (don't) disable link */ 2087 cbp->tcp_udp_cksum = 0; /* (don't) enable checksum */ 2088 cbp->vlan_tco = 0; /* (don't) enable vlan wakeup */ 2089 cbp->link_wake_en = 0; /* (don't) assert PME# on link change */ 2090 cbp->arp_wake_en = 0; /* (don't) assert PME# on arp */ 2091 cbp->mc_wake_en = 0; /* (don't) enable PME# on mcmatch */ 2092 cbp->nsai = 1; /* (don't) disable source addr insert */ 2093 cbp->preamble_length = 2; /* (7 byte) preamble */ 2094 cbp->loopback = 0; /* (don't) loopback */ 2095 cbp->linear_priority = 0; /* (normal CSMA/CD operation) */ 2096 cbp->linear_pri_mode = 0; /* (wait after xmit only) */ 2097 cbp->interfrm_spacing = 6; /* (96 bits of) interframe spacing */ 2098 cbp->promiscuous = prm; /* promiscuous mode */ 2099 cbp->bcast_disable = 0; /* (don't) disable broadcasts */ 2100 cbp->wait_after_win = 0; /* (don't) enable modified backoff alg*/ 2101 cbp->ignore_ul = 0; /* consider U/L bit in IA matching */ 2102 cbp->crc16_en = 0; /* (don't) enable crc-16 algorithm */ 2103 cbp->crscdt = sc->flags & FXP_FLAG_SERIAL_MEDIA ? 1 : 0; 2104 2105 cbp->stripping = !prm; /* truncate rx packet to byte count */ 2106 cbp->padding = 1; /* (do) pad short tx packets */ 2107 cbp->rcv_crc_xfer = 0; /* (don't) xfer CRC to host */ 2108 cbp->long_rx_en = sc->flags & FXP_FLAG_LONG_PKT_EN ? 1 : 0; 2109 cbp->ia_wake_en = 0; /* (don't) wake up on address match */ 2110 cbp->magic_pkt_dis = 0; /* (don't) disable magic packet */ 2111 /* must set wake_en in PMCSR also */ 2112 cbp->force_fdx = 0; /* (don't) force full duplex */ 2113 cbp->fdx_pin_en = 1; /* (enable) FDX# pin */ 2114 cbp->multi_ia = 0; /* (don't) accept multiple IAs */ 2115 cbp->mc_all = sc->flags & FXP_FLAG_ALL_MCAST ? 1 : 0; 2116 cbp->gamla_rx = sc->flags & FXP_FLAG_EXT_RFA ? 1 : 0; 2117 2118 if (fxp_noflow || sc->revision == FXP_REV_82557) { 2119 /* 2120 * The 82557 has no hardware flow control, the values 2121 * below are the defaults for the chip. 2122 */ 2123 cbp->fc_delay_lsb = 0; 2124 cbp->fc_delay_msb = 0x40; 2125 cbp->pri_fc_thresh = 3; 2126 cbp->tx_fc_dis = 0; 2127 cbp->rx_fc_restop = 0; 2128 cbp->rx_fc_restart = 0; 2129 cbp->fc_filter = 0; 2130 cbp->pri_fc_loc = 1; 2131 } else { 2132 cbp->fc_delay_lsb = 0x1f; 2133 cbp->fc_delay_msb = 0x01; 2134 cbp->pri_fc_thresh = 3; 2135 cbp->tx_fc_dis = 0; /* enable transmit FC */ 2136 cbp->rx_fc_restop = 1; /* enable FC restop frames */ 2137 cbp->rx_fc_restart = 1; /* enable FC restart frames */ 2138 cbp->fc_filter = !prm; /* drop FC frames to host */ 2139 cbp->pri_fc_loc = 1; /* FC pri location (byte31) */ 2140 } 2141 2142 /* 2143 * Start the config command/DMA. 2144 */ 2145 fxp_scb_wait(sc); 2146 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE); 2147 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->fxp_desc.cbl_addr); 2148 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2149 /* ...and wait for it to complete. */ 2150 fxp_dma_wait(sc, &cbp->cb_status, sc->cbl_tag, sc->cbl_map); 2151 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_POSTWRITE); 2152 2153 /* 2154 * Now initialize the station address. Temporarily use the TxCB 2155 * memory area like we did above for the config CB. 2156 */ 2157 cb_ias = (struct fxp_cb_ias *)sc->fxp_desc.cbl_list; 2158 cb_ias->cb_status = 0; 2159 cb_ias->cb_command = htole16(FXP_CB_COMMAND_IAS | FXP_CB_COMMAND_EL); 2160 cb_ias->link_addr = 0xffffffff; 2161 bcopy(sc->arpcom.ac_enaddr, cb_ias->macaddr, 2162 sizeof(sc->arpcom.ac_enaddr)); 2163 2164 /* 2165 * Start the IAS (Individual Address Setup) command/DMA. 2166 */ 2167 fxp_scb_wait(sc); 2168 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE); 2169 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2170 /* ...and wait for it to complete. */ 2171 fxp_dma_wait(sc, &cb_ias->cb_status, sc->cbl_tag, sc->cbl_map); 2172 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_POSTWRITE); 2173 2174 /* 2175 * Initialize transmit control block (TxCB) list. 2176 */ 2177 txp = sc->fxp_desc.tx_list; 2178 tcbp = sc->fxp_desc.cbl_list; 2179 bzero(tcbp, FXP_TXCB_SZ); 2180 for (i = 0; i < FXP_NTXCB; i++) { 2181 txp[i].tx_cb = tcbp + i; 2182 txp[i].tx_mbuf = NULL; 2183 tcbp[i].cb_status = htole16(FXP_CB_STATUS_C | FXP_CB_STATUS_OK); 2184 tcbp[i].cb_command = htole16(FXP_CB_COMMAND_NOP); 2185 tcbp[i].link_addr = htole32(sc->fxp_desc.cbl_addr + 2186 (((i + 1) & FXP_TXCB_MASK) * sizeof(struct fxp_cb_tx))); 2187 if (sc->flags & FXP_FLAG_EXT_TXCB) 2188 tcbp[i].tbd_array_addr = 2189 htole32(FXP_TXCB_DMA_ADDR(sc, &tcbp[i].tbd[2])); 2190 else 2191 tcbp[i].tbd_array_addr = 2192 htole32(FXP_TXCB_DMA_ADDR(sc, &tcbp[i].tbd[0])); 2193 txp[i].tx_next = &txp[(i + 1) & FXP_TXCB_MASK]; 2194 } 2195 /* 2196 * Set the suspend flag on the first TxCB and start the control 2197 * unit. It will execute the NOP and then suspend. 2198 */ 2199 tcbp->cb_command = htole16(FXP_CB_COMMAND_NOP | FXP_CB_COMMAND_S); 2200 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE); 2201 sc->fxp_desc.tx_first = sc->fxp_desc.tx_last = txp; 2202 sc->tx_queued = 1; 2203 2204 fxp_scb_wait(sc); 2205 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2206 2207 /* 2208 * Initialize receiver buffer area - RFA. 2209 */ 2210 fxp_scb_wait(sc); 2211 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->fxp_desc.rx_head->rx_addr); 2212 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_START); 2213 2214 /* 2215 * Set current media. 2216 */ 2217 if (sc->miibus != NULL) 2218 mii_mediachg(device_get_softc(sc->miibus)); 2219 2220 ifp->if_flags |= IFF_RUNNING; 2221 ifp->if_flags &= ~IFF_OACTIVE; 2222 2223 /* 2224 * Enable interrupts. 2225 */ 2226 #ifdef DEVICE_POLLING 2227 /* 2228 * ... but only do that if we are not polling. And because (presumably) 2229 * the default is interrupts on, we need to disable them explicitly! 2230 */ 2231 if ( ifp->if_flags & IFF_POLLING ) 2232 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE); 2233 else 2234 #endif /* DEVICE_POLLING */ 2235 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, 0); 2236 2237 /* 2238 * Start stats updater. 2239 */ 2240 callout_reset(&sc->stat_ch, hz, fxp_tick, sc); 2241 splx(s); 2242 } 2243 2244 static int 2245 fxp_serial_ifmedia_upd(struct ifnet *ifp) 2246 { 2247 2248 return (0); 2249 } 2250 2251 static void 2252 fxp_serial_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 2253 { 2254 2255 ifmr->ifm_active = IFM_ETHER|IFM_MANUAL; 2256 } 2257 2258 /* 2259 * Change media according to request. 2260 */ 2261 static int 2262 fxp_ifmedia_upd(struct ifnet *ifp) 2263 { 2264 struct fxp_softc *sc = ifp->if_softc; 2265 struct mii_data *mii; 2266 2267 mii = device_get_softc(sc->miibus); 2268 mii_mediachg(mii); 2269 return (0); 2270 } 2271 2272 /* 2273 * Notify the world which media we're using. 2274 */ 2275 static void 2276 fxp_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 2277 { 2278 struct fxp_softc *sc = ifp->if_softc; 2279 struct mii_data *mii; 2280 2281 mii = device_get_softc(sc->miibus); 2282 mii_pollstat(mii); 2283 ifmr->ifm_active = mii->mii_media_active; 2284 ifmr->ifm_status = mii->mii_media_status; 2285 2286 if (ifmr->ifm_status & IFM_10_T && sc->flags & FXP_FLAG_CU_RESUME_BUG) 2287 sc->cu_resume_bug = 1; 2288 else 2289 sc->cu_resume_bug = 0; 2290 } 2291 2292 /* 2293 * Add a buffer to the end of the RFA buffer list. 2294 * Return 0 if successful, 1 for failure. A failure results in 2295 * adding the 'oldm' (if non-NULL) on to the end of the list - 2296 * tossing out its old contents and recycling it. 2297 * The RFA struct is stuck at the beginning of mbuf cluster and the 2298 * data pointer is fixed up to point just past it. 2299 */ 2300 static int 2301 fxp_add_rfabuf(struct fxp_softc *sc, struct fxp_rx *rxp) 2302 { 2303 struct mbuf *m; 2304 struct fxp_rfa *rfa, *p_rfa; 2305 struct fxp_rx *p_rx; 2306 bus_dmamap_t tmp_map; 2307 int error; 2308 2309 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 2310 if (m == NULL) 2311 return (ENOBUFS); 2312 2313 /* 2314 * Move the data pointer up so that the incoming data packet 2315 * will be 32-bit aligned. 2316 */ 2317 m->m_data += RFA_ALIGNMENT_FUDGE; 2318 2319 /* 2320 * Get a pointer to the base of the mbuf cluster and move 2321 * data start past it. 2322 */ 2323 rfa = mtod(m, struct fxp_rfa *); 2324 m->m_data += sc->rfa_size; 2325 rfa->size = htole16(MCLBYTES - sc->rfa_size - RFA_ALIGNMENT_FUDGE); 2326 2327 rfa->rfa_status = 0; 2328 rfa->rfa_control = htole16(FXP_RFA_CONTROL_EL); 2329 rfa->actual_size = 0; 2330 2331 /* 2332 * Initialize the rest of the RFA. Note that since the RFA 2333 * is misaligned, we cannot store values directly. We're thus 2334 * using the le32enc() function which handles endianness and 2335 * is also alignment-safe. 2336 */ 2337 le32enc(&rfa->link_addr, 0xffffffff); 2338 le32enc(&rfa->rbd_addr, 0xffffffff); 2339 2340 /* Map the RFA into DMA memory. */ 2341 error = bus_dmamap_load(sc->fxp_mtag, sc->spare_map, rfa, 2342 MCLBYTES - RFA_ALIGNMENT_FUDGE, fxp_dma_map_addr, 2343 &rxp->rx_addr, 0); 2344 if (error) { 2345 m_freem(m); 2346 return (error); 2347 } 2348 2349 bus_dmamap_unload(sc->fxp_mtag, rxp->rx_map); 2350 tmp_map = sc->spare_map; 2351 sc->spare_map = rxp->rx_map; 2352 rxp->rx_map = tmp_map; 2353 rxp->rx_mbuf = m; 2354 2355 bus_dmamap_sync(sc->fxp_mtag, rxp->rx_map, 2356 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2357 2358 /* 2359 * If there are other buffers already on the list, attach this 2360 * one to the end by fixing up the tail to point to this one. 2361 */ 2362 if (sc->fxp_desc.rx_head != NULL) { 2363 p_rx = sc->fxp_desc.rx_tail; 2364 p_rfa = (struct fxp_rfa *) 2365 (p_rx->rx_mbuf->m_ext.ext_buf + RFA_ALIGNMENT_FUDGE); 2366 p_rx->rx_next = rxp; 2367 le32enc(&p_rfa->link_addr, rxp->rx_addr); 2368 p_rfa->rfa_control = 0; 2369 bus_dmamap_sync(sc->fxp_mtag, p_rx->rx_map, 2370 BUS_DMASYNC_PREWRITE); 2371 } else { 2372 rxp->rx_next = NULL; 2373 sc->fxp_desc.rx_head = rxp; 2374 } 2375 sc->fxp_desc.rx_tail = rxp; 2376 return (0); 2377 } 2378 2379 static volatile int 2380 fxp_miibus_readreg(device_t dev, int phy, int reg) 2381 { 2382 struct fxp_softc *sc = device_get_softc(dev); 2383 int count = 10000; 2384 int value; 2385 2386 CSR_WRITE_4(sc, FXP_CSR_MDICONTROL, 2387 (FXP_MDI_READ << 26) | (reg << 16) | (phy << 21)); 2388 2389 while (((value = CSR_READ_4(sc, FXP_CSR_MDICONTROL)) & 0x10000000) == 0 2390 && count--) 2391 DELAY(10); 2392 2393 if (count <= 0) 2394 device_printf(dev, "fxp_miibus_readreg: timed out\n"); 2395 2396 return (value & 0xffff); 2397 } 2398 2399 static void 2400 fxp_miibus_writereg(device_t dev, int phy, int reg, int value) 2401 { 2402 struct fxp_softc *sc = device_get_softc(dev); 2403 int count = 10000; 2404 2405 CSR_WRITE_4(sc, FXP_CSR_MDICONTROL, 2406 (FXP_MDI_WRITE << 26) | (reg << 16) | (phy << 21) | 2407 (value & 0xffff)); 2408 2409 while ((CSR_READ_4(sc, FXP_CSR_MDICONTROL) & 0x10000000) == 0 && 2410 count--) 2411 DELAY(10); 2412 2413 if (count <= 0) 2414 device_printf(dev, "fxp_miibus_writereg: timed out\n"); 2415 } 2416 2417 static int 2418 fxp_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 2419 { 2420 struct fxp_softc *sc = ifp->if_softc; 2421 struct ifreq *ifr = (struct ifreq *)data; 2422 struct mii_data *mii; 2423 int s, error = 0; 2424 2425 /* 2426 * Detaching causes us to call ioctl with the mutex owned. Preclude 2427 * that by saying we're busy if the lock is already held. 2428 */ 2429 if (mtx_owned(&sc->sc_mtx)) 2430 return (EBUSY); 2431 2432 FXP_LOCK(sc); 2433 s = splimp(); 2434 2435 switch (command) { 2436 case SIOCSIFFLAGS: 2437 if (ifp->if_flags & IFF_ALLMULTI) 2438 sc->flags |= FXP_FLAG_ALL_MCAST; 2439 else 2440 sc->flags &= ~FXP_FLAG_ALL_MCAST; 2441 2442 /* 2443 * If interface is marked up and not running, then start it. 2444 * If it is marked down and running, stop it. 2445 * XXX If it's up then re-initialize it. This is so flags 2446 * such as IFF_PROMISC are handled. 2447 */ 2448 if (ifp->if_flags & IFF_UP) { 2449 fxp_init_body(sc); 2450 } else { 2451 if (ifp->if_flags & IFF_RUNNING) 2452 fxp_stop(sc); 2453 } 2454 break; 2455 2456 case SIOCADDMULTI: 2457 case SIOCDELMULTI: 2458 if (ifp->if_flags & IFF_ALLMULTI) 2459 sc->flags |= FXP_FLAG_ALL_MCAST; 2460 else 2461 sc->flags &= ~FXP_FLAG_ALL_MCAST; 2462 /* 2463 * Multicast list has changed; set the hardware filter 2464 * accordingly. 2465 */ 2466 if ((sc->flags & FXP_FLAG_ALL_MCAST) == 0) 2467 fxp_mc_setup(sc); 2468 /* 2469 * fxp_mc_setup() can set FXP_FLAG_ALL_MCAST, so check it 2470 * again rather than else {}. 2471 */ 2472 if (sc->flags & FXP_FLAG_ALL_MCAST) 2473 fxp_init_body(sc); 2474 error = 0; 2475 break; 2476 2477 case SIOCSIFMEDIA: 2478 case SIOCGIFMEDIA: 2479 if (sc->miibus != NULL) { 2480 mii = device_get_softc(sc->miibus); 2481 error = ifmedia_ioctl(ifp, ifr, 2482 &mii->mii_media, command); 2483 } else { 2484 error = ifmedia_ioctl(ifp, ifr, &sc->sc_media, command); 2485 } 2486 break; 2487 2488 default: 2489 /* 2490 * ether_ioctl() will eventually call fxp_start() which 2491 * will result in mutex recursion so drop it first. 2492 */ 2493 FXP_UNLOCK(sc); 2494 error = ether_ioctl(ifp, command, data); 2495 } 2496 if (mtx_owned(&sc->sc_mtx)) 2497 FXP_UNLOCK(sc); 2498 splx(s); 2499 return (error); 2500 } 2501 2502 /* 2503 * Fill in the multicast address list and return number of entries. 2504 */ 2505 static int 2506 fxp_mc_addrs(struct fxp_softc *sc) 2507 { 2508 struct fxp_cb_mcs *mcsp = sc->mcsp; 2509 struct ifnet *ifp = &sc->sc_if; 2510 struct ifmultiaddr *ifma; 2511 int nmcasts; 2512 2513 nmcasts = 0; 2514 if ((sc->flags & FXP_FLAG_ALL_MCAST) == 0) { 2515 #if __FreeBSD_version < 500000 2516 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 2517 #else 2518 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 2519 #endif 2520 if (ifma->ifma_addr->sa_family != AF_LINK) 2521 continue; 2522 if (nmcasts >= MAXMCADDR) { 2523 sc->flags |= FXP_FLAG_ALL_MCAST; 2524 nmcasts = 0; 2525 break; 2526 } 2527 bcopy(LLADDR((struct sockaddr_dl *)ifma->ifma_addr), 2528 &sc->mcsp->mc_addr[nmcasts][0], ETHER_ADDR_LEN); 2529 nmcasts++; 2530 } 2531 } 2532 mcsp->mc_cnt = htole16(nmcasts * ETHER_ADDR_LEN); 2533 return (nmcasts); 2534 } 2535 2536 /* 2537 * Program the multicast filter. 2538 * 2539 * We have an artificial restriction that the multicast setup command 2540 * must be the first command in the chain, so we take steps to ensure 2541 * this. By requiring this, it allows us to keep up the performance of 2542 * the pre-initialized command ring (esp. link pointers) by not actually 2543 * inserting the mcsetup command in the ring - i.e. its link pointer 2544 * points to the TxCB ring, but the mcsetup descriptor itself is not part 2545 * of it. We then can do 'CU_START' on the mcsetup descriptor and have it 2546 * lead into the regular TxCB ring when it completes. 2547 * 2548 * This function must be called at splimp. 2549 */ 2550 static void 2551 fxp_mc_setup(struct fxp_softc *sc) 2552 { 2553 struct fxp_cb_mcs *mcsp = sc->mcsp; 2554 struct ifnet *ifp = &sc->sc_if; 2555 struct fxp_tx *txp; 2556 int count; 2557 2558 /* 2559 * If there are queued commands, we must wait until they are all 2560 * completed. If we are already waiting, then add a NOP command 2561 * with interrupt option so that we're notified when all commands 2562 * have been completed - fxp_start() ensures that no additional 2563 * TX commands will be added when need_mcsetup is true. 2564 */ 2565 if (sc->tx_queued) { 2566 /* 2567 * need_mcsetup will be true if we are already waiting for the 2568 * NOP command to be completed (see below). In this case, bail. 2569 */ 2570 if (sc->need_mcsetup) 2571 return; 2572 sc->need_mcsetup = 1; 2573 2574 /* 2575 * Add a NOP command with interrupt so that we are notified 2576 * when all TX commands have been processed. 2577 */ 2578 txp = sc->fxp_desc.tx_last->tx_next; 2579 txp->tx_mbuf = NULL; 2580 txp->tx_cb->cb_status = 0; 2581 txp->tx_cb->cb_command = htole16(FXP_CB_COMMAND_NOP | 2582 FXP_CB_COMMAND_S | FXP_CB_COMMAND_I); 2583 /* 2584 * Advance the end of list forward. 2585 */ 2586 sc->fxp_desc.tx_last->tx_cb->cb_command &= 2587 htole16(~FXP_CB_COMMAND_S); 2588 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE); 2589 sc->fxp_desc.tx_last = txp; 2590 sc->tx_queued++; 2591 /* 2592 * Issue a resume in case the CU has just suspended. 2593 */ 2594 fxp_scb_wait(sc); 2595 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_RESUME); 2596 /* 2597 * Set a 5 second timer just in case we don't hear from the 2598 * card again. 2599 */ 2600 ifp->if_timer = 5; 2601 2602 return; 2603 } 2604 sc->need_mcsetup = 0; 2605 2606 /* 2607 * Initialize multicast setup descriptor. 2608 */ 2609 mcsp->cb_status = 0; 2610 mcsp->cb_command = htole16(FXP_CB_COMMAND_MCAS | 2611 FXP_CB_COMMAND_S | FXP_CB_COMMAND_I); 2612 mcsp->link_addr = htole32(sc->fxp_desc.cbl_addr); 2613 txp = &sc->fxp_desc.mcs_tx; 2614 txp->tx_mbuf = NULL; 2615 txp->tx_cb = (struct fxp_cb_tx *)sc->mcsp; 2616 txp->tx_next = sc->fxp_desc.tx_list; 2617 (void) fxp_mc_addrs(sc); 2618 sc->fxp_desc.tx_first = sc->fxp_desc.tx_last = txp; 2619 sc->tx_queued = 1; 2620 2621 /* 2622 * Wait until command unit is not active. This should never 2623 * be the case when nothing is queued, but make sure anyway. 2624 */ 2625 count = 100; 2626 while ((CSR_READ_1(sc, FXP_CSR_SCB_RUSCUS) >> 6) == 2627 FXP_SCB_CUS_ACTIVE && --count) 2628 DELAY(10); 2629 if (count == 0) { 2630 device_printf(sc->dev, "command queue timeout\n"); 2631 return; 2632 } 2633 2634 /* 2635 * Start the multicast setup command. 2636 */ 2637 fxp_scb_wait(sc); 2638 bus_dmamap_sync(sc->mcs_tag, sc->mcs_map, BUS_DMASYNC_PREWRITE); 2639 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->mcs_addr); 2640 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2641 2642 ifp->if_timer = 2; 2643 return; 2644 } 2645 2646 static u_int32_t fxp_ucode_d101a[] = D101_A_RCVBUNDLE_UCODE; 2647 static u_int32_t fxp_ucode_d101b0[] = D101_B0_RCVBUNDLE_UCODE; 2648 static u_int32_t fxp_ucode_d101ma[] = D101M_B_RCVBUNDLE_UCODE; 2649 static u_int32_t fxp_ucode_d101s[] = D101S_RCVBUNDLE_UCODE; 2650 static u_int32_t fxp_ucode_d102[] = D102_B_RCVBUNDLE_UCODE; 2651 static u_int32_t fxp_ucode_d102c[] = D102_C_RCVBUNDLE_UCODE; 2652 2653 #define UCODE(x) x, sizeof(x) 2654 2655 struct ucode { 2656 u_int32_t revision; 2657 u_int32_t *ucode; 2658 int length; 2659 u_short int_delay_offset; 2660 u_short bundle_max_offset; 2661 } ucode_table[] = { 2662 { FXP_REV_82558_A4, UCODE(fxp_ucode_d101a), D101_CPUSAVER_DWORD, 0 }, 2663 { FXP_REV_82558_B0, UCODE(fxp_ucode_d101b0), D101_CPUSAVER_DWORD, 0 }, 2664 { FXP_REV_82559_A0, UCODE(fxp_ucode_d101ma), 2665 D101M_CPUSAVER_DWORD, D101M_CPUSAVER_BUNDLE_MAX_DWORD }, 2666 { FXP_REV_82559S_A, UCODE(fxp_ucode_d101s), 2667 D101S_CPUSAVER_DWORD, D101S_CPUSAVER_BUNDLE_MAX_DWORD }, 2668 { FXP_REV_82550, UCODE(fxp_ucode_d102), 2669 D102_B_CPUSAVER_DWORD, D102_B_CPUSAVER_BUNDLE_MAX_DWORD }, 2670 { FXP_REV_82550_C, UCODE(fxp_ucode_d102c), 2671 D102_C_CPUSAVER_DWORD, D102_C_CPUSAVER_BUNDLE_MAX_DWORD }, 2672 { 0, NULL, 0, 0, 0 } 2673 }; 2674 2675 static void 2676 fxp_load_ucode(struct fxp_softc *sc) 2677 { 2678 struct ucode *uc; 2679 struct fxp_cb_ucode *cbp; 2680 2681 for (uc = ucode_table; uc->ucode != NULL; uc++) 2682 if (sc->revision == uc->revision) 2683 break; 2684 if (uc->ucode == NULL) 2685 return; 2686 cbp = (struct fxp_cb_ucode *)sc->fxp_desc.cbl_list; 2687 cbp->cb_status = 0; 2688 cbp->cb_command = htole16(FXP_CB_COMMAND_UCODE | FXP_CB_COMMAND_EL); 2689 cbp->link_addr = 0xffffffff; /* (no) next command */ 2690 memcpy(cbp->ucode, uc->ucode, uc->length); 2691 if (uc->int_delay_offset) 2692 *(u_int16_t *)&cbp->ucode[uc->int_delay_offset] = 2693 htole16(sc->tunable_int_delay + sc->tunable_int_delay / 2); 2694 if (uc->bundle_max_offset) 2695 *(u_int16_t *)&cbp->ucode[uc->bundle_max_offset] = 2696 htole16(sc->tunable_bundle_max); 2697 /* 2698 * Download the ucode to the chip. 2699 */ 2700 fxp_scb_wait(sc); 2701 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE); 2702 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->fxp_desc.cbl_addr); 2703 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2704 /* ...and wait for it to complete. */ 2705 fxp_dma_wait(sc, &cbp->cb_status, sc->cbl_tag, sc->cbl_map); 2706 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_POSTWRITE); 2707 device_printf(sc->dev, 2708 "Microcode loaded, int_delay: %d usec bundle_max: %d\n", 2709 sc->tunable_int_delay, 2710 uc->bundle_max_offset == 0 ? 0 : sc->tunable_bundle_max); 2711 sc->flags |= FXP_FLAG_UCODE; 2712 } 2713 2714 static int 2715 sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high) 2716 { 2717 int error, value; 2718 2719 value = *(int *)arg1; 2720 error = sysctl_handle_int(oidp, &value, 0, req); 2721 if (error || !req->newptr) 2722 return (error); 2723 if (value < low || value > high) 2724 return (EINVAL); 2725 *(int *)arg1 = value; 2726 return (0); 2727 } 2728 2729 /* 2730 * Interrupt delay is expressed in microseconds, a multiplier is used 2731 * to convert this to the appropriate clock ticks before using. 2732 */ 2733 static int 2734 sysctl_hw_fxp_int_delay(SYSCTL_HANDLER_ARGS) 2735 { 2736 return (sysctl_int_range(oidp, arg1, arg2, req, 300, 3000)); 2737 } 2738 2739 static int 2740 sysctl_hw_fxp_bundle_max(SYSCTL_HANDLER_ARGS) 2741 { 2742 return (sysctl_int_range(oidp, arg1, arg2, req, 1, 0xffff)); 2743 } 2744