1 /*- 2 * Copyright (c) 1995, David Greenman 3 * Copyright (c) 2001 Jonathan Lemon <jlemon@freebsd.org> 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice unmodified, this list of conditions, and the following 11 * disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 * 28 */ 29 30 #include <sys/cdefs.h> 31 __FBSDID("$FreeBSD$"); 32 33 /* 34 * Intel EtherExpress Pro/100B PCI Fast Ethernet driver 35 */ 36 37 #include <sys/cdefs.h> 38 __FBSDID("$FreeBSD$"); 39 40 #include <sys/param.h> 41 #include <sys/systm.h> 42 #include <sys/endian.h> 43 #include <sys/mbuf.h> 44 /* #include <sys/mutex.h> */ 45 #include <sys/kernel.h> 46 #include <sys/socket.h> 47 #include <sys/sysctl.h> 48 49 #include <net/if.h> 50 #include <net/if_dl.h> 51 #include <net/if_media.h> 52 53 #include <net/bpf.h> 54 #include <sys/sockio.h> 55 #include <sys/bus.h> 56 #include <machine/bus.h> 57 #include <sys/rman.h> 58 #include <machine/resource.h> 59 60 #include <net/ethernet.h> 61 #include <net/if_arp.h> 62 63 #include <machine/clock.h> /* for DELAY */ 64 65 #include <net/if_types.h> 66 #include <net/if_vlan_var.h> 67 68 #ifdef FXP_IP_CSUM_WAR 69 #include <netinet/in.h> 70 #include <netinet/in_systm.h> 71 #include <netinet/ip.h> 72 #include <machine/in_cksum.h> 73 #endif 74 75 #include <dev/pci/pcivar.h> 76 #include <dev/pci/pcireg.h> /* for PCIM_CMD_xxx */ 77 78 #include <dev/mii/mii.h> 79 #include <dev/mii/miivar.h> 80 81 #include <dev/fxp/if_fxpreg.h> 82 #include <dev/fxp/if_fxpvar.h> 83 #include <dev/fxp/rcvbundl.h> 84 85 MODULE_DEPEND(fxp, pci, 1, 1, 1); 86 MODULE_DEPEND(fxp, ether, 1, 1, 1); 87 MODULE_DEPEND(fxp, miibus, 1, 1, 1); 88 #include "miibus_if.h" 89 90 /* 91 * NOTE! On the Alpha, we have an alignment constraint. The 92 * card DMAs the packet immediately following the RFA. However, 93 * the first thing in the packet is a 14-byte Ethernet header. 94 * This means that the packet is misaligned. To compensate, 95 * we actually offset the RFA 2 bytes into the cluster. This 96 * alignes the packet after the Ethernet header at a 32-bit 97 * boundary. HOWEVER! This means that the RFA is misaligned! 98 */ 99 #define RFA_ALIGNMENT_FUDGE 2 100 101 /* 102 * Set initial transmit threshold at 64 (512 bytes). This is 103 * increased by 64 (512 bytes) at a time, to maximum of 192 104 * (1536 bytes), if an underrun occurs. 105 */ 106 static int tx_threshold = 64; 107 108 /* 109 * The configuration byte map has several undefined fields which 110 * must be one or must be zero. Set up a template for these bits 111 * only, (assuming a 82557 chip) leaving the actual configuration 112 * to fxp_init. 113 * 114 * See struct fxp_cb_config for the bit definitions. 115 */ 116 static u_char fxp_cb_config_template[] = { 117 0x0, 0x0, /* cb_status */ 118 0x0, 0x0, /* cb_command */ 119 0x0, 0x0, 0x0, 0x0, /* link_addr */ 120 0x0, /* 0 */ 121 0x0, /* 1 */ 122 0x0, /* 2 */ 123 0x0, /* 3 */ 124 0x0, /* 4 */ 125 0x0, /* 5 */ 126 0x32, /* 6 */ 127 0x0, /* 7 */ 128 0x0, /* 8 */ 129 0x0, /* 9 */ 130 0x6, /* 10 */ 131 0x0, /* 11 */ 132 0x0, /* 12 */ 133 0x0, /* 13 */ 134 0xf2, /* 14 */ 135 0x48, /* 15 */ 136 0x0, /* 16 */ 137 0x40, /* 17 */ 138 0xf0, /* 18 */ 139 0x0, /* 19 */ 140 0x3f, /* 20 */ 141 0x5 /* 21 */ 142 }; 143 144 struct fxp_ident { 145 u_int16_t devid; 146 int16_t revid; /* -1 matches anything */ 147 char *name; 148 }; 149 150 /* 151 * Claim various Intel PCI device identifiers for this driver. The 152 * sub-vendor and sub-device field are extensively used to identify 153 * particular variants, but we don't currently differentiate between 154 * them. 155 */ 156 static struct fxp_ident fxp_ident_table[] = { 157 { 0x1029, -1, "Intel 82559 PCI/CardBus Pro/100" }, 158 { 0x1030, -1, "Intel 82559 Pro/100 Ethernet" }, 159 { 0x1031, -1, "Intel 82801CAM (ICH3) Pro/100 VE Ethernet" }, 160 { 0x1032, -1, "Intel 82801CAM (ICH3) Pro/100 VE Ethernet" }, 161 { 0x1033, -1, "Intel 82801CAM (ICH3) Pro/100 VM Ethernet" }, 162 { 0x1034, -1, "Intel 82801CAM (ICH3) Pro/100 VM Ethernet" }, 163 { 0x1035, -1, "Intel 82801CAM (ICH3) Pro/100 Ethernet" }, 164 { 0x1036, -1, "Intel 82801CAM (ICH3) Pro/100 Ethernet" }, 165 { 0x1037, -1, "Intel 82801CAM (ICH3) Pro/100 Ethernet" }, 166 { 0x1038, -1, "Intel 82801CAM (ICH3) Pro/100 VM Ethernet" }, 167 { 0x1039, -1, "Intel 82801DB (ICH4) Pro/100 VE Ethernet" }, 168 { 0x103A, -1, "Intel 82801DB (ICH4) Pro/100 Ethernet" }, 169 { 0x103B, -1, "Intel 82801DB (ICH4) Pro/100 VM Ethernet" }, 170 { 0x103C, -1, "Intel 82801DB (ICH4) Pro/100 Ethernet" }, 171 { 0x103D, -1, "Intel 82801DB (ICH4) Pro/100 VE Ethernet" }, 172 { 0x103E, -1, "Intel 82801DB (ICH4) Pro/100 VM Ethernet" }, 173 { 0x1050, -1, "Intel 82801BA (D865) Pro/100 VE Ethernet" }, 174 { 0x1059, -1, "Intel 82551QM Pro/100 M Mobile Connection" }, 175 { 0x1209, -1, "Intel 82559ER Embedded 10/100 Ethernet" }, 176 { 0x1229, 0x01, "Intel 82557 Pro/100 Ethernet" }, 177 { 0x1229, 0x02, "Intel 82557 Pro/100 Ethernet" }, 178 { 0x1229, 0x03, "Intel 82557 Pro/100 Ethernet" }, 179 { 0x1229, 0x04, "Intel 82558 Pro/100 Ethernet" }, 180 { 0x1229, 0x05, "Intel 82558 Pro/100 Ethernet" }, 181 { 0x1229, 0x06, "Intel 82559 Pro/100 Ethernet" }, 182 { 0x1229, 0x07, "Intel 82559 Pro/100 Ethernet" }, 183 { 0x1229, 0x08, "Intel 82559 Pro/100 Ethernet" }, 184 { 0x1229, 0x09, "Intel 82559ER Pro/100 Ethernet" }, 185 { 0x1229, 0x0c, "Intel 82550 Pro/100 Ethernet" }, 186 { 0x1229, 0x0d, "Intel 82550 Pro/100 Ethernet" }, 187 { 0x1229, 0x0e, "Intel 82550 Pro/100 Ethernet" }, 188 { 0x1229, 0x0f, "Intel 82551 Pro/100 Ethernet" }, 189 { 0x1229, 0x10, "Intel 82551 Pro/100 Ethernet" }, 190 { 0x1229, -1, "Intel 82557/8/9 Pro/100 Ethernet" }, 191 { 0x2449, -1, "Intel 82801BA/CAM (ICH2/3) Pro/100 Ethernet" }, 192 { 0, -1, NULL }, 193 }; 194 195 #ifdef FXP_IP_CSUM_WAR 196 #define FXP_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 197 #else 198 #define FXP_CSUM_FEATURES (CSUM_TCP | CSUM_UDP) 199 #endif 200 201 static int fxp_probe(device_t dev); 202 static int fxp_attach(device_t dev); 203 static int fxp_detach(device_t dev); 204 static int fxp_shutdown(device_t dev); 205 static int fxp_suspend(device_t dev); 206 static int fxp_resume(device_t dev); 207 208 static void fxp_intr(void *xsc); 209 static void fxp_intr_body(struct fxp_softc *sc, struct ifnet *ifp, 210 u_int8_t statack, int count); 211 static void fxp_init(void *xsc); 212 static void fxp_init_body(struct fxp_softc *sc); 213 static void fxp_tick(void *xsc); 214 #ifndef BURN_BRIDGES 215 static void fxp_powerstate_d0(device_t dev); 216 #endif 217 static void fxp_start(struct ifnet *ifp); 218 static void fxp_start_body(struct ifnet *ifp); 219 static void fxp_stop(struct fxp_softc *sc); 220 static void fxp_release(struct fxp_softc *sc); 221 static int fxp_ioctl(struct ifnet *ifp, u_long command, 222 caddr_t data); 223 static void fxp_watchdog(struct ifnet *ifp); 224 static int fxp_add_rfabuf(struct fxp_softc *sc, 225 struct fxp_rx *rxp); 226 static int fxp_mc_addrs(struct fxp_softc *sc); 227 static void fxp_mc_setup(struct fxp_softc *sc); 228 static u_int16_t fxp_eeprom_getword(struct fxp_softc *sc, int offset, 229 int autosize); 230 static void fxp_eeprom_putword(struct fxp_softc *sc, int offset, 231 u_int16_t data); 232 static void fxp_autosize_eeprom(struct fxp_softc *sc); 233 static void fxp_read_eeprom(struct fxp_softc *sc, u_short *data, 234 int offset, int words); 235 static void fxp_write_eeprom(struct fxp_softc *sc, u_short *data, 236 int offset, int words); 237 static int fxp_ifmedia_upd(struct ifnet *ifp); 238 static void fxp_ifmedia_sts(struct ifnet *ifp, 239 struct ifmediareq *ifmr); 240 static int fxp_serial_ifmedia_upd(struct ifnet *ifp); 241 static void fxp_serial_ifmedia_sts(struct ifnet *ifp, 242 struct ifmediareq *ifmr); 243 static volatile int fxp_miibus_readreg(device_t dev, int phy, int reg); 244 static void fxp_miibus_writereg(device_t dev, int phy, int reg, 245 int value); 246 static void fxp_load_ucode(struct fxp_softc *sc); 247 static int sysctl_int_range(SYSCTL_HANDLER_ARGS, 248 int low, int high); 249 static int sysctl_hw_fxp_bundle_max(SYSCTL_HANDLER_ARGS); 250 static int sysctl_hw_fxp_int_delay(SYSCTL_HANDLER_ARGS); 251 static void fxp_scb_wait(struct fxp_softc *sc); 252 static void fxp_scb_cmd(struct fxp_softc *sc, int cmd); 253 static void fxp_dma_wait(struct fxp_softc *sc, 254 volatile u_int16_t *status, bus_dma_tag_t dmat, 255 bus_dmamap_t map); 256 257 static device_method_t fxp_methods[] = { 258 /* Device interface */ 259 DEVMETHOD(device_probe, fxp_probe), 260 DEVMETHOD(device_attach, fxp_attach), 261 DEVMETHOD(device_detach, fxp_detach), 262 DEVMETHOD(device_shutdown, fxp_shutdown), 263 DEVMETHOD(device_suspend, fxp_suspend), 264 DEVMETHOD(device_resume, fxp_resume), 265 266 /* MII interface */ 267 DEVMETHOD(miibus_readreg, fxp_miibus_readreg), 268 DEVMETHOD(miibus_writereg, fxp_miibus_writereg), 269 270 { 0, 0 } 271 }; 272 273 static driver_t fxp_driver = { 274 "fxp", 275 fxp_methods, 276 sizeof(struct fxp_softc), 277 }; 278 279 static devclass_t fxp_devclass; 280 281 DRIVER_MODULE(fxp, pci, fxp_driver, fxp_devclass, 0, 0); 282 DRIVER_MODULE(fxp, cardbus, fxp_driver, fxp_devclass, 0, 0); 283 DRIVER_MODULE(miibus, fxp, miibus_driver, miibus_devclass, 0, 0); 284 285 static int fxp_rnr; 286 SYSCTL_INT(_hw, OID_AUTO, fxp_rnr, CTLFLAG_RW, &fxp_rnr, 0, "fxp rnr events"); 287 288 static int fxp_noflow; 289 SYSCTL_INT(_hw, OID_AUTO, fxp_noflow, CTLFLAG_RW, &fxp_noflow, 0, "fxp flow control disabled"); 290 TUNABLE_INT("hw.fxp_noflow", &fxp_noflow); 291 292 /* 293 * Wait for the previous command to be accepted (but not necessarily 294 * completed). 295 */ 296 static void 297 fxp_scb_wait(struct fxp_softc *sc) 298 { 299 int i = 10000; 300 301 while (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) && --i) 302 DELAY(2); 303 if (i == 0) 304 device_printf(sc->dev, "SCB timeout: 0x%x 0x%x 0x%x 0x%x\n", 305 CSR_READ_1(sc, FXP_CSR_SCB_COMMAND), 306 CSR_READ_1(sc, FXP_CSR_SCB_STATACK), 307 CSR_READ_1(sc, FXP_CSR_SCB_RUSCUS), 308 CSR_READ_2(sc, FXP_CSR_FLOWCONTROL)); 309 } 310 311 static void 312 fxp_scb_cmd(struct fxp_softc *sc, int cmd) 313 { 314 315 if (cmd == FXP_SCB_COMMAND_CU_RESUME && sc->cu_resume_bug) { 316 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_CB_COMMAND_NOP); 317 fxp_scb_wait(sc); 318 } 319 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, cmd); 320 } 321 322 static void 323 fxp_dma_wait(struct fxp_softc *sc, volatile u_int16_t *status, 324 bus_dma_tag_t dmat, bus_dmamap_t map) 325 { 326 int i = 10000; 327 328 bus_dmamap_sync(dmat, map, BUS_DMASYNC_POSTREAD); 329 while (!(le16toh(*status) & FXP_CB_STATUS_C) && --i) { 330 DELAY(2); 331 bus_dmamap_sync(dmat, map, BUS_DMASYNC_POSTREAD); 332 } 333 if (i == 0) 334 device_printf(sc->dev, "DMA timeout\n"); 335 } 336 337 /* 338 * Return identification string if this device is ours. 339 */ 340 static int 341 fxp_probe(device_t dev) 342 { 343 u_int16_t devid; 344 u_int8_t revid; 345 struct fxp_ident *ident; 346 347 if (pci_get_vendor(dev) == FXP_VENDORID_INTEL) { 348 devid = pci_get_device(dev); 349 revid = pci_get_revid(dev); 350 for (ident = fxp_ident_table; ident->name != NULL; ident++) { 351 if (ident->devid == devid && 352 (ident->revid == revid || ident->revid == -1)) { 353 device_set_desc(dev, ident->name); 354 return (0); 355 } 356 } 357 } 358 return (ENXIO); 359 } 360 361 #ifndef BURN_BRIDGES 362 static void 363 fxp_powerstate_d0(device_t dev) 364 { 365 #if __FreeBSD_version >= 430002 366 u_int32_t iobase, membase, irq; 367 368 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 369 /* Save important PCI config data. */ 370 iobase = pci_read_config(dev, FXP_PCI_IOBA, 4); 371 membase = pci_read_config(dev, FXP_PCI_MMBA, 4); 372 irq = pci_read_config(dev, PCIR_INTLINE, 4); 373 374 /* Reset the power state. */ 375 device_printf(dev, "chip is in D%d power mode " 376 "-- setting to D0\n", pci_get_powerstate(dev)); 377 378 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 379 380 /* Restore PCI config data. */ 381 pci_write_config(dev, FXP_PCI_IOBA, iobase, 4); 382 pci_write_config(dev, FXP_PCI_MMBA, membase, 4); 383 pci_write_config(dev, PCIR_INTLINE, irq, 4); 384 } 385 #endif 386 } 387 #endif 388 389 static void 390 fxp_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error) 391 { 392 u_int32_t *addr; 393 394 if (error) 395 return; 396 397 KASSERT(nseg == 1, ("too many DMA segments, %d should be 1", nseg)); 398 addr = arg; 399 *addr = segs->ds_addr; 400 } 401 402 static int 403 fxp_attach(device_t dev) 404 { 405 int error = 0; 406 struct fxp_softc *sc = device_get_softc(dev); 407 struct ifnet *ifp; 408 struct fxp_rx *rxp; 409 u_int32_t val; 410 u_int16_t data, myea[ETHER_ADDR_LEN / 2]; 411 int i, rid, m1, m2, prefer_iomap, maxtxseg; 412 int s, ipcbxmit_disable; 413 414 sc->dev = dev; 415 callout_init(&sc->stat_ch, CALLOUT_MPSAFE); 416 sysctl_ctx_init(&sc->sysctl_ctx); 417 mtx_init(&sc->sc_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 418 MTX_DEF); 419 ifmedia_init(&sc->sc_media, 0, fxp_serial_ifmedia_upd, 420 fxp_serial_ifmedia_sts); 421 422 s = splimp(); 423 424 /* 425 * Enable bus mastering. 426 */ 427 pci_enable_busmaster(dev); 428 val = pci_read_config(dev, PCIR_COMMAND, 2); 429 #ifndef BURN_BRIDGES 430 fxp_powerstate_d0(dev); 431 #endif 432 /* 433 * Figure out which we should try first - memory mapping or i/o mapping? 434 * We default to memory mapping. Then we accept an override from the 435 * command line. Then we check to see which one is enabled. 436 */ 437 m1 = PCIM_CMD_MEMEN; 438 m2 = PCIM_CMD_PORTEN; 439 prefer_iomap = 0; 440 if (resource_int_value(device_get_name(dev), device_get_unit(dev), 441 "prefer_iomap", &prefer_iomap) == 0 && prefer_iomap != 0) { 442 m1 = PCIM_CMD_PORTEN; 443 m2 = PCIM_CMD_MEMEN; 444 } 445 446 sc->rtp = (m1 == PCIM_CMD_MEMEN)? SYS_RES_MEMORY : SYS_RES_IOPORT; 447 sc->rgd = (m1 == PCIM_CMD_MEMEN)? FXP_PCI_MMBA : FXP_PCI_IOBA; 448 sc->mem = bus_alloc_resource(dev, sc->rtp, &sc->rgd, 449 0, ~0, 1, RF_ACTIVE); 450 if (sc->mem == NULL) { 451 sc->rtp = 452 (m2 == PCIM_CMD_MEMEN)? SYS_RES_MEMORY : SYS_RES_IOPORT; 453 sc->rgd = (m2 == PCIM_CMD_MEMEN)? FXP_PCI_MMBA : FXP_PCI_IOBA; 454 sc->mem = bus_alloc_resource(dev, sc->rtp, &sc->rgd, 455 0, ~0, 1, RF_ACTIVE); 456 } 457 458 if (!sc->mem) { 459 error = ENXIO; 460 goto fail; 461 } 462 if (bootverbose) { 463 device_printf(dev, "using %s space register mapping\n", 464 sc->rtp == SYS_RES_MEMORY? "memory" : "I/O"); 465 } 466 467 sc->sc_st = rman_get_bustag(sc->mem); 468 sc->sc_sh = rman_get_bushandle(sc->mem); 469 470 /* 471 * Allocate our interrupt. 472 */ 473 rid = 0; 474 sc->irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 475 RF_SHAREABLE | RF_ACTIVE); 476 if (sc->irq == NULL) { 477 device_printf(dev, "could not map interrupt\n"); 478 error = ENXIO; 479 goto fail; 480 } 481 482 /* 483 * Reset to a stable state. 484 */ 485 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET); 486 DELAY(10); 487 488 /* 489 * Find out how large of an SEEPROM we have. 490 */ 491 fxp_autosize_eeprom(sc); 492 493 /* 494 * Determine whether we must use the 503 serial interface. 495 */ 496 fxp_read_eeprom(sc, &data, 6, 1); 497 if ((data & FXP_PHY_DEVICE_MASK) != 0 && 498 (data & FXP_PHY_SERIAL_ONLY)) 499 sc->flags |= FXP_FLAG_SERIAL_MEDIA; 500 501 /* 502 * Create the sysctl tree 503 */ 504 sc->sysctl_tree = SYSCTL_ADD_NODE(&sc->sysctl_ctx, 505 SYSCTL_STATIC_CHILDREN(_hw), OID_AUTO, 506 device_get_nameunit(dev), CTLFLAG_RD, 0, ""); 507 if (sc->sysctl_tree == NULL) { 508 error = ENXIO; 509 goto fail; 510 } 511 SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree), 512 OID_AUTO, "int_delay", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_PRISON, 513 &sc->tunable_int_delay, 0, sysctl_hw_fxp_int_delay, "I", 514 "FXP driver receive interrupt microcode bundling delay"); 515 SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree), 516 OID_AUTO, "bundle_max", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_PRISON, 517 &sc->tunable_bundle_max, 0, sysctl_hw_fxp_bundle_max, "I", 518 "FXP driver receive interrupt microcode bundle size limit"); 519 520 /* 521 * Pull in device tunables. 522 */ 523 sc->tunable_int_delay = TUNABLE_INT_DELAY; 524 sc->tunable_bundle_max = TUNABLE_BUNDLE_MAX; 525 (void) resource_int_value(device_get_name(dev), device_get_unit(dev), 526 "int_delay", &sc->tunable_int_delay); 527 (void) resource_int_value(device_get_name(dev), device_get_unit(dev), 528 "bundle_max", &sc->tunable_bundle_max); 529 530 /* 531 * Find out the chip revision; lump all 82557 revs together. 532 */ 533 fxp_read_eeprom(sc, &data, 5, 1); 534 if ((data >> 8) == 1) 535 sc->revision = FXP_REV_82557; 536 else 537 sc->revision = pci_get_revid(dev); 538 539 /* 540 * Enable workarounds for certain chip revision deficiencies. 541 * 542 * Systems based on the ICH2/ICH2-M chip from Intel, and possibly 543 * some systems based a normal 82559 design, have a defect where 544 * the chip can cause a PCI protocol violation if it receives 545 * a CU_RESUME command when it is entering the IDLE state. The 546 * workaround is to disable Dynamic Standby Mode, so the chip never 547 * deasserts CLKRUN#, and always remains in an active state. 548 * 549 * See Intel 82801BA/82801BAM Specification Update, Errata #30. 550 */ 551 i = pci_get_device(dev); 552 if (i == 0x2449 || (i > 0x1030 && i < 0x1039) || 553 sc->revision >= FXP_REV_82559_A0) { 554 fxp_read_eeprom(sc, &data, 10, 1); 555 if (data & 0x02) { /* STB enable */ 556 u_int16_t cksum; 557 int i; 558 559 device_printf(dev, 560 "Disabling dynamic standby mode in EEPROM\n"); 561 data &= ~0x02; 562 fxp_write_eeprom(sc, &data, 10, 1); 563 device_printf(dev, "New EEPROM ID: 0x%x\n", data); 564 cksum = 0; 565 for (i = 0; i < (1 << sc->eeprom_size) - 1; i++) { 566 fxp_read_eeprom(sc, &data, i, 1); 567 cksum += data; 568 } 569 i = (1 << sc->eeprom_size) - 1; 570 cksum = 0xBABA - cksum; 571 fxp_read_eeprom(sc, &data, i, 1); 572 fxp_write_eeprom(sc, &cksum, i, 1); 573 device_printf(dev, 574 "EEPROM checksum @ 0x%x: 0x%x -> 0x%x\n", 575 i, data, cksum); 576 #if 1 577 /* 578 * If the user elects to continue, try the software 579 * workaround, as it is better than nothing. 580 */ 581 sc->flags |= FXP_FLAG_CU_RESUME_BUG; 582 #endif 583 } 584 } 585 586 /* 587 * If we are not a 82557 chip, we can enable extended features. 588 */ 589 if (sc->revision != FXP_REV_82557) { 590 /* 591 * If MWI is enabled in the PCI configuration, and there 592 * is a valid cacheline size (8 or 16 dwords), then tell 593 * the board to turn on MWI. 594 */ 595 if (val & PCIM_CMD_MWRICEN && 596 pci_read_config(dev, PCIR_CACHELNSZ, 1) != 0) 597 sc->flags |= FXP_FLAG_MWI_ENABLE; 598 599 /* turn on the extended TxCB feature */ 600 sc->flags |= FXP_FLAG_EXT_TXCB; 601 602 /* enable reception of long frames for VLAN */ 603 sc->flags |= FXP_FLAG_LONG_PKT_EN; 604 } 605 606 /* 607 * Enable use of extended RFDs and TCBs for 82550 608 * and later chips. Note: we need extended TXCB support 609 * too, but that's already enabled by the code above. 610 * Be careful to do this only on the right devices. 611 * 612 * At least some 82550 cards probed as "chip=0x12298086 rev=0x0d" 613 * truncate packets that end with an mbuf containing 1 to 3 bytes 614 * when used with this feature enabled in the previous version of the 615 * driver. This problem appears to be fixed now that the driver 616 * always sets the hardware parse bit in the IPCB structure, which 617 * the "Intel 8255x 10/100 Mbps Ethernet Controller Family Open 618 * Source Software Developer Manual" says is necessary in the 619 * cases where packet truncation was observed. 620 * 621 * The device hint "hint.fxp.UNIT_NUMBER.ipcbxmit_disable" 622 * allows this feature to be disabled at boot time. 623 * 624 * If fxp is not compiled into the kernel, this feature may also 625 * be disabled at run time: 626 * # kldunload fxp 627 * # kenv hint.fxp.0.ipcbxmit_disable=1 628 * # kldload fxp 629 */ 630 631 if (resource_int_value("fxp", device_get_unit(dev), "ipcbxmit_disable", 632 &ipcbxmit_disable) != 0) 633 ipcbxmit_disable = 0; 634 if (ipcbxmit_disable == 0 && (sc->revision == FXP_REV_82550 || 635 sc->revision == FXP_REV_82550_C)) { 636 sc->rfa_size = sizeof (struct fxp_rfa); 637 sc->tx_cmd = FXP_CB_COMMAND_IPCBXMIT; 638 sc->flags |= FXP_FLAG_EXT_RFA; 639 } else { 640 sc->rfa_size = sizeof (struct fxp_rfa) - FXP_RFAX_LEN; 641 sc->tx_cmd = FXP_CB_COMMAND_XMIT; 642 } 643 644 /* 645 * Allocate DMA tags and DMA safe memory. 646 */ 647 maxtxseg = sc->flags & FXP_FLAG_EXT_RFA ? FXP_NTXSEG - 1 : FXP_NTXSEG; 648 error = bus_dma_tag_create(NULL, 2, 0, BUS_SPACE_MAXADDR_32BIT, 649 BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES * maxtxseg, 650 maxtxseg, MCLBYTES, 0, busdma_lock_mutex, &Giant, &sc->fxp_mtag); 651 if (error) { 652 device_printf(dev, "could not allocate dma tag\n"); 653 goto fail; 654 } 655 656 error = bus_dma_tag_create(NULL, 4, 0, BUS_SPACE_MAXADDR_32BIT, 657 BUS_SPACE_MAXADDR, NULL, NULL, sizeof(struct fxp_stats), 1, 658 sizeof(struct fxp_stats), 0, busdma_lock_mutex, &Giant, 659 &sc->fxp_stag); 660 if (error) { 661 device_printf(dev, "could not allocate dma tag\n"); 662 goto fail; 663 } 664 665 error = bus_dmamem_alloc(sc->fxp_stag, (void **)&sc->fxp_stats, 666 BUS_DMA_NOWAIT | BUS_DMA_ZERO, &sc->fxp_smap); 667 if (error) 668 goto fail; 669 error = bus_dmamap_load(sc->fxp_stag, sc->fxp_smap, sc->fxp_stats, 670 sizeof(struct fxp_stats), fxp_dma_map_addr, &sc->stats_addr, 0); 671 if (error) { 672 device_printf(dev, "could not map the stats buffer\n"); 673 goto fail; 674 } 675 676 error = bus_dma_tag_create(NULL, 4, 0, BUS_SPACE_MAXADDR_32BIT, 677 BUS_SPACE_MAXADDR, NULL, NULL, FXP_TXCB_SZ, 1, 678 FXP_TXCB_SZ, 0, busdma_lock_mutex, &Giant, &sc->cbl_tag); 679 if (error) { 680 device_printf(dev, "could not allocate dma tag\n"); 681 goto fail; 682 } 683 684 error = bus_dmamem_alloc(sc->cbl_tag, (void **)&sc->fxp_desc.cbl_list, 685 BUS_DMA_NOWAIT | BUS_DMA_ZERO, &sc->cbl_map); 686 if (error) 687 goto fail; 688 689 error = bus_dmamap_load(sc->cbl_tag, sc->cbl_map, 690 sc->fxp_desc.cbl_list, FXP_TXCB_SZ, fxp_dma_map_addr, 691 &sc->fxp_desc.cbl_addr, 0); 692 if (error) { 693 device_printf(dev, "could not map DMA memory\n"); 694 goto fail; 695 } 696 697 error = bus_dma_tag_create(NULL, 4, 0, BUS_SPACE_MAXADDR_32BIT, 698 BUS_SPACE_MAXADDR, NULL, NULL, sizeof(struct fxp_cb_mcs), 1, 699 sizeof(struct fxp_cb_mcs), 0, busdma_lock_mutex, &Giant, 700 &sc->mcs_tag); 701 if (error) { 702 device_printf(dev, "could not allocate dma tag\n"); 703 goto fail; 704 } 705 706 error = bus_dmamem_alloc(sc->mcs_tag, (void **)&sc->mcsp, 707 BUS_DMA_NOWAIT, &sc->mcs_map); 708 if (error) 709 goto fail; 710 error = bus_dmamap_load(sc->mcs_tag, sc->mcs_map, sc->mcsp, 711 sizeof(struct fxp_cb_mcs), fxp_dma_map_addr, &sc->mcs_addr, 0); 712 if (error) { 713 device_printf(dev, "can't map the multicast setup command\n"); 714 goto fail; 715 } 716 717 /* 718 * Pre-allocate the TX DMA maps. 719 */ 720 for (i = 0; i < FXP_NTXCB; i++) { 721 error = bus_dmamap_create(sc->fxp_mtag, 0, 722 &sc->fxp_desc.tx_list[i].tx_map); 723 if (error) { 724 device_printf(dev, "can't create DMA map for TX\n"); 725 goto fail; 726 } 727 } 728 error = bus_dmamap_create(sc->fxp_mtag, 0, &sc->spare_map); 729 if (error) { 730 device_printf(dev, "can't create spare DMA map\n"); 731 goto fail; 732 } 733 734 /* 735 * Pre-allocate our receive buffers. 736 */ 737 sc->fxp_desc.rx_head = sc->fxp_desc.rx_tail = NULL; 738 for (i = 0; i < FXP_NRFABUFS; i++) { 739 rxp = &sc->fxp_desc.rx_list[i]; 740 error = bus_dmamap_create(sc->fxp_mtag, 0, &rxp->rx_map); 741 if (error) { 742 device_printf(dev, "can't create DMA map for RX\n"); 743 goto fail; 744 } 745 if (fxp_add_rfabuf(sc, rxp) != 0) { 746 error = ENOMEM; 747 goto fail; 748 } 749 } 750 751 /* 752 * Read MAC address. 753 */ 754 fxp_read_eeprom(sc, myea, 0, 3); 755 sc->arpcom.ac_enaddr[0] = myea[0] & 0xff; 756 sc->arpcom.ac_enaddr[1] = myea[0] >> 8; 757 sc->arpcom.ac_enaddr[2] = myea[1] & 0xff; 758 sc->arpcom.ac_enaddr[3] = myea[1] >> 8; 759 sc->arpcom.ac_enaddr[4] = myea[2] & 0xff; 760 sc->arpcom.ac_enaddr[5] = myea[2] >> 8; 761 device_printf(dev, "Ethernet address %6D%s\n", 762 sc->arpcom.ac_enaddr, ":", 763 sc->flags & FXP_FLAG_SERIAL_MEDIA ? ", 10Mbps" : ""); 764 if (bootverbose) { 765 device_printf(dev, "PCI IDs: %04x %04x %04x %04x %04x\n", 766 pci_get_vendor(dev), pci_get_device(dev), 767 pci_get_subvendor(dev), pci_get_subdevice(dev), 768 pci_get_revid(dev)); 769 fxp_read_eeprom(sc, &data, 10, 1); 770 device_printf(dev, "Dynamic Standby mode is %s\n", 771 data & 0x02 ? "enabled" : "disabled"); 772 } 773 774 /* 775 * If this is only a 10Mbps device, then there is no MII, and 776 * the PHY will use a serial interface instead. 777 * 778 * The Seeq 80c24 AutoDUPLEX(tm) Ethernet Interface Adapter 779 * doesn't have a programming interface of any sort. The 780 * media is sensed automatically based on how the link partner 781 * is configured. This is, in essence, manual configuration. 782 */ 783 if (sc->flags & FXP_FLAG_SERIAL_MEDIA) { 784 ifmedia_add(&sc->sc_media, IFM_ETHER|IFM_MANUAL, 0, NULL); 785 ifmedia_set(&sc->sc_media, IFM_ETHER|IFM_MANUAL); 786 } else { 787 if (mii_phy_probe(dev, &sc->miibus, fxp_ifmedia_upd, 788 fxp_ifmedia_sts)) { 789 device_printf(dev, "MII without any PHY!\n"); 790 error = ENXIO; 791 goto fail; 792 } 793 } 794 795 ifp = &sc->arpcom.ac_if; 796 ifp->if_unit = device_get_unit(dev); 797 ifp->if_name = "fxp"; 798 ifp->if_output = ether_output; 799 ifp->if_baudrate = 100000000; 800 ifp->if_init = fxp_init; 801 ifp->if_softc = sc; 802 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 803 ifp->if_ioctl = fxp_ioctl; 804 ifp->if_start = fxp_start; 805 ifp->if_watchdog = fxp_watchdog; 806 807 /* Enable checksum offload for 82550 or better chips */ 808 if (sc->flags & FXP_FLAG_EXT_RFA) { 809 ifp->if_hwassist = FXP_CSUM_FEATURES; 810 ifp->if_capabilities = IFCAP_HWCSUM; 811 ifp->if_capenable = ifp->if_capabilities; 812 } 813 814 /* 815 * Attach the interface. 816 */ 817 ether_ifattach(ifp, sc->arpcom.ac_enaddr); 818 819 /* 820 * Tell the upper layer(s) we support long frames. 821 */ 822 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 823 ifp->if_capabilities |= IFCAP_VLAN_MTU; 824 825 /* 826 * Let the system queue as many packets as we have available 827 * TX descriptors. 828 */ 829 ifp->if_snd.ifq_maxlen = FXP_NTXCB - 1; 830 831 /* 832 * Hook our interrupt after all initialization is complete. 833 * XXX This driver has been tested with the INTR_MPSAFFE flag set 834 * however, ifp and its functions are not fully locked so MPSAFE 835 * should not be used unless you can handle potential data loss. 836 */ 837 error = bus_setup_intr(dev, sc->irq, INTR_TYPE_NET /*|INTR_MPSAFE*/, 838 fxp_intr, sc, &sc->ih); 839 if (error) { 840 device_printf(dev, "could not setup irq\n"); 841 ether_ifdetach(&sc->arpcom.ac_if); 842 goto fail; 843 } 844 845 fail: 846 splx(s); 847 if (error) 848 fxp_release(sc); 849 return (error); 850 } 851 852 /* 853 * Release all resources. The softc lock should not be held and the 854 * interrupt should already be torn down. 855 */ 856 static void 857 fxp_release(struct fxp_softc *sc) 858 { 859 struct fxp_rx *rxp; 860 struct fxp_tx *txp; 861 int i; 862 863 mtx_assert(&sc->sc_mtx, MA_NOTOWNED); 864 if (sc->ih) 865 panic("fxp_release() called with intr handle still active"); 866 if (sc->miibus) 867 device_delete_child(sc->dev, sc->miibus); 868 bus_generic_detach(sc->dev); 869 ifmedia_removeall(&sc->sc_media); 870 if (sc->fxp_desc.cbl_list) { 871 bus_dmamap_unload(sc->cbl_tag, sc->cbl_map); 872 bus_dmamem_free(sc->cbl_tag, sc->fxp_desc.cbl_list, 873 sc->cbl_map); 874 } 875 if (sc->fxp_stats) { 876 bus_dmamap_unload(sc->fxp_stag, sc->fxp_smap); 877 bus_dmamem_free(sc->fxp_stag, sc->fxp_stats, sc->fxp_smap); 878 } 879 if (sc->mcsp) { 880 bus_dmamap_unload(sc->mcs_tag, sc->mcs_map); 881 bus_dmamem_free(sc->mcs_tag, sc->mcsp, sc->mcs_map); 882 } 883 if (sc->irq) 884 bus_release_resource(sc->dev, SYS_RES_IRQ, 0, sc->irq); 885 if (sc->mem) 886 bus_release_resource(sc->dev, sc->rtp, sc->rgd, sc->mem); 887 if (sc->fxp_mtag) { 888 for (i = 0; i < FXP_NRFABUFS; i++) { 889 rxp = &sc->fxp_desc.rx_list[i]; 890 if (rxp->rx_mbuf != NULL) { 891 bus_dmamap_sync(sc->fxp_mtag, rxp->rx_map, 892 BUS_DMASYNC_POSTREAD); 893 bus_dmamap_unload(sc->fxp_mtag, rxp->rx_map); 894 m_freem(rxp->rx_mbuf); 895 } 896 bus_dmamap_destroy(sc->fxp_mtag, rxp->rx_map); 897 } 898 bus_dmamap_destroy(sc->fxp_mtag, sc->spare_map); 899 bus_dma_tag_destroy(sc->fxp_mtag); 900 } 901 if (sc->fxp_stag) { 902 for (i = 0; i < FXP_NTXCB; i++) { 903 txp = &sc->fxp_desc.tx_list[i]; 904 if (txp->tx_mbuf != NULL) { 905 bus_dmamap_sync(sc->fxp_mtag, txp->tx_map, 906 BUS_DMASYNC_POSTWRITE); 907 bus_dmamap_unload(sc->fxp_mtag, txp->tx_map); 908 m_freem(txp->tx_mbuf); 909 } 910 bus_dmamap_destroy(sc->fxp_mtag, txp->tx_map); 911 } 912 bus_dma_tag_destroy(sc->fxp_stag); 913 } 914 if (sc->cbl_tag) 915 bus_dma_tag_destroy(sc->cbl_tag); 916 if (sc->mcs_tag) 917 bus_dma_tag_destroy(sc->mcs_tag); 918 919 sysctl_ctx_free(&sc->sysctl_ctx); 920 921 mtx_destroy(&sc->sc_mtx); 922 } 923 924 /* 925 * Detach interface. 926 */ 927 static int 928 fxp_detach(device_t dev) 929 { 930 struct fxp_softc *sc = device_get_softc(dev); 931 int s; 932 933 FXP_LOCK(sc); 934 s = splimp(); 935 936 sc->suspended = 1; /* Do same thing as we do for suspend */ 937 /* 938 * Close down routes etc. 939 */ 940 ether_ifdetach(&sc->arpcom.ac_if); 941 942 /* 943 * Stop DMA and drop transmit queue, but disable interrupts first. 944 */ 945 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE); 946 fxp_stop(sc); 947 FXP_UNLOCK(sc); 948 949 /* 950 * Unhook interrupt before dropping lock. This is to prevent 951 * races with fxp_intr(). 952 */ 953 bus_teardown_intr(sc->dev, sc->irq, sc->ih); 954 sc->ih = NULL; 955 956 splx(s); 957 958 /* Release our allocated resources. */ 959 fxp_release(sc); 960 return (0); 961 } 962 963 /* 964 * Device shutdown routine. Called at system shutdown after sync. The 965 * main purpose of this routine is to shut off receiver DMA so that 966 * kernel memory doesn't get clobbered during warmboot. 967 */ 968 static int 969 fxp_shutdown(device_t dev) 970 { 971 /* 972 * Make sure that DMA is disabled prior to reboot. Not doing 973 * do could allow DMA to corrupt kernel memory during the 974 * reboot before the driver initializes. 975 */ 976 fxp_stop((struct fxp_softc *) device_get_softc(dev)); 977 return (0); 978 } 979 980 /* 981 * Device suspend routine. Stop the interface and save some PCI 982 * settings in case the BIOS doesn't restore them properly on 983 * resume. 984 */ 985 static int 986 fxp_suspend(device_t dev) 987 { 988 struct fxp_softc *sc = device_get_softc(dev); 989 int i, s; 990 991 FXP_LOCK(sc); 992 s = splimp(); 993 994 fxp_stop(sc); 995 996 for (i = 0; i < 5; i++) 997 sc->saved_maps[i] = pci_read_config(dev, PCIR_BAR(i), 4); 998 sc->saved_biosaddr = pci_read_config(dev, PCIR_BIOS, 4); 999 sc->saved_intline = pci_read_config(dev, PCIR_INTLINE, 1); 1000 sc->saved_cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1); 1001 sc->saved_lattimer = pci_read_config(dev, PCIR_LATTIMER, 1); 1002 1003 sc->suspended = 1; 1004 1005 FXP_UNLOCK(sc); 1006 splx(s); 1007 return (0); 1008 } 1009 1010 /* 1011 * Device resume routine. Restore some PCI settings in case the BIOS 1012 * doesn't, re-enable busmastering, and restart the interface if 1013 * appropriate. 1014 */ 1015 static int 1016 fxp_resume(device_t dev) 1017 { 1018 struct fxp_softc *sc = device_get_softc(dev); 1019 struct ifnet *ifp = &sc->sc_if; 1020 u_int16_t pci_command; 1021 int i, s; 1022 1023 FXP_LOCK(sc); 1024 s = splimp(); 1025 #ifndef BURN_BRIDGES 1026 fxp_powerstate_d0(dev); 1027 #endif 1028 /* better way to do this? */ 1029 for (i = 0; i < 5; i++) 1030 pci_write_config(dev, PCIR_BAR(i), sc->saved_maps[i], 4); 1031 pci_write_config(dev, PCIR_BIOS, sc->saved_biosaddr, 4); 1032 pci_write_config(dev, PCIR_INTLINE, sc->saved_intline, 1); 1033 pci_write_config(dev, PCIR_CACHELNSZ, sc->saved_cachelnsz, 1); 1034 pci_write_config(dev, PCIR_LATTIMER, sc->saved_lattimer, 1); 1035 1036 /* reenable busmastering */ 1037 pci_command = pci_read_config(dev, PCIR_COMMAND, 2); 1038 pci_command |= (PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN); 1039 pci_write_config(dev, PCIR_COMMAND, pci_command, 2); 1040 1041 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET); 1042 DELAY(10); 1043 1044 /* reinitialize interface if necessary */ 1045 if (ifp->if_flags & IFF_UP) 1046 fxp_init_body(sc); 1047 1048 sc->suspended = 0; 1049 1050 FXP_UNLOCK(sc); 1051 splx(s); 1052 return (0); 1053 } 1054 1055 static void 1056 fxp_eeprom_shiftin(struct fxp_softc *sc, int data, int length) 1057 { 1058 u_int16_t reg; 1059 int x; 1060 1061 /* 1062 * Shift in data. 1063 */ 1064 for (x = 1 << (length - 1); x; x >>= 1) { 1065 if (data & x) 1066 reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI; 1067 else 1068 reg = FXP_EEPROM_EECS; 1069 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 1070 DELAY(1); 1071 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK); 1072 DELAY(1); 1073 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 1074 DELAY(1); 1075 } 1076 } 1077 1078 /* 1079 * Read from the serial EEPROM. Basically, you manually shift in 1080 * the read opcode (one bit at a time) and then shift in the address, 1081 * and then you shift out the data (all of this one bit at a time). 1082 * The word size is 16 bits, so you have to provide the address for 1083 * every 16 bits of data. 1084 */ 1085 static u_int16_t 1086 fxp_eeprom_getword(struct fxp_softc *sc, int offset, int autosize) 1087 { 1088 u_int16_t reg, data; 1089 int x; 1090 1091 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 1092 /* 1093 * Shift in read opcode. 1094 */ 1095 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_READ, 3); 1096 /* 1097 * Shift in address. 1098 */ 1099 data = 0; 1100 for (x = 1 << (sc->eeprom_size - 1); x; x >>= 1) { 1101 if (offset & x) 1102 reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI; 1103 else 1104 reg = FXP_EEPROM_EECS; 1105 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 1106 DELAY(1); 1107 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK); 1108 DELAY(1); 1109 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 1110 DELAY(1); 1111 reg = CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO; 1112 data++; 1113 if (autosize && reg == 0) { 1114 sc->eeprom_size = data; 1115 break; 1116 } 1117 } 1118 /* 1119 * Shift out data. 1120 */ 1121 data = 0; 1122 reg = FXP_EEPROM_EECS; 1123 for (x = 1 << 15; x; x >>= 1) { 1124 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK); 1125 DELAY(1); 1126 if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO) 1127 data |= x; 1128 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 1129 DELAY(1); 1130 } 1131 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 1132 DELAY(1); 1133 1134 return (data); 1135 } 1136 1137 static void 1138 fxp_eeprom_putword(struct fxp_softc *sc, int offset, u_int16_t data) 1139 { 1140 int i; 1141 1142 /* 1143 * Erase/write enable. 1144 */ 1145 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 1146 fxp_eeprom_shiftin(sc, 0x4, 3); 1147 fxp_eeprom_shiftin(sc, 0x03 << (sc->eeprom_size - 2), sc->eeprom_size); 1148 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 1149 DELAY(1); 1150 /* 1151 * Shift in write opcode, address, data. 1152 */ 1153 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 1154 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_WRITE, 3); 1155 fxp_eeprom_shiftin(sc, offset, sc->eeprom_size); 1156 fxp_eeprom_shiftin(sc, data, 16); 1157 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 1158 DELAY(1); 1159 /* 1160 * Wait for EEPROM to finish up. 1161 */ 1162 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 1163 DELAY(1); 1164 for (i = 0; i < 1000; i++) { 1165 if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO) 1166 break; 1167 DELAY(50); 1168 } 1169 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 1170 DELAY(1); 1171 /* 1172 * Erase/write disable. 1173 */ 1174 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 1175 fxp_eeprom_shiftin(sc, 0x4, 3); 1176 fxp_eeprom_shiftin(sc, 0, sc->eeprom_size); 1177 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 1178 DELAY(1); 1179 } 1180 1181 /* 1182 * From NetBSD: 1183 * 1184 * Figure out EEPROM size. 1185 * 1186 * 559's can have either 64-word or 256-word EEPROMs, the 558 1187 * datasheet only talks about 64-word EEPROMs, and the 557 datasheet 1188 * talks about the existance of 16 to 256 word EEPROMs. 1189 * 1190 * The only known sizes are 64 and 256, where the 256 version is used 1191 * by CardBus cards to store CIS information. 1192 * 1193 * The address is shifted in msb-to-lsb, and after the last 1194 * address-bit the EEPROM is supposed to output a `dummy zero' bit, 1195 * after which follows the actual data. We try to detect this zero, by 1196 * probing the data-out bit in the EEPROM control register just after 1197 * having shifted in a bit. If the bit is zero, we assume we've 1198 * shifted enough address bits. The data-out should be tri-state, 1199 * before this, which should translate to a logical one. 1200 */ 1201 static void 1202 fxp_autosize_eeprom(struct fxp_softc *sc) 1203 { 1204 1205 /* guess maximum size of 256 words */ 1206 sc->eeprom_size = 8; 1207 1208 /* autosize */ 1209 (void) fxp_eeprom_getword(sc, 0, 1); 1210 } 1211 1212 static void 1213 fxp_read_eeprom(struct fxp_softc *sc, u_short *data, int offset, int words) 1214 { 1215 int i; 1216 1217 for (i = 0; i < words; i++) 1218 data[i] = fxp_eeprom_getword(sc, offset + i, 0); 1219 } 1220 1221 static void 1222 fxp_write_eeprom(struct fxp_softc *sc, u_short *data, int offset, int words) 1223 { 1224 int i; 1225 1226 for (i = 0; i < words; i++) 1227 fxp_eeprom_putword(sc, offset + i, data[i]); 1228 } 1229 1230 static void 1231 fxp_dma_map_txbuf(void *arg, bus_dma_segment_t *segs, int nseg, 1232 bus_size_t mapsize, int error) 1233 { 1234 struct fxp_softc *sc; 1235 struct fxp_cb_tx *txp; 1236 int i; 1237 1238 if (error) 1239 return; 1240 1241 KASSERT(nseg <= FXP_NTXSEG, ("too many DMA segments")); 1242 1243 sc = arg; 1244 txp = sc->fxp_desc.tx_last->tx_next->tx_cb; 1245 for (i = 0; i < nseg; i++) { 1246 KASSERT(segs[i].ds_len <= MCLBYTES, ("segment size too large")); 1247 /* 1248 * If this is an 82550/82551, then we're using extended 1249 * TxCBs _and_ we're using checksum offload. This means 1250 * that the TxCB is really an IPCB. One major difference 1251 * between the two is that with plain extended TxCBs, 1252 * the bottom half of the TxCB contains two entries from 1253 * the TBD array, whereas IPCBs contain just one entry: 1254 * one entry (8 bytes) has been sacrificed for the TCP/IP 1255 * checksum offload control bits. So to make things work 1256 * right, we have to start filling in the TBD array 1257 * starting from a different place depending on whether 1258 * the chip is an 82550/82551 or not. 1259 */ 1260 if (sc->flags & FXP_FLAG_EXT_RFA) { 1261 txp->tbd[i + 1].tb_addr = htole32(segs[i].ds_addr); 1262 txp->tbd[i + 1].tb_size = htole32(segs[i].ds_len); 1263 } else { 1264 txp->tbd[i].tb_addr = htole32(segs[i].ds_addr); 1265 txp->tbd[i].tb_size = htole32(segs[i].ds_len); 1266 } 1267 } 1268 txp->tbd_number = nseg; 1269 } 1270 1271 /* 1272 * Grab the softc lock and call the real fxp_start_body() routine 1273 */ 1274 static void 1275 fxp_start(struct ifnet *ifp) 1276 { 1277 struct fxp_softc *sc = ifp->if_softc; 1278 1279 FXP_LOCK(sc); 1280 fxp_start_body(ifp); 1281 FXP_UNLOCK(sc); 1282 } 1283 1284 /* 1285 * Start packet transmission on the interface. 1286 * This routine must be called with the softc lock held, and is an 1287 * internal entry point only. 1288 */ 1289 static void 1290 fxp_start_body(struct ifnet *ifp) 1291 { 1292 struct fxp_softc *sc = ifp->if_softc; 1293 struct fxp_tx *txp; 1294 struct mbuf *mb_head; 1295 int error; 1296 1297 mtx_assert(&sc->sc_mtx, MA_OWNED); 1298 /* 1299 * See if we need to suspend xmit until the multicast filter 1300 * has been reprogrammed (which can only be done at the head 1301 * of the command chain). 1302 */ 1303 if (sc->need_mcsetup) { 1304 return; 1305 } 1306 1307 txp = NULL; 1308 1309 /* 1310 * We're finished if there is nothing more to add to the list or if 1311 * we're all filled up with buffers to transmit. 1312 * NOTE: One TxCB is reserved to guarantee that fxp_mc_setup() can add 1313 * a NOP command when needed. 1314 */ 1315 while (ifp->if_snd.ifq_head != NULL && sc->tx_queued < FXP_NTXCB - 1) { 1316 1317 /* 1318 * Grab a packet to transmit. 1319 */ 1320 IF_DEQUEUE(&ifp->if_snd, mb_head); 1321 1322 /* 1323 * Get pointer to next available tx desc. 1324 */ 1325 txp = sc->fxp_desc.tx_last->tx_next; 1326 1327 /* 1328 * A note in Appendix B of the Intel 8255x 10/100 Mbps 1329 * Ethernet Controller Family Open Source Software 1330 * Developer Manual says: 1331 * Using software parsing is only allowed with legal 1332 * TCP/IP or UDP/IP packets. 1333 * ... 1334 * For all other datagrams, hardware parsing must 1335 * be used. 1336 * Software parsing appears to truncate ICMP and 1337 * fragmented UDP packets that contain one to three 1338 * bytes in the second (and final) mbuf of the packet. 1339 */ 1340 if (sc->flags & FXP_FLAG_EXT_RFA) 1341 txp->tx_cb->ipcb_ip_activation_high = 1342 FXP_IPCB_HARDWAREPARSING_ENABLE; 1343 1344 /* 1345 * Deal with TCP/IP checksum offload. Note that 1346 * in order for TCP checksum offload to work, 1347 * the pseudo header checksum must have already 1348 * been computed and stored in the checksum field 1349 * in the TCP header. The stack should have 1350 * already done this for us. 1351 */ 1352 1353 if (mb_head->m_pkthdr.csum_flags) { 1354 if (mb_head->m_pkthdr.csum_flags & CSUM_DELAY_DATA) { 1355 txp->tx_cb->ipcb_ip_schedule = 1356 FXP_IPCB_TCPUDP_CHECKSUM_ENABLE; 1357 if (mb_head->m_pkthdr.csum_flags & CSUM_TCP) 1358 txp->tx_cb->ipcb_ip_schedule |= 1359 FXP_IPCB_TCP_PACKET; 1360 } 1361 #ifdef FXP_IP_CSUM_WAR 1362 /* 1363 * XXX The 82550 chip appears to have trouble 1364 * dealing with IP header checksums in very small 1365 * datagrams, namely fragments from 1 to 3 bytes 1366 * in size. For example, say you want to transmit 1367 * a UDP packet of 1473 bytes. The packet will be 1368 * fragmented over two IP datagrams, the latter 1369 * containing only one byte of data. The 82550 will 1370 * botch the header checksum on the 1-byte fragment. 1371 * As long as the datagram contains 4 or more bytes 1372 * of data, you're ok. 1373 * 1374 * The following code attempts to work around this 1375 * problem: if the datagram is less than 38 bytes 1376 * in size (14 bytes ether header, 20 bytes IP header, 1377 * plus 4 bytes of data), we punt and compute the IP 1378 * header checksum by hand. This workaround doesn't 1379 * work very well, however, since it can be fooled 1380 * by things like VLAN tags and IP options that make 1381 * the header sizes/offsets vary. 1382 */ 1383 1384 if (mb_head->m_pkthdr.csum_flags & CSUM_IP) { 1385 if (mb_head->m_pkthdr.len < 38) { 1386 struct ip *ip; 1387 mb_head->m_data += ETHER_HDR_LEN; 1388 ip = mtod(mb_head, struct ip *); 1389 ip->ip_sum = in_cksum(mb_head, 1390 ip->ip_hl << 2); 1391 mb_head->m_data -= ETHER_HDR_LEN; 1392 } else { 1393 txp->tx_cb->ipcb_ip_activation_high = 1394 FXP_IPCB_HARDWAREPARSING_ENABLE; 1395 txp->tx_cb->ipcb_ip_schedule |= 1396 FXP_IPCB_IP_CHECKSUM_ENABLE; 1397 } 1398 } 1399 #endif 1400 } 1401 1402 /* 1403 * Go through each of the mbufs in the chain and initialize 1404 * the transmit buffer descriptors with the physical address 1405 * and size of the mbuf. 1406 */ 1407 error = bus_dmamap_load_mbuf(sc->fxp_mtag, txp->tx_map, 1408 mb_head, fxp_dma_map_txbuf, sc, 0); 1409 1410 if (error && error != EFBIG) { 1411 device_printf(sc->dev, "can't map mbuf (error %d)\n", 1412 error); 1413 m_freem(mb_head); 1414 break; 1415 } 1416 1417 if (error) { 1418 struct mbuf *mn; 1419 1420 /* 1421 * We ran out of segments. We have to recopy this 1422 * mbuf chain first. Bail out if we can't get the 1423 * new buffers. 1424 */ 1425 mn = m_defrag(mb_head, M_DONTWAIT); 1426 if (mn == NULL) { 1427 m_freem(mb_head); 1428 break; 1429 } else { 1430 mb_head = mn; 1431 } 1432 error = bus_dmamap_load_mbuf(sc->fxp_mtag, txp->tx_map, 1433 mb_head, fxp_dma_map_txbuf, sc, 0); 1434 if (error) { 1435 device_printf(sc->dev, 1436 "can't map mbuf (error %d)\n", error); 1437 m_freem(mb_head); 1438 break; 1439 } 1440 } 1441 1442 bus_dmamap_sync(sc->fxp_mtag, txp->tx_map, 1443 BUS_DMASYNC_PREWRITE); 1444 1445 txp->tx_mbuf = mb_head; 1446 txp->tx_cb->cb_status = 0; 1447 txp->tx_cb->byte_count = 0; 1448 if (sc->tx_queued != FXP_CXINT_THRESH - 1) { 1449 txp->tx_cb->cb_command = 1450 htole16(sc->tx_cmd | FXP_CB_COMMAND_SF | 1451 FXP_CB_COMMAND_S); 1452 } else { 1453 txp->tx_cb->cb_command = 1454 htole16(sc->tx_cmd | FXP_CB_COMMAND_SF | 1455 FXP_CB_COMMAND_S | FXP_CB_COMMAND_I); 1456 /* 1457 * Set a 5 second timer just in case we don't hear 1458 * from the card again. 1459 */ 1460 ifp->if_timer = 5; 1461 } 1462 txp->tx_cb->tx_threshold = tx_threshold; 1463 1464 /* 1465 * Advance the end of list forward. 1466 */ 1467 1468 #ifdef __alpha__ 1469 /* 1470 * On platforms which can't access memory in 16-bit 1471 * granularities, we must prevent the card from DMA'ing 1472 * up the status while we update the command field. 1473 * This could cause us to overwrite the completion status. 1474 * XXX This is probably bogus and we're _not_ looking 1475 * for atomicity here. 1476 */ 1477 atomic_clear_16(&sc->fxp_desc.tx_last->tx_cb->cb_command, 1478 htole16(FXP_CB_COMMAND_S)); 1479 #else 1480 sc->fxp_desc.tx_last->tx_cb->cb_command &= 1481 htole16(~FXP_CB_COMMAND_S); 1482 #endif /*__alpha__*/ 1483 sc->fxp_desc.tx_last = txp; 1484 1485 /* 1486 * Advance the beginning of the list forward if there are 1487 * no other packets queued (when nothing is queued, tx_first 1488 * sits on the last TxCB that was sent out). 1489 */ 1490 if (sc->tx_queued == 0) 1491 sc->fxp_desc.tx_first = txp; 1492 1493 sc->tx_queued++; 1494 1495 /* 1496 * Pass packet to bpf if there is a listener. 1497 */ 1498 BPF_MTAP(ifp, mb_head); 1499 } 1500 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE); 1501 1502 /* 1503 * We're finished. If we added to the list, issue a RESUME to get DMA 1504 * going again if suspended. 1505 */ 1506 if (txp != NULL) { 1507 fxp_scb_wait(sc); 1508 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_RESUME); 1509 } 1510 } 1511 1512 #ifdef DEVICE_POLLING 1513 static poll_handler_t fxp_poll; 1514 1515 static void 1516 fxp_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 1517 { 1518 struct fxp_softc *sc = ifp->if_softc; 1519 u_int8_t statack; 1520 1521 FXP_LOCK(sc); 1522 if (cmd == POLL_DEREGISTER) { /* final call, enable interrupts */ 1523 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, 0); 1524 FXP_UNLOCK(sc); 1525 return; 1526 } 1527 statack = FXP_SCB_STATACK_CXTNO | FXP_SCB_STATACK_CNA | 1528 FXP_SCB_STATACK_FR; 1529 if (cmd == POLL_AND_CHECK_STATUS) { 1530 u_int8_t tmp; 1531 1532 tmp = CSR_READ_1(sc, FXP_CSR_SCB_STATACK); 1533 if (tmp == 0xff || tmp == 0) { 1534 FXP_UNLOCK(sc); 1535 return; /* nothing to do */ 1536 } 1537 tmp &= ~statack; 1538 /* ack what we can */ 1539 if (tmp != 0) 1540 CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, tmp); 1541 statack |= tmp; 1542 } 1543 fxp_intr_body(sc, ifp, statack, count); 1544 FXP_UNLOCK(sc); 1545 } 1546 #endif /* DEVICE_POLLING */ 1547 1548 /* 1549 * Process interface interrupts. 1550 */ 1551 static void 1552 fxp_intr(void *xsc) 1553 { 1554 struct fxp_softc *sc = xsc; 1555 struct ifnet *ifp = &sc->sc_if; 1556 u_int8_t statack; 1557 1558 FXP_LOCK(sc); 1559 if (sc->suspended) { 1560 FXP_UNLOCK(sc); 1561 return; 1562 } 1563 1564 #ifdef DEVICE_POLLING 1565 if (ifp->if_flags & IFF_POLLING) { 1566 FXP_UNLOCK(sc); 1567 return; 1568 } 1569 if (ether_poll_register(fxp_poll, ifp)) { 1570 /* disable interrupts */ 1571 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE); 1572 FXP_UNLOCK(sc); 1573 fxp_poll(ifp, 0, 1); 1574 return; 1575 } 1576 #endif 1577 while ((statack = CSR_READ_1(sc, FXP_CSR_SCB_STATACK)) != 0) { 1578 /* 1579 * It should not be possible to have all bits set; the 1580 * FXP_SCB_INTR_SWI bit always returns 0 on a read. If 1581 * all bits are set, this may indicate that the card has 1582 * been physically ejected, so ignore it. 1583 */ 1584 if (statack == 0xff) { 1585 FXP_UNLOCK(sc); 1586 return; 1587 } 1588 1589 /* 1590 * First ACK all the interrupts in this pass. 1591 */ 1592 CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, statack); 1593 fxp_intr_body(sc, ifp, statack, -1); 1594 } 1595 FXP_UNLOCK(sc); 1596 } 1597 1598 static void 1599 fxp_txeof(struct fxp_softc *sc) 1600 { 1601 struct fxp_tx *txp; 1602 1603 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREREAD); 1604 for (txp = sc->fxp_desc.tx_first; sc->tx_queued && 1605 (le16toh(txp->tx_cb->cb_status) & FXP_CB_STATUS_C) != 0; 1606 txp = txp->tx_next) { 1607 if (txp->tx_mbuf != NULL) { 1608 bus_dmamap_sync(sc->fxp_mtag, txp->tx_map, 1609 BUS_DMASYNC_POSTWRITE); 1610 bus_dmamap_unload(sc->fxp_mtag, txp->tx_map); 1611 m_freem(txp->tx_mbuf); 1612 txp->tx_mbuf = NULL; 1613 /* clear this to reset csum offload bits */ 1614 txp->tx_cb->tbd[0].tb_addr = 0; 1615 } 1616 sc->tx_queued--; 1617 } 1618 sc->fxp_desc.tx_first = txp; 1619 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE); 1620 } 1621 1622 static void 1623 fxp_intr_body(struct fxp_softc *sc, struct ifnet *ifp, u_int8_t statack, 1624 int count) 1625 { 1626 struct mbuf *m; 1627 struct fxp_rx *rxp; 1628 struct fxp_rfa *rfa; 1629 int rnr = (statack & FXP_SCB_STATACK_RNR) ? 1 : 0; 1630 1631 mtx_assert(&sc->sc_mtx, MA_OWNED); 1632 if (rnr) 1633 fxp_rnr++; 1634 #ifdef DEVICE_POLLING 1635 /* Pick up a deferred RNR condition if `count' ran out last time. */ 1636 if (sc->flags & FXP_FLAG_DEFERRED_RNR) { 1637 sc->flags &= ~FXP_FLAG_DEFERRED_RNR; 1638 rnr = 1; 1639 } 1640 #endif 1641 1642 /* 1643 * Free any finished transmit mbuf chains. 1644 * 1645 * Handle the CNA event likt a CXTNO event. It used to 1646 * be that this event (control unit not ready) was not 1647 * encountered, but it is now with the SMPng modifications. 1648 * The exact sequence of events that occur when the interface 1649 * is brought up are different now, and if this event 1650 * goes unhandled, the configuration/rxfilter setup sequence 1651 * can stall for several seconds. The result is that no 1652 * packets go out onto the wire for about 5 to 10 seconds 1653 * after the interface is ifconfig'ed for the first time. 1654 */ 1655 if (statack & (FXP_SCB_STATACK_CXTNO | FXP_SCB_STATACK_CNA)) { 1656 fxp_txeof(sc); 1657 1658 ifp->if_timer = 0; 1659 if (sc->tx_queued == 0) { 1660 if (sc->need_mcsetup) 1661 fxp_mc_setup(sc); 1662 } 1663 /* 1664 * Try to start more packets transmitting. 1665 */ 1666 if (ifp->if_snd.ifq_head != NULL) 1667 fxp_start_body(ifp); 1668 } 1669 1670 /* 1671 * Just return if nothing happened on the receive side. 1672 */ 1673 if (!rnr && (statack & FXP_SCB_STATACK_FR) == 0) 1674 return; 1675 1676 /* 1677 * Process receiver interrupts. If a no-resource (RNR) 1678 * condition exists, get whatever packets we can and 1679 * re-start the receiver. 1680 * 1681 * When using polling, we do not process the list to completion, 1682 * so when we get an RNR interrupt we must defer the restart 1683 * until we hit the last buffer with the C bit set. 1684 * If we run out of cycles and rfa_headm has the C bit set, 1685 * record the pending RNR in the FXP_FLAG_DEFERRED_RNR flag so 1686 * that the info will be used in the subsequent polling cycle. 1687 */ 1688 for (;;) { 1689 rxp = sc->fxp_desc.rx_head; 1690 m = rxp->rx_mbuf; 1691 rfa = (struct fxp_rfa *)(m->m_ext.ext_buf + 1692 RFA_ALIGNMENT_FUDGE); 1693 bus_dmamap_sync(sc->fxp_mtag, rxp->rx_map, 1694 BUS_DMASYNC_POSTREAD); 1695 1696 #ifdef DEVICE_POLLING /* loop at most count times if count >=0 */ 1697 if (count >= 0 && count-- == 0) { 1698 if (rnr) { 1699 /* Defer RNR processing until the next time. */ 1700 sc->flags |= FXP_FLAG_DEFERRED_RNR; 1701 rnr = 0; 1702 } 1703 break; 1704 } 1705 #endif /* DEVICE_POLLING */ 1706 1707 if ((le16toh(rfa->rfa_status) & FXP_RFA_STATUS_C) == 0) 1708 break; 1709 1710 /* 1711 * Advance head forward. 1712 */ 1713 sc->fxp_desc.rx_head = rxp->rx_next; 1714 1715 /* 1716 * Add a new buffer to the receive chain. 1717 * If this fails, the old buffer is recycled 1718 * instead. 1719 */ 1720 if (fxp_add_rfabuf(sc, rxp) == 0) { 1721 int total_len; 1722 1723 /* 1724 * Fetch packet length (the top 2 bits of 1725 * actual_size are flags set by the controller 1726 * upon completion), and drop the packet in case 1727 * of bogus length or CRC errors. 1728 */ 1729 total_len = le16toh(rfa->actual_size) & 0x3fff; 1730 if (total_len < sizeof(struct ether_header) || 1731 total_len > MCLBYTES - RFA_ALIGNMENT_FUDGE - 1732 sc->rfa_size || 1733 le16toh(rfa->rfa_status) & FXP_RFA_STATUS_CRC) { 1734 m_freem(m); 1735 continue; 1736 } 1737 1738 /* Do IP checksum checking. */ 1739 if (le16toh(rfa->rfa_status) & FXP_RFA_STATUS_PARSE) { 1740 if (rfa->rfax_csum_sts & 1741 FXP_RFDX_CS_IP_CSUM_BIT_VALID) 1742 m->m_pkthdr.csum_flags |= 1743 CSUM_IP_CHECKED; 1744 if (rfa->rfax_csum_sts & 1745 FXP_RFDX_CS_IP_CSUM_VALID) 1746 m->m_pkthdr.csum_flags |= 1747 CSUM_IP_VALID; 1748 if ((rfa->rfax_csum_sts & 1749 FXP_RFDX_CS_TCPUDP_CSUM_BIT_VALID) && 1750 (rfa->rfax_csum_sts & 1751 FXP_RFDX_CS_TCPUDP_CSUM_VALID)) { 1752 m->m_pkthdr.csum_flags |= 1753 CSUM_DATA_VALID|CSUM_PSEUDO_HDR; 1754 m->m_pkthdr.csum_data = 0xffff; 1755 } 1756 } 1757 1758 m->m_pkthdr.len = m->m_len = total_len; 1759 m->m_pkthdr.rcvif = ifp; 1760 1761 /* 1762 * Drop locks before calling if_input() since it 1763 * may re-enter fxp_start() in the netisr case. 1764 * This would result in a lock reversal. Better 1765 * performance might be obtained by chaining all 1766 * packets received, dropping the lock, and then 1767 * calling if_input() on each one. 1768 */ 1769 FXP_UNLOCK(sc); 1770 (*ifp->if_input)(ifp, m); 1771 FXP_LOCK(sc); 1772 } 1773 } 1774 if (rnr) { 1775 fxp_scb_wait(sc); 1776 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 1777 sc->fxp_desc.rx_head->rx_addr); 1778 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_START); 1779 } 1780 } 1781 1782 /* 1783 * Update packet in/out/collision statistics. The i82557 doesn't 1784 * allow you to access these counters without doing a fairly 1785 * expensive DMA to get _all_ of the statistics it maintains, so 1786 * we do this operation here only once per second. The statistics 1787 * counters in the kernel are updated from the previous dump-stats 1788 * DMA and then a new dump-stats DMA is started. The on-chip 1789 * counters are zeroed when the DMA completes. If we can't start 1790 * the DMA immediately, we don't wait - we just prepare to read 1791 * them again next time. 1792 */ 1793 static void 1794 fxp_tick(void *xsc) 1795 { 1796 struct fxp_softc *sc = xsc; 1797 struct ifnet *ifp = &sc->sc_if; 1798 struct fxp_stats *sp = sc->fxp_stats; 1799 int s; 1800 1801 FXP_LOCK(sc); 1802 s = splimp(); 1803 bus_dmamap_sync(sc->fxp_stag, sc->fxp_smap, BUS_DMASYNC_POSTREAD); 1804 ifp->if_opackets += le32toh(sp->tx_good); 1805 ifp->if_collisions += le32toh(sp->tx_total_collisions); 1806 if (sp->rx_good) { 1807 ifp->if_ipackets += le32toh(sp->rx_good); 1808 sc->rx_idle_secs = 0; 1809 } else { 1810 /* 1811 * Receiver's been idle for another second. 1812 */ 1813 sc->rx_idle_secs++; 1814 } 1815 ifp->if_ierrors += 1816 le32toh(sp->rx_crc_errors) + 1817 le32toh(sp->rx_alignment_errors) + 1818 le32toh(sp->rx_rnr_errors) + 1819 le32toh(sp->rx_overrun_errors); 1820 /* 1821 * If any transmit underruns occured, bump up the transmit 1822 * threshold by another 512 bytes (64 * 8). 1823 */ 1824 if (sp->tx_underruns) { 1825 ifp->if_oerrors += le32toh(sp->tx_underruns); 1826 if (tx_threshold < 192) 1827 tx_threshold += 64; 1828 } 1829 1830 /* 1831 * Release any xmit buffers that have completed DMA. This isn't 1832 * strictly necessary to do here, but it's advantagous for mbufs 1833 * with external storage to be released in a timely manner rather 1834 * than being defered for a potentially long time. This limits 1835 * the delay to a maximum of one second. 1836 */ 1837 fxp_txeof(sc); 1838 1839 /* 1840 * If we haven't received any packets in FXP_MAC_RX_IDLE seconds, 1841 * then assume the receiver has locked up and attempt to clear 1842 * the condition by reprogramming the multicast filter. This is 1843 * a work-around for a bug in the 82557 where the receiver locks 1844 * up if it gets certain types of garbage in the syncronization 1845 * bits prior to the packet header. This bug is supposed to only 1846 * occur in 10Mbps mode, but has been seen to occur in 100Mbps 1847 * mode as well (perhaps due to a 10/100 speed transition). 1848 */ 1849 if (sc->rx_idle_secs > FXP_MAX_RX_IDLE) { 1850 sc->rx_idle_secs = 0; 1851 fxp_mc_setup(sc); 1852 } 1853 /* 1854 * If there is no pending command, start another stats 1855 * dump. Otherwise punt for now. 1856 */ 1857 if (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) == 0) { 1858 /* 1859 * Start another stats dump. 1860 */ 1861 bus_dmamap_sync(sc->fxp_stag, sc->fxp_smap, 1862 BUS_DMASYNC_PREREAD); 1863 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_DUMPRESET); 1864 } else { 1865 /* 1866 * A previous command is still waiting to be accepted. 1867 * Just zero our copy of the stats and wait for the 1868 * next timer event to update them. 1869 */ 1870 sp->tx_good = 0; 1871 sp->tx_underruns = 0; 1872 sp->tx_total_collisions = 0; 1873 1874 sp->rx_good = 0; 1875 sp->rx_crc_errors = 0; 1876 sp->rx_alignment_errors = 0; 1877 sp->rx_rnr_errors = 0; 1878 sp->rx_overrun_errors = 0; 1879 } 1880 if (sc->miibus != NULL) 1881 mii_tick(device_get_softc(sc->miibus)); 1882 1883 /* 1884 * Schedule another timeout one second from now. 1885 */ 1886 callout_reset(&sc->stat_ch, hz, fxp_tick, sc); 1887 FXP_UNLOCK(sc); 1888 splx(s); 1889 } 1890 1891 /* 1892 * Stop the interface. Cancels the statistics updater and resets 1893 * the interface. 1894 */ 1895 static void 1896 fxp_stop(struct fxp_softc *sc) 1897 { 1898 struct ifnet *ifp = &sc->sc_if; 1899 struct fxp_tx *txp; 1900 int i; 1901 1902 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1903 ifp->if_timer = 0; 1904 1905 #ifdef DEVICE_POLLING 1906 ether_poll_deregister(ifp); 1907 #endif 1908 /* 1909 * Cancel stats updater. 1910 */ 1911 callout_stop(&sc->stat_ch); 1912 1913 /* 1914 * Issue software reset, which also unloads the microcode. 1915 */ 1916 sc->flags &= ~FXP_FLAG_UCODE; 1917 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SOFTWARE_RESET); 1918 DELAY(50); 1919 1920 /* 1921 * Release any xmit buffers. 1922 */ 1923 txp = sc->fxp_desc.tx_list; 1924 if (txp != NULL) { 1925 for (i = 0; i < FXP_NTXCB; i++) { 1926 if (txp[i].tx_mbuf != NULL) { 1927 bus_dmamap_sync(sc->fxp_mtag, txp[i].tx_map, 1928 BUS_DMASYNC_POSTWRITE); 1929 bus_dmamap_unload(sc->fxp_mtag, txp[i].tx_map); 1930 m_freem(txp[i].tx_mbuf); 1931 txp[i].tx_mbuf = NULL; 1932 /* clear this to reset csum offload bits */ 1933 txp[i].tx_cb->tbd[0].tb_addr = 0; 1934 } 1935 } 1936 } 1937 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE); 1938 sc->tx_queued = 0; 1939 } 1940 1941 /* 1942 * Watchdog/transmission transmit timeout handler. Called when a 1943 * transmission is started on the interface, but no interrupt is 1944 * received before the timeout. This usually indicates that the 1945 * card has wedged for some reason. 1946 */ 1947 static void 1948 fxp_watchdog(struct ifnet *ifp) 1949 { 1950 struct fxp_softc *sc = ifp->if_softc; 1951 1952 FXP_LOCK(sc); 1953 device_printf(sc->dev, "device timeout\n"); 1954 ifp->if_oerrors++; 1955 1956 fxp_init_body(sc); 1957 FXP_UNLOCK(sc); 1958 } 1959 1960 /* 1961 * Acquire locks and then call the real initialization function. This 1962 * is necessary because ether_ioctl() calls if_init() and this would 1963 * result in mutex recursion if the mutex was held. 1964 */ 1965 static void 1966 fxp_init(void *xsc) 1967 { 1968 struct fxp_softc *sc = xsc; 1969 1970 FXP_LOCK(sc); 1971 fxp_init_body(sc); 1972 FXP_UNLOCK(sc); 1973 } 1974 1975 /* 1976 * Perform device initialization. This routine must be called with the 1977 * softc lock held. 1978 */ 1979 static void 1980 fxp_init_body(struct fxp_softc *sc) 1981 { 1982 struct ifnet *ifp = &sc->sc_if; 1983 struct fxp_cb_config *cbp; 1984 struct fxp_cb_ias *cb_ias; 1985 struct fxp_cb_tx *tcbp; 1986 struct fxp_tx *txp; 1987 struct fxp_cb_mcs *mcsp; 1988 int i, prm, s; 1989 1990 mtx_assert(&sc->sc_mtx, MA_OWNED); 1991 s = splimp(); 1992 /* 1993 * Cancel any pending I/O 1994 */ 1995 fxp_stop(sc); 1996 1997 prm = (ifp->if_flags & IFF_PROMISC) ? 1 : 0; 1998 1999 /* 2000 * Initialize base of CBL and RFA memory. Loading with zero 2001 * sets it up for regular linear addressing. 2002 */ 2003 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 0); 2004 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_BASE); 2005 2006 fxp_scb_wait(sc); 2007 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_BASE); 2008 2009 /* 2010 * Initialize base of dump-stats buffer. 2011 */ 2012 fxp_scb_wait(sc); 2013 bus_dmamap_sync(sc->fxp_stag, sc->fxp_smap, BUS_DMASYNC_PREREAD); 2014 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->stats_addr); 2015 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_DUMP_ADR); 2016 2017 /* 2018 * Attempt to load microcode if requested. 2019 */ 2020 if (ifp->if_flags & IFF_LINK0 && (sc->flags & FXP_FLAG_UCODE) == 0) 2021 fxp_load_ucode(sc); 2022 2023 /* 2024 * Initialize the multicast address list. 2025 */ 2026 if (fxp_mc_addrs(sc)) { 2027 mcsp = sc->mcsp; 2028 mcsp->cb_status = 0; 2029 mcsp->cb_command = 2030 htole16(FXP_CB_COMMAND_MCAS | FXP_CB_COMMAND_EL); 2031 mcsp->link_addr = 0xffffffff; 2032 /* 2033 * Start the multicast setup command. 2034 */ 2035 fxp_scb_wait(sc); 2036 bus_dmamap_sync(sc->mcs_tag, sc->mcs_map, BUS_DMASYNC_PREWRITE); 2037 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->mcs_addr); 2038 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2039 /* ...and wait for it to complete. */ 2040 fxp_dma_wait(sc, &mcsp->cb_status, sc->mcs_tag, sc->mcs_map); 2041 bus_dmamap_sync(sc->mcs_tag, sc->mcs_map, 2042 BUS_DMASYNC_POSTWRITE); 2043 } 2044 2045 /* 2046 * We temporarily use memory that contains the TxCB list to 2047 * construct the config CB. The TxCB list memory is rebuilt 2048 * later. 2049 */ 2050 cbp = (struct fxp_cb_config *)sc->fxp_desc.cbl_list; 2051 2052 /* 2053 * This bcopy is kind of disgusting, but there are a bunch of must be 2054 * zero and must be one bits in this structure and this is the easiest 2055 * way to initialize them all to proper values. 2056 */ 2057 bcopy(fxp_cb_config_template, cbp, sizeof(fxp_cb_config_template)); 2058 2059 cbp->cb_status = 0; 2060 cbp->cb_command = htole16(FXP_CB_COMMAND_CONFIG | 2061 FXP_CB_COMMAND_EL); 2062 cbp->link_addr = 0xffffffff; /* (no) next command */ 2063 cbp->byte_count = sc->flags & FXP_FLAG_EXT_RFA ? 32 : 22; 2064 cbp->rx_fifo_limit = 8; /* rx fifo threshold (32 bytes) */ 2065 cbp->tx_fifo_limit = 0; /* tx fifo threshold (0 bytes) */ 2066 cbp->adaptive_ifs = 0; /* (no) adaptive interframe spacing */ 2067 cbp->mwi_enable = sc->flags & FXP_FLAG_MWI_ENABLE ? 1 : 0; 2068 cbp->type_enable = 0; /* actually reserved */ 2069 cbp->read_align_en = sc->flags & FXP_FLAG_READ_ALIGN ? 1 : 0; 2070 cbp->end_wr_on_cl = sc->flags & FXP_FLAG_WRITE_ALIGN ? 1 : 0; 2071 cbp->rx_dma_bytecount = 0; /* (no) rx DMA max */ 2072 cbp->tx_dma_bytecount = 0; /* (no) tx DMA max */ 2073 cbp->dma_mbce = 0; /* (disable) dma max counters */ 2074 cbp->late_scb = 0; /* (don't) defer SCB update */ 2075 cbp->direct_dma_dis = 1; /* disable direct rcv dma mode */ 2076 cbp->tno_int_or_tco_en =0; /* (disable) tx not okay interrupt */ 2077 cbp->ci_int = 1; /* interrupt on CU idle */ 2078 cbp->ext_txcb_dis = sc->flags & FXP_FLAG_EXT_TXCB ? 0 : 1; 2079 cbp->ext_stats_dis = 1; /* disable extended counters */ 2080 cbp->keep_overrun_rx = 0; /* don't pass overrun frames to host */ 2081 cbp->save_bf = sc->revision == FXP_REV_82557 ? 1 : prm; 2082 cbp->disc_short_rx = !prm; /* discard short packets */ 2083 cbp->underrun_retry = 1; /* retry mode (once) on DMA underrun */ 2084 cbp->two_frames = 0; /* do not limit FIFO to 2 frames */ 2085 cbp->dyn_tbd = 0; /* (no) dynamic TBD mode */ 2086 cbp->ext_rfa = sc->flags & FXP_FLAG_EXT_RFA ? 1 : 0; 2087 cbp->mediatype = sc->flags & FXP_FLAG_SERIAL_MEDIA ? 0 : 1; 2088 cbp->csma_dis = 0; /* (don't) disable link */ 2089 cbp->tcp_udp_cksum = 0; /* (don't) enable checksum */ 2090 cbp->vlan_tco = 0; /* (don't) enable vlan wakeup */ 2091 cbp->link_wake_en = 0; /* (don't) assert PME# on link change */ 2092 cbp->arp_wake_en = 0; /* (don't) assert PME# on arp */ 2093 cbp->mc_wake_en = 0; /* (don't) enable PME# on mcmatch */ 2094 cbp->nsai = 1; /* (don't) disable source addr insert */ 2095 cbp->preamble_length = 2; /* (7 byte) preamble */ 2096 cbp->loopback = 0; /* (don't) loopback */ 2097 cbp->linear_priority = 0; /* (normal CSMA/CD operation) */ 2098 cbp->linear_pri_mode = 0; /* (wait after xmit only) */ 2099 cbp->interfrm_spacing = 6; /* (96 bits of) interframe spacing */ 2100 cbp->promiscuous = prm; /* promiscuous mode */ 2101 cbp->bcast_disable = 0; /* (don't) disable broadcasts */ 2102 cbp->wait_after_win = 0; /* (don't) enable modified backoff alg*/ 2103 cbp->ignore_ul = 0; /* consider U/L bit in IA matching */ 2104 cbp->crc16_en = 0; /* (don't) enable crc-16 algorithm */ 2105 cbp->crscdt = sc->flags & FXP_FLAG_SERIAL_MEDIA ? 1 : 0; 2106 2107 cbp->stripping = !prm; /* truncate rx packet to byte count */ 2108 cbp->padding = 1; /* (do) pad short tx packets */ 2109 cbp->rcv_crc_xfer = 0; /* (don't) xfer CRC to host */ 2110 cbp->long_rx_en = sc->flags & FXP_FLAG_LONG_PKT_EN ? 1 : 0; 2111 cbp->ia_wake_en = 0; /* (don't) wake up on address match */ 2112 cbp->magic_pkt_dis = 0; /* (don't) disable magic packet */ 2113 /* must set wake_en in PMCSR also */ 2114 cbp->force_fdx = 0; /* (don't) force full duplex */ 2115 cbp->fdx_pin_en = 1; /* (enable) FDX# pin */ 2116 cbp->multi_ia = 0; /* (don't) accept multiple IAs */ 2117 cbp->mc_all = sc->flags & FXP_FLAG_ALL_MCAST ? 1 : 0; 2118 cbp->gamla_rx = sc->flags & FXP_FLAG_EXT_RFA ? 1 : 0; 2119 2120 if (fxp_noflow || sc->revision == FXP_REV_82557) { 2121 /* 2122 * The 82557 has no hardware flow control, the values 2123 * below are the defaults for the chip. 2124 */ 2125 cbp->fc_delay_lsb = 0; 2126 cbp->fc_delay_msb = 0x40; 2127 cbp->pri_fc_thresh = 3; 2128 cbp->tx_fc_dis = 0; 2129 cbp->rx_fc_restop = 0; 2130 cbp->rx_fc_restart = 0; 2131 cbp->fc_filter = 0; 2132 cbp->pri_fc_loc = 1; 2133 } else { 2134 cbp->fc_delay_lsb = 0x1f; 2135 cbp->fc_delay_msb = 0x01; 2136 cbp->pri_fc_thresh = 3; 2137 cbp->tx_fc_dis = 0; /* enable transmit FC */ 2138 cbp->rx_fc_restop = 1; /* enable FC restop frames */ 2139 cbp->rx_fc_restart = 1; /* enable FC restart frames */ 2140 cbp->fc_filter = !prm; /* drop FC frames to host */ 2141 cbp->pri_fc_loc = 1; /* FC pri location (byte31) */ 2142 } 2143 2144 /* 2145 * Start the config command/DMA. 2146 */ 2147 fxp_scb_wait(sc); 2148 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE); 2149 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->fxp_desc.cbl_addr); 2150 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2151 /* ...and wait for it to complete. */ 2152 fxp_dma_wait(sc, &cbp->cb_status, sc->cbl_tag, sc->cbl_map); 2153 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_POSTWRITE); 2154 2155 /* 2156 * Now initialize the station address. Temporarily use the TxCB 2157 * memory area like we did above for the config CB. 2158 */ 2159 cb_ias = (struct fxp_cb_ias *)sc->fxp_desc.cbl_list; 2160 cb_ias->cb_status = 0; 2161 cb_ias->cb_command = htole16(FXP_CB_COMMAND_IAS | FXP_CB_COMMAND_EL); 2162 cb_ias->link_addr = 0xffffffff; 2163 bcopy(sc->arpcom.ac_enaddr, cb_ias->macaddr, 2164 sizeof(sc->arpcom.ac_enaddr)); 2165 2166 /* 2167 * Start the IAS (Individual Address Setup) command/DMA. 2168 */ 2169 fxp_scb_wait(sc); 2170 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE); 2171 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2172 /* ...and wait for it to complete. */ 2173 fxp_dma_wait(sc, &cb_ias->cb_status, sc->cbl_tag, sc->cbl_map); 2174 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_POSTWRITE); 2175 2176 /* 2177 * Initialize transmit control block (TxCB) list. 2178 */ 2179 txp = sc->fxp_desc.tx_list; 2180 tcbp = sc->fxp_desc.cbl_list; 2181 bzero(tcbp, FXP_TXCB_SZ); 2182 for (i = 0; i < FXP_NTXCB; i++) { 2183 txp[i].tx_cb = tcbp + i; 2184 txp[i].tx_mbuf = NULL; 2185 tcbp[i].cb_status = htole16(FXP_CB_STATUS_C | FXP_CB_STATUS_OK); 2186 tcbp[i].cb_command = htole16(FXP_CB_COMMAND_NOP); 2187 tcbp[i].link_addr = htole32(sc->fxp_desc.cbl_addr + 2188 (((i + 1) & FXP_TXCB_MASK) * sizeof(struct fxp_cb_tx))); 2189 if (sc->flags & FXP_FLAG_EXT_TXCB) 2190 tcbp[i].tbd_array_addr = 2191 htole32(FXP_TXCB_DMA_ADDR(sc, &tcbp[i].tbd[2])); 2192 else 2193 tcbp[i].tbd_array_addr = 2194 htole32(FXP_TXCB_DMA_ADDR(sc, &tcbp[i].tbd[0])); 2195 txp[i].tx_next = &txp[(i + 1) & FXP_TXCB_MASK]; 2196 } 2197 /* 2198 * Set the suspend flag on the first TxCB and start the control 2199 * unit. It will execute the NOP and then suspend. 2200 */ 2201 tcbp->cb_command = htole16(FXP_CB_COMMAND_NOP | FXP_CB_COMMAND_S); 2202 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE); 2203 sc->fxp_desc.tx_first = sc->fxp_desc.tx_last = txp; 2204 sc->tx_queued = 1; 2205 2206 fxp_scb_wait(sc); 2207 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2208 2209 /* 2210 * Initialize receiver buffer area - RFA. 2211 */ 2212 fxp_scb_wait(sc); 2213 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->fxp_desc.rx_head->rx_addr); 2214 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_START); 2215 2216 /* 2217 * Set current media. 2218 */ 2219 if (sc->miibus != NULL) 2220 mii_mediachg(device_get_softc(sc->miibus)); 2221 2222 ifp->if_flags |= IFF_RUNNING; 2223 ifp->if_flags &= ~IFF_OACTIVE; 2224 2225 /* 2226 * Enable interrupts. 2227 */ 2228 #ifdef DEVICE_POLLING 2229 /* 2230 * ... but only do that if we are not polling. And because (presumably) 2231 * the default is interrupts on, we need to disable them explicitly! 2232 */ 2233 if ( ifp->if_flags & IFF_POLLING ) 2234 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE); 2235 else 2236 #endif /* DEVICE_POLLING */ 2237 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, 0); 2238 2239 /* 2240 * Start stats updater. 2241 */ 2242 callout_reset(&sc->stat_ch, hz, fxp_tick, sc); 2243 splx(s); 2244 } 2245 2246 static int 2247 fxp_serial_ifmedia_upd(struct ifnet *ifp) 2248 { 2249 2250 return (0); 2251 } 2252 2253 static void 2254 fxp_serial_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 2255 { 2256 2257 ifmr->ifm_active = IFM_ETHER|IFM_MANUAL; 2258 } 2259 2260 /* 2261 * Change media according to request. 2262 */ 2263 static int 2264 fxp_ifmedia_upd(struct ifnet *ifp) 2265 { 2266 struct fxp_softc *sc = ifp->if_softc; 2267 struct mii_data *mii; 2268 2269 mii = device_get_softc(sc->miibus); 2270 mii_mediachg(mii); 2271 return (0); 2272 } 2273 2274 /* 2275 * Notify the world which media we're using. 2276 */ 2277 static void 2278 fxp_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 2279 { 2280 struct fxp_softc *sc = ifp->if_softc; 2281 struct mii_data *mii; 2282 2283 mii = device_get_softc(sc->miibus); 2284 mii_pollstat(mii); 2285 ifmr->ifm_active = mii->mii_media_active; 2286 ifmr->ifm_status = mii->mii_media_status; 2287 2288 if (ifmr->ifm_status & IFM_10_T && sc->flags & FXP_FLAG_CU_RESUME_BUG) 2289 sc->cu_resume_bug = 1; 2290 else 2291 sc->cu_resume_bug = 0; 2292 } 2293 2294 /* 2295 * Add a buffer to the end of the RFA buffer list. 2296 * Return 0 if successful, 1 for failure. A failure results in 2297 * adding the 'oldm' (if non-NULL) on to the end of the list - 2298 * tossing out its old contents and recycling it. 2299 * The RFA struct is stuck at the beginning of mbuf cluster and the 2300 * data pointer is fixed up to point just past it. 2301 */ 2302 static int 2303 fxp_add_rfabuf(struct fxp_softc *sc, struct fxp_rx *rxp) 2304 { 2305 struct mbuf *m; 2306 struct fxp_rfa *rfa, *p_rfa; 2307 struct fxp_rx *p_rx; 2308 bus_dmamap_t tmp_map; 2309 int error; 2310 2311 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 2312 if (m == NULL) 2313 return (ENOBUFS); 2314 2315 /* 2316 * Move the data pointer up so that the incoming data packet 2317 * will be 32-bit aligned. 2318 */ 2319 m->m_data += RFA_ALIGNMENT_FUDGE; 2320 2321 /* 2322 * Get a pointer to the base of the mbuf cluster and move 2323 * data start past it. 2324 */ 2325 rfa = mtod(m, struct fxp_rfa *); 2326 m->m_data += sc->rfa_size; 2327 rfa->size = htole16(MCLBYTES - sc->rfa_size - RFA_ALIGNMENT_FUDGE); 2328 2329 rfa->rfa_status = 0; 2330 rfa->rfa_control = htole16(FXP_RFA_CONTROL_EL); 2331 rfa->actual_size = 0; 2332 2333 /* 2334 * Initialize the rest of the RFA. Note that since the RFA 2335 * is misaligned, we cannot store values directly. We're thus 2336 * using the le32enc() function which handles endianness and 2337 * is also alignment-safe. 2338 */ 2339 le32enc(&rfa->link_addr, 0xffffffff); 2340 le32enc(&rfa->rbd_addr, 0xffffffff); 2341 2342 /* Map the RFA into DMA memory. */ 2343 error = bus_dmamap_load(sc->fxp_mtag, sc->spare_map, rfa, 2344 MCLBYTES - RFA_ALIGNMENT_FUDGE, fxp_dma_map_addr, 2345 &rxp->rx_addr, 0); 2346 if (error) { 2347 m_freem(m); 2348 return (error); 2349 } 2350 2351 bus_dmamap_unload(sc->fxp_mtag, rxp->rx_map); 2352 tmp_map = sc->spare_map; 2353 sc->spare_map = rxp->rx_map; 2354 rxp->rx_map = tmp_map; 2355 rxp->rx_mbuf = m; 2356 2357 bus_dmamap_sync(sc->fxp_mtag, rxp->rx_map, 2358 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2359 2360 /* 2361 * If there are other buffers already on the list, attach this 2362 * one to the end by fixing up the tail to point to this one. 2363 */ 2364 if (sc->fxp_desc.rx_head != NULL) { 2365 p_rx = sc->fxp_desc.rx_tail; 2366 p_rfa = (struct fxp_rfa *) 2367 (p_rx->rx_mbuf->m_ext.ext_buf + RFA_ALIGNMENT_FUDGE); 2368 p_rx->rx_next = rxp; 2369 le32enc(&p_rfa->link_addr, rxp->rx_addr); 2370 p_rfa->rfa_control = 0; 2371 bus_dmamap_sync(sc->fxp_mtag, p_rx->rx_map, 2372 BUS_DMASYNC_PREWRITE); 2373 } else { 2374 rxp->rx_next = NULL; 2375 sc->fxp_desc.rx_head = rxp; 2376 } 2377 sc->fxp_desc.rx_tail = rxp; 2378 return (0); 2379 } 2380 2381 static volatile int 2382 fxp_miibus_readreg(device_t dev, int phy, int reg) 2383 { 2384 struct fxp_softc *sc = device_get_softc(dev); 2385 int count = 10000; 2386 int value; 2387 2388 CSR_WRITE_4(sc, FXP_CSR_MDICONTROL, 2389 (FXP_MDI_READ << 26) | (reg << 16) | (phy << 21)); 2390 2391 while (((value = CSR_READ_4(sc, FXP_CSR_MDICONTROL)) & 0x10000000) == 0 2392 && count--) 2393 DELAY(10); 2394 2395 if (count <= 0) 2396 device_printf(dev, "fxp_miibus_readreg: timed out\n"); 2397 2398 return (value & 0xffff); 2399 } 2400 2401 static void 2402 fxp_miibus_writereg(device_t dev, int phy, int reg, int value) 2403 { 2404 struct fxp_softc *sc = device_get_softc(dev); 2405 int count = 10000; 2406 2407 CSR_WRITE_4(sc, FXP_CSR_MDICONTROL, 2408 (FXP_MDI_WRITE << 26) | (reg << 16) | (phy << 21) | 2409 (value & 0xffff)); 2410 2411 while ((CSR_READ_4(sc, FXP_CSR_MDICONTROL) & 0x10000000) == 0 && 2412 count--) 2413 DELAY(10); 2414 2415 if (count <= 0) 2416 device_printf(dev, "fxp_miibus_writereg: timed out\n"); 2417 } 2418 2419 static int 2420 fxp_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 2421 { 2422 struct fxp_softc *sc = ifp->if_softc; 2423 struct ifreq *ifr = (struct ifreq *)data; 2424 struct mii_data *mii; 2425 int s, error = 0; 2426 2427 /* 2428 * Detaching causes us to call ioctl with the mutex owned. Preclude 2429 * that by saying we're busy if the lock is already held. 2430 */ 2431 if (mtx_owned(&sc->sc_mtx)) 2432 return (EBUSY); 2433 2434 FXP_LOCK(sc); 2435 s = splimp(); 2436 2437 switch (command) { 2438 case SIOCSIFFLAGS: 2439 if (ifp->if_flags & IFF_ALLMULTI) 2440 sc->flags |= FXP_FLAG_ALL_MCAST; 2441 else 2442 sc->flags &= ~FXP_FLAG_ALL_MCAST; 2443 2444 /* 2445 * If interface is marked up and not running, then start it. 2446 * If it is marked down and running, stop it. 2447 * XXX If it's up then re-initialize it. This is so flags 2448 * such as IFF_PROMISC are handled. 2449 */ 2450 if (ifp->if_flags & IFF_UP) { 2451 fxp_init_body(sc); 2452 } else { 2453 if (ifp->if_flags & IFF_RUNNING) 2454 fxp_stop(sc); 2455 } 2456 break; 2457 2458 case SIOCADDMULTI: 2459 case SIOCDELMULTI: 2460 if (ifp->if_flags & IFF_ALLMULTI) 2461 sc->flags |= FXP_FLAG_ALL_MCAST; 2462 else 2463 sc->flags &= ~FXP_FLAG_ALL_MCAST; 2464 /* 2465 * Multicast list has changed; set the hardware filter 2466 * accordingly. 2467 */ 2468 if ((sc->flags & FXP_FLAG_ALL_MCAST) == 0) 2469 fxp_mc_setup(sc); 2470 /* 2471 * fxp_mc_setup() can set FXP_FLAG_ALL_MCAST, so check it 2472 * again rather than else {}. 2473 */ 2474 if (sc->flags & FXP_FLAG_ALL_MCAST) 2475 fxp_init_body(sc); 2476 error = 0; 2477 break; 2478 2479 case SIOCSIFMEDIA: 2480 case SIOCGIFMEDIA: 2481 if (sc->miibus != NULL) { 2482 mii = device_get_softc(sc->miibus); 2483 error = ifmedia_ioctl(ifp, ifr, 2484 &mii->mii_media, command); 2485 } else { 2486 error = ifmedia_ioctl(ifp, ifr, &sc->sc_media, command); 2487 } 2488 break; 2489 2490 default: 2491 /* 2492 * ether_ioctl() will eventually call fxp_start() which 2493 * will result in mutex recursion so drop it first. 2494 */ 2495 FXP_UNLOCK(sc); 2496 error = ether_ioctl(ifp, command, data); 2497 } 2498 if (mtx_owned(&sc->sc_mtx)) 2499 FXP_UNLOCK(sc); 2500 splx(s); 2501 return (error); 2502 } 2503 2504 /* 2505 * Fill in the multicast address list and return number of entries. 2506 */ 2507 static int 2508 fxp_mc_addrs(struct fxp_softc *sc) 2509 { 2510 struct fxp_cb_mcs *mcsp = sc->mcsp; 2511 struct ifnet *ifp = &sc->sc_if; 2512 struct ifmultiaddr *ifma; 2513 int nmcasts; 2514 2515 nmcasts = 0; 2516 if ((sc->flags & FXP_FLAG_ALL_MCAST) == 0) { 2517 #if __FreeBSD_version < 500000 2518 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 2519 #else 2520 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 2521 #endif 2522 if (ifma->ifma_addr->sa_family != AF_LINK) 2523 continue; 2524 if (nmcasts >= MAXMCADDR) { 2525 sc->flags |= FXP_FLAG_ALL_MCAST; 2526 nmcasts = 0; 2527 break; 2528 } 2529 bcopy(LLADDR((struct sockaddr_dl *)ifma->ifma_addr), 2530 &sc->mcsp->mc_addr[nmcasts][0], ETHER_ADDR_LEN); 2531 nmcasts++; 2532 } 2533 } 2534 mcsp->mc_cnt = htole16(nmcasts * ETHER_ADDR_LEN); 2535 return (nmcasts); 2536 } 2537 2538 /* 2539 * Program the multicast filter. 2540 * 2541 * We have an artificial restriction that the multicast setup command 2542 * must be the first command in the chain, so we take steps to ensure 2543 * this. By requiring this, it allows us to keep up the performance of 2544 * the pre-initialized command ring (esp. link pointers) by not actually 2545 * inserting the mcsetup command in the ring - i.e. its link pointer 2546 * points to the TxCB ring, but the mcsetup descriptor itself is not part 2547 * of it. We then can do 'CU_START' on the mcsetup descriptor and have it 2548 * lead into the regular TxCB ring when it completes. 2549 * 2550 * This function must be called at splimp. 2551 */ 2552 static void 2553 fxp_mc_setup(struct fxp_softc *sc) 2554 { 2555 struct fxp_cb_mcs *mcsp = sc->mcsp; 2556 struct ifnet *ifp = &sc->sc_if; 2557 struct fxp_tx *txp; 2558 int count; 2559 2560 /* 2561 * If there are queued commands, we must wait until they are all 2562 * completed. If we are already waiting, then add a NOP command 2563 * with interrupt option so that we're notified when all commands 2564 * have been completed - fxp_start() ensures that no additional 2565 * TX commands will be added when need_mcsetup is true. 2566 */ 2567 if (sc->tx_queued) { 2568 /* 2569 * need_mcsetup will be true if we are already waiting for the 2570 * NOP command to be completed (see below). In this case, bail. 2571 */ 2572 if (sc->need_mcsetup) 2573 return; 2574 sc->need_mcsetup = 1; 2575 2576 /* 2577 * Add a NOP command with interrupt so that we are notified 2578 * when all TX commands have been processed. 2579 */ 2580 txp = sc->fxp_desc.tx_last->tx_next; 2581 txp->tx_mbuf = NULL; 2582 txp->tx_cb->cb_status = 0; 2583 txp->tx_cb->cb_command = htole16(FXP_CB_COMMAND_NOP | 2584 FXP_CB_COMMAND_S | FXP_CB_COMMAND_I); 2585 /* 2586 * Advance the end of list forward. 2587 */ 2588 sc->fxp_desc.tx_last->tx_cb->cb_command &= 2589 htole16(~FXP_CB_COMMAND_S); 2590 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE); 2591 sc->fxp_desc.tx_last = txp; 2592 sc->tx_queued++; 2593 /* 2594 * Issue a resume in case the CU has just suspended. 2595 */ 2596 fxp_scb_wait(sc); 2597 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_RESUME); 2598 /* 2599 * Set a 5 second timer just in case we don't hear from the 2600 * card again. 2601 */ 2602 ifp->if_timer = 5; 2603 2604 return; 2605 } 2606 sc->need_mcsetup = 0; 2607 2608 /* 2609 * Initialize multicast setup descriptor. 2610 */ 2611 mcsp->cb_status = 0; 2612 mcsp->cb_command = htole16(FXP_CB_COMMAND_MCAS | 2613 FXP_CB_COMMAND_S | FXP_CB_COMMAND_I); 2614 mcsp->link_addr = htole32(sc->fxp_desc.cbl_addr); 2615 txp = &sc->fxp_desc.mcs_tx; 2616 txp->tx_mbuf = NULL; 2617 txp->tx_cb = (struct fxp_cb_tx *)sc->mcsp; 2618 txp->tx_next = sc->fxp_desc.tx_list; 2619 (void) fxp_mc_addrs(sc); 2620 sc->fxp_desc.tx_first = sc->fxp_desc.tx_last = txp; 2621 sc->tx_queued = 1; 2622 2623 /* 2624 * Wait until command unit is not active. This should never 2625 * be the case when nothing is queued, but make sure anyway. 2626 */ 2627 count = 100; 2628 while ((CSR_READ_1(sc, FXP_CSR_SCB_RUSCUS) >> 6) == 2629 FXP_SCB_CUS_ACTIVE && --count) 2630 DELAY(10); 2631 if (count == 0) { 2632 device_printf(sc->dev, "command queue timeout\n"); 2633 return; 2634 } 2635 2636 /* 2637 * Start the multicast setup command. 2638 */ 2639 fxp_scb_wait(sc); 2640 bus_dmamap_sync(sc->mcs_tag, sc->mcs_map, BUS_DMASYNC_PREWRITE); 2641 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->mcs_addr); 2642 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2643 2644 ifp->if_timer = 2; 2645 return; 2646 } 2647 2648 static u_int32_t fxp_ucode_d101a[] = D101_A_RCVBUNDLE_UCODE; 2649 static u_int32_t fxp_ucode_d101b0[] = D101_B0_RCVBUNDLE_UCODE; 2650 static u_int32_t fxp_ucode_d101ma[] = D101M_B_RCVBUNDLE_UCODE; 2651 static u_int32_t fxp_ucode_d101s[] = D101S_RCVBUNDLE_UCODE; 2652 static u_int32_t fxp_ucode_d102[] = D102_B_RCVBUNDLE_UCODE; 2653 static u_int32_t fxp_ucode_d102c[] = D102_C_RCVBUNDLE_UCODE; 2654 2655 #define UCODE(x) x, sizeof(x) 2656 2657 struct ucode { 2658 u_int32_t revision; 2659 u_int32_t *ucode; 2660 int length; 2661 u_short int_delay_offset; 2662 u_short bundle_max_offset; 2663 } ucode_table[] = { 2664 { FXP_REV_82558_A4, UCODE(fxp_ucode_d101a), D101_CPUSAVER_DWORD, 0 }, 2665 { FXP_REV_82558_B0, UCODE(fxp_ucode_d101b0), D101_CPUSAVER_DWORD, 0 }, 2666 { FXP_REV_82559_A0, UCODE(fxp_ucode_d101ma), 2667 D101M_CPUSAVER_DWORD, D101M_CPUSAVER_BUNDLE_MAX_DWORD }, 2668 { FXP_REV_82559S_A, UCODE(fxp_ucode_d101s), 2669 D101S_CPUSAVER_DWORD, D101S_CPUSAVER_BUNDLE_MAX_DWORD }, 2670 { FXP_REV_82550, UCODE(fxp_ucode_d102), 2671 D102_B_CPUSAVER_DWORD, D102_B_CPUSAVER_BUNDLE_MAX_DWORD }, 2672 { FXP_REV_82550_C, UCODE(fxp_ucode_d102c), 2673 D102_C_CPUSAVER_DWORD, D102_C_CPUSAVER_BUNDLE_MAX_DWORD }, 2674 { 0, NULL, 0, 0, 0 } 2675 }; 2676 2677 static void 2678 fxp_load_ucode(struct fxp_softc *sc) 2679 { 2680 struct ucode *uc; 2681 struct fxp_cb_ucode *cbp; 2682 2683 for (uc = ucode_table; uc->ucode != NULL; uc++) 2684 if (sc->revision == uc->revision) 2685 break; 2686 if (uc->ucode == NULL) 2687 return; 2688 cbp = (struct fxp_cb_ucode *)sc->fxp_desc.cbl_list; 2689 cbp->cb_status = 0; 2690 cbp->cb_command = htole16(FXP_CB_COMMAND_UCODE | FXP_CB_COMMAND_EL); 2691 cbp->link_addr = 0xffffffff; /* (no) next command */ 2692 memcpy(cbp->ucode, uc->ucode, uc->length); 2693 if (uc->int_delay_offset) 2694 *(u_int16_t *)&cbp->ucode[uc->int_delay_offset] = 2695 htole16(sc->tunable_int_delay + sc->tunable_int_delay / 2); 2696 if (uc->bundle_max_offset) 2697 *(u_int16_t *)&cbp->ucode[uc->bundle_max_offset] = 2698 htole16(sc->tunable_bundle_max); 2699 /* 2700 * Download the ucode to the chip. 2701 */ 2702 fxp_scb_wait(sc); 2703 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE); 2704 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->fxp_desc.cbl_addr); 2705 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2706 /* ...and wait for it to complete. */ 2707 fxp_dma_wait(sc, &cbp->cb_status, sc->cbl_tag, sc->cbl_map); 2708 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_POSTWRITE); 2709 device_printf(sc->dev, 2710 "Microcode loaded, int_delay: %d usec bundle_max: %d\n", 2711 sc->tunable_int_delay, 2712 uc->bundle_max_offset == 0 ? 0 : sc->tunable_bundle_max); 2713 sc->flags |= FXP_FLAG_UCODE; 2714 } 2715 2716 static int 2717 sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high) 2718 { 2719 int error, value; 2720 2721 value = *(int *)arg1; 2722 error = sysctl_handle_int(oidp, &value, 0, req); 2723 if (error || !req->newptr) 2724 return (error); 2725 if (value < low || value > high) 2726 return (EINVAL); 2727 *(int *)arg1 = value; 2728 return (0); 2729 } 2730 2731 /* 2732 * Interrupt delay is expressed in microseconds, a multiplier is used 2733 * to convert this to the appropriate clock ticks before using. 2734 */ 2735 static int 2736 sysctl_hw_fxp_int_delay(SYSCTL_HANDLER_ARGS) 2737 { 2738 return (sysctl_int_range(oidp, arg1, arg2, req, 300, 3000)); 2739 } 2740 2741 static int 2742 sysctl_hw_fxp_bundle_max(SYSCTL_HANDLER_ARGS) 2743 { 2744 return (sysctl_int_range(oidp, arg1, arg2, req, 1, 0xffff)); 2745 } 2746