1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 1995, David Greenman 5 * Copyright (c) 2001 Jonathan Lemon <jlemon@freebsd.org> 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice unmodified, this list of conditions, and the following 13 * disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 * 30 */ 31 32 #include <sys/cdefs.h> 33 /* 34 * Intel EtherExpress Pro/100B PCI Fast Ethernet driver 35 */ 36 37 #ifdef HAVE_KERNEL_OPTION_HEADERS 38 #include "opt_device_polling.h" 39 #endif 40 41 #include <sys/param.h> 42 #include <sys/systm.h> 43 #include <sys/bus.h> 44 #include <sys/endian.h> 45 #include <sys/kernel.h> 46 #include <sys/mbuf.h> 47 #include <sys/lock.h> 48 #include <sys/malloc.h> 49 #include <sys/module.h> 50 #include <sys/mutex.h> 51 #include <sys/rman.h> 52 #include <sys/socket.h> 53 #include <sys/sockio.h> 54 #include <sys/sysctl.h> 55 56 #include <net/bpf.h> 57 #include <net/ethernet.h> 58 #include <net/if.h> 59 #include <net/if_var.h> 60 #include <net/if_arp.h> 61 #include <net/if_dl.h> 62 #include <net/if_media.h> 63 #include <net/if_types.h> 64 #include <net/if_vlan_var.h> 65 66 #include <netinet/in.h> 67 #include <netinet/in_systm.h> 68 #include <netinet/ip.h> 69 #include <netinet/tcp.h> 70 #include <netinet/udp.h> 71 72 #include <machine/bus.h> 73 #include <machine/in_cksum.h> 74 #include <machine/resource.h> 75 76 #include <dev/pci/pcivar.h> 77 #include <dev/pci/pcireg.h> /* for PCIM_CMD_xxx */ 78 79 #include <dev/mii/mii.h> 80 #include <dev/mii/miivar.h> 81 82 #include <dev/fxp/if_fxpreg.h> 83 #include <dev/fxp/if_fxpvar.h> 84 #include <dev/fxp/rcvbundl.h> 85 86 MODULE_DEPEND(fxp, pci, 1, 1, 1); 87 MODULE_DEPEND(fxp, ether, 1, 1, 1); 88 MODULE_DEPEND(fxp, miibus, 1, 1, 1); 89 #include "miibus_if.h" 90 91 /* 92 * NOTE! On !x86 we typically have an alignment constraint. The 93 * card DMAs the packet immediately following the RFA. However, 94 * the first thing in the packet is a 14-byte Ethernet header. 95 * This means that the packet is misaligned. To compensate, 96 * we actually offset the RFA 2 bytes into the cluster. This 97 * alignes the packet after the Ethernet header at a 32-bit 98 * boundary. HOWEVER! This means that the RFA is misaligned! 99 */ 100 #define RFA_ALIGNMENT_FUDGE 2 101 102 /* 103 * Set initial transmit threshold at 64 (512 bytes). This is 104 * increased by 64 (512 bytes) at a time, to maximum of 192 105 * (1536 bytes), if an underrun occurs. 106 */ 107 static int tx_threshold = 64; 108 109 /* 110 * The configuration byte map has several undefined fields which 111 * must be one or must be zero. Set up a template for these bits. 112 * The actual configuration is performed in fxp_init_body. 113 * 114 * See struct fxp_cb_config for the bit definitions. 115 */ 116 static const u_char fxp_cb_config_template[] = { 117 0x0, 0x0, /* cb_status */ 118 0x0, 0x0, /* cb_command */ 119 0x0, 0x0, 0x0, 0x0, /* link_addr */ 120 0x0, /* 0 */ 121 0x0, /* 1 */ 122 0x0, /* 2 */ 123 0x0, /* 3 */ 124 0x0, /* 4 */ 125 0x0, /* 5 */ 126 0x32, /* 6 */ 127 0x0, /* 7 */ 128 0x0, /* 8 */ 129 0x0, /* 9 */ 130 0x6, /* 10 */ 131 0x0, /* 11 */ 132 0x0, /* 12 */ 133 0x0, /* 13 */ 134 0xf2, /* 14 */ 135 0x48, /* 15 */ 136 0x0, /* 16 */ 137 0x40, /* 17 */ 138 0xf0, /* 18 */ 139 0x0, /* 19 */ 140 0x3f, /* 20 */ 141 0x5, /* 21 */ 142 0x0, /* 22 */ 143 0x0, /* 23 */ 144 0x0, /* 24 */ 145 0x0, /* 25 */ 146 0x0, /* 26 */ 147 0x0, /* 27 */ 148 0x0, /* 28 */ 149 0x0, /* 29 */ 150 0x0, /* 30 */ 151 0x0 /* 31 */ 152 }; 153 154 /* 155 * Claim various Intel PCI device identifiers for this driver. The 156 * sub-vendor and sub-device field are extensively used to identify 157 * particular variants, but we don't currently differentiate between 158 * them. 159 */ 160 static const struct fxp_ident fxp_ident_table[] = { 161 { 0x8086, 0x1029, -1, 0, "Intel 82559 PCI/CardBus Pro/100" }, 162 { 0x8086, 0x1030, -1, 0, "Intel 82559 Pro/100 Ethernet" }, 163 { 0x8086, 0x1031, -1, 3, "Intel 82801CAM (ICH3) Pro/100 VE Ethernet" }, 164 { 0x8086, 0x1032, -1, 3, "Intel 82801CAM (ICH3) Pro/100 VE Ethernet" }, 165 { 0x8086, 0x1033, -1, 3, "Intel 82801CAM (ICH3) Pro/100 VM Ethernet" }, 166 { 0x8086, 0x1034, -1, 3, "Intel 82801CAM (ICH3) Pro/100 VM Ethernet" }, 167 { 0x8086, 0x1035, -1, 3, "Intel 82801CAM (ICH3) Pro/100 Ethernet" }, 168 { 0x8086, 0x1036, -1, 3, "Intel 82801CAM (ICH3) Pro/100 Ethernet" }, 169 { 0x8086, 0x1037, -1, 3, "Intel 82801CAM (ICH3) Pro/100 Ethernet" }, 170 { 0x8086, 0x1038, -1, 3, "Intel 82801CAM (ICH3) Pro/100 VM Ethernet" }, 171 { 0x8086, 0x1039, -1, 4, "Intel 82801DB (ICH4) Pro/100 VE Ethernet" }, 172 { 0x8086, 0x103A, -1, 4, "Intel 82801DB (ICH4) Pro/100 Ethernet" }, 173 { 0x8086, 0x103B, -1, 4, "Intel 82801DB (ICH4) Pro/100 VM Ethernet" }, 174 { 0x8086, 0x103C, -1, 4, "Intel 82801DB (ICH4) Pro/100 Ethernet" }, 175 { 0x8086, 0x103D, -1, 4, "Intel 82801DB (ICH4) Pro/100 VE Ethernet" }, 176 { 0x8086, 0x103E, -1, 4, "Intel 82801DB (ICH4) Pro/100 VM Ethernet" }, 177 { 0x8086, 0x1050, -1, 5, "Intel 82801BA (D865) Pro/100 VE Ethernet" }, 178 { 0x8086, 0x1051, -1, 5, "Intel 82562ET (ICH5/ICH5R) Pro/100 VE Ethernet" }, 179 { 0x8086, 0x1059, -1, 0, "Intel 82551QM Pro/100 M Mobile Connection" }, 180 { 0x8086, 0x1064, -1, 6, "Intel 82562EZ (ICH6)" }, 181 { 0x8086, 0x1065, -1, 6, "Intel 82562ET/EZ/GT/GZ PRO/100 VE Ethernet" }, 182 { 0x8086, 0x1068, -1, 6, "Intel 82801FBM (ICH6-M) Pro/100 VE Ethernet" }, 183 { 0x8086, 0x1069, -1, 6, "Intel 82562EM/EX/GX Pro/100 Ethernet" }, 184 { 0x8086, 0x1091, -1, 7, "Intel 82562GX Pro/100 Ethernet" }, 185 { 0x8086, 0x1092, -1, 7, "Intel Pro/100 VE Network Connection" }, 186 { 0x8086, 0x1093, -1, 7, "Intel Pro/100 VM Network Connection" }, 187 { 0x8086, 0x1094, -1, 7, "Intel Pro/100 946GZ (ICH7) Network Connection" }, 188 { 0x8086, 0x1209, -1, 0, "Intel 82559ER Embedded 10/100 Ethernet" }, 189 { 0x8086, 0x1229, 0x01, 0, "Intel 82557 Pro/100 Ethernet" }, 190 { 0x8086, 0x1229, 0x02, 0, "Intel 82557 Pro/100 Ethernet" }, 191 { 0x8086, 0x1229, 0x03, 0, "Intel 82557 Pro/100 Ethernet" }, 192 { 0x8086, 0x1229, 0x04, 0, "Intel 82558 Pro/100 Ethernet" }, 193 { 0x8086, 0x1229, 0x05, 0, "Intel 82558 Pro/100 Ethernet" }, 194 { 0x8086, 0x1229, 0x06, 0, "Intel 82559 Pro/100 Ethernet" }, 195 { 0x8086, 0x1229, 0x07, 0, "Intel 82559 Pro/100 Ethernet" }, 196 { 0x8086, 0x1229, 0x08, 0, "Intel 82559 Pro/100 Ethernet" }, 197 { 0x8086, 0x1229, 0x09, 0, "Intel 82559ER Pro/100 Ethernet" }, 198 { 0x8086, 0x1229, 0x0c, 0, "Intel 82550 Pro/100 Ethernet" }, 199 { 0x8086, 0x1229, 0x0d, 0, "Intel 82550C Pro/100 Ethernet" }, 200 { 0x8086, 0x1229, 0x0e, 0, "Intel 82550 Pro/100 Ethernet" }, 201 { 0x8086, 0x1229, 0x0f, 0, "Intel 82551 Pro/100 Ethernet" }, 202 { 0x8086, 0x1229, 0x10, 0, "Intel 82551 Pro/100 Ethernet" }, 203 { 0x8086, 0x1229, -1, 0, "Intel 82557/8/9 Pro/100 Ethernet" }, 204 { 0x8086, 0x2449, -1, 2, "Intel 82801BA/CAM (ICH2/3) Pro/100 Ethernet" }, 205 { 0x8086, 0x27dc, -1, 7, "Intel 82801GB (ICH7) 10/100 Ethernet" }, 206 { 0, 0, -1, 0, NULL }, 207 }; 208 209 #ifdef FXP_IP_CSUM_WAR 210 #define FXP_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 211 #else 212 #define FXP_CSUM_FEATURES (CSUM_TCP | CSUM_UDP) 213 #endif 214 215 static int fxp_probe(device_t dev); 216 static int fxp_attach(device_t dev); 217 static int fxp_detach(device_t dev); 218 static int fxp_shutdown(device_t dev); 219 static int fxp_suspend(device_t dev); 220 static int fxp_resume(device_t dev); 221 222 static const struct fxp_ident *fxp_find_ident(device_t dev); 223 static void fxp_intr(void *xsc); 224 static void fxp_rxcsum(struct fxp_softc *sc, if_t ifp, 225 struct mbuf *m, uint16_t status, int pos); 226 static int fxp_intr_body(struct fxp_softc *sc, if_t ifp, 227 uint8_t statack, int count); 228 static void fxp_init(void *xsc); 229 static void fxp_init_body(struct fxp_softc *sc, int); 230 static void fxp_tick(void *xsc); 231 static void fxp_start(if_t ifp); 232 static void fxp_start_body(if_t ifp); 233 static int fxp_encap(struct fxp_softc *sc, struct mbuf **m_head); 234 static void fxp_txeof(struct fxp_softc *sc); 235 static void fxp_stop(struct fxp_softc *sc); 236 static void fxp_release(struct fxp_softc *sc); 237 static int fxp_ioctl(if_t ifp, u_long command, 238 caddr_t data); 239 static void fxp_watchdog(struct fxp_softc *sc); 240 static void fxp_add_rfabuf(struct fxp_softc *sc, 241 struct fxp_rx *rxp); 242 static void fxp_discard_rfabuf(struct fxp_softc *sc, 243 struct fxp_rx *rxp); 244 static int fxp_new_rfabuf(struct fxp_softc *sc, 245 struct fxp_rx *rxp); 246 static void fxp_mc_addrs(struct fxp_softc *sc); 247 static void fxp_mc_setup(struct fxp_softc *sc); 248 static uint16_t fxp_eeprom_getword(struct fxp_softc *sc, int offset, 249 int autosize); 250 static void fxp_eeprom_putword(struct fxp_softc *sc, int offset, 251 uint16_t data); 252 static void fxp_autosize_eeprom(struct fxp_softc *sc); 253 static void fxp_load_eeprom(struct fxp_softc *sc); 254 static void fxp_read_eeprom(struct fxp_softc *sc, u_short *data, 255 int offset, int words); 256 static void fxp_write_eeprom(struct fxp_softc *sc, u_short *data, 257 int offset, int words); 258 static int fxp_ifmedia_upd(if_t ifp); 259 static void fxp_ifmedia_sts(if_t ifp, 260 struct ifmediareq *ifmr); 261 static int fxp_serial_ifmedia_upd(if_t ifp); 262 static void fxp_serial_ifmedia_sts(if_t ifp, 263 struct ifmediareq *ifmr); 264 static int fxp_miibus_readreg(device_t dev, int phy, int reg); 265 static int fxp_miibus_writereg(device_t dev, int phy, int reg, 266 int value); 267 static void fxp_miibus_statchg(device_t dev); 268 static void fxp_load_ucode(struct fxp_softc *sc); 269 static void fxp_update_stats(struct fxp_softc *sc); 270 static void fxp_sysctl_node(struct fxp_softc *sc); 271 static int sysctl_int_range(SYSCTL_HANDLER_ARGS, 272 int low, int high); 273 static int sysctl_hw_fxp_bundle_max(SYSCTL_HANDLER_ARGS); 274 static int sysctl_hw_fxp_int_delay(SYSCTL_HANDLER_ARGS); 275 static void fxp_scb_wait(struct fxp_softc *sc); 276 static void fxp_scb_cmd(struct fxp_softc *sc, int cmd); 277 static void fxp_dma_wait(struct fxp_softc *sc, 278 volatile uint16_t *status, bus_dma_tag_t dmat, 279 bus_dmamap_t map); 280 281 static device_method_t fxp_methods[] = { 282 /* Device interface */ 283 DEVMETHOD(device_probe, fxp_probe), 284 DEVMETHOD(device_attach, fxp_attach), 285 DEVMETHOD(device_detach, fxp_detach), 286 DEVMETHOD(device_shutdown, fxp_shutdown), 287 DEVMETHOD(device_suspend, fxp_suspend), 288 DEVMETHOD(device_resume, fxp_resume), 289 290 /* MII interface */ 291 DEVMETHOD(miibus_readreg, fxp_miibus_readreg), 292 DEVMETHOD(miibus_writereg, fxp_miibus_writereg), 293 DEVMETHOD(miibus_statchg, fxp_miibus_statchg), 294 295 DEVMETHOD_END 296 }; 297 298 static driver_t fxp_driver = { 299 "fxp", 300 fxp_methods, 301 sizeof(struct fxp_softc), 302 }; 303 304 DRIVER_MODULE_ORDERED(fxp, pci, fxp_driver, NULL, NULL, SI_ORDER_ANY); 305 MODULE_PNP_INFO("U16:vendor;U16:device", pci, fxp, fxp_ident_table, 306 nitems(fxp_ident_table) - 1); 307 DRIVER_MODULE(miibus, fxp, miibus_driver, NULL, NULL); 308 309 static struct resource_spec fxp_res_spec_mem[] = { 310 { SYS_RES_MEMORY, FXP_PCI_MMBA, RF_ACTIVE }, 311 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE }, 312 { -1, 0 } 313 }; 314 315 static struct resource_spec fxp_res_spec_io[] = { 316 { SYS_RES_IOPORT, FXP_PCI_IOBA, RF_ACTIVE }, 317 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE }, 318 { -1, 0 } 319 }; 320 321 /* 322 * Wait for the previous command to be accepted (but not necessarily 323 * completed). 324 */ 325 static void 326 fxp_scb_wait(struct fxp_softc *sc) 327 { 328 union { 329 uint16_t w; 330 uint8_t b[2]; 331 } flowctl; 332 int i = 10000; 333 334 while (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) && --i) 335 DELAY(2); 336 if (i == 0) { 337 flowctl.b[0] = CSR_READ_1(sc, FXP_CSR_FC_THRESH); 338 flowctl.b[1] = CSR_READ_1(sc, FXP_CSR_FC_STATUS); 339 device_printf(sc->dev, "SCB timeout: 0x%x 0x%x 0x%x 0x%x\n", 340 CSR_READ_1(sc, FXP_CSR_SCB_COMMAND), 341 CSR_READ_1(sc, FXP_CSR_SCB_STATACK), 342 CSR_READ_1(sc, FXP_CSR_SCB_RUSCUS), flowctl.w); 343 } 344 } 345 346 static void 347 fxp_scb_cmd(struct fxp_softc *sc, int cmd) 348 { 349 350 if (cmd == FXP_SCB_COMMAND_CU_RESUME && sc->cu_resume_bug) { 351 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_CB_COMMAND_NOP); 352 fxp_scb_wait(sc); 353 } 354 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, cmd); 355 } 356 357 static void 358 fxp_dma_wait(struct fxp_softc *sc, volatile uint16_t *status, 359 bus_dma_tag_t dmat, bus_dmamap_t map) 360 { 361 int i; 362 363 for (i = 10000; i > 0; i--) { 364 DELAY(2); 365 bus_dmamap_sync(dmat, map, 366 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 367 if ((le16toh(*status) & FXP_CB_STATUS_C) != 0) 368 break; 369 } 370 if (i == 0) 371 device_printf(sc->dev, "DMA timeout\n"); 372 } 373 374 static const struct fxp_ident * 375 fxp_find_ident(device_t dev) 376 { 377 uint16_t vendor; 378 uint16_t device; 379 uint8_t revid; 380 const struct fxp_ident *ident; 381 382 vendor = pci_get_vendor(dev); 383 device = pci_get_device(dev); 384 revid = pci_get_revid(dev); 385 for (ident = fxp_ident_table; ident->name != NULL; ident++) { 386 if (ident->vendor == vendor && ident->device == device && 387 (ident->revid == revid || ident->revid == -1)) { 388 return (ident); 389 } 390 } 391 return (NULL); 392 } 393 394 /* 395 * Return identification string if this device is ours. 396 */ 397 static int 398 fxp_probe(device_t dev) 399 { 400 const struct fxp_ident *ident; 401 402 ident = fxp_find_ident(dev); 403 if (ident != NULL) { 404 device_set_desc(dev, ident->name); 405 return (BUS_PROBE_DEFAULT); 406 } 407 return (ENXIO); 408 } 409 410 static void 411 fxp_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error) 412 { 413 uint32_t *addr; 414 415 if (error) 416 return; 417 418 KASSERT(nseg == 1, ("too many DMA segments, %d should be 1", nseg)); 419 addr = arg; 420 *addr = segs->ds_addr; 421 } 422 423 static int 424 fxp_attach(device_t dev) 425 { 426 struct fxp_softc *sc; 427 struct fxp_cb_tx *tcbp; 428 struct fxp_tx *txp; 429 struct fxp_rx *rxp; 430 if_t ifp; 431 uint32_t val; 432 uint16_t data; 433 u_char eaddr[ETHER_ADDR_LEN]; 434 int error, flags, i, pmc, prefer_iomap; 435 436 error = 0; 437 sc = device_get_softc(dev); 438 sc->dev = dev; 439 mtx_init(&sc->sc_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 440 MTX_DEF); 441 callout_init_mtx(&sc->stat_ch, &sc->sc_mtx, 0); 442 ifmedia_init(&sc->sc_media, 0, fxp_serial_ifmedia_upd, 443 fxp_serial_ifmedia_sts); 444 445 ifp = sc->ifp = if_gethandle(IFT_ETHER); 446 447 /* 448 * Enable bus mastering. 449 */ 450 pci_enable_busmaster(dev); 451 452 /* 453 * Figure out which we should try first - memory mapping or i/o mapping? 454 * We default to memory mapping. Then we accept an override from the 455 * command line. Then we check to see which one is enabled. 456 */ 457 prefer_iomap = 0; 458 resource_int_value(device_get_name(dev), device_get_unit(dev), 459 "prefer_iomap", &prefer_iomap); 460 if (prefer_iomap) 461 sc->fxp_spec = fxp_res_spec_io; 462 else 463 sc->fxp_spec = fxp_res_spec_mem; 464 465 error = bus_alloc_resources(dev, sc->fxp_spec, sc->fxp_res); 466 if (error) { 467 if (sc->fxp_spec == fxp_res_spec_mem) 468 sc->fxp_spec = fxp_res_spec_io; 469 else 470 sc->fxp_spec = fxp_res_spec_mem; 471 error = bus_alloc_resources(dev, sc->fxp_spec, sc->fxp_res); 472 } 473 if (error) { 474 device_printf(dev, "could not allocate resources\n"); 475 error = ENXIO; 476 goto fail; 477 } 478 479 if (bootverbose) { 480 device_printf(dev, "using %s space register mapping\n", 481 sc->fxp_spec == fxp_res_spec_mem ? "memory" : "I/O"); 482 } 483 484 /* 485 * Put CU/RU idle state and prepare full reset. 486 */ 487 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET); 488 DELAY(10); 489 /* Full reset and disable interrupts. */ 490 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SOFTWARE_RESET); 491 DELAY(10); 492 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE); 493 494 /* 495 * Find out how large of an SEEPROM we have. 496 */ 497 fxp_autosize_eeprom(sc); 498 fxp_load_eeprom(sc); 499 500 /* 501 * Find out the chip revision; lump all 82557 revs together. 502 */ 503 sc->ident = fxp_find_ident(dev); 504 if (sc->ident->ich > 0) { 505 /* Assume ICH controllers are 82559. */ 506 sc->revision = FXP_REV_82559_A0; 507 } else { 508 data = sc->eeprom[FXP_EEPROM_MAP_CNTR]; 509 if ((data >> 8) == 1) 510 sc->revision = FXP_REV_82557; 511 else 512 sc->revision = pci_get_revid(dev); 513 } 514 515 /* 516 * Check availability of WOL. 82559ER does not support WOL. 517 */ 518 if (sc->revision >= FXP_REV_82558_A4 && 519 sc->revision != FXP_REV_82559S_A) { 520 data = sc->eeprom[FXP_EEPROM_MAP_ID]; 521 if ((data & 0x20) != 0 && 522 pci_find_cap(sc->dev, PCIY_PMG, &pmc) == 0) 523 sc->flags |= FXP_FLAG_WOLCAP; 524 } 525 526 if (sc->revision == FXP_REV_82550_C) { 527 /* 528 * 82550C with server extension requires microcode to 529 * receive fragmented UDP datagrams. However if the 530 * microcode is used for client-only featured 82550C 531 * it locks up controller. 532 */ 533 data = sc->eeprom[FXP_EEPROM_MAP_COMPAT]; 534 if ((data & 0x0400) == 0) 535 sc->flags |= FXP_FLAG_NO_UCODE; 536 } 537 538 /* Receiver lock-up workaround detection. */ 539 if (sc->revision < FXP_REV_82558_A4) { 540 data = sc->eeprom[FXP_EEPROM_MAP_COMPAT]; 541 if ((data & 0x03) != 0x03) { 542 sc->flags |= FXP_FLAG_RXBUG; 543 device_printf(dev, "Enabling Rx lock-up workaround\n"); 544 } 545 } 546 547 /* 548 * Determine whether we must use the 503 serial interface. 549 */ 550 data = sc->eeprom[FXP_EEPROM_MAP_PRI_PHY]; 551 if (sc->revision == FXP_REV_82557 && (data & FXP_PHY_DEVICE_MASK) != 0 552 && (data & FXP_PHY_SERIAL_ONLY)) 553 sc->flags |= FXP_FLAG_SERIAL_MEDIA; 554 555 fxp_sysctl_node(sc); 556 /* 557 * Enable workarounds for certain chip revision deficiencies. 558 * 559 * Systems based on the ICH2/ICH2-M chip from Intel, and possibly 560 * some systems based a normal 82559 design, have a defect where 561 * the chip can cause a PCI protocol violation if it receives 562 * a CU_RESUME command when it is entering the IDLE state. The 563 * workaround is to disable Dynamic Standby Mode, so the chip never 564 * deasserts CLKRUN#, and always remains in an active state. 565 * 566 * See Intel 82801BA/82801BAM Specification Update, Errata #30. 567 */ 568 if ((sc->ident->ich >= 2 && sc->ident->ich <= 3) || 569 (sc->ident->ich == 0 && sc->revision >= FXP_REV_82559_A0)) { 570 data = sc->eeprom[FXP_EEPROM_MAP_ID]; 571 if (data & 0x02) { /* STB enable */ 572 uint16_t cksum; 573 int i; 574 575 device_printf(dev, 576 "Disabling dynamic standby mode in EEPROM\n"); 577 data &= ~0x02; 578 sc->eeprom[FXP_EEPROM_MAP_ID] = data; 579 fxp_write_eeprom(sc, &data, FXP_EEPROM_MAP_ID, 1); 580 device_printf(dev, "New EEPROM ID: 0x%x\n", data); 581 cksum = 0; 582 for (i = 0; i < (1 << sc->eeprom_size) - 1; i++) 583 cksum += sc->eeprom[i]; 584 i = (1 << sc->eeprom_size) - 1; 585 cksum = 0xBABA - cksum; 586 fxp_write_eeprom(sc, &cksum, i, 1); 587 device_printf(dev, 588 "EEPROM checksum @ 0x%x: 0x%x -> 0x%x\n", 589 i, sc->eeprom[i], cksum); 590 sc->eeprom[i] = cksum; 591 /* 592 * If the user elects to continue, try the software 593 * workaround, as it is better than nothing. 594 */ 595 sc->flags |= FXP_FLAG_CU_RESUME_BUG; 596 } 597 } 598 599 /* 600 * If we are not a 82557 chip, we can enable extended features. 601 */ 602 if (sc->revision != FXP_REV_82557) { 603 /* 604 * If MWI is enabled in the PCI configuration, and there 605 * is a valid cacheline size (8 or 16 dwords), then tell 606 * the board to turn on MWI. 607 */ 608 val = pci_read_config(dev, PCIR_COMMAND, 2); 609 if (val & PCIM_CMD_MWRICEN && 610 pci_read_config(dev, PCIR_CACHELNSZ, 1) != 0) 611 sc->flags |= FXP_FLAG_MWI_ENABLE; 612 613 /* turn on the extended TxCB feature */ 614 sc->flags |= FXP_FLAG_EXT_TXCB; 615 616 /* enable reception of long frames for VLAN */ 617 sc->flags |= FXP_FLAG_LONG_PKT_EN; 618 } else { 619 /* a hack to get long VLAN frames on a 82557 */ 620 sc->flags |= FXP_FLAG_SAVE_BAD; 621 } 622 623 /* For 82559 or later chips, Rx checksum offload is supported. */ 624 if (sc->revision >= FXP_REV_82559_A0) { 625 /* 82559ER does not support Rx checksum offloading. */ 626 if (sc->ident->device != 0x1209) 627 sc->flags |= FXP_FLAG_82559_RXCSUM; 628 } 629 /* 630 * Enable use of extended RFDs and TCBs for 82550 631 * and later chips. Note: we need extended TXCB support 632 * too, but that's already enabled by the code above. 633 * Be careful to do this only on the right devices. 634 */ 635 if (sc->revision == FXP_REV_82550 || sc->revision == FXP_REV_82550_C || 636 sc->revision == FXP_REV_82551_E || sc->revision == FXP_REV_82551_F 637 || sc->revision == FXP_REV_82551_10) { 638 sc->rfa_size = sizeof (struct fxp_rfa); 639 sc->tx_cmd = FXP_CB_COMMAND_IPCBXMIT; 640 sc->flags |= FXP_FLAG_EXT_RFA; 641 /* Use extended RFA instead of 82559 checksum mode. */ 642 sc->flags &= ~FXP_FLAG_82559_RXCSUM; 643 } else { 644 sc->rfa_size = sizeof (struct fxp_rfa) - FXP_RFAX_LEN; 645 sc->tx_cmd = FXP_CB_COMMAND_XMIT; 646 } 647 648 /* 649 * Allocate DMA tags and DMA safe memory. 650 */ 651 sc->maxtxseg = FXP_NTXSEG; 652 sc->maxsegsize = MCLBYTES; 653 if (sc->flags & FXP_FLAG_EXT_RFA) { 654 sc->maxtxseg--; 655 sc->maxsegsize = FXP_TSO_SEGSIZE; 656 } 657 error = bus_dma_tag_create(bus_get_dma_tag(dev), 2, 0, 658 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 659 sc->maxsegsize * sc->maxtxseg + sizeof(struct ether_vlan_header), 660 sc->maxtxseg, sc->maxsegsize, 0, NULL, NULL, &sc->fxp_txmtag); 661 if (error) { 662 device_printf(dev, "could not create TX DMA tag\n"); 663 goto fail; 664 } 665 666 error = bus_dma_tag_create(bus_get_dma_tag(dev), 2, 0, 667 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 668 MCLBYTES, 1, MCLBYTES, 0, NULL, NULL, &sc->fxp_rxmtag); 669 if (error) { 670 device_printf(dev, "could not create RX DMA tag\n"); 671 goto fail; 672 } 673 674 error = bus_dma_tag_create(bus_get_dma_tag(dev), 4, 0, 675 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 676 sizeof(struct fxp_stats), 1, sizeof(struct fxp_stats), 0, 677 NULL, NULL, &sc->fxp_stag); 678 if (error) { 679 device_printf(dev, "could not create stats DMA tag\n"); 680 goto fail; 681 } 682 683 error = bus_dmamem_alloc(sc->fxp_stag, (void **)&sc->fxp_stats, 684 BUS_DMA_NOWAIT | BUS_DMA_COHERENT | BUS_DMA_ZERO, &sc->fxp_smap); 685 if (error) { 686 device_printf(dev, "could not allocate stats DMA memory\n"); 687 goto fail; 688 } 689 error = bus_dmamap_load(sc->fxp_stag, sc->fxp_smap, sc->fxp_stats, 690 sizeof(struct fxp_stats), fxp_dma_map_addr, &sc->stats_addr, 691 BUS_DMA_NOWAIT); 692 if (error) { 693 device_printf(dev, "could not load the stats DMA buffer\n"); 694 goto fail; 695 } 696 697 error = bus_dma_tag_create(bus_get_dma_tag(dev), 4, 0, 698 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 699 FXP_TXCB_SZ, 1, FXP_TXCB_SZ, 0, NULL, NULL, &sc->cbl_tag); 700 if (error) { 701 device_printf(dev, "could not create TxCB DMA tag\n"); 702 goto fail; 703 } 704 705 error = bus_dmamem_alloc(sc->cbl_tag, (void **)&sc->fxp_desc.cbl_list, 706 BUS_DMA_NOWAIT | BUS_DMA_COHERENT | BUS_DMA_ZERO, &sc->cbl_map); 707 if (error) { 708 device_printf(dev, "could not allocate TxCB DMA memory\n"); 709 goto fail; 710 } 711 712 error = bus_dmamap_load(sc->cbl_tag, sc->cbl_map, 713 sc->fxp_desc.cbl_list, FXP_TXCB_SZ, fxp_dma_map_addr, 714 &sc->fxp_desc.cbl_addr, BUS_DMA_NOWAIT); 715 if (error) { 716 device_printf(dev, "could not load TxCB DMA buffer\n"); 717 goto fail; 718 } 719 720 error = bus_dma_tag_create(bus_get_dma_tag(dev), 4, 0, 721 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 722 sizeof(struct fxp_cb_mcs), 1, sizeof(struct fxp_cb_mcs), 0, 723 NULL, NULL, &sc->mcs_tag); 724 if (error) { 725 device_printf(dev, 726 "could not create multicast setup DMA tag\n"); 727 goto fail; 728 } 729 730 error = bus_dmamem_alloc(sc->mcs_tag, (void **)&sc->mcsp, 731 BUS_DMA_NOWAIT | BUS_DMA_COHERENT | BUS_DMA_ZERO, &sc->mcs_map); 732 if (error) { 733 device_printf(dev, 734 "could not allocate multicast setup DMA memory\n"); 735 goto fail; 736 } 737 error = bus_dmamap_load(sc->mcs_tag, sc->mcs_map, sc->mcsp, 738 sizeof(struct fxp_cb_mcs), fxp_dma_map_addr, &sc->mcs_addr, 739 BUS_DMA_NOWAIT); 740 if (error) { 741 device_printf(dev, 742 "can't load the multicast setup DMA buffer\n"); 743 goto fail; 744 } 745 746 /* 747 * Pre-allocate the TX DMA maps and setup the pointers to 748 * the TX command blocks. 749 */ 750 txp = sc->fxp_desc.tx_list; 751 tcbp = sc->fxp_desc.cbl_list; 752 for (i = 0; i < FXP_NTXCB; i++) { 753 txp[i].tx_cb = tcbp + i; 754 error = bus_dmamap_create(sc->fxp_txmtag, 0, &txp[i].tx_map); 755 if (error) { 756 device_printf(dev, "can't create DMA map for TX\n"); 757 goto fail; 758 } 759 } 760 error = bus_dmamap_create(sc->fxp_rxmtag, 0, &sc->spare_map); 761 if (error) { 762 device_printf(dev, "can't create spare DMA map\n"); 763 goto fail; 764 } 765 766 /* 767 * Pre-allocate our receive buffers. 768 */ 769 sc->fxp_desc.rx_head = sc->fxp_desc.rx_tail = NULL; 770 for (i = 0; i < FXP_NRFABUFS; i++) { 771 rxp = &sc->fxp_desc.rx_list[i]; 772 error = bus_dmamap_create(sc->fxp_rxmtag, 0, &rxp->rx_map); 773 if (error) { 774 device_printf(dev, "can't create DMA map for RX\n"); 775 goto fail; 776 } 777 if (fxp_new_rfabuf(sc, rxp) != 0) { 778 error = ENOMEM; 779 goto fail; 780 } 781 fxp_add_rfabuf(sc, rxp); 782 } 783 784 /* 785 * Read MAC address. 786 */ 787 eaddr[0] = sc->eeprom[FXP_EEPROM_MAP_IA0] & 0xff; 788 eaddr[1] = sc->eeprom[FXP_EEPROM_MAP_IA0] >> 8; 789 eaddr[2] = sc->eeprom[FXP_EEPROM_MAP_IA1] & 0xff; 790 eaddr[3] = sc->eeprom[FXP_EEPROM_MAP_IA1] >> 8; 791 eaddr[4] = sc->eeprom[FXP_EEPROM_MAP_IA2] & 0xff; 792 eaddr[5] = sc->eeprom[FXP_EEPROM_MAP_IA2] >> 8; 793 if (bootverbose) { 794 device_printf(dev, "PCI IDs: %04x %04x %04x %04x %04x\n", 795 pci_get_vendor(dev), pci_get_device(dev), 796 pci_get_subvendor(dev), pci_get_subdevice(dev), 797 pci_get_revid(dev)); 798 device_printf(dev, "Dynamic Standby mode is %s\n", 799 sc->eeprom[FXP_EEPROM_MAP_ID] & 0x02 ? "enabled" : 800 "disabled"); 801 } 802 803 /* 804 * If this is only a 10Mbps device, then there is no MII, and 805 * the PHY will use a serial interface instead. 806 * 807 * The Seeq 80c24 AutoDUPLEX(tm) Ethernet Interface Adapter 808 * doesn't have a programming interface of any sort. The 809 * media is sensed automatically based on how the link partner 810 * is configured. This is, in essence, manual configuration. 811 */ 812 if (sc->flags & FXP_FLAG_SERIAL_MEDIA) { 813 ifmedia_add(&sc->sc_media, IFM_ETHER|IFM_MANUAL, 0, NULL); 814 ifmedia_set(&sc->sc_media, IFM_ETHER|IFM_MANUAL); 815 } else { 816 /* 817 * i82557 wedge when isolating all of their PHYs. 818 */ 819 flags = MIIF_NOISOLATE; 820 if (sc->revision >= FXP_REV_82558_A4) 821 flags |= MIIF_DOPAUSE; 822 error = mii_attach(dev, &sc->miibus, ifp, 823 (ifm_change_cb_t)fxp_ifmedia_upd, 824 (ifm_stat_cb_t)fxp_ifmedia_sts, BMSR_DEFCAPMASK, 825 MII_PHY_ANY, MII_OFFSET_ANY, flags); 826 if (error != 0) { 827 device_printf(dev, "attaching PHYs failed\n"); 828 goto fail; 829 } 830 } 831 832 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 833 if_setdev(ifp, dev); 834 if_setinitfn(ifp, fxp_init); 835 if_setsoftc(ifp, sc); 836 if_setflags(ifp, IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST); 837 if_setioctlfn(ifp, fxp_ioctl); 838 if_setstartfn(ifp, fxp_start); 839 840 if_setcapabilities(ifp, 0); 841 if_setcapenable(ifp, 0); 842 843 /* Enable checksum offload/TSO for 82550 or better chips */ 844 if (sc->flags & FXP_FLAG_EXT_RFA) { 845 if_sethwassist(ifp, FXP_CSUM_FEATURES | CSUM_TSO); 846 if_setcapabilitiesbit(ifp, IFCAP_HWCSUM | IFCAP_TSO4, 0); 847 if_setcapenablebit(ifp, IFCAP_HWCSUM | IFCAP_TSO4, 0); 848 } 849 850 if (sc->flags & FXP_FLAG_82559_RXCSUM) { 851 if_setcapabilitiesbit(ifp, IFCAP_RXCSUM, 0); 852 if_setcapenablebit(ifp, IFCAP_RXCSUM, 0); 853 } 854 855 if (sc->flags & FXP_FLAG_WOLCAP) { 856 if_setcapabilitiesbit(ifp, IFCAP_WOL_MAGIC, 0); 857 if_setcapenablebit(ifp, IFCAP_WOL_MAGIC, 0); 858 } 859 860 #ifdef DEVICE_POLLING 861 /* Inform the world we support polling. */ 862 if_setcapabilitiesbit(ifp, IFCAP_POLLING, 0); 863 #endif 864 865 /* 866 * Attach the interface. 867 */ 868 ether_ifattach(ifp, eaddr); 869 870 /* 871 * Tell the upper layer(s) we support long frames. 872 * Must appear after the call to ether_ifattach() because 873 * ether_ifattach() sets ifi_hdrlen to the default value. 874 */ 875 if_setifheaderlen(ifp, sizeof(struct ether_vlan_header)); 876 if_setcapabilitiesbit(ifp, IFCAP_VLAN_MTU, 0); 877 if_setcapenablebit(ifp, IFCAP_VLAN_MTU, 0); 878 if ((sc->flags & FXP_FLAG_EXT_RFA) != 0) { 879 if_setcapabilitiesbit(ifp, IFCAP_VLAN_HWTAGGING | 880 IFCAP_VLAN_HWCSUM | IFCAP_VLAN_HWTSO, 0); 881 if_setcapenablebit(ifp, IFCAP_VLAN_HWTAGGING | 882 IFCAP_VLAN_HWCSUM | IFCAP_VLAN_HWTSO, 0); 883 } 884 885 /* 886 * Let the system queue as many packets as we have available 887 * TX descriptors. 888 */ 889 if_setsendqlen(ifp, FXP_NTXCB - 1); 890 if_setsendqready(ifp); 891 892 /* 893 * Hook our interrupt after all initialization is complete. 894 */ 895 error = bus_setup_intr(dev, sc->fxp_res[1], INTR_TYPE_NET | INTR_MPSAFE, 896 NULL, fxp_intr, sc, &sc->ih); 897 if (error) { 898 device_printf(dev, "could not setup irq\n"); 899 ether_ifdetach(sc->ifp); 900 goto fail; 901 } 902 903 /* 904 * Configure hardware to reject magic frames otherwise 905 * system will hang on recipt of magic frames. 906 */ 907 if ((sc->flags & FXP_FLAG_WOLCAP) != 0) { 908 FXP_LOCK(sc); 909 /* Clear wakeup events. */ 910 CSR_WRITE_1(sc, FXP_CSR_PMDR, CSR_READ_1(sc, FXP_CSR_PMDR)); 911 fxp_init_body(sc, 0); 912 fxp_stop(sc); 913 FXP_UNLOCK(sc); 914 } 915 916 fail: 917 if (error) 918 fxp_release(sc); 919 return (error); 920 } 921 922 /* 923 * Release all resources. The softc lock should not be held and the 924 * interrupt should already be torn down. 925 */ 926 static void 927 fxp_release(struct fxp_softc *sc) 928 { 929 struct fxp_rx *rxp; 930 struct fxp_tx *txp; 931 int i; 932 933 FXP_LOCK_ASSERT(sc, MA_NOTOWNED); 934 KASSERT(sc->ih == NULL, 935 ("fxp_release() called with intr handle still active")); 936 bus_generic_detach(sc->dev); 937 ifmedia_removeall(&sc->sc_media); 938 if (sc->fxp_desc.cbl_list) { 939 bus_dmamap_unload(sc->cbl_tag, sc->cbl_map); 940 bus_dmamem_free(sc->cbl_tag, sc->fxp_desc.cbl_list, 941 sc->cbl_map); 942 } 943 if (sc->fxp_stats) { 944 bus_dmamap_unload(sc->fxp_stag, sc->fxp_smap); 945 bus_dmamem_free(sc->fxp_stag, sc->fxp_stats, sc->fxp_smap); 946 } 947 if (sc->mcsp) { 948 bus_dmamap_unload(sc->mcs_tag, sc->mcs_map); 949 bus_dmamem_free(sc->mcs_tag, sc->mcsp, sc->mcs_map); 950 } 951 bus_release_resources(sc->dev, sc->fxp_spec, sc->fxp_res); 952 if (sc->fxp_rxmtag) { 953 for (i = 0; i < FXP_NRFABUFS; i++) { 954 rxp = &sc->fxp_desc.rx_list[i]; 955 if (rxp->rx_mbuf != NULL) { 956 bus_dmamap_sync(sc->fxp_rxmtag, rxp->rx_map, 957 BUS_DMASYNC_POSTREAD); 958 bus_dmamap_unload(sc->fxp_rxmtag, rxp->rx_map); 959 m_freem(rxp->rx_mbuf); 960 } 961 bus_dmamap_destroy(sc->fxp_rxmtag, rxp->rx_map); 962 } 963 bus_dmamap_destroy(sc->fxp_rxmtag, sc->spare_map); 964 bus_dma_tag_destroy(sc->fxp_rxmtag); 965 } 966 if (sc->fxp_txmtag) { 967 for (i = 0; i < FXP_NTXCB; i++) { 968 txp = &sc->fxp_desc.tx_list[i]; 969 if (txp->tx_mbuf != NULL) { 970 bus_dmamap_sync(sc->fxp_txmtag, txp->tx_map, 971 BUS_DMASYNC_POSTWRITE); 972 bus_dmamap_unload(sc->fxp_txmtag, txp->tx_map); 973 m_freem(txp->tx_mbuf); 974 } 975 bus_dmamap_destroy(sc->fxp_txmtag, txp->tx_map); 976 } 977 bus_dma_tag_destroy(sc->fxp_txmtag); 978 } 979 if (sc->fxp_stag) 980 bus_dma_tag_destroy(sc->fxp_stag); 981 if (sc->cbl_tag) 982 bus_dma_tag_destroy(sc->cbl_tag); 983 if (sc->mcs_tag) 984 bus_dma_tag_destroy(sc->mcs_tag); 985 if (sc->ifp) 986 if_free(sc->ifp); 987 988 mtx_destroy(&sc->sc_mtx); 989 } 990 991 /* 992 * Detach interface. 993 */ 994 static int 995 fxp_detach(device_t dev) 996 { 997 struct fxp_softc *sc = device_get_softc(dev); 998 999 #ifdef DEVICE_POLLING 1000 if (if_getcapenable(sc->ifp) & IFCAP_POLLING) 1001 ether_poll_deregister(sc->ifp); 1002 #endif 1003 1004 FXP_LOCK(sc); 1005 /* 1006 * Stop DMA and drop transmit queue, but disable interrupts first. 1007 */ 1008 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE); 1009 fxp_stop(sc); 1010 FXP_UNLOCK(sc); 1011 callout_drain(&sc->stat_ch); 1012 1013 /* 1014 * Close down routes etc. 1015 */ 1016 ether_ifdetach(sc->ifp); 1017 1018 /* 1019 * Unhook interrupt before dropping lock. This is to prevent 1020 * races with fxp_intr(). 1021 */ 1022 bus_teardown_intr(sc->dev, sc->fxp_res[1], sc->ih); 1023 sc->ih = NULL; 1024 1025 /* Release our allocated resources. */ 1026 fxp_release(sc); 1027 return (0); 1028 } 1029 1030 /* 1031 * Device shutdown routine. Called at system shutdown after sync. The 1032 * main purpose of this routine is to shut off receiver DMA so that 1033 * kernel memory doesn't get clobbered during warmboot. 1034 */ 1035 static int 1036 fxp_shutdown(device_t dev) 1037 { 1038 1039 /* 1040 * Make sure that DMA is disabled prior to reboot. Not doing 1041 * do could allow DMA to corrupt kernel memory during the 1042 * reboot before the driver initializes. 1043 */ 1044 return (fxp_suspend(dev)); 1045 } 1046 1047 /* 1048 * Device suspend routine. Stop the interface and save some PCI 1049 * settings in case the BIOS doesn't restore them properly on 1050 * resume. 1051 */ 1052 static int 1053 fxp_suspend(device_t dev) 1054 { 1055 struct fxp_softc *sc = device_get_softc(dev); 1056 if_t ifp; 1057 int pmc; 1058 uint16_t pmstat; 1059 1060 FXP_LOCK(sc); 1061 1062 ifp = sc->ifp; 1063 if (pci_find_cap(sc->dev, PCIY_PMG, &pmc) == 0) { 1064 pmstat = pci_read_config(sc->dev, pmc + PCIR_POWER_STATUS, 2); 1065 pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE); 1066 if ((if_getcapenable(ifp) & IFCAP_WOL_MAGIC) != 0) { 1067 /* Request PME. */ 1068 pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE; 1069 sc->flags |= FXP_FLAG_WOL; 1070 /* Reconfigure hardware to accept magic frames. */ 1071 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 1072 fxp_init_body(sc, 0); 1073 } 1074 pci_write_config(sc->dev, pmc + PCIR_POWER_STATUS, pmstat, 2); 1075 } 1076 fxp_stop(sc); 1077 1078 sc->suspended = 1; 1079 1080 FXP_UNLOCK(sc); 1081 return (0); 1082 } 1083 1084 /* 1085 * Device resume routine. re-enable busmastering, and restart the interface if 1086 * appropriate. 1087 */ 1088 static int 1089 fxp_resume(device_t dev) 1090 { 1091 struct fxp_softc *sc = device_get_softc(dev); 1092 if_t ifp = sc->ifp; 1093 int pmc; 1094 uint16_t pmstat; 1095 1096 FXP_LOCK(sc); 1097 1098 if (pci_find_cap(sc->dev, PCIY_PMG, &pmc) == 0) { 1099 sc->flags &= ~FXP_FLAG_WOL; 1100 pmstat = pci_read_config(sc->dev, pmc + PCIR_POWER_STATUS, 2); 1101 /* Disable PME and clear PME status. */ 1102 pmstat &= ~PCIM_PSTAT_PMEENABLE; 1103 pci_write_config(sc->dev, pmc + PCIR_POWER_STATUS, pmstat, 2); 1104 if ((sc->flags & FXP_FLAG_WOLCAP) != 0) 1105 CSR_WRITE_1(sc, FXP_CSR_PMDR, 1106 CSR_READ_1(sc, FXP_CSR_PMDR)); 1107 } 1108 1109 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET); 1110 DELAY(10); 1111 1112 /* reinitialize interface if necessary */ 1113 if (if_getflags(ifp) & IFF_UP) 1114 fxp_init_body(sc, 1); 1115 1116 sc->suspended = 0; 1117 1118 FXP_UNLOCK(sc); 1119 return (0); 1120 } 1121 1122 static void 1123 fxp_eeprom_shiftin(struct fxp_softc *sc, int data, int length) 1124 { 1125 uint16_t reg; 1126 int x; 1127 1128 /* 1129 * Shift in data. 1130 */ 1131 for (x = 1 << (length - 1); x; x >>= 1) { 1132 if (data & x) 1133 reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI; 1134 else 1135 reg = FXP_EEPROM_EECS; 1136 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 1137 DELAY(1); 1138 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK); 1139 DELAY(1); 1140 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 1141 DELAY(1); 1142 } 1143 } 1144 1145 /* 1146 * Read from the serial EEPROM. Basically, you manually shift in 1147 * the read opcode (one bit at a time) and then shift in the address, 1148 * and then you shift out the data (all of this one bit at a time). 1149 * The word size is 16 bits, so you have to provide the address for 1150 * every 16 bits of data. 1151 */ 1152 static uint16_t 1153 fxp_eeprom_getword(struct fxp_softc *sc, int offset, int autosize) 1154 { 1155 uint16_t reg, data; 1156 int x; 1157 1158 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 1159 /* 1160 * Shift in read opcode. 1161 */ 1162 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_READ, 3); 1163 /* 1164 * Shift in address. 1165 */ 1166 data = 0; 1167 for (x = 1 << (sc->eeprom_size - 1); x; x >>= 1) { 1168 if (offset & x) 1169 reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI; 1170 else 1171 reg = FXP_EEPROM_EECS; 1172 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 1173 DELAY(1); 1174 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK); 1175 DELAY(1); 1176 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 1177 DELAY(1); 1178 reg = CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO; 1179 data++; 1180 if (autosize && reg == 0) { 1181 sc->eeprom_size = data; 1182 break; 1183 } 1184 } 1185 /* 1186 * Shift out data. 1187 */ 1188 data = 0; 1189 reg = FXP_EEPROM_EECS; 1190 for (x = 1 << 15; x; x >>= 1) { 1191 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK); 1192 DELAY(1); 1193 if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO) 1194 data |= x; 1195 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 1196 DELAY(1); 1197 } 1198 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 1199 DELAY(1); 1200 1201 return (data); 1202 } 1203 1204 static void 1205 fxp_eeprom_putword(struct fxp_softc *sc, int offset, uint16_t data) 1206 { 1207 int i; 1208 1209 /* 1210 * Erase/write enable. 1211 */ 1212 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 1213 fxp_eeprom_shiftin(sc, 0x4, 3); 1214 fxp_eeprom_shiftin(sc, 0x03 << (sc->eeprom_size - 2), sc->eeprom_size); 1215 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 1216 DELAY(1); 1217 /* 1218 * Shift in write opcode, address, data. 1219 */ 1220 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 1221 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_WRITE, 3); 1222 fxp_eeprom_shiftin(sc, offset, sc->eeprom_size); 1223 fxp_eeprom_shiftin(sc, data, 16); 1224 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 1225 DELAY(1); 1226 /* 1227 * Wait for EEPROM to finish up. 1228 */ 1229 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 1230 DELAY(1); 1231 for (i = 0; i < 1000; i++) { 1232 if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO) 1233 break; 1234 DELAY(50); 1235 } 1236 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 1237 DELAY(1); 1238 /* 1239 * Erase/write disable. 1240 */ 1241 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 1242 fxp_eeprom_shiftin(sc, 0x4, 3); 1243 fxp_eeprom_shiftin(sc, 0, sc->eeprom_size); 1244 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 1245 DELAY(1); 1246 } 1247 1248 /* 1249 * From NetBSD: 1250 * 1251 * Figure out EEPROM size. 1252 * 1253 * 559's can have either 64-word or 256-word EEPROMs, the 558 1254 * datasheet only talks about 64-word EEPROMs, and the 557 datasheet 1255 * talks about the existence of 16 to 256 word EEPROMs. 1256 * 1257 * The only known sizes are 64 and 256, where the 256 version is used 1258 * by CardBus cards to store CIS information. 1259 * 1260 * The address is shifted in msb-to-lsb, and after the last 1261 * address-bit the EEPROM is supposed to output a `dummy zero' bit, 1262 * after which follows the actual data. We try to detect this zero, by 1263 * probing the data-out bit in the EEPROM control register just after 1264 * having shifted in a bit. If the bit is zero, we assume we've 1265 * shifted enough address bits. The data-out should be tri-state, 1266 * before this, which should translate to a logical one. 1267 */ 1268 static void 1269 fxp_autosize_eeprom(struct fxp_softc *sc) 1270 { 1271 1272 /* guess maximum size of 256 words */ 1273 sc->eeprom_size = 8; 1274 1275 /* autosize */ 1276 (void) fxp_eeprom_getword(sc, 0, 1); 1277 } 1278 1279 static void 1280 fxp_read_eeprom(struct fxp_softc *sc, u_short *data, int offset, int words) 1281 { 1282 int i; 1283 1284 for (i = 0; i < words; i++) 1285 data[i] = fxp_eeprom_getword(sc, offset + i, 0); 1286 } 1287 1288 static void 1289 fxp_write_eeprom(struct fxp_softc *sc, u_short *data, int offset, int words) 1290 { 1291 int i; 1292 1293 for (i = 0; i < words; i++) 1294 fxp_eeprom_putword(sc, offset + i, data[i]); 1295 } 1296 1297 static void 1298 fxp_load_eeprom(struct fxp_softc *sc) 1299 { 1300 int i; 1301 uint16_t cksum; 1302 1303 fxp_read_eeprom(sc, sc->eeprom, 0, 1 << sc->eeprom_size); 1304 cksum = 0; 1305 for (i = 0; i < (1 << sc->eeprom_size) - 1; i++) 1306 cksum += sc->eeprom[i]; 1307 cksum = 0xBABA - cksum; 1308 if (cksum != sc->eeprom[(1 << sc->eeprom_size) - 1]) 1309 device_printf(sc->dev, 1310 "EEPROM checksum mismatch! (0x%04x -> 0x%04x)\n", 1311 cksum, sc->eeprom[(1 << sc->eeprom_size) - 1]); 1312 } 1313 1314 /* 1315 * Grab the softc lock and call the real fxp_start_body() routine 1316 */ 1317 static void 1318 fxp_start(if_t ifp) 1319 { 1320 struct fxp_softc *sc = if_getsoftc(ifp); 1321 1322 FXP_LOCK(sc); 1323 fxp_start_body(ifp); 1324 FXP_UNLOCK(sc); 1325 } 1326 1327 /* 1328 * Start packet transmission on the interface. 1329 * This routine must be called with the softc lock held, and is an 1330 * internal entry point only. 1331 */ 1332 static void 1333 fxp_start_body(if_t ifp) 1334 { 1335 struct fxp_softc *sc = if_getsoftc(ifp); 1336 struct mbuf *mb_head; 1337 int txqueued; 1338 1339 FXP_LOCK_ASSERT(sc, MA_OWNED); 1340 1341 if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 1342 IFF_DRV_RUNNING) 1343 return; 1344 1345 if (sc->tx_queued > FXP_NTXCB_HIWAT) 1346 fxp_txeof(sc); 1347 /* 1348 * We're finished if there is nothing more to add to the list or if 1349 * we're all filled up with buffers to transmit. 1350 * NOTE: One TxCB is reserved to guarantee that fxp_mc_setup() can add 1351 * a NOP command when needed. 1352 */ 1353 txqueued = 0; 1354 while (!if_sendq_empty(ifp) && sc->tx_queued < FXP_NTXCB - 1) { 1355 1356 /* 1357 * Grab a packet to transmit. 1358 */ 1359 mb_head = if_dequeue(ifp); 1360 if (mb_head == NULL) 1361 break; 1362 1363 if (fxp_encap(sc, &mb_head)) { 1364 if (mb_head == NULL) 1365 break; 1366 if_sendq_prepend(ifp, mb_head); 1367 if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, 0); 1368 } 1369 txqueued++; 1370 /* 1371 * Pass packet to bpf if there is a listener. 1372 */ 1373 bpf_mtap_if(ifp, mb_head); 1374 } 1375 1376 /* 1377 * We're finished. If we added to the list, issue a RESUME to get DMA 1378 * going again if suspended. 1379 */ 1380 if (txqueued > 0) { 1381 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, 1382 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1383 fxp_scb_wait(sc); 1384 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_RESUME); 1385 /* 1386 * Set a 5 second timer just in case we don't hear 1387 * from the card again. 1388 */ 1389 sc->watchdog_timer = 5; 1390 } 1391 } 1392 1393 static int 1394 fxp_encap(struct fxp_softc *sc, struct mbuf **m_head) 1395 { 1396 struct mbuf *m; 1397 struct fxp_tx *txp; 1398 struct fxp_cb_tx *cbp; 1399 struct tcphdr *tcp; 1400 bus_dma_segment_t segs[FXP_NTXSEG]; 1401 int error, i, nseg, tcp_payload; 1402 1403 FXP_LOCK_ASSERT(sc, MA_OWNED); 1404 1405 tcp_payload = 0; 1406 tcp = NULL; 1407 /* 1408 * Get pointer to next available tx desc. 1409 */ 1410 txp = sc->fxp_desc.tx_last->tx_next; 1411 1412 /* 1413 * A note in Appendix B of the Intel 8255x 10/100 Mbps 1414 * Ethernet Controller Family Open Source Software 1415 * Developer Manual says: 1416 * Using software parsing is only allowed with legal 1417 * TCP/IP or UDP/IP packets. 1418 * ... 1419 * For all other datagrams, hardware parsing must 1420 * be used. 1421 * Software parsing appears to truncate ICMP and 1422 * fragmented UDP packets that contain one to three 1423 * bytes in the second (and final) mbuf of the packet. 1424 */ 1425 if (sc->flags & FXP_FLAG_EXT_RFA) 1426 txp->tx_cb->ipcb_ip_activation_high = 1427 FXP_IPCB_HARDWAREPARSING_ENABLE; 1428 1429 m = *m_head; 1430 if (m->m_pkthdr.csum_flags & CSUM_TSO) { 1431 /* 1432 * 82550/82551 requires ethernet/IP/TCP headers must be 1433 * contained in the first active transmit buffer. 1434 */ 1435 struct ether_header *eh; 1436 struct ip *ip; 1437 uint32_t ip_off, poff; 1438 1439 if (M_WRITABLE(*m_head) == 0) { 1440 /* Get a writable copy. */ 1441 m = m_dup(*m_head, M_NOWAIT); 1442 m_freem(*m_head); 1443 if (m == NULL) { 1444 *m_head = NULL; 1445 return (ENOBUFS); 1446 } 1447 *m_head = m; 1448 } 1449 ip_off = sizeof(struct ether_header); 1450 m = m_pullup(*m_head, ip_off); 1451 if (m == NULL) { 1452 *m_head = NULL; 1453 return (ENOBUFS); 1454 } 1455 eh = mtod(m, struct ether_header *); 1456 /* Check the existence of VLAN tag. */ 1457 if (eh->ether_type == htons(ETHERTYPE_VLAN)) { 1458 ip_off = sizeof(struct ether_vlan_header); 1459 m = m_pullup(m, ip_off); 1460 if (m == NULL) { 1461 *m_head = NULL; 1462 return (ENOBUFS); 1463 } 1464 } 1465 m = m_pullup(m, ip_off + sizeof(struct ip)); 1466 if (m == NULL) { 1467 *m_head = NULL; 1468 return (ENOBUFS); 1469 } 1470 ip = (struct ip *)(mtod(m, char *) + ip_off); 1471 poff = ip_off + (ip->ip_hl << 2); 1472 m = m_pullup(m, poff + sizeof(struct tcphdr)); 1473 if (m == NULL) { 1474 *m_head = NULL; 1475 return (ENOBUFS); 1476 } 1477 tcp = (struct tcphdr *)(mtod(m, char *) + poff); 1478 m = m_pullup(m, poff + (tcp->th_off << 2)); 1479 if (m == NULL) { 1480 *m_head = NULL; 1481 return (ENOBUFS); 1482 } 1483 1484 /* 1485 * Since 82550/82551 doesn't modify IP length and pseudo 1486 * checksum in the first frame driver should compute it. 1487 */ 1488 ip = (struct ip *)(mtod(m, char *) + ip_off); 1489 tcp = (struct tcphdr *)(mtod(m, char *) + poff); 1490 ip->ip_sum = 0; 1491 ip->ip_len = htons(m->m_pkthdr.tso_segsz + (ip->ip_hl << 2) + 1492 (tcp->th_off << 2)); 1493 tcp->th_sum = in_pseudo(ip->ip_src.s_addr, ip->ip_dst.s_addr, 1494 htons(IPPROTO_TCP + (tcp->th_off << 2) + 1495 m->m_pkthdr.tso_segsz)); 1496 /* Compute total TCP payload. */ 1497 tcp_payload = m->m_pkthdr.len - ip_off - (ip->ip_hl << 2); 1498 tcp_payload -= tcp->th_off << 2; 1499 *m_head = m; 1500 } else if (m->m_pkthdr.csum_flags & FXP_CSUM_FEATURES) { 1501 /* 1502 * Deal with TCP/IP checksum offload. Note that 1503 * in order for TCP checksum offload to work, 1504 * the pseudo header checksum must have already 1505 * been computed and stored in the checksum field 1506 * in the TCP header. The stack should have 1507 * already done this for us. 1508 */ 1509 txp->tx_cb->ipcb_ip_schedule = FXP_IPCB_TCPUDP_CHECKSUM_ENABLE; 1510 if (m->m_pkthdr.csum_flags & CSUM_TCP) 1511 txp->tx_cb->ipcb_ip_schedule |= FXP_IPCB_TCP_PACKET; 1512 1513 #ifdef FXP_IP_CSUM_WAR 1514 /* 1515 * XXX The 82550 chip appears to have trouble 1516 * dealing with IP header checksums in very small 1517 * datagrams, namely fragments from 1 to 3 bytes 1518 * in size. For example, say you want to transmit 1519 * a UDP packet of 1473 bytes. The packet will be 1520 * fragmented over two IP datagrams, the latter 1521 * containing only one byte of data. The 82550 will 1522 * botch the header checksum on the 1-byte fragment. 1523 * As long as the datagram contains 4 or more bytes 1524 * of data, you're ok. 1525 * 1526 * The following code attempts to work around this 1527 * problem: if the datagram is less than 38 bytes 1528 * in size (14 bytes ether header, 20 bytes IP header, 1529 * plus 4 bytes of data), we punt and compute the IP 1530 * header checksum by hand. This workaround doesn't 1531 * work very well, however, since it can be fooled 1532 * by things like VLAN tags and IP options that make 1533 * the header sizes/offsets vary. 1534 */ 1535 1536 if (m->m_pkthdr.csum_flags & CSUM_IP) { 1537 if (m->m_pkthdr.len < 38) { 1538 struct ip *ip; 1539 m->m_data += ETHER_HDR_LEN; 1540 ip = mtod(m, struct ip *); 1541 ip->ip_sum = in_cksum(m, ip->ip_hl << 2); 1542 m->m_data -= ETHER_HDR_LEN; 1543 m->m_pkthdr.csum_flags &= ~CSUM_IP; 1544 } else { 1545 txp->tx_cb->ipcb_ip_activation_high = 1546 FXP_IPCB_HARDWAREPARSING_ENABLE; 1547 txp->tx_cb->ipcb_ip_schedule |= 1548 FXP_IPCB_IP_CHECKSUM_ENABLE; 1549 } 1550 } 1551 #endif 1552 } 1553 1554 error = bus_dmamap_load_mbuf_sg(sc->fxp_txmtag, txp->tx_map, *m_head, 1555 segs, &nseg, 0); 1556 if (error == EFBIG) { 1557 m = m_collapse(*m_head, M_NOWAIT, sc->maxtxseg); 1558 if (m == NULL) { 1559 m_freem(*m_head); 1560 *m_head = NULL; 1561 return (ENOMEM); 1562 } 1563 *m_head = m; 1564 error = bus_dmamap_load_mbuf_sg(sc->fxp_txmtag, txp->tx_map, 1565 *m_head, segs, &nseg, 0); 1566 if (error != 0) { 1567 m_freem(*m_head); 1568 *m_head = NULL; 1569 return (ENOMEM); 1570 } 1571 } else if (error != 0) 1572 return (error); 1573 if (nseg == 0) { 1574 m_freem(*m_head); 1575 *m_head = NULL; 1576 return (EIO); 1577 } 1578 1579 KASSERT(nseg <= sc->maxtxseg, ("too many DMA segments")); 1580 bus_dmamap_sync(sc->fxp_txmtag, txp->tx_map, BUS_DMASYNC_PREWRITE); 1581 1582 cbp = txp->tx_cb; 1583 for (i = 0; i < nseg; i++) { 1584 /* 1585 * If this is an 82550/82551, then we're using extended 1586 * TxCBs _and_ we're using checksum offload. This means 1587 * that the TxCB is really an IPCB. One major difference 1588 * between the two is that with plain extended TxCBs, 1589 * the bottom half of the TxCB contains two entries from 1590 * the TBD array, whereas IPCBs contain just one entry: 1591 * one entry (8 bytes) has been sacrificed for the TCP/IP 1592 * checksum offload control bits. So to make things work 1593 * right, we have to start filling in the TBD array 1594 * starting from a different place depending on whether 1595 * the chip is an 82550/82551 or not. 1596 */ 1597 if (sc->flags & FXP_FLAG_EXT_RFA) { 1598 cbp->tbd[i + 1].tb_addr = htole32(segs[i].ds_addr); 1599 cbp->tbd[i + 1].tb_size = htole32(segs[i].ds_len); 1600 } else { 1601 cbp->tbd[i].tb_addr = htole32(segs[i].ds_addr); 1602 cbp->tbd[i].tb_size = htole32(segs[i].ds_len); 1603 } 1604 } 1605 if (sc->flags & FXP_FLAG_EXT_RFA) { 1606 /* Configure dynamic TBD for 82550/82551. */ 1607 cbp->tbd_number = 0xFF; 1608 cbp->tbd[nseg].tb_size |= htole32(0x8000); 1609 } else 1610 cbp->tbd_number = nseg; 1611 /* Configure TSO. */ 1612 if (m->m_pkthdr.csum_flags & CSUM_TSO) { 1613 cbp->tbdtso.tb_size = htole32(m->m_pkthdr.tso_segsz << 16); 1614 cbp->tbd[1].tb_size |= htole32(tcp_payload << 16); 1615 cbp->ipcb_ip_schedule |= FXP_IPCB_LARGESEND_ENABLE | 1616 FXP_IPCB_IP_CHECKSUM_ENABLE | 1617 FXP_IPCB_TCP_PACKET | 1618 FXP_IPCB_TCPUDP_CHECKSUM_ENABLE; 1619 } 1620 /* Configure VLAN hardware tag insertion. */ 1621 if ((m->m_flags & M_VLANTAG) != 0) { 1622 cbp->ipcb_vlan_id = htons(m->m_pkthdr.ether_vtag); 1623 txp->tx_cb->ipcb_ip_activation_high |= 1624 FXP_IPCB_INSERTVLAN_ENABLE; 1625 } 1626 1627 txp->tx_mbuf = m; 1628 txp->tx_cb->cb_status = 0; 1629 txp->tx_cb->byte_count = 0; 1630 if (sc->tx_queued != FXP_CXINT_THRESH - 1) 1631 txp->tx_cb->cb_command = 1632 htole16(sc->tx_cmd | FXP_CB_COMMAND_SF | 1633 FXP_CB_COMMAND_S); 1634 else 1635 txp->tx_cb->cb_command = 1636 htole16(sc->tx_cmd | FXP_CB_COMMAND_SF | 1637 FXP_CB_COMMAND_S | FXP_CB_COMMAND_I); 1638 if ((m->m_pkthdr.csum_flags & CSUM_TSO) == 0) 1639 txp->tx_cb->tx_threshold = tx_threshold; 1640 1641 /* 1642 * Advance the end of list forward. 1643 */ 1644 sc->fxp_desc.tx_last->tx_cb->cb_command &= htole16(~FXP_CB_COMMAND_S); 1645 sc->fxp_desc.tx_last = txp; 1646 1647 /* 1648 * Advance the beginning of the list forward if there are 1649 * no other packets queued (when nothing is queued, tx_first 1650 * sits on the last TxCB that was sent out). 1651 */ 1652 if (sc->tx_queued == 0) 1653 sc->fxp_desc.tx_first = txp; 1654 1655 sc->tx_queued++; 1656 1657 return (0); 1658 } 1659 1660 #ifdef DEVICE_POLLING 1661 static poll_handler_t fxp_poll; 1662 1663 static int 1664 fxp_poll(if_t ifp, enum poll_cmd cmd, int count) 1665 { 1666 struct fxp_softc *sc = if_getsoftc(ifp); 1667 uint8_t statack; 1668 int rx_npkts = 0; 1669 1670 FXP_LOCK(sc); 1671 if (!(if_getdrvflags(ifp) & IFF_DRV_RUNNING)) { 1672 FXP_UNLOCK(sc); 1673 return (rx_npkts); 1674 } 1675 1676 statack = FXP_SCB_STATACK_CXTNO | FXP_SCB_STATACK_CNA | 1677 FXP_SCB_STATACK_FR; 1678 if (cmd == POLL_AND_CHECK_STATUS) { 1679 uint8_t tmp; 1680 1681 tmp = CSR_READ_1(sc, FXP_CSR_SCB_STATACK); 1682 if (tmp == 0xff || tmp == 0) { 1683 FXP_UNLOCK(sc); 1684 return (rx_npkts); /* nothing to do */ 1685 } 1686 tmp &= ~statack; 1687 /* ack what we can */ 1688 if (tmp != 0) 1689 CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, tmp); 1690 statack |= tmp; 1691 } 1692 rx_npkts = fxp_intr_body(sc, ifp, statack, count); 1693 FXP_UNLOCK(sc); 1694 return (rx_npkts); 1695 } 1696 #endif /* DEVICE_POLLING */ 1697 1698 /* 1699 * Process interface interrupts. 1700 */ 1701 static void 1702 fxp_intr(void *xsc) 1703 { 1704 struct fxp_softc *sc = xsc; 1705 if_t ifp = sc->ifp; 1706 uint8_t statack; 1707 1708 FXP_LOCK(sc); 1709 if (sc->suspended) { 1710 FXP_UNLOCK(sc); 1711 return; 1712 } 1713 1714 #ifdef DEVICE_POLLING 1715 if (if_getcapenable(ifp) & IFCAP_POLLING) { 1716 FXP_UNLOCK(sc); 1717 return; 1718 } 1719 #endif 1720 while ((statack = CSR_READ_1(sc, FXP_CSR_SCB_STATACK)) != 0) { 1721 /* 1722 * It should not be possible to have all bits set; the 1723 * FXP_SCB_INTR_SWI bit always returns 0 on a read. If 1724 * all bits are set, this may indicate that the card has 1725 * been physically ejected, so ignore it. 1726 */ 1727 if (statack == 0xff) { 1728 FXP_UNLOCK(sc); 1729 return; 1730 } 1731 1732 /* 1733 * First ACK all the interrupts in this pass. 1734 */ 1735 CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, statack); 1736 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) 1737 fxp_intr_body(sc, ifp, statack, -1); 1738 } 1739 FXP_UNLOCK(sc); 1740 } 1741 1742 static void 1743 fxp_txeof(struct fxp_softc *sc) 1744 { 1745 if_t ifp; 1746 struct fxp_tx *txp; 1747 1748 ifp = sc->ifp; 1749 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, 1750 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1751 for (txp = sc->fxp_desc.tx_first; sc->tx_queued && 1752 (le16toh(txp->tx_cb->cb_status) & FXP_CB_STATUS_C) != 0; 1753 txp = txp->tx_next) { 1754 if (txp->tx_mbuf != NULL) { 1755 bus_dmamap_sync(sc->fxp_txmtag, txp->tx_map, 1756 BUS_DMASYNC_POSTWRITE); 1757 bus_dmamap_unload(sc->fxp_txmtag, txp->tx_map); 1758 m_freem(txp->tx_mbuf); 1759 txp->tx_mbuf = NULL; 1760 /* clear this to reset csum offload bits */ 1761 txp->tx_cb->tbd[0].tb_addr = 0; 1762 } 1763 sc->tx_queued--; 1764 if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE); 1765 } 1766 sc->fxp_desc.tx_first = txp; 1767 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, 1768 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1769 if (sc->tx_queued == 0) 1770 sc->watchdog_timer = 0; 1771 } 1772 1773 static void 1774 fxp_rxcsum(struct fxp_softc *sc, if_t ifp, struct mbuf *m, 1775 uint16_t status, int pos) 1776 { 1777 struct ether_header *eh; 1778 struct ip *ip; 1779 struct udphdr *uh; 1780 int32_t hlen, len, pktlen, temp32; 1781 uint16_t csum, *opts; 1782 1783 if ((sc->flags & FXP_FLAG_82559_RXCSUM) == 0) { 1784 if ((status & FXP_RFA_STATUS_PARSE) != 0) { 1785 if (status & FXP_RFDX_CS_IP_CSUM_BIT_VALID) 1786 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 1787 if (status & FXP_RFDX_CS_IP_CSUM_VALID) 1788 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 1789 if ((status & FXP_RFDX_CS_TCPUDP_CSUM_BIT_VALID) && 1790 (status & FXP_RFDX_CS_TCPUDP_CSUM_VALID)) { 1791 m->m_pkthdr.csum_flags |= CSUM_DATA_VALID | 1792 CSUM_PSEUDO_HDR; 1793 m->m_pkthdr.csum_data = 0xffff; 1794 } 1795 } 1796 return; 1797 } 1798 1799 pktlen = m->m_pkthdr.len; 1800 if (pktlen < sizeof(struct ether_header) + sizeof(struct ip)) 1801 return; 1802 eh = mtod(m, struct ether_header *); 1803 if (eh->ether_type != htons(ETHERTYPE_IP)) 1804 return; 1805 ip = (struct ip *)(eh + 1); 1806 if (ip->ip_v != IPVERSION) 1807 return; 1808 1809 hlen = ip->ip_hl << 2; 1810 pktlen -= sizeof(struct ether_header); 1811 if (hlen < sizeof(struct ip)) 1812 return; 1813 if (ntohs(ip->ip_len) < hlen) 1814 return; 1815 if (ntohs(ip->ip_len) != pktlen) 1816 return; 1817 if (ip->ip_off & htons(IP_MF | IP_OFFMASK)) 1818 return; /* can't handle fragmented packet */ 1819 1820 switch (ip->ip_p) { 1821 case IPPROTO_TCP: 1822 if (pktlen < (hlen + sizeof(struct tcphdr))) 1823 return; 1824 break; 1825 case IPPROTO_UDP: 1826 if (pktlen < (hlen + sizeof(struct udphdr))) 1827 return; 1828 uh = (struct udphdr *)((caddr_t)ip + hlen); 1829 if (uh->uh_sum == 0) 1830 return; /* no checksum */ 1831 break; 1832 default: 1833 return; 1834 } 1835 /* Extract computed checksum. */ 1836 csum = be16dec(mtod(m, char *) + pos); 1837 /* checksum fixup for IP options */ 1838 len = hlen - sizeof(struct ip); 1839 if (len > 0) { 1840 opts = (uint16_t *)(ip + 1); 1841 for (; len > 0; len -= sizeof(uint16_t), opts++) { 1842 temp32 = csum - *opts; 1843 temp32 = (temp32 >> 16) + (temp32 & 65535); 1844 csum = temp32 & 65535; 1845 } 1846 } 1847 m->m_pkthdr.csum_flags |= CSUM_DATA_VALID; 1848 m->m_pkthdr.csum_data = csum; 1849 } 1850 1851 static int 1852 fxp_intr_body(struct fxp_softc *sc, if_t ifp, uint8_t statack, 1853 int count) 1854 { 1855 struct mbuf *m; 1856 struct fxp_rx *rxp; 1857 struct fxp_rfa *rfa; 1858 int rnr = (statack & FXP_SCB_STATACK_RNR) ? 1 : 0; 1859 int rx_npkts; 1860 uint16_t status; 1861 1862 rx_npkts = 0; 1863 FXP_LOCK_ASSERT(sc, MA_OWNED); 1864 1865 if (rnr) 1866 sc->rnr++; 1867 #ifdef DEVICE_POLLING 1868 /* Pick up a deferred RNR condition if `count' ran out last time. */ 1869 if (sc->flags & FXP_FLAG_DEFERRED_RNR) { 1870 sc->flags &= ~FXP_FLAG_DEFERRED_RNR; 1871 rnr = 1; 1872 } 1873 #endif 1874 1875 /* 1876 * Free any finished transmit mbuf chains. 1877 * 1878 * Handle the CNA event likt a CXTNO event. It used to 1879 * be that this event (control unit not ready) was not 1880 * encountered, but it is now with the SMPng modifications. 1881 * The exact sequence of events that occur when the interface 1882 * is brought up are different now, and if this event 1883 * goes unhandled, the configuration/rxfilter setup sequence 1884 * can stall for several seconds. The result is that no 1885 * packets go out onto the wire for about 5 to 10 seconds 1886 * after the interface is ifconfig'ed for the first time. 1887 */ 1888 if (statack & (FXP_SCB_STATACK_CXTNO | FXP_SCB_STATACK_CNA)) 1889 fxp_txeof(sc); 1890 1891 /* 1892 * Try to start more packets transmitting. 1893 */ 1894 if (!if_sendq_empty(ifp)) 1895 fxp_start_body(ifp); 1896 1897 /* 1898 * Just return if nothing happened on the receive side. 1899 */ 1900 if (!rnr && (statack & FXP_SCB_STATACK_FR) == 0) 1901 return (rx_npkts); 1902 1903 /* 1904 * Process receiver interrupts. If a no-resource (RNR) 1905 * condition exists, get whatever packets we can and 1906 * re-start the receiver. 1907 * 1908 * When using polling, we do not process the list to completion, 1909 * so when we get an RNR interrupt we must defer the restart 1910 * until we hit the last buffer with the C bit set. 1911 * If we run out of cycles and rfa_headm has the C bit set, 1912 * record the pending RNR in the FXP_FLAG_DEFERRED_RNR flag so 1913 * that the info will be used in the subsequent polling cycle. 1914 */ 1915 for (;;) { 1916 rxp = sc->fxp_desc.rx_head; 1917 m = rxp->rx_mbuf; 1918 rfa = (struct fxp_rfa *)(m->m_ext.ext_buf + 1919 RFA_ALIGNMENT_FUDGE); 1920 bus_dmamap_sync(sc->fxp_rxmtag, rxp->rx_map, 1921 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1922 1923 #ifdef DEVICE_POLLING /* loop at most count times if count >=0 */ 1924 if (count >= 0 && count-- == 0) { 1925 if (rnr) { 1926 /* Defer RNR processing until the next time. */ 1927 sc->flags |= FXP_FLAG_DEFERRED_RNR; 1928 rnr = 0; 1929 } 1930 break; 1931 } 1932 #endif /* DEVICE_POLLING */ 1933 1934 status = le16toh(rfa->rfa_status); 1935 if ((status & FXP_RFA_STATUS_C) == 0) 1936 break; 1937 1938 if ((status & FXP_RFA_STATUS_RNR) != 0) 1939 rnr++; 1940 /* 1941 * Advance head forward. 1942 */ 1943 sc->fxp_desc.rx_head = rxp->rx_next; 1944 1945 /* 1946 * Add a new buffer to the receive chain. 1947 * If this fails, the old buffer is recycled 1948 * instead. 1949 */ 1950 if (fxp_new_rfabuf(sc, rxp) == 0) { 1951 int total_len; 1952 1953 /* 1954 * Fetch packet length (the top 2 bits of 1955 * actual_size are flags set by the controller 1956 * upon completion), and drop the packet in case 1957 * of bogus length or CRC errors. 1958 */ 1959 total_len = le16toh(rfa->actual_size) & 0x3fff; 1960 if ((sc->flags & FXP_FLAG_82559_RXCSUM) != 0 && 1961 (if_getcapenable(ifp) & IFCAP_RXCSUM) != 0) { 1962 /* Adjust for appended checksum bytes. */ 1963 total_len -= 2; 1964 } 1965 if (total_len < (int)sizeof(struct ether_header) || 1966 total_len > (MCLBYTES - RFA_ALIGNMENT_FUDGE - 1967 sc->rfa_size) || 1968 status & (FXP_RFA_STATUS_CRC | 1969 FXP_RFA_STATUS_ALIGN | FXP_RFA_STATUS_OVERRUN)) { 1970 m_freem(m); 1971 fxp_add_rfabuf(sc, rxp); 1972 continue; 1973 } 1974 1975 m->m_pkthdr.len = m->m_len = total_len; 1976 if_setrcvif(m, ifp); 1977 1978 /* Do IP checksum checking. */ 1979 if ((if_getcapenable(ifp) & IFCAP_RXCSUM) != 0) 1980 fxp_rxcsum(sc, ifp, m, status, total_len); 1981 if ((if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING) != 0 && 1982 (status & FXP_RFA_STATUS_VLAN) != 0) { 1983 m->m_pkthdr.ether_vtag = 1984 ntohs(rfa->rfax_vlan_id); 1985 m->m_flags |= M_VLANTAG; 1986 } 1987 /* 1988 * Drop locks before calling if_input() since it 1989 * may re-enter fxp_start() in the netisr case. 1990 * This would result in a lock reversal. Better 1991 * performance might be obtained by chaining all 1992 * packets received, dropping the lock, and then 1993 * calling if_input() on each one. 1994 */ 1995 FXP_UNLOCK(sc); 1996 if_input(ifp, m); 1997 FXP_LOCK(sc); 1998 rx_npkts++; 1999 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) == 0) 2000 return (rx_npkts); 2001 } else { 2002 /* Reuse RFA and loaded DMA map. */ 2003 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1); 2004 fxp_discard_rfabuf(sc, rxp); 2005 } 2006 fxp_add_rfabuf(sc, rxp); 2007 } 2008 if (rnr) { 2009 fxp_scb_wait(sc); 2010 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 2011 sc->fxp_desc.rx_head->rx_addr); 2012 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_START); 2013 } 2014 return (rx_npkts); 2015 } 2016 2017 static void 2018 fxp_update_stats(struct fxp_softc *sc) 2019 { 2020 if_t ifp = sc->ifp; 2021 struct fxp_stats *sp = sc->fxp_stats; 2022 struct fxp_hwstats *hsp; 2023 uint32_t *status; 2024 2025 FXP_LOCK_ASSERT(sc, MA_OWNED); 2026 2027 bus_dmamap_sync(sc->fxp_stag, sc->fxp_smap, 2028 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2029 /* Update statistical counters. */ 2030 if (sc->revision >= FXP_REV_82559_A0) 2031 status = &sp->completion_status; 2032 else if (sc->revision >= FXP_REV_82558_A4) 2033 status = (uint32_t *)&sp->tx_tco; 2034 else 2035 status = &sp->tx_pause; 2036 if (*status == htole32(FXP_STATS_DR_COMPLETE)) { 2037 hsp = &sc->fxp_hwstats; 2038 hsp->tx_good += le32toh(sp->tx_good); 2039 hsp->tx_maxcols += le32toh(sp->tx_maxcols); 2040 hsp->tx_latecols += le32toh(sp->tx_latecols); 2041 hsp->tx_underruns += le32toh(sp->tx_underruns); 2042 hsp->tx_lostcrs += le32toh(sp->tx_lostcrs); 2043 hsp->tx_deffered += le32toh(sp->tx_deffered); 2044 hsp->tx_single_collisions += le32toh(sp->tx_single_collisions); 2045 hsp->tx_multiple_collisions += 2046 le32toh(sp->tx_multiple_collisions); 2047 hsp->tx_total_collisions += le32toh(sp->tx_total_collisions); 2048 hsp->rx_good += le32toh(sp->rx_good); 2049 hsp->rx_crc_errors += le32toh(sp->rx_crc_errors); 2050 hsp->rx_alignment_errors += le32toh(sp->rx_alignment_errors); 2051 hsp->rx_rnr_errors += le32toh(sp->rx_rnr_errors); 2052 hsp->rx_overrun_errors += le32toh(sp->rx_overrun_errors); 2053 hsp->rx_cdt_errors += le32toh(sp->rx_cdt_errors); 2054 hsp->rx_shortframes += le32toh(sp->rx_shortframes); 2055 hsp->tx_pause += le32toh(sp->tx_pause); 2056 hsp->rx_pause += le32toh(sp->rx_pause); 2057 hsp->rx_controls += le32toh(sp->rx_controls); 2058 hsp->tx_tco += le16toh(sp->tx_tco); 2059 hsp->rx_tco += le16toh(sp->rx_tco); 2060 2061 if_inc_counter(ifp, IFCOUNTER_OPACKETS, le32toh(sp->tx_good)); 2062 if_inc_counter(ifp, IFCOUNTER_COLLISIONS, 2063 le32toh(sp->tx_total_collisions)); 2064 if (sp->rx_good) { 2065 if_inc_counter(ifp, IFCOUNTER_IPACKETS, 2066 le32toh(sp->rx_good)); 2067 sc->rx_idle_secs = 0; 2068 } else if (sc->flags & FXP_FLAG_RXBUG) { 2069 /* 2070 * Receiver's been idle for another second. 2071 */ 2072 sc->rx_idle_secs++; 2073 } 2074 if_inc_counter(ifp, IFCOUNTER_IERRORS, 2075 le32toh(sp->rx_crc_errors) + 2076 le32toh(sp->rx_alignment_errors) + 2077 le32toh(sp->rx_rnr_errors) + 2078 le32toh(sp->rx_overrun_errors)); 2079 /* 2080 * If any transmit underruns occurred, bump up the transmit 2081 * threshold by another 512 bytes (64 * 8). 2082 */ 2083 if (sp->tx_underruns) { 2084 if_inc_counter(ifp, IFCOUNTER_OERRORS, 2085 le32toh(sp->tx_underruns)); 2086 if (tx_threshold < 192) 2087 tx_threshold += 64; 2088 } 2089 *status = 0; 2090 bus_dmamap_sync(sc->fxp_stag, sc->fxp_smap, 2091 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2092 } 2093 } 2094 2095 /* 2096 * Update packet in/out/collision statistics. The i82557 doesn't 2097 * allow you to access these counters without doing a fairly 2098 * expensive DMA to get _all_ of the statistics it maintains, so 2099 * we do this operation here only once per second. The statistics 2100 * counters in the kernel are updated from the previous dump-stats 2101 * DMA and then a new dump-stats DMA is started. The on-chip 2102 * counters are zeroed when the DMA completes. If we can't start 2103 * the DMA immediately, we don't wait - we just prepare to read 2104 * them again next time. 2105 */ 2106 static void 2107 fxp_tick(void *xsc) 2108 { 2109 struct fxp_softc *sc = xsc; 2110 if_t ifp = sc->ifp; 2111 2112 FXP_LOCK_ASSERT(sc, MA_OWNED); 2113 2114 /* Update statistical counters. */ 2115 fxp_update_stats(sc); 2116 2117 /* 2118 * Release any xmit buffers that have completed DMA. This isn't 2119 * strictly necessary to do here, but it's advantagous for mbufs 2120 * with external storage to be released in a timely manner rather 2121 * than being defered for a potentially long time. This limits 2122 * the delay to a maximum of one second. 2123 */ 2124 fxp_txeof(sc); 2125 2126 /* 2127 * If we haven't received any packets in FXP_MAC_RX_IDLE seconds, 2128 * then assume the receiver has locked up and attempt to clear 2129 * the condition by reprogramming the multicast filter. This is 2130 * a work-around for a bug in the 82557 where the receiver locks 2131 * up if it gets certain types of garbage in the synchronization 2132 * bits prior to the packet header. This bug is supposed to only 2133 * occur in 10Mbps mode, but has been seen to occur in 100Mbps 2134 * mode as well (perhaps due to a 10/100 speed transition). 2135 */ 2136 if (sc->rx_idle_secs > FXP_MAX_RX_IDLE) { 2137 sc->rx_idle_secs = 0; 2138 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) { 2139 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 2140 fxp_init_body(sc, 1); 2141 } 2142 return; 2143 } 2144 /* 2145 * If there is no pending command, start another stats 2146 * dump. Otherwise punt for now. 2147 */ 2148 if (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) == 0) { 2149 /* 2150 * Start another stats dump. 2151 */ 2152 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_DUMPRESET); 2153 } 2154 if (sc->miibus != NULL) 2155 mii_tick(device_get_softc(sc->miibus)); 2156 2157 /* 2158 * Check that chip hasn't hung. 2159 */ 2160 fxp_watchdog(sc); 2161 2162 /* 2163 * Schedule another timeout one second from now. 2164 */ 2165 callout_reset(&sc->stat_ch, hz, fxp_tick, sc); 2166 } 2167 2168 /* 2169 * Stop the interface. Cancels the statistics updater and resets 2170 * the interface. 2171 */ 2172 static void 2173 fxp_stop(struct fxp_softc *sc) 2174 { 2175 if_t ifp = sc->ifp; 2176 struct fxp_tx *txp; 2177 int i; 2178 2179 if_setdrvflagbits(ifp, 0, (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)); 2180 sc->watchdog_timer = 0; 2181 2182 /* 2183 * Cancel stats updater. 2184 */ 2185 callout_stop(&sc->stat_ch); 2186 2187 /* 2188 * Preserve PCI configuration, configure, IA/multicast 2189 * setup and put RU and CU into idle state. 2190 */ 2191 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET); 2192 DELAY(50); 2193 /* Disable interrupts. */ 2194 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE); 2195 2196 fxp_update_stats(sc); 2197 2198 /* 2199 * Release any xmit buffers. 2200 */ 2201 txp = sc->fxp_desc.tx_list; 2202 for (i = 0; i < FXP_NTXCB; i++) { 2203 if (txp[i].tx_mbuf != NULL) { 2204 bus_dmamap_sync(sc->fxp_txmtag, txp[i].tx_map, 2205 BUS_DMASYNC_POSTWRITE); 2206 bus_dmamap_unload(sc->fxp_txmtag, txp[i].tx_map); 2207 m_freem(txp[i].tx_mbuf); 2208 txp[i].tx_mbuf = NULL; 2209 /* clear this to reset csum offload bits */ 2210 txp[i].tx_cb->tbd[0].tb_addr = 0; 2211 } 2212 } 2213 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, 2214 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2215 sc->tx_queued = 0; 2216 } 2217 2218 /* 2219 * Watchdog/transmission transmit timeout handler. Called when a 2220 * transmission is started on the interface, but no interrupt is 2221 * received before the timeout. This usually indicates that the 2222 * card has wedged for some reason. 2223 */ 2224 static void 2225 fxp_watchdog(struct fxp_softc *sc) 2226 { 2227 if_t ifp = sc->ifp; 2228 2229 FXP_LOCK_ASSERT(sc, MA_OWNED); 2230 2231 if (sc->watchdog_timer == 0 || --sc->watchdog_timer) 2232 return; 2233 2234 device_printf(sc->dev, "device timeout\n"); 2235 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 2236 2237 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 2238 fxp_init_body(sc, 1); 2239 } 2240 2241 /* 2242 * Acquire locks and then call the real initialization function. This 2243 * is necessary because ether_ioctl() calls if_init() and this would 2244 * result in mutex recursion if the mutex was held. 2245 */ 2246 static void 2247 fxp_init(void *xsc) 2248 { 2249 struct fxp_softc *sc = xsc; 2250 2251 FXP_LOCK(sc); 2252 fxp_init_body(sc, 1); 2253 FXP_UNLOCK(sc); 2254 } 2255 2256 /* 2257 * Perform device initialization. This routine must be called with the 2258 * softc lock held. 2259 */ 2260 static void 2261 fxp_init_body(struct fxp_softc *sc, int setmedia) 2262 { 2263 if_t ifp = sc->ifp; 2264 struct mii_data *mii; 2265 struct fxp_cb_config *cbp; 2266 struct fxp_cb_ias *cb_ias; 2267 struct fxp_cb_tx *tcbp; 2268 struct fxp_tx *txp; 2269 int i, prm; 2270 2271 FXP_LOCK_ASSERT(sc, MA_OWNED); 2272 2273 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) 2274 return; 2275 2276 /* 2277 * Cancel any pending I/O 2278 */ 2279 fxp_stop(sc); 2280 2281 /* 2282 * Issue software reset, which also unloads the microcode. 2283 */ 2284 sc->flags &= ~FXP_FLAG_UCODE; 2285 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SOFTWARE_RESET); 2286 DELAY(50); 2287 2288 prm = (if_getflags(ifp) & IFF_PROMISC) ? 1 : 0; 2289 2290 /* 2291 * Initialize base of CBL and RFA memory. Loading with zero 2292 * sets it up for regular linear addressing. 2293 */ 2294 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 0); 2295 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_BASE); 2296 2297 fxp_scb_wait(sc); 2298 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_BASE); 2299 2300 /* 2301 * Initialize base of dump-stats buffer. 2302 */ 2303 fxp_scb_wait(sc); 2304 bzero(sc->fxp_stats, sizeof(struct fxp_stats)); 2305 bus_dmamap_sync(sc->fxp_stag, sc->fxp_smap, 2306 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2307 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->stats_addr); 2308 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_DUMP_ADR); 2309 2310 /* 2311 * Attempt to load microcode if requested. 2312 * For ICH based controllers do not load microcode. 2313 */ 2314 if (sc->ident->ich == 0) { 2315 if (if_getflags(ifp) & IFF_LINK0 && 2316 (sc->flags & FXP_FLAG_UCODE) == 0) 2317 fxp_load_ucode(sc); 2318 } 2319 2320 /* 2321 * Set IFF_ALLMULTI status. It's needed in configure action 2322 * command. 2323 */ 2324 fxp_mc_addrs(sc); 2325 2326 /* 2327 * We temporarily use memory that contains the TxCB list to 2328 * construct the config CB. The TxCB list memory is rebuilt 2329 * later. 2330 */ 2331 cbp = (struct fxp_cb_config *)sc->fxp_desc.cbl_list; 2332 2333 /* 2334 * This bcopy is kind of disgusting, but there are a bunch of must be 2335 * zero and must be one bits in this structure and this is the easiest 2336 * way to initialize them all to proper values. 2337 */ 2338 bcopy(fxp_cb_config_template, cbp, sizeof(fxp_cb_config_template)); 2339 2340 cbp->cb_status = 0; 2341 cbp->cb_command = htole16(FXP_CB_COMMAND_CONFIG | 2342 FXP_CB_COMMAND_EL); 2343 cbp->link_addr = 0xffffffff; /* (no) next command */ 2344 cbp->byte_count = sc->flags & FXP_FLAG_EXT_RFA ? 32 : 22; 2345 cbp->rx_fifo_limit = 8; /* rx fifo threshold (32 bytes) */ 2346 cbp->tx_fifo_limit = 0; /* tx fifo threshold (0 bytes) */ 2347 cbp->adaptive_ifs = 0; /* (no) adaptive interframe spacing */ 2348 cbp->mwi_enable = sc->flags & FXP_FLAG_MWI_ENABLE ? 1 : 0; 2349 cbp->type_enable = 0; /* actually reserved */ 2350 cbp->read_align_en = sc->flags & FXP_FLAG_READ_ALIGN ? 1 : 0; 2351 cbp->end_wr_on_cl = sc->flags & FXP_FLAG_WRITE_ALIGN ? 1 : 0; 2352 cbp->rx_dma_bytecount = 0; /* (no) rx DMA max */ 2353 cbp->tx_dma_bytecount = 0; /* (no) tx DMA max */ 2354 cbp->dma_mbce = 0; /* (disable) dma max counters */ 2355 cbp->late_scb = 0; /* (don't) defer SCB update */ 2356 cbp->direct_dma_dis = 1; /* disable direct rcv dma mode */ 2357 cbp->tno_int_or_tco_en =0; /* (disable) tx not okay interrupt */ 2358 cbp->ci_int = 1; /* interrupt on CU idle */ 2359 cbp->ext_txcb_dis = sc->flags & FXP_FLAG_EXT_TXCB ? 0 : 1; 2360 cbp->ext_stats_dis = 1; /* disable extended counters */ 2361 cbp->keep_overrun_rx = 0; /* don't pass overrun frames to host */ 2362 cbp->save_bf = sc->flags & FXP_FLAG_SAVE_BAD ? 1 : prm; 2363 cbp->disc_short_rx = !prm; /* discard short packets */ 2364 cbp->underrun_retry = 1; /* retry mode (once) on DMA underrun */ 2365 cbp->two_frames = 0; /* do not limit FIFO to 2 frames */ 2366 cbp->dyn_tbd = sc->flags & FXP_FLAG_EXT_RFA ? 1 : 0; 2367 cbp->ext_rfa = sc->flags & FXP_FLAG_EXT_RFA ? 1 : 0; 2368 cbp->mediatype = sc->flags & FXP_FLAG_SERIAL_MEDIA ? 0 : 1; 2369 cbp->csma_dis = 0; /* (don't) disable link */ 2370 cbp->tcp_udp_cksum = ((sc->flags & FXP_FLAG_82559_RXCSUM) != 0 && 2371 (if_getcapenable(ifp) & IFCAP_RXCSUM) != 0) ? 1 : 0; 2372 cbp->vlan_tco = 0; /* (don't) enable vlan wakeup */ 2373 cbp->link_wake_en = 0; /* (don't) assert PME# on link change */ 2374 cbp->arp_wake_en = 0; /* (don't) assert PME# on arp */ 2375 cbp->mc_wake_en = 0; /* (don't) enable PME# on mcmatch */ 2376 cbp->nsai = 1; /* (don't) disable source addr insert */ 2377 cbp->preamble_length = 2; /* (7 byte) preamble */ 2378 cbp->loopback = 0; /* (don't) loopback */ 2379 cbp->linear_priority = 0; /* (normal CSMA/CD operation) */ 2380 cbp->linear_pri_mode = 0; /* (wait after xmit only) */ 2381 cbp->interfrm_spacing = 6; /* (96 bits of) interframe spacing */ 2382 cbp->promiscuous = prm; /* promiscuous mode */ 2383 cbp->bcast_disable = 0; /* (don't) disable broadcasts */ 2384 cbp->wait_after_win = 0; /* (don't) enable modified backoff alg*/ 2385 cbp->ignore_ul = 0; /* consider U/L bit in IA matching */ 2386 cbp->crc16_en = 0; /* (don't) enable crc-16 algorithm */ 2387 cbp->crscdt = sc->flags & FXP_FLAG_SERIAL_MEDIA ? 1 : 0; 2388 2389 cbp->stripping = !prm; /* truncate rx packet to byte count */ 2390 cbp->padding = 1; /* (do) pad short tx packets */ 2391 cbp->rcv_crc_xfer = 0; /* (don't) xfer CRC to host */ 2392 cbp->long_rx_en = sc->flags & FXP_FLAG_LONG_PKT_EN ? 1 : 0; 2393 cbp->ia_wake_en = 0; /* (don't) wake up on address match */ 2394 cbp->magic_pkt_dis = sc->flags & FXP_FLAG_WOL ? 0 : 1; 2395 cbp->force_fdx = 0; /* (don't) force full duplex */ 2396 cbp->fdx_pin_en = 1; /* (enable) FDX# pin */ 2397 cbp->multi_ia = 0; /* (don't) accept multiple IAs */ 2398 cbp->mc_all = if_getflags(ifp) & IFF_ALLMULTI ? 1 : prm; 2399 cbp->gamla_rx = sc->flags & FXP_FLAG_EXT_RFA ? 1 : 0; 2400 cbp->vlan_strip_en = ((sc->flags & FXP_FLAG_EXT_RFA) != 0 && 2401 (if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING) != 0) ? 1 : 0; 2402 2403 if (sc->revision == FXP_REV_82557) { 2404 /* 2405 * The 82557 has no hardware flow control, the values 2406 * below are the defaults for the chip. 2407 */ 2408 cbp->fc_delay_lsb = 0; 2409 cbp->fc_delay_msb = 0x40; 2410 cbp->pri_fc_thresh = 3; 2411 cbp->tx_fc_dis = 0; 2412 cbp->rx_fc_restop = 0; 2413 cbp->rx_fc_restart = 0; 2414 cbp->fc_filter = 0; 2415 cbp->pri_fc_loc = 1; 2416 } else { 2417 /* Set pause RX FIFO threshold to 1KB. */ 2418 CSR_WRITE_1(sc, FXP_CSR_FC_THRESH, 1); 2419 /* Set pause time. */ 2420 cbp->fc_delay_lsb = 0xff; 2421 cbp->fc_delay_msb = 0xff; 2422 cbp->pri_fc_thresh = 3; 2423 mii = device_get_softc(sc->miibus); 2424 if ((IFM_OPTIONS(mii->mii_media_active) & 2425 IFM_ETH_TXPAUSE) != 0) 2426 /* enable transmit FC */ 2427 cbp->tx_fc_dis = 0; 2428 else 2429 /* disable transmit FC */ 2430 cbp->tx_fc_dis = 1; 2431 if ((IFM_OPTIONS(mii->mii_media_active) & 2432 IFM_ETH_RXPAUSE) != 0) { 2433 /* enable FC restart/restop frames */ 2434 cbp->rx_fc_restart = 1; 2435 cbp->rx_fc_restop = 1; 2436 } else { 2437 /* disable FC restart/restop frames */ 2438 cbp->rx_fc_restart = 0; 2439 cbp->rx_fc_restop = 0; 2440 } 2441 cbp->fc_filter = !prm; /* drop FC frames to host */ 2442 cbp->pri_fc_loc = 1; /* FC pri location (byte31) */ 2443 } 2444 2445 /* Enable 82558 and 82559 extended statistics functionality. */ 2446 if (sc->revision >= FXP_REV_82558_A4) { 2447 if (sc->revision >= FXP_REV_82559_A0) { 2448 /* 2449 * Extend configuration table size to 32 2450 * to include TCO configuration. 2451 */ 2452 cbp->byte_count = 32; 2453 cbp->ext_stats_dis = 1; 2454 /* Enable TCO stats. */ 2455 cbp->tno_int_or_tco_en = 1; 2456 cbp->gamla_rx = 1; 2457 } else 2458 cbp->ext_stats_dis = 0; 2459 } 2460 2461 /* 2462 * Start the config command/DMA. 2463 */ 2464 fxp_scb_wait(sc); 2465 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, 2466 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2467 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->fxp_desc.cbl_addr); 2468 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2469 /* ...and wait for it to complete. */ 2470 fxp_dma_wait(sc, &cbp->cb_status, sc->cbl_tag, sc->cbl_map); 2471 2472 /* 2473 * Now initialize the station address. Temporarily use the TxCB 2474 * memory area like we did above for the config CB. 2475 */ 2476 cb_ias = (struct fxp_cb_ias *)sc->fxp_desc.cbl_list; 2477 cb_ias->cb_status = 0; 2478 cb_ias->cb_command = htole16(FXP_CB_COMMAND_IAS | FXP_CB_COMMAND_EL); 2479 cb_ias->link_addr = 0xffffffff; 2480 bcopy(if_getlladdr(sc->ifp), cb_ias->macaddr, ETHER_ADDR_LEN); 2481 2482 /* 2483 * Start the IAS (Individual Address Setup) command/DMA. 2484 */ 2485 fxp_scb_wait(sc); 2486 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, 2487 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2488 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->fxp_desc.cbl_addr); 2489 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2490 /* ...and wait for it to complete. */ 2491 fxp_dma_wait(sc, &cb_ias->cb_status, sc->cbl_tag, sc->cbl_map); 2492 2493 /* 2494 * Initialize the multicast address list. 2495 */ 2496 fxp_mc_setup(sc); 2497 2498 /* 2499 * Initialize transmit control block (TxCB) list. 2500 */ 2501 txp = sc->fxp_desc.tx_list; 2502 tcbp = sc->fxp_desc.cbl_list; 2503 bzero(tcbp, FXP_TXCB_SZ); 2504 for (i = 0; i < FXP_NTXCB; i++) { 2505 txp[i].tx_mbuf = NULL; 2506 tcbp[i].cb_status = htole16(FXP_CB_STATUS_C | FXP_CB_STATUS_OK); 2507 tcbp[i].cb_command = htole16(FXP_CB_COMMAND_NOP); 2508 tcbp[i].link_addr = htole32(sc->fxp_desc.cbl_addr + 2509 (((i + 1) & FXP_TXCB_MASK) * sizeof(struct fxp_cb_tx))); 2510 if (sc->flags & FXP_FLAG_EXT_TXCB) 2511 tcbp[i].tbd_array_addr = 2512 htole32(FXP_TXCB_DMA_ADDR(sc, &tcbp[i].tbd[2])); 2513 else 2514 tcbp[i].tbd_array_addr = 2515 htole32(FXP_TXCB_DMA_ADDR(sc, &tcbp[i].tbd[0])); 2516 txp[i].tx_next = &txp[(i + 1) & FXP_TXCB_MASK]; 2517 } 2518 /* 2519 * Set the suspend flag on the first TxCB and start the control 2520 * unit. It will execute the NOP and then suspend. 2521 */ 2522 tcbp->cb_command = htole16(FXP_CB_COMMAND_NOP | FXP_CB_COMMAND_S); 2523 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, 2524 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2525 sc->fxp_desc.tx_first = sc->fxp_desc.tx_last = txp; 2526 sc->tx_queued = 1; 2527 2528 fxp_scb_wait(sc); 2529 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->fxp_desc.cbl_addr); 2530 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2531 2532 /* 2533 * Initialize receiver buffer area - RFA. 2534 */ 2535 fxp_scb_wait(sc); 2536 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->fxp_desc.rx_head->rx_addr); 2537 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_START); 2538 2539 if (sc->miibus != NULL && setmedia != 0) 2540 mii_mediachg(device_get_softc(sc->miibus)); 2541 2542 if_setdrvflagbits(ifp, IFF_DRV_RUNNING, IFF_DRV_OACTIVE); 2543 2544 /* 2545 * Enable interrupts. 2546 */ 2547 #ifdef DEVICE_POLLING 2548 /* 2549 * ... but only do that if we are not polling. And because (presumably) 2550 * the default is interrupts on, we need to disable them explicitly! 2551 */ 2552 if (if_getcapenable(ifp) & IFCAP_POLLING ) 2553 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE); 2554 else 2555 #endif /* DEVICE_POLLING */ 2556 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, 0); 2557 2558 /* 2559 * Start stats updater. 2560 */ 2561 callout_reset(&sc->stat_ch, hz, fxp_tick, sc); 2562 } 2563 2564 static int 2565 fxp_serial_ifmedia_upd(if_t ifp) 2566 { 2567 2568 return (0); 2569 } 2570 2571 static void 2572 fxp_serial_ifmedia_sts(if_t ifp, struct ifmediareq *ifmr) 2573 { 2574 2575 ifmr->ifm_active = IFM_ETHER|IFM_MANUAL; 2576 } 2577 2578 /* 2579 * Change media according to request. 2580 */ 2581 static int 2582 fxp_ifmedia_upd(if_t ifp) 2583 { 2584 struct fxp_softc *sc = if_getsoftc(ifp); 2585 struct mii_data *mii; 2586 struct mii_softc *miisc; 2587 2588 mii = device_get_softc(sc->miibus); 2589 FXP_LOCK(sc); 2590 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 2591 PHY_RESET(miisc); 2592 mii_mediachg(mii); 2593 FXP_UNLOCK(sc); 2594 return (0); 2595 } 2596 2597 /* 2598 * Notify the world which media we're using. 2599 */ 2600 static void 2601 fxp_ifmedia_sts(if_t ifp, struct ifmediareq *ifmr) 2602 { 2603 struct fxp_softc *sc = if_getsoftc(ifp); 2604 struct mii_data *mii; 2605 2606 mii = device_get_softc(sc->miibus); 2607 FXP_LOCK(sc); 2608 mii_pollstat(mii); 2609 ifmr->ifm_active = mii->mii_media_active; 2610 ifmr->ifm_status = mii->mii_media_status; 2611 FXP_UNLOCK(sc); 2612 } 2613 2614 /* 2615 * Add a buffer to the end of the RFA buffer list. 2616 * Return 0 if successful, 1 for failure. A failure results in 2617 * reusing the RFA buffer. 2618 * The RFA struct is stuck at the beginning of mbuf cluster and the 2619 * data pointer is fixed up to point just past it. 2620 */ 2621 static int 2622 fxp_new_rfabuf(struct fxp_softc *sc, struct fxp_rx *rxp) 2623 { 2624 struct mbuf *m; 2625 struct fxp_rfa *rfa; 2626 bus_dmamap_t tmp_map; 2627 int error; 2628 2629 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 2630 if (m == NULL) 2631 return (ENOBUFS); 2632 2633 /* 2634 * Move the data pointer up so that the incoming data packet 2635 * will be 32-bit aligned. 2636 */ 2637 m->m_data += RFA_ALIGNMENT_FUDGE; 2638 2639 /* 2640 * Get a pointer to the base of the mbuf cluster and move 2641 * data start past it. 2642 */ 2643 rfa = mtod(m, struct fxp_rfa *); 2644 m->m_data += sc->rfa_size; 2645 rfa->size = htole16(MCLBYTES - sc->rfa_size - RFA_ALIGNMENT_FUDGE); 2646 2647 rfa->rfa_status = 0; 2648 rfa->rfa_control = htole16(FXP_RFA_CONTROL_EL); 2649 rfa->actual_size = 0; 2650 m->m_len = m->m_pkthdr.len = MCLBYTES - RFA_ALIGNMENT_FUDGE - 2651 sc->rfa_size; 2652 2653 /* 2654 * Initialize the rest of the RFA. Note that since the RFA 2655 * is misaligned, we cannot store values directly. We're thus 2656 * using the le32enc() function which handles endianness and 2657 * is also alignment-safe. 2658 */ 2659 le32enc(&rfa->link_addr, 0xffffffff); 2660 le32enc(&rfa->rbd_addr, 0xffffffff); 2661 2662 /* Map the RFA into DMA memory. */ 2663 error = bus_dmamap_load(sc->fxp_rxmtag, sc->spare_map, rfa, 2664 MCLBYTES - RFA_ALIGNMENT_FUDGE, fxp_dma_map_addr, 2665 &rxp->rx_addr, BUS_DMA_NOWAIT); 2666 if (error) { 2667 m_freem(m); 2668 return (error); 2669 } 2670 2671 if (rxp->rx_mbuf != NULL) 2672 bus_dmamap_unload(sc->fxp_rxmtag, rxp->rx_map); 2673 tmp_map = sc->spare_map; 2674 sc->spare_map = rxp->rx_map; 2675 rxp->rx_map = tmp_map; 2676 rxp->rx_mbuf = m; 2677 2678 bus_dmamap_sync(sc->fxp_rxmtag, rxp->rx_map, 2679 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2680 return (0); 2681 } 2682 2683 static void 2684 fxp_add_rfabuf(struct fxp_softc *sc, struct fxp_rx *rxp) 2685 { 2686 struct fxp_rfa *p_rfa; 2687 struct fxp_rx *p_rx; 2688 2689 /* 2690 * If there are other buffers already on the list, attach this 2691 * one to the end by fixing up the tail to point to this one. 2692 */ 2693 if (sc->fxp_desc.rx_head != NULL) { 2694 p_rx = sc->fxp_desc.rx_tail; 2695 p_rfa = (struct fxp_rfa *) 2696 (p_rx->rx_mbuf->m_ext.ext_buf + RFA_ALIGNMENT_FUDGE); 2697 p_rx->rx_next = rxp; 2698 le32enc(&p_rfa->link_addr, rxp->rx_addr); 2699 p_rfa->rfa_control = 0; 2700 bus_dmamap_sync(sc->fxp_rxmtag, p_rx->rx_map, 2701 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2702 } else { 2703 rxp->rx_next = NULL; 2704 sc->fxp_desc.rx_head = rxp; 2705 } 2706 sc->fxp_desc.rx_tail = rxp; 2707 } 2708 2709 static void 2710 fxp_discard_rfabuf(struct fxp_softc *sc, struct fxp_rx *rxp) 2711 { 2712 struct mbuf *m; 2713 struct fxp_rfa *rfa; 2714 2715 m = rxp->rx_mbuf; 2716 m->m_data = m->m_ext.ext_buf; 2717 /* 2718 * Move the data pointer up so that the incoming data packet 2719 * will be 32-bit aligned. 2720 */ 2721 m->m_data += RFA_ALIGNMENT_FUDGE; 2722 2723 /* 2724 * Get a pointer to the base of the mbuf cluster and move 2725 * data start past it. 2726 */ 2727 rfa = mtod(m, struct fxp_rfa *); 2728 m->m_data += sc->rfa_size; 2729 rfa->size = htole16(MCLBYTES - sc->rfa_size - RFA_ALIGNMENT_FUDGE); 2730 2731 rfa->rfa_status = 0; 2732 rfa->rfa_control = htole16(FXP_RFA_CONTROL_EL); 2733 rfa->actual_size = 0; 2734 2735 /* 2736 * Initialize the rest of the RFA. Note that since the RFA 2737 * is misaligned, we cannot store values directly. We're thus 2738 * using the le32enc() function which handles endianness and 2739 * is also alignment-safe. 2740 */ 2741 le32enc(&rfa->link_addr, 0xffffffff); 2742 le32enc(&rfa->rbd_addr, 0xffffffff); 2743 2744 bus_dmamap_sync(sc->fxp_rxmtag, rxp->rx_map, 2745 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2746 } 2747 2748 static int 2749 fxp_miibus_readreg(device_t dev, int phy, int reg) 2750 { 2751 struct fxp_softc *sc = device_get_softc(dev); 2752 int count = 10000; 2753 int value; 2754 2755 CSR_WRITE_4(sc, FXP_CSR_MDICONTROL, 2756 (FXP_MDI_READ << 26) | (reg << 16) | (phy << 21)); 2757 2758 while (((value = CSR_READ_4(sc, FXP_CSR_MDICONTROL)) & 0x10000000) == 0 2759 && count--) 2760 DELAY(10); 2761 2762 if (count <= 0) 2763 device_printf(dev, "fxp_miibus_readreg: timed out\n"); 2764 2765 return (value & 0xffff); 2766 } 2767 2768 static int 2769 fxp_miibus_writereg(device_t dev, int phy, int reg, int value) 2770 { 2771 struct fxp_softc *sc = device_get_softc(dev); 2772 int count = 10000; 2773 2774 CSR_WRITE_4(sc, FXP_CSR_MDICONTROL, 2775 (FXP_MDI_WRITE << 26) | (reg << 16) | (phy << 21) | 2776 (value & 0xffff)); 2777 2778 while ((CSR_READ_4(sc, FXP_CSR_MDICONTROL) & 0x10000000) == 0 && 2779 count--) 2780 DELAY(10); 2781 2782 if (count <= 0) 2783 device_printf(dev, "fxp_miibus_writereg: timed out\n"); 2784 return (0); 2785 } 2786 2787 static void 2788 fxp_miibus_statchg(device_t dev) 2789 { 2790 struct fxp_softc *sc; 2791 struct mii_data *mii; 2792 if_t ifp; 2793 2794 sc = device_get_softc(dev); 2795 mii = device_get_softc(sc->miibus); 2796 ifp = sc->ifp; 2797 if (mii == NULL || ifp == (void *)NULL || 2798 (if_getdrvflags(ifp) & IFF_DRV_RUNNING) == 0 || 2799 (mii->mii_media_status & (IFM_AVALID | IFM_ACTIVE)) != 2800 (IFM_AVALID | IFM_ACTIVE)) 2801 return; 2802 2803 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_10_T && 2804 sc->flags & FXP_FLAG_CU_RESUME_BUG) 2805 sc->cu_resume_bug = 1; 2806 else 2807 sc->cu_resume_bug = 0; 2808 /* 2809 * Call fxp_init_body in order to adjust the flow control settings. 2810 * Note that the 82557 doesn't support hardware flow control. 2811 */ 2812 if (sc->revision == FXP_REV_82557) 2813 return; 2814 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 2815 fxp_init_body(sc, 0); 2816 } 2817 2818 static int 2819 fxp_ioctl(if_t ifp, u_long command, caddr_t data) 2820 { 2821 struct fxp_softc *sc = if_getsoftc(ifp); 2822 struct ifreq *ifr = (struct ifreq *)data; 2823 struct mii_data *mii; 2824 int flag, mask, error = 0, reinit; 2825 2826 switch (command) { 2827 case SIOCSIFFLAGS: 2828 FXP_LOCK(sc); 2829 /* 2830 * If interface is marked up and not running, then start it. 2831 * If it is marked down and running, stop it. 2832 * XXX If it's up then re-initialize it. This is so flags 2833 * such as IFF_PROMISC are handled. 2834 */ 2835 if (if_getflags(ifp) & IFF_UP) { 2836 if (((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) && 2837 ((if_getflags(ifp) ^ sc->if_flags) & 2838 (IFF_PROMISC | IFF_ALLMULTI | IFF_LINK0)) != 0) { 2839 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 2840 fxp_init_body(sc, 0); 2841 } else if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) == 0) 2842 fxp_init_body(sc, 1); 2843 } else { 2844 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) 2845 fxp_stop(sc); 2846 } 2847 sc->if_flags = if_getflags(ifp); 2848 FXP_UNLOCK(sc); 2849 break; 2850 2851 case SIOCADDMULTI: 2852 case SIOCDELMULTI: 2853 FXP_LOCK(sc); 2854 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) { 2855 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 2856 fxp_init_body(sc, 0); 2857 } 2858 FXP_UNLOCK(sc); 2859 break; 2860 2861 case SIOCSIFMEDIA: 2862 case SIOCGIFMEDIA: 2863 if (sc->miibus != NULL) { 2864 mii = device_get_softc(sc->miibus); 2865 error = ifmedia_ioctl(ifp, ifr, 2866 &mii->mii_media, command); 2867 } else { 2868 error = ifmedia_ioctl(ifp, ifr, &sc->sc_media, command); 2869 } 2870 break; 2871 2872 case SIOCSIFCAP: 2873 reinit = 0; 2874 mask = if_getcapenable(ifp) ^ ifr->ifr_reqcap; 2875 #ifdef DEVICE_POLLING 2876 if (mask & IFCAP_POLLING) { 2877 if (ifr->ifr_reqcap & IFCAP_POLLING) { 2878 error = ether_poll_register(fxp_poll, ifp); 2879 if (error) 2880 return(error); 2881 FXP_LOCK(sc); 2882 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, 2883 FXP_SCB_INTR_DISABLE); 2884 if_setcapenablebit(ifp, IFCAP_POLLING, 0); 2885 FXP_UNLOCK(sc); 2886 } else { 2887 error = ether_poll_deregister(ifp); 2888 /* Enable interrupts in any case */ 2889 FXP_LOCK(sc); 2890 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, 0); 2891 if_setcapenablebit(ifp, 0, IFCAP_POLLING); 2892 FXP_UNLOCK(sc); 2893 } 2894 } 2895 #endif 2896 FXP_LOCK(sc); 2897 if ((mask & IFCAP_TXCSUM) != 0 && 2898 (if_getcapabilities(ifp) & IFCAP_TXCSUM) != 0) { 2899 if_togglecapenable(ifp, IFCAP_TXCSUM); 2900 if ((if_getcapenable(ifp) & IFCAP_TXCSUM) != 0) 2901 if_sethwassistbits(ifp, FXP_CSUM_FEATURES, 0); 2902 else 2903 if_sethwassistbits(ifp, 0, FXP_CSUM_FEATURES); 2904 } 2905 if ((mask & IFCAP_RXCSUM) != 0 && 2906 (if_getcapabilities(ifp) & IFCAP_RXCSUM) != 0) { 2907 if_togglecapenable(ifp, IFCAP_RXCSUM); 2908 if ((sc->flags & FXP_FLAG_82559_RXCSUM) != 0) 2909 reinit++; 2910 } 2911 if ((mask & IFCAP_TSO4) != 0 && 2912 (if_getcapabilities(ifp) & IFCAP_TSO4) != 0) { 2913 if_togglecapenable(ifp, IFCAP_TSO4); 2914 if ((if_getcapenable(ifp) & IFCAP_TSO4) != 0) 2915 if_sethwassistbits(ifp, CSUM_TSO, 0); 2916 else 2917 if_sethwassistbits(ifp, 0, CSUM_TSO); 2918 } 2919 if ((mask & IFCAP_WOL_MAGIC) != 0 && 2920 (if_getcapabilities(ifp) & IFCAP_WOL_MAGIC) != 0) 2921 if_togglecapenable(ifp, IFCAP_WOL_MAGIC); 2922 if ((mask & IFCAP_VLAN_MTU) != 0 && 2923 (if_getcapabilities(ifp) & IFCAP_VLAN_MTU) != 0) { 2924 if_togglecapenable(ifp, IFCAP_VLAN_MTU); 2925 if (sc->revision != FXP_REV_82557) 2926 flag = FXP_FLAG_LONG_PKT_EN; 2927 else /* a hack to get long frames on the old chip */ 2928 flag = FXP_FLAG_SAVE_BAD; 2929 sc->flags ^= flag; 2930 if (if_getflags(ifp) & IFF_UP) 2931 reinit++; 2932 } 2933 if ((mask & IFCAP_VLAN_HWCSUM) != 0 && 2934 (if_getcapabilities(ifp) & IFCAP_VLAN_HWCSUM) != 0) 2935 if_togglecapenable(ifp, IFCAP_VLAN_HWCSUM); 2936 if ((mask & IFCAP_VLAN_HWTSO) != 0 && 2937 (if_getcapabilities(ifp) & IFCAP_VLAN_HWTSO) != 0) 2938 if_togglecapenable(ifp, IFCAP_VLAN_HWTSO); 2939 if ((mask & IFCAP_VLAN_HWTAGGING) != 0 && 2940 (if_getcapabilities(ifp) & IFCAP_VLAN_HWTAGGING) != 0) { 2941 if_togglecapenable(ifp, IFCAP_VLAN_HWTAGGING); 2942 if ((if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING) == 0) 2943 if_setcapenablebit(ifp, 0, IFCAP_VLAN_HWTSO | 2944 IFCAP_VLAN_HWCSUM); 2945 reinit++; 2946 } 2947 if (reinit > 0 && 2948 (if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) { 2949 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 2950 fxp_init_body(sc, 0); 2951 } 2952 FXP_UNLOCK(sc); 2953 if_vlancap(ifp); 2954 break; 2955 2956 default: 2957 error = ether_ioctl(ifp, command, data); 2958 } 2959 return (error); 2960 } 2961 2962 static u_int 2963 fxp_setup_maddr(void *arg, struct sockaddr_dl *sdl, u_int cnt) 2964 { 2965 struct fxp_softc *sc = arg; 2966 struct fxp_cb_mcs *mcsp = sc->mcsp; 2967 2968 if (mcsp->mc_cnt < MAXMCADDR) 2969 bcopy(LLADDR(sdl), mcsp->mc_addr[mcsp->mc_cnt * ETHER_ADDR_LEN], 2970 ETHER_ADDR_LEN); 2971 mcsp->mc_cnt++; 2972 return (1); 2973 } 2974 2975 /* 2976 * Fill in the multicast address list and return number of entries. 2977 */ 2978 static void 2979 fxp_mc_addrs(struct fxp_softc *sc) 2980 { 2981 struct fxp_cb_mcs *mcsp = sc->mcsp; 2982 if_t ifp = sc->ifp; 2983 2984 if ((if_getflags(ifp) & IFF_ALLMULTI) == 0) { 2985 mcsp->mc_cnt = 0; 2986 if_foreach_llmaddr(sc->ifp, fxp_setup_maddr, sc); 2987 if (mcsp->mc_cnt >= MAXMCADDR) { 2988 if_setflagbits(ifp, IFF_ALLMULTI, 0); 2989 mcsp->mc_cnt = 0; 2990 } 2991 } 2992 mcsp->mc_cnt = htole16(mcsp->mc_cnt * ETHER_ADDR_LEN); 2993 } 2994 2995 /* 2996 * Program the multicast filter. 2997 * 2998 * We have an artificial restriction that the multicast setup command 2999 * must be the first command in the chain, so we take steps to ensure 3000 * this. By requiring this, it allows us to keep up the performance of 3001 * the pre-initialized command ring (esp. link pointers) by not actually 3002 * inserting the mcsetup command in the ring - i.e. its link pointer 3003 * points to the TxCB ring, but the mcsetup descriptor itself is not part 3004 * of it. We then can do 'CU_START' on the mcsetup descriptor and have it 3005 * lead into the regular TxCB ring when it completes. 3006 */ 3007 static void 3008 fxp_mc_setup(struct fxp_softc *sc) 3009 { 3010 struct fxp_cb_mcs *mcsp; 3011 int count; 3012 3013 FXP_LOCK_ASSERT(sc, MA_OWNED); 3014 3015 mcsp = sc->mcsp; 3016 mcsp->cb_status = 0; 3017 mcsp->cb_command = htole16(FXP_CB_COMMAND_MCAS | FXP_CB_COMMAND_EL); 3018 mcsp->link_addr = 0xffffffff; 3019 fxp_mc_addrs(sc); 3020 3021 /* 3022 * Wait until command unit is idle. This should never be the 3023 * case when nothing is queued, but make sure anyway. 3024 */ 3025 count = 100; 3026 while ((CSR_READ_1(sc, FXP_CSR_SCB_RUSCUS) >> 6) != 3027 FXP_SCB_CUS_IDLE && --count) 3028 DELAY(10); 3029 if (count == 0) { 3030 device_printf(sc->dev, "command queue timeout\n"); 3031 return; 3032 } 3033 3034 /* 3035 * Start the multicast setup command. 3036 */ 3037 fxp_scb_wait(sc); 3038 bus_dmamap_sync(sc->mcs_tag, sc->mcs_map, 3039 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3040 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->mcs_addr); 3041 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 3042 /* ...and wait for it to complete. */ 3043 fxp_dma_wait(sc, &mcsp->cb_status, sc->mcs_tag, sc->mcs_map); 3044 } 3045 3046 static uint32_t fxp_ucode_d101a[] = D101_A_RCVBUNDLE_UCODE; 3047 static uint32_t fxp_ucode_d101b0[] = D101_B0_RCVBUNDLE_UCODE; 3048 static uint32_t fxp_ucode_d101ma[] = D101M_B_RCVBUNDLE_UCODE; 3049 static uint32_t fxp_ucode_d101s[] = D101S_RCVBUNDLE_UCODE; 3050 static uint32_t fxp_ucode_d102[] = D102_B_RCVBUNDLE_UCODE; 3051 static uint32_t fxp_ucode_d102c[] = D102_C_RCVBUNDLE_UCODE; 3052 static uint32_t fxp_ucode_d102e[] = D102_E_RCVBUNDLE_UCODE; 3053 3054 #define UCODE(x) x, sizeof(x)/sizeof(uint32_t) 3055 3056 static const struct ucode { 3057 uint32_t revision; 3058 uint32_t *ucode; 3059 int length; 3060 u_short int_delay_offset; 3061 u_short bundle_max_offset; 3062 } ucode_table[] = { 3063 { FXP_REV_82558_A4, UCODE(fxp_ucode_d101a), D101_CPUSAVER_DWORD, 0 }, 3064 { FXP_REV_82558_B0, UCODE(fxp_ucode_d101b0), D101_CPUSAVER_DWORD, 0 }, 3065 { FXP_REV_82559_A0, UCODE(fxp_ucode_d101ma), 3066 D101M_CPUSAVER_DWORD, D101M_CPUSAVER_BUNDLE_MAX_DWORD }, 3067 { FXP_REV_82559S_A, UCODE(fxp_ucode_d101s), 3068 D101S_CPUSAVER_DWORD, D101S_CPUSAVER_BUNDLE_MAX_DWORD }, 3069 { FXP_REV_82550, UCODE(fxp_ucode_d102), 3070 D102_B_CPUSAVER_DWORD, D102_B_CPUSAVER_BUNDLE_MAX_DWORD }, 3071 { FXP_REV_82550_C, UCODE(fxp_ucode_d102c), 3072 D102_C_CPUSAVER_DWORD, D102_C_CPUSAVER_BUNDLE_MAX_DWORD }, 3073 { FXP_REV_82551_F, UCODE(fxp_ucode_d102e), 3074 D102_E_CPUSAVER_DWORD, D102_E_CPUSAVER_BUNDLE_MAX_DWORD }, 3075 { FXP_REV_82551_10, UCODE(fxp_ucode_d102e), 3076 D102_E_CPUSAVER_DWORD, D102_E_CPUSAVER_BUNDLE_MAX_DWORD }, 3077 { 0, NULL, 0, 0, 0 } 3078 }; 3079 3080 static void 3081 fxp_load_ucode(struct fxp_softc *sc) 3082 { 3083 const struct ucode *uc; 3084 struct fxp_cb_ucode *cbp; 3085 int i; 3086 3087 if (sc->flags & FXP_FLAG_NO_UCODE) 3088 return; 3089 3090 for (uc = ucode_table; uc->ucode != NULL; uc++) 3091 if (sc->revision == uc->revision) 3092 break; 3093 if (uc->ucode == NULL) 3094 return; 3095 cbp = (struct fxp_cb_ucode *)sc->fxp_desc.cbl_list; 3096 cbp->cb_status = 0; 3097 cbp->cb_command = htole16(FXP_CB_COMMAND_UCODE | FXP_CB_COMMAND_EL); 3098 cbp->link_addr = 0xffffffff; /* (no) next command */ 3099 for (i = 0; i < uc->length; i++) 3100 cbp->ucode[i] = htole32(uc->ucode[i]); 3101 if (uc->int_delay_offset) 3102 *(uint16_t *)&cbp->ucode[uc->int_delay_offset] = 3103 htole16(sc->tunable_int_delay + sc->tunable_int_delay / 2); 3104 if (uc->bundle_max_offset) 3105 *(uint16_t *)&cbp->ucode[uc->bundle_max_offset] = 3106 htole16(sc->tunable_bundle_max); 3107 /* 3108 * Download the ucode to the chip. 3109 */ 3110 fxp_scb_wait(sc); 3111 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, 3112 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3113 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->fxp_desc.cbl_addr); 3114 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 3115 /* ...and wait for it to complete. */ 3116 fxp_dma_wait(sc, &cbp->cb_status, sc->cbl_tag, sc->cbl_map); 3117 device_printf(sc->dev, 3118 "Microcode loaded, int_delay: %d usec bundle_max: %d\n", 3119 sc->tunable_int_delay, 3120 uc->bundle_max_offset == 0 ? 0 : sc->tunable_bundle_max); 3121 sc->flags |= FXP_FLAG_UCODE; 3122 bzero(cbp, FXP_TXCB_SZ); 3123 } 3124 3125 #define FXP_SYSCTL_STAT_ADD(c, h, n, p, d) \ 3126 SYSCTL_ADD_UINT(c, h, OID_AUTO, n, CTLFLAG_RD, p, 0, d) 3127 3128 static void 3129 fxp_sysctl_node(struct fxp_softc *sc) 3130 { 3131 struct sysctl_ctx_list *ctx; 3132 struct sysctl_oid_list *child, *parent; 3133 struct sysctl_oid *tree; 3134 struct fxp_hwstats *hsp; 3135 3136 ctx = device_get_sysctl_ctx(sc->dev); 3137 child = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)); 3138 3139 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "int_delay", 3140 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_MPSAFE, 3141 &sc->tunable_int_delay, 0, sysctl_hw_fxp_int_delay, "I", 3142 "FXP driver receive interrupt microcode bundling delay"); 3143 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "bundle_max", 3144 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_MPSAFE, 3145 &sc->tunable_bundle_max, 0, sysctl_hw_fxp_bundle_max, "I", 3146 "FXP driver receive interrupt microcode bundle size limit"); 3147 SYSCTL_ADD_INT(ctx, child,OID_AUTO, "rnr", CTLFLAG_RD, &sc->rnr, 0, 3148 "FXP RNR events"); 3149 3150 /* 3151 * Pull in device tunables. 3152 */ 3153 sc->tunable_int_delay = TUNABLE_INT_DELAY; 3154 sc->tunable_bundle_max = TUNABLE_BUNDLE_MAX; 3155 (void) resource_int_value(device_get_name(sc->dev), 3156 device_get_unit(sc->dev), "int_delay", &sc->tunable_int_delay); 3157 (void) resource_int_value(device_get_name(sc->dev), 3158 device_get_unit(sc->dev), "bundle_max", &sc->tunable_bundle_max); 3159 sc->rnr = 0; 3160 3161 hsp = &sc->fxp_hwstats; 3162 tree = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "stats", 3163 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "FXP statistics"); 3164 parent = SYSCTL_CHILDREN(tree); 3165 3166 /* Rx MAC statistics. */ 3167 tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "rx", 3168 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "Rx MAC statistics"); 3169 child = SYSCTL_CHILDREN(tree); 3170 FXP_SYSCTL_STAT_ADD(ctx, child, "good_frames", 3171 &hsp->rx_good, "Good frames"); 3172 FXP_SYSCTL_STAT_ADD(ctx, child, "crc_errors", 3173 &hsp->rx_crc_errors, "CRC errors"); 3174 FXP_SYSCTL_STAT_ADD(ctx, child, "alignment_errors", 3175 &hsp->rx_alignment_errors, "Alignment errors"); 3176 FXP_SYSCTL_STAT_ADD(ctx, child, "rnr_errors", 3177 &hsp->rx_rnr_errors, "RNR errors"); 3178 FXP_SYSCTL_STAT_ADD(ctx, child, "overrun_errors", 3179 &hsp->rx_overrun_errors, "Overrun errors"); 3180 FXP_SYSCTL_STAT_ADD(ctx, child, "cdt_errors", 3181 &hsp->rx_cdt_errors, "Collision detect errors"); 3182 FXP_SYSCTL_STAT_ADD(ctx, child, "shortframes", 3183 &hsp->rx_shortframes, "Short frame errors"); 3184 if (sc->revision >= FXP_REV_82558_A4) { 3185 FXP_SYSCTL_STAT_ADD(ctx, child, "pause", 3186 &hsp->rx_pause, "Pause frames"); 3187 FXP_SYSCTL_STAT_ADD(ctx, child, "controls", 3188 &hsp->rx_controls, "Unsupported control frames"); 3189 } 3190 if (sc->revision >= FXP_REV_82559_A0) 3191 FXP_SYSCTL_STAT_ADD(ctx, child, "tco", 3192 &hsp->rx_tco, "TCO frames"); 3193 3194 /* Tx MAC statistics. */ 3195 tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "tx", 3196 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "Tx MAC statistics"); 3197 child = SYSCTL_CHILDREN(tree); 3198 FXP_SYSCTL_STAT_ADD(ctx, child, "good_frames", 3199 &hsp->tx_good, "Good frames"); 3200 FXP_SYSCTL_STAT_ADD(ctx, child, "maxcols", 3201 &hsp->tx_maxcols, "Maximum collisions errors"); 3202 FXP_SYSCTL_STAT_ADD(ctx, child, "latecols", 3203 &hsp->tx_latecols, "Late collisions errors"); 3204 FXP_SYSCTL_STAT_ADD(ctx, child, "underruns", 3205 &hsp->tx_underruns, "Underrun errors"); 3206 FXP_SYSCTL_STAT_ADD(ctx, child, "lostcrs", 3207 &hsp->tx_lostcrs, "Lost carrier sense"); 3208 FXP_SYSCTL_STAT_ADD(ctx, child, "deffered", 3209 &hsp->tx_deffered, "Deferred"); 3210 FXP_SYSCTL_STAT_ADD(ctx, child, "single_collisions", 3211 &hsp->tx_single_collisions, "Single collisions"); 3212 FXP_SYSCTL_STAT_ADD(ctx, child, "multiple_collisions", 3213 &hsp->tx_multiple_collisions, "Multiple collisions"); 3214 FXP_SYSCTL_STAT_ADD(ctx, child, "total_collisions", 3215 &hsp->tx_total_collisions, "Total collisions"); 3216 if (sc->revision >= FXP_REV_82558_A4) 3217 FXP_SYSCTL_STAT_ADD(ctx, child, "pause", 3218 &hsp->tx_pause, "Pause frames"); 3219 if (sc->revision >= FXP_REV_82559_A0) 3220 FXP_SYSCTL_STAT_ADD(ctx, child, "tco", 3221 &hsp->tx_tco, "TCO frames"); 3222 } 3223 3224 #undef FXP_SYSCTL_STAT_ADD 3225 3226 static int 3227 sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high) 3228 { 3229 int error, value; 3230 3231 value = *(int *)arg1; 3232 error = sysctl_handle_int(oidp, &value, 0, req); 3233 if (error || !req->newptr) 3234 return (error); 3235 if (value < low || value > high) 3236 return (EINVAL); 3237 *(int *)arg1 = value; 3238 return (0); 3239 } 3240 3241 /* 3242 * Interrupt delay is expressed in microseconds, a multiplier is used 3243 * to convert this to the appropriate clock ticks before using. 3244 */ 3245 static int 3246 sysctl_hw_fxp_int_delay(SYSCTL_HANDLER_ARGS) 3247 { 3248 3249 return (sysctl_int_range(oidp, arg1, arg2, req, 300, 3000)); 3250 } 3251 3252 static int 3253 sysctl_hw_fxp_bundle_max(SYSCTL_HANDLER_ARGS) 3254 { 3255 3256 return (sysctl_int_range(oidp, arg1, arg2, req, 1, 0xffff)); 3257 } 3258