1 /*- 2 * Copyright (c) 1995, David Greenman 3 * Copyright (c) 2001 Jonathan Lemon <jlemon@freebsd.org> 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice unmodified, this list of conditions, and the following 11 * disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 * 28 */ 29 30 #include <sys/cdefs.h> 31 __FBSDID("$FreeBSD$"); 32 33 /* 34 * Intel EtherExpress Pro/100B PCI Fast Ethernet driver 35 */ 36 37 #include <sys/param.h> 38 #include <sys/systm.h> 39 #include <sys/endian.h> 40 #include <sys/mbuf.h> 41 /* #include <sys/mutex.h> */ 42 #include <sys/kernel.h> 43 #include <sys/module.h> 44 #include <sys/socket.h> 45 #include <sys/sysctl.h> 46 47 #include <net/if.h> 48 #include <net/if_dl.h> 49 #include <net/if_media.h> 50 51 #include <net/bpf.h> 52 #include <sys/sockio.h> 53 #include <sys/bus.h> 54 #include <machine/bus.h> 55 #include <sys/rman.h> 56 #include <machine/resource.h> 57 58 #include <net/ethernet.h> 59 #include <net/if_arp.h> 60 61 #include <machine/clock.h> /* for DELAY */ 62 63 #include <net/if_types.h> 64 #include <net/if_vlan_var.h> 65 66 #ifdef FXP_IP_CSUM_WAR 67 #include <netinet/in.h> 68 #include <netinet/in_systm.h> 69 #include <netinet/ip.h> 70 #include <machine/in_cksum.h> 71 #endif 72 73 #include <dev/pci/pcivar.h> 74 #include <dev/pci/pcireg.h> /* for PCIM_CMD_xxx */ 75 76 #include <dev/mii/mii.h> 77 #include <dev/mii/miivar.h> 78 79 #include <dev/fxp/if_fxpreg.h> 80 #include <dev/fxp/if_fxpvar.h> 81 #include <dev/fxp/rcvbundl.h> 82 83 MODULE_DEPEND(fxp, pci, 1, 1, 1); 84 MODULE_DEPEND(fxp, ether, 1, 1, 1); 85 MODULE_DEPEND(fxp, miibus, 1, 1, 1); 86 #include "miibus_if.h" 87 88 /* 89 * NOTE! On the Alpha, we have an alignment constraint. The 90 * card DMAs the packet immediately following the RFA. However, 91 * the first thing in the packet is a 14-byte Ethernet header. 92 * This means that the packet is misaligned. To compensate, 93 * we actually offset the RFA 2 bytes into the cluster. This 94 * alignes the packet after the Ethernet header at a 32-bit 95 * boundary. HOWEVER! This means that the RFA is misaligned! 96 */ 97 #define RFA_ALIGNMENT_FUDGE 2 98 99 /* 100 * Set initial transmit threshold at 64 (512 bytes). This is 101 * increased by 64 (512 bytes) at a time, to maximum of 192 102 * (1536 bytes), if an underrun occurs. 103 */ 104 static int tx_threshold = 64; 105 106 /* 107 * The configuration byte map has several undefined fields which 108 * must be one or must be zero. Set up a template for these bits 109 * only, (assuming a 82557 chip) leaving the actual configuration 110 * to fxp_init. 111 * 112 * See struct fxp_cb_config for the bit definitions. 113 */ 114 static u_char fxp_cb_config_template[] = { 115 0x0, 0x0, /* cb_status */ 116 0x0, 0x0, /* cb_command */ 117 0x0, 0x0, 0x0, 0x0, /* link_addr */ 118 0x0, /* 0 */ 119 0x0, /* 1 */ 120 0x0, /* 2 */ 121 0x0, /* 3 */ 122 0x0, /* 4 */ 123 0x0, /* 5 */ 124 0x32, /* 6 */ 125 0x0, /* 7 */ 126 0x0, /* 8 */ 127 0x0, /* 9 */ 128 0x6, /* 10 */ 129 0x0, /* 11 */ 130 0x0, /* 12 */ 131 0x0, /* 13 */ 132 0xf2, /* 14 */ 133 0x48, /* 15 */ 134 0x0, /* 16 */ 135 0x40, /* 17 */ 136 0xf0, /* 18 */ 137 0x0, /* 19 */ 138 0x3f, /* 20 */ 139 0x5 /* 21 */ 140 }; 141 142 struct fxp_ident { 143 u_int16_t devid; 144 int16_t revid; /* -1 matches anything */ 145 char *name; 146 }; 147 148 /* 149 * Claim various Intel PCI device identifiers for this driver. The 150 * sub-vendor and sub-device field are extensively used to identify 151 * particular variants, but we don't currently differentiate between 152 * them. 153 */ 154 static struct fxp_ident fxp_ident_table[] = { 155 { 0x1029, -1, "Intel 82559 PCI/CardBus Pro/100" }, 156 { 0x1030, -1, "Intel 82559 Pro/100 Ethernet" }, 157 { 0x1031, -1, "Intel 82801CAM (ICH3) Pro/100 VE Ethernet" }, 158 { 0x1032, -1, "Intel 82801CAM (ICH3) Pro/100 VE Ethernet" }, 159 { 0x1033, -1, "Intel 82801CAM (ICH3) Pro/100 VM Ethernet" }, 160 { 0x1034, -1, "Intel 82801CAM (ICH3) Pro/100 VM Ethernet" }, 161 { 0x1035, -1, "Intel 82801CAM (ICH3) Pro/100 Ethernet" }, 162 { 0x1036, -1, "Intel 82801CAM (ICH3) Pro/100 Ethernet" }, 163 { 0x1037, -1, "Intel 82801CAM (ICH3) Pro/100 Ethernet" }, 164 { 0x1038, -1, "Intel 82801CAM (ICH3) Pro/100 VM Ethernet" }, 165 { 0x1039, -1, "Intel 82801DB (ICH4) Pro/100 VE Ethernet" }, 166 { 0x103A, -1, "Intel 82801DB (ICH4) Pro/100 Ethernet" }, 167 { 0x103B, -1, "Intel 82801DB (ICH4) Pro/100 VM Ethernet" }, 168 { 0x103C, -1, "Intel 82801DB (ICH4) Pro/100 Ethernet" }, 169 { 0x103D, -1, "Intel 82801DB (ICH4) Pro/100 VE Ethernet" }, 170 { 0x103E, -1, "Intel 82801DB (ICH4) Pro/100 VM Ethernet" }, 171 { 0x1050, -1, "Intel 82801BA (D865) Pro/100 VE Ethernet" }, 172 { 0x1051, -1, "Intel 82562ET (ICH5/ICH5R) Pro/100 VE Ethernet" }, 173 { 0x1059, -1, "Intel 82551QM Pro/100 M Mobile Connection" }, 174 { 0x1064, -1, "Intel 82562EZ (ICH6)" }, 175 { 0x1209, -1, "Intel 82559ER Embedded 10/100 Ethernet" }, 176 { 0x1229, 0x01, "Intel 82557 Pro/100 Ethernet" }, 177 { 0x1229, 0x02, "Intel 82557 Pro/100 Ethernet" }, 178 { 0x1229, 0x03, "Intel 82557 Pro/100 Ethernet" }, 179 { 0x1229, 0x04, "Intel 82558 Pro/100 Ethernet" }, 180 { 0x1229, 0x05, "Intel 82558 Pro/100 Ethernet" }, 181 { 0x1229, 0x06, "Intel 82559 Pro/100 Ethernet" }, 182 { 0x1229, 0x07, "Intel 82559 Pro/100 Ethernet" }, 183 { 0x1229, 0x08, "Intel 82559 Pro/100 Ethernet" }, 184 { 0x1229, 0x09, "Intel 82559ER Pro/100 Ethernet" }, 185 { 0x1229, 0x0c, "Intel 82550 Pro/100 Ethernet" }, 186 { 0x1229, 0x0d, "Intel 82550 Pro/100 Ethernet" }, 187 { 0x1229, 0x0e, "Intel 82550 Pro/100 Ethernet" }, 188 { 0x1229, 0x0f, "Intel 82551 Pro/100 Ethernet" }, 189 { 0x1229, 0x10, "Intel 82551 Pro/100 Ethernet" }, 190 { 0x1229, -1, "Intel 82557/8/9 Pro/100 Ethernet" }, 191 { 0x2449, -1, "Intel 82801BA/CAM (ICH2/3) Pro/100 Ethernet" }, 192 { 0, -1, NULL }, 193 }; 194 195 #ifdef FXP_IP_CSUM_WAR 196 #define FXP_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 197 #else 198 #define FXP_CSUM_FEATURES (CSUM_TCP | CSUM_UDP) 199 #endif 200 201 static int fxp_probe(device_t dev); 202 static int fxp_attach(device_t dev); 203 static int fxp_detach(device_t dev); 204 static int fxp_shutdown(device_t dev); 205 static int fxp_suspend(device_t dev); 206 static int fxp_resume(device_t dev); 207 208 static void fxp_intr(void *xsc); 209 static void fxp_intr_body(struct fxp_softc *sc, struct ifnet *ifp, 210 u_int8_t statack, int count); 211 static void fxp_init(void *xsc); 212 static void fxp_init_body(struct fxp_softc *sc); 213 static void fxp_tick(void *xsc); 214 static void fxp_start(struct ifnet *ifp); 215 static void fxp_start_body(struct ifnet *ifp); 216 static void fxp_stop(struct fxp_softc *sc); 217 static void fxp_release(struct fxp_softc *sc); 218 static int fxp_ioctl(struct ifnet *ifp, u_long command, 219 caddr_t data); 220 static void fxp_watchdog(struct ifnet *ifp); 221 static int fxp_add_rfabuf(struct fxp_softc *sc, 222 struct fxp_rx *rxp); 223 static int fxp_mc_addrs(struct fxp_softc *sc); 224 static void fxp_mc_setup(struct fxp_softc *sc); 225 static u_int16_t fxp_eeprom_getword(struct fxp_softc *sc, int offset, 226 int autosize); 227 static void fxp_eeprom_putword(struct fxp_softc *sc, int offset, 228 u_int16_t data); 229 static void fxp_autosize_eeprom(struct fxp_softc *sc); 230 static void fxp_read_eeprom(struct fxp_softc *sc, u_short *data, 231 int offset, int words); 232 static void fxp_write_eeprom(struct fxp_softc *sc, u_short *data, 233 int offset, int words); 234 static int fxp_ifmedia_upd(struct ifnet *ifp); 235 static void fxp_ifmedia_sts(struct ifnet *ifp, 236 struct ifmediareq *ifmr); 237 static int fxp_serial_ifmedia_upd(struct ifnet *ifp); 238 static void fxp_serial_ifmedia_sts(struct ifnet *ifp, 239 struct ifmediareq *ifmr); 240 static volatile int fxp_miibus_readreg(device_t dev, int phy, int reg); 241 static void fxp_miibus_writereg(device_t dev, int phy, int reg, 242 int value); 243 static void fxp_load_ucode(struct fxp_softc *sc); 244 static int sysctl_int_range(SYSCTL_HANDLER_ARGS, 245 int low, int high); 246 static int sysctl_hw_fxp_bundle_max(SYSCTL_HANDLER_ARGS); 247 static int sysctl_hw_fxp_int_delay(SYSCTL_HANDLER_ARGS); 248 static void fxp_scb_wait(struct fxp_softc *sc); 249 static void fxp_scb_cmd(struct fxp_softc *sc, int cmd); 250 static void fxp_dma_wait(struct fxp_softc *sc, 251 volatile u_int16_t *status, bus_dma_tag_t dmat, 252 bus_dmamap_t map); 253 254 static device_method_t fxp_methods[] = { 255 /* Device interface */ 256 DEVMETHOD(device_probe, fxp_probe), 257 DEVMETHOD(device_attach, fxp_attach), 258 DEVMETHOD(device_detach, fxp_detach), 259 DEVMETHOD(device_shutdown, fxp_shutdown), 260 DEVMETHOD(device_suspend, fxp_suspend), 261 DEVMETHOD(device_resume, fxp_resume), 262 263 /* MII interface */ 264 DEVMETHOD(miibus_readreg, fxp_miibus_readreg), 265 DEVMETHOD(miibus_writereg, fxp_miibus_writereg), 266 267 { 0, 0 } 268 }; 269 270 static driver_t fxp_driver = { 271 "fxp", 272 fxp_methods, 273 sizeof(struct fxp_softc), 274 }; 275 276 static devclass_t fxp_devclass; 277 278 DRIVER_MODULE(fxp, pci, fxp_driver, fxp_devclass, 0, 0); 279 DRIVER_MODULE(fxp, cardbus, fxp_driver, fxp_devclass, 0, 0); 280 DRIVER_MODULE(miibus, fxp, miibus_driver, miibus_devclass, 0, 0); 281 282 /* 283 * Wait for the previous command to be accepted (but not necessarily 284 * completed). 285 */ 286 static void 287 fxp_scb_wait(struct fxp_softc *sc) 288 { 289 int i = 10000; 290 291 while (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) && --i) 292 DELAY(2); 293 if (i == 0) 294 device_printf(sc->dev, "SCB timeout: 0x%x 0x%x 0x%x 0x%x\n", 295 CSR_READ_1(sc, FXP_CSR_SCB_COMMAND), 296 CSR_READ_1(sc, FXP_CSR_SCB_STATACK), 297 CSR_READ_1(sc, FXP_CSR_SCB_RUSCUS), 298 CSR_READ_2(sc, FXP_CSR_FLOWCONTROL)); 299 } 300 301 static void 302 fxp_scb_cmd(struct fxp_softc *sc, int cmd) 303 { 304 305 if (cmd == FXP_SCB_COMMAND_CU_RESUME && sc->cu_resume_bug) { 306 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_CB_COMMAND_NOP); 307 fxp_scb_wait(sc); 308 } 309 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, cmd); 310 } 311 312 static void 313 fxp_dma_wait(struct fxp_softc *sc, volatile u_int16_t *status, 314 bus_dma_tag_t dmat, bus_dmamap_t map) 315 { 316 int i = 10000; 317 318 bus_dmamap_sync(dmat, map, BUS_DMASYNC_POSTREAD); 319 while (!(le16toh(*status) & FXP_CB_STATUS_C) && --i) { 320 DELAY(2); 321 bus_dmamap_sync(dmat, map, BUS_DMASYNC_POSTREAD); 322 } 323 if (i == 0) 324 device_printf(sc->dev, "DMA timeout\n"); 325 } 326 327 /* 328 * Return identification string if this device is ours. 329 */ 330 static int 331 fxp_probe(device_t dev) 332 { 333 u_int16_t devid; 334 u_int8_t revid; 335 struct fxp_ident *ident; 336 337 if (pci_get_vendor(dev) == FXP_VENDORID_INTEL) { 338 devid = pci_get_device(dev); 339 revid = pci_get_revid(dev); 340 for (ident = fxp_ident_table; ident->name != NULL; ident++) { 341 if (ident->devid == devid && 342 (ident->revid == revid || ident->revid == -1)) { 343 device_set_desc(dev, ident->name); 344 return (0); 345 } 346 } 347 } 348 return (ENXIO); 349 } 350 351 static void 352 fxp_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error) 353 { 354 u_int32_t *addr; 355 356 if (error) 357 return; 358 359 KASSERT(nseg == 1, ("too many DMA segments, %d should be 1", nseg)); 360 addr = arg; 361 *addr = segs->ds_addr; 362 } 363 364 static int 365 fxp_attach(device_t dev) 366 { 367 int error = 0; 368 struct fxp_softc *sc = device_get_softc(dev); 369 struct ifnet *ifp; 370 struct fxp_rx *rxp; 371 u_int32_t val; 372 u_int16_t data, myea[ETHER_ADDR_LEN / 2]; 373 int i, rid, m1, m2, prefer_iomap, maxtxseg; 374 int s; 375 376 sc->dev = dev; 377 callout_init(&sc->stat_ch, CALLOUT_MPSAFE); 378 mtx_init(&sc->sc_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 379 MTX_DEF); 380 ifmedia_init(&sc->sc_media, 0, fxp_serial_ifmedia_upd, 381 fxp_serial_ifmedia_sts); 382 383 s = splimp(); 384 385 /* 386 * Enable bus mastering. 387 */ 388 pci_enable_busmaster(dev); 389 val = pci_read_config(dev, PCIR_COMMAND, 2); 390 391 /* 392 * Figure out which we should try first - memory mapping or i/o mapping? 393 * We default to memory mapping. Then we accept an override from the 394 * command line. Then we check to see which one is enabled. 395 */ 396 m1 = PCIM_CMD_MEMEN; 397 m2 = PCIM_CMD_PORTEN; 398 prefer_iomap = 0; 399 if (resource_int_value(device_get_name(dev), device_get_unit(dev), 400 "prefer_iomap", &prefer_iomap) == 0 && prefer_iomap != 0) { 401 m1 = PCIM_CMD_PORTEN; 402 m2 = PCIM_CMD_MEMEN; 403 } 404 405 sc->rtp = (m1 == PCIM_CMD_MEMEN)? SYS_RES_MEMORY : SYS_RES_IOPORT; 406 sc->rgd = (m1 == PCIM_CMD_MEMEN)? FXP_PCI_MMBA : FXP_PCI_IOBA; 407 sc->mem = bus_alloc_resource_any(dev, sc->rtp, &sc->rgd, RF_ACTIVE); 408 if (sc->mem == NULL) { 409 sc->rtp = 410 (m2 == PCIM_CMD_MEMEN)? SYS_RES_MEMORY : SYS_RES_IOPORT; 411 sc->rgd = (m2 == PCIM_CMD_MEMEN)? FXP_PCI_MMBA : FXP_PCI_IOBA; 412 sc->mem = bus_alloc_resource_any(dev, sc->rtp, &sc->rgd, 413 RF_ACTIVE); 414 } 415 416 if (!sc->mem) { 417 error = ENXIO; 418 goto fail; 419 } 420 if (bootverbose) { 421 device_printf(dev, "using %s space register mapping\n", 422 sc->rtp == SYS_RES_MEMORY? "memory" : "I/O"); 423 } 424 425 sc->sc_st = rman_get_bustag(sc->mem); 426 sc->sc_sh = rman_get_bushandle(sc->mem); 427 428 /* 429 * Allocate our interrupt. 430 */ 431 rid = 0; 432 sc->irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 433 RF_SHAREABLE | RF_ACTIVE); 434 if (sc->irq == NULL) { 435 device_printf(dev, "could not map interrupt\n"); 436 error = ENXIO; 437 goto fail; 438 } 439 440 /* 441 * Reset to a stable state. 442 */ 443 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET); 444 DELAY(10); 445 446 /* 447 * Find out how large of an SEEPROM we have. 448 */ 449 fxp_autosize_eeprom(sc); 450 451 /* 452 * Determine whether we must use the 503 serial interface. 453 */ 454 fxp_read_eeprom(sc, &data, 6, 1); 455 if (sc->revision <= FXP_REV_82557 && (data & FXP_PHY_DEVICE_MASK) != 0 456 && (data & FXP_PHY_SERIAL_ONLY)) 457 sc->flags |= FXP_FLAG_SERIAL_MEDIA; 458 459 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 460 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 461 OID_AUTO, "int_delay", CTLTYPE_INT | CTLFLAG_RW, 462 &sc->tunable_int_delay, 0, sysctl_hw_fxp_int_delay, "I", 463 "FXP driver receive interrupt microcode bundling delay"); 464 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 465 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 466 OID_AUTO, "bundle_max", CTLTYPE_INT | CTLFLAG_RW, 467 &sc->tunable_bundle_max, 0, sysctl_hw_fxp_bundle_max, "I", 468 "FXP driver receive interrupt microcode bundle size limit"); 469 SYSCTL_ADD_INT(device_get_sysctl_ctx(dev), 470 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 471 OID_AUTO, "rnr", CTLFLAG_RD, &sc->rnr, 0, 472 "FXP RNR events"); 473 SYSCTL_ADD_INT(device_get_sysctl_ctx(dev), 474 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 475 OID_AUTO, "noflow", CTLFLAG_RW, &sc->tunable_noflow, 0, 476 "FXP flow control disabled"); 477 478 /* 479 * Pull in device tunables. 480 */ 481 sc->tunable_int_delay = TUNABLE_INT_DELAY; 482 sc->tunable_bundle_max = TUNABLE_BUNDLE_MAX; 483 sc->tunable_noflow = 1; 484 (void) resource_int_value(device_get_name(dev), device_get_unit(dev), 485 "int_delay", &sc->tunable_int_delay); 486 (void) resource_int_value(device_get_name(dev), device_get_unit(dev), 487 "bundle_max", &sc->tunable_bundle_max); 488 (void) resource_int_value(device_get_name(dev), device_get_unit(dev), 489 "noflow", &sc->tunable_noflow); 490 sc->rnr = 0; 491 492 /* 493 * Find out the chip revision; lump all 82557 revs together. 494 */ 495 fxp_read_eeprom(sc, &data, 5, 1); 496 if ((data >> 8) == 1) 497 sc->revision = FXP_REV_82557; 498 else 499 sc->revision = pci_get_revid(dev); 500 501 /* 502 * Enable workarounds for certain chip revision deficiencies. 503 * 504 * Systems based on the ICH2/ICH2-M chip from Intel, and possibly 505 * some systems based a normal 82559 design, have a defect where 506 * the chip can cause a PCI protocol violation if it receives 507 * a CU_RESUME command when it is entering the IDLE state. The 508 * workaround is to disable Dynamic Standby Mode, so the chip never 509 * deasserts CLKRUN#, and always remains in an active state. 510 * 511 * See Intel 82801BA/82801BAM Specification Update, Errata #30. 512 */ 513 i = pci_get_device(dev); 514 if (i == 0x2449 || (i > 0x1030 && i < 0x1039) || 515 sc->revision >= FXP_REV_82559_A0) { 516 fxp_read_eeprom(sc, &data, 10, 1); 517 if (data & 0x02) { /* STB enable */ 518 u_int16_t cksum; 519 int i; 520 521 device_printf(dev, 522 "Disabling dynamic standby mode in EEPROM\n"); 523 data &= ~0x02; 524 fxp_write_eeprom(sc, &data, 10, 1); 525 device_printf(dev, "New EEPROM ID: 0x%x\n", data); 526 cksum = 0; 527 for (i = 0; i < (1 << sc->eeprom_size) - 1; i++) { 528 fxp_read_eeprom(sc, &data, i, 1); 529 cksum += data; 530 } 531 i = (1 << sc->eeprom_size) - 1; 532 cksum = 0xBABA - cksum; 533 fxp_read_eeprom(sc, &data, i, 1); 534 fxp_write_eeprom(sc, &cksum, i, 1); 535 device_printf(dev, 536 "EEPROM checksum @ 0x%x: 0x%x -> 0x%x\n", 537 i, data, cksum); 538 #if 1 539 /* 540 * If the user elects to continue, try the software 541 * workaround, as it is better than nothing. 542 */ 543 sc->flags |= FXP_FLAG_CU_RESUME_BUG; 544 #endif 545 } 546 } 547 548 /* 549 * If we are not a 82557 chip, we can enable extended features. 550 */ 551 if (sc->revision != FXP_REV_82557) { 552 /* 553 * If MWI is enabled in the PCI configuration, and there 554 * is a valid cacheline size (8 or 16 dwords), then tell 555 * the board to turn on MWI. 556 */ 557 if (val & PCIM_CMD_MWRICEN && 558 pci_read_config(dev, PCIR_CACHELNSZ, 1) != 0) 559 sc->flags |= FXP_FLAG_MWI_ENABLE; 560 561 /* turn on the extended TxCB feature */ 562 sc->flags |= FXP_FLAG_EXT_TXCB; 563 564 /* enable reception of long frames for VLAN */ 565 sc->flags |= FXP_FLAG_LONG_PKT_EN; 566 } else { 567 /* a hack to get long VLAN frames on a 82557 */ 568 sc->flags |= FXP_FLAG_SAVE_BAD; 569 } 570 571 /* 572 * Enable use of extended RFDs and TCBs for 82550 573 * and later chips. Note: we need extended TXCB support 574 * too, but that's already enabled by the code above. 575 * Be careful to do this only on the right devices. 576 */ 577 578 if (sc->revision == FXP_REV_82550 || sc->revision == FXP_REV_82550_C) { 579 sc->rfa_size = sizeof (struct fxp_rfa); 580 sc->tx_cmd = FXP_CB_COMMAND_IPCBXMIT; 581 sc->flags |= FXP_FLAG_EXT_RFA; 582 } else { 583 sc->rfa_size = sizeof (struct fxp_rfa) - FXP_RFAX_LEN; 584 sc->tx_cmd = FXP_CB_COMMAND_XMIT; 585 } 586 587 /* 588 * Allocate DMA tags and DMA safe memory. 589 */ 590 maxtxseg = sc->flags & FXP_FLAG_EXT_RFA ? FXP_NTXSEG - 1 : FXP_NTXSEG; 591 error = bus_dma_tag_create(NULL, 2, 0, BUS_SPACE_MAXADDR_32BIT, 592 BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES * maxtxseg, 593 maxtxseg, MCLBYTES, 0, busdma_lock_mutex, &Giant, &sc->fxp_mtag); 594 if (error) { 595 device_printf(dev, "could not allocate dma tag\n"); 596 goto fail; 597 } 598 599 error = bus_dma_tag_create(NULL, 4, 0, BUS_SPACE_MAXADDR_32BIT, 600 BUS_SPACE_MAXADDR, NULL, NULL, sizeof(struct fxp_stats), 1, 601 sizeof(struct fxp_stats), 0, busdma_lock_mutex, &Giant, 602 &sc->fxp_stag); 603 if (error) { 604 device_printf(dev, "could not allocate dma tag\n"); 605 goto fail; 606 } 607 608 error = bus_dmamem_alloc(sc->fxp_stag, (void **)&sc->fxp_stats, 609 BUS_DMA_NOWAIT | BUS_DMA_ZERO, &sc->fxp_smap); 610 if (error) 611 goto fail; 612 error = bus_dmamap_load(sc->fxp_stag, sc->fxp_smap, sc->fxp_stats, 613 sizeof(struct fxp_stats), fxp_dma_map_addr, &sc->stats_addr, 0); 614 if (error) { 615 device_printf(dev, "could not map the stats buffer\n"); 616 goto fail; 617 } 618 619 error = bus_dma_tag_create(NULL, 4, 0, BUS_SPACE_MAXADDR_32BIT, 620 BUS_SPACE_MAXADDR, NULL, NULL, FXP_TXCB_SZ, 1, 621 FXP_TXCB_SZ, 0, busdma_lock_mutex, &Giant, &sc->cbl_tag); 622 if (error) { 623 device_printf(dev, "could not allocate dma tag\n"); 624 goto fail; 625 } 626 627 error = bus_dmamem_alloc(sc->cbl_tag, (void **)&sc->fxp_desc.cbl_list, 628 BUS_DMA_NOWAIT | BUS_DMA_ZERO, &sc->cbl_map); 629 if (error) 630 goto fail; 631 632 error = bus_dmamap_load(sc->cbl_tag, sc->cbl_map, 633 sc->fxp_desc.cbl_list, FXP_TXCB_SZ, fxp_dma_map_addr, 634 &sc->fxp_desc.cbl_addr, 0); 635 if (error) { 636 device_printf(dev, "could not map DMA memory\n"); 637 goto fail; 638 } 639 640 error = bus_dma_tag_create(NULL, 4, 0, BUS_SPACE_MAXADDR_32BIT, 641 BUS_SPACE_MAXADDR, NULL, NULL, sizeof(struct fxp_cb_mcs), 1, 642 sizeof(struct fxp_cb_mcs), 0, busdma_lock_mutex, &Giant, 643 &sc->mcs_tag); 644 if (error) { 645 device_printf(dev, "could not allocate dma tag\n"); 646 goto fail; 647 } 648 649 error = bus_dmamem_alloc(sc->mcs_tag, (void **)&sc->mcsp, 650 BUS_DMA_NOWAIT, &sc->mcs_map); 651 if (error) 652 goto fail; 653 error = bus_dmamap_load(sc->mcs_tag, sc->mcs_map, sc->mcsp, 654 sizeof(struct fxp_cb_mcs), fxp_dma_map_addr, &sc->mcs_addr, 0); 655 if (error) { 656 device_printf(dev, "can't map the multicast setup command\n"); 657 goto fail; 658 } 659 660 /* 661 * Pre-allocate the TX DMA maps. 662 */ 663 for (i = 0; i < FXP_NTXCB; i++) { 664 error = bus_dmamap_create(sc->fxp_mtag, 0, 665 &sc->fxp_desc.tx_list[i].tx_map); 666 if (error) { 667 device_printf(dev, "can't create DMA map for TX\n"); 668 goto fail; 669 } 670 } 671 error = bus_dmamap_create(sc->fxp_mtag, 0, &sc->spare_map); 672 if (error) { 673 device_printf(dev, "can't create spare DMA map\n"); 674 goto fail; 675 } 676 677 /* 678 * Pre-allocate our receive buffers. 679 */ 680 sc->fxp_desc.rx_head = sc->fxp_desc.rx_tail = NULL; 681 for (i = 0; i < FXP_NRFABUFS; i++) { 682 rxp = &sc->fxp_desc.rx_list[i]; 683 error = bus_dmamap_create(sc->fxp_mtag, 0, &rxp->rx_map); 684 if (error) { 685 device_printf(dev, "can't create DMA map for RX\n"); 686 goto fail; 687 } 688 if (fxp_add_rfabuf(sc, rxp) != 0) { 689 error = ENOMEM; 690 goto fail; 691 } 692 } 693 694 /* 695 * Read MAC address. 696 */ 697 fxp_read_eeprom(sc, myea, 0, 3); 698 sc->arpcom.ac_enaddr[0] = myea[0] & 0xff; 699 sc->arpcom.ac_enaddr[1] = myea[0] >> 8; 700 sc->arpcom.ac_enaddr[2] = myea[1] & 0xff; 701 sc->arpcom.ac_enaddr[3] = myea[1] >> 8; 702 sc->arpcom.ac_enaddr[4] = myea[2] & 0xff; 703 sc->arpcom.ac_enaddr[5] = myea[2] >> 8; 704 if (bootverbose) { 705 device_printf(dev, "PCI IDs: %04x %04x %04x %04x %04x\n", 706 pci_get_vendor(dev), pci_get_device(dev), 707 pci_get_subvendor(dev), pci_get_subdevice(dev), 708 pci_get_revid(dev)); 709 fxp_read_eeprom(sc, &data, 10, 1); 710 device_printf(dev, "Dynamic Standby mode is %s\n", 711 data & 0x02 ? "enabled" : "disabled"); 712 } 713 714 /* 715 * If this is only a 10Mbps device, then there is no MII, and 716 * the PHY will use a serial interface instead. 717 * 718 * The Seeq 80c24 AutoDUPLEX(tm) Ethernet Interface Adapter 719 * doesn't have a programming interface of any sort. The 720 * media is sensed automatically based on how the link partner 721 * is configured. This is, in essence, manual configuration. 722 */ 723 if (sc->flags & FXP_FLAG_SERIAL_MEDIA) { 724 ifmedia_add(&sc->sc_media, IFM_ETHER|IFM_MANUAL, 0, NULL); 725 ifmedia_set(&sc->sc_media, IFM_ETHER|IFM_MANUAL); 726 } else { 727 if (mii_phy_probe(dev, &sc->miibus, fxp_ifmedia_upd, 728 fxp_ifmedia_sts)) { 729 device_printf(dev, "MII without any PHY!\n"); 730 error = ENXIO; 731 goto fail; 732 } 733 } 734 735 ifp = &sc->arpcom.ac_if; 736 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 737 ifp->if_baudrate = 100000000; 738 ifp->if_init = fxp_init; 739 ifp->if_softc = sc; 740 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 741 ifp->if_ioctl = fxp_ioctl; 742 ifp->if_start = fxp_start; 743 ifp->if_watchdog = fxp_watchdog; 744 745 ifp->if_capabilities = ifp->if_capenable = 0; 746 747 /* Enable checksum offload for 82550 or better chips */ 748 if (sc->flags & FXP_FLAG_EXT_RFA) { 749 ifp->if_hwassist = FXP_CSUM_FEATURES; 750 ifp->if_capabilities |= IFCAP_HWCSUM; 751 ifp->if_capenable |= IFCAP_HWCSUM; 752 } 753 754 #ifdef DEVICE_POLLING 755 /* Inform the world we support polling. */ 756 ifp->if_capabilities |= IFCAP_POLLING; 757 ifp->if_capenable |= IFCAP_POLLING; 758 #endif 759 760 /* 761 * Attach the interface. 762 */ 763 ether_ifattach(ifp, sc->arpcom.ac_enaddr); 764 765 /* 766 * Tell the upper layer(s) we support long frames. 767 * Must appear after the call to ether_ifattach() because 768 * ether_ifattach() sets ifi_hdrlen to the default value. 769 */ 770 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 771 ifp->if_capabilities |= IFCAP_VLAN_MTU; 772 ifp->if_capenable |= IFCAP_VLAN_MTU; /* the hw bits already set */ 773 774 /* 775 * Let the system queue as many packets as we have available 776 * TX descriptors. 777 */ 778 IFQ_SET_MAXLEN(&ifp->if_snd, FXP_NTXCB - 1); 779 ifp->if_snd.ifq_drv_maxlen = FXP_NTXCB - 1; 780 IFQ_SET_READY(&ifp->if_snd); 781 782 /* 783 * Hook our interrupt after all initialization is complete. 784 * XXX This driver has been tested with the INTR_MPSAFFE flag set 785 * however, ifp and its functions are not fully locked so MPSAFE 786 * should not be used unless you can handle potential data loss. 787 */ 788 error = bus_setup_intr(dev, sc->irq, INTR_TYPE_NET | INTR_MPSAFE, 789 fxp_intr, sc, &sc->ih); 790 if (error) { 791 device_printf(dev, "could not setup irq\n"); 792 ether_ifdetach(&sc->arpcom.ac_if); 793 goto fail; 794 } 795 796 fail: 797 splx(s); 798 if (error) 799 fxp_release(sc); 800 return (error); 801 } 802 803 /* 804 * Release all resources. The softc lock should not be held and the 805 * interrupt should already be torn down. 806 */ 807 static void 808 fxp_release(struct fxp_softc *sc) 809 { 810 struct fxp_rx *rxp; 811 struct fxp_tx *txp; 812 int i; 813 814 FXP_LOCK_ASSERT(sc, MA_NOTOWNED); 815 KASSERT(sc->ih == NULL, 816 ("fxp_release() called with intr handle still active")); 817 if (sc->miibus) 818 device_delete_child(sc->dev, sc->miibus); 819 bus_generic_detach(sc->dev); 820 ifmedia_removeall(&sc->sc_media); 821 if (sc->fxp_desc.cbl_list) { 822 bus_dmamap_unload(sc->cbl_tag, sc->cbl_map); 823 bus_dmamem_free(sc->cbl_tag, sc->fxp_desc.cbl_list, 824 sc->cbl_map); 825 } 826 if (sc->fxp_stats) { 827 bus_dmamap_unload(sc->fxp_stag, sc->fxp_smap); 828 bus_dmamem_free(sc->fxp_stag, sc->fxp_stats, sc->fxp_smap); 829 } 830 if (sc->mcsp) { 831 bus_dmamap_unload(sc->mcs_tag, sc->mcs_map); 832 bus_dmamem_free(sc->mcs_tag, sc->mcsp, sc->mcs_map); 833 } 834 if (sc->irq) 835 bus_release_resource(sc->dev, SYS_RES_IRQ, 0, sc->irq); 836 if (sc->mem) 837 bus_release_resource(sc->dev, sc->rtp, sc->rgd, sc->mem); 838 if (sc->fxp_mtag) { 839 for (i = 0; i < FXP_NRFABUFS; i++) { 840 rxp = &sc->fxp_desc.rx_list[i]; 841 if (rxp->rx_mbuf != NULL) { 842 bus_dmamap_sync(sc->fxp_mtag, rxp->rx_map, 843 BUS_DMASYNC_POSTREAD); 844 bus_dmamap_unload(sc->fxp_mtag, rxp->rx_map); 845 m_freem(rxp->rx_mbuf); 846 } 847 bus_dmamap_destroy(sc->fxp_mtag, rxp->rx_map); 848 } 849 bus_dmamap_destroy(sc->fxp_mtag, sc->spare_map); 850 bus_dma_tag_destroy(sc->fxp_mtag); 851 } 852 if (sc->fxp_stag) { 853 for (i = 0; i < FXP_NTXCB; i++) { 854 txp = &sc->fxp_desc.tx_list[i]; 855 if (txp->tx_mbuf != NULL) { 856 bus_dmamap_sync(sc->fxp_mtag, txp->tx_map, 857 BUS_DMASYNC_POSTWRITE); 858 bus_dmamap_unload(sc->fxp_mtag, txp->tx_map); 859 m_freem(txp->tx_mbuf); 860 } 861 bus_dmamap_destroy(sc->fxp_mtag, txp->tx_map); 862 } 863 bus_dma_tag_destroy(sc->fxp_stag); 864 } 865 if (sc->cbl_tag) 866 bus_dma_tag_destroy(sc->cbl_tag); 867 if (sc->mcs_tag) 868 bus_dma_tag_destroy(sc->mcs_tag); 869 870 mtx_destroy(&sc->sc_mtx); 871 } 872 873 /* 874 * Detach interface. 875 */ 876 static int 877 fxp_detach(device_t dev) 878 { 879 struct fxp_softc *sc = device_get_softc(dev); 880 int s; 881 882 FXP_LOCK(sc); 883 s = splimp(); 884 885 sc->suspended = 1; /* Do same thing as we do for suspend */ 886 /* 887 * Close down routes etc. 888 */ 889 ether_ifdetach(&sc->arpcom.ac_if); 890 891 /* 892 * Stop DMA and drop transmit queue, but disable interrupts first. 893 */ 894 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE); 895 fxp_stop(sc); 896 FXP_UNLOCK(sc); 897 898 /* 899 * Unhook interrupt before dropping lock. This is to prevent 900 * races with fxp_intr(). 901 */ 902 bus_teardown_intr(sc->dev, sc->irq, sc->ih); 903 sc->ih = NULL; 904 905 splx(s); 906 907 /* Release our allocated resources. */ 908 fxp_release(sc); 909 return (0); 910 } 911 912 /* 913 * Device shutdown routine. Called at system shutdown after sync. The 914 * main purpose of this routine is to shut off receiver DMA so that 915 * kernel memory doesn't get clobbered during warmboot. 916 */ 917 static int 918 fxp_shutdown(device_t dev) 919 { 920 /* 921 * Make sure that DMA is disabled prior to reboot. Not doing 922 * do could allow DMA to corrupt kernel memory during the 923 * reboot before the driver initializes. 924 */ 925 fxp_stop((struct fxp_softc *) device_get_softc(dev)); 926 return (0); 927 } 928 929 /* 930 * Device suspend routine. Stop the interface and save some PCI 931 * settings in case the BIOS doesn't restore them properly on 932 * resume. 933 */ 934 static int 935 fxp_suspend(device_t dev) 936 { 937 struct fxp_softc *sc = device_get_softc(dev); 938 int i, s; 939 940 FXP_LOCK(sc); 941 s = splimp(); 942 943 fxp_stop(sc); 944 945 for (i = 0; i < 5; i++) 946 sc->saved_maps[i] = pci_read_config(dev, PCIR_BAR(i), 4); 947 sc->saved_biosaddr = pci_read_config(dev, PCIR_BIOS, 4); 948 sc->saved_intline = pci_read_config(dev, PCIR_INTLINE, 1); 949 sc->saved_cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1); 950 sc->saved_lattimer = pci_read_config(dev, PCIR_LATTIMER, 1); 951 952 sc->suspended = 1; 953 954 FXP_UNLOCK(sc); 955 splx(s); 956 return (0); 957 } 958 959 /* 960 * Device resume routine. Restore some PCI settings in case the BIOS 961 * doesn't, re-enable busmastering, and restart the interface if 962 * appropriate. 963 */ 964 static int 965 fxp_resume(device_t dev) 966 { 967 struct fxp_softc *sc = device_get_softc(dev); 968 struct ifnet *ifp = &sc->sc_if; 969 u_int16_t pci_command; 970 int i, s; 971 972 FXP_LOCK(sc); 973 s = splimp(); 974 975 /* better way to do this? */ 976 for (i = 0; i < 5; i++) 977 pci_write_config(dev, PCIR_BAR(i), sc->saved_maps[i], 4); 978 pci_write_config(dev, PCIR_BIOS, sc->saved_biosaddr, 4); 979 pci_write_config(dev, PCIR_INTLINE, sc->saved_intline, 1); 980 pci_write_config(dev, PCIR_CACHELNSZ, sc->saved_cachelnsz, 1); 981 pci_write_config(dev, PCIR_LATTIMER, sc->saved_lattimer, 1); 982 983 /* reenable busmastering */ 984 pci_command = pci_read_config(dev, PCIR_COMMAND, 2); 985 pci_command |= (PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN); 986 pci_write_config(dev, PCIR_COMMAND, pci_command, 2); 987 988 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET); 989 DELAY(10); 990 991 /* reinitialize interface if necessary */ 992 if (ifp->if_flags & IFF_UP) 993 fxp_init_body(sc); 994 995 sc->suspended = 0; 996 997 FXP_UNLOCK(sc); 998 splx(s); 999 return (0); 1000 } 1001 1002 static void 1003 fxp_eeprom_shiftin(struct fxp_softc *sc, int data, int length) 1004 { 1005 u_int16_t reg; 1006 int x; 1007 1008 /* 1009 * Shift in data. 1010 */ 1011 for (x = 1 << (length - 1); x; x >>= 1) { 1012 if (data & x) 1013 reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI; 1014 else 1015 reg = FXP_EEPROM_EECS; 1016 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 1017 DELAY(1); 1018 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK); 1019 DELAY(1); 1020 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 1021 DELAY(1); 1022 } 1023 } 1024 1025 /* 1026 * Read from the serial EEPROM. Basically, you manually shift in 1027 * the read opcode (one bit at a time) and then shift in the address, 1028 * and then you shift out the data (all of this one bit at a time). 1029 * The word size is 16 bits, so you have to provide the address for 1030 * every 16 bits of data. 1031 */ 1032 static u_int16_t 1033 fxp_eeprom_getword(struct fxp_softc *sc, int offset, int autosize) 1034 { 1035 u_int16_t reg, data; 1036 int x; 1037 1038 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 1039 /* 1040 * Shift in read opcode. 1041 */ 1042 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_READ, 3); 1043 /* 1044 * Shift in address. 1045 */ 1046 data = 0; 1047 for (x = 1 << (sc->eeprom_size - 1); x; x >>= 1) { 1048 if (offset & x) 1049 reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI; 1050 else 1051 reg = FXP_EEPROM_EECS; 1052 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 1053 DELAY(1); 1054 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK); 1055 DELAY(1); 1056 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 1057 DELAY(1); 1058 reg = CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO; 1059 data++; 1060 if (autosize && reg == 0) { 1061 sc->eeprom_size = data; 1062 break; 1063 } 1064 } 1065 /* 1066 * Shift out data. 1067 */ 1068 data = 0; 1069 reg = FXP_EEPROM_EECS; 1070 for (x = 1 << 15; x; x >>= 1) { 1071 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK); 1072 DELAY(1); 1073 if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO) 1074 data |= x; 1075 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 1076 DELAY(1); 1077 } 1078 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 1079 DELAY(1); 1080 1081 return (data); 1082 } 1083 1084 static void 1085 fxp_eeprom_putword(struct fxp_softc *sc, int offset, u_int16_t data) 1086 { 1087 int i; 1088 1089 /* 1090 * Erase/write enable. 1091 */ 1092 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 1093 fxp_eeprom_shiftin(sc, 0x4, 3); 1094 fxp_eeprom_shiftin(sc, 0x03 << (sc->eeprom_size - 2), sc->eeprom_size); 1095 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 1096 DELAY(1); 1097 /* 1098 * Shift in write opcode, address, data. 1099 */ 1100 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 1101 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_WRITE, 3); 1102 fxp_eeprom_shiftin(sc, offset, sc->eeprom_size); 1103 fxp_eeprom_shiftin(sc, data, 16); 1104 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 1105 DELAY(1); 1106 /* 1107 * Wait for EEPROM to finish up. 1108 */ 1109 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 1110 DELAY(1); 1111 for (i = 0; i < 1000; i++) { 1112 if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO) 1113 break; 1114 DELAY(50); 1115 } 1116 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 1117 DELAY(1); 1118 /* 1119 * Erase/write disable. 1120 */ 1121 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 1122 fxp_eeprom_shiftin(sc, 0x4, 3); 1123 fxp_eeprom_shiftin(sc, 0, sc->eeprom_size); 1124 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 1125 DELAY(1); 1126 } 1127 1128 /* 1129 * From NetBSD: 1130 * 1131 * Figure out EEPROM size. 1132 * 1133 * 559's can have either 64-word or 256-word EEPROMs, the 558 1134 * datasheet only talks about 64-word EEPROMs, and the 557 datasheet 1135 * talks about the existance of 16 to 256 word EEPROMs. 1136 * 1137 * The only known sizes are 64 and 256, where the 256 version is used 1138 * by CardBus cards to store CIS information. 1139 * 1140 * The address is shifted in msb-to-lsb, and after the last 1141 * address-bit the EEPROM is supposed to output a `dummy zero' bit, 1142 * after which follows the actual data. We try to detect this zero, by 1143 * probing the data-out bit in the EEPROM control register just after 1144 * having shifted in a bit. If the bit is zero, we assume we've 1145 * shifted enough address bits. The data-out should be tri-state, 1146 * before this, which should translate to a logical one. 1147 */ 1148 static void 1149 fxp_autosize_eeprom(struct fxp_softc *sc) 1150 { 1151 1152 /* guess maximum size of 256 words */ 1153 sc->eeprom_size = 8; 1154 1155 /* autosize */ 1156 (void) fxp_eeprom_getword(sc, 0, 1); 1157 } 1158 1159 static void 1160 fxp_read_eeprom(struct fxp_softc *sc, u_short *data, int offset, int words) 1161 { 1162 int i; 1163 1164 for (i = 0; i < words; i++) 1165 data[i] = fxp_eeprom_getword(sc, offset + i, 0); 1166 } 1167 1168 static void 1169 fxp_write_eeprom(struct fxp_softc *sc, u_short *data, int offset, int words) 1170 { 1171 int i; 1172 1173 for (i = 0; i < words; i++) 1174 fxp_eeprom_putword(sc, offset + i, data[i]); 1175 } 1176 1177 static void 1178 fxp_dma_map_txbuf(void *arg, bus_dma_segment_t *segs, int nseg, 1179 bus_size_t mapsize, int error) 1180 { 1181 struct fxp_softc *sc; 1182 struct fxp_cb_tx *txp; 1183 int i; 1184 1185 if (error) 1186 return; 1187 1188 KASSERT(nseg <= FXP_NTXSEG, ("too many DMA segments")); 1189 1190 sc = arg; 1191 txp = sc->fxp_desc.tx_last->tx_next->tx_cb; 1192 for (i = 0; i < nseg; i++) { 1193 KASSERT(segs[i].ds_len <= MCLBYTES, ("segment size too large")); 1194 /* 1195 * If this is an 82550/82551, then we're using extended 1196 * TxCBs _and_ we're using checksum offload. This means 1197 * that the TxCB is really an IPCB. One major difference 1198 * between the two is that with plain extended TxCBs, 1199 * the bottom half of the TxCB contains two entries from 1200 * the TBD array, whereas IPCBs contain just one entry: 1201 * one entry (8 bytes) has been sacrificed for the TCP/IP 1202 * checksum offload control bits. So to make things work 1203 * right, we have to start filling in the TBD array 1204 * starting from a different place depending on whether 1205 * the chip is an 82550/82551 or not. 1206 */ 1207 if (sc->flags & FXP_FLAG_EXT_RFA) { 1208 txp->tbd[i + 1].tb_addr = htole32(segs[i].ds_addr); 1209 txp->tbd[i + 1].tb_size = htole32(segs[i].ds_len); 1210 } else { 1211 txp->tbd[i].tb_addr = htole32(segs[i].ds_addr); 1212 txp->tbd[i].tb_size = htole32(segs[i].ds_len); 1213 } 1214 } 1215 txp->tbd_number = nseg; 1216 } 1217 1218 /* 1219 * Grab the softc lock and call the real fxp_start_body() routine 1220 */ 1221 static void 1222 fxp_start(struct ifnet *ifp) 1223 { 1224 struct fxp_softc *sc = ifp->if_softc; 1225 1226 FXP_LOCK(sc); 1227 fxp_start_body(ifp); 1228 FXP_UNLOCK(sc); 1229 } 1230 1231 /* 1232 * Start packet transmission on the interface. 1233 * This routine must be called with the softc lock held, and is an 1234 * internal entry point only. 1235 */ 1236 static void 1237 fxp_start_body(struct ifnet *ifp) 1238 { 1239 struct fxp_softc *sc = ifp->if_softc; 1240 struct fxp_tx *txp; 1241 struct mbuf *mb_head; 1242 int error; 1243 1244 FXP_LOCK_ASSERT(sc, MA_OWNED); 1245 /* 1246 * See if we need to suspend xmit until the multicast filter 1247 * has been reprogrammed (which can only be done at the head 1248 * of the command chain). 1249 */ 1250 if (sc->need_mcsetup) { 1251 return; 1252 } 1253 1254 txp = NULL; 1255 1256 /* 1257 * We're finished if there is nothing more to add to the list or if 1258 * we're all filled up with buffers to transmit. 1259 * NOTE: One TxCB is reserved to guarantee that fxp_mc_setup() can add 1260 * a NOP command when needed. 1261 */ 1262 while (!IFQ_DRV_IS_EMPTY(&ifp->if_snd) && 1263 sc->tx_queued < FXP_NTXCB - 1) { 1264 1265 /* 1266 * Grab a packet to transmit. 1267 */ 1268 IFQ_DRV_DEQUEUE(&ifp->if_snd, mb_head); 1269 if (mb_head == NULL) 1270 break; 1271 1272 /* 1273 * Get pointer to next available tx desc. 1274 */ 1275 txp = sc->fxp_desc.tx_last->tx_next; 1276 1277 /* 1278 * A note in Appendix B of the Intel 8255x 10/100 Mbps 1279 * Ethernet Controller Family Open Source Software 1280 * Developer Manual says: 1281 * Using software parsing is only allowed with legal 1282 * TCP/IP or UDP/IP packets. 1283 * ... 1284 * For all other datagrams, hardware parsing must 1285 * be used. 1286 * Software parsing appears to truncate ICMP and 1287 * fragmented UDP packets that contain one to three 1288 * bytes in the second (and final) mbuf of the packet. 1289 */ 1290 if (sc->flags & FXP_FLAG_EXT_RFA) 1291 txp->tx_cb->ipcb_ip_activation_high = 1292 FXP_IPCB_HARDWAREPARSING_ENABLE; 1293 1294 /* 1295 * Deal with TCP/IP checksum offload. Note that 1296 * in order for TCP checksum offload to work, 1297 * the pseudo header checksum must have already 1298 * been computed and stored in the checksum field 1299 * in the TCP header. The stack should have 1300 * already done this for us. 1301 */ 1302 1303 if (mb_head->m_pkthdr.csum_flags) { 1304 if (mb_head->m_pkthdr.csum_flags & CSUM_DELAY_DATA) { 1305 txp->tx_cb->ipcb_ip_schedule = 1306 FXP_IPCB_TCPUDP_CHECKSUM_ENABLE; 1307 if (mb_head->m_pkthdr.csum_flags & CSUM_TCP) 1308 txp->tx_cb->ipcb_ip_schedule |= 1309 FXP_IPCB_TCP_PACKET; 1310 } 1311 #ifdef FXP_IP_CSUM_WAR 1312 /* 1313 * XXX The 82550 chip appears to have trouble 1314 * dealing with IP header checksums in very small 1315 * datagrams, namely fragments from 1 to 3 bytes 1316 * in size. For example, say you want to transmit 1317 * a UDP packet of 1473 bytes. The packet will be 1318 * fragmented over two IP datagrams, the latter 1319 * containing only one byte of data. The 82550 will 1320 * botch the header checksum on the 1-byte fragment. 1321 * As long as the datagram contains 4 or more bytes 1322 * of data, you're ok. 1323 * 1324 * The following code attempts to work around this 1325 * problem: if the datagram is less than 38 bytes 1326 * in size (14 bytes ether header, 20 bytes IP header, 1327 * plus 4 bytes of data), we punt and compute the IP 1328 * header checksum by hand. This workaround doesn't 1329 * work very well, however, since it can be fooled 1330 * by things like VLAN tags and IP options that make 1331 * the header sizes/offsets vary. 1332 */ 1333 1334 if (mb_head->m_pkthdr.csum_flags & CSUM_IP) { 1335 if (mb_head->m_pkthdr.len < 38) { 1336 struct ip *ip; 1337 mb_head->m_data += ETHER_HDR_LEN; 1338 ip = mtod(mb_head, struct ip *); 1339 ip->ip_sum = in_cksum(mb_head, 1340 ip->ip_hl << 2); 1341 mb_head->m_data -= ETHER_HDR_LEN; 1342 } else { 1343 txp->tx_cb->ipcb_ip_activation_high = 1344 FXP_IPCB_HARDWAREPARSING_ENABLE; 1345 txp->tx_cb->ipcb_ip_schedule |= 1346 FXP_IPCB_IP_CHECKSUM_ENABLE; 1347 } 1348 } 1349 #endif 1350 } 1351 1352 /* 1353 * Go through each of the mbufs in the chain and initialize 1354 * the transmit buffer descriptors with the physical address 1355 * and size of the mbuf. 1356 */ 1357 error = bus_dmamap_load_mbuf(sc->fxp_mtag, txp->tx_map, 1358 mb_head, fxp_dma_map_txbuf, sc, 0); 1359 1360 if (error && error != EFBIG) { 1361 device_printf(sc->dev, "can't map mbuf (error %d)\n", 1362 error); 1363 m_freem(mb_head); 1364 break; 1365 } 1366 1367 if (error) { 1368 struct mbuf *mn; 1369 1370 /* 1371 * We ran out of segments. We have to recopy this 1372 * mbuf chain first. Bail out if we can't get the 1373 * new buffers. 1374 */ 1375 mn = m_defrag(mb_head, M_DONTWAIT); 1376 if (mn == NULL) { 1377 m_freem(mb_head); 1378 break; 1379 } else { 1380 mb_head = mn; 1381 } 1382 error = bus_dmamap_load_mbuf(sc->fxp_mtag, txp->tx_map, 1383 mb_head, fxp_dma_map_txbuf, sc, 0); 1384 if (error) { 1385 device_printf(sc->dev, 1386 "can't map mbuf (error %d)\n", error); 1387 m_freem(mb_head); 1388 break; 1389 } 1390 } 1391 1392 bus_dmamap_sync(sc->fxp_mtag, txp->tx_map, 1393 BUS_DMASYNC_PREWRITE); 1394 1395 txp->tx_mbuf = mb_head; 1396 txp->tx_cb->cb_status = 0; 1397 txp->tx_cb->byte_count = 0; 1398 if (sc->tx_queued != FXP_CXINT_THRESH - 1) { 1399 txp->tx_cb->cb_command = 1400 htole16(sc->tx_cmd | FXP_CB_COMMAND_SF | 1401 FXP_CB_COMMAND_S); 1402 } else { 1403 txp->tx_cb->cb_command = 1404 htole16(sc->tx_cmd | FXP_CB_COMMAND_SF | 1405 FXP_CB_COMMAND_S | FXP_CB_COMMAND_I); 1406 /* 1407 * Set a 5 second timer just in case we don't hear 1408 * from the card again. 1409 */ 1410 ifp->if_timer = 5; 1411 } 1412 txp->tx_cb->tx_threshold = tx_threshold; 1413 1414 /* 1415 * Advance the end of list forward. 1416 */ 1417 1418 #ifdef __alpha__ 1419 /* 1420 * On platforms which can't access memory in 16-bit 1421 * granularities, we must prevent the card from DMA'ing 1422 * up the status while we update the command field. 1423 * This could cause us to overwrite the completion status. 1424 * XXX This is probably bogus and we're _not_ looking 1425 * for atomicity here. 1426 */ 1427 atomic_clear_16(&sc->fxp_desc.tx_last->tx_cb->cb_command, 1428 htole16(FXP_CB_COMMAND_S)); 1429 #else 1430 sc->fxp_desc.tx_last->tx_cb->cb_command &= 1431 htole16(~FXP_CB_COMMAND_S); 1432 #endif /*__alpha__*/ 1433 sc->fxp_desc.tx_last = txp; 1434 1435 /* 1436 * Advance the beginning of the list forward if there are 1437 * no other packets queued (when nothing is queued, tx_first 1438 * sits on the last TxCB that was sent out). 1439 */ 1440 if (sc->tx_queued == 0) 1441 sc->fxp_desc.tx_first = txp; 1442 1443 sc->tx_queued++; 1444 1445 /* 1446 * Pass packet to bpf if there is a listener. 1447 */ 1448 BPF_MTAP(ifp, mb_head); 1449 } 1450 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE); 1451 1452 /* 1453 * We're finished. If we added to the list, issue a RESUME to get DMA 1454 * going again if suspended. 1455 */ 1456 if (txp != NULL) { 1457 fxp_scb_wait(sc); 1458 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_RESUME); 1459 } 1460 } 1461 1462 #ifdef DEVICE_POLLING 1463 static poll_handler_t fxp_poll; 1464 1465 static void 1466 fxp_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 1467 { 1468 struct fxp_softc *sc = ifp->if_softc; 1469 u_int8_t statack; 1470 1471 FXP_LOCK(sc); 1472 if (!(ifp->if_capenable & IFCAP_POLLING)) { 1473 ether_poll_deregister(ifp); 1474 cmd = POLL_DEREGISTER; 1475 } 1476 if (cmd == POLL_DEREGISTER) { /* final call, enable interrupts */ 1477 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, 0); 1478 FXP_UNLOCK(sc); 1479 return; 1480 } 1481 statack = FXP_SCB_STATACK_CXTNO | FXP_SCB_STATACK_CNA | 1482 FXP_SCB_STATACK_FR; 1483 if (cmd == POLL_AND_CHECK_STATUS) { 1484 u_int8_t tmp; 1485 1486 tmp = CSR_READ_1(sc, FXP_CSR_SCB_STATACK); 1487 if (tmp == 0xff || tmp == 0) { 1488 FXP_UNLOCK(sc); 1489 return; /* nothing to do */ 1490 } 1491 tmp &= ~statack; 1492 /* ack what we can */ 1493 if (tmp != 0) 1494 CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, tmp); 1495 statack |= tmp; 1496 } 1497 fxp_intr_body(sc, ifp, statack, count); 1498 FXP_UNLOCK(sc); 1499 } 1500 #endif /* DEVICE_POLLING */ 1501 1502 /* 1503 * Process interface interrupts. 1504 */ 1505 static void 1506 fxp_intr(void *xsc) 1507 { 1508 struct fxp_softc *sc = xsc; 1509 struct ifnet *ifp = &sc->sc_if; 1510 u_int8_t statack; 1511 1512 FXP_LOCK(sc); 1513 if (sc->suspended) { 1514 FXP_UNLOCK(sc); 1515 return; 1516 } 1517 1518 #ifdef DEVICE_POLLING 1519 if (ifp->if_flags & IFF_POLLING) { 1520 FXP_UNLOCK(sc); 1521 return; 1522 } 1523 if ((ifp->if_capenable & IFCAP_POLLING) && 1524 ether_poll_register(fxp_poll, ifp)) { 1525 /* disable interrupts */ 1526 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE); 1527 FXP_UNLOCK(sc); 1528 fxp_poll(ifp, 0, 1); 1529 return; 1530 } 1531 #endif 1532 while ((statack = CSR_READ_1(sc, FXP_CSR_SCB_STATACK)) != 0) { 1533 /* 1534 * It should not be possible to have all bits set; the 1535 * FXP_SCB_INTR_SWI bit always returns 0 on a read. If 1536 * all bits are set, this may indicate that the card has 1537 * been physically ejected, so ignore it. 1538 */ 1539 if (statack == 0xff) { 1540 FXP_UNLOCK(sc); 1541 return; 1542 } 1543 1544 /* 1545 * First ACK all the interrupts in this pass. 1546 */ 1547 CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, statack); 1548 fxp_intr_body(sc, ifp, statack, -1); 1549 } 1550 FXP_UNLOCK(sc); 1551 } 1552 1553 static void 1554 fxp_txeof(struct fxp_softc *sc) 1555 { 1556 struct fxp_tx *txp; 1557 1558 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREREAD); 1559 for (txp = sc->fxp_desc.tx_first; sc->tx_queued && 1560 (le16toh(txp->tx_cb->cb_status) & FXP_CB_STATUS_C) != 0; 1561 txp = txp->tx_next) { 1562 if (txp->tx_mbuf != NULL) { 1563 bus_dmamap_sync(sc->fxp_mtag, txp->tx_map, 1564 BUS_DMASYNC_POSTWRITE); 1565 bus_dmamap_unload(sc->fxp_mtag, txp->tx_map); 1566 m_freem(txp->tx_mbuf); 1567 txp->tx_mbuf = NULL; 1568 /* clear this to reset csum offload bits */ 1569 txp->tx_cb->tbd[0].tb_addr = 0; 1570 } 1571 sc->tx_queued--; 1572 } 1573 sc->fxp_desc.tx_first = txp; 1574 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE); 1575 } 1576 1577 static void 1578 fxp_intr_body(struct fxp_softc *sc, struct ifnet *ifp, u_int8_t statack, 1579 int count) 1580 { 1581 struct mbuf *m; 1582 struct fxp_rx *rxp; 1583 struct fxp_rfa *rfa; 1584 int rnr = (statack & FXP_SCB_STATACK_RNR) ? 1 : 0; 1585 1586 FXP_LOCK_ASSERT(sc, MA_OWNED); 1587 if (rnr) 1588 sc->rnr++; 1589 #ifdef DEVICE_POLLING 1590 /* Pick up a deferred RNR condition if `count' ran out last time. */ 1591 if (sc->flags & FXP_FLAG_DEFERRED_RNR) { 1592 sc->flags &= ~FXP_FLAG_DEFERRED_RNR; 1593 rnr = 1; 1594 } 1595 #endif 1596 1597 /* 1598 * Free any finished transmit mbuf chains. 1599 * 1600 * Handle the CNA event likt a CXTNO event. It used to 1601 * be that this event (control unit not ready) was not 1602 * encountered, but it is now with the SMPng modifications. 1603 * The exact sequence of events that occur when the interface 1604 * is brought up are different now, and if this event 1605 * goes unhandled, the configuration/rxfilter setup sequence 1606 * can stall for several seconds. The result is that no 1607 * packets go out onto the wire for about 5 to 10 seconds 1608 * after the interface is ifconfig'ed for the first time. 1609 */ 1610 if (statack & (FXP_SCB_STATACK_CXTNO | FXP_SCB_STATACK_CNA)) { 1611 fxp_txeof(sc); 1612 1613 ifp->if_timer = 0; 1614 if (sc->tx_queued == 0) { 1615 if (sc->need_mcsetup) 1616 fxp_mc_setup(sc); 1617 } 1618 /* 1619 * Try to start more packets transmitting. 1620 */ 1621 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1622 fxp_start_body(ifp); 1623 } 1624 1625 /* 1626 * Just return if nothing happened on the receive side. 1627 */ 1628 if (!rnr && (statack & FXP_SCB_STATACK_FR) == 0) 1629 return; 1630 1631 /* 1632 * Process receiver interrupts. If a no-resource (RNR) 1633 * condition exists, get whatever packets we can and 1634 * re-start the receiver. 1635 * 1636 * When using polling, we do not process the list to completion, 1637 * so when we get an RNR interrupt we must defer the restart 1638 * until we hit the last buffer with the C bit set. 1639 * If we run out of cycles and rfa_headm has the C bit set, 1640 * record the pending RNR in the FXP_FLAG_DEFERRED_RNR flag so 1641 * that the info will be used in the subsequent polling cycle. 1642 */ 1643 for (;;) { 1644 rxp = sc->fxp_desc.rx_head; 1645 m = rxp->rx_mbuf; 1646 rfa = (struct fxp_rfa *)(m->m_ext.ext_buf + 1647 RFA_ALIGNMENT_FUDGE); 1648 bus_dmamap_sync(sc->fxp_mtag, rxp->rx_map, 1649 BUS_DMASYNC_POSTREAD); 1650 1651 #ifdef DEVICE_POLLING /* loop at most count times if count >=0 */ 1652 if (count >= 0 && count-- == 0) { 1653 if (rnr) { 1654 /* Defer RNR processing until the next time. */ 1655 sc->flags |= FXP_FLAG_DEFERRED_RNR; 1656 rnr = 0; 1657 } 1658 break; 1659 } 1660 #endif /* DEVICE_POLLING */ 1661 1662 if ((le16toh(rfa->rfa_status) & FXP_RFA_STATUS_C) == 0) 1663 break; 1664 1665 /* 1666 * Advance head forward. 1667 */ 1668 sc->fxp_desc.rx_head = rxp->rx_next; 1669 1670 /* 1671 * Add a new buffer to the receive chain. 1672 * If this fails, the old buffer is recycled 1673 * instead. 1674 */ 1675 if (fxp_add_rfabuf(sc, rxp) == 0) { 1676 int total_len; 1677 1678 /* 1679 * Fetch packet length (the top 2 bits of 1680 * actual_size are flags set by the controller 1681 * upon completion), and drop the packet in case 1682 * of bogus length or CRC errors. 1683 */ 1684 total_len = le16toh(rfa->actual_size) & 0x3fff; 1685 if (total_len < sizeof(struct ether_header) || 1686 total_len > MCLBYTES - RFA_ALIGNMENT_FUDGE - 1687 sc->rfa_size || 1688 le16toh(rfa->rfa_status) & FXP_RFA_STATUS_CRC) { 1689 m_freem(m); 1690 continue; 1691 } 1692 1693 /* Do IP checksum checking. */ 1694 if (le16toh(rfa->rfa_status) & FXP_RFA_STATUS_PARSE) { 1695 if (rfa->rfax_csum_sts & 1696 FXP_RFDX_CS_IP_CSUM_BIT_VALID) 1697 m->m_pkthdr.csum_flags |= 1698 CSUM_IP_CHECKED; 1699 if (rfa->rfax_csum_sts & 1700 FXP_RFDX_CS_IP_CSUM_VALID) 1701 m->m_pkthdr.csum_flags |= 1702 CSUM_IP_VALID; 1703 if ((rfa->rfax_csum_sts & 1704 FXP_RFDX_CS_TCPUDP_CSUM_BIT_VALID) && 1705 (rfa->rfax_csum_sts & 1706 FXP_RFDX_CS_TCPUDP_CSUM_VALID)) { 1707 m->m_pkthdr.csum_flags |= 1708 CSUM_DATA_VALID|CSUM_PSEUDO_HDR; 1709 m->m_pkthdr.csum_data = 0xffff; 1710 } 1711 } 1712 1713 m->m_pkthdr.len = m->m_len = total_len; 1714 m->m_pkthdr.rcvif = ifp; 1715 1716 /* 1717 * Drop locks before calling if_input() since it 1718 * may re-enter fxp_start() in the netisr case. 1719 * This would result in a lock reversal. Better 1720 * performance might be obtained by chaining all 1721 * packets received, dropping the lock, and then 1722 * calling if_input() on each one. 1723 */ 1724 FXP_UNLOCK(sc); 1725 (*ifp->if_input)(ifp, m); 1726 FXP_LOCK(sc); 1727 } 1728 } 1729 if (rnr) { 1730 fxp_scb_wait(sc); 1731 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 1732 sc->fxp_desc.rx_head->rx_addr); 1733 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_START); 1734 } 1735 } 1736 1737 /* 1738 * Update packet in/out/collision statistics. The i82557 doesn't 1739 * allow you to access these counters without doing a fairly 1740 * expensive DMA to get _all_ of the statistics it maintains, so 1741 * we do this operation here only once per second. The statistics 1742 * counters in the kernel are updated from the previous dump-stats 1743 * DMA and then a new dump-stats DMA is started. The on-chip 1744 * counters are zeroed when the DMA completes. If we can't start 1745 * the DMA immediately, we don't wait - we just prepare to read 1746 * them again next time. 1747 */ 1748 static void 1749 fxp_tick(void *xsc) 1750 { 1751 struct fxp_softc *sc = xsc; 1752 struct ifnet *ifp = &sc->sc_if; 1753 struct fxp_stats *sp = sc->fxp_stats; 1754 int s; 1755 1756 FXP_LOCK(sc); 1757 s = splimp(); 1758 bus_dmamap_sync(sc->fxp_stag, sc->fxp_smap, BUS_DMASYNC_POSTREAD); 1759 ifp->if_opackets += le32toh(sp->tx_good); 1760 ifp->if_collisions += le32toh(sp->tx_total_collisions); 1761 if (sp->rx_good) { 1762 ifp->if_ipackets += le32toh(sp->rx_good); 1763 sc->rx_idle_secs = 0; 1764 } else { 1765 /* 1766 * Receiver's been idle for another second. 1767 */ 1768 sc->rx_idle_secs++; 1769 } 1770 ifp->if_ierrors += 1771 le32toh(sp->rx_crc_errors) + 1772 le32toh(sp->rx_alignment_errors) + 1773 le32toh(sp->rx_rnr_errors) + 1774 le32toh(sp->rx_overrun_errors); 1775 /* 1776 * If any transmit underruns occured, bump up the transmit 1777 * threshold by another 512 bytes (64 * 8). 1778 */ 1779 if (sp->tx_underruns) { 1780 ifp->if_oerrors += le32toh(sp->tx_underruns); 1781 if (tx_threshold < 192) 1782 tx_threshold += 64; 1783 } 1784 1785 /* 1786 * Release any xmit buffers that have completed DMA. This isn't 1787 * strictly necessary to do here, but it's advantagous for mbufs 1788 * with external storage to be released in a timely manner rather 1789 * than being defered for a potentially long time. This limits 1790 * the delay to a maximum of one second. 1791 */ 1792 fxp_txeof(sc); 1793 1794 /* 1795 * If we haven't received any packets in FXP_MAC_RX_IDLE seconds, 1796 * then assume the receiver has locked up and attempt to clear 1797 * the condition by reprogramming the multicast filter. This is 1798 * a work-around for a bug in the 82557 where the receiver locks 1799 * up if it gets certain types of garbage in the syncronization 1800 * bits prior to the packet header. This bug is supposed to only 1801 * occur in 10Mbps mode, but has been seen to occur in 100Mbps 1802 * mode as well (perhaps due to a 10/100 speed transition). 1803 */ 1804 if (sc->rx_idle_secs > FXP_MAX_RX_IDLE) { 1805 sc->rx_idle_secs = 0; 1806 fxp_mc_setup(sc); 1807 } 1808 /* 1809 * If there is no pending command, start another stats 1810 * dump. Otherwise punt for now. 1811 */ 1812 if (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) == 0) { 1813 /* 1814 * Start another stats dump. 1815 */ 1816 bus_dmamap_sync(sc->fxp_stag, sc->fxp_smap, 1817 BUS_DMASYNC_PREREAD); 1818 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_DUMPRESET); 1819 } else { 1820 /* 1821 * A previous command is still waiting to be accepted. 1822 * Just zero our copy of the stats and wait for the 1823 * next timer event to update them. 1824 */ 1825 sp->tx_good = 0; 1826 sp->tx_underruns = 0; 1827 sp->tx_total_collisions = 0; 1828 1829 sp->rx_good = 0; 1830 sp->rx_crc_errors = 0; 1831 sp->rx_alignment_errors = 0; 1832 sp->rx_rnr_errors = 0; 1833 sp->rx_overrun_errors = 0; 1834 } 1835 if (sc->miibus != NULL) 1836 mii_tick(device_get_softc(sc->miibus)); 1837 1838 /* 1839 * Schedule another timeout one second from now. 1840 */ 1841 callout_reset(&sc->stat_ch, hz, fxp_tick, sc); 1842 FXP_UNLOCK(sc); 1843 splx(s); 1844 } 1845 1846 /* 1847 * Stop the interface. Cancels the statistics updater and resets 1848 * the interface. 1849 */ 1850 static void 1851 fxp_stop(struct fxp_softc *sc) 1852 { 1853 struct ifnet *ifp = &sc->sc_if; 1854 struct fxp_tx *txp; 1855 int i; 1856 1857 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1858 ifp->if_timer = 0; 1859 1860 #ifdef DEVICE_POLLING 1861 ether_poll_deregister(ifp); 1862 #endif 1863 /* 1864 * Cancel stats updater. 1865 */ 1866 callout_stop(&sc->stat_ch); 1867 1868 /* 1869 * Issue software reset, which also unloads the microcode. 1870 */ 1871 sc->flags &= ~FXP_FLAG_UCODE; 1872 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SOFTWARE_RESET); 1873 DELAY(50); 1874 1875 /* 1876 * Release any xmit buffers. 1877 */ 1878 txp = sc->fxp_desc.tx_list; 1879 if (txp != NULL) { 1880 for (i = 0; i < FXP_NTXCB; i++) { 1881 if (txp[i].tx_mbuf != NULL) { 1882 bus_dmamap_sync(sc->fxp_mtag, txp[i].tx_map, 1883 BUS_DMASYNC_POSTWRITE); 1884 bus_dmamap_unload(sc->fxp_mtag, txp[i].tx_map); 1885 m_freem(txp[i].tx_mbuf); 1886 txp[i].tx_mbuf = NULL; 1887 /* clear this to reset csum offload bits */ 1888 txp[i].tx_cb->tbd[0].tb_addr = 0; 1889 } 1890 } 1891 } 1892 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE); 1893 sc->tx_queued = 0; 1894 } 1895 1896 /* 1897 * Watchdog/transmission transmit timeout handler. Called when a 1898 * transmission is started on the interface, but no interrupt is 1899 * received before the timeout. This usually indicates that the 1900 * card has wedged for some reason. 1901 */ 1902 static void 1903 fxp_watchdog(struct ifnet *ifp) 1904 { 1905 struct fxp_softc *sc = ifp->if_softc; 1906 1907 FXP_LOCK(sc); 1908 device_printf(sc->dev, "device timeout\n"); 1909 ifp->if_oerrors++; 1910 1911 fxp_init_body(sc); 1912 FXP_UNLOCK(sc); 1913 } 1914 1915 /* 1916 * Acquire locks and then call the real initialization function. This 1917 * is necessary because ether_ioctl() calls if_init() and this would 1918 * result in mutex recursion if the mutex was held. 1919 */ 1920 static void 1921 fxp_init(void *xsc) 1922 { 1923 struct fxp_softc *sc = xsc; 1924 1925 FXP_LOCK(sc); 1926 fxp_init_body(sc); 1927 FXP_UNLOCK(sc); 1928 } 1929 1930 /* 1931 * Perform device initialization. This routine must be called with the 1932 * softc lock held. 1933 */ 1934 static void 1935 fxp_init_body(struct fxp_softc *sc) 1936 { 1937 struct ifnet *ifp = &sc->sc_if; 1938 struct fxp_cb_config *cbp; 1939 struct fxp_cb_ias *cb_ias; 1940 struct fxp_cb_tx *tcbp; 1941 struct fxp_tx *txp; 1942 struct fxp_cb_mcs *mcsp; 1943 int i, prm, s; 1944 1945 FXP_LOCK_ASSERT(sc, MA_OWNED); 1946 s = splimp(); 1947 /* 1948 * Cancel any pending I/O 1949 */ 1950 fxp_stop(sc); 1951 1952 prm = (ifp->if_flags & IFF_PROMISC) ? 1 : 0; 1953 1954 /* 1955 * Initialize base of CBL and RFA memory. Loading with zero 1956 * sets it up for regular linear addressing. 1957 */ 1958 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 0); 1959 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_BASE); 1960 1961 fxp_scb_wait(sc); 1962 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_BASE); 1963 1964 /* 1965 * Initialize base of dump-stats buffer. 1966 */ 1967 fxp_scb_wait(sc); 1968 bus_dmamap_sync(sc->fxp_stag, sc->fxp_smap, BUS_DMASYNC_PREREAD); 1969 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->stats_addr); 1970 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_DUMP_ADR); 1971 1972 /* 1973 * Attempt to load microcode if requested. 1974 */ 1975 if (ifp->if_flags & IFF_LINK0 && (sc->flags & FXP_FLAG_UCODE) == 0) 1976 fxp_load_ucode(sc); 1977 1978 /* 1979 * Initialize the multicast address list. 1980 */ 1981 if (fxp_mc_addrs(sc)) { 1982 mcsp = sc->mcsp; 1983 mcsp->cb_status = 0; 1984 mcsp->cb_command = 1985 htole16(FXP_CB_COMMAND_MCAS | FXP_CB_COMMAND_EL); 1986 mcsp->link_addr = 0xffffffff; 1987 /* 1988 * Start the multicast setup command. 1989 */ 1990 fxp_scb_wait(sc); 1991 bus_dmamap_sync(sc->mcs_tag, sc->mcs_map, BUS_DMASYNC_PREWRITE); 1992 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->mcs_addr); 1993 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 1994 /* ...and wait for it to complete. */ 1995 fxp_dma_wait(sc, &mcsp->cb_status, sc->mcs_tag, sc->mcs_map); 1996 bus_dmamap_sync(sc->mcs_tag, sc->mcs_map, 1997 BUS_DMASYNC_POSTWRITE); 1998 } 1999 2000 /* 2001 * We temporarily use memory that contains the TxCB list to 2002 * construct the config CB. The TxCB list memory is rebuilt 2003 * later. 2004 */ 2005 cbp = (struct fxp_cb_config *)sc->fxp_desc.cbl_list; 2006 2007 /* 2008 * This bcopy is kind of disgusting, but there are a bunch of must be 2009 * zero and must be one bits in this structure and this is the easiest 2010 * way to initialize them all to proper values. 2011 */ 2012 bcopy(fxp_cb_config_template, cbp, sizeof(fxp_cb_config_template)); 2013 2014 cbp->cb_status = 0; 2015 cbp->cb_command = htole16(FXP_CB_COMMAND_CONFIG | 2016 FXP_CB_COMMAND_EL); 2017 cbp->link_addr = 0xffffffff; /* (no) next command */ 2018 cbp->byte_count = sc->flags & FXP_FLAG_EXT_RFA ? 32 : 22; 2019 cbp->rx_fifo_limit = 8; /* rx fifo threshold (32 bytes) */ 2020 cbp->tx_fifo_limit = 0; /* tx fifo threshold (0 bytes) */ 2021 cbp->adaptive_ifs = 0; /* (no) adaptive interframe spacing */ 2022 cbp->mwi_enable = sc->flags & FXP_FLAG_MWI_ENABLE ? 1 : 0; 2023 cbp->type_enable = 0; /* actually reserved */ 2024 cbp->read_align_en = sc->flags & FXP_FLAG_READ_ALIGN ? 1 : 0; 2025 cbp->end_wr_on_cl = sc->flags & FXP_FLAG_WRITE_ALIGN ? 1 : 0; 2026 cbp->rx_dma_bytecount = 0; /* (no) rx DMA max */ 2027 cbp->tx_dma_bytecount = 0; /* (no) tx DMA max */ 2028 cbp->dma_mbce = 0; /* (disable) dma max counters */ 2029 cbp->late_scb = 0; /* (don't) defer SCB update */ 2030 cbp->direct_dma_dis = 1; /* disable direct rcv dma mode */ 2031 cbp->tno_int_or_tco_en =0; /* (disable) tx not okay interrupt */ 2032 cbp->ci_int = 1; /* interrupt on CU idle */ 2033 cbp->ext_txcb_dis = sc->flags & FXP_FLAG_EXT_TXCB ? 0 : 1; 2034 cbp->ext_stats_dis = 1; /* disable extended counters */ 2035 cbp->keep_overrun_rx = 0; /* don't pass overrun frames to host */ 2036 cbp->save_bf = sc->flags & FXP_FLAG_SAVE_BAD ? 1 : prm; 2037 cbp->disc_short_rx = !prm; /* discard short packets */ 2038 cbp->underrun_retry = 1; /* retry mode (once) on DMA underrun */ 2039 cbp->two_frames = 0; /* do not limit FIFO to 2 frames */ 2040 cbp->dyn_tbd = 0; /* (no) dynamic TBD mode */ 2041 cbp->ext_rfa = sc->flags & FXP_FLAG_EXT_RFA ? 1 : 0; 2042 cbp->mediatype = sc->flags & FXP_FLAG_SERIAL_MEDIA ? 0 : 1; 2043 cbp->csma_dis = 0; /* (don't) disable link */ 2044 cbp->tcp_udp_cksum = 0; /* (don't) enable checksum */ 2045 cbp->vlan_tco = 0; /* (don't) enable vlan wakeup */ 2046 cbp->link_wake_en = 0; /* (don't) assert PME# on link change */ 2047 cbp->arp_wake_en = 0; /* (don't) assert PME# on arp */ 2048 cbp->mc_wake_en = 0; /* (don't) enable PME# on mcmatch */ 2049 cbp->nsai = 1; /* (don't) disable source addr insert */ 2050 cbp->preamble_length = 2; /* (7 byte) preamble */ 2051 cbp->loopback = 0; /* (don't) loopback */ 2052 cbp->linear_priority = 0; /* (normal CSMA/CD operation) */ 2053 cbp->linear_pri_mode = 0; /* (wait after xmit only) */ 2054 cbp->interfrm_spacing = 6; /* (96 bits of) interframe spacing */ 2055 cbp->promiscuous = prm; /* promiscuous mode */ 2056 cbp->bcast_disable = 0; /* (don't) disable broadcasts */ 2057 cbp->wait_after_win = 0; /* (don't) enable modified backoff alg*/ 2058 cbp->ignore_ul = 0; /* consider U/L bit in IA matching */ 2059 cbp->crc16_en = 0; /* (don't) enable crc-16 algorithm */ 2060 cbp->crscdt = sc->flags & FXP_FLAG_SERIAL_MEDIA ? 1 : 0; 2061 2062 cbp->stripping = !prm; /* truncate rx packet to byte count */ 2063 cbp->padding = 1; /* (do) pad short tx packets */ 2064 cbp->rcv_crc_xfer = 0; /* (don't) xfer CRC to host */ 2065 cbp->long_rx_en = sc->flags & FXP_FLAG_LONG_PKT_EN ? 1 : 0; 2066 cbp->ia_wake_en = 0; /* (don't) wake up on address match */ 2067 cbp->magic_pkt_dis = 0; /* (don't) disable magic packet */ 2068 /* must set wake_en in PMCSR also */ 2069 cbp->force_fdx = 0; /* (don't) force full duplex */ 2070 cbp->fdx_pin_en = 1; /* (enable) FDX# pin */ 2071 cbp->multi_ia = 0; /* (don't) accept multiple IAs */ 2072 cbp->mc_all = sc->flags & FXP_FLAG_ALL_MCAST ? 1 : 0; 2073 cbp->gamla_rx = sc->flags & FXP_FLAG_EXT_RFA ? 1 : 0; 2074 2075 if (sc->tunable_noflow || sc->revision == FXP_REV_82557) { 2076 /* 2077 * The 82557 has no hardware flow control, the values 2078 * below are the defaults for the chip. 2079 */ 2080 cbp->fc_delay_lsb = 0; 2081 cbp->fc_delay_msb = 0x40; 2082 cbp->pri_fc_thresh = 3; 2083 cbp->tx_fc_dis = 0; 2084 cbp->rx_fc_restop = 0; 2085 cbp->rx_fc_restart = 0; 2086 cbp->fc_filter = 0; 2087 cbp->pri_fc_loc = 1; 2088 } else { 2089 cbp->fc_delay_lsb = 0x1f; 2090 cbp->fc_delay_msb = 0x01; 2091 cbp->pri_fc_thresh = 3; 2092 cbp->tx_fc_dis = 0; /* enable transmit FC */ 2093 cbp->rx_fc_restop = 1; /* enable FC restop frames */ 2094 cbp->rx_fc_restart = 1; /* enable FC restart frames */ 2095 cbp->fc_filter = !prm; /* drop FC frames to host */ 2096 cbp->pri_fc_loc = 1; /* FC pri location (byte31) */ 2097 } 2098 2099 /* 2100 * Start the config command/DMA. 2101 */ 2102 fxp_scb_wait(sc); 2103 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE); 2104 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->fxp_desc.cbl_addr); 2105 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2106 /* ...and wait for it to complete. */ 2107 fxp_dma_wait(sc, &cbp->cb_status, sc->cbl_tag, sc->cbl_map); 2108 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_POSTWRITE); 2109 2110 /* 2111 * Now initialize the station address. Temporarily use the TxCB 2112 * memory area like we did above for the config CB. 2113 */ 2114 cb_ias = (struct fxp_cb_ias *)sc->fxp_desc.cbl_list; 2115 cb_ias->cb_status = 0; 2116 cb_ias->cb_command = htole16(FXP_CB_COMMAND_IAS | FXP_CB_COMMAND_EL); 2117 cb_ias->link_addr = 0xffffffff; 2118 bcopy(sc->arpcom.ac_enaddr, cb_ias->macaddr, 2119 sizeof(sc->arpcom.ac_enaddr)); 2120 2121 /* 2122 * Start the IAS (Individual Address Setup) command/DMA. 2123 */ 2124 fxp_scb_wait(sc); 2125 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE); 2126 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2127 /* ...and wait for it to complete. */ 2128 fxp_dma_wait(sc, &cb_ias->cb_status, sc->cbl_tag, sc->cbl_map); 2129 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_POSTWRITE); 2130 2131 /* 2132 * Initialize transmit control block (TxCB) list. 2133 */ 2134 txp = sc->fxp_desc.tx_list; 2135 tcbp = sc->fxp_desc.cbl_list; 2136 bzero(tcbp, FXP_TXCB_SZ); 2137 for (i = 0; i < FXP_NTXCB; i++) { 2138 txp[i].tx_cb = tcbp + i; 2139 txp[i].tx_mbuf = NULL; 2140 tcbp[i].cb_status = htole16(FXP_CB_STATUS_C | FXP_CB_STATUS_OK); 2141 tcbp[i].cb_command = htole16(FXP_CB_COMMAND_NOP); 2142 tcbp[i].link_addr = htole32(sc->fxp_desc.cbl_addr + 2143 (((i + 1) & FXP_TXCB_MASK) * sizeof(struct fxp_cb_tx))); 2144 if (sc->flags & FXP_FLAG_EXT_TXCB) 2145 tcbp[i].tbd_array_addr = 2146 htole32(FXP_TXCB_DMA_ADDR(sc, &tcbp[i].tbd[2])); 2147 else 2148 tcbp[i].tbd_array_addr = 2149 htole32(FXP_TXCB_DMA_ADDR(sc, &tcbp[i].tbd[0])); 2150 txp[i].tx_next = &txp[(i + 1) & FXP_TXCB_MASK]; 2151 } 2152 /* 2153 * Set the suspend flag on the first TxCB and start the control 2154 * unit. It will execute the NOP and then suspend. 2155 */ 2156 tcbp->cb_command = htole16(FXP_CB_COMMAND_NOP | FXP_CB_COMMAND_S); 2157 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE); 2158 sc->fxp_desc.tx_first = sc->fxp_desc.tx_last = txp; 2159 sc->tx_queued = 1; 2160 2161 fxp_scb_wait(sc); 2162 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2163 2164 /* 2165 * Initialize receiver buffer area - RFA. 2166 */ 2167 fxp_scb_wait(sc); 2168 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->fxp_desc.rx_head->rx_addr); 2169 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_START); 2170 2171 /* 2172 * Set current media. 2173 */ 2174 if (sc->miibus != NULL) 2175 mii_mediachg(device_get_softc(sc->miibus)); 2176 2177 ifp->if_flags |= IFF_RUNNING; 2178 ifp->if_flags &= ~IFF_OACTIVE; 2179 2180 /* 2181 * Enable interrupts. 2182 */ 2183 #ifdef DEVICE_POLLING 2184 /* 2185 * ... but only do that if we are not polling. And because (presumably) 2186 * the default is interrupts on, we need to disable them explicitly! 2187 */ 2188 if ( ifp->if_flags & IFF_POLLING ) 2189 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE); 2190 else 2191 #endif /* DEVICE_POLLING */ 2192 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, 0); 2193 2194 /* 2195 * Start stats updater. 2196 */ 2197 callout_reset(&sc->stat_ch, hz, fxp_tick, sc); 2198 splx(s); 2199 } 2200 2201 static int 2202 fxp_serial_ifmedia_upd(struct ifnet *ifp) 2203 { 2204 2205 return (0); 2206 } 2207 2208 static void 2209 fxp_serial_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 2210 { 2211 2212 ifmr->ifm_active = IFM_ETHER|IFM_MANUAL; 2213 } 2214 2215 /* 2216 * Change media according to request. 2217 */ 2218 static int 2219 fxp_ifmedia_upd(struct ifnet *ifp) 2220 { 2221 struct fxp_softc *sc = ifp->if_softc; 2222 struct mii_data *mii; 2223 2224 mii = device_get_softc(sc->miibus); 2225 mii_mediachg(mii); 2226 return (0); 2227 } 2228 2229 /* 2230 * Notify the world which media we're using. 2231 */ 2232 static void 2233 fxp_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 2234 { 2235 struct fxp_softc *sc = ifp->if_softc; 2236 struct mii_data *mii; 2237 2238 mii = device_get_softc(sc->miibus); 2239 mii_pollstat(mii); 2240 ifmr->ifm_active = mii->mii_media_active; 2241 ifmr->ifm_status = mii->mii_media_status; 2242 2243 if (ifmr->ifm_status & IFM_10_T && sc->flags & FXP_FLAG_CU_RESUME_BUG) 2244 sc->cu_resume_bug = 1; 2245 else 2246 sc->cu_resume_bug = 0; 2247 } 2248 2249 /* 2250 * Add a buffer to the end of the RFA buffer list. 2251 * Return 0 if successful, 1 for failure. A failure results in 2252 * adding the 'oldm' (if non-NULL) on to the end of the list - 2253 * tossing out its old contents and recycling it. 2254 * The RFA struct is stuck at the beginning of mbuf cluster and the 2255 * data pointer is fixed up to point just past it. 2256 */ 2257 static int 2258 fxp_add_rfabuf(struct fxp_softc *sc, struct fxp_rx *rxp) 2259 { 2260 struct mbuf *m; 2261 struct fxp_rfa *rfa, *p_rfa; 2262 struct fxp_rx *p_rx; 2263 bus_dmamap_t tmp_map; 2264 int error; 2265 2266 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 2267 if (m == NULL) 2268 return (ENOBUFS); 2269 2270 /* 2271 * Move the data pointer up so that the incoming data packet 2272 * will be 32-bit aligned. 2273 */ 2274 m->m_data += RFA_ALIGNMENT_FUDGE; 2275 2276 /* 2277 * Get a pointer to the base of the mbuf cluster and move 2278 * data start past it. 2279 */ 2280 rfa = mtod(m, struct fxp_rfa *); 2281 m->m_data += sc->rfa_size; 2282 rfa->size = htole16(MCLBYTES - sc->rfa_size - RFA_ALIGNMENT_FUDGE); 2283 2284 rfa->rfa_status = 0; 2285 rfa->rfa_control = htole16(FXP_RFA_CONTROL_EL); 2286 rfa->actual_size = 0; 2287 2288 /* 2289 * Initialize the rest of the RFA. Note that since the RFA 2290 * is misaligned, we cannot store values directly. We're thus 2291 * using the le32enc() function which handles endianness and 2292 * is also alignment-safe. 2293 */ 2294 le32enc(&rfa->link_addr, 0xffffffff); 2295 le32enc(&rfa->rbd_addr, 0xffffffff); 2296 2297 /* Map the RFA into DMA memory. */ 2298 error = bus_dmamap_load(sc->fxp_mtag, sc->spare_map, rfa, 2299 MCLBYTES - RFA_ALIGNMENT_FUDGE, fxp_dma_map_addr, 2300 &rxp->rx_addr, 0); 2301 if (error) { 2302 m_freem(m); 2303 return (error); 2304 } 2305 2306 bus_dmamap_unload(sc->fxp_mtag, rxp->rx_map); 2307 tmp_map = sc->spare_map; 2308 sc->spare_map = rxp->rx_map; 2309 rxp->rx_map = tmp_map; 2310 rxp->rx_mbuf = m; 2311 2312 bus_dmamap_sync(sc->fxp_mtag, rxp->rx_map, 2313 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2314 2315 /* 2316 * If there are other buffers already on the list, attach this 2317 * one to the end by fixing up the tail to point to this one. 2318 */ 2319 if (sc->fxp_desc.rx_head != NULL) { 2320 p_rx = sc->fxp_desc.rx_tail; 2321 p_rfa = (struct fxp_rfa *) 2322 (p_rx->rx_mbuf->m_ext.ext_buf + RFA_ALIGNMENT_FUDGE); 2323 p_rx->rx_next = rxp; 2324 le32enc(&p_rfa->link_addr, rxp->rx_addr); 2325 p_rfa->rfa_control = 0; 2326 bus_dmamap_sync(sc->fxp_mtag, p_rx->rx_map, 2327 BUS_DMASYNC_PREWRITE); 2328 } else { 2329 rxp->rx_next = NULL; 2330 sc->fxp_desc.rx_head = rxp; 2331 } 2332 sc->fxp_desc.rx_tail = rxp; 2333 return (0); 2334 } 2335 2336 static volatile int 2337 fxp_miibus_readreg(device_t dev, int phy, int reg) 2338 { 2339 struct fxp_softc *sc = device_get_softc(dev); 2340 int count = 10000; 2341 int value; 2342 2343 CSR_WRITE_4(sc, FXP_CSR_MDICONTROL, 2344 (FXP_MDI_READ << 26) | (reg << 16) | (phy << 21)); 2345 2346 while (((value = CSR_READ_4(sc, FXP_CSR_MDICONTROL)) & 0x10000000) == 0 2347 && count--) 2348 DELAY(10); 2349 2350 if (count <= 0) 2351 device_printf(dev, "fxp_miibus_readreg: timed out\n"); 2352 2353 return (value & 0xffff); 2354 } 2355 2356 static void 2357 fxp_miibus_writereg(device_t dev, int phy, int reg, int value) 2358 { 2359 struct fxp_softc *sc = device_get_softc(dev); 2360 int count = 10000; 2361 2362 CSR_WRITE_4(sc, FXP_CSR_MDICONTROL, 2363 (FXP_MDI_WRITE << 26) | (reg << 16) | (phy << 21) | 2364 (value & 0xffff)); 2365 2366 while ((CSR_READ_4(sc, FXP_CSR_MDICONTROL) & 0x10000000) == 0 && 2367 count--) 2368 DELAY(10); 2369 2370 if (count <= 0) 2371 device_printf(dev, "fxp_miibus_writereg: timed out\n"); 2372 } 2373 2374 static int 2375 fxp_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 2376 { 2377 struct fxp_softc *sc = ifp->if_softc; 2378 struct ifreq *ifr = (struct ifreq *)data; 2379 struct mii_data *mii; 2380 int flag, mask, s, error = 0; 2381 2382 /* 2383 * Detaching causes us to call ioctl with the mutex owned. Preclude 2384 * that by saying we're busy if the lock is already held. 2385 */ 2386 if (FXP_LOCKED(sc)) 2387 return (EBUSY); 2388 2389 FXP_LOCK(sc); 2390 s = splimp(); 2391 2392 switch (command) { 2393 case SIOCSIFFLAGS: 2394 if (ifp->if_flags & IFF_ALLMULTI) 2395 sc->flags |= FXP_FLAG_ALL_MCAST; 2396 else 2397 sc->flags &= ~FXP_FLAG_ALL_MCAST; 2398 2399 /* 2400 * If interface is marked up and not running, then start it. 2401 * If it is marked down and running, stop it. 2402 * XXX If it's up then re-initialize it. This is so flags 2403 * such as IFF_PROMISC are handled. 2404 */ 2405 if (ifp->if_flags & IFF_UP) { 2406 fxp_init_body(sc); 2407 } else { 2408 if (ifp->if_flags & IFF_RUNNING) 2409 fxp_stop(sc); 2410 } 2411 break; 2412 2413 case SIOCADDMULTI: 2414 case SIOCDELMULTI: 2415 if (ifp->if_flags & IFF_ALLMULTI) 2416 sc->flags |= FXP_FLAG_ALL_MCAST; 2417 else 2418 sc->flags &= ~FXP_FLAG_ALL_MCAST; 2419 /* 2420 * Multicast list has changed; set the hardware filter 2421 * accordingly. 2422 */ 2423 if ((sc->flags & FXP_FLAG_ALL_MCAST) == 0) 2424 fxp_mc_setup(sc); 2425 /* 2426 * fxp_mc_setup() can set FXP_FLAG_ALL_MCAST, so check it 2427 * again rather than else {}. 2428 */ 2429 if (sc->flags & FXP_FLAG_ALL_MCAST) 2430 fxp_init_body(sc); 2431 error = 0; 2432 break; 2433 2434 case SIOCSIFMEDIA: 2435 case SIOCGIFMEDIA: 2436 if (sc->miibus != NULL) { 2437 mii = device_get_softc(sc->miibus); 2438 error = ifmedia_ioctl(ifp, ifr, 2439 &mii->mii_media, command); 2440 } else { 2441 error = ifmedia_ioctl(ifp, ifr, &sc->sc_media, command); 2442 } 2443 break; 2444 2445 case SIOCSIFCAP: 2446 mask = ifp->if_capenable ^ ifr->ifr_reqcap; 2447 if (mask & IFCAP_POLLING) 2448 ifp->if_capenable ^= IFCAP_POLLING; 2449 if (mask & IFCAP_VLAN_MTU) { 2450 ifp->if_capenable ^= IFCAP_VLAN_MTU; 2451 if (sc->revision != FXP_REV_82557) 2452 flag = FXP_FLAG_LONG_PKT_EN; 2453 else /* a hack to get long frames on the old chip */ 2454 flag = FXP_FLAG_SAVE_BAD; 2455 sc->flags ^= flag; 2456 if (ifp->if_flags & IFF_UP) 2457 fxp_init_body(sc); 2458 } 2459 break; 2460 2461 default: 2462 /* 2463 * ether_ioctl() will eventually call fxp_start() which 2464 * will result in mutex recursion so drop it first. 2465 */ 2466 FXP_UNLOCK(sc); 2467 error = ether_ioctl(ifp, command, data); 2468 } 2469 if (FXP_LOCKED(sc)) 2470 FXP_UNLOCK(sc); 2471 splx(s); 2472 return (error); 2473 } 2474 2475 /* 2476 * Fill in the multicast address list and return number of entries. 2477 */ 2478 static int 2479 fxp_mc_addrs(struct fxp_softc *sc) 2480 { 2481 struct fxp_cb_mcs *mcsp = sc->mcsp; 2482 struct ifnet *ifp = &sc->sc_if; 2483 struct ifmultiaddr *ifma; 2484 int nmcasts; 2485 2486 nmcasts = 0; 2487 if ((sc->flags & FXP_FLAG_ALL_MCAST) == 0) { 2488 #if __FreeBSD_version < 500000 2489 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 2490 #else 2491 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 2492 #endif 2493 if (ifma->ifma_addr->sa_family != AF_LINK) 2494 continue; 2495 if (nmcasts >= MAXMCADDR) { 2496 sc->flags |= FXP_FLAG_ALL_MCAST; 2497 nmcasts = 0; 2498 break; 2499 } 2500 bcopy(LLADDR((struct sockaddr_dl *)ifma->ifma_addr), 2501 &sc->mcsp->mc_addr[nmcasts][0], ETHER_ADDR_LEN); 2502 nmcasts++; 2503 } 2504 } 2505 mcsp->mc_cnt = htole16(nmcasts * ETHER_ADDR_LEN); 2506 return (nmcasts); 2507 } 2508 2509 /* 2510 * Program the multicast filter. 2511 * 2512 * We have an artificial restriction that the multicast setup command 2513 * must be the first command in the chain, so we take steps to ensure 2514 * this. By requiring this, it allows us to keep up the performance of 2515 * the pre-initialized command ring (esp. link pointers) by not actually 2516 * inserting the mcsetup command in the ring - i.e. its link pointer 2517 * points to the TxCB ring, but the mcsetup descriptor itself is not part 2518 * of it. We then can do 'CU_START' on the mcsetup descriptor and have it 2519 * lead into the regular TxCB ring when it completes. 2520 * 2521 * This function must be called at splimp. 2522 */ 2523 static void 2524 fxp_mc_setup(struct fxp_softc *sc) 2525 { 2526 struct fxp_cb_mcs *mcsp = sc->mcsp; 2527 struct ifnet *ifp = &sc->sc_if; 2528 struct fxp_tx *txp; 2529 int count; 2530 2531 FXP_LOCK_ASSERT(sc, MA_OWNED); 2532 /* 2533 * If there are queued commands, we must wait until they are all 2534 * completed. If we are already waiting, then add a NOP command 2535 * with interrupt option so that we're notified when all commands 2536 * have been completed - fxp_start() ensures that no additional 2537 * TX commands will be added when need_mcsetup is true. 2538 */ 2539 if (sc->tx_queued) { 2540 /* 2541 * need_mcsetup will be true if we are already waiting for the 2542 * NOP command to be completed (see below). In this case, bail. 2543 */ 2544 if (sc->need_mcsetup) 2545 return; 2546 sc->need_mcsetup = 1; 2547 2548 /* 2549 * Add a NOP command with interrupt so that we are notified 2550 * when all TX commands have been processed. 2551 */ 2552 txp = sc->fxp_desc.tx_last->tx_next; 2553 txp->tx_mbuf = NULL; 2554 txp->tx_cb->cb_status = 0; 2555 txp->tx_cb->cb_command = htole16(FXP_CB_COMMAND_NOP | 2556 FXP_CB_COMMAND_S | FXP_CB_COMMAND_I); 2557 /* 2558 * Advance the end of list forward. 2559 */ 2560 sc->fxp_desc.tx_last->tx_cb->cb_command &= 2561 htole16(~FXP_CB_COMMAND_S); 2562 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE); 2563 sc->fxp_desc.tx_last = txp; 2564 sc->tx_queued++; 2565 /* 2566 * Issue a resume in case the CU has just suspended. 2567 */ 2568 fxp_scb_wait(sc); 2569 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_RESUME); 2570 /* 2571 * Set a 5 second timer just in case we don't hear from the 2572 * card again. 2573 */ 2574 ifp->if_timer = 5; 2575 2576 return; 2577 } 2578 sc->need_mcsetup = 0; 2579 2580 /* 2581 * Initialize multicast setup descriptor. 2582 */ 2583 mcsp->cb_status = 0; 2584 mcsp->cb_command = htole16(FXP_CB_COMMAND_MCAS | 2585 FXP_CB_COMMAND_S | FXP_CB_COMMAND_I); 2586 mcsp->link_addr = htole32(sc->fxp_desc.cbl_addr); 2587 txp = &sc->fxp_desc.mcs_tx; 2588 txp->tx_mbuf = NULL; 2589 txp->tx_cb = (struct fxp_cb_tx *)sc->mcsp; 2590 txp->tx_next = sc->fxp_desc.tx_list; 2591 (void) fxp_mc_addrs(sc); 2592 sc->fxp_desc.tx_first = sc->fxp_desc.tx_last = txp; 2593 sc->tx_queued = 1; 2594 2595 /* 2596 * Wait until command unit is not active. This should never 2597 * be the case when nothing is queued, but make sure anyway. 2598 */ 2599 count = 100; 2600 while ((CSR_READ_1(sc, FXP_CSR_SCB_RUSCUS) >> 6) == 2601 FXP_SCB_CUS_ACTIVE && --count) 2602 DELAY(10); 2603 if (count == 0) { 2604 device_printf(sc->dev, "command queue timeout\n"); 2605 return; 2606 } 2607 2608 /* 2609 * Start the multicast setup command. 2610 */ 2611 fxp_scb_wait(sc); 2612 bus_dmamap_sync(sc->mcs_tag, sc->mcs_map, BUS_DMASYNC_PREWRITE); 2613 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->mcs_addr); 2614 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2615 2616 ifp->if_timer = 2; 2617 return; 2618 } 2619 2620 static u_int32_t fxp_ucode_d101a[] = D101_A_RCVBUNDLE_UCODE; 2621 static u_int32_t fxp_ucode_d101b0[] = D101_B0_RCVBUNDLE_UCODE; 2622 static u_int32_t fxp_ucode_d101ma[] = D101M_B_RCVBUNDLE_UCODE; 2623 static u_int32_t fxp_ucode_d101s[] = D101S_RCVBUNDLE_UCODE; 2624 static u_int32_t fxp_ucode_d102[] = D102_B_RCVBUNDLE_UCODE; 2625 static u_int32_t fxp_ucode_d102c[] = D102_C_RCVBUNDLE_UCODE; 2626 2627 #define UCODE(x) x, sizeof(x)/sizeof(u_int32_t) 2628 2629 struct ucode { 2630 u_int32_t revision; 2631 u_int32_t *ucode; 2632 int length; 2633 u_short int_delay_offset; 2634 u_short bundle_max_offset; 2635 } ucode_table[] = { 2636 { FXP_REV_82558_A4, UCODE(fxp_ucode_d101a), D101_CPUSAVER_DWORD, 0 }, 2637 { FXP_REV_82558_B0, UCODE(fxp_ucode_d101b0), D101_CPUSAVER_DWORD, 0 }, 2638 { FXP_REV_82559_A0, UCODE(fxp_ucode_d101ma), 2639 D101M_CPUSAVER_DWORD, D101M_CPUSAVER_BUNDLE_MAX_DWORD }, 2640 { FXP_REV_82559S_A, UCODE(fxp_ucode_d101s), 2641 D101S_CPUSAVER_DWORD, D101S_CPUSAVER_BUNDLE_MAX_DWORD }, 2642 { FXP_REV_82550, UCODE(fxp_ucode_d102), 2643 D102_B_CPUSAVER_DWORD, D102_B_CPUSAVER_BUNDLE_MAX_DWORD }, 2644 { FXP_REV_82550_C, UCODE(fxp_ucode_d102c), 2645 D102_C_CPUSAVER_DWORD, D102_C_CPUSAVER_BUNDLE_MAX_DWORD }, 2646 { 0, NULL, 0, 0, 0 } 2647 }; 2648 2649 static void 2650 fxp_load_ucode(struct fxp_softc *sc) 2651 { 2652 struct ucode *uc; 2653 struct fxp_cb_ucode *cbp; 2654 int i; 2655 2656 for (uc = ucode_table; uc->ucode != NULL; uc++) 2657 if (sc->revision == uc->revision) 2658 break; 2659 if (uc->ucode == NULL) 2660 return; 2661 cbp = (struct fxp_cb_ucode *)sc->fxp_desc.cbl_list; 2662 cbp->cb_status = 0; 2663 cbp->cb_command = htole16(FXP_CB_COMMAND_UCODE | FXP_CB_COMMAND_EL); 2664 cbp->link_addr = 0xffffffff; /* (no) next command */ 2665 for (i = 0; i < uc->length; i++) 2666 cbp->ucode[i] = htole32(uc->ucode[i]); 2667 if (uc->int_delay_offset) 2668 *(u_int16_t *)&cbp->ucode[uc->int_delay_offset] = 2669 htole16(sc->tunable_int_delay + sc->tunable_int_delay / 2); 2670 if (uc->bundle_max_offset) 2671 *(u_int16_t *)&cbp->ucode[uc->bundle_max_offset] = 2672 htole16(sc->tunable_bundle_max); 2673 /* 2674 * Download the ucode to the chip. 2675 */ 2676 fxp_scb_wait(sc); 2677 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE); 2678 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->fxp_desc.cbl_addr); 2679 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2680 /* ...and wait for it to complete. */ 2681 fxp_dma_wait(sc, &cbp->cb_status, sc->cbl_tag, sc->cbl_map); 2682 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_POSTWRITE); 2683 device_printf(sc->dev, 2684 "Microcode loaded, int_delay: %d usec bundle_max: %d\n", 2685 sc->tunable_int_delay, 2686 uc->bundle_max_offset == 0 ? 0 : sc->tunable_bundle_max); 2687 sc->flags |= FXP_FLAG_UCODE; 2688 } 2689 2690 static int 2691 sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high) 2692 { 2693 int error, value; 2694 2695 value = *(int *)arg1; 2696 error = sysctl_handle_int(oidp, &value, 0, req); 2697 if (error || !req->newptr) 2698 return (error); 2699 if (value < low || value > high) 2700 return (EINVAL); 2701 *(int *)arg1 = value; 2702 return (0); 2703 } 2704 2705 /* 2706 * Interrupt delay is expressed in microseconds, a multiplier is used 2707 * to convert this to the appropriate clock ticks before using. 2708 */ 2709 static int 2710 sysctl_hw_fxp_int_delay(SYSCTL_HANDLER_ARGS) 2711 { 2712 return (sysctl_int_range(oidp, arg1, arg2, req, 300, 3000)); 2713 } 2714 2715 static int 2716 sysctl_hw_fxp_bundle_max(SYSCTL_HANDLER_ARGS) 2717 { 2718 return (sysctl_int_range(oidp, arg1, arg2, req, 1, 0xffff)); 2719 } 2720