1 /*- 2 * Copyright (c) 1995, David Greenman 3 * Copyright (c) 2001 Jonathan Lemon <jlemon@freebsd.org> 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice unmodified, this list of conditions, and the following 11 * disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 * 28 * $FreeBSD$ 29 */ 30 31 /* 32 * Intel EtherExpress Pro/100B PCI Fast Ethernet driver 33 */ 34 35 #include "vlan.h" 36 37 #include <sys/param.h> 38 #include <sys/systm.h> 39 #include <sys/mbuf.h> 40 #include <sys/malloc.h> 41 /* #include <sys/mutex.h> */ 42 #include <sys/kernel.h> 43 #include <sys/socket.h> 44 45 #include <net/if.h> 46 #include <net/if_dl.h> 47 #include <net/if_media.h> 48 49 #ifdef NS 50 #include <netns/ns.h> 51 #include <netns/ns_if.h> 52 #endif 53 54 #include <net/bpf.h> 55 #include <sys/sockio.h> 56 #include <sys/bus.h> 57 #include <machine/bus.h> 58 #include <sys/rman.h> 59 #include <machine/resource.h> 60 61 #include <net/ethernet.h> 62 #include <net/if_arp.h> 63 64 #include <vm/vm.h> /* for vtophys */ 65 #include <vm/pmap.h> /* for vtophys */ 66 #include <machine/clock.h> /* for DELAY */ 67 68 #if NVLAN > 0 69 #include <net/if_types.h> 70 #include <net/if_vlan_var.h> 71 #endif 72 73 #include <pci/pcivar.h> 74 #include <pci/pcireg.h> /* for PCIM_CMD_xxx */ 75 76 #include <dev/mii/mii.h> 77 #include <dev/mii/miivar.h> 78 79 #include <dev/fxp/if_fxpreg.h> 80 #include <dev/fxp/if_fxpvar.h> 81 82 MODULE_DEPEND(fxp, miibus, 1, 1, 1); 83 #include "miibus_if.h" 84 85 /* 86 * NOTE! On the Alpha, we have an alignment constraint. The 87 * card DMAs the packet immediately following the RFA. However, 88 * the first thing in the packet is a 14-byte Ethernet header. 89 * This means that the packet is misaligned. To compensate, 90 * we actually offset the RFA 2 bytes into the cluster. This 91 * alignes the packet after the Ethernet header at a 32-bit 92 * boundary. HOWEVER! This means that the RFA is misaligned! 93 */ 94 #define RFA_ALIGNMENT_FUDGE 2 95 96 /* 97 * Set initial transmit threshold at 64 (512 bytes). This is 98 * increased by 64 (512 bytes) at a time, to maximum of 192 99 * (1536 bytes), if an underrun occurs. 100 */ 101 static int tx_threshold = 64; 102 103 /* 104 * The configuration byte map has several undefined fields which 105 * must be one or must be zero. Set up a template for these bits 106 * only, (assuming a 82557 chip) leaving the actual configuration 107 * to fxp_init. 108 * 109 * See struct fxp_cb_config for the bit definitions. 110 */ 111 static u_char fxp_cb_config_template[] = { 112 0x0, 0x0, /* cb_status */ 113 0x0, 0x0, /* cb_command */ 114 0x0, 0x0, 0x0, 0x0, /* link_addr */ 115 0x0, /* 0 */ 116 0x0, /* 1 */ 117 0x0, /* 2 */ 118 0x0, /* 3 */ 119 0x0, /* 4 */ 120 0x0, /* 5 */ 121 0x32, /* 6 */ 122 0x0, /* 7 */ 123 0x0, /* 8 */ 124 0x0, /* 9 */ 125 0x6, /* 10 */ 126 0x0, /* 11 */ 127 0x0, /* 12 */ 128 0x0, /* 13 */ 129 0xf2, /* 14 */ 130 0x48, /* 15 */ 131 0x0, /* 16 */ 132 0x40, /* 17 */ 133 0xf0, /* 18 */ 134 0x0, /* 19 */ 135 0x3f, /* 20 */ 136 0x5 /* 21 */ 137 }; 138 139 struct fxp_ident { 140 u_int16_t devid; 141 char *name; 142 }; 143 144 /* 145 * Claim various Intel PCI device identifiers for this driver. The 146 * sub-vendor and sub-device field are extensively used to identify 147 * particular variants, but we don't currently differentiate between 148 * them. 149 */ 150 static struct fxp_ident fxp_ident_table[] = { 151 { 0x1229, "Intel Pro 10/100B/100+ Ethernet" }, 152 { 0x2449, "Intel Pro/100 Ethernet" }, 153 { 0x1209, "Intel Embedded 10/100 Ethernet" }, 154 { 0x1029, "Intel Pro/100 Ethernet" }, 155 { 0x1030, "Intel Pro/100 Ethernet" }, 156 { 0x1031, "Intel Pro/100 Ethernet" }, 157 { 0x1032, "Intel Pro/100 Ethernet" }, 158 { 0x1033, "Intel Pro/100 Ethernet" }, 159 { 0x1034, "Intel Pro/100 Ethernet" }, 160 { 0x1035, "Intel Pro/100 Ethernet" }, 161 { 0x1036, "Intel Pro/100 Ethernet" }, 162 { 0x1037, "Intel Pro/100 Ethernet" }, 163 { 0x1038, "Intel Pro/100 Ethernet" }, 164 { 0, NULL }, 165 }; 166 167 static int fxp_probe(device_t dev); 168 static int fxp_attach(device_t dev); 169 static int fxp_detach(device_t dev); 170 static int fxp_shutdown(device_t dev); 171 static int fxp_suspend(device_t dev); 172 static int fxp_resume(device_t dev); 173 174 static void fxp_intr(void *xsc); 175 static void fxp_init(void *xsc); 176 static void fxp_tick(void *xsc); 177 static void fxp_powerstate_d0(device_t dev); 178 static void fxp_start(struct ifnet *ifp); 179 static void fxp_stop(struct fxp_softc *sc); 180 static void fxp_release(struct fxp_softc *sc); 181 static int fxp_ioctl(struct ifnet *ifp, u_long command, 182 caddr_t data); 183 static void fxp_watchdog(struct ifnet *ifp); 184 static int fxp_add_rfabuf(struct fxp_softc *sc, struct mbuf *oldm); 185 static void fxp_mc_setup(struct fxp_softc *sc); 186 static u_int16_t fxp_eeprom_getword(struct fxp_softc *sc, int offset, 187 int autosize); 188 static void fxp_autosize_eeprom(struct fxp_softc *sc); 189 static void fxp_read_eeprom(struct fxp_softc *sc, u_short *data, 190 int offset, int words); 191 static int fxp_ifmedia_upd(struct ifnet *ifp); 192 static void fxp_ifmedia_sts(struct ifnet *ifp, 193 struct ifmediareq *ifmr); 194 static int fxp_serial_ifmedia_upd(struct ifnet *ifp); 195 static void fxp_serial_ifmedia_sts(struct ifnet *ifp, 196 struct ifmediareq *ifmr); 197 static volatile int fxp_miibus_readreg(device_t dev, int phy, int reg); 198 static void fxp_miibus_writereg(device_t dev, int phy, int reg, 199 int value); 200 static __inline void fxp_lwcopy(volatile u_int32_t *src, 201 volatile u_int32_t *dst); 202 static __inline void fxp_scb_wait(struct fxp_softc *sc); 203 static __inline void fxp_scb_cmd(struct fxp_softc *sc, int cmd); 204 static __inline void fxp_dma_wait(volatile u_int16_t *status, 205 struct fxp_softc *sc); 206 207 static device_method_t fxp_methods[] = { 208 /* Device interface */ 209 DEVMETHOD(device_probe, fxp_probe), 210 DEVMETHOD(device_attach, fxp_attach), 211 DEVMETHOD(device_detach, fxp_detach), 212 DEVMETHOD(device_shutdown, fxp_shutdown), 213 DEVMETHOD(device_suspend, fxp_suspend), 214 DEVMETHOD(device_resume, fxp_resume), 215 216 /* MII interface */ 217 DEVMETHOD(miibus_readreg, fxp_miibus_readreg), 218 DEVMETHOD(miibus_writereg, fxp_miibus_writereg), 219 220 { 0, 0 } 221 }; 222 223 static driver_t fxp_driver = { 224 "fxp", 225 fxp_methods, 226 sizeof(struct fxp_softc), 227 }; 228 229 static devclass_t fxp_devclass; 230 231 DRIVER_MODULE(if_fxp, pci, fxp_driver, fxp_devclass, 0, 0); 232 DRIVER_MODULE(if_fxp, cardbus, fxp_driver, fxp_devclass, 0, 0); 233 DRIVER_MODULE(miibus, fxp, miibus_driver, miibus_devclass, 0, 0); 234 235 /* 236 * Inline function to copy a 16-bit aligned 32-bit quantity. 237 */ 238 static __inline void 239 fxp_lwcopy(volatile u_int32_t *src, volatile u_int32_t *dst) 240 { 241 #ifdef __i386__ 242 *dst = *src; 243 #else 244 volatile u_int16_t *a = (volatile u_int16_t *)src; 245 volatile u_int16_t *b = (volatile u_int16_t *)dst; 246 247 b[0] = a[0]; 248 b[1] = a[1]; 249 #endif 250 } 251 252 /* 253 * Wait for the previous command to be accepted (but not necessarily 254 * completed). 255 */ 256 static __inline void 257 fxp_scb_wait(struct fxp_softc *sc) 258 { 259 int i = 10000; 260 261 while (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) && --i) 262 DELAY(2); 263 if (i == 0) 264 device_printf(sc->dev, "SCB timeout: 0x%x, 0x%x, 0x%x 0x%x\n", 265 CSR_READ_1(sc, FXP_CSR_SCB_COMMAND), 266 CSR_READ_1(sc, FXP_CSR_SCB_STATACK), 267 CSR_READ_1(sc, FXP_CSR_SCB_RUSCUS), 268 CSR_READ_2(sc, FXP_CSR_FLOWCONTROL)); 269 } 270 271 static __inline void 272 fxp_scb_cmd(struct fxp_softc *sc, int cmd) 273 { 274 275 if (cmd == FXP_SCB_COMMAND_CU_RESUME && sc->cu_resume_bug) { 276 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_CB_COMMAND_NOP); 277 fxp_scb_wait(sc); 278 } 279 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, cmd); 280 } 281 282 static __inline void 283 fxp_dma_wait(volatile u_int16_t *status, struct fxp_softc *sc) 284 { 285 int i = 10000; 286 287 while (!(*status & FXP_CB_STATUS_C) && --i) 288 DELAY(2); 289 if (i == 0) 290 device_printf(sc->dev, "DMA timeout\n"); 291 } 292 293 /* 294 * Return identification string if this is device is ours. 295 */ 296 static int 297 fxp_probe(device_t dev) 298 { 299 u_int16_t devid; 300 struct fxp_ident *ident; 301 302 if (pci_get_vendor(dev) == FXP_VENDORID_INTEL) { 303 devid = pci_get_device(dev); 304 for (ident = fxp_ident_table; ident->name != NULL; ident++) { 305 if (ident->devid == devid) { 306 device_set_desc(dev, ident->name); 307 return (0); 308 } 309 } 310 } 311 return (ENXIO); 312 } 313 314 static void 315 fxp_powerstate_d0(device_t dev) 316 { 317 #if __FreeBSD_version >= 430002 318 u_int32_t iobase, membase, irq; 319 320 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 321 /* Save important PCI config data. */ 322 iobase = pci_read_config(dev, FXP_PCI_IOBA, 4); 323 membase = pci_read_config(dev, FXP_PCI_MMBA, 4); 324 irq = pci_read_config(dev, PCIR_INTLINE, 4); 325 326 /* Reset the power state. */ 327 device_printf(dev, "chip is in D%d power mode " 328 "-- setting to D0\n", pci_get_powerstate(dev)); 329 330 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 331 332 /* Restore PCI config data. */ 333 pci_write_config(dev, FXP_PCI_IOBA, iobase, 4); 334 pci_write_config(dev, FXP_PCI_MMBA, membase, 4); 335 pci_write_config(dev, PCIR_INTLINE, irq, 4); 336 } 337 #endif 338 } 339 340 static int 341 fxp_attach(device_t dev) 342 { 343 int error = 0; 344 struct fxp_softc *sc = device_get_softc(dev); 345 struct ifnet *ifp; 346 u_int32_t val; 347 u_int16_t data; 348 int i, rid, m1, m2, prefer_iomap; 349 int s; 350 351 bzero(sc, sizeof(*sc)); 352 sc->dev = dev; 353 callout_handle_init(&sc->stat_ch); 354 mtx_init(&sc->sc_mtx, device_get_nameunit(dev), MTX_DEF | MTX_RECURSE); 355 356 s = splimp(); 357 358 /* 359 * Enable bus mastering. Enable memory space too, in case 360 * BIOS/Prom forgot about it. 361 */ 362 val = pci_read_config(dev, PCIR_COMMAND, 2); 363 val |= (PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN); 364 pci_write_config(dev, PCIR_COMMAND, val, 2); 365 val = pci_read_config(dev, PCIR_COMMAND, 2); 366 367 fxp_powerstate_d0(dev); 368 369 /* 370 * Figure out which we should try first - memory mapping or i/o mapping? 371 * We default to memory mapping. Then we accept an override from the 372 * command line. Then we check to see which one is enabled. 373 */ 374 m1 = PCIM_CMD_MEMEN; 375 m2 = PCIM_CMD_PORTEN; 376 prefer_iomap = 0; 377 if (resource_int_value(device_get_name(dev), device_get_unit(dev), 378 "prefer_iomap", &prefer_iomap) == 0 && prefer_iomap != 0) { 379 m1 = PCIM_CMD_PORTEN; 380 m2 = PCIM_CMD_MEMEN; 381 } 382 383 if (val & m1) { 384 sc->rtp = 385 (m1 == PCIM_CMD_MEMEN)? SYS_RES_MEMORY : SYS_RES_IOPORT; 386 sc->rgd = (m1 == PCIM_CMD_MEMEN)? FXP_PCI_MMBA : FXP_PCI_IOBA; 387 sc->mem = bus_alloc_resource(dev, sc->rtp, &sc->rgd, 388 0, ~0, 1, RF_ACTIVE); 389 } 390 if (sc->mem == NULL && (val & m2)) { 391 sc->rtp = 392 (m2 == PCIM_CMD_MEMEN)? SYS_RES_MEMORY : SYS_RES_IOPORT; 393 sc->rgd = (m2 == PCIM_CMD_MEMEN)? FXP_PCI_MMBA : FXP_PCI_IOBA; 394 sc->mem = bus_alloc_resource(dev, sc->rtp, &sc->rgd, 395 0, ~0, 1, RF_ACTIVE); 396 } 397 398 if (!sc->mem) { 399 device_printf(dev, "could not map device registers\n"); 400 error = ENXIO; 401 goto fail; 402 } 403 if (bootverbose) { 404 device_printf(dev, "using %s space register mapping\n", 405 sc->rtp == SYS_RES_MEMORY? "memory" : "I/O"); 406 } 407 408 sc->sc_st = rman_get_bustag(sc->mem); 409 sc->sc_sh = rman_get_bushandle(sc->mem); 410 411 /* 412 * Allocate our interrupt. 413 */ 414 rid = 0; 415 sc->irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 416 RF_SHAREABLE | RF_ACTIVE); 417 if (sc->irq == NULL) { 418 device_printf(dev, "could not map interrupt\n"); 419 error = ENXIO; 420 goto fail; 421 } 422 423 error = bus_setup_intr(dev, sc->irq, INTR_TYPE_NET, 424 fxp_intr, sc, &sc->ih); 425 if (error) { 426 device_printf(dev, "could not setup irq\n"); 427 goto fail; 428 } 429 430 /* 431 * Reset to a stable state. 432 */ 433 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET); 434 DELAY(10); 435 436 sc->cbl_base = malloc(sizeof(struct fxp_cb_tx) * FXP_NTXCB, 437 M_DEVBUF, M_NOWAIT | M_ZERO); 438 if (sc->cbl_base == NULL) 439 goto failmem; 440 441 sc->fxp_stats = malloc(sizeof(struct fxp_stats), M_DEVBUF, 442 M_NOWAIT | M_ZERO); 443 if (sc->fxp_stats == NULL) 444 goto failmem; 445 446 sc->mcsp = malloc(sizeof(struct fxp_cb_mcs), M_DEVBUF, M_NOWAIT); 447 if (sc->mcsp == NULL) 448 goto failmem; 449 450 /* 451 * Pre-allocate our receive buffers. 452 */ 453 for (i = 0; i < FXP_NRFABUFS; i++) { 454 if (fxp_add_rfabuf(sc, NULL) != 0) { 455 goto failmem; 456 } 457 } 458 459 /* 460 * Find out how large of an SEEPROM we have. 461 */ 462 fxp_autosize_eeprom(sc); 463 464 /* 465 * Determine whether we must use the 503 serial interface. 466 */ 467 fxp_read_eeprom(sc, &data, 6, 1); 468 if ((data & FXP_PHY_DEVICE_MASK) != 0 && 469 (data & FXP_PHY_SERIAL_ONLY)) 470 sc->flags |= FXP_FLAG_SERIAL_MEDIA; 471 472 /* 473 * Find out the basic controller type; we currently only 474 * differentiate between a 82557 and greater. 475 */ 476 fxp_read_eeprom(sc, &data, 5, 1); 477 if ((data >> 8) == 1) 478 sc->chip = FXP_CHIP_82557; 479 480 /* 481 * Enable workarounds for certain chip revision deficiencies. 482 */ 483 i = pci_get_device(dev); 484 if (i == 0x2449 || (i > 0x1030 && i < 0x1039)) 485 sc->flags |= FXP_FLAG_CU_RESUME_BUG; 486 487 /* 488 * If we are not a 82557 chip, we can enable extended features. 489 */ 490 if (sc->chip != FXP_CHIP_82557) { 491 /* 492 * If MWI is enabled in the PCI configuration, and there 493 * is a valid cacheline size (8 or 16 dwords), then tell 494 * the board to turn on MWI. 495 */ 496 if (val & PCIM_CMD_MWRICEN && 497 pci_read_config(dev, PCIR_CACHELNSZ, 1) != 0) 498 sc->flags |= FXP_FLAG_MWI_ENABLE; 499 500 /* turn on the extended TxCB feature */ 501 sc->flags |= FXP_FLAG_EXT_TXCB; 502 #if NVLAN > 0 503 /* enable reception of long frames for VLAN */ 504 sc->flags |= FXP_FLAG_LONG_PKT_EN; 505 #endif 506 } 507 508 /* 509 * Read MAC address. 510 */ 511 fxp_read_eeprom(sc, (u_int16_t *)sc->arpcom.ac_enaddr, 0, 3); 512 device_printf(dev, "Ethernet address %6D%s\n", 513 sc->arpcom.ac_enaddr, ":", 514 sc->flags & FXP_FLAG_SERIAL_MEDIA ? ", 10Mbps" : ""); 515 if (bootverbose) { 516 device_printf(dev, "PCI IDs: %04x %04x %04x %04x %04x\n", 517 pci_get_vendor(dev), pci_get_device(dev), 518 pci_get_subvendor(dev), pci_get_subdevice(dev), 519 pci_get_revid(dev)); 520 device_printf(dev, "Chip Type: %d\n", sc->chip); 521 } 522 523 /* 524 * If this is only a 10Mbps device, then there is no MII, and 525 * the PHY will use a serial interface instead. 526 * 527 * The Seeq 80c24 AutoDUPLEX(tm) Ethernet Interface Adapter 528 * doesn't have a programming interface of any sort. The 529 * media is sensed automatically based on how the link partner 530 * is configured. This is, in essence, manual configuration. 531 */ 532 if (sc->flags & FXP_FLAG_SERIAL_MEDIA) { 533 ifmedia_init(&sc->sc_media, 0, fxp_serial_ifmedia_upd, 534 fxp_serial_ifmedia_sts); 535 ifmedia_add(&sc->sc_media, IFM_ETHER|IFM_MANUAL, 0, NULL); 536 ifmedia_set(&sc->sc_media, IFM_ETHER|IFM_MANUAL); 537 } else { 538 if (mii_phy_probe(dev, &sc->miibus, fxp_ifmedia_upd, 539 fxp_ifmedia_sts)) { 540 device_printf(dev, "MII without any PHY!\n"); 541 error = ENXIO; 542 goto fail; 543 } 544 } 545 546 ifp = &sc->arpcom.ac_if; 547 ifp->if_unit = device_get_unit(dev); 548 ifp->if_name = "fxp"; 549 ifp->if_output = ether_output; 550 ifp->if_baudrate = 100000000; 551 ifp->if_init = fxp_init; 552 ifp->if_softc = sc; 553 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 554 ifp->if_ioctl = fxp_ioctl; 555 ifp->if_start = fxp_start; 556 ifp->if_watchdog = fxp_watchdog; 557 558 /* 559 * Attach the interface. 560 */ 561 ether_ifattach(ifp, ETHER_BPF_SUPPORTED); 562 563 #if NVLAN > 0 564 /* 565 * Tell the upper layer(s) we support long frames. 566 */ 567 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 568 #endif 569 570 /* 571 * Let the system queue as many packets as we have available 572 * TX descriptors. 573 */ 574 ifp->if_snd.ifq_maxlen = FXP_NTXCB - 1; 575 576 splx(s); 577 return (0); 578 579 failmem: 580 device_printf(dev, "Failed to malloc memory\n"); 581 error = ENOMEM; 582 fail: 583 splx(s); 584 fxp_release(sc); 585 return (error); 586 } 587 588 /* 589 * release all resources 590 */ 591 static void 592 fxp_release(struct fxp_softc *sc) 593 { 594 595 bus_generic_detach(sc->dev); 596 if (sc->miibus) 597 device_delete_child(sc->dev, sc->miibus); 598 599 if (sc->cbl_base) 600 free(sc->cbl_base, M_DEVBUF); 601 if (sc->fxp_stats) 602 free(sc->fxp_stats, M_DEVBUF); 603 if (sc->mcsp) 604 free(sc->mcsp, M_DEVBUF); 605 if (sc->rfa_headm) 606 m_freem(sc->rfa_headm); 607 608 if (sc->ih) 609 bus_teardown_intr(sc->dev, sc->irq, sc->ih); 610 if (sc->irq) 611 bus_release_resource(sc->dev, SYS_RES_IRQ, 0, sc->irq); 612 if (sc->mem) 613 bus_release_resource(sc->dev, sc->rtp, sc->rgd, sc->mem); 614 mtx_destroy(&sc->sc_mtx); 615 } 616 617 /* 618 * Detach interface. 619 */ 620 static int 621 fxp_detach(device_t dev) 622 { 623 struct fxp_softc *sc = device_get_softc(dev); 624 int s; 625 626 /* disable interrupts */ 627 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE); 628 629 s = splimp(); 630 631 /* 632 * Stop DMA and drop transmit queue. 633 */ 634 fxp_stop(sc); 635 636 /* 637 * Close down routes etc. 638 */ 639 ether_ifdetach(&sc->arpcom.ac_if, ETHER_BPF_SUPPORTED); 640 641 /* 642 * Free all media structures. 643 */ 644 ifmedia_removeall(&sc->sc_media); 645 646 splx(s); 647 648 /* Release our allocated resources. */ 649 fxp_release(sc); 650 651 return (0); 652 } 653 654 /* 655 * Device shutdown routine. Called at system shutdown after sync. The 656 * main purpose of this routine is to shut off receiver DMA so that 657 * kernel memory doesn't get clobbered during warmboot. 658 */ 659 static int 660 fxp_shutdown(device_t dev) 661 { 662 /* 663 * Make sure that DMA is disabled prior to reboot. Not doing 664 * do could allow DMA to corrupt kernel memory during the 665 * reboot before the driver initializes. 666 */ 667 fxp_stop((struct fxp_softc *) device_get_softc(dev)); 668 return (0); 669 } 670 671 /* 672 * Device suspend routine. Stop the interface and save some PCI 673 * settings in case the BIOS doesn't restore them properly on 674 * resume. 675 */ 676 static int 677 fxp_suspend(device_t dev) 678 { 679 struct fxp_softc *sc = device_get_softc(dev); 680 int i, s; 681 682 s = splimp(); 683 684 fxp_stop(sc); 685 686 for (i = 0; i < 5; i++) 687 sc->saved_maps[i] = pci_read_config(dev, PCIR_MAPS + i * 4, 4); 688 sc->saved_biosaddr = pci_read_config(dev, PCIR_BIOS, 4); 689 sc->saved_intline = pci_read_config(dev, PCIR_INTLINE, 1); 690 sc->saved_cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1); 691 sc->saved_lattimer = pci_read_config(dev, PCIR_LATTIMER, 1); 692 693 sc->suspended = 1; 694 695 splx(s); 696 return (0); 697 } 698 699 /* 700 * Device resume routine. Restore some PCI settings in case the BIOS 701 * doesn't, re-enable busmastering, and restart the interface if 702 * appropriate. 703 */ 704 static int 705 fxp_resume(device_t dev) 706 { 707 struct fxp_softc *sc = device_get_softc(dev); 708 struct ifnet *ifp = &sc->sc_if; 709 u_int16_t pci_command; 710 int i, s; 711 712 s = splimp(); 713 714 fxp_powerstate_d0(dev); 715 716 /* better way to do this? */ 717 for (i = 0; i < 5; i++) 718 pci_write_config(dev, PCIR_MAPS + i * 4, sc->saved_maps[i], 4); 719 pci_write_config(dev, PCIR_BIOS, sc->saved_biosaddr, 4); 720 pci_write_config(dev, PCIR_INTLINE, sc->saved_intline, 1); 721 pci_write_config(dev, PCIR_CACHELNSZ, sc->saved_cachelnsz, 1); 722 pci_write_config(dev, PCIR_LATTIMER, sc->saved_lattimer, 1); 723 724 /* reenable busmastering */ 725 pci_command = pci_read_config(dev, PCIR_COMMAND, 2); 726 pci_command |= (PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN); 727 pci_write_config(dev, PCIR_COMMAND, pci_command, 2); 728 729 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET); 730 DELAY(10); 731 732 /* reinitialize interface if necessary */ 733 if (ifp->if_flags & IFF_UP) 734 fxp_init(sc); 735 736 sc->suspended = 0; 737 738 splx(s); 739 return (0); 740 } 741 742 /* 743 * Read from the serial EEPROM. Basically, you manually shift in 744 * the read opcode (one bit at a time) and then shift in the address, 745 * and then you shift out the data (all of this one bit at a time). 746 * The word size is 16 bits, so you have to provide the address for 747 * every 16 bits of data. 748 */ 749 static u_int16_t 750 fxp_eeprom_getword(struct fxp_softc *sc, int offset, int autosize) 751 { 752 u_int16_t reg, data; 753 int x; 754 755 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 756 /* 757 * Shift in read opcode. 758 */ 759 for (x = 1 << 2; x; x >>= 1) { 760 if (FXP_EEPROM_OPC_READ & x) 761 reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI; 762 else 763 reg = FXP_EEPROM_EECS; 764 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 765 DELAY(1); 766 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK); 767 DELAY(1); 768 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 769 DELAY(1); 770 } 771 /* 772 * Shift in address. 773 */ 774 data = 0; 775 for (x = 1 << (sc->eeprom_size - 1); x; x >>= 1) { 776 if (offset & x) 777 reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI; 778 else 779 reg = FXP_EEPROM_EECS; 780 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 781 DELAY(1); 782 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK); 783 DELAY(1); 784 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 785 DELAY(1); 786 reg = CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO; 787 data++; 788 if (autosize && reg == 0) { 789 sc->eeprom_size = data; 790 break; 791 } 792 } 793 /* 794 * Shift out data. 795 */ 796 data = 0; 797 reg = FXP_EEPROM_EECS; 798 for (x = 1 << 15; x; x >>= 1) { 799 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK); 800 DELAY(1); 801 if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO) 802 data |= x; 803 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 804 DELAY(1); 805 } 806 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 807 DELAY(1); 808 809 return (data); 810 } 811 812 /* 813 * From NetBSD: 814 * 815 * Figure out EEPROM size. 816 * 817 * 559's can have either 64-word or 256-word EEPROMs, the 558 818 * datasheet only talks about 64-word EEPROMs, and the 557 datasheet 819 * talks about the existance of 16 to 256 word EEPROMs. 820 * 821 * The only known sizes are 64 and 256, where the 256 version is used 822 * by CardBus cards to store CIS information. 823 * 824 * The address is shifted in msb-to-lsb, and after the last 825 * address-bit the EEPROM is supposed to output a `dummy zero' bit, 826 * after which follows the actual data. We try to detect this zero, by 827 * probing the data-out bit in the EEPROM control register just after 828 * having shifted in a bit. If the bit is zero, we assume we've 829 * shifted enough address bits. The data-out should be tri-state, 830 * before this, which should translate to a logical one. 831 * 832 * Other ways to do this would be to try to read a register with known 833 * contents with a varying number of address bits, but no such 834 * register seem to be available. The high bits of register 10 are 01 835 * on the 558 and 559, but apparently not on the 557. 836 * 837 * The Linux driver computes a checksum on the EEPROM data, but the 838 * value of this checksum is not very well documented. 839 */ 840 static void 841 fxp_autosize_eeprom(struct fxp_softc *sc) 842 { 843 844 /* guess maximum size of 256 words */ 845 sc->eeprom_size = 8; 846 847 /* autosize */ 848 (void) fxp_eeprom_getword(sc, 0, 1); 849 } 850 851 static void 852 fxp_read_eeprom(struct fxp_softc *sc, u_short *data, int offset, int words) 853 { 854 int i; 855 856 for (i = 0; i < words; i++) 857 data[i] = fxp_eeprom_getword(sc, offset + i, 0); 858 } 859 860 /* 861 * Start packet transmission on the interface. 862 */ 863 static void 864 fxp_start(struct ifnet *ifp) 865 { 866 struct fxp_softc *sc = ifp->if_softc; 867 struct fxp_cb_tx *txp; 868 869 /* 870 * See if we need to suspend xmit until the multicast filter 871 * has been reprogrammed (which can only be done at the head 872 * of the command chain). 873 */ 874 if (sc->need_mcsetup) { 875 return; 876 } 877 878 txp = NULL; 879 880 /* 881 * We're finished if there is nothing more to add to the list or if 882 * we're all filled up with buffers to transmit. 883 * NOTE: One TxCB is reserved to guarantee that fxp_mc_setup() can add 884 * a NOP command when needed. 885 */ 886 while (ifp->if_snd.ifq_head != NULL && sc->tx_queued < FXP_NTXCB - 1) { 887 struct mbuf *m, *mb_head; 888 int segment; 889 890 /* 891 * Grab a packet to transmit. 892 */ 893 IF_DEQUEUE(&ifp->if_snd, mb_head); 894 895 /* 896 * Get pointer to next available tx desc. 897 */ 898 txp = sc->cbl_last->next; 899 900 /* 901 * Go through each of the mbufs in the chain and initialize 902 * the transmit buffer descriptors with the physical address 903 * and size of the mbuf. 904 */ 905 tbdinit: 906 for (m = mb_head, segment = 0; m != NULL; m = m->m_next) { 907 if (m->m_len != 0) { 908 if (segment == FXP_NTXSEG) 909 break; 910 txp->tbd[segment].tb_addr = 911 vtophys(mtod(m, vm_offset_t)); 912 txp->tbd[segment].tb_size = m->m_len; 913 segment++; 914 } 915 } 916 if (m != NULL) { 917 struct mbuf *mn; 918 919 /* 920 * We ran out of segments. We have to recopy this 921 * mbuf chain first. Bail out if we can't get the 922 * new buffers. 923 */ 924 MGETHDR(mn, M_DONTWAIT, MT_DATA); 925 if (mn == NULL) { 926 m_freem(mb_head); 927 break; 928 } 929 if (mb_head->m_pkthdr.len > MHLEN) { 930 MCLGET(mn, M_DONTWAIT); 931 if ((mn->m_flags & M_EXT) == 0) { 932 m_freem(mn); 933 m_freem(mb_head); 934 break; 935 } 936 } 937 m_copydata(mb_head, 0, mb_head->m_pkthdr.len, 938 mtod(mn, caddr_t)); 939 mn->m_pkthdr.len = mn->m_len = mb_head->m_pkthdr.len; 940 m_freem(mb_head); 941 mb_head = mn; 942 goto tbdinit; 943 } 944 945 txp->tbd_number = segment; 946 txp->mb_head = mb_head; 947 txp->cb_status = 0; 948 if (sc->tx_queued != FXP_CXINT_THRESH - 1) { 949 txp->cb_command = 950 FXP_CB_COMMAND_XMIT | FXP_CB_COMMAND_SF | 951 FXP_CB_COMMAND_S; 952 } else { 953 txp->cb_command = 954 FXP_CB_COMMAND_XMIT | FXP_CB_COMMAND_SF | 955 FXP_CB_COMMAND_S | FXP_CB_COMMAND_I; 956 /* 957 * Set a 5 second timer just in case we don't hear 958 * from the card again. 959 */ 960 ifp->if_timer = 5; 961 } 962 txp->tx_threshold = tx_threshold; 963 964 /* 965 * Advance the end of list forward. 966 */ 967 968 #ifdef __alpha__ 969 /* 970 * On platforms which can't access memory in 16-bit 971 * granularities, we must prevent the card from DMA'ing 972 * up the status while we update the command field. 973 * This could cause us to overwrite the completion status. 974 */ 975 atomic_clear_short(&sc->cbl_last->cb_command, 976 FXP_CB_COMMAND_S); 977 #else 978 sc->cbl_last->cb_command &= ~FXP_CB_COMMAND_S; 979 #endif /*__alpha__*/ 980 sc->cbl_last = txp; 981 982 /* 983 * Advance the beginning of the list forward if there are 984 * no other packets queued (when nothing is queued, cbl_first 985 * sits on the last TxCB that was sent out). 986 */ 987 if (sc->tx_queued == 0) 988 sc->cbl_first = txp; 989 990 sc->tx_queued++; 991 992 /* 993 * Pass packet to bpf if there is a listener. 994 */ 995 if (ifp->if_bpf) 996 bpf_mtap(ifp, mb_head); 997 } 998 999 /* 1000 * We're finished. If we added to the list, issue a RESUME to get DMA 1001 * going again if suspended. 1002 */ 1003 if (txp != NULL) { 1004 fxp_scb_wait(sc); 1005 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_RESUME); 1006 } 1007 } 1008 1009 /* 1010 * Process interface interrupts. 1011 */ 1012 static void 1013 fxp_intr(void *xsc) 1014 { 1015 struct fxp_softc *sc = xsc; 1016 struct ifnet *ifp = &sc->sc_if; 1017 u_int8_t statack; 1018 1019 if (sc->suspended) { 1020 return; 1021 } 1022 1023 while ((statack = CSR_READ_1(sc, FXP_CSR_SCB_STATACK)) != 0) { 1024 /* 1025 * It should not be possible to have all bits set; the 1026 * FXP_SCB_INTR_SWI bit always returns 0 on a read. If 1027 * all bits are set, this may indicate that the card has 1028 * been physically ejected, so ignore it. 1029 */ 1030 if (statack == 0xff) 1031 return; 1032 1033 /* 1034 * First ACK all the interrupts in this pass. 1035 */ 1036 CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, statack); 1037 1038 /* 1039 * Free any finished transmit mbuf chains. 1040 * 1041 * Handle the CNA event likt a CXTNO event. It used to 1042 * be that this event (control unit not ready) was not 1043 * encountered, but it is now with the SMPng modifications. 1044 * The exact sequence of events that occur when the interface 1045 * is brought up are different now, and if this event 1046 * goes unhandled, the configuration/rxfilter setup sequence 1047 * can stall for several seconds. The result is that no 1048 * packets go out onto the wire for about 5 to 10 seconds 1049 * after the interface is ifconfig'ed for the first time. 1050 */ 1051 if (statack & (FXP_SCB_STATACK_CXTNO | FXP_SCB_STATACK_CNA)) { 1052 struct fxp_cb_tx *txp; 1053 1054 for (txp = sc->cbl_first; sc->tx_queued && 1055 (txp->cb_status & FXP_CB_STATUS_C) != 0; 1056 txp = txp->next) { 1057 if (txp->mb_head != NULL) { 1058 m_freem(txp->mb_head); 1059 txp->mb_head = NULL; 1060 } 1061 sc->tx_queued--; 1062 } 1063 sc->cbl_first = txp; 1064 ifp->if_timer = 0; 1065 if (sc->tx_queued == 0) { 1066 if (sc->need_mcsetup) 1067 fxp_mc_setup(sc); 1068 } 1069 /* 1070 * Try to start more packets transmitting. 1071 */ 1072 if (ifp->if_snd.ifq_head != NULL) 1073 fxp_start(ifp); 1074 } 1075 /* 1076 * Process receiver interrupts. If a no-resource (RNR) 1077 * condition exists, get whatever packets we can and 1078 * re-start the receiver. 1079 */ 1080 if (statack & (FXP_SCB_STATACK_FR | FXP_SCB_STATACK_RNR)) { 1081 struct mbuf *m; 1082 struct fxp_rfa *rfa; 1083 rcvloop: 1084 m = sc->rfa_headm; 1085 rfa = (struct fxp_rfa *)(m->m_ext.ext_buf + 1086 RFA_ALIGNMENT_FUDGE); 1087 1088 if (rfa->rfa_status & FXP_RFA_STATUS_C) { 1089 /* 1090 * Remove first packet from the chain. 1091 */ 1092 sc->rfa_headm = m->m_next; 1093 m->m_next = NULL; 1094 1095 /* 1096 * Add a new buffer to the receive chain. 1097 * If this fails, the old buffer is recycled 1098 * instead. 1099 */ 1100 if (fxp_add_rfabuf(sc, m) == 0) { 1101 struct ether_header *eh; 1102 int total_len; 1103 1104 total_len = rfa->actual_size & 1105 (MCLBYTES - 1); 1106 if (total_len < 1107 sizeof(struct ether_header)) { 1108 m_freem(m); 1109 goto rcvloop; 1110 } 1111 #if NVLAN > 0 1112 /* 1113 * Drop the packet if it has CRC 1114 * errors. This test is only needed 1115 * when doing 802.1q VLAN on the 82557 1116 * chip. 1117 */ 1118 if (rfa->rfa_status & 1119 FXP_RFA_STATUS_CRC) { 1120 m_freem(m); 1121 goto rcvloop; 1122 } 1123 #endif 1124 m->m_pkthdr.rcvif = ifp; 1125 m->m_pkthdr.len = m->m_len = total_len; 1126 eh = mtod(m, struct ether_header *); 1127 m->m_data += 1128 sizeof(struct ether_header); 1129 m->m_len -= 1130 sizeof(struct ether_header); 1131 m->m_pkthdr.len = m->m_len; 1132 ether_input(ifp, eh, m); 1133 } 1134 goto rcvloop; 1135 } 1136 if (statack & FXP_SCB_STATACK_RNR) { 1137 fxp_scb_wait(sc); 1138 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 1139 vtophys(sc->rfa_headm->m_ext.ext_buf) + 1140 RFA_ALIGNMENT_FUDGE); 1141 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_START); 1142 } 1143 } 1144 } 1145 } 1146 1147 /* 1148 * Update packet in/out/collision statistics. The i82557 doesn't 1149 * allow you to access these counters without doing a fairly 1150 * expensive DMA to get _all_ of the statistics it maintains, so 1151 * we do this operation here only once per second. The statistics 1152 * counters in the kernel are updated from the previous dump-stats 1153 * DMA and then a new dump-stats DMA is started. The on-chip 1154 * counters are zeroed when the DMA completes. If we can't start 1155 * the DMA immediately, we don't wait - we just prepare to read 1156 * them again next time. 1157 */ 1158 static void 1159 fxp_tick(void *xsc) 1160 { 1161 struct fxp_softc *sc = xsc; 1162 struct ifnet *ifp = &sc->sc_if; 1163 struct fxp_stats *sp = sc->fxp_stats; 1164 struct fxp_cb_tx *txp; 1165 int s; 1166 1167 ifp->if_opackets += sp->tx_good; 1168 ifp->if_collisions += sp->tx_total_collisions; 1169 if (sp->rx_good) { 1170 ifp->if_ipackets += sp->rx_good; 1171 sc->rx_idle_secs = 0; 1172 } else { 1173 /* 1174 * Receiver's been idle for another second. 1175 */ 1176 sc->rx_idle_secs++; 1177 } 1178 ifp->if_ierrors += 1179 sp->rx_crc_errors + 1180 sp->rx_alignment_errors + 1181 sp->rx_rnr_errors + 1182 sp->rx_overrun_errors; 1183 /* 1184 * If any transmit underruns occured, bump up the transmit 1185 * threshold by another 512 bytes (64 * 8). 1186 */ 1187 if (sp->tx_underruns) { 1188 ifp->if_oerrors += sp->tx_underruns; 1189 if (tx_threshold < 192) 1190 tx_threshold += 64; 1191 } 1192 s = splimp(); 1193 /* 1194 * Release any xmit buffers that have completed DMA. This isn't 1195 * strictly necessary to do here, but it's advantagous for mbufs 1196 * with external storage to be released in a timely manner rather 1197 * than being defered for a potentially long time. This limits 1198 * the delay to a maximum of one second. 1199 */ 1200 for (txp = sc->cbl_first; sc->tx_queued && 1201 (txp->cb_status & FXP_CB_STATUS_C) != 0; 1202 txp = txp->next) { 1203 if (txp->mb_head != NULL) { 1204 m_freem(txp->mb_head); 1205 txp->mb_head = NULL; 1206 } 1207 sc->tx_queued--; 1208 } 1209 sc->cbl_first = txp; 1210 /* 1211 * If we haven't received any packets in FXP_MAC_RX_IDLE seconds, 1212 * then assume the receiver has locked up and attempt to clear 1213 * the condition by reprogramming the multicast filter. This is 1214 * a work-around for a bug in the 82557 where the receiver locks 1215 * up if it gets certain types of garbage in the syncronization 1216 * bits prior to the packet header. This bug is supposed to only 1217 * occur in 10Mbps mode, but has been seen to occur in 100Mbps 1218 * mode as well (perhaps due to a 10/100 speed transition). 1219 */ 1220 if (sc->rx_idle_secs > FXP_MAX_RX_IDLE) { 1221 sc->rx_idle_secs = 0; 1222 fxp_mc_setup(sc); 1223 } 1224 /* 1225 * If there is no pending command, start another stats 1226 * dump. Otherwise punt for now. 1227 */ 1228 if (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) == 0) { 1229 /* 1230 * Start another stats dump. 1231 */ 1232 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_DUMPRESET); 1233 } else { 1234 /* 1235 * A previous command is still waiting to be accepted. 1236 * Just zero our copy of the stats and wait for the 1237 * next timer event to update them. 1238 */ 1239 sp->tx_good = 0; 1240 sp->tx_underruns = 0; 1241 sp->tx_total_collisions = 0; 1242 1243 sp->rx_good = 0; 1244 sp->rx_crc_errors = 0; 1245 sp->rx_alignment_errors = 0; 1246 sp->rx_rnr_errors = 0; 1247 sp->rx_overrun_errors = 0; 1248 } 1249 if (sc->miibus != NULL) 1250 mii_tick(device_get_softc(sc->miibus)); 1251 splx(s); 1252 /* 1253 * Schedule another timeout one second from now. 1254 */ 1255 sc->stat_ch = timeout(fxp_tick, sc, hz); 1256 } 1257 1258 /* 1259 * Stop the interface. Cancels the statistics updater and resets 1260 * the interface. 1261 */ 1262 static void 1263 fxp_stop(struct fxp_softc *sc) 1264 { 1265 struct ifnet *ifp = &sc->sc_if; 1266 struct fxp_cb_tx *txp; 1267 int i; 1268 1269 1270 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1271 ifp->if_timer = 0; 1272 1273 /* 1274 * Cancel stats updater. 1275 */ 1276 untimeout(fxp_tick, sc, sc->stat_ch); 1277 1278 /* 1279 * Issue software reset 1280 */ 1281 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET); 1282 DELAY(10); 1283 1284 /* 1285 * Release any xmit buffers. 1286 */ 1287 txp = sc->cbl_base; 1288 if (txp != NULL) { 1289 for (i = 0; i < FXP_NTXCB; i++) { 1290 if (txp[i].mb_head != NULL) { 1291 m_freem(txp[i].mb_head); 1292 txp[i].mb_head = NULL; 1293 } 1294 } 1295 } 1296 sc->tx_queued = 0; 1297 1298 /* 1299 * Free all the receive buffers then reallocate/reinitialize 1300 */ 1301 if (sc->rfa_headm != NULL) 1302 m_freem(sc->rfa_headm); 1303 sc->rfa_headm = NULL; 1304 sc->rfa_tailm = NULL; 1305 for (i = 0; i < FXP_NRFABUFS; i++) { 1306 if (fxp_add_rfabuf(sc, NULL) != 0) { 1307 /* 1308 * This "can't happen" - we're at splimp() 1309 * and we just freed all the buffers we need 1310 * above. 1311 */ 1312 panic("fxp_stop: no buffers!"); 1313 } 1314 } 1315 } 1316 1317 /* 1318 * Watchdog/transmission transmit timeout handler. Called when a 1319 * transmission is started on the interface, but no interrupt is 1320 * received before the timeout. This usually indicates that the 1321 * card has wedged for some reason. 1322 */ 1323 static void 1324 fxp_watchdog(struct ifnet *ifp) 1325 { 1326 struct fxp_softc *sc = ifp->if_softc; 1327 1328 device_printf(sc->dev, "device timeout\n"); 1329 ifp->if_oerrors++; 1330 1331 fxp_init(sc); 1332 } 1333 1334 static void 1335 fxp_init(void *xsc) 1336 { 1337 struct fxp_softc *sc = xsc; 1338 struct ifnet *ifp = &sc->sc_if; 1339 struct fxp_cb_config *cbp; 1340 struct fxp_cb_ias *cb_ias; 1341 struct fxp_cb_tx *txp; 1342 int i, prm, s; 1343 1344 s = splimp(); 1345 /* 1346 * Cancel any pending I/O 1347 */ 1348 fxp_stop(sc); 1349 1350 prm = (ifp->if_flags & IFF_PROMISC) ? 1 : 0; 1351 1352 /* 1353 * Initialize base of CBL and RFA memory. Loading with zero 1354 * sets it up for regular linear addressing. 1355 */ 1356 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 0); 1357 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_BASE); 1358 1359 fxp_scb_wait(sc); 1360 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_BASE); 1361 1362 /* 1363 * Initialize base of dump-stats buffer. 1364 */ 1365 fxp_scb_wait(sc); 1366 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, vtophys(sc->fxp_stats)); 1367 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_DUMP_ADR); 1368 1369 /* 1370 * We temporarily use memory that contains the TxCB list to 1371 * construct the config CB. The TxCB list memory is rebuilt 1372 * later. 1373 */ 1374 cbp = (struct fxp_cb_config *) sc->cbl_base; 1375 1376 /* 1377 * This bcopy is kind of disgusting, but there are a bunch of must be 1378 * zero and must be one bits in this structure and this is the easiest 1379 * way to initialize them all to proper values. 1380 */ 1381 bcopy(fxp_cb_config_template, 1382 (void *)(uintptr_t)(volatile void *)&cbp->cb_status, 1383 sizeof(fxp_cb_config_template)); 1384 1385 cbp->cb_status = 0; 1386 cbp->cb_command = FXP_CB_COMMAND_CONFIG | FXP_CB_COMMAND_EL; 1387 cbp->link_addr = -1; /* (no) next command */ 1388 cbp->byte_count = 22; /* (22) bytes to config */ 1389 cbp->rx_fifo_limit = 8; /* rx fifo threshold (32 bytes) */ 1390 cbp->tx_fifo_limit = 0; /* tx fifo threshold (0 bytes) */ 1391 cbp->adaptive_ifs = 0; /* (no) adaptive interframe spacing */ 1392 cbp->mwi_enable = sc->flags & FXP_FLAG_MWI_ENABLE ? 1 : 0; 1393 cbp->type_enable = 0; /* actually reserved */ 1394 cbp->read_align_en = sc->flags & FXP_FLAG_READ_ALIGN ? 1 : 0; 1395 cbp->end_wr_on_cl = sc->flags & FXP_FLAG_WRITE_ALIGN ? 1 : 0; 1396 cbp->rx_dma_bytecount = 0; /* (no) rx DMA max */ 1397 cbp->tx_dma_bytecount = 0; /* (no) tx DMA max */ 1398 cbp->dma_mbce = 0; /* (disable) dma max counters */ 1399 cbp->late_scb = 0; /* (don't) defer SCB update */ 1400 cbp->direct_dma_dis = 1; /* disable direct rcv dma mode */ 1401 cbp->tno_int_or_tco_en =0; /* (disable) tx not okay interrupt */ 1402 cbp->ci_int = 1; /* interrupt on CU idle */ 1403 cbp->ext_txcb_dis = sc->flags & FXP_FLAG_EXT_TXCB ? 0 : 1; 1404 cbp->ext_stats_dis = 1; /* disable extended counters */ 1405 cbp->keep_overrun_rx = 0; /* don't pass overrun frames to host */ 1406 #if NVLAN > 0 1407 cbp->save_bf = sc->chip == FXP_CHIP_82557 ? 1 : prm; 1408 #else 1409 cbp->save_bf = prm; /* save bad frames */ 1410 #endif 1411 cbp->disc_short_rx = !prm; /* discard short packets */ 1412 cbp->underrun_retry = 1; /* retry mode (once) on DMA underrun */ 1413 cbp->two_frames = 0; /* do not limit FIFO to 2 frames */ 1414 cbp->dyn_tbd = 0; /* (no) dynamic TBD mode */ 1415 cbp->mediatype = sc->flags & FXP_FLAG_SERIAL_MEDIA ? 0 : 1; 1416 cbp->csma_dis = 0; /* (don't) disable link */ 1417 cbp->tcp_udp_cksum = 0; /* (don't) enable checksum */ 1418 cbp->vlan_tco = 0; /* (don't) enable vlan wakeup */ 1419 cbp->link_wake_en = 0; /* (don't) assert PME# on link change */ 1420 cbp->arp_wake_en = 0; /* (don't) assert PME# on arp */ 1421 cbp->mc_wake_en = 0; /* (don't) enable PME# on mcmatch */ 1422 cbp->nsai = 1; /* (don't) disable source addr insert */ 1423 cbp->preamble_length = 2; /* (7 byte) preamble */ 1424 cbp->loopback = 0; /* (don't) loopback */ 1425 cbp->linear_priority = 0; /* (normal CSMA/CD operation) */ 1426 cbp->linear_pri_mode = 0; /* (wait after xmit only) */ 1427 cbp->interfrm_spacing = 6; /* (96 bits of) interframe spacing */ 1428 cbp->promiscuous = prm; /* promiscuous mode */ 1429 cbp->bcast_disable = 0; /* (don't) disable broadcasts */ 1430 cbp->wait_after_win = 0; /* (don't) enable modified backoff alg*/ 1431 cbp->ignore_ul = 0; /* consider U/L bit in IA matching */ 1432 cbp->crc16_en = 0; /* (don't) enable crc-16 algorithm */ 1433 cbp->crscdt = sc->flags & FXP_FLAG_SERIAL_MEDIA ? 1 : 0; 1434 1435 cbp->stripping = !prm; /* truncate rx packet to byte count */ 1436 cbp->padding = 1; /* (do) pad short tx packets */ 1437 cbp->rcv_crc_xfer = 0; /* (don't) xfer CRC to host */ 1438 cbp->long_rx_en = sc->flags & FXP_FLAG_LONG_PKT_EN ? 1 : 0; 1439 cbp->ia_wake_en = 0; /* (don't) wake up on address match */ 1440 cbp->magic_pkt_dis = 0; /* (don't) disable magic packet */ 1441 /* must set wake_en in PMCSR also */ 1442 cbp->force_fdx = 0; /* (don't) force full duplex */ 1443 cbp->fdx_pin_en = 1; /* (enable) FDX# pin */ 1444 cbp->multi_ia = 0; /* (don't) accept multiple IAs */ 1445 cbp->mc_all = sc->flags & FXP_FLAG_ALL_MCAST ? 1 : 0; 1446 1447 if (sc->chip == FXP_CHIP_82557) { 1448 /* 1449 * The 82557 has no hardware flow control, the values 1450 * below are the defaults for the chip. 1451 */ 1452 cbp->fc_delay_lsb = 0; 1453 cbp->fc_delay_msb = 0x40; 1454 cbp->pri_fc_thresh = 3; 1455 cbp->tx_fc_dis = 0; 1456 cbp->rx_fc_restop = 0; 1457 cbp->rx_fc_restart = 0; 1458 cbp->fc_filter = 0; 1459 cbp->pri_fc_loc = 1; 1460 } else { 1461 cbp->fc_delay_lsb = 0x1f; 1462 cbp->fc_delay_msb = 0x01; 1463 cbp->pri_fc_thresh = 3; 1464 cbp->tx_fc_dis = 0; /* enable transmit FC */ 1465 cbp->rx_fc_restop = 1; /* enable FC restop frames */ 1466 cbp->rx_fc_restart = 1; /* enable FC restart frames */ 1467 cbp->fc_filter = !prm; /* drop FC frames to host */ 1468 cbp->pri_fc_loc = 1; /* FC pri location (byte31) */ 1469 } 1470 1471 /* 1472 * Start the config command/DMA. 1473 */ 1474 fxp_scb_wait(sc); 1475 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, vtophys(&cbp->cb_status)); 1476 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 1477 /* ...and wait for it to complete. */ 1478 fxp_dma_wait(&cbp->cb_status, sc); 1479 1480 /* 1481 * Now initialize the station address. Temporarily use the TxCB 1482 * memory area like we did above for the config CB. 1483 */ 1484 cb_ias = (struct fxp_cb_ias *) sc->cbl_base; 1485 cb_ias->cb_status = 0; 1486 cb_ias->cb_command = FXP_CB_COMMAND_IAS | FXP_CB_COMMAND_EL; 1487 cb_ias->link_addr = -1; 1488 bcopy(sc->arpcom.ac_enaddr, 1489 (void *)(uintptr_t)(volatile void *)cb_ias->macaddr, 1490 sizeof(sc->arpcom.ac_enaddr)); 1491 1492 /* 1493 * Start the IAS (Individual Address Setup) command/DMA. 1494 */ 1495 fxp_scb_wait(sc); 1496 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 1497 /* ...and wait for it to complete. */ 1498 fxp_dma_wait(&cb_ias->cb_status, sc); 1499 1500 /* 1501 * Initialize transmit control block (TxCB) list. 1502 */ 1503 1504 txp = sc->cbl_base; 1505 bzero(txp, sizeof(struct fxp_cb_tx) * FXP_NTXCB); 1506 for (i = 0; i < FXP_NTXCB; i++) { 1507 txp[i].cb_status = FXP_CB_STATUS_C | FXP_CB_STATUS_OK; 1508 txp[i].cb_command = FXP_CB_COMMAND_NOP; 1509 txp[i].link_addr = 1510 vtophys(&txp[(i + 1) & FXP_TXCB_MASK].cb_status); 1511 if (sc->flags & FXP_FLAG_EXT_TXCB) 1512 txp[i].tbd_array_addr = vtophys(&txp[i].tbd[2]); 1513 else 1514 txp[i].tbd_array_addr = vtophys(&txp[i].tbd[0]); 1515 txp[i].next = &txp[(i + 1) & FXP_TXCB_MASK]; 1516 } 1517 /* 1518 * Set the suspend flag on the first TxCB and start the control 1519 * unit. It will execute the NOP and then suspend. 1520 */ 1521 txp->cb_command = FXP_CB_COMMAND_NOP | FXP_CB_COMMAND_S; 1522 sc->cbl_first = sc->cbl_last = txp; 1523 sc->tx_queued = 1; 1524 1525 fxp_scb_wait(sc); 1526 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 1527 1528 /* 1529 * Initialize receiver buffer area - RFA. 1530 */ 1531 fxp_scb_wait(sc); 1532 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 1533 vtophys(sc->rfa_headm->m_ext.ext_buf) + RFA_ALIGNMENT_FUDGE); 1534 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_START); 1535 1536 /* 1537 * Set current media. 1538 */ 1539 if (sc->miibus != NULL) 1540 mii_mediachg(device_get_softc(sc->miibus)); 1541 1542 ifp->if_flags |= IFF_RUNNING; 1543 ifp->if_flags &= ~IFF_OACTIVE; 1544 1545 /* 1546 * Enable interrupts. 1547 */ 1548 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, 0); 1549 splx(s); 1550 1551 /* 1552 * Start stats updater. 1553 */ 1554 sc->stat_ch = timeout(fxp_tick, sc, hz); 1555 } 1556 1557 static int 1558 fxp_serial_ifmedia_upd(struct ifnet *ifp) 1559 { 1560 1561 return (0); 1562 } 1563 1564 static void 1565 fxp_serial_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 1566 { 1567 1568 ifmr->ifm_active = IFM_ETHER|IFM_MANUAL; 1569 } 1570 1571 /* 1572 * Change media according to request. 1573 */ 1574 static int 1575 fxp_ifmedia_upd(struct ifnet *ifp) 1576 { 1577 struct fxp_softc *sc = ifp->if_softc; 1578 struct mii_data *mii; 1579 1580 mii = device_get_softc(sc->miibus); 1581 mii_mediachg(mii); 1582 return (0); 1583 } 1584 1585 /* 1586 * Notify the world which media we're using. 1587 */ 1588 static void 1589 fxp_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 1590 { 1591 struct fxp_softc *sc = ifp->if_softc; 1592 struct mii_data *mii; 1593 1594 mii = device_get_softc(sc->miibus); 1595 mii_pollstat(mii); 1596 ifmr->ifm_active = mii->mii_media_active; 1597 ifmr->ifm_status = mii->mii_media_status; 1598 1599 if (ifmr->ifm_status & IFM_10_T && sc->flags & FXP_FLAG_CU_RESUME_BUG) 1600 sc->cu_resume_bug = 1; 1601 else 1602 sc->cu_resume_bug = 0; 1603 } 1604 1605 /* 1606 * Add a buffer to the end of the RFA buffer list. 1607 * Return 0 if successful, 1 for failure. A failure results in 1608 * adding the 'oldm' (if non-NULL) on to the end of the list - 1609 * tossing out its old contents and recycling it. 1610 * The RFA struct is stuck at the beginning of mbuf cluster and the 1611 * data pointer is fixed up to point just past it. 1612 */ 1613 static int 1614 fxp_add_rfabuf(struct fxp_softc *sc, struct mbuf *oldm) 1615 { 1616 u_int32_t v; 1617 struct mbuf *m; 1618 struct fxp_rfa *rfa, *p_rfa; 1619 1620 MGETHDR(m, M_DONTWAIT, MT_DATA); 1621 if (m != NULL) { 1622 MCLGET(m, M_DONTWAIT); 1623 if ((m->m_flags & M_EXT) == 0) { 1624 m_freem(m); 1625 if (oldm == NULL) 1626 return 1; 1627 m = oldm; 1628 m->m_data = m->m_ext.ext_buf; 1629 } 1630 } else { 1631 if (oldm == NULL) 1632 return 1; 1633 m = oldm; 1634 m->m_data = m->m_ext.ext_buf; 1635 } 1636 1637 /* 1638 * Move the data pointer up so that the incoming data packet 1639 * will be 32-bit aligned. 1640 */ 1641 m->m_data += RFA_ALIGNMENT_FUDGE; 1642 1643 /* 1644 * Get a pointer to the base of the mbuf cluster and move 1645 * data start past it. 1646 */ 1647 rfa = mtod(m, struct fxp_rfa *); 1648 m->m_data += sizeof(struct fxp_rfa); 1649 rfa->size = (u_int16_t)(MCLBYTES - sizeof(struct fxp_rfa) - RFA_ALIGNMENT_FUDGE); 1650 1651 /* 1652 * Initialize the rest of the RFA. Note that since the RFA 1653 * is misaligned, we cannot store values directly. Instead, 1654 * we use an optimized, inline copy. 1655 */ 1656 1657 rfa->rfa_status = 0; 1658 rfa->rfa_control = FXP_RFA_CONTROL_EL; 1659 rfa->actual_size = 0; 1660 1661 v = -1; 1662 fxp_lwcopy(&v, (volatile u_int32_t *) rfa->link_addr); 1663 fxp_lwcopy(&v, (volatile u_int32_t *) rfa->rbd_addr); 1664 1665 /* 1666 * If there are other buffers already on the list, attach this 1667 * one to the end by fixing up the tail to point to this one. 1668 */ 1669 if (sc->rfa_headm != NULL) { 1670 p_rfa = (struct fxp_rfa *) (sc->rfa_tailm->m_ext.ext_buf + 1671 RFA_ALIGNMENT_FUDGE); 1672 sc->rfa_tailm->m_next = m; 1673 v = vtophys(rfa); 1674 fxp_lwcopy(&v, (volatile u_int32_t *) p_rfa->link_addr); 1675 p_rfa->rfa_control = 0; 1676 } else { 1677 sc->rfa_headm = m; 1678 } 1679 sc->rfa_tailm = m; 1680 1681 return (m == oldm); 1682 } 1683 1684 static volatile int 1685 fxp_miibus_readreg(device_t dev, int phy, int reg) 1686 { 1687 struct fxp_softc *sc = device_get_softc(dev); 1688 int count = 10000; 1689 int value; 1690 1691 CSR_WRITE_4(sc, FXP_CSR_MDICONTROL, 1692 (FXP_MDI_READ << 26) | (reg << 16) | (phy << 21)); 1693 1694 while (((value = CSR_READ_4(sc, FXP_CSR_MDICONTROL)) & 0x10000000) == 0 1695 && count--) 1696 DELAY(10); 1697 1698 if (count <= 0) 1699 device_printf(dev, "fxp_miibus_readreg: timed out\n"); 1700 1701 return (value & 0xffff); 1702 } 1703 1704 static void 1705 fxp_miibus_writereg(device_t dev, int phy, int reg, int value) 1706 { 1707 struct fxp_softc *sc = device_get_softc(dev); 1708 int count = 10000; 1709 1710 CSR_WRITE_4(sc, FXP_CSR_MDICONTROL, 1711 (FXP_MDI_WRITE << 26) | (reg << 16) | (phy << 21) | 1712 (value & 0xffff)); 1713 1714 while ((CSR_READ_4(sc, FXP_CSR_MDICONTROL) & 0x10000000) == 0 && 1715 count--) 1716 DELAY(10); 1717 1718 if (count <= 0) 1719 device_printf(dev, "fxp_miibus_writereg: timed out\n"); 1720 } 1721 1722 static int 1723 fxp_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 1724 { 1725 struct fxp_softc *sc = ifp->if_softc; 1726 struct ifreq *ifr = (struct ifreq *)data; 1727 struct mii_data *mii; 1728 int s, error = 0; 1729 1730 s = splimp(); 1731 1732 switch (command) { 1733 case SIOCSIFADDR: 1734 case SIOCGIFADDR: 1735 case SIOCSIFMTU: 1736 error = ether_ioctl(ifp, command, data); 1737 break; 1738 1739 case SIOCSIFFLAGS: 1740 if (ifp->if_flags & IFF_ALLMULTI) 1741 sc->flags |= FXP_FLAG_ALL_MCAST; 1742 else 1743 sc->flags &= ~FXP_FLAG_ALL_MCAST; 1744 1745 /* 1746 * If interface is marked up and not running, then start it. 1747 * If it is marked down and running, stop it. 1748 * XXX If it's up then re-initialize it. This is so flags 1749 * such as IFF_PROMISC are handled. 1750 */ 1751 if (ifp->if_flags & IFF_UP) { 1752 fxp_init(sc); 1753 } else { 1754 if (ifp->if_flags & IFF_RUNNING) 1755 fxp_stop(sc); 1756 } 1757 break; 1758 1759 case SIOCADDMULTI: 1760 case SIOCDELMULTI: 1761 if (ifp->if_flags & IFF_ALLMULTI) 1762 sc->flags |= FXP_FLAG_ALL_MCAST; 1763 else 1764 sc->flags &= ~FXP_FLAG_ALL_MCAST; 1765 /* 1766 * Multicast list has changed; set the hardware filter 1767 * accordingly. 1768 */ 1769 if ((sc->flags & FXP_FLAG_ALL_MCAST) == 0) 1770 fxp_mc_setup(sc); 1771 /* 1772 * fxp_mc_setup() can set FXP_FLAG_ALL_MCAST, so check it 1773 * again rather than else {}. 1774 */ 1775 if (sc->flags & FXP_FLAG_ALL_MCAST) 1776 fxp_init(sc); 1777 error = 0; 1778 break; 1779 1780 case SIOCSIFMEDIA: 1781 case SIOCGIFMEDIA: 1782 if (sc->miibus != NULL) { 1783 mii = device_get_softc(sc->miibus); 1784 error = ifmedia_ioctl(ifp, ifr, 1785 &mii->mii_media, command); 1786 } else { 1787 error = ifmedia_ioctl(ifp, ifr, &sc->sc_media, command); 1788 } 1789 break; 1790 1791 default: 1792 error = EINVAL; 1793 } 1794 splx(s); 1795 return (error); 1796 } 1797 1798 /* 1799 * Program the multicast filter. 1800 * 1801 * We have an artificial restriction that the multicast setup command 1802 * must be the first command in the chain, so we take steps to ensure 1803 * this. By requiring this, it allows us to keep up the performance of 1804 * the pre-initialized command ring (esp. link pointers) by not actually 1805 * inserting the mcsetup command in the ring - i.e. its link pointer 1806 * points to the TxCB ring, but the mcsetup descriptor itself is not part 1807 * of it. We then can do 'CU_START' on the mcsetup descriptor and have it 1808 * lead into the regular TxCB ring when it completes. 1809 * 1810 * This function must be called at splimp. 1811 */ 1812 static void 1813 fxp_mc_setup(struct fxp_softc *sc) 1814 { 1815 struct fxp_cb_mcs *mcsp = sc->mcsp; 1816 struct ifnet *ifp = &sc->sc_if; 1817 struct ifmultiaddr *ifma; 1818 int nmcasts; 1819 int count; 1820 1821 /* 1822 * If there are queued commands, we must wait until they are all 1823 * completed. If we are already waiting, then add a NOP command 1824 * with interrupt option so that we're notified when all commands 1825 * have been completed - fxp_start() ensures that no additional 1826 * TX commands will be added when need_mcsetup is true. 1827 */ 1828 if (sc->tx_queued) { 1829 struct fxp_cb_tx *txp; 1830 1831 /* 1832 * need_mcsetup will be true if we are already waiting for the 1833 * NOP command to be completed (see below). In this case, bail. 1834 */ 1835 if (sc->need_mcsetup) 1836 return; 1837 sc->need_mcsetup = 1; 1838 1839 /* 1840 * Add a NOP command with interrupt so that we are notified when all 1841 * TX commands have been processed. 1842 */ 1843 txp = sc->cbl_last->next; 1844 txp->mb_head = NULL; 1845 txp->cb_status = 0; 1846 txp->cb_command = FXP_CB_COMMAND_NOP | 1847 FXP_CB_COMMAND_S | FXP_CB_COMMAND_I; 1848 /* 1849 * Advance the end of list forward. 1850 */ 1851 sc->cbl_last->cb_command &= ~FXP_CB_COMMAND_S; 1852 sc->cbl_last = txp; 1853 sc->tx_queued++; 1854 /* 1855 * Issue a resume in case the CU has just suspended. 1856 */ 1857 fxp_scb_wait(sc); 1858 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_RESUME); 1859 /* 1860 * Set a 5 second timer just in case we don't hear from the 1861 * card again. 1862 */ 1863 ifp->if_timer = 5; 1864 1865 return; 1866 } 1867 sc->need_mcsetup = 0; 1868 1869 /* 1870 * Initialize multicast setup descriptor. 1871 */ 1872 mcsp->next = sc->cbl_base; 1873 mcsp->mb_head = NULL; 1874 mcsp->cb_status = 0; 1875 mcsp->cb_command = FXP_CB_COMMAND_MCAS | 1876 FXP_CB_COMMAND_S | FXP_CB_COMMAND_I; 1877 mcsp->link_addr = vtophys(&sc->cbl_base->cb_status); 1878 1879 nmcasts = 0; 1880 if ((sc->flags & FXP_FLAG_ALL_MCAST) == 0) { 1881 #if __FreeBSD_version < 500000 1882 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1883 #else 1884 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1885 #endif 1886 if (ifma->ifma_addr->sa_family != AF_LINK) 1887 continue; 1888 if (nmcasts >= MAXMCADDR) { 1889 sc->flags |= FXP_FLAG_ALL_MCAST; 1890 nmcasts = 0; 1891 break; 1892 } 1893 bcopy(LLADDR((struct sockaddr_dl *)ifma->ifma_addr), 1894 (void *)(uintptr_t)(volatile void *) 1895 &sc->mcsp->mc_addr[nmcasts][0], 6); 1896 nmcasts++; 1897 } 1898 } 1899 mcsp->mc_cnt = nmcasts * 6; 1900 sc->cbl_first = sc->cbl_last = (struct fxp_cb_tx *) mcsp; 1901 sc->tx_queued = 1; 1902 1903 /* 1904 * Wait until command unit is not active. This should never 1905 * be the case when nothing is queued, but make sure anyway. 1906 */ 1907 count = 100; 1908 while ((CSR_READ_1(sc, FXP_CSR_SCB_RUSCUS) >> 6) == 1909 FXP_SCB_CUS_ACTIVE && --count) 1910 DELAY(10); 1911 if (count == 0) { 1912 device_printf(sc->dev, "command queue timeout\n"); 1913 return; 1914 } 1915 1916 /* 1917 * Start the multicast setup command. 1918 */ 1919 fxp_scb_wait(sc); 1920 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, vtophys(&mcsp->cb_status)); 1921 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 1922 1923 ifp->if_timer = 2; 1924 return; 1925 } 1926