1 /*- 2 * Copyright (c) 1995, David Greenman 3 * Copyright (c) 2001 Jonathan Lemon <jlemon@freebsd.org> 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice unmodified, this list of conditions, and the following 11 * disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 * 28 * $FreeBSD$ 29 */ 30 31 /* 32 * Intel EtherExpress Pro/100B PCI Fast Ethernet driver 33 */ 34 35 #include <sys/param.h> 36 #include <sys/systm.h> 37 #include <sys/mbuf.h> 38 #include <sys/malloc.h> 39 /* #include <sys/mutex.h> */ 40 #include <sys/kernel.h> 41 #include <sys/socket.h> 42 43 #include <net/if.h> 44 #include <net/if_dl.h> 45 #include <net/if_media.h> 46 47 #ifdef NS 48 #include <netns/ns.h> 49 #include <netns/ns_if.h> 50 #endif 51 52 #include <net/bpf.h> 53 #include <sys/sockio.h> 54 #include <sys/bus.h> 55 #include <machine/bus.h> 56 #include <sys/rman.h> 57 #include <machine/resource.h> 58 59 #include <net/ethernet.h> 60 #include <net/if_arp.h> 61 62 #include <vm/vm.h> /* for vtophys */ 63 #include <vm/pmap.h> /* for vtophys */ 64 #include <machine/clock.h> /* for DELAY */ 65 66 #include <net/if_types.h> 67 #include <net/if_vlan_var.h> 68 69 #include <pci/pcivar.h> 70 #include <pci/pcireg.h> /* for PCIM_CMD_xxx */ 71 72 #include <dev/mii/mii.h> 73 #include <dev/mii/miivar.h> 74 75 #include <dev/fxp/if_fxpreg.h> 76 #include <dev/fxp/if_fxpvar.h> 77 78 MODULE_DEPEND(fxp, miibus, 1, 1, 1); 79 #include "miibus_if.h" 80 81 /* 82 * NOTE! On the Alpha, we have an alignment constraint. The 83 * card DMAs the packet immediately following the RFA. However, 84 * the first thing in the packet is a 14-byte Ethernet header. 85 * This means that the packet is misaligned. To compensate, 86 * we actually offset the RFA 2 bytes into the cluster. This 87 * alignes the packet after the Ethernet header at a 32-bit 88 * boundary. HOWEVER! This means that the RFA is misaligned! 89 */ 90 #define RFA_ALIGNMENT_FUDGE 2 91 92 /* 93 * Set initial transmit threshold at 64 (512 bytes). This is 94 * increased by 64 (512 bytes) at a time, to maximum of 192 95 * (1536 bytes), if an underrun occurs. 96 */ 97 static int tx_threshold = 64; 98 99 /* 100 * The configuration byte map has several undefined fields which 101 * must be one or must be zero. Set up a template for these bits 102 * only, (assuming a 82557 chip) leaving the actual configuration 103 * to fxp_init. 104 * 105 * See struct fxp_cb_config for the bit definitions. 106 */ 107 static u_char fxp_cb_config_template[] = { 108 0x0, 0x0, /* cb_status */ 109 0x0, 0x0, /* cb_command */ 110 0x0, 0x0, 0x0, 0x0, /* link_addr */ 111 0x0, /* 0 */ 112 0x0, /* 1 */ 113 0x0, /* 2 */ 114 0x0, /* 3 */ 115 0x0, /* 4 */ 116 0x0, /* 5 */ 117 0x32, /* 6 */ 118 0x0, /* 7 */ 119 0x0, /* 8 */ 120 0x0, /* 9 */ 121 0x6, /* 10 */ 122 0x0, /* 11 */ 123 0x0, /* 12 */ 124 0x0, /* 13 */ 125 0xf2, /* 14 */ 126 0x48, /* 15 */ 127 0x0, /* 16 */ 128 0x40, /* 17 */ 129 0xf0, /* 18 */ 130 0x0, /* 19 */ 131 0x3f, /* 20 */ 132 0x5 /* 21 */ 133 }; 134 135 struct fxp_ident { 136 u_int16_t devid; 137 char *name; 138 }; 139 140 /* 141 * Claim various Intel PCI device identifiers for this driver. The 142 * sub-vendor and sub-device field are extensively used to identify 143 * particular variants, but we don't currently differentiate between 144 * them. 145 */ 146 static struct fxp_ident fxp_ident_table[] = { 147 { 0x1229, "Intel Pro 10/100B/100+ Ethernet" }, 148 { 0x2449, "Intel Pro/100 Ethernet" }, 149 { 0x1209, "Intel Embedded 10/100 Ethernet" }, 150 { 0x1029, "Intel Pro/100 Ethernet" }, 151 { 0x1030, "Intel Pro/100 Ethernet" }, 152 { 0x1031, "Intel Pro/100 Ethernet" }, 153 { 0x1032, "Intel Pro/100 Ethernet" }, 154 { 0x1033, "Intel Pro/100 Ethernet" }, 155 { 0x1034, "Intel Pro/100 Ethernet" }, 156 { 0x1035, "Intel Pro/100 Ethernet" }, 157 { 0x1036, "Intel Pro/100 Ethernet" }, 158 { 0x1037, "Intel Pro/100 Ethernet" }, 159 { 0x1038, "Intel Pro/100 Ethernet" }, 160 { 0, NULL }, 161 }; 162 163 static int fxp_probe(device_t dev); 164 static int fxp_attach(device_t dev); 165 static int fxp_detach(device_t dev); 166 static int fxp_shutdown(device_t dev); 167 static int fxp_suspend(device_t dev); 168 static int fxp_resume(device_t dev); 169 170 static void fxp_intr(void *xsc); 171 static void fxp_init(void *xsc); 172 static void fxp_tick(void *xsc); 173 static void fxp_powerstate_d0(device_t dev); 174 static void fxp_start(struct ifnet *ifp); 175 static void fxp_stop(struct fxp_softc *sc); 176 static void fxp_release(struct fxp_softc *sc); 177 static int fxp_ioctl(struct ifnet *ifp, u_long command, 178 caddr_t data); 179 static void fxp_watchdog(struct ifnet *ifp); 180 static int fxp_add_rfabuf(struct fxp_softc *sc, struct mbuf *oldm); 181 static void fxp_mc_setup(struct fxp_softc *sc); 182 static u_int16_t fxp_eeprom_getword(struct fxp_softc *sc, int offset, 183 int autosize); 184 static void fxp_eeprom_putword(struct fxp_softc *sc, int offset, 185 u_int16_t data); 186 static void fxp_autosize_eeprom(struct fxp_softc *sc); 187 static void fxp_read_eeprom(struct fxp_softc *sc, u_short *data, 188 int offset, int words); 189 static void fxp_write_eeprom(struct fxp_softc *sc, u_short *data, 190 int offset, int words); 191 static int fxp_ifmedia_upd(struct ifnet *ifp); 192 static void fxp_ifmedia_sts(struct ifnet *ifp, 193 struct ifmediareq *ifmr); 194 static int fxp_serial_ifmedia_upd(struct ifnet *ifp); 195 static void fxp_serial_ifmedia_sts(struct ifnet *ifp, 196 struct ifmediareq *ifmr); 197 static volatile int fxp_miibus_readreg(device_t dev, int phy, int reg); 198 static void fxp_miibus_writereg(device_t dev, int phy, int reg, 199 int value); 200 static __inline void fxp_lwcopy(volatile u_int32_t *src, 201 volatile u_int32_t *dst); 202 static __inline void fxp_scb_wait(struct fxp_softc *sc); 203 static __inline void fxp_scb_cmd(struct fxp_softc *sc, int cmd); 204 static __inline void fxp_dma_wait(volatile u_int16_t *status, 205 struct fxp_softc *sc); 206 207 static device_method_t fxp_methods[] = { 208 /* Device interface */ 209 DEVMETHOD(device_probe, fxp_probe), 210 DEVMETHOD(device_attach, fxp_attach), 211 DEVMETHOD(device_detach, fxp_detach), 212 DEVMETHOD(device_shutdown, fxp_shutdown), 213 DEVMETHOD(device_suspend, fxp_suspend), 214 DEVMETHOD(device_resume, fxp_resume), 215 216 /* MII interface */ 217 DEVMETHOD(miibus_readreg, fxp_miibus_readreg), 218 DEVMETHOD(miibus_writereg, fxp_miibus_writereg), 219 220 { 0, 0 } 221 }; 222 223 static driver_t fxp_driver = { 224 "fxp", 225 fxp_methods, 226 sizeof(struct fxp_softc), 227 }; 228 229 static devclass_t fxp_devclass; 230 231 DRIVER_MODULE(if_fxp, pci, fxp_driver, fxp_devclass, 0, 0); 232 DRIVER_MODULE(if_fxp, cardbus, fxp_driver, fxp_devclass, 0, 0); 233 DRIVER_MODULE(miibus, fxp, miibus_driver, miibus_devclass, 0, 0); 234 235 /* 236 * Inline function to copy a 16-bit aligned 32-bit quantity. 237 */ 238 static __inline void 239 fxp_lwcopy(volatile u_int32_t *src, volatile u_int32_t *dst) 240 { 241 #ifdef __i386__ 242 *dst = *src; 243 #else 244 volatile u_int16_t *a = (volatile u_int16_t *)src; 245 volatile u_int16_t *b = (volatile u_int16_t *)dst; 246 247 b[0] = a[0]; 248 b[1] = a[1]; 249 #endif 250 } 251 252 /* 253 * Wait for the previous command to be accepted (but not necessarily 254 * completed). 255 */ 256 static __inline void 257 fxp_scb_wait(struct fxp_softc *sc) 258 { 259 int i = 10000; 260 261 while (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) && --i) 262 DELAY(2); 263 if (i == 0) 264 device_printf(sc->dev, "SCB timeout: 0x%x 0x%x 0x%x 0x%x\n", 265 CSR_READ_1(sc, FXP_CSR_SCB_COMMAND), 266 CSR_READ_1(sc, FXP_CSR_SCB_STATACK), 267 CSR_READ_1(sc, FXP_CSR_SCB_RUSCUS), 268 CSR_READ_2(sc, FXP_CSR_FLOWCONTROL)); 269 } 270 271 static __inline void 272 fxp_scb_cmd(struct fxp_softc *sc, int cmd) 273 { 274 275 if (cmd == FXP_SCB_COMMAND_CU_RESUME && sc->cu_resume_bug) { 276 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_CB_COMMAND_NOP); 277 fxp_scb_wait(sc); 278 } 279 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, cmd); 280 } 281 282 static __inline void 283 fxp_dma_wait(volatile u_int16_t *status, struct fxp_softc *sc) 284 { 285 int i = 10000; 286 287 while (!(*status & FXP_CB_STATUS_C) && --i) 288 DELAY(2); 289 if (i == 0) 290 device_printf(sc->dev, "DMA timeout\n"); 291 } 292 293 /* 294 * Return identification string if this is device is ours. 295 */ 296 static int 297 fxp_probe(device_t dev) 298 { 299 u_int16_t devid; 300 struct fxp_ident *ident; 301 302 if (pci_get_vendor(dev) == FXP_VENDORID_INTEL) { 303 devid = pci_get_device(dev); 304 for (ident = fxp_ident_table; ident->name != NULL; ident++) { 305 if (ident->devid == devid) { 306 device_set_desc(dev, ident->name); 307 return (0); 308 } 309 } 310 } 311 return (ENXIO); 312 } 313 314 static void 315 fxp_powerstate_d0(device_t dev) 316 { 317 #if __FreeBSD_version >= 430002 318 u_int32_t iobase, membase, irq; 319 320 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 321 /* Save important PCI config data. */ 322 iobase = pci_read_config(dev, FXP_PCI_IOBA, 4); 323 membase = pci_read_config(dev, FXP_PCI_MMBA, 4); 324 irq = pci_read_config(dev, PCIR_INTLINE, 4); 325 326 /* Reset the power state. */ 327 device_printf(dev, "chip is in D%d power mode " 328 "-- setting to D0\n", pci_get_powerstate(dev)); 329 330 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 331 332 /* Restore PCI config data. */ 333 pci_write_config(dev, FXP_PCI_IOBA, iobase, 4); 334 pci_write_config(dev, FXP_PCI_MMBA, membase, 4); 335 pci_write_config(dev, PCIR_INTLINE, irq, 4); 336 } 337 #endif 338 } 339 340 static int 341 fxp_attach(device_t dev) 342 { 343 int error = 0; 344 struct fxp_softc *sc = device_get_softc(dev); 345 struct ifnet *ifp; 346 u_int32_t val; 347 u_int16_t data; 348 int i, rid, m1, m2, prefer_iomap; 349 int s; 350 351 bzero(sc, sizeof(*sc)); 352 sc->dev = dev; 353 callout_handle_init(&sc->stat_ch); 354 mtx_init(&sc->sc_mtx, device_get_nameunit(dev), MTX_DEF | MTX_RECURSE); 355 356 s = splimp(); 357 358 /* 359 * Enable bus mastering. Enable memory space too, in case 360 * BIOS/Prom forgot about it. 361 */ 362 val = pci_read_config(dev, PCIR_COMMAND, 2); 363 val |= (PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN); 364 pci_write_config(dev, PCIR_COMMAND, val, 2); 365 val = pci_read_config(dev, PCIR_COMMAND, 2); 366 367 fxp_powerstate_d0(dev); 368 369 /* 370 * Figure out which we should try first - memory mapping or i/o mapping? 371 * We default to memory mapping. Then we accept an override from the 372 * command line. Then we check to see which one is enabled. 373 */ 374 m1 = PCIM_CMD_MEMEN; 375 m2 = PCIM_CMD_PORTEN; 376 prefer_iomap = 0; 377 if (resource_int_value(device_get_name(dev), device_get_unit(dev), 378 "prefer_iomap", &prefer_iomap) == 0 && prefer_iomap != 0) { 379 m1 = PCIM_CMD_PORTEN; 380 m2 = PCIM_CMD_MEMEN; 381 } 382 383 if (val & m1) { 384 sc->rtp = 385 (m1 == PCIM_CMD_MEMEN)? SYS_RES_MEMORY : SYS_RES_IOPORT; 386 sc->rgd = (m1 == PCIM_CMD_MEMEN)? FXP_PCI_MMBA : FXP_PCI_IOBA; 387 sc->mem = bus_alloc_resource(dev, sc->rtp, &sc->rgd, 388 0, ~0, 1, RF_ACTIVE); 389 } 390 if (sc->mem == NULL && (val & m2)) { 391 sc->rtp = 392 (m2 == PCIM_CMD_MEMEN)? SYS_RES_MEMORY : SYS_RES_IOPORT; 393 sc->rgd = (m2 == PCIM_CMD_MEMEN)? FXP_PCI_MMBA : FXP_PCI_IOBA; 394 sc->mem = bus_alloc_resource(dev, sc->rtp, &sc->rgd, 395 0, ~0, 1, RF_ACTIVE); 396 } 397 398 if (!sc->mem) { 399 device_printf(dev, "could not map device registers\n"); 400 error = ENXIO; 401 goto fail; 402 } 403 if (bootverbose) { 404 device_printf(dev, "using %s space register mapping\n", 405 sc->rtp == SYS_RES_MEMORY? "memory" : "I/O"); 406 } 407 408 sc->sc_st = rman_get_bustag(sc->mem); 409 sc->sc_sh = rman_get_bushandle(sc->mem); 410 411 /* 412 * Allocate our interrupt. 413 */ 414 rid = 0; 415 sc->irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 416 RF_SHAREABLE | RF_ACTIVE); 417 if (sc->irq == NULL) { 418 device_printf(dev, "could not map interrupt\n"); 419 error = ENXIO; 420 goto fail; 421 } 422 423 error = bus_setup_intr(dev, sc->irq, INTR_TYPE_NET, 424 fxp_intr, sc, &sc->ih); 425 if (error) { 426 device_printf(dev, "could not setup irq\n"); 427 goto fail; 428 } 429 430 /* 431 * Reset to a stable state. 432 */ 433 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET); 434 DELAY(10); 435 436 sc->cbl_base = malloc(sizeof(struct fxp_cb_tx) * FXP_NTXCB, 437 M_DEVBUF, M_NOWAIT | M_ZERO); 438 if (sc->cbl_base == NULL) 439 goto failmem; 440 441 sc->fxp_stats = malloc(sizeof(struct fxp_stats), M_DEVBUF, 442 M_NOWAIT | M_ZERO); 443 if (sc->fxp_stats == NULL) 444 goto failmem; 445 446 sc->mcsp = malloc(sizeof(struct fxp_cb_mcs), M_DEVBUF, M_NOWAIT); 447 if (sc->mcsp == NULL) 448 goto failmem; 449 450 /* 451 * Pre-allocate our receive buffers. 452 */ 453 for (i = 0; i < FXP_NRFABUFS; i++) { 454 if (fxp_add_rfabuf(sc, NULL) != 0) { 455 goto failmem; 456 } 457 } 458 459 /* 460 * Find out how large of an SEEPROM we have. 461 */ 462 fxp_autosize_eeprom(sc); 463 464 /* 465 * Determine whether we must use the 503 serial interface. 466 */ 467 fxp_read_eeprom(sc, &data, 6, 1); 468 if ((data & FXP_PHY_DEVICE_MASK) != 0 && 469 (data & FXP_PHY_SERIAL_ONLY)) 470 sc->flags |= FXP_FLAG_SERIAL_MEDIA; 471 472 /* 473 * Find out the basic controller type; we currently only 474 * differentiate between a 82557 and greater. 475 */ 476 fxp_read_eeprom(sc, &data, 5, 1); 477 if ((data >> 8) == 1) 478 sc->chip = FXP_CHIP_82557; 479 480 /* 481 * Enable workarounds for certain chip revision deficiencies. 482 * 483 * Systems based on the ICH2/ICH2-M chip from Intel have a defect 484 * where the chip can cause a PCI protocol violation if it receives 485 * a CU_RESUME command when it is entering the IDLE state. The 486 * workaround is to disable Dynamic Standby Mode, so the chip never 487 * deasserts CLKRUN#, and always remains in an active state. 488 * 489 * See Intel 82801BA/82801BAM Specification Update, Errata #30. 490 */ 491 i = pci_get_device(dev); 492 if (i == 0x2449 || (i > 0x1030 && i < 0x1039)) { 493 fxp_read_eeprom(sc, &data, 10, 1); 494 if (data & 0x02) { /* STB enable */ 495 u_int16_t cksum; 496 int i; 497 498 device_printf(dev, 499 "*** DISABLING DYNAMIC STANDBY MODE IN EEPROM ***\n"); 500 data &= ~0x02; 501 fxp_write_eeprom(sc, &data, 10, 1); 502 device_printf(dev, "New EEPROM ID: 0x%x\n", data); 503 cksum = 0; 504 for (i = 0; i < (1 << sc->eeprom_size) - 1; i++) { 505 fxp_read_eeprom(sc, &data, i, 1); 506 cksum += data; 507 } 508 i = (1 << sc->eeprom_size) - 1; 509 cksum = 0xBABA - cksum; 510 fxp_read_eeprom(sc, &data, i, 1); 511 fxp_write_eeprom(sc, &cksum, i, 1); 512 device_printf(dev, 513 "EEPROM checksum @ 0x%x: 0x%x -> 0x%x\n", 514 i, data, cksum); 515 /* 516 * We need to do a full PCI reset here. A software 517 * reset to the port doesn't cut it, but let's try 518 * anyway. 519 */ 520 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SOFTWARE_RESET); 521 DELAY(50); 522 device_printf(dev, 523 "*** PLEASE REBOOT THE SYSTEM NOW FOR CORRECT OPERATION ***\n"); 524 #if 1 525 /* 526 * If the user elects to continue, try the software 527 * workaround, as it is better than nothing. 528 */ 529 sc->flags |= FXP_FLAG_CU_RESUME_BUG; 530 #endif 531 } 532 } 533 534 /* 535 * If we are not a 82557 chip, we can enable extended features. 536 */ 537 if (sc->chip != FXP_CHIP_82557) { 538 /* 539 * If MWI is enabled in the PCI configuration, and there 540 * is a valid cacheline size (8 or 16 dwords), then tell 541 * the board to turn on MWI. 542 */ 543 if (val & PCIM_CMD_MWRICEN && 544 pci_read_config(dev, PCIR_CACHELNSZ, 1) != 0) 545 sc->flags |= FXP_FLAG_MWI_ENABLE; 546 547 /* turn on the extended TxCB feature */ 548 sc->flags |= FXP_FLAG_EXT_TXCB; 549 550 /* enable reception of long frames for VLAN */ 551 sc->flags |= FXP_FLAG_LONG_PKT_EN; 552 } 553 554 /* 555 * Read MAC address. 556 */ 557 fxp_read_eeprom(sc, (u_int16_t *)sc->arpcom.ac_enaddr, 0, 3); 558 device_printf(dev, "Ethernet address %6D%s\n", 559 sc->arpcom.ac_enaddr, ":", 560 sc->flags & FXP_FLAG_SERIAL_MEDIA ? ", 10Mbps" : ""); 561 if (bootverbose) { 562 device_printf(dev, "PCI IDs: %04x %04x %04x %04x %04x\n", 563 pci_get_vendor(dev), pci_get_device(dev), 564 pci_get_subvendor(dev), pci_get_subdevice(dev), 565 pci_get_revid(dev)); 566 device_printf(dev, "Chip Type: %d\n", sc->chip); 567 } 568 569 /* 570 * If this is only a 10Mbps device, then there is no MII, and 571 * the PHY will use a serial interface instead. 572 * 573 * The Seeq 80c24 AutoDUPLEX(tm) Ethernet Interface Adapter 574 * doesn't have a programming interface of any sort. The 575 * media is sensed automatically based on how the link partner 576 * is configured. This is, in essence, manual configuration. 577 */ 578 if (sc->flags & FXP_FLAG_SERIAL_MEDIA) { 579 ifmedia_init(&sc->sc_media, 0, fxp_serial_ifmedia_upd, 580 fxp_serial_ifmedia_sts); 581 ifmedia_add(&sc->sc_media, IFM_ETHER|IFM_MANUAL, 0, NULL); 582 ifmedia_set(&sc->sc_media, IFM_ETHER|IFM_MANUAL); 583 } else { 584 if (mii_phy_probe(dev, &sc->miibus, fxp_ifmedia_upd, 585 fxp_ifmedia_sts)) { 586 device_printf(dev, "MII without any PHY!\n"); 587 error = ENXIO; 588 goto fail; 589 } 590 } 591 592 ifp = &sc->arpcom.ac_if; 593 ifp->if_unit = device_get_unit(dev); 594 ifp->if_name = "fxp"; 595 ifp->if_output = ether_output; 596 ifp->if_baudrate = 100000000; 597 ifp->if_init = fxp_init; 598 ifp->if_softc = sc; 599 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 600 ifp->if_ioctl = fxp_ioctl; 601 ifp->if_start = fxp_start; 602 ifp->if_watchdog = fxp_watchdog; 603 604 /* 605 * Attach the interface. 606 */ 607 ether_ifattach(ifp, ETHER_BPF_SUPPORTED); 608 609 /* 610 * Tell the upper layer(s) we support long frames. 611 */ 612 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 613 614 /* 615 * Let the system queue as many packets as we have available 616 * TX descriptors. 617 */ 618 ifp->if_snd.ifq_maxlen = FXP_NTXCB - 1; 619 620 splx(s); 621 return (0); 622 623 failmem: 624 device_printf(dev, "Failed to malloc memory\n"); 625 error = ENOMEM; 626 fail: 627 splx(s); 628 fxp_release(sc); 629 return (error); 630 } 631 632 /* 633 * release all resources 634 */ 635 static void 636 fxp_release(struct fxp_softc *sc) 637 { 638 639 bus_generic_detach(sc->dev); 640 if (sc->miibus) 641 device_delete_child(sc->dev, sc->miibus); 642 643 if (sc->cbl_base) 644 free(sc->cbl_base, M_DEVBUF); 645 if (sc->fxp_stats) 646 free(sc->fxp_stats, M_DEVBUF); 647 if (sc->mcsp) 648 free(sc->mcsp, M_DEVBUF); 649 if (sc->rfa_headm) 650 m_freem(sc->rfa_headm); 651 652 if (sc->ih) 653 bus_teardown_intr(sc->dev, sc->irq, sc->ih); 654 if (sc->irq) 655 bus_release_resource(sc->dev, SYS_RES_IRQ, 0, sc->irq); 656 if (sc->mem) 657 bus_release_resource(sc->dev, sc->rtp, sc->rgd, sc->mem); 658 mtx_destroy(&sc->sc_mtx); 659 } 660 661 /* 662 * Detach interface. 663 */ 664 static int 665 fxp_detach(device_t dev) 666 { 667 struct fxp_softc *sc = device_get_softc(dev); 668 int s; 669 670 /* disable interrupts */ 671 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE); 672 673 s = splimp(); 674 675 /* 676 * Stop DMA and drop transmit queue. 677 */ 678 fxp_stop(sc); 679 680 /* 681 * Close down routes etc. 682 */ 683 ether_ifdetach(&sc->arpcom.ac_if, ETHER_BPF_SUPPORTED); 684 685 /* 686 * Free all media structures. 687 */ 688 ifmedia_removeall(&sc->sc_media); 689 690 splx(s); 691 692 /* Release our allocated resources. */ 693 fxp_release(sc); 694 695 return (0); 696 } 697 698 /* 699 * Device shutdown routine. Called at system shutdown after sync. The 700 * main purpose of this routine is to shut off receiver DMA so that 701 * kernel memory doesn't get clobbered during warmboot. 702 */ 703 static int 704 fxp_shutdown(device_t dev) 705 { 706 /* 707 * Make sure that DMA is disabled prior to reboot. Not doing 708 * do could allow DMA to corrupt kernel memory during the 709 * reboot before the driver initializes. 710 */ 711 fxp_stop((struct fxp_softc *) device_get_softc(dev)); 712 return (0); 713 } 714 715 /* 716 * Device suspend routine. Stop the interface and save some PCI 717 * settings in case the BIOS doesn't restore them properly on 718 * resume. 719 */ 720 static int 721 fxp_suspend(device_t dev) 722 { 723 struct fxp_softc *sc = device_get_softc(dev); 724 int i, s; 725 726 s = splimp(); 727 728 fxp_stop(sc); 729 730 for (i = 0; i < 5; i++) 731 sc->saved_maps[i] = pci_read_config(dev, PCIR_MAPS + i * 4, 4); 732 sc->saved_biosaddr = pci_read_config(dev, PCIR_BIOS, 4); 733 sc->saved_intline = pci_read_config(dev, PCIR_INTLINE, 1); 734 sc->saved_cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1); 735 sc->saved_lattimer = pci_read_config(dev, PCIR_LATTIMER, 1); 736 737 sc->suspended = 1; 738 739 splx(s); 740 return (0); 741 } 742 743 /* 744 * Device resume routine. Restore some PCI settings in case the BIOS 745 * doesn't, re-enable busmastering, and restart the interface if 746 * appropriate. 747 */ 748 static int 749 fxp_resume(device_t dev) 750 { 751 struct fxp_softc *sc = device_get_softc(dev); 752 struct ifnet *ifp = &sc->sc_if; 753 u_int16_t pci_command; 754 int i, s; 755 756 s = splimp(); 757 758 fxp_powerstate_d0(dev); 759 760 /* better way to do this? */ 761 for (i = 0; i < 5; i++) 762 pci_write_config(dev, PCIR_MAPS + i * 4, sc->saved_maps[i], 4); 763 pci_write_config(dev, PCIR_BIOS, sc->saved_biosaddr, 4); 764 pci_write_config(dev, PCIR_INTLINE, sc->saved_intline, 1); 765 pci_write_config(dev, PCIR_CACHELNSZ, sc->saved_cachelnsz, 1); 766 pci_write_config(dev, PCIR_LATTIMER, sc->saved_lattimer, 1); 767 768 /* reenable busmastering */ 769 pci_command = pci_read_config(dev, PCIR_COMMAND, 2); 770 pci_command |= (PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN); 771 pci_write_config(dev, PCIR_COMMAND, pci_command, 2); 772 773 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET); 774 DELAY(10); 775 776 /* reinitialize interface if necessary */ 777 if (ifp->if_flags & IFF_UP) 778 fxp_init(sc); 779 780 sc->suspended = 0; 781 782 splx(s); 783 return (0); 784 } 785 786 static void 787 fxp_eeprom_shiftin(struct fxp_softc *sc, int data, int length) 788 { 789 u_int16_t reg; 790 int x; 791 792 /* 793 * Shift in data. 794 */ 795 for (x = 1 << (length - 1); x; x >>= 1) { 796 if (data & x) 797 reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI; 798 else 799 reg = FXP_EEPROM_EECS; 800 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 801 DELAY(1); 802 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK); 803 DELAY(1); 804 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 805 DELAY(1); 806 } 807 } 808 809 /* 810 * Read from the serial EEPROM. Basically, you manually shift in 811 * the read opcode (one bit at a time) and then shift in the address, 812 * and then you shift out the data (all of this one bit at a time). 813 * The word size is 16 bits, so you have to provide the address for 814 * every 16 bits of data. 815 */ 816 static u_int16_t 817 fxp_eeprom_getword(struct fxp_softc *sc, int offset, int autosize) 818 { 819 u_int16_t reg, data; 820 int x; 821 822 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 823 /* 824 * Shift in read opcode. 825 */ 826 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_READ, 3); 827 /* 828 * Shift in address. 829 */ 830 data = 0; 831 for (x = 1 << (sc->eeprom_size - 1); x; x >>= 1) { 832 if (offset & x) 833 reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI; 834 else 835 reg = FXP_EEPROM_EECS; 836 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 837 DELAY(1); 838 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK); 839 DELAY(1); 840 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 841 DELAY(1); 842 reg = CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO; 843 data++; 844 if (autosize && reg == 0) { 845 sc->eeprom_size = data; 846 break; 847 } 848 } 849 /* 850 * Shift out data. 851 */ 852 data = 0; 853 reg = FXP_EEPROM_EECS; 854 for (x = 1 << 15; x; x >>= 1) { 855 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK); 856 DELAY(1); 857 if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO) 858 data |= x; 859 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 860 DELAY(1); 861 } 862 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 863 DELAY(1); 864 865 return (data); 866 } 867 868 static void 869 fxp_eeprom_putword(struct fxp_softc *sc, int offset, u_int16_t data) 870 { 871 int i; 872 873 /* 874 * Erase/write enable. 875 */ 876 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 877 fxp_eeprom_shiftin(sc, 0x4, 3); 878 fxp_eeprom_shiftin(sc, 0x03 << (sc->eeprom_size - 2), sc->eeprom_size); 879 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 880 DELAY(1); 881 /* 882 * Shift in write opcode, address, data. 883 */ 884 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 885 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_WRITE, 3); 886 fxp_eeprom_shiftin(sc, offset, sc->eeprom_size); 887 fxp_eeprom_shiftin(sc, data, 16); 888 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 889 DELAY(1); 890 /* 891 * Wait for EEPROM to finish up. 892 */ 893 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 894 DELAY(1); 895 for (i = 0; i < 1000; i++) { 896 if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO) 897 break; 898 DELAY(50); 899 } 900 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 901 DELAY(1); 902 /* 903 * Erase/write disable. 904 */ 905 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 906 fxp_eeprom_shiftin(sc, 0x4, 3); 907 fxp_eeprom_shiftin(sc, 0, sc->eeprom_size); 908 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 909 DELAY(1); 910 } 911 912 /* 913 * From NetBSD: 914 * 915 * Figure out EEPROM size. 916 * 917 * 559's can have either 64-word or 256-word EEPROMs, the 558 918 * datasheet only talks about 64-word EEPROMs, and the 557 datasheet 919 * talks about the existance of 16 to 256 word EEPROMs. 920 * 921 * The only known sizes are 64 and 256, where the 256 version is used 922 * by CardBus cards to store CIS information. 923 * 924 * The address is shifted in msb-to-lsb, and after the last 925 * address-bit the EEPROM is supposed to output a `dummy zero' bit, 926 * after which follows the actual data. We try to detect this zero, by 927 * probing the data-out bit in the EEPROM control register just after 928 * having shifted in a bit. If the bit is zero, we assume we've 929 * shifted enough address bits. The data-out should be tri-state, 930 * before this, which should translate to a logical one. 931 */ 932 static void 933 fxp_autosize_eeprom(struct fxp_softc *sc) 934 { 935 936 /* guess maximum size of 256 words */ 937 sc->eeprom_size = 8; 938 939 /* autosize */ 940 (void) fxp_eeprom_getword(sc, 0, 1); 941 } 942 943 static void 944 fxp_read_eeprom(struct fxp_softc *sc, u_short *data, int offset, int words) 945 { 946 int i; 947 948 for (i = 0; i < words; i++) 949 data[i] = fxp_eeprom_getword(sc, offset + i, 0); 950 } 951 952 static void 953 fxp_write_eeprom(struct fxp_softc *sc, u_short *data, int offset, int words) 954 { 955 int i; 956 957 for (i = 0; i < words; i++) 958 fxp_eeprom_putword(sc, offset + i, data[i]); 959 } 960 961 /* 962 * Start packet transmission on the interface. 963 */ 964 static void 965 fxp_start(struct ifnet *ifp) 966 { 967 struct fxp_softc *sc = ifp->if_softc; 968 struct fxp_cb_tx *txp; 969 970 /* 971 * See if we need to suspend xmit until the multicast filter 972 * has been reprogrammed (which can only be done at the head 973 * of the command chain). 974 */ 975 if (sc->need_mcsetup) { 976 return; 977 } 978 979 txp = NULL; 980 981 /* 982 * We're finished if there is nothing more to add to the list or if 983 * we're all filled up with buffers to transmit. 984 * NOTE: One TxCB is reserved to guarantee that fxp_mc_setup() can add 985 * a NOP command when needed. 986 */ 987 while (ifp->if_snd.ifq_head != NULL && sc->tx_queued < FXP_NTXCB - 1) { 988 struct mbuf *m, *mb_head; 989 int segment; 990 991 /* 992 * Grab a packet to transmit. 993 */ 994 IF_DEQUEUE(&ifp->if_snd, mb_head); 995 996 /* 997 * Get pointer to next available tx desc. 998 */ 999 txp = sc->cbl_last->next; 1000 1001 /* 1002 * Go through each of the mbufs in the chain and initialize 1003 * the transmit buffer descriptors with the physical address 1004 * and size of the mbuf. 1005 */ 1006 tbdinit: 1007 for (m = mb_head, segment = 0; m != NULL; m = m->m_next) { 1008 if (m->m_len != 0) { 1009 if (segment == FXP_NTXSEG) 1010 break; 1011 txp->tbd[segment].tb_addr = 1012 vtophys(mtod(m, vm_offset_t)); 1013 txp->tbd[segment].tb_size = m->m_len; 1014 segment++; 1015 } 1016 } 1017 if (m != NULL) { 1018 struct mbuf *mn; 1019 1020 /* 1021 * We ran out of segments. We have to recopy this 1022 * mbuf chain first. Bail out if we can't get the 1023 * new buffers. 1024 */ 1025 MGETHDR(mn, M_DONTWAIT, MT_DATA); 1026 if (mn == NULL) { 1027 m_freem(mb_head); 1028 break; 1029 } 1030 if (mb_head->m_pkthdr.len > MHLEN) { 1031 MCLGET(mn, M_DONTWAIT); 1032 if ((mn->m_flags & M_EXT) == 0) { 1033 m_freem(mn); 1034 m_freem(mb_head); 1035 break; 1036 } 1037 } 1038 m_copydata(mb_head, 0, mb_head->m_pkthdr.len, 1039 mtod(mn, caddr_t)); 1040 mn->m_pkthdr.len = mn->m_len = mb_head->m_pkthdr.len; 1041 m_freem(mb_head); 1042 mb_head = mn; 1043 goto tbdinit; 1044 } 1045 1046 txp->tbd_number = segment; 1047 txp->mb_head = mb_head; 1048 txp->cb_status = 0; 1049 if (sc->tx_queued != FXP_CXINT_THRESH - 1) { 1050 txp->cb_command = 1051 FXP_CB_COMMAND_XMIT | FXP_CB_COMMAND_SF | 1052 FXP_CB_COMMAND_S; 1053 } else { 1054 txp->cb_command = 1055 FXP_CB_COMMAND_XMIT | FXP_CB_COMMAND_SF | 1056 FXP_CB_COMMAND_S | FXP_CB_COMMAND_I; 1057 /* 1058 * Set a 5 second timer just in case we don't hear 1059 * from the card again. 1060 */ 1061 ifp->if_timer = 5; 1062 } 1063 txp->tx_threshold = tx_threshold; 1064 1065 /* 1066 * Advance the end of list forward. 1067 */ 1068 1069 #ifdef __alpha__ 1070 /* 1071 * On platforms which can't access memory in 16-bit 1072 * granularities, we must prevent the card from DMA'ing 1073 * up the status while we update the command field. 1074 * This could cause us to overwrite the completion status. 1075 */ 1076 atomic_clear_short(&sc->cbl_last->cb_command, 1077 FXP_CB_COMMAND_S); 1078 #else 1079 sc->cbl_last->cb_command &= ~FXP_CB_COMMAND_S; 1080 #endif /*__alpha__*/ 1081 sc->cbl_last = txp; 1082 1083 /* 1084 * Advance the beginning of the list forward if there are 1085 * no other packets queued (when nothing is queued, cbl_first 1086 * sits on the last TxCB that was sent out). 1087 */ 1088 if (sc->tx_queued == 0) 1089 sc->cbl_first = txp; 1090 1091 sc->tx_queued++; 1092 1093 /* 1094 * Pass packet to bpf if there is a listener. 1095 */ 1096 if (ifp->if_bpf) 1097 bpf_mtap(ifp, mb_head); 1098 } 1099 1100 /* 1101 * We're finished. If we added to the list, issue a RESUME to get DMA 1102 * going again if suspended. 1103 */ 1104 if (txp != NULL) { 1105 fxp_scb_wait(sc); 1106 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_RESUME); 1107 } 1108 } 1109 1110 /* 1111 * Process interface interrupts. 1112 */ 1113 static void 1114 fxp_intr(void *xsc) 1115 { 1116 struct fxp_softc *sc = xsc; 1117 struct ifnet *ifp = &sc->sc_if; 1118 u_int8_t statack; 1119 1120 if (sc->suspended) { 1121 return; 1122 } 1123 1124 while ((statack = CSR_READ_1(sc, FXP_CSR_SCB_STATACK)) != 0) { 1125 /* 1126 * It should not be possible to have all bits set; the 1127 * FXP_SCB_INTR_SWI bit always returns 0 on a read. If 1128 * all bits are set, this may indicate that the card has 1129 * been physically ejected, so ignore it. 1130 */ 1131 if (statack == 0xff) 1132 return; 1133 1134 /* 1135 * First ACK all the interrupts in this pass. 1136 */ 1137 CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, statack); 1138 1139 /* 1140 * Free any finished transmit mbuf chains. 1141 * 1142 * Handle the CNA event likt a CXTNO event. It used to 1143 * be that this event (control unit not ready) was not 1144 * encountered, but it is now with the SMPng modifications. 1145 * The exact sequence of events that occur when the interface 1146 * is brought up are different now, and if this event 1147 * goes unhandled, the configuration/rxfilter setup sequence 1148 * can stall for several seconds. The result is that no 1149 * packets go out onto the wire for about 5 to 10 seconds 1150 * after the interface is ifconfig'ed for the first time. 1151 */ 1152 if (statack & (FXP_SCB_STATACK_CXTNO | FXP_SCB_STATACK_CNA)) { 1153 struct fxp_cb_tx *txp; 1154 1155 for (txp = sc->cbl_first; sc->tx_queued && 1156 (txp->cb_status & FXP_CB_STATUS_C) != 0; 1157 txp = txp->next) { 1158 if (txp->mb_head != NULL) { 1159 m_freem(txp->mb_head); 1160 txp->mb_head = NULL; 1161 } 1162 sc->tx_queued--; 1163 } 1164 sc->cbl_first = txp; 1165 ifp->if_timer = 0; 1166 if (sc->tx_queued == 0) { 1167 if (sc->need_mcsetup) 1168 fxp_mc_setup(sc); 1169 } 1170 /* 1171 * Try to start more packets transmitting. 1172 */ 1173 if (ifp->if_snd.ifq_head != NULL) 1174 fxp_start(ifp); 1175 } 1176 /* 1177 * Process receiver interrupts. If a no-resource (RNR) 1178 * condition exists, get whatever packets we can and 1179 * re-start the receiver. 1180 */ 1181 if (statack & (FXP_SCB_STATACK_FR | FXP_SCB_STATACK_RNR)) { 1182 struct mbuf *m; 1183 struct fxp_rfa *rfa; 1184 rcvloop: 1185 m = sc->rfa_headm; 1186 rfa = (struct fxp_rfa *)(m->m_ext.ext_buf + 1187 RFA_ALIGNMENT_FUDGE); 1188 1189 if (rfa->rfa_status & FXP_RFA_STATUS_C) { 1190 /* 1191 * Remove first packet from the chain. 1192 */ 1193 sc->rfa_headm = m->m_next; 1194 m->m_next = NULL; 1195 1196 /* 1197 * Add a new buffer to the receive chain. 1198 * If this fails, the old buffer is recycled 1199 * instead. 1200 */ 1201 if (fxp_add_rfabuf(sc, m) == 0) { 1202 struct ether_header *eh; 1203 int total_len; 1204 1205 total_len = rfa->actual_size & 1206 (MCLBYTES - 1); 1207 if (total_len < 1208 sizeof(struct ether_header)) { 1209 m_freem(m); 1210 goto rcvloop; 1211 } 1212 1213 /* 1214 * Drop the packet if it has CRC 1215 * errors. This test is only needed 1216 * when doing 802.1q VLAN on the 82557 1217 * chip. 1218 */ 1219 if (rfa->rfa_status & 1220 FXP_RFA_STATUS_CRC) { 1221 m_freem(m); 1222 goto rcvloop; 1223 } 1224 1225 m->m_pkthdr.rcvif = ifp; 1226 m->m_pkthdr.len = m->m_len = total_len; 1227 eh = mtod(m, struct ether_header *); 1228 m->m_data += 1229 sizeof(struct ether_header); 1230 m->m_len -= 1231 sizeof(struct ether_header); 1232 m->m_pkthdr.len = m->m_len; 1233 ether_input(ifp, eh, m); 1234 } 1235 goto rcvloop; 1236 } 1237 if (statack & FXP_SCB_STATACK_RNR) { 1238 fxp_scb_wait(sc); 1239 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 1240 vtophys(sc->rfa_headm->m_ext.ext_buf) + 1241 RFA_ALIGNMENT_FUDGE); 1242 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_START); 1243 } 1244 } 1245 } 1246 } 1247 1248 /* 1249 * Update packet in/out/collision statistics. The i82557 doesn't 1250 * allow you to access these counters without doing a fairly 1251 * expensive DMA to get _all_ of the statistics it maintains, so 1252 * we do this operation here only once per second. The statistics 1253 * counters in the kernel are updated from the previous dump-stats 1254 * DMA and then a new dump-stats DMA is started. The on-chip 1255 * counters are zeroed when the DMA completes. If we can't start 1256 * the DMA immediately, we don't wait - we just prepare to read 1257 * them again next time. 1258 */ 1259 static void 1260 fxp_tick(void *xsc) 1261 { 1262 struct fxp_softc *sc = xsc; 1263 struct ifnet *ifp = &sc->sc_if; 1264 struct fxp_stats *sp = sc->fxp_stats; 1265 struct fxp_cb_tx *txp; 1266 int s; 1267 1268 ifp->if_opackets += sp->tx_good; 1269 ifp->if_collisions += sp->tx_total_collisions; 1270 if (sp->rx_good) { 1271 ifp->if_ipackets += sp->rx_good; 1272 sc->rx_idle_secs = 0; 1273 } else { 1274 /* 1275 * Receiver's been idle for another second. 1276 */ 1277 sc->rx_idle_secs++; 1278 } 1279 ifp->if_ierrors += 1280 sp->rx_crc_errors + 1281 sp->rx_alignment_errors + 1282 sp->rx_rnr_errors + 1283 sp->rx_overrun_errors; 1284 /* 1285 * If any transmit underruns occured, bump up the transmit 1286 * threshold by another 512 bytes (64 * 8). 1287 */ 1288 if (sp->tx_underruns) { 1289 ifp->if_oerrors += sp->tx_underruns; 1290 if (tx_threshold < 192) 1291 tx_threshold += 64; 1292 } 1293 s = splimp(); 1294 /* 1295 * Release any xmit buffers that have completed DMA. This isn't 1296 * strictly necessary to do here, but it's advantagous for mbufs 1297 * with external storage to be released in a timely manner rather 1298 * than being defered for a potentially long time. This limits 1299 * the delay to a maximum of one second. 1300 */ 1301 for (txp = sc->cbl_first; sc->tx_queued && 1302 (txp->cb_status & FXP_CB_STATUS_C) != 0; 1303 txp = txp->next) { 1304 if (txp->mb_head != NULL) { 1305 m_freem(txp->mb_head); 1306 txp->mb_head = NULL; 1307 } 1308 sc->tx_queued--; 1309 } 1310 sc->cbl_first = txp; 1311 /* 1312 * If we haven't received any packets in FXP_MAC_RX_IDLE seconds, 1313 * then assume the receiver has locked up and attempt to clear 1314 * the condition by reprogramming the multicast filter. This is 1315 * a work-around for a bug in the 82557 where the receiver locks 1316 * up if it gets certain types of garbage in the syncronization 1317 * bits prior to the packet header. This bug is supposed to only 1318 * occur in 10Mbps mode, but has been seen to occur in 100Mbps 1319 * mode as well (perhaps due to a 10/100 speed transition). 1320 */ 1321 if (sc->rx_idle_secs > FXP_MAX_RX_IDLE) { 1322 sc->rx_idle_secs = 0; 1323 fxp_mc_setup(sc); 1324 } 1325 /* 1326 * If there is no pending command, start another stats 1327 * dump. Otherwise punt for now. 1328 */ 1329 if (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) == 0) { 1330 /* 1331 * Start another stats dump. 1332 */ 1333 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_DUMPRESET); 1334 } else { 1335 /* 1336 * A previous command is still waiting to be accepted. 1337 * Just zero our copy of the stats and wait for the 1338 * next timer event to update them. 1339 */ 1340 sp->tx_good = 0; 1341 sp->tx_underruns = 0; 1342 sp->tx_total_collisions = 0; 1343 1344 sp->rx_good = 0; 1345 sp->rx_crc_errors = 0; 1346 sp->rx_alignment_errors = 0; 1347 sp->rx_rnr_errors = 0; 1348 sp->rx_overrun_errors = 0; 1349 } 1350 if (sc->miibus != NULL) 1351 mii_tick(device_get_softc(sc->miibus)); 1352 splx(s); 1353 /* 1354 * Schedule another timeout one second from now. 1355 */ 1356 sc->stat_ch = timeout(fxp_tick, sc, hz); 1357 } 1358 1359 /* 1360 * Stop the interface. Cancels the statistics updater and resets 1361 * the interface. 1362 */ 1363 static void 1364 fxp_stop(struct fxp_softc *sc) 1365 { 1366 struct ifnet *ifp = &sc->sc_if; 1367 struct fxp_cb_tx *txp; 1368 int i; 1369 1370 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1371 ifp->if_timer = 0; 1372 1373 /* 1374 * Cancel stats updater. 1375 */ 1376 untimeout(fxp_tick, sc, sc->stat_ch); 1377 1378 /* 1379 * Issue software reset 1380 */ 1381 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET); 1382 DELAY(10); 1383 1384 /* 1385 * Release any xmit buffers. 1386 */ 1387 txp = sc->cbl_base; 1388 if (txp != NULL) { 1389 for (i = 0; i < FXP_NTXCB; i++) { 1390 if (txp[i].mb_head != NULL) { 1391 m_freem(txp[i].mb_head); 1392 txp[i].mb_head = NULL; 1393 } 1394 } 1395 } 1396 sc->tx_queued = 0; 1397 1398 /* 1399 * Free all the receive buffers then reallocate/reinitialize 1400 */ 1401 if (sc->rfa_headm != NULL) 1402 m_freem(sc->rfa_headm); 1403 sc->rfa_headm = NULL; 1404 sc->rfa_tailm = NULL; 1405 for (i = 0; i < FXP_NRFABUFS; i++) { 1406 if (fxp_add_rfabuf(sc, NULL) != 0) { 1407 /* 1408 * This "can't happen" - we're at splimp() 1409 * and we just freed all the buffers we need 1410 * above. 1411 */ 1412 panic("fxp_stop: no buffers!"); 1413 } 1414 } 1415 } 1416 1417 /* 1418 * Watchdog/transmission transmit timeout handler. Called when a 1419 * transmission is started on the interface, but no interrupt is 1420 * received before the timeout. This usually indicates that the 1421 * card has wedged for some reason. 1422 */ 1423 static void 1424 fxp_watchdog(struct ifnet *ifp) 1425 { 1426 struct fxp_softc *sc = ifp->if_softc; 1427 1428 device_printf(sc->dev, "device timeout\n"); 1429 ifp->if_oerrors++; 1430 1431 fxp_init(sc); 1432 } 1433 1434 static void 1435 fxp_init(void *xsc) 1436 { 1437 struct fxp_softc *sc = xsc; 1438 struct ifnet *ifp = &sc->sc_if; 1439 struct fxp_cb_config *cbp; 1440 struct fxp_cb_ias *cb_ias; 1441 struct fxp_cb_tx *txp; 1442 int i, prm, s; 1443 1444 s = splimp(); 1445 /* 1446 * Cancel any pending I/O 1447 */ 1448 fxp_stop(sc); 1449 1450 prm = (ifp->if_flags & IFF_PROMISC) ? 1 : 0; 1451 1452 /* 1453 * Initialize base of CBL and RFA memory. Loading with zero 1454 * sets it up for regular linear addressing. 1455 */ 1456 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 0); 1457 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_BASE); 1458 1459 fxp_scb_wait(sc); 1460 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_BASE); 1461 1462 /* 1463 * Initialize base of dump-stats buffer. 1464 */ 1465 fxp_scb_wait(sc); 1466 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, vtophys(sc->fxp_stats)); 1467 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_DUMP_ADR); 1468 1469 /* 1470 * We temporarily use memory that contains the TxCB list to 1471 * construct the config CB. The TxCB list memory is rebuilt 1472 * later. 1473 */ 1474 cbp = (struct fxp_cb_config *) sc->cbl_base; 1475 1476 /* 1477 * This bcopy is kind of disgusting, but there are a bunch of must be 1478 * zero and must be one bits in this structure and this is the easiest 1479 * way to initialize them all to proper values. 1480 */ 1481 bcopy(fxp_cb_config_template, 1482 (void *)(uintptr_t)(volatile void *)&cbp->cb_status, 1483 sizeof(fxp_cb_config_template)); 1484 1485 cbp->cb_status = 0; 1486 cbp->cb_command = FXP_CB_COMMAND_CONFIG | FXP_CB_COMMAND_EL; 1487 cbp->link_addr = -1; /* (no) next command */ 1488 cbp->byte_count = 22; /* (22) bytes to config */ 1489 cbp->rx_fifo_limit = 8; /* rx fifo threshold (32 bytes) */ 1490 cbp->tx_fifo_limit = 0; /* tx fifo threshold (0 bytes) */ 1491 cbp->adaptive_ifs = 0; /* (no) adaptive interframe spacing */ 1492 cbp->mwi_enable = sc->flags & FXP_FLAG_MWI_ENABLE ? 1 : 0; 1493 cbp->type_enable = 0; /* actually reserved */ 1494 cbp->read_align_en = sc->flags & FXP_FLAG_READ_ALIGN ? 1 : 0; 1495 cbp->end_wr_on_cl = sc->flags & FXP_FLAG_WRITE_ALIGN ? 1 : 0; 1496 cbp->rx_dma_bytecount = 0; /* (no) rx DMA max */ 1497 cbp->tx_dma_bytecount = 0; /* (no) tx DMA max */ 1498 cbp->dma_mbce = 0; /* (disable) dma max counters */ 1499 cbp->late_scb = 0; /* (don't) defer SCB update */ 1500 cbp->direct_dma_dis = 1; /* disable direct rcv dma mode */ 1501 cbp->tno_int_or_tco_en =0; /* (disable) tx not okay interrupt */ 1502 cbp->ci_int = 1; /* interrupt on CU idle */ 1503 cbp->ext_txcb_dis = sc->flags & FXP_FLAG_EXT_TXCB ? 0 : 1; 1504 cbp->ext_stats_dis = 1; /* disable extended counters */ 1505 cbp->keep_overrun_rx = 0; /* don't pass overrun frames to host */ 1506 cbp->save_bf = sc->chip == FXP_CHIP_82557 ? 1 : prm; 1507 cbp->disc_short_rx = !prm; /* discard short packets */ 1508 cbp->underrun_retry = 1; /* retry mode (once) on DMA underrun */ 1509 cbp->two_frames = 0; /* do not limit FIFO to 2 frames */ 1510 cbp->dyn_tbd = 0; /* (no) dynamic TBD mode */ 1511 cbp->mediatype = sc->flags & FXP_FLAG_SERIAL_MEDIA ? 0 : 1; 1512 cbp->csma_dis = 0; /* (don't) disable link */ 1513 cbp->tcp_udp_cksum = 0; /* (don't) enable checksum */ 1514 cbp->vlan_tco = 0; /* (don't) enable vlan wakeup */ 1515 cbp->link_wake_en = 0; /* (don't) assert PME# on link change */ 1516 cbp->arp_wake_en = 0; /* (don't) assert PME# on arp */ 1517 cbp->mc_wake_en = 0; /* (don't) enable PME# on mcmatch */ 1518 cbp->nsai = 1; /* (don't) disable source addr insert */ 1519 cbp->preamble_length = 2; /* (7 byte) preamble */ 1520 cbp->loopback = 0; /* (don't) loopback */ 1521 cbp->linear_priority = 0; /* (normal CSMA/CD operation) */ 1522 cbp->linear_pri_mode = 0; /* (wait after xmit only) */ 1523 cbp->interfrm_spacing = 6; /* (96 bits of) interframe spacing */ 1524 cbp->promiscuous = prm; /* promiscuous mode */ 1525 cbp->bcast_disable = 0; /* (don't) disable broadcasts */ 1526 cbp->wait_after_win = 0; /* (don't) enable modified backoff alg*/ 1527 cbp->ignore_ul = 0; /* consider U/L bit in IA matching */ 1528 cbp->crc16_en = 0; /* (don't) enable crc-16 algorithm */ 1529 cbp->crscdt = sc->flags & FXP_FLAG_SERIAL_MEDIA ? 1 : 0; 1530 1531 cbp->stripping = !prm; /* truncate rx packet to byte count */ 1532 cbp->padding = 1; /* (do) pad short tx packets */ 1533 cbp->rcv_crc_xfer = 0; /* (don't) xfer CRC to host */ 1534 cbp->long_rx_en = sc->flags & FXP_FLAG_LONG_PKT_EN ? 1 : 0; 1535 cbp->ia_wake_en = 0; /* (don't) wake up on address match */ 1536 cbp->magic_pkt_dis = 0; /* (don't) disable magic packet */ 1537 /* must set wake_en in PMCSR also */ 1538 cbp->force_fdx = 0; /* (don't) force full duplex */ 1539 cbp->fdx_pin_en = 1; /* (enable) FDX# pin */ 1540 cbp->multi_ia = 0; /* (don't) accept multiple IAs */ 1541 cbp->mc_all = sc->flags & FXP_FLAG_ALL_MCAST ? 1 : 0; 1542 1543 if (sc->chip == FXP_CHIP_82557) { 1544 /* 1545 * The 82557 has no hardware flow control, the values 1546 * below are the defaults for the chip. 1547 */ 1548 cbp->fc_delay_lsb = 0; 1549 cbp->fc_delay_msb = 0x40; 1550 cbp->pri_fc_thresh = 3; 1551 cbp->tx_fc_dis = 0; 1552 cbp->rx_fc_restop = 0; 1553 cbp->rx_fc_restart = 0; 1554 cbp->fc_filter = 0; 1555 cbp->pri_fc_loc = 1; 1556 } else { 1557 cbp->fc_delay_lsb = 0x1f; 1558 cbp->fc_delay_msb = 0x01; 1559 cbp->pri_fc_thresh = 3; 1560 cbp->tx_fc_dis = 0; /* enable transmit FC */ 1561 cbp->rx_fc_restop = 1; /* enable FC restop frames */ 1562 cbp->rx_fc_restart = 1; /* enable FC restart frames */ 1563 cbp->fc_filter = !prm; /* drop FC frames to host */ 1564 cbp->pri_fc_loc = 1; /* FC pri location (byte31) */ 1565 } 1566 1567 /* 1568 * Start the config command/DMA. 1569 */ 1570 fxp_scb_wait(sc); 1571 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, vtophys(&cbp->cb_status)); 1572 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 1573 /* ...and wait for it to complete. */ 1574 fxp_dma_wait(&cbp->cb_status, sc); 1575 1576 /* 1577 * Now initialize the station address. Temporarily use the TxCB 1578 * memory area like we did above for the config CB. 1579 */ 1580 cb_ias = (struct fxp_cb_ias *) sc->cbl_base; 1581 cb_ias->cb_status = 0; 1582 cb_ias->cb_command = FXP_CB_COMMAND_IAS | FXP_CB_COMMAND_EL; 1583 cb_ias->link_addr = -1; 1584 bcopy(sc->arpcom.ac_enaddr, 1585 (void *)(uintptr_t)(volatile void *)cb_ias->macaddr, 1586 sizeof(sc->arpcom.ac_enaddr)); 1587 1588 /* 1589 * Start the IAS (Individual Address Setup) command/DMA. 1590 */ 1591 fxp_scb_wait(sc); 1592 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 1593 /* ...and wait for it to complete. */ 1594 fxp_dma_wait(&cb_ias->cb_status, sc); 1595 1596 /* 1597 * Initialize transmit control block (TxCB) list. 1598 */ 1599 1600 txp = sc->cbl_base; 1601 bzero(txp, sizeof(struct fxp_cb_tx) * FXP_NTXCB); 1602 for (i = 0; i < FXP_NTXCB; i++) { 1603 txp[i].cb_status = FXP_CB_STATUS_C | FXP_CB_STATUS_OK; 1604 txp[i].cb_command = FXP_CB_COMMAND_NOP; 1605 txp[i].link_addr = 1606 vtophys(&txp[(i + 1) & FXP_TXCB_MASK].cb_status); 1607 if (sc->flags & FXP_FLAG_EXT_TXCB) 1608 txp[i].tbd_array_addr = vtophys(&txp[i].tbd[2]); 1609 else 1610 txp[i].tbd_array_addr = vtophys(&txp[i].tbd[0]); 1611 txp[i].next = &txp[(i + 1) & FXP_TXCB_MASK]; 1612 } 1613 /* 1614 * Set the suspend flag on the first TxCB and start the control 1615 * unit. It will execute the NOP and then suspend. 1616 */ 1617 txp->cb_command = FXP_CB_COMMAND_NOP | FXP_CB_COMMAND_S; 1618 sc->cbl_first = sc->cbl_last = txp; 1619 sc->tx_queued = 1; 1620 1621 fxp_scb_wait(sc); 1622 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 1623 1624 /* 1625 * Initialize receiver buffer area - RFA. 1626 */ 1627 fxp_scb_wait(sc); 1628 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 1629 vtophys(sc->rfa_headm->m_ext.ext_buf) + RFA_ALIGNMENT_FUDGE); 1630 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_START); 1631 1632 /* 1633 * Set current media. 1634 */ 1635 if (sc->miibus != NULL) 1636 mii_mediachg(device_get_softc(sc->miibus)); 1637 1638 ifp->if_flags |= IFF_RUNNING; 1639 ifp->if_flags &= ~IFF_OACTIVE; 1640 1641 /* 1642 * Enable interrupts. 1643 */ 1644 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, 0); 1645 splx(s); 1646 1647 /* 1648 * Start stats updater. 1649 */ 1650 sc->stat_ch = timeout(fxp_tick, sc, hz); 1651 } 1652 1653 static int 1654 fxp_serial_ifmedia_upd(struct ifnet *ifp) 1655 { 1656 1657 return (0); 1658 } 1659 1660 static void 1661 fxp_serial_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 1662 { 1663 1664 ifmr->ifm_active = IFM_ETHER|IFM_MANUAL; 1665 } 1666 1667 /* 1668 * Change media according to request. 1669 */ 1670 static int 1671 fxp_ifmedia_upd(struct ifnet *ifp) 1672 { 1673 struct fxp_softc *sc = ifp->if_softc; 1674 struct mii_data *mii; 1675 1676 mii = device_get_softc(sc->miibus); 1677 mii_mediachg(mii); 1678 return (0); 1679 } 1680 1681 /* 1682 * Notify the world which media we're using. 1683 */ 1684 static void 1685 fxp_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 1686 { 1687 struct fxp_softc *sc = ifp->if_softc; 1688 struct mii_data *mii; 1689 1690 mii = device_get_softc(sc->miibus); 1691 mii_pollstat(mii); 1692 ifmr->ifm_active = mii->mii_media_active; 1693 ifmr->ifm_status = mii->mii_media_status; 1694 1695 if (ifmr->ifm_status & IFM_10_T && sc->flags & FXP_FLAG_CU_RESUME_BUG) 1696 sc->cu_resume_bug = 1; 1697 else 1698 sc->cu_resume_bug = 0; 1699 } 1700 1701 /* 1702 * Add a buffer to the end of the RFA buffer list. 1703 * Return 0 if successful, 1 for failure. A failure results in 1704 * adding the 'oldm' (if non-NULL) on to the end of the list - 1705 * tossing out its old contents and recycling it. 1706 * The RFA struct is stuck at the beginning of mbuf cluster and the 1707 * data pointer is fixed up to point just past it. 1708 */ 1709 static int 1710 fxp_add_rfabuf(struct fxp_softc *sc, struct mbuf *oldm) 1711 { 1712 u_int32_t v; 1713 struct mbuf *m; 1714 struct fxp_rfa *rfa, *p_rfa; 1715 1716 MGETHDR(m, M_DONTWAIT, MT_DATA); 1717 if (m != NULL) { 1718 MCLGET(m, M_DONTWAIT); 1719 if ((m->m_flags & M_EXT) == 0) { 1720 m_freem(m); 1721 if (oldm == NULL) 1722 return 1; 1723 m = oldm; 1724 m->m_data = m->m_ext.ext_buf; 1725 } 1726 } else { 1727 if (oldm == NULL) 1728 return 1; 1729 m = oldm; 1730 m->m_data = m->m_ext.ext_buf; 1731 } 1732 1733 /* 1734 * Move the data pointer up so that the incoming data packet 1735 * will be 32-bit aligned. 1736 */ 1737 m->m_data += RFA_ALIGNMENT_FUDGE; 1738 1739 /* 1740 * Get a pointer to the base of the mbuf cluster and move 1741 * data start past it. 1742 */ 1743 rfa = mtod(m, struct fxp_rfa *); 1744 m->m_data += sizeof(struct fxp_rfa); 1745 rfa->size = (u_int16_t)(MCLBYTES - sizeof(struct fxp_rfa) - RFA_ALIGNMENT_FUDGE); 1746 1747 /* 1748 * Initialize the rest of the RFA. Note that since the RFA 1749 * is misaligned, we cannot store values directly. Instead, 1750 * we use an optimized, inline copy. 1751 */ 1752 1753 rfa->rfa_status = 0; 1754 rfa->rfa_control = FXP_RFA_CONTROL_EL; 1755 rfa->actual_size = 0; 1756 1757 v = -1; 1758 fxp_lwcopy(&v, (volatile u_int32_t *) rfa->link_addr); 1759 fxp_lwcopy(&v, (volatile u_int32_t *) rfa->rbd_addr); 1760 1761 /* 1762 * If there are other buffers already on the list, attach this 1763 * one to the end by fixing up the tail to point to this one. 1764 */ 1765 if (sc->rfa_headm != NULL) { 1766 p_rfa = (struct fxp_rfa *) (sc->rfa_tailm->m_ext.ext_buf + 1767 RFA_ALIGNMENT_FUDGE); 1768 sc->rfa_tailm->m_next = m; 1769 v = vtophys(rfa); 1770 fxp_lwcopy(&v, (volatile u_int32_t *) p_rfa->link_addr); 1771 p_rfa->rfa_control = 0; 1772 } else { 1773 sc->rfa_headm = m; 1774 } 1775 sc->rfa_tailm = m; 1776 1777 return (m == oldm); 1778 } 1779 1780 static volatile int 1781 fxp_miibus_readreg(device_t dev, int phy, int reg) 1782 { 1783 struct fxp_softc *sc = device_get_softc(dev); 1784 int count = 10000; 1785 int value; 1786 1787 CSR_WRITE_4(sc, FXP_CSR_MDICONTROL, 1788 (FXP_MDI_READ << 26) | (reg << 16) | (phy << 21)); 1789 1790 while (((value = CSR_READ_4(sc, FXP_CSR_MDICONTROL)) & 0x10000000) == 0 1791 && count--) 1792 DELAY(10); 1793 1794 if (count <= 0) 1795 device_printf(dev, "fxp_miibus_readreg: timed out\n"); 1796 1797 return (value & 0xffff); 1798 } 1799 1800 static void 1801 fxp_miibus_writereg(device_t dev, int phy, int reg, int value) 1802 { 1803 struct fxp_softc *sc = device_get_softc(dev); 1804 int count = 10000; 1805 1806 CSR_WRITE_4(sc, FXP_CSR_MDICONTROL, 1807 (FXP_MDI_WRITE << 26) | (reg << 16) | (phy << 21) | 1808 (value & 0xffff)); 1809 1810 while ((CSR_READ_4(sc, FXP_CSR_MDICONTROL) & 0x10000000) == 0 && 1811 count--) 1812 DELAY(10); 1813 1814 if (count <= 0) 1815 device_printf(dev, "fxp_miibus_writereg: timed out\n"); 1816 } 1817 1818 static int 1819 fxp_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 1820 { 1821 struct fxp_softc *sc = ifp->if_softc; 1822 struct ifreq *ifr = (struct ifreq *)data; 1823 struct mii_data *mii; 1824 int s, error = 0; 1825 1826 s = splimp(); 1827 1828 switch (command) { 1829 case SIOCSIFADDR: 1830 case SIOCGIFADDR: 1831 case SIOCSIFMTU: 1832 error = ether_ioctl(ifp, command, data); 1833 break; 1834 1835 case SIOCSIFFLAGS: 1836 if (ifp->if_flags & IFF_ALLMULTI) 1837 sc->flags |= FXP_FLAG_ALL_MCAST; 1838 else 1839 sc->flags &= ~FXP_FLAG_ALL_MCAST; 1840 1841 /* 1842 * If interface is marked up and not running, then start it. 1843 * If it is marked down and running, stop it. 1844 * XXX If it's up then re-initialize it. This is so flags 1845 * such as IFF_PROMISC are handled. 1846 */ 1847 if (ifp->if_flags & IFF_UP) { 1848 fxp_init(sc); 1849 } else { 1850 if (ifp->if_flags & IFF_RUNNING) 1851 fxp_stop(sc); 1852 } 1853 break; 1854 1855 case SIOCADDMULTI: 1856 case SIOCDELMULTI: 1857 if (ifp->if_flags & IFF_ALLMULTI) 1858 sc->flags |= FXP_FLAG_ALL_MCAST; 1859 else 1860 sc->flags &= ~FXP_FLAG_ALL_MCAST; 1861 /* 1862 * Multicast list has changed; set the hardware filter 1863 * accordingly. 1864 */ 1865 if ((sc->flags & FXP_FLAG_ALL_MCAST) == 0) 1866 fxp_mc_setup(sc); 1867 /* 1868 * fxp_mc_setup() can set FXP_FLAG_ALL_MCAST, so check it 1869 * again rather than else {}. 1870 */ 1871 if (sc->flags & FXP_FLAG_ALL_MCAST) 1872 fxp_init(sc); 1873 error = 0; 1874 break; 1875 1876 case SIOCSIFMEDIA: 1877 case SIOCGIFMEDIA: 1878 if (sc->miibus != NULL) { 1879 mii = device_get_softc(sc->miibus); 1880 error = ifmedia_ioctl(ifp, ifr, 1881 &mii->mii_media, command); 1882 } else { 1883 error = ifmedia_ioctl(ifp, ifr, &sc->sc_media, command); 1884 } 1885 break; 1886 1887 default: 1888 error = EINVAL; 1889 } 1890 splx(s); 1891 return (error); 1892 } 1893 1894 /* 1895 * Program the multicast filter. 1896 * 1897 * We have an artificial restriction that the multicast setup command 1898 * must be the first command in the chain, so we take steps to ensure 1899 * this. By requiring this, it allows us to keep up the performance of 1900 * the pre-initialized command ring (esp. link pointers) by not actually 1901 * inserting the mcsetup command in the ring - i.e. its link pointer 1902 * points to the TxCB ring, but the mcsetup descriptor itself is not part 1903 * of it. We then can do 'CU_START' on the mcsetup descriptor and have it 1904 * lead into the regular TxCB ring when it completes. 1905 * 1906 * This function must be called at splimp. 1907 */ 1908 static void 1909 fxp_mc_setup(struct fxp_softc *sc) 1910 { 1911 struct fxp_cb_mcs *mcsp = sc->mcsp; 1912 struct ifnet *ifp = &sc->sc_if; 1913 struct ifmultiaddr *ifma; 1914 int nmcasts; 1915 int count; 1916 1917 /* 1918 * If there are queued commands, we must wait until they are all 1919 * completed. If we are already waiting, then add a NOP command 1920 * with interrupt option so that we're notified when all commands 1921 * have been completed - fxp_start() ensures that no additional 1922 * TX commands will be added when need_mcsetup is true. 1923 */ 1924 if (sc->tx_queued) { 1925 struct fxp_cb_tx *txp; 1926 1927 /* 1928 * need_mcsetup will be true if we are already waiting for the 1929 * NOP command to be completed (see below). In this case, bail. 1930 */ 1931 if (sc->need_mcsetup) 1932 return; 1933 sc->need_mcsetup = 1; 1934 1935 /* 1936 * Add a NOP command with interrupt so that we are notified when all 1937 * TX commands have been processed. 1938 */ 1939 txp = sc->cbl_last->next; 1940 txp->mb_head = NULL; 1941 txp->cb_status = 0; 1942 txp->cb_command = FXP_CB_COMMAND_NOP | 1943 FXP_CB_COMMAND_S | FXP_CB_COMMAND_I; 1944 /* 1945 * Advance the end of list forward. 1946 */ 1947 sc->cbl_last->cb_command &= ~FXP_CB_COMMAND_S; 1948 sc->cbl_last = txp; 1949 sc->tx_queued++; 1950 /* 1951 * Issue a resume in case the CU has just suspended. 1952 */ 1953 fxp_scb_wait(sc); 1954 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_RESUME); 1955 /* 1956 * Set a 5 second timer just in case we don't hear from the 1957 * card again. 1958 */ 1959 ifp->if_timer = 5; 1960 1961 return; 1962 } 1963 sc->need_mcsetup = 0; 1964 1965 /* 1966 * Initialize multicast setup descriptor. 1967 */ 1968 mcsp->next = sc->cbl_base; 1969 mcsp->mb_head = NULL; 1970 mcsp->cb_status = 0; 1971 mcsp->cb_command = FXP_CB_COMMAND_MCAS | 1972 FXP_CB_COMMAND_S | FXP_CB_COMMAND_I; 1973 mcsp->link_addr = vtophys(&sc->cbl_base->cb_status); 1974 1975 nmcasts = 0; 1976 if ((sc->flags & FXP_FLAG_ALL_MCAST) == 0) { 1977 #if __FreeBSD_version < 500000 1978 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1979 #else 1980 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1981 #endif 1982 if (ifma->ifma_addr->sa_family != AF_LINK) 1983 continue; 1984 if (nmcasts >= MAXMCADDR) { 1985 sc->flags |= FXP_FLAG_ALL_MCAST; 1986 nmcasts = 0; 1987 break; 1988 } 1989 bcopy(LLADDR((struct sockaddr_dl *)ifma->ifma_addr), 1990 (void *)(uintptr_t)(volatile void *) 1991 &sc->mcsp->mc_addr[nmcasts][0], 6); 1992 nmcasts++; 1993 } 1994 } 1995 mcsp->mc_cnt = nmcasts * 6; 1996 sc->cbl_first = sc->cbl_last = (struct fxp_cb_tx *) mcsp; 1997 sc->tx_queued = 1; 1998 1999 /* 2000 * Wait until command unit is not active. This should never 2001 * be the case when nothing is queued, but make sure anyway. 2002 */ 2003 count = 100; 2004 while ((CSR_READ_1(sc, FXP_CSR_SCB_RUSCUS) >> 6) == 2005 FXP_SCB_CUS_ACTIVE && --count) 2006 DELAY(10); 2007 if (count == 0) { 2008 device_printf(sc->dev, "command queue timeout\n"); 2009 return; 2010 } 2011 2012 /* 2013 * Start the multicast setup command. 2014 */ 2015 fxp_scb_wait(sc); 2016 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, vtophys(&mcsp->cb_status)); 2017 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2018 2019 ifp->if_timer = 2; 2020 return; 2021 } 2022