1 /*- 2 * Copyright (c) 1995, David Greenman 3 * Copyright (c) 2001 Jonathan Lemon <jlemon@freebsd.org> 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice unmodified, this list of conditions, and the following 11 * disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 * 28 */ 29 30 #include <sys/cdefs.h> 31 __FBSDID("$FreeBSD$"); 32 33 /* 34 * Intel EtherExpress Pro/100B PCI Fast Ethernet driver 35 */ 36 37 #ifdef HAVE_KERNEL_OPTION_HEADERS 38 #include "opt_device_polling.h" 39 #endif 40 41 #include <sys/param.h> 42 #include <sys/systm.h> 43 #include <sys/endian.h> 44 #include <sys/mbuf.h> 45 /* #include <sys/mutex.h> */ 46 #include <sys/kernel.h> 47 #include <sys/module.h> 48 #include <sys/socket.h> 49 #include <sys/sysctl.h> 50 51 #include <net/if.h> 52 #include <net/if_dl.h> 53 #include <net/if_media.h> 54 55 #include <net/bpf.h> 56 #include <sys/sockio.h> 57 #include <sys/bus.h> 58 #include <machine/bus.h> 59 #include <sys/rman.h> 60 #include <machine/resource.h> 61 62 #include <net/ethernet.h> 63 #include <net/if_arp.h> 64 65 66 #include <net/if_types.h> 67 #include <net/if_vlan_var.h> 68 69 #ifdef FXP_IP_CSUM_WAR 70 #include <netinet/in.h> 71 #include <netinet/in_systm.h> 72 #include <netinet/ip.h> 73 #include <machine/in_cksum.h> 74 #endif 75 76 #include <dev/pci/pcivar.h> 77 #include <dev/pci/pcireg.h> /* for PCIM_CMD_xxx */ 78 79 #include <dev/mii/mii.h> 80 #include <dev/mii/miivar.h> 81 82 #include <dev/fxp/if_fxpreg.h> 83 #include <dev/fxp/if_fxpvar.h> 84 #include <dev/fxp/rcvbundl.h> 85 86 MODULE_DEPEND(fxp, pci, 1, 1, 1); 87 MODULE_DEPEND(fxp, ether, 1, 1, 1); 88 MODULE_DEPEND(fxp, miibus, 1, 1, 1); 89 #include "miibus_if.h" 90 91 /* 92 * NOTE! On the Alpha, we have an alignment constraint. The 93 * card DMAs the packet immediately following the RFA. However, 94 * the first thing in the packet is a 14-byte Ethernet header. 95 * This means that the packet is misaligned. To compensate, 96 * we actually offset the RFA 2 bytes into the cluster. This 97 * alignes the packet after the Ethernet header at a 32-bit 98 * boundary. HOWEVER! This means that the RFA is misaligned! 99 */ 100 #define RFA_ALIGNMENT_FUDGE 2 101 102 /* 103 * Set initial transmit threshold at 64 (512 bytes). This is 104 * increased by 64 (512 bytes) at a time, to maximum of 192 105 * (1536 bytes), if an underrun occurs. 106 */ 107 static int tx_threshold = 64; 108 109 /* 110 * The configuration byte map has several undefined fields which 111 * must be one or must be zero. Set up a template for these bits 112 * only, (assuming a 82557 chip) leaving the actual configuration 113 * to fxp_init. 114 * 115 * See struct fxp_cb_config for the bit definitions. 116 */ 117 static u_char fxp_cb_config_template[] = { 118 0x0, 0x0, /* cb_status */ 119 0x0, 0x0, /* cb_command */ 120 0x0, 0x0, 0x0, 0x0, /* link_addr */ 121 0x0, /* 0 */ 122 0x0, /* 1 */ 123 0x0, /* 2 */ 124 0x0, /* 3 */ 125 0x0, /* 4 */ 126 0x0, /* 5 */ 127 0x32, /* 6 */ 128 0x0, /* 7 */ 129 0x0, /* 8 */ 130 0x0, /* 9 */ 131 0x6, /* 10 */ 132 0x0, /* 11 */ 133 0x0, /* 12 */ 134 0x0, /* 13 */ 135 0xf2, /* 14 */ 136 0x48, /* 15 */ 137 0x0, /* 16 */ 138 0x40, /* 17 */ 139 0xf0, /* 18 */ 140 0x0, /* 19 */ 141 0x3f, /* 20 */ 142 0x5 /* 21 */ 143 }; 144 145 struct fxp_ident { 146 uint16_t devid; 147 int16_t revid; /* -1 matches anything */ 148 char *name; 149 }; 150 151 /* 152 * Claim various Intel PCI device identifiers for this driver. The 153 * sub-vendor and sub-device field are extensively used to identify 154 * particular variants, but we don't currently differentiate between 155 * them. 156 */ 157 static struct fxp_ident fxp_ident_table[] = { 158 { 0x1029, -1, "Intel 82559 PCI/CardBus Pro/100" }, 159 { 0x1030, -1, "Intel 82559 Pro/100 Ethernet" }, 160 { 0x1031, -1, "Intel 82801CAM (ICH3) Pro/100 VE Ethernet" }, 161 { 0x1032, -1, "Intel 82801CAM (ICH3) Pro/100 VE Ethernet" }, 162 { 0x1033, -1, "Intel 82801CAM (ICH3) Pro/100 VM Ethernet" }, 163 { 0x1034, -1, "Intel 82801CAM (ICH3) Pro/100 VM Ethernet" }, 164 { 0x1035, -1, "Intel 82801CAM (ICH3) Pro/100 Ethernet" }, 165 { 0x1036, -1, "Intel 82801CAM (ICH3) Pro/100 Ethernet" }, 166 { 0x1037, -1, "Intel 82801CAM (ICH3) Pro/100 Ethernet" }, 167 { 0x1038, -1, "Intel 82801CAM (ICH3) Pro/100 VM Ethernet" }, 168 { 0x1039, -1, "Intel 82801DB (ICH4) Pro/100 VE Ethernet" }, 169 { 0x103A, -1, "Intel 82801DB (ICH4) Pro/100 Ethernet" }, 170 { 0x103B, -1, "Intel 82801DB (ICH4) Pro/100 VM Ethernet" }, 171 { 0x103C, -1, "Intel 82801DB (ICH4) Pro/100 Ethernet" }, 172 { 0x103D, -1, "Intel 82801DB (ICH4) Pro/100 VE Ethernet" }, 173 { 0x103E, -1, "Intel 82801DB (ICH4) Pro/100 VM Ethernet" }, 174 { 0x1050, -1, "Intel 82801BA (D865) Pro/100 VE Ethernet" }, 175 { 0x1051, -1, "Intel 82562ET (ICH5/ICH5R) Pro/100 VE Ethernet" }, 176 { 0x1059, -1, "Intel 82551QM Pro/100 M Mobile Connection" }, 177 { 0x1064, -1, "Intel 82562EZ (ICH6)" }, 178 { 0x1065, -1, "Intel 82562ET/EZ/GT/GZ PRO/100 VE Ethernet" }, 179 { 0x1068, -1, "Intel 82801FBM (ICH6-M) Pro/100 VE Ethernet" }, 180 { 0x1069, -1, "Intel 82562EM/EX/GX Pro/100 Ethernet" }, 181 { 0x1092, -1, "Intel Pro/100 VE Network Connection" }, 182 { 0x1093, -1, "Intel Pro/100 VM Network Connection" }, 183 { 0x1094, -1, "Intel Pro/100 946GZ (ICH7) Network Connection" }, 184 { 0x1209, -1, "Intel 82559ER Embedded 10/100 Ethernet" }, 185 { 0x1229, 0x01, "Intel 82557 Pro/100 Ethernet" }, 186 { 0x1229, 0x02, "Intel 82557 Pro/100 Ethernet" }, 187 { 0x1229, 0x03, "Intel 82557 Pro/100 Ethernet" }, 188 { 0x1229, 0x04, "Intel 82558 Pro/100 Ethernet" }, 189 { 0x1229, 0x05, "Intel 82558 Pro/100 Ethernet" }, 190 { 0x1229, 0x06, "Intel 82559 Pro/100 Ethernet" }, 191 { 0x1229, 0x07, "Intel 82559 Pro/100 Ethernet" }, 192 { 0x1229, 0x08, "Intel 82559 Pro/100 Ethernet" }, 193 { 0x1229, 0x09, "Intel 82559ER Pro/100 Ethernet" }, 194 { 0x1229, 0x0c, "Intel 82550 Pro/100 Ethernet" }, 195 { 0x1229, 0x0d, "Intel 82550 Pro/100 Ethernet" }, 196 { 0x1229, 0x0e, "Intel 82550 Pro/100 Ethernet" }, 197 { 0x1229, 0x0f, "Intel 82551 Pro/100 Ethernet" }, 198 { 0x1229, 0x10, "Intel 82551 Pro/100 Ethernet" }, 199 { 0x1229, -1, "Intel 82557/8/9 Pro/100 Ethernet" }, 200 { 0x2449, -1, "Intel 82801BA/CAM (ICH2/3) Pro/100 Ethernet" }, 201 { 0x27dc, -1, "Intel 82801GB (ICH7) 10/100 Ethernet" }, 202 { 0, -1, NULL }, 203 }; 204 205 #ifdef FXP_IP_CSUM_WAR 206 #define FXP_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 207 #else 208 #define FXP_CSUM_FEATURES (CSUM_TCP | CSUM_UDP) 209 #endif 210 211 static int fxp_probe(device_t dev); 212 static int fxp_attach(device_t dev); 213 static int fxp_detach(device_t dev); 214 static int fxp_shutdown(device_t dev); 215 static int fxp_suspend(device_t dev); 216 static int fxp_resume(device_t dev); 217 218 static void fxp_intr(void *xsc); 219 static void fxp_intr_body(struct fxp_softc *sc, struct ifnet *ifp, 220 uint8_t statack, int count); 221 static void fxp_init(void *xsc); 222 static void fxp_init_body(struct fxp_softc *sc); 223 static void fxp_tick(void *xsc); 224 static void fxp_start(struct ifnet *ifp); 225 static void fxp_start_body(struct ifnet *ifp); 226 static int fxp_encap(struct fxp_softc *sc, struct mbuf *m_head); 227 static void fxp_stop(struct fxp_softc *sc); 228 static void fxp_release(struct fxp_softc *sc); 229 static int fxp_ioctl(struct ifnet *ifp, u_long command, 230 caddr_t data); 231 static void fxp_watchdog(struct fxp_softc *sc); 232 static int fxp_add_rfabuf(struct fxp_softc *sc, 233 struct fxp_rx *rxp); 234 static int fxp_mc_addrs(struct fxp_softc *sc); 235 static void fxp_mc_setup(struct fxp_softc *sc); 236 static uint16_t fxp_eeprom_getword(struct fxp_softc *sc, int offset, 237 int autosize); 238 static void fxp_eeprom_putword(struct fxp_softc *sc, int offset, 239 uint16_t data); 240 static void fxp_autosize_eeprom(struct fxp_softc *sc); 241 static void fxp_read_eeprom(struct fxp_softc *sc, u_short *data, 242 int offset, int words); 243 static void fxp_write_eeprom(struct fxp_softc *sc, u_short *data, 244 int offset, int words); 245 static int fxp_ifmedia_upd(struct ifnet *ifp); 246 static void fxp_ifmedia_sts(struct ifnet *ifp, 247 struct ifmediareq *ifmr); 248 static int fxp_serial_ifmedia_upd(struct ifnet *ifp); 249 static void fxp_serial_ifmedia_sts(struct ifnet *ifp, 250 struct ifmediareq *ifmr); 251 static volatile int fxp_miibus_readreg(device_t dev, int phy, int reg); 252 static void fxp_miibus_writereg(device_t dev, int phy, int reg, 253 int value); 254 static void fxp_load_ucode(struct fxp_softc *sc); 255 static int sysctl_int_range(SYSCTL_HANDLER_ARGS, 256 int low, int high); 257 static int sysctl_hw_fxp_bundle_max(SYSCTL_HANDLER_ARGS); 258 static int sysctl_hw_fxp_int_delay(SYSCTL_HANDLER_ARGS); 259 static void fxp_scb_wait(struct fxp_softc *sc); 260 static void fxp_scb_cmd(struct fxp_softc *sc, int cmd); 261 static void fxp_dma_wait(struct fxp_softc *sc, 262 volatile uint16_t *status, bus_dma_tag_t dmat, 263 bus_dmamap_t map); 264 265 static device_method_t fxp_methods[] = { 266 /* Device interface */ 267 DEVMETHOD(device_probe, fxp_probe), 268 DEVMETHOD(device_attach, fxp_attach), 269 DEVMETHOD(device_detach, fxp_detach), 270 DEVMETHOD(device_shutdown, fxp_shutdown), 271 DEVMETHOD(device_suspend, fxp_suspend), 272 DEVMETHOD(device_resume, fxp_resume), 273 274 /* MII interface */ 275 DEVMETHOD(miibus_readreg, fxp_miibus_readreg), 276 DEVMETHOD(miibus_writereg, fxp_miibus_writereg), 277 278 { 0, 0 } 279 }; 280 281 static driver_t fxp_driver = { 282 "fxp", 283 fxp_methods, 284 sizeof(struct fxp_softc), 285 }; 286 287 static devclass_t fxp_devclass; 288 289 DRIVER_MODULE(fxp, pci, fxp_driver, fxp_devclass, 0, 0); 290 DRIVER_MODULE(fxp, cardbus, fxp_driver, fxp_devclass, 0, 0); 291 DRIVER_MODULE(miibus, fxp, miibus_driver, miibus_devclass, 0, 0); 292 293 static struct resource_spec fxp_res_spec_mem[] = { 294 { SYS_RES_MEMORY, FXP_PCI_MMBA, RF_ACTIVE }, 295 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE }, 296 { -1, 0 } 297 }; 298 299 static struct resource_spec fxp_res_spec_io[] = { 300 { SYS_RES_IOPORT, FXP_PCI_IOBA, RF_ACTIVE }, 301 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE }, 302 { -1, 0 } 303 }; 304 305 /* 306 * Wait for the previous command to be accepted (but not necessarily 307 * completed). 308 */ 309 static void 310 fxp_scb_wait(struct fxp_softc *sc) 311 { 312 union { 313 uint16_t w; 314 uint8_t b[2]; 315 } flowctl; 316 int i = 10000; 317 318 while (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) && --i) 319 DELAY(2); 320 if (i == 0) { 321 flowctl.b[0] = CSR_READ_1(sc, FXP_CSR_FLOWCONTROL); 322 flowctl.b[1] = CSR_READ_1(sc, FXP_CSR_FLOWCONTROL + 1); 323 device_printf(sc->dev, "SCB timeout: 0x%x 0x%x 0x%x 0x%x\n", 324 CSR_READ_1(sc, FXP_CSR_SCB_COMMAND), 325 CSR_READ_1(sc, FXP_CSR_SCB_STATACK), 326 CSR_READ_1(sc, FXP_CSR_SCB_RUSCUS), flowctl.w); 327 } 328 } 329 330 static void 331 fxp_scb_cmd(struct fxp_softc *sc, int cmd) 332 { 333 334 if (cmd == FXP_SCB_COMMAND_CU_RESUME && sc->cu_resume_bug) { 335 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_CB_COMMAND_NOP); 336 fxp_scb_wait(sc); 337 } 338 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, cmd); 339 } 340 341 static void 342 fxp_dma_wait(struct fxp_softc *sc, volatile uint16_t *status, 343 bus_dma_tag_t dmat, bus_dmamap_t map) 344 { 345 int i = 10000; 346 347 bus_dmamap_sync(dmat, map, BUS_DMASYNC_POSTREAD); 348 while (!(le16toh(*status) & FXP_CB_STATUS_C) && --i) { 349 DELAY(2); 350 bus_dmamap_sync(dmat, map, BUS_DMASYNC_POSTREAD); 351 } 352 if (i == 0) 353 device_printf(sc->dev, "DMA timeout\n"); 354 } 355 356 /* 357 * Return identification string if this device is ours. 358 */ 359 static int 360 fxp_probe(device_t dev) 361 { 362 uint16_t devid; 363 uint8_t revid; 364 struct fxp_ident *ident; 365 366 if (pci_get_vendor(dev) == FXP_VENDORID_INTEL) { 367 devid = pci_get_device(dev); 368 revid = pci_get_revid(dev); 369 for (ident = fxp_ident_table; ident->name != NULL; ident++) { 370 if (ident->devid == devid && 371 (ident->revid == revid || ident->revid == -1)) { 372 device_set_desc(dev, ident->name); 373 return (BUS_PROBE_DEFAULT); 374 } 375 } 376 } 377 return (ENXIO); 378 } 379 380 static void 381 fxp_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error) 382 { 383 uint32_t *addr; 384 385 if (error) 386 return; 387 388 KASSERT(nseg == 1, ("too many DMA segments, %d should be 1", nseg)); 389 addr = arg; 390 *addr = segs->ds_addr; 391 } 392 393 static int 394 fxp_attach(device_t dev) 395 { 396 struct fxp_softc *sc; 397 struct fxp_cb_tx *tcbp; 398 struct fxp_tx *txp; 399 struct fxp_rx *rxp; 400 struct ifnet *ifp; 401 uint32_t val; 402 uint16_t data, myea[ETHER_ADDR_LEN / 2]; 403 u_char eaddr[ETHER_ADDR_LEN]; 404 int i, prefer_iomap; 405 int error; 406 407 error = 0; 408 sc = device_get_softc(dev); 409 sc->dev = dev; 410 mtx_init(&sc->sc_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 411 MTX_DEF); 412 callout_init_mtx(&sc->stat_ch, &sc->sc_mtx, 0); 413 ifmedia_init(&sc->sc_media, 0, fxp_serial_ifmedia_upd, 414 fxp_serial_ifmedia_sts); 415 416 ifp = sc->ifp = if_alloc(IFT_ETHER); 417 if (ifp == NULL) { 418 device_printf(dev, "can not if_alloc()\n"); 419 error = ENOSPC; 420 goto fail; 421 } 422 423 /* 424 * Enable bus mastering. 425 */ 426 pci_enable_busmaster(dev); 427 val = pci_read_config(dev, PCIR_COMMAND, 2); 428 429 /* 430 * Figure out which we should try first - memory mapping or i/o mapping? 431 * We default to memory mapping. Then we accept an override from the 432 * command line. Then we check to see which one is enabled. 433 */ 434 prefer_iomap = 0; 435 resource_int_value(device_get_name(dev), device_get_unit(dev), 436 "prefer_iomap", &prefer_iomap); 437 if (prefer_iomap) 438 sc->fxp_spec = fxp_res_spec_io; 439 else 440 sc->fxp_spec = fxp_res_spec_mem; 441 442 error = bus_alloc_resources(dev, sc->fxp_spec, sc->fxp_res); 443 if (error) { 444 if (sc->fxp_spec == fxp_res_spec_mem) 445 sc->fxp_spec = fxp_res_spec_io; 446 else 447 sc->fxp_spec = fxp_res_spec_mem; 448 error = bus_alloc_resources(dev, sc->fxp_spec, sc->fxp_res); 449 } 450 if (error) { 451 device_printf(dev, "could not allocate resources\n"); 452 error = ENXIO; 453 goto fail; 454 } 455 456 if (bootverbose) { 457 device_printf(dev, "using %s space register mapping\n", 458 sc->fxp_spec == fxp_res_spec_mem ? "memory" : "I/O"); 459 } 460 461 /* 462 * Reset to a stable state. 463 */ 464 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET); 465 DELAY(10); 466 467 /* 468 * Find out how large of an SEEPROM we have. 469 */ 470 fxp_autosize_eeprom(sc); 471 472 /* 473 * Find out the chip revision; lump all 82557 revs together. 474 */ 475 fxp_read_eeprom(sc, &data, 5, 1); 476 if ((data >> 8) == 1) 477 sc->revision = FXP_REV_82557; 478 else 479 sc->revision = pci_get_revid(dev); 480 481 /* 482 * Determine whether we must use the 503 serial interface. 483 */ 484 fxp_read_eeprom(sc, &data, 6, 1); 485 if (sc->revision == FXP_REV_82557 && (data & FXP_PHY_DEVICE_MASK) != 0 486 && (data & FXP_PHY_SERIAL_ONLY)) 487 sc->flags |= FXP_FLAG_SERIAL_MEDIA; 488 489 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 490 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 491 OID_AUTO, "int_delay", CTLTYPE_INT | CTLFLAG_RW, 492 &sc->tunable_int_delay, 0, sysctl_hw_fxp_int_delay, "I", 493 "FXP driver receive interrupt microcode bundling delay"); 494 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 495 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 496 OID_AUTO, "bundle_max", CTLTYPE_INT | CTLFLAG_RW, 497 &sc->tunable_bundle_max, 0, sysctl_hw_fxp_bundle_max, "I", 498 "FXP driver receive interrupt microcode bundle size limit"); 499 SYSCTL_ADD_INT(device_get_sysctl_ctx(dev), 500 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 501 OID_AUTO, "rnr", CTLFLAG_RD, &sc->rnr, 0, 502 "FXP RNR events"); 503 SYSCTL_ADD_INT(device_get_sysctl_ctx(dev), 504 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 505 OID_AUTO, "noflow", CTLFLAG_RW, &sc->tunable_noflow, 0, 506 "FXP flow control disabled"); 507 508 /* 509 * Pull in device tunables. 510 */ 511 sc->tunable_int_delay = TUNABLE_INT_DELAY; 512 sc->tunable_bundle_max = TUNABLE_BUNDLE_MAX; 513 sc->tunable_noflow = 1; 514 (void) resource_int_value(device_get_name(dev), device_get_unit(dev), 515 "int_delay", &sc->tunable_int_delay); 516 (void) resource_int_value(device_get_name(dev), device_get_unit(dev), 517 "bundle_max", &sc->tunable_bundle_max); 518 (void) resource_int_value(device_get_name(dev), device_get_unit(dev), 519 "noflow", &sc->tunable_noflow); 520 sc->rnr = 0; 521 522 /* 523 * Enable workarounds for certain chip revision deficiencies. 524 * 525 * Systems based on the ICH2/ICH2-M chip from Intel, and possibly 526 * some systems based a normal 82559 design, have a defect where 527 * the chip can cause a PCI protocol violation if it receives 528 * a CU_RESUME command when it is entering the IDLE state. The 529 * workaround is to disable Dynamic Standby Mode, so the chip never 530 * deasserts CLKRUN#, and always remains in an active state. 531 * 532 * See Intel 82801BA/82801BAM Specification Update, Errata #30. 533 */ 534 i = pci_get_device(dev); 535 if (i == 0x2449 || (i > 0x1030 && i < 0x1039) || 536 sc->revision >= FXP_REV_82559_A0) { 537 fxp_read_eeprom(sc, &data, 10, 1); 538 if (data & 0x02) { /* STB enable */ 539 uint16_t cksum; 540 int i; 541 542 device_printf(dev, 543 "Disabling dynamic standby mode in EEPROM\n"); 544 data &= ~0x02; 545 fxp_write_eeprom(sc, &data, 10, 1); 546 device_printf(dev, "New EEPROM ID: 0x%x\n", data); 547 cksum = 0; 548 for (i = 0; i < (1 << sc->eeprom_size) - 1; i++) { 549 fxp_read_eeprom(sc, &data, i, 1); 550 cksum += data; 551 } 552 i = (1 << sc->eeprom_size) - 1; 553 cksum = 0xBABA - cksum; 554 fxp_read_eeprom(sc, &data, i, 1); 555 fxp_write_eeprom(sc, &cksum, i, 1); 556 device_printf(dev, 557 "EEPROM checksum @ 0x%x: 0x%x -> 0x%x\n", 558 i, data, cksum); 559 #if 1 560 /* 561 * If the user elects to continue, try the software 562 * workaround, as it is better than nothing. 563 */ 564 sc->flags |= FXP_FLAG_CU_RESUME_BUG; 565 #endif 566 } 567 } 568 569 /* 570 * If we are not a 82557 chip, we can enable extended features. 571 */ 572 if (sc->revision != FXP_REV_82557) { 573 /* 574 * If MWI is enabled in the PCI configuration, and there 575 * is a valid cacheline size (8 or 16 dwords), then tell 576 * the board to turn on MWI. 577 */ 578 if (val & PCIM_CMD_MWRICEN && 579 pci_read_config(dev, PCIR_CACHELNSZ, 1) != 0) 580 sc->flags |= FXP_FLAG_MWI_ENABLE; 581 582 /* turn on the extended TxCB feature */ 583 sc->flags |= FXP_FLAG_EXT_TXCB; 584 585 /* enable reception of long frames for VLAN */ 586 sc->flags |= FXP_FLAG_LONG_PKT_EN; 587 } else { 588 /* a hack to get long VLAN frames on a 82557 */ 589 sc->flags |= FXP_FLAG_SAVE_BAD; 590 } 591 592 /* 593 * Enable use of extended RFDs and TCBs for 82550 594 * and later chips. Note: we need extended TXCB support 595 * too, but that's already enabled by the code above. 596 * Be careful to do this only on the right devices. 597 */ 598 if (sc->revision == FXP_REV_82550 || sc->revision == FXP_REV_82550_C || 599 sc->revision == FXP_REV_82551_E || sc->revision == FXP_REV_82551_F 600 || sc->revision == FXP_REV_82551_10) { 601 sc->rfa_size = sizeof (struct fxp_rfa); 602 sc->tx_cmd = FXP_CB_COMMAND_IPCBXMIT; 603 sc->flags |= FXP_FLAG_EXT_RFA; 604 } else { 605 sc->rfa_size = sizeof (struct fxp_rfa) - FXP_RFAX_LEN; 606 sc->tx_cmd = FXP_CB_COMMAND_XMIT; 607 } 608 609 /* 610 * Allocate DMA tags and DMA safe memory. 611 */ 612 sc->maxtxseg = FXP_NTXSEG; 613 if (sc->flags & FXP_FLAG_EXT_RFA) 614 sc->maxtxseg--; 615 error = bus_dma_tag_create(bus_get_dma_tag(dev), 2, 0, 616 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 617 MCLBYTES * sc->maxtxseg, sc->maxtxseg, MCLBYTES, 0, 618 busdma_lock_mutex, &Giant, &sc->fxp_mtag); 619 if (error) { 620 device_printf(dev, "could not allocate dma tag\n"); 621 goto fail; 622 } 623 624 error = bus_dma_tag_create(bus_get_dma_tag(dev), 4, 0, 625 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 626 sizeof(struct fxp_stats), 1, sizeof(struct fxp_stats), 0, 627 busdma_lock_mutex, &Giant, &sc->fxp_stag); 628 if (error) { 629 device_printf(dev, "could not allocate dma tag\n"); 630 goto fail; 631 } 632 633 error = bus_dmamem_alloc(sc->fxp_stag, (void **)&sc->fxp_stats, 634 BUS_DMA_NOWAIT | BUS_DMA_ZERO, &sc->fxp_smap); 635 if (error) 636 goto fail; 637 error = bus_dmamap_load(sc->fxp_stag, sc->fxp_smap, sc->fxp_stats, 638 sizeof(struct fxp_stats), fxp_dma_map_addr, &sc->stats_addr, 0); 639 if (error) { 640 device_printf(dev, "could not map the stats buffer\n"); 641 goto fail; 642 } 643 644 error = bus_dma_tag_create(bus_get_dma_tag(dev), 4, 0, 645 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 646 FXP_TXCB_SZ, 1, FXP_TXCB_SZ, 0, 647 busdma_lock_mutex, &Giant, &sc->cbl_tag); 648 if (error) { 649 device_printf(dev, "could not allocate dma tag\n"); 650 goto fail; 651 } 652 653 error = bus_dmamem_alloc(sc->cbl_tag, (void **)&sc->fxp_desc.cbl_list, 654 BUS_DMA_NOWAIT | BUS_DMA_ZERO, &sc->cbl_map); 655 if (error) 656 goto fail; 657 658 error = bus_dmamap_load(sc->cbl_tag, sc->cbl_map, 659 sc->fxp_desc.cbl_list, FXP_TXCB_SZ, fxp_dma_map_addr, 660 &sc->fxp_desc.cbl_addr, 0); 661 if (error) { 662 device_printf(dev, "could not map DMA memory\n"); 663 goto fail; 664 } 665 666 error = bus_dma_tag_create(bus_get_dma_tag(dev), 4, 0, 667 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 668 sizeof(struct fxp_cb_mcs), 1, sizeof(struct fxp_cb_mcs), 0, 669 busdma_lock_mutex, &Giant, &sc->mcs_tag); 670 if (error) { 671 device_printf(dev, "could not allocate dma tag\n"); 672 goto fail; 673 } 674 675 error = bus_dmamem_alloc(sc->mcs_tag, (void **)&sc->mcsp, 676 BUS_DMA_NOWAIT, &sc->mcs_map); 677 if (error) 678 goto fail; 679 error = bus_dmamap_load(sc->mcs_tag, sc->mcs_map, sc->mcsp, 680 sizeof(struct fxp_cb_mcs), fxp_dma_map_addr, &sc->mcs_addr, 0); 681 if (error) { 682 device_printf(dev, "can't map the multicast setup command\n"); 683 goto fail; 684 } 685 686 /* 687 * Pre-allocate the TX DMA maps and setup the pointers to 688 * the TX command blocks. 689 */ 690 txp = sc->fxp_desc.tx_list; 691 tcbp = sc->fxp_desc.cbl_list; 692 for (i = 0; i < FXP_NTXCB; i++) { 693 txp[i].tx_cb = tcbp + i; 694 error = bus_dmamap_create(sc->fxp_mtag, 0, &txp[i].tx_map); 695 if (error) { 696 device_printf(dev, "can't create DMA map for TX\n"); 697 goto fail; 698 } 699 } 700 error = bus_dmamap_create(sc->fxp_mtag, 0, &sc->spare_map); 701 if (error) { 702 device_printf(dev, "can't create spare DMA map\n"); 703 goto fail; 704 } 705 706 /* 707 * Pre-allocate our receive buffers. 708 */ 709 sc->fxp_desc.rx_head = sc->fxp_desc.rx_tail = NULL; 710 for (i = 0; i < FXP_NRFABUFS; i++) { 711 rxp = &sc->fxp_desc.rx_list[i]; 712 error = bus_dmamap_create(sc->fxp_mtag, 0, &rxp->rx_map); 713 if (error) { 714 device_printf(dev, "can't create DMA map for RX\n"); 715 goto fail; 716 } 717 if (fxp_add_rfabuf(sc, rxp) != 0) { 718 error = ENOMEM; 719 goto fail; 720 } 721 } 722 723 /* 724 * Read MAC address. 725 */ 726 fxp_read_eeprom(sc, myea, 0, 3); 727 eaddr[0] = myea[0] & 0xff; 728 eaddr[1] = myea[0] >> 8; 729 eaddr[2] = myea[1] & 0xff; 730 eaddr[3] = myea[1] >> 8; 731 eaddr[4] = myea[2] & 0xff; 732 eaddr[5] = myea[2] >> 8; 733 if (bootverbose) { 734 device_printf(dev, "PCI IDs: %04x %04x %04x %04x %04x\n", 735 pci_get_vendor(dev), pci_get_device(dev), 736 pci_get_subvendor(dev), pci_get_subdevice(dev), 737 pci_get_revid(dev)); 738 fxp_read_eeprom(sc, &data, 10, 1); 739 device_printf(dev, "Dynamic Standby mode is %s\n", 740 data & 0x02 ? "enabled" : "disabled"); 741 } 742 743 /* 744 * If this is only a 10Mbps device, then there is no MII, and 745 * the PHY will use a serial interface instead. 746 * 747 * The Seeq 80c24 AutoDUPLEX(tm) Ethernet Interface Adapter 748 * doesn't have a programming interface of any sort. The 749 * media is sensed automatically based on how the link partner 750 * is configured. This is, in essence, manual configuration. 751 */ 752 if (sc->flags & FXP_FLAG_SERIAL_MEDIA) { 753 ifmedia_add(&sc->sc_media, IFM_ETHER|IFM_MANUAL, 0, NULL); 754 ifmedia_set(&sc->sc_media, IFM_ETHER|IFM_MANUAL); 755 } else { 756 if (mii_phy_probe(dev, &sc->miibus, fxp_ifmedia_upd, 757 fxp_ifmedia_sts)) { 758 device_printf(dev, "MII without any PHY!\n"); 759 error = ENXIO; 760 goto fail; 761 } 762 } 763 764 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 765 ifp->if_init = fxp_init; 766 ifp->if_softc = sc; 767 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 768 ifp->if_ioctl = fxp_ioctl; 769 ifp->if_start = fxp_start; 770 771 ifp->if_capabilities = ifp->if_capenable = 0; 772 773 /* Enable checksum offload for 82550 or better chips */ 774 if (sc->flags & FXP_FLAG_EXT_RFA) { 775 ifp->if_hwassist = FXP_CSUM_FEATURES; 776 ifp->if_capabilities |= IFCAP_HWCSUM; 777 ifp->if_capenable |= IFCAP_HWCSUM; 778 } 779 780 #ifdef DEVICE_POLLING 781 /* Inform the world we support polling. */ 782 ifp->if_capabilities |= IFCAP_POLLING; 783 #endif 784 785 /* 786 * Attach the interface. 787 */ 788 ether_ifattach(ifp, eaddr); 789 790 /* 791 * Tell the upper layer(s) we support long frames. 792 * Must appear after the call to ether_ifattach() because 793 * ether_ifattach() sets ifi_hdrlen to the default value. 794 */ 795 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 796 ifp->if_capabilities |= IFCAP_VLAN_MTU; 797 ifp->if_capenable |= IFCAP_VLAN_MTU; /* the hw bits already set */ 798 799 /* 800 * Let the system queue as many packets as we have available 801 * TX descriptors. 802 */ 803 IFQ_SET_MAXLEN(&ifp->if_snd, FXP_NTXCB - 1); 804 ifp->if_snd.ifq_drv_maxlen = FXP_NTXCB - 1; 805 IFQ_SET_READY(&ifp->if_snd); 806 807 /* 808 * Hook our interrupt after all initialization is complete. 809 */ 810 error = bus_setup_intr(dev, sc->fxp_res[1], INTR_TYPE_NET | INTR_MPSAFE, 811 NULL, fxp_intr, sc, &sc->ih); 812 if (error) { 813 device_printf(dev, "could not setup irq\n"); 814 ether_ifdetach(sc->ifp); 815 goto fail; 816 } 817 818 fail: 819 if (error) 820 fxp_release(sc); 821 return (error); 822 } 823 824 /* 825 * Release all resources. The softc lock should not be held and the 826 * interrupt should already be torn down. 827 */ 828 static void 829 fxp_release(struct fxp_softc *sc) 830 { 831 struct fxp_rx *rxp; 832 struct fxp_tx *txp; 833 int i; 834 835 FXP_LOCK_ASSERT(sc, MA_NOTOWNED); 836 KASSERT(sc->ih == NULL, 837 ("fxp_release() called with intr handle still active")); 838 if (sc->miibus) 839 device_delete_child(sc->dev, sc->miibus); 840 bus_generic_detach(sc->dev); 841 ifmedia_removeall(&sc->sc_media); 842 if (sc->fxp_desc.cbl_list) { 843 bus_dmamap_unload(sc->cbl_tag, sc->cbl_map); 844 bus_dmamem_free(sc->cbl_tag, sc->fxp_desc.cbl_list, 845 sc->cbl_map); 846 } 847 if (sc->fxp_stats) { 848 bus_dmamap_unload(sc->fxp_stag, sc->fxp_smap); 849 bus_dmamem_free(sc->fxp_stag, sc->fxp_stats, sc->fxp_smap); 850 } 851 if (sc->mcsp) { 852 bus_dmamap_unload(sc->mcs_tag, sc->mcs_map); 853 bus_dmamem_free(sc->mcs_tag, sc->mcsp, sc->mcs_map); 854 } 855 bus_release_resources(sc->dev, sc->fxp_spec, sc->fxp_res); 856 if (sc->fxp_mtag) { 857 for (i = 0; i < FXP_NRFABUFS; i++) { 858 rxp = &sc->fxp_desc.rx_list[i]; 859 if (rxp->rx_mbuf != NULL) { 860 bus_dmamap_sync(sc->fxp_mtag, rxp->rx_map, 861 BUS_DMASYNC_POSTREAD); 862 bus_dmamap_unload(sc->fxp_mtag, rxp->rx_map); 863 m_freem(rxp->rx_mbuf); 864 } 865 bus_dmamap_destroy(sc->fxp_mtag, rxp->rx_map); 866 } 867 bus_dmamap_destroy(sc->fxp_mtag, sc->spare_map); 868 for (i = 0; i < FXP_NTXCB; i++) { 869 txp = &sc->fxp_desc.tx_list[i]; 870 if (txp->tx_mbuf != NULL) { 871 bus_dmamap_sync(sc->fxp_mtag, txp->tx_map, 872 BUS_DMASYNC_POSTWRITE); 873 bus_dmamap_unload(sc->fxp_mtag, txp->tx_map); 874 m_freem(txp->tx_mbuf); 875 } 876 bus_dmamap_destroy(sc->fxp_mtag, txp->tx_map); 877 } 878 bus_dma_tag_destroy(sc->fxp_mtag); 879 } 880 if (sc->fxp_stag) 881 bus_dma_tag_destroy(sc->fxp_stag); 882 if (sc->cbl_tag) 883 bus_dma_tag_destroy(sc->cbl_tag); 884 if (sc->mcs_tag) 885 bus_dma_tag_destroy(sc->mcs_tag); 886 if (sc->ifp) 887 if_free(sc->ifp); 888 889 mtx_destroy(&sc->sc_mtx); 890 } 891 892 /* 893 * Detach interface. 894 */ 895 static int 896 fxp_detach(device_t dev) 897 { 898 struct fxp_softc *sc = device_get_softc(dev); 899 900 #ifdef DEVICE_POLLING 901 if (sc->ifp->if_capenable & IFCAP_POLLING) 902 ether_poll_deregister(sc->ifp); 903 #endif 904 905 FXP_LOCK(sc); 906 sc->suspended = 1; /* Do same thing as we do for suspend */ 907 /* 908 * Stop DMA and drop transmit queue, but disable interrupts first. 909 */ 910 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE); 911 fxp_stop(sc); 912 FXP_UNLOCK(sc); 913 callout_drain(&sc->stat_ch); 914 915 /* 916 * Close down routes etc. 917 */ 918 ether_ifdetach(sc->ifp); 919 920 /* 921 * Unhook interrupt before dropping lock. This is to prevent 922 * races with fxp_intr(). 923 */ 924 bus_teardown_intr(sc->dev, sc->fxp_res[1], sc->ih); 925 sc->ih = NULL; 926 927 /* Release our allocated resources. */ 928 fxp_release(sc); 929 return (0); 930 } 931 932 /* 933 * Device shutdown routine. Called at system shutdown after sync. The 934 * main purpose of this routine is to shut off receiver DMA so that 935 * kernel memory doesn't get clobbered during warmboot. 936 */ 937 static int 938 fxp_shutdown(device_t dev) 939 { 940 struct fxp_softc *sc = device_get_softc(dev); 941 942 /* 943 * Make sure that DMA is disabled prior to reboot. Not doing 944 * do could allow DMA to corrupt kernel memory during the 945 * reboot before the driver initializes. 946 */ 947 FXP_LOCK(sc); 948 fxp_stop(sc); 949 FXP_UNLOCK(sc); 950 return (0); 951 } 952 953 /* 954 * Device suspend routine. Stop the interface and save some PCI 955 * settings in case the BIOS doesn't restore them properly on 956 * resume. 957 */ 958 static int 959 fxp_suspend(device_t dev) 960 { 961 struct fxp_softc *sc = device_get_softc(dev); 962 963 FXP_LOCK(sc); 964 965 fxp_stop(sc); 966 967 sc->suspended = 1; 968 969 FXP_UNLOCK(sc); 970 return (0); 971 } 972 973 /* 974 * Device resume routine. re-enable busmastering, and restart the interface if 975 * appropriate. 976 */ 977 static int 978 fxp_resume(device_t dev) 979 { 980 struct fxp_softc *sc = device_get_softc(dev); 981 struct ifnet *ifp = sc->ifp; 982 983 FXP_LOCK(sc); 984 985 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET); 986 DELAY(10); 987 988 /* reinitialize interface if necessary */ 989 if (ifp->if_flags & IFF_UP) 990 fxp_init_body(sc); 991 992 sc->suspended = 0; 993 994 FXP_UNLOCK(sc); 995 return (0); 996 } 997 998 static void 999 fxp_eeprom_shiftin(struct fxp_softc *sc, int data, int length) 1000 { 1001 uint16_t reg; 1002 int x; 1003 1004 /* 1005 * Shift in data. 1006 */ 1007 for (x = 1 << (length - 1); x; x >>= 1) { 1008 if (data & x) 1009 reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI; 1010 else 1011 reg = FXP_EEPROM_EECS; 1012 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 1013 DELAY(1); 1014 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK); 1015 DELAY(1); 1016 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 1017 DELAY(1); 1018 } 1019 } 1020 1021 /* 1022 * Read from the serial EEPROM. Basically, you manually shift in 1023 * the read opcode (one bit at a time) and then shift in the address, 1024 * and then you shift out the data (all of this one bit at a time). 1025 * The word size is 16 bits, so you have to provide the address for 1026 * every 16 bits of data. 1027 */ 1028 static uint16_t 1029 fxp_eeprom_getword(struct fxp_softc *sc, int offset, int autosize) 1030 { 1031 uint16_t reg, data; 1032 int x; 1033 1034 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 1035 /* 1036 * Shift in read opcode. 1037 */ 1038 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_READ, 3); 1039 /* 1040 * Shift in address. 1041 */ 1042 data = 0; 1043 for (x = 1 << (sc->eeprom_size - 1); x; x >>= 1) { 1044 if (offset & x) 1045 reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI; 1046 else 1047 reg = FXP_EEPROM_EECS; 1048 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 1049 DELAY(1); 1050 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK); 1051 DELAY(1); 1052 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 1053 DELAY(1); 1054 reg = CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO; 1055 data++; 1056 if (autosize && reg == 0) { 1057 sc->eeprom_size = data; 1058 break; 1059 } 1060 } 1061 /* 1062 * Shift out data. 1063 */ 1064 data = 0; 1065 reg = FXP_EEPROM_EECS; 1066 for (x = 1 << 15; x; x >>= 1) { 1067 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK); 1068 DELAY(1); 1069 if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO) 1070 data |= x; 1071 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 1072 DELAY(1); 1073 } 1074 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 1075 DELAY(1); 1076 1077 return (data); 1078 } 1079 1080 static void 1081 fxp_eeprom_putword(struct fxp_softc *sc, int offset, uint16_t data) 1082 { 1083 int i; 1084 1085 /* 1086 * Erase/write enable. 1087 */ 1088 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 1089 fxp_eeprom_shiftin(sc, 0x4, 3); 1090 fxp_eeprom_shiftin(sc, 0x03 << (sc->eeprom_size - 2), sc->eeprom_size); 1091 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 1092 DELAY(1); 1093 /* 1094 * Shift in write opcode, address, data. 1095 */ 1096 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 1097 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_WRITE, 3); 1098 fxp_eeprom_shiftin(sc, offset, sc->eeprom_size); 1099 fxp_eeprom_shiftin(sc, data, 16); 1100 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 1101 DELAY(1); 1102 /* 1103 * Wait for EEPROM to finish up. 1104 */ 1105 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 1106 DELAY(1); 1107 for (i = 0; i < 1000; i++) { 1108 if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO) 1109 break; 1110 DELAY(50); 1111 } 1112 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 1113 DELAY(1); 1114 /* 1115 * Erase/write disable. 1116 */ 1117 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 1118 fxp_eeprom_shiftin(sc, 0x4, 3); 1119 fxp_eeprom_shiftin(sc, 0, sc->eeprom_size); 1120 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 1121 DELAY(1); 1122 } 1123 1124 /* 1125 * From NetBSD: 1126 * 1127 * Figure out EEPROM size. 1128 * 1129 * 559's can have either 64-word or 256-word EEPROMs, the 558 1130 * datasheet only talks about 64-word EEPROMs, and the 557 datasheet 1131 * talks about the existance of 16 to 256 word EEPROMs. 1132 * 1133 * The only known sizes are 64 and 256, where the 256 version is used 1134 * by CardBus cards to store CIS information. 1135 * 1136 * The address is shifted in msb-to-lsb, and after the last 1137 * address-bit the EEPROM is supposed to output a `dummy zero' bit, 1138 * after which follows the actual data. We try to detect this zero, by 1139 * probing the data-out bit in the EEPROM control register just after 1140 * having shifted in a bit. If the bit is zero, we assume we've 1141 * shifted enough address bits. The data-out should be tri-state, 1142 * before this, which should translate to a logical one. 1143 */ 1144 static void 1145 fxp_autosize_eeprom(struct fxp_softc *sc) 1146 { 1147 1148 /* guess maximum size of 256 words */ 1149 sc->eeprom_size = 8; 1150 1151 /* autosize */ 1152 (void) fxp_eeprom_getword(sc, 0, 1); 1153 } 1154 1155 static void 1156 fxp_read_eeprom(struct fxp_softc *sc, u_short *data, int offset, int words) 1157 { 1158 int i; 1159 1160 for (i = 0; i < words; i++) 1161 data[i] = fxp_eeprom_getword(sc, offset + i, 0); 1162 } 1163 1164 static void 1165 fxp_write_eeprom(struct fxp_softc *sc, u_short *data, int offset, int words) 1166 { 1167 int i; 1168 1169 for (i = 0; i < words; i++) 1170 fxp_eeprom_putword(sc, offset + i, data[i]); 1171 } 1172 1173 /* 1174 * Grab the softc lock and call the real fxp_start_body() routine 1175 */ 1176 static void 1177 fxp_start(struct ifnet *ifp) 1178 { 1179 struct fxp_softc *sc = ifp->if_softc; 1180 1181 FXP_LOCK(sc); 1182 fxp_start_body(ifp); 1183 FXP_UNLOCK(sc); 1184 } 1185 1186 /* 1187 * Start packet transmission on the interface. 1188 * This routine must be called with the softc lock held, and is an 1189 * internal entry point only. 1190 */ 1191 static void 1192 fxp_start_body(struct ifnet *ifp) 1193 { 1194 struct fxp_softc *sc = ifp->if_softc; 1195 struct mbuf *mb_head; 1196 int error, txqueued; 1197 1198 FXP_LOCK_ASSERT(sc, MA_OWNED); 1199 1200 /* 1201 * See if we need to suspend xmit until the multicast filter 1202 * has been reprogrammed (which can only be done at the head 1203 * of the command chain). 1204 */ 1205 if (sc->need_mcsetup) 1206 return; 1207 1208 /* 1209 * We're finished if there is nothing more to add to the list or if 1210 * we're all filled up with buffers to transmit. 1211 * NOTE: One TxCB is reserved to guarantee that fxp_mc_setup() can add 1212 * a NOP command when needed. 1213 */ 1214 txqueued = 0; 1215 while (!IFQ_DRV_IS_EMPTY(&ifp->if_snd) && 1216 sc->tx_queued < FXP_NTXCB - 1) { 1217 1218 /* 1219 * Grab a packet to transmit. 1220 */ 1221 IFQ_DRV_DEQUEUE(&ifp->if_snd, mb_head); 1222 if (mb_head == NULL) 1223 break; 1224 1225 error = fxp_encap(sc, mb_head); 1226 if (error) 1227 break; 1228 txqueued = 1; 1229 } 1230 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE); 1231 1232 /* 1233 * We're finished. If we added to the list, issue a RESUME to get DMA 1234 * going again if suspended. 1235 */ 1236 if (txqueued) { 1237 fxp_scb_wait(sc); 1238 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_RESUME); 1239 } 1240 } 1241 1242 static int 1243 fxp_encap(struct fxp_softc *sc, struct mbuf *m_head) 1244 { 1245 struct ifnet *ifp; 1246 struct mbuf *m; 1247 struct fxp_tx *txp; 1248 struct fxp_cb_tx *cbp; 1249 bus_dma_segment_t segs[FXP_NTXSEG]; 1250 int chainlen, error, i, nseg; 1251 1252 FXP_LOCK_ASSERT(sc, MA_OWNED); 1253 ifp = sc->ifp; 1254 1255 /* 1256 * Get pointer to next available tx desc. 1257 */ 1258 txp = sc->fxp_desc.tx_last->tx_next; 1259 1260 /* 1261 * A note in Appendix B of the Intel 8255x 10/100 Mbps 1262 * Ethernet Controller Family Open Source Software 1263 * Developer Manual says: 1264 * Using software parsing is only allowed with legal 1265 * TCP/IP or UDP/IP packets. 1266 * ... 1267 * For all other datagrams, hardware parsing must 1268 * be used. 1269 * Software parsing appears to truncate ICMP and 1270 * fragmented UDP packets that contain one to three 1271 * bytes in the second (and final) mbuf of the packet. 1272 */ 1273 if (sc->flags & FXP_FLAG_EXT_RFA) 1274 txp->tx_cb->ipcb_ip_activation_high = 1275 FXP_IPCB_HARDWAREPARSING_ENABLE; 1276 1277 /* 1278 * Deal with TCP/IP checksum offload. Note that 1279 * in order for TCP checksum offload to work, 1280 * the pseudo header checksum must have already 1281 * been computed and stored in the checksum field 1282 * in the TCP header. The stack should have 1283 * already done this for us. 1284 */ 1285 if (m_head->m_pkthdr.csum_flags) { 1286 if (m_head->m_pkthdr.csum_flags & CSUM_DELAY_DATA) { 1287 txp->tx_cb->ipcb_ip_schedule = 1288 FXP_IPCB_TCPUDP_CHECKSUM_ENABLE; 1289 if (m_head->m_pkthdr.csum_flags & CSUM_TCP) 1290 txp->tx_cb->ipcb_ip_schedule |= 1291 FXP_IPCB_TCP_PACKET; 1292 } 1293 1294 #ifdef FXP_IP_CSUM_WAR 1295 /* 1296 * XXX The 82550 chip appears to have trouble 1297 * dealing with IP header checksums in very small 1298 * datagrams, namely fragments from 1 to 3 bytes 1299 * in size. For example, say you want to transmit 1300 * a UDP packet of 1473 bytes. The packet will be 1301 * fragmented over two IP datagrams, the latter 1302 * containing only one byte of data. The 82550 will 1303 * botch the header checksum on the 1-byte fragment. 1304 * As long as the datagram contains 4 or more bytes 1305 * of data, you're ok. 1306 * 1307 * The following code attempts to work around this 1308 * problem: if the datagram is less than 38 bytes 1309 * in size (14 bytes ether header, 20 bytes IP header, 1310 * plus 4 bytes of data), we punt and compute the IP 1311 * header checksum by hand. This workaround doesn't 1312 * work very well, however, since it can be fooled 1313 * by things like VLAN tags and IP options that make 1314 * the header sizes/offsets vary. 1315 */ 1316 1317 if (m_head->m_pkthdr.csum_flags & CSUM_IP) { 1318 if (m_head->m_pkthdr.len < 38) { 1319 struct ip *ip; 1320 m_head->m_data += ETHER_HDR_LEN; 1321 ip = mtod(mb_head, struct ip *); 1322 ip->ip_sum = in_cksum(mb_head, ip->ip_hl << 2); 1323 m_head->m_data -= ETHER_HDR_LEN; 1324 } else { 1325 txp->tx_cb->ipcb_ip_activation_high = 1326 FXP_IPCB_HARDWAREPARSING_ENABLE; 1327 txp->tx_cb->ipcb_ip_schedule |= 1328 FXP_IPCB_IP_CHECKSUM_ENABLE; 1329 } 1330 } 1331 #endif 1332 } 1333 1334 chainlen = 0; 1335 for (m = m_head; m != NULL && chainlen <= sc->maxtxseg; m = m->m_next) 1336 chainlen++; 1337 if (chainlen > sc->maxtxseg) { 1338 struct mbuf *mn; 1339 1340 /* 1341 * We ran out of segments. We have to recopy this 1342 * mbuf chain first. Bail out if we can't get the 1343 * new buffers. 1344 */ 1345 mn = m_defrag(m_head, M_DONTWAIT); 1346 if (mn == NULL) { 1347 m_freem(m_head); 1348 return (-1); 1349 } else { 1350 m_head = mn; 1351 } 1352 } 1353 1354 /* 1355 * Go through each of the mbufs in the chain and initialize 1356 * the transmit buffer descriptors with the physical address 1357 * and size of the mbuf. 1358 */ 1359 error = bus_dmamap_load_mbuf_sg(sc->fxp_mtag, txp->tx_map, 1360 m_head, segs, &nseg, 0); 1361 if (error) { 1362 device_printf(sc->dev, "can't map mbuf (error %d)\n", error); 1363 m_freem(m_head); 1364 return (-1); 1365 } 1366 1367 KASSERT(nseg <= sc->maxtxseg, ("too many DMA segments")); 1368 1369 cbp = txp->tx_cb; 1370 for (i = 0; i < nseg; i++) { 1371 KASSERT(segs[i].ds_len <= MCLBYTES, ("segment size too large")); 1372 /* 1373 * If this is an 82550/82551, then we're using extended 1374 * TxCBs _and_ we're using checksum offload. This means 1375 * that the TxCB is really an IPCB. One major difference 1376 * between the two is that with plain extended TxCBs, 1377 * the bottom half of the TxCB contains two entries from 1378 * the TBD array, whereas IPCBs contain just one entry: 1379 * one entry (8 bytes) has been sacrificed for the TCP/IP 1380 * checksum offload control bits. So to make things work 1381 * right, we have to start filling in the TBD array 1382 * starting from a different place depending on whether 1383 * the chip is an 82550/82551 or not. 1384 */ 1385 if (sc->flags & FXP_FLAG_EXT_RFA) { 1386 cbp->tbd[i + 1].tb_addr = htole32(segs[i].ds_addr); 1387 cbp->tbd[i + 1].tb_size = htole32(segs[i].ds_len); 1388 } else { 1389 cbp->tbd[i].tb_addr = htole32(segs[i].ds_addr); 1390 cbp->tbd[i].tb_size = htole32(segs[i].ds_len); 1391 } 1392 } 1393 cbp->tbd_number = nseg; 1394 1395 bus_dmamap_sync(sc->fxp_mtag, txp->tx_map, BUS_DMASYNC_PREWRITE); 1396 txp->tx_mbuf = m_head; 1397 txp->tx_cb->cb_status = 0; 1398 txp->tx_cb->byte_count = 0; 1399 if (sc->tx_queued != FXP_CXINT_THRESH - 1) { 1400 txp->tx_cb->cb_command = 1401 htole16(sc->tx_cmd | FXP_CB_COMMAND_SF | 1402 FXP_CB_COMMAND_S); 1403 } else { 1404 txp->tx_cb->cb_command = 1405 htole16(sc->tx_cmd | FXP_CB_COMMAND_SF | 1406 FXP_CB_COMMAND_S | FXP_CB_COMMAND_I); 1407 /* 1408 * Set a 5 second timer just in case we don't hear 1409 * from the card again. 1410 */ 1411 sc->watchdog_timer = 5; 1412 } 1413 txp->tx_cb->tx_threshold = tx_threshold; 1414 1415 /* 1416 * Advance the end of list forward. 1417 */ 1418 1419 #ifdef __alpha__ 1420 /* 1421 * On platforms which can't access memory in 16-bit 1422 * granularities, we must prevent the card from DMA'ing 1423 * up the status while we update the command field. 1424 * This could cause us to overwrite the completion status. 1425 * XXX This is probably bogus and we're _not_ looking 1426 * for atomicity here. 1427 */ 1428 atomic_clear_16(&sc->fxp_desc.tx_last->tx_cb->cb_command, 1429 htole16(FXP_CB_COMMAND_S)); 1430 #else 1431 sc->fxp_desc.tx_last->tx_cb->cb_command &= htole16(~FXP_CB_COMMAND_S); 1432 #endif /*__alpha__*/ 1433 sc->fxp_desc.tx_last = txp; 1434 1435 /* 1436 * Advance the beginning of the list forward if there are 1437 * no other packets queued (when nothing is queued, tx_first 1438 * sits on the last TxCB that was sent out). 1439 */ 1440 if (sc->tx_queued == 0) 1441 sc->fxp_desc.tx_first = txp; 1442 1443 sc->tx_queued++; 1444 1445 /* 1446 * Pass packet to bpf if there is a listener. 1447 */ 1448 BPF_MTAP(ifp, m_head); 1449 return (0); 1450 } 1451 1452 #ifdef DEVICE_POLLING 1453 static poll_handler_t fxp_poll; 1454 1455 static void 1456 fxp_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 1457 { 1458 struct fxp_softc *sc = ifp->if_softc; 1459 uint8_t statack; 1460 1461 FXP_LOCK(sc); 1462 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) { 1463 FXP_UNLOCK(sc); 1464 return; 1465 } 1466 1467 statack = FXP_SCB_STATACK_CXTNO | FXP_SCB_STATACK_CNA | 1468 FXP_SCB_STATACK_FR; 1469 if (cmd == POLL_AND_CHECK_STATUS) { 1470 uint8_t tmp; 1471 1472 tmp = CSR_READ_1(sc, FXP_CSR_SCB_STATACK); 1473 if (tmp == 0xff || tmp == 0) { 1474 FXP_UNLOCK(sc); 1475 return; /* nothing to do */ 1476 } 1477 tmp &= ~statack; 1478 /* ack what we can */ 1479 if (tmp != 0) 1480 CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, tmp); 1481 statack |= tmp; 1482 } 1483 fxp_intr_body(sc, ifp, statack, count); 1484 FXP_UNLOCK(sc); 1485 } 1486 #endif /* DEVICE_POLLING */ 1487 1488 /* 1489 * Process interface interrupts. 1490 */ 1491 static void 1492 fxp_intr(void *xsc) 1493 { 1494 struct fxp_softc *sc = xsc; 1495 struct ifnet *ifp = sc->ifp; 1496 uint8_t statack; 1497 1498 FXP_LOCK(sc); 1499 if (sc->suspended) { 1500 FXP_UNLOCK(sc); 1501 return; 1502 } 1503 1504 #ifdef DEVICE_POLLING 1505 if (ifp->if_capenable & IFCAP_POLLING) { 1506 FXP_UNLOCK(sc); 1507 return; 1508 } 1509 #endif 1510 while ((statack = CSR_READ_1(sc, FXP_CSR_SCB_STATACK)) != 0) { 1511 /* 1512 * It should not be possible to have all bits set; the 1513 * FXP_SCB_INTR_SWI bit always returns 0 on a read. If 1514 * all bits are set, this may indicate that the card has 1515 * been physically ejected, so ignore it. 1516 */ 1517 if (statack == 0xff) { 1518 FXP_UNLOCK(sc); 1519 return; 1520 } 1521 1522 /* 1523 * First ACK all the interrupts in this pass. 1524 */ 1525 CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, statack); 1526 fxp_intr_body(sc, ifp, statack, -1); 1527 } 1528 FXP_UNLOCK(sc); 1529 } 1530 1531 static void 1532 fxp_txeof(struct fxp_softc *sc) 1533 { 1534 struct fxp_tx *txp; 1535 1536 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREREAD); 1537 for (txp = sc->fxp_desc.tx_first; sc->tx_queued && 1538 (le16toh(txp->tx_cb->cb_status) & FXP_CB_STATUS_C) != 0; 1539 txp = txp->tx_next) { 1540 if (txp->tx_mbuf != NULL) { 1541 bus_dmamap_sync(sc->fxp_mtag, txp->tx_map, 1542 BUS_DMASYNC_POSTWRITE); 1543 bus_dmamap_unload(sc->fxp_mtag, txp->tx_map); 1544 m_freem(txp->tx_mbuf); 1545 txp->tx_mbuf = NULL; 1546 /* clear this to reset csum offload bits */ 1547 txp->tx_cb->tbd[0].tb_addr = 0; 1548 } 1549 sc->tx_queued--; 1550 } 1551 sc->fxp_desc.tx_first = txp; 1552 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE); 1553 } 1554 1555 static void 1556 fxp_intr_body(struct fxp_softc *sc, struct ifnet *ifp, uint8_t statack, 1557 int count) 1558 { 1559 struct mbuf *m; 1560 struct fxp_rx *rxp; 1561 struct fxp_rfa *rfa; 1562 int rnr = (statack & FXP_SCB_STATACK_RNR) ? 1 : 0; 1563 int fxp_rc = 0; 1564 1565 FXP_LOCK_ASSERT(sc, MA_OWNED); 1566 if (rnr) 1567 sc->rnr++; 1568 #ifdef DEVICE_POLLING 1569 /* Pick up a deferred RNR condition if `count' ran out last time. */ 1570 if (sc->flags & FXP_FLAG_DEFERRED_RNR) { 1571 sc->flags &= ~FXP_FLAG_DEFERRED_RNR; 1572 rnr = 1; 1573 } 1574 #endif 1575 1576 /* 1577 * Free any finished transmit mbuf chains. 1578 * 1579 * Handle the CNA event likt a CXTNO event. It used to 1580 * be that this event (control unit not ready) was not 1581 * encountered, but it is now with the SMPng modifications. 1582 * The exact sequence of events that occur when the interface 1583 * is brought up are different now, and if this event 1584 * goes unhandled, the configuration/rxfilter setup sequence 1585 * can stall for several seconds. The result is that no 1586 * packets go out onto the wire for about 5 to 10 seconds 1587 * after the interface is ifconfig'ed for the first time. 1588 */ 1589 if (statack & (FXP_SCB_STATACK_CXTNO | FXP_SCB_STATACK_CNA)) { 1590 fxp_txeof(sc); 1591 1592 sc->watchdog_timer = 0; 1593 if (sc->tx_queued == 0) { 1594 if (sc->need_mcsetup) 1595 fxp_mc_setup(sc); 1596 } 1597 /* 1598 * Try to start more packets transmitting. 1599 */ 1600 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1601 fxp_start_body(ifp); 1602 } 1603 1604 /* 1605 * Just return if nothing happened on the receive side. 1606 */ 1607 if (!rnr && (statack & FXP_SCB_STATACK_FR) == 0) 1608 return; 1609 1610 /* 1611 * Process receiver interrupts. If a no-resource (RNR) 1612 * condition exists, get whatever packets we can and 1613 * re-start the receiver. 1614 * 1615 * When using polling, we do not process the list to completion, 1616 * so when we get an RNR interrupt we must defer the restart 1617 * until we hit the last buffer with the C bit set. 1618 * If we run out of cycles and rfa_headm has the C bit set, 1619 * record the pending RNR in the FXP_FLAG_DEFERRED_RNR flag so 1620 * that the info will be used in the subsequent polling cycle. 1621 */ 1622 for (;;) { 1623 rxp = sc->fxp_desc.rx_head; 1624 m = rxp->rx_mbuf; 1625 rfa = (struct fxp_rfa *)(m->m_ext.ext_buf + 1626 RFA_ALIGNMENT_FUDGE); 1627 bus_dmamap_sync(sc->fxp_mtag, rxp->rx_map, 1628 BUS_DMASYNC_POSTREAD); 1629 1630 #ifdef DEVICE_POLLING /* loop at most count times if count >=0 */ 1631 if (count >= 0 && count-- == 0) { 1632 if (rnr) { 1633 /* Defer RNR processing until the next time. */ 1634 sc->flags |= FXP_FLAG_DEFERRED_RNR; 1635 rnr = 0; 1636 } 1637 break; 1638 } 1639 #endif /* DEVICE_POLLING */ 1640 1641 if ((le16toh(rfa->rfa_status) & FXP_RFA_STATUS_C) == 0) 1642 break; 1643 1644 /* 1645 * Advance head forward. 1646 */ 1647 sc->fxp_desc.rx_head = rxp->rx_next; 1648 1649 /* 1650 * Add a new buffer to the receive chain. 1651 * If this fails, the old buffer is recycled 1652 * instead. 1653 */ 1654 fxp_rc = fxp_add_rfabuf(sc, rxp); 1655 if (fxp_rc == 0) { 1656 int total_len; 1657 1658 /* 1659 * Fetch packet length (the top 2 bits of 1660 * actual_size are flags set by the controller 1661 * upon completion), and drop the packet in case 1662 * of bogus length or CRC errors. 1663 */ 1664 total_len = le16toh(rfa->actual_size) & 0x3fff; 1665 if (total_len < sizeof(struct ether_header) || 1666 total_len > MCLBYTES - RFA_ALIGNMENT_FUDGE - 1667 sc->rfa_size || 1668 le16toh(rfa->rfa_status) & FXP_RFA_STATUS_CRC) { 1669 m_freem(m); 1670 continue; 1671 } 1672 1673 /* Do IP checksum checking. */ 1674 if (le16toh(rfa->rfa_status) & FXP_RFA_STATUS_PARSE) { 1675 if (rfa->rfax_csum_sts & 1676 FXP_RFDX_CS_IP_CSUM_BIT_VALID) 1677 m->m_pkthdr.csum_flags |= 1678 CSUM_IP_CHECKED; 1679 if (rfa->rfax_csum_sts & 1680 FXP_RFDX_CS_IP_CSUM_VALID) 1681 m->m_pkthdr.csum_flags |= 1682 CSUM_IP_VALID; 1683 if ((rfa->rfax_csum_sts & 1684 FXP_RFDX_CS_TCPUDP_CSUM_BIT_VALID) && 1685 (rfa->rfax_csum_sts & 1686 FXP_RFDX_CS_TCPUDP_CSUM_VALID)) { 1687 m->m_pkthdr.csum_flags |= 1688 CSUM_DATA_VALID|CSUM_PSEUDO_HDR; 1689 m->m_pkthdr.csum_data = 0xffff; 1690 } 1691 } 1692 1693 m->m_pkthdr.len = m->m_len = total_len; 1694 m->m_pkthdr.rcvif = ifp; 1695 1696 /* 1697 * Drop locks before calling if_input() since it 1698 * may re-enter fxp_start() in the netisr case. 1699 * This would result in a lock reversal. Better 1700 * performance might be obtained by chaining all 1701 * packets received, dropping the lock, and then 1702 * calling if_input() on each one. 1703 */ 1704 FXP_UNLOCK(sc); 1705 (*ifp->if_input)(ifp, m); 1706 FXP_LOCK(sc); 1707 } else if (fxp_rc == ENOBUFS) { 1708 rnr = 0; 1709 break; 1710 } 1711 } 1712 if (rnr) { 1713 fxp_scb_wait(sc); 1714 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 1715 sc->fxp_desc.rx_head->rx_addr); 1716 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_START); 1717 } 1718 } 1719 1720 /* 1721 * Update packet in/out/collision statistics. The i82557 doesn't 1722 * allow you to access these counters without doing a fairly 1723 * expensive DMA to get _all_ of the statistics it maintains, so 1724 * we do this operation here only once per second. The statistics 1725 * counters in the kernel are updated from the previous dump-stats 1726 * DMA and then a new dump-stats DMA is started. The on-chip 1727 * counters are zeroed when the DMA completes. If we can't start 1728 * the DMA immediately, we don't wait - we just prepare to read 1729 * them again next time. 1730 */ 1731 static void 1732 fxp_tick(void *xsc) 1733 { 1734 struct fxp_softc *sc = xsc; 1735 struct ifnet *ifp = sc->ifp; 1736 struct fxp_stats *sp = sc->fxp_stats; 1737 1738 FXP_LOCK_ASSERT(sc, MA_OWNED); 1739 bus_dmamap_sync(sc->fxp_stag, sc->fxp_smap, BUS_DMASYNC_POSTREAD); 1740 ifp->if_opackets += le32toh(sp->tx_good); 1741 ifp->if_collisions += le32toh(sp->tx_total_collisions); 1742 if (sp->rx_good) { 1743 ifp->if_ipackets += le32toh(sp->rx_good); 1744 sc->rx_idle_secs = 0; 1745 } else { 1746 /* 1747 * Receiver's been idle for another second. 1748 */ 1749 sc->rx_idle_secs++; 1750 } 1751 ifp->if_ierrors += 1752 le32toh(sp->rx_crc_errors) + 1753 le32toh(sp->rx_alignment_errors) + 1754 le32toh(sp->rx_rnr_errors) + 1755 le32toh(sp->rx_overrun_errors); 1756 /* 1757 * If any transmit underruns occured, bump up the transmit 1758 * threshold by another 512 bytes (64 * 8). 1759 */ 1760 if (sp->tx_underruns) { 1761 ifp->if_oerrors += le32toh(sp->tx_underruns); 1762 if (tx_threshold < 192) 1763 tx_threshold += 64; 1764 } 1765 1766 /* 1767 * Release any xmit buffers that have completed DMA. This isn't 1768 * strictly necessary to do here, but it's advantagous for mbufs 1769 * with external storage to be released in a timely manner rather 1770 * than being defered for a potentially long time. This limits 1771 * the delay to a maximum of one second. 1772 */ 1773 fxp_txeof(sc); 1774 1775 /* 1776 * If we haven't received any packets in FXP_MAC_RX_IDLE seconds, 1777 * then assume the receiver has locked up and attempt to clear 1778 * the condition by reprogramming the multicast filter. This is 1779 * a work-around for a bug in the 82557 where the receiver locks 1780 * up if it gets certain types of garbage in the syncronization 1781 * bits prior to the packet header. This bug is supposed to only 1782 * occur in 10Mbps mode, but has been seen to occur in 100Mbps 1783 * mode as well (perhaps due to a 10/100 speed transition). 1784 */ 1785 if (sc->rx_idle_secs > FXP_MAX_RX_IDLE) { 1786 sc->rx_idle_secs = 0; 1787 fxp_mc_setup(sc); 1788 } 1789 /* 1790 * If there is no pending command, start another stats 1791 * dump. Otherwise punt for now. 1792 */ 1793 if (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) == 0) { 1794 /* 1795 * Start another stats dump. 1796 */ 1797 bus_dmamap_sync(sc->fxp_stag, sc->fxp_smap, 1798 BUS_DMASYNC_PREREAD); 1799 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_DUMPRESET); 1800 } else { 1801 /* 1802 * A previous command is still waiting to be accepted. 1803 * Just zero our copy of the stats and wait for the 1804 * next timer event to update them. 1805 */ 1806 sp->tx_good = 0; 1807 sp->tx_underruns = 0; 1808 sp->tx_total_collisions = 0; 1809 1810 sp->rx_good = 0; 1811 sp->rx_crc_errors = 0; 1812 sp->rx_alignment_errors = 0; 1813 sp->rx_rnr_errors = 0; 1814 sp->rx_overrun_errors = 0; 1815 } 1816 if (sc->miibus != NULL) 1817 mii_tick(device_get_softc(sc->miibus)); 1818 1819 /* 1820 * Check that chip hasn't hung. 1821 */ 1822 fxp_watchdog(sc); 1823 1824 /* 1825 * Schedule another timeout one second from now. 1826 */ 1827 callout_reset(&sc->stat_ch, hz, fxp_tick, sc); 1828 } 1829 1830 /* 1831 * Stop the interface. Cancels the statistics updater and resets 1832 * the interface. 1833 */ 1834 static void 1835 fxp_stop(struct fxp_softc *sc) 1836 { 1837 struct ifnet *ifp = sc->ifp; 1838 struct fxp_tx *txp; 1839 int i; 1840 1841 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 1842 sc->watchdog_timer = 0; 1843 1844 /* 1845 * Cancel stats updater. 1846 */ 1847 callout_stop(&sc->stat_ch); 1848 1849 /* 1850 * Issue software reset, which also unloads the microcode. 1851 */ 1852 sc->flags &= ~FXP_FLAG_UCODE; 1853 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SOFTWARE_RESET); 1854 DELAY(50); 1855 1856 /* 1857 * Release any xmit buffers. 1858 */ 1859 txp = sc->fxp_desc.tx_list; 1860 if (txp != NULL) { 1861 for (i = 0; i < FXP_NTXCB; i++) { 1862 if (txp[i].tx_mbuf != NULL) { 1863 bus_dmamap_sync(sc->fxp_mtag, txp[i].tx_map, 1864 BUS_DMASYNC_POSTWRITE); 1865 bus_dmamap_unload(sc->fxp_mtag, txp[i].tx_map); 1866 m_freem(txp[i].tx_mbuf); 1867 txp[i].tx_mbuf = NULL; 1868 /* clear this to reset csum offload bits */ 1869 txp[i].tx_cb->tbd[0].tb_addr = 0; 1870 } 1871 } 1872 } 1873 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE); 1874 sc->tx_queued = 0; 1875 } 1876 1877 /* 1878 * Watchdog/transmission transmit timeout handler. Called when a 1879 * transmission is started on the interface, but no interrupt is 1880 * received before the timeout. This usually indicates that the 1881 * card has wedged for some reason. 1882 */ 1883 static void 1884 fxp_watchdog(struct fxp_softc *sc) 1885 { 1886 1887 FXP_LOCK_ASSERT(sc, MA_OWNED); 1888 1889 if (sc->watchdog_timer == 0 || --sc->watchdog_timer) 1890 return; 1891 1892 device_printf(sc->dev, "device timeout\n"); 1893 sc->ifp->if_oerrors++; 1894 1895 fxp_init_body(sc); 1896 } 1897 1898 /* 1899 * Acquire locks and then call the real initialization function. This 1900 * is necessary because ether_ioctl() calls if_init() and this would 1901 * result in mutex recursion if the mutex was held. 1902 */ 1903 static void 1904 fxp_init(void *xsc) 1905 { 1906 struct fxp_softc *sc = xsc; 1907 1908 FXP_LOCK(sc); 1909 fxp_init_body(sc); 1910 FXP_UNLOCK(sc); 1911 } 1912 1913 /* 1914 * Perform device initialization. This routine must be called with the 1915 * softc lock held. 1916 */ 1917 static void 1918 fxp_init_body(struct fxp_softc *sc) 1919 { 1920 struct ifnet *ifp = sc->ifp; 1921 struct fxp_cb_config *cbp; 1922 struct fxp_cb_ias *cb_ias; 1923 struct fxp_cb_tx *tcbp; 1924 struct fxp_tx *txp; 1925 struct fxp_cb_mcs *mcsp; 1926 int i, prm; 1927 1928 FXP_LOCK_ASSERT(sc, MA_OWNED); 1929 /* 1930 * Cancel any pending I/O 1931 */ 1932 fxp_stop(sc); 1933 1934 prm = (ifp->if_flags & IFF_PROMISC) ? 1 : 0; 1935 1936 /* 1937 * Initialize base of CBL and RFA memory. Loading with zero 1938 * sets it up for regular linear addressing. 1939 */ 1940 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 0); 1941 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_BASE); 1942 1943 fxp_scb_wait(sc); 1944 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_BASE); 1945 1946 /* 1947 * Initialize base of dump-stats buffer. 1948 */ 1949 fxp_scb_wait(sc); 1950 bus_dmamap_sync(sc->fxp_stag, sc->fxp_smap, BUS_DMASYNC_PREREAD); 1951 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->stats_addr); 1952 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_DUMP_ADR); 1953 1954 /* 1955 * Attempt to load microcode if requested. 1956 */ 1957 if (ifp->if_flags & IFF_LINK0 && (sc->flags & FXP_FLAG_UCODE) == 0) 1958 fxp_load_ucode(sc); 1959 1960 /* 1961 * Initialize the multicast address list. 1962 */ 1963 if (fxp_mc_addrs(sc)) { 1964 mcsp = sc->mcsp; 1965 mcsp->cb_status = 0; 1966 mcsp->cb_command = 1967 htole16(FXP_CB_COMMAND_MCAS | FXP_CB_COMMAND_EL); 1968 mcsp->link_addr = 0xffffffff; 1969 /* 1970 * Start the multicast setup command. 1971 */ 1972 fxp_scb_wait(sc); 1973 bus_dmamap_sync(sc->mcs_tag, sc->mcs_map, BUS_DMASYNC_PREWRITE); 1974 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->mcs_addr); 1975 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 1976 /* ...and wait for it to complete. */ 1977 fxp_dma_wait(sc, &mcsp->cb_status, sc->mcs_tag, sc->mcs_map); 1978 bus_dmamap_sync(sc->mcs_tag, sc->mcs_map, 1979 BUS_DMASYNC_POSTWRITE); 1980 } 1981 1982 /* 1983 * We temporarily use memory that contains the TxCB list to 1984 * construct the config CB. The TxCB list memory is rebuilt 1985 * later. 1986 */ 1987 cbp = (struct fxp_cb_config *)sc->fxp_desc.cbl_list; 1988 1989 /* 1990 * This bcopy is kind of disgusting, but there are a bunch of must be 1991 * zero and must be one bits in this structure and this is the easiest 1992 * way to initialize them all to proper values. 1993 */ 1994 bcopy(fxp_cb_config_template, cbp, sizeof(fxp_cb_config_template)); 1995 1996 cbp->cb_status = 0; 1997 cbp->cb_command = htole16(FXP_CB_COMMAND_CONFIG | 1998 FXP_CB_COMMAND_EL); 1999 cbp->link_addr = 0xffffffff; /* (no) next command */ 2000 cbp->byte_count = sc->flags & FXP_FLAG_EXT_RFA ? 32 : 22; 2001 cbp->rx_fifo_limit = 8; /* rx fifo threshold (32 bytes) */ 2002 cbp->tx_fifo_limit = 0; /* tx fifo threshold (0 bytes) */ 2003 cbp->adaptive_ifs = 0; /* (no) adaptive interframe spacing */ 2004 cbp->mwi_enable = sc->flags & FXP_FLAG_MWI_ENABLE ? 1 : 0; 2005 cbp->type_enable = 0; /* actually reserved */ 2006 cbp->read_align_en = sc->flags & FXP_FLAG_READ_ALIGN ? 1 : 0; 2007 cbp->end_wr_on_cl = sc->flags & FXP_FLAG_WRITE_ALIGN ? 1 : 0; 2008 cbp->rx_dma_bytecount = 0; /* (no) rx DMA max */ 2009 cbp->tx_dma_bytecount = 0; /* (no) tx DMA max */ 2010 cbp->dma_mbce = 0; /* (disable) dma max counters */ 2011 cbp->late_scb = 0; /* (don't) defer SCB update */ 2012 cbp->direct_dma_dis = 1; /* disable direct rcv dma mode */ 2013 cbp->tno_int_or_tco_en =0; /* (disable) tx not okay interrupt */ 2014 cbp->ci_int = 1; /* interrupt on CU idle */ 2015 cbp->ext_txcb_dis = sc->flags & FXP_FLAG_EXT_TXCB ? 0 : 1; 2016 cbp->ext_stats_dis = 1; /* disable extended counters */ 2017 cbp->keep_overrun_rx = 0; /* don't pass overrun frames to host */ 2018 cbp->save_bf = sc->flags & FXP_FLAG_SAVE_BAD ? 1 : prm; 2019 cbp->disc_short_rx = !prm; /* discard short packets */ 2020 cbp->underrun_retry = 1; /* retry mode (once) on DMA underrun */ 2021 cbp->two_frames = 0; /* do not limit FIFO to 2 frames */ 2022 cbp->dyn_tbd = 0; /* (no) dynamic TBD mode */ 2023 cbp->ext_rfa = sc->flags & FXP_FLAG_EXT_RFA ? 1 : 0; 2024 cbp->mediatype = sc->flags & FXP_FLAG_SERIAL_MEDIA ? 0 : 1; 2025 cbp->csma_dis = 0; /* (don't) disable link */ 2026 cbp->tcp_udp_cksum = 0; /* (don't) enable checksum */ 2027 cbp->vlan_tco = 0; /* (don't) enable vlan wakeup */ 2028 cbp->link_wake_en = 0; /* (don't) assert PME# on link change */ 2029 cbp->arp_wake_en = 0; /* (don't) assert PME# on arp */ 2030 cbp->mc_wake_en = 0; /* (don't) enable PME# on mcmatch */ 2031 cbp->nsai = 1; /* (don't) disable source addr insert */ 2032 cbp->preamble_length = 2; /* (7 byte) preamble */ 2033 cbp->loopback = 0; /* (don't) loopback */ 2034 cbp->linear_priority = 0; /* (normal CSMA/CD operation) */ 2035 cbp->linear_pri_mode = 0; /* (wait after xmit only) */ 2036 cbp->interfrm_spacing = 6; /* (96 bits of) interframe spacing */ 2037 cbp->promiscuous = prm; /* promiscuous mode */ 2038 cbp->bcast_disable = 0; /* (don't) disable broadcasts */ 2039 cbp->wait_after_win = 0; /* (don't) enable modified backoff alg*/ 2040 cbp->ignore_ul = 0; /* consider U/L bit in IA matching */ 2041 cbp->crc16_en = 0; /* (don't) enable crc-16 algorithm */ 2042 cbp->crscdt = sc->flags & FXP_FLAG_SERIAL_MEDIA ? 1 : 0; 2043 2044 cbp->stripping = !prm; /* truncate rx packet to byte count */ 2045 cbp->padding = 1; /* (do) pad short tx packets */ 2046 cbp->rcv_crc_xfer = 0; /* (don't) xfer CRC to host */ 2047 cbp->long_rx_en = sc->flags & FXP_FLAG_LONG_PKT_EN ? 1 : 0; 2048 cbp->ia_wake_en = 0; /* (don't) wake up on address match */ 2049 cbp->magic_pkt_dis = 0; /* (don't) disable magic packet */ 2050 /* must set wake_en in PMCSR also */ 2051 cbp->force_fdx = 0; /* (don't) force full duplex */ 2052 cbp->fdx_pin_en = 1; /* (enable) FDX# pin */ 2053 cbp->multi_ia = 0; /* (don't) accept multiple IAs */ 2054 cbp->mc_all = sc->flags & FXP_FLAG_ALL_MCAST ? 1 : 0; 2055 cbp->gamla_rx = sc->flags & FXP_FLAG_EXT_RFA ? 1 : 0; 2056 2057 if (sc->tunable_noflow || sc->revision == FXP_REV_82557) { 2058 /* 2059 * The 82557 has no hardware flow control, the values 2060 * below are the defaults for the chip. 2061 */ 2062 cbp->fc_delay_lsb = 0; 2063 cbp->fc_delay_msb = 0x40; 2064 cbp->pri_fc_thresh = 3; 2065 cbp->tx_fc_dis = 0; 2066 cbp->rx_fc_restop = 0; 2067 cbp->rx_fc_restart = 0; 2068 cbp->fc_filter = 0; 2069 cbp->pri_fc_loc = 1; 2070 } else { 2071 cbp->fc_delay_lsb = 0x1f; 2072 cbp->fc_delay_msb = 0x01; 2073 cbp->pri_fc_thresh = 3; 2074 cbp->tx_fc_dis = 0; /* enable transmit FC */ 2075 cbp->rx_fc_restop = 1; /* enable FC restop frames */ 2076 cbp->rx_fc_restart = 1; /* enable FC restart frames */ 2077 cbp->fc_filter = !prm; /* drop FC frames to host */ 2078 cbp->pri_fc_loc = 1; /* FC pri location (byte31) */ 2079 } 2080 2081 /* 2082 * Start the config command/DMA. 2083 */ 2084 fxp_scb_wait(sc); 2085 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE); 2086 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->fxp_desc.cbl_addr); 2087 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2088 /* ...and wait for it to complete. */ 2089 fxp_dma_wait(sc, &cbp->cb_status, sc->cbl_tag, sc->cbl_map); 2090 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_POSTWRITE); 2091 2092 /* 2093 * Now initialize the station address. Temporarily use the TxCB 2094 * memory area like we did above for the config CB. 2095 */ 2096 cb_ias = (struct fxp_cb_ias *)sc->fxp_desc.cbl_list; 2097 cb_ias->cb_status = 0; 2098 cb_ias->cb_command = htole16(FXP_CB_COMMAND_IAS | FXP_CB_COMMAND_EL); 2099 cb_ias->link_addr = 0xffffffff; 2100 bcopy(IF_LLADDR(sc->ifp), cb_ias->macaddr, ETHER_ADDR_LEN); 2101 2102 /* 2103 * Start the IAS (Individual Address Setup) command/DMA. 2104 */ 2105 fxp_scb_wait(sc); 2106 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE); 2107 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2108 /* ...and wait for it to complete. */ 2109 fxp_dma_wait(sc, &cb_ias->cb_status, sc->cbl_tag, sc->cbl_map); 2110 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_POSTWRITE); 2111 2112 /* 2113 * Initialize transmit control block (TxCB) list. 2114 */ 2115 txp = sc->fxp_desc.tx_list; 2116 tcbp = sc->fxp_desc.cbl_list; 2117 bzero(tcbp, FXP_TXCB_SZ); 2118 for (i = 0; i < FXP_NTXCB; i++) { 2119 txp[i].tx_mbuf = NULL; 2120 tcbp[i].cb_status = htole16(FXP_CB_STATUS_C | FXP_CB_STATUS_OK); 2121 tcbp[i].cb_command = htole16(FXP_CB_COMMAND_NOP); 2122 tcbp[i].link_addr = htole32(sc->fxp_desc.cbl_addr + 2123 (((i + 1) & FXP_TXCB_MASK) * sizeof(struct fxp_cb_tx))); 2124 if (sc->flags & FXP_FLAG_EXT_TXCB) 2125 tcbp[i].tbd_array_addr = 2126 htole32(FXP_TXCB_DMA_ADDR(sc, &tcbp[i].tbd[2])); 2127 else 2128 tcbp[i].tbd_array_addr = 2129 htole32(FXP_TXCB_DMA_ADDR(sc, &tcbp[i].tbd[0])); 2130 txp[i].tx_next = &txp[(i + 1) & FXP_TXCB_MASK]; 2131 } 2132 /* 2133 * Set the suspend flag on the first TxCB and start the control 2134 * unit. It will execute the NOP and then suspend. 2135 */ 2136 tcbp->cb_command = htole16(FXP_CB_COMMAND_NOP | FXP_CB_COMMAND_S); 2137 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE); 2138 sc->fxp_desc.tx_first = sc->fxp_desc.tx_last = txp; 2139 sc->tx_queued = 1; 2140 2141 fxp_scb_wait(sc); 2142 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2143 2144 /* 2145 * Initialize receiver buffer area - RFA. 2146 */ 2147 fxp_scb_wait(sc); 2148 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->fxp_desc.rx_head->rx_addr); 2149 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_START); 2150 2151 /* 2152 * Set current media. 2153 */ 2154 if (sc->miibus != NULL) 2155 mii_mediachg(device_get_softc(sc->miibus)); 2156 2157 ifp->if_drv_flags |= IFF_DRV_RUNNING; 2158 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 2159 2160 /* 2161 * Enable interrupts. 2162 */ 2163 #ifdef DEVICE_POLLING 2164 /* 2165 * ... but only do that if we are not polling. And because (presumably) 2166 * the default is interrupts on, we need to disable them explicitly! 2167 */ 2168 if (ifp->if_capenable & IFCAP_POLLING ) 2169 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE); 2170 else 2171 #endif /* DEVICE_POLLING */ 2172 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, 0); 2173 2174 /* 2175 * Start stats updater. 2176 */ 2177 callout_reset(&sc->stat_ch, hz, fxp_tick, sc); 2178 } 2179 2180 static int 2181 fxp_serial_ifmedia_upd(struct ifnet *ifp) 2182 { 2183 2184 return (0); 2185 } 2186 2187 static void 2188 fxp_serial_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 2189 { 2190 2191 ifmr->ifm_active = IFM_ETHER|IFM_MANUAL; 2192 } 2193 2194 /* 2195 * Change media according to request. 2196 */ 2197 static int 2198 fxp_ifmedia_upd(struct ifnet *ifp) 2199 { 2200 struct fxp_softc *sc = ifp->if_softc; 2201 struct mii_data *mii; 2202 2203 mii = device_get_softc(sc->miibus); 2204 FXP_LOCK(sc); 2205 if (mii->mii_instance) { 2206 struct mii_softc *miisc; 2207 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 2208 mii_phy_reset(miisc); 2209 } 2210 mii_mediachg(mii); 2211 FXP_UNLOCK(sc); 2212 return (0); 2213 } 2214 2215 /* 2216 * Notify the world which media we're using. 2217 */ 2218 static void 2219 fxp_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 2220 { 2221 struct fxp_softc *sc = ifp->if_softc; 2222 struct mii_data *mii; 2223 2224 mii = device_get_softc(sc->miibus); 2225 FXP_LOCK(sc); 2226 mii_pollstat(mii); 2227 ifmr->ifm_active = mii->mii_media_active; 2228 ifmr->ifm_status = mii->mii_media_status; 2229 2230 if (IFM_SUBTYPE(ifmr->ifm_active) == IFM_10_T && 2231 sc->flags & FXP_FLAG_CU_RESUME_BUG) 2232 sc->cu_resume_bug = 1; 2233 else 2234 sc->cu_resume_bug = 0; 2235 FXP_UNLOCK(sc); 2236 } 2237 2238 /* 2239 * Add a buffer to the end of the RFA buffer list. 2240 * Return 0 if successful, 1 for failure. A failure results in 2241 * adding the 'oldm' (if non-NULL) on to the end of the list - 2242 * tossing out its old contents and recycling it. 2243 * The RFA struct is stuck at the beginning of mbuf cluster and the 2244 * data pointer is fixed up to point just past it. 2245 */ 2246 static int 2247 fxp_add_rfabuf(struct fxp_softc *sc, struct fxp_rx *rxp) 2248 { 2249 struct mbuf *m; 2250 struct fxp_rfa *rfa, *p_rfa; 2251 struct fxp_rx *p_rx; 2252 bus_dmamap_t tmp_map; 2253 int error; 2254 2255 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 2256 if (m == NULL) 2257 return (ENOBUFS); 2258 2259 /* 2260 * Move the data pointer up so that the incoming data packet 2261 * will be 32-bit aligned. 2262 */ 2263 m->m_data += RFA_ALIGNMENT_FUDGE; 2264 2265 /* 2266 * Get a pointer to the base of the mbuf cluster and move 2267 * data start past it. 2268 */ 2269 rfa = mtod(m, struct fxp_rfa *); 2270 m->m_data += sc->rfa_size; 2271 rfa->size = htole16(MCLBYTES - sc->rfa_size - RFA_ALIGNMENT_FUDGE); 2272 2273 rfa->rfa_status = 0; 2274 rfa->rfa_control = htole16(FXP_RFA_CONTROL_EL); 2275 rfa->actual_size = 0; 2276 2277 /* 2278 * Initialize the rest of the RFA. Note that since the RFA 2279 * is misaligned, we cannot store values directly. We're thus 2280 * using the le32enc() function which handles endianness and 2281 * is also alignment-safe. 2282 */ 2283 le32enc(&rfa->link_addr, 0xffffffff); 2284 le32enc(&rfa->rbd_addr, 0xffffffff); 2285 2286 /* Map the RFA into DMA memory. */ 2287 error = bus_dmamap_load(sc->fxp_mtag, sc->spare_map, rfa, 2288 MCLBYTES - RFA_ALIGNMENT_FUDGE, fxp_dma_map_addr, 2289 &rxp->rx_addr, 0); 2290 if (error) { 2291 m_freem(m); 2292 return (error); 2293 } 2294 2295 bus_dmamap_unload(sc->fxp_mtag, rxp->rx_map); 2296 tmp_map = sc->spare_map; 2297 sc->spare_map = rxp->rx_map; 2298 rxp->rx_map = tmp_map; 2299 rxp->rx_mbuf = m; 2300 2301 bus_dmamap_sync(sc->fxp_mtag, rxp->rx_map, 2302 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2303 2304 /* 2305 * If there are other buffers already on the list, attach this 2306 * one to the end by fixing up the tail to point to this one. 2307 */ 2308 if (sc->fxp_desc.rx_head != NULL) { 2309 p_rx = sc->fxp_desc.rx_tail; 2310 p_rfa = (struct fxp_rfa *) 2311 (p_rx->rx_mbuf->m_ext.ext_buf + RFA_ALIGNMENT_FUDGE); 2312 p_rx->rx_next = rxp; 2313 le32enc(&p_rfa->link_addr, rxp->rx_addr); 2314 p_rfa->rfa_control = 0; 2315 bus_dmamap_sync(sc->fxp_mtag, p_rx->rx_map, 2316 BUS_DMASYNC_PREWRITE); 2317 } else { 2318 rxp->rx_next = NULL; 2319 sc->fxp_desc.rx_head = rxp; 2320 } 2321 sc->fxp_desc.rx_tail = rxp; 2322 return (0); 2323 } 2324 2325 static volatile int 2326 fxp_miibus_readreg(device_t dev, int phy, int reg) 2327 { 2328 struct fxp_softc *sc = device_get_softc(dev); 2329 int count = 10000; 2330 int value; 2331 2332 CSR_WRITE_4(sc, FXP_CSR_MDICONTROL, 2333 (FXP_MDI_READ << 26) | (reg << 16) | (phy << 21)); 2334 2335 while (((value = CSR_READ_4(sc, FXP_CSR_MDICONTROL)) & 0x10000000) == 0 2336 && count--) 2337 DELAY(10); 2338 2339 if (count <= 0) 2340 device_printf(dev, "fxp_miibus_readreg: timed out\n"); 2341 2342 return (value & 0xffff); 2343 } 2344 2345 static void 2346 fxp_miibus_writereg(device_t dev, int phy, int reg, int value) 2347 { 2348 struct fxp_softc *sc = device_get_softc(dev); 2349 int count = 10000; 2350 2351 CSR_WRITE_4(sc, FXP_CSR_MDICONTROL, 2352 (FXP_MDI_WRITE << 26) | (reg << 16) | (phy << 21) | 2353 (value & 0xffff)); 2354 2355 while ((CSR_READ_4(sc, FXP_CSR_MDICONTROL) & 0x10000000) == 0 && 2356 count--) 2357 DELAY(10); 2358 2359 if (count <= 0) 2360 device_printf(dev, "fxp_miibus_writereg: timed out\n"); 2361 } 2362 2363 static int 2364 fxp_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 2365 { 2366 struct fxp_softc *sc = ifp->if_softc; 2367 struct ifreq *ifr = (struct ifreq *)data; 2368 struct mii_data *mii; 2369 int flag, mask, error = 0; 2370 2371 switch (command) { 2372 case SIOCSIFFLAGS: 2373 FXP_LOCK(sc); 2374 if (ifp->if_flags & IFF_ALLMULTI) 2375 sc->flags |= FXP_FLAG_ALL_MCAST; 2376 else 2377 sc->flags &= ~FXP_FLAG_ALL_MCAST; 2378 2379 /* 2380 * If interface is marked up and not running, then start it. 2381 * If it is marked down and running, stop it. 2382 * XXX If it's up then re-initialize it. This is so flags 2383 * such as IFF_PROMISC are handled. 2384 */ 2385 if (ifp->if_flags & IFF_UP) { 2386 fxp_init_body(sc); 2387 } else { 2388 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 2389 fxp_stop(sc); 2390 } 2391 FXP_UNLOCK(sc); 2392 break; 2393 2394 case SIOCADDMULTI: 2395 case SIOCDELMULTI: 2396 FXP_LOCK(sc); 2397 if (ifp->if_flags & IFF_ALLMULTI) 2398 sc->flags |= FXP_FLAG_ALL_MCAST; 2399 else 2400 sc->flags &= ~FXP_FLAG_ALL_MCAST; 2401 /* 2402 * Multicast list has changed; set the hardware filter 2403 * accordingly. 2404 */ 2405 if ((sc->flags & FXP_FLAG_ALL_MCAST) == 0) 2406 fxp_mc_setup(sc); 2407 /* 2408 * fxp_mc_setup() can set FXP_FLAG_ALL_MCAST, so check it 2409 * again rather than else {}. 2410 */ 2411 if (sc->flags & FXP_FLAG_ALL_MCAST) 2412 fxp_init_body(sc); 2413 FXP_UNLOCK(sc); 2414 error = 0; 2415 break; 2416 2417 case SIOCSIFMEDIA: 2418 case SIOCGIFMEDIA: 2419 if (sc->miibus != NULL) { 2420 mii = device_get_softc(sc->miibus); 2421 error = ifmedia_ioctl(ifp, ifr, 2422 &mii->mii_media, command); 2423 } else { 2424 error = ifmedia_ioctl(ifp, ifr, &sc->sc_media, command); 2425 } 2426 break; 2427 2428 case SIOCSIFCAP: 2429 mask = ifp->if_capenable ^ ifr->ifr_reqcap; 2430 #ifdef DEVICE_POLLING 2431 if (mask & IFCAP_POLLING) { 2432 if (ifr->ifr_reqcap & IFCAP_POLLING) { 2433 error = ether_poll_register(fxp_poll, ifp); 2434 if (error) 2435 return(error); 2436 FXP_LOCK(sc); 2437 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, 2438 FXP_SCB_INTR_DISABLE); 2439 ifp->if_capenable |= IFCAP_POLLING; 2440 FXP_UNLOCK(sc); 2441 } else { 2442 error = ether_poll_deregister(ifp); 2443 /* Enable interrupts in any case */ 2444 FXP_LOCK(sc); 2445 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, 0); 2446 ifp->if_capenable &= ~IFCAP_POLLING; 2447 FXP_UNLOCK(sc); 2448 } 2449 } 2450 #endif 2451 if (mask & IFCAP_VLAN_MTU) { 2452 FXP_LOCK(sc); 2453 ifp->if_capenable ^= IFCAP_VLAN_MTU; 2454 if (sc->revision != FXP_REV_82557) 2455 flag = FXP_FLAG_LONG_PKT_EN; 2456 else /* a hack to get long frames on the old chip */ 2457 flag = FXP_FLAG_SAVE_BAD; 2458 sc->flags ^= flag; 2459 if (ifp->if_flags & IFF_UP) 2460 fxp_init_body(sc); 2461 FXP_UNLOCK(sc); 2462 } 2463 break; 2464 2465 default: 2466 error = ether_ioctl(ifp, command, data); 2467 } 2468 return (error); 2469 } 2470 2471 /* 2472 * Fill in the multicast address list and return number of entries. 2473 */ 2474 static int 2475 fxp_mc_addrs(struct fxp_softc *sc) 2476 { 2477 struct fxp_cb_mcs *mcsp = sc->mcsp; 2478 struct ifnet *ifp = sc->ifp; 2479 struct ifmultiaddr *ifma; 2480 int nmcasts; 2481 2482 nmcasts = 0; 2483 if ((sc->flags & FXP_FLAG_ALL_MCAST) == 0) { 2484 IF_ADDR_LOCK(ifp); 2485 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 2486 if (ifma->ifma_addr->sa_family != AF_LINK) 2487 continue; 2488 if (nmcasts >= MAXMCADDR) { 2489 sc->flags |= FXP_FLAG_ALL_MCAST; 2490 nmcasts = 0; 2491 break; 2492 } 2493 bcopy(LLADDR((struct sockaddr_dl *)ifma->ifma_addr), 2494 &sc->mcsp->mc_addr[nmcasts][0], ETHER_ADDR_LEN); 2495 nmcasts++; 2496 } 2497 IF_ADDR_UNLOCK(ifp); 2498 } 2499 mcsp->mc_cnt = htole16(nmcasts * ETHER_ADDR_LEN); 2500 return (nmcasts); 2501 } 2502 2503 /* 2504 * Program the multicast filter. 2505 * 2506 * We have an artificial restriction that the multicast setup command 2507 * must be the first command in the chain, so we take steps to ensure 2508 * this. By requiring this, it allows us to keep up the performance of 2509 * the pre-initialized command ring (esp. link pointers) by not actually 2510 * inserting the mcsetup command in the ring - i.e. its link pointer 2511 * points to the TxCB ring, but the mcsetup descriptor itself is not part 2512 * of it. We then can do 'CU_START' on the mcsetup descriptor and have it 2513 * lead into the regular TxCB ring when it completes. 2514 * 2515 * This function must be called at splimp. 2516 */ 2517 static void 2518 fxp_mc_setup(struct fxp_softc *sc) 2519 { 2520 struct fxp_cb_mcs *mcsp = sc->mcsp; 2521 struct fxp_tx *txp; 2522 int count; 2523 2524 FXP_LOCK_ASSERT(sc, MA_OWNED); 2525 /* 2526 * If there are queued commands, we must wait until they are all 2527 * completed. If we are already waiting, then add a NOP command 2528 * with interrupt option so that we're notified when all commands 2529 * have been completed - fxp_start() ensures that no additional 2530 * TX commands will be added when need_mcsetup is true. 2531 */ 2532 if (sc->tx_queued) { 2533 /* 2534 * need_mcsetup will be true if we are already waiting for the 2535 * NOP command to be completed (see below). In this case, bail. 2536 */ 2537 if (sc->need_mcsetup) 2538 return; 2539 sc->need_mcsetup = 1; 2540 2541 /* 2542 * Add a NOP command with interrupt so that we are notified 2543 * when all TX commands have been processed. 2544 */ 2545 txp = sc->fxp_desc.tx_last->tx_next; 2546 txp->tx_mbuf = NULL; 2547 txp->tx_cb->cb_status = 0; 2548 txp->tx_cb->cb_command = htole16(FXP_CB_COMMAND_NOP | 2549 FXP_CB_COMMAND_S | FXP_CB_COMMAND_I); 2550 /* 2551 * Advance the end of list forward. 2552 */ 2553 sc->fxp_desc.tx_last->tx_cb->cb_command &= 2554 htole16(~FXP_CB_COMMAND_S); 2555 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE); 2556 sc->fxp_desc.tx_last = txp; 2557 sc->tx_queued++; 2558 /* 2559 * Issue a resume in case the CU has just suspended. 2560 */ 2561 fxp_scb_wait(sc); 2562 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_RESUME); 2563 /* 2564 * Set a 5 second timer just in case we don't hear from the 2565 * card again. 2566 */ 2567 sc->watchdog_timer = 5; 2568 2569 return; 2570 } 2571 sc->need_mcsetup = 0; 2572 2573 /* 2574 * Initialize multicast setup descriptor. 2575 */ 2576 mcsp->cb_status = 0; 2577 mcsp->cb_command = htole16(FXP_CB_COMMAND_MCAS | 2578 FXP_CB_COMMAND_S | FXP_CB_COMMAND_I); 2579 mcsp->link_addr = htole32(sc->fxp_desc.cbl_addr); 2580 txp = &sc->fxp_desc.mcs_tx; 2581 txp->tx_mbuf = NULL; 2582 txp->tx_cb = (struct fxp_cb_tx *)sc->mcsp; 2583 txp->tx_next = sc->fxp_desc.tx_list; 2584 (void) fxp_mc_addrs(sc); 2585 sc->fxp_desc.tx_first = sc->fxp_desc.tx_last = txp; 2586 sc->tx_queued = 1; 2587 2588 /* 2589 * Wait until command unit is not active. This should never 2590 * be the case when nothing is queued, but make sure anyway. 2591 */ 2592 count = 100; 2593 while ((CSR_READ_1(sc, FXP_CSR_SCB_RUSCUS) >> 6) == 2594 FXP_SCB_CUS_ACTIVE && --count) 2595 DELAY(10); 2596 if (count == 0) { 2597 device_printf(sc->dev, "command queue timeout\n"); 2598 return; 2599 } 2600 2601 /* 2602 * Start the multicast setup command. 2603 */ 2604 fxp_scb_wait(sc); 2605 bus_dmamap_sync(sc->mcs_tag, sc->mcs_map, BUS_DMASYNC_PREWRITE); 2606 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->mcs_addr); 2607 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2608 2609 sc->watchdog_timer = 2; 2610 return; 2611 } 2612 2613 static uint32_t fxp_ucode_d101a[] = D101_A_RCVBUNDLE_UCODE; 2614 static uint32_t fxp_ucode_d101b0[] = D101_B0_RCVBUNDLE_UCODE; 2615 static uint32_t fxp_ucode_d101ma[] = D101M_B_RCVBUNDLE_UCODE; 2616 static uint32_t fxp_ucode_d101s[] = D101S_RCVBUNDLE_UCODE; 2617 static uint32_t fxp_ucode_d102[] = D102_B_RCVBUNDLE_UCODE; 2618 static uint32_t fxp_ucode_d102c[] = D102_C_RCVBUNDLE_UCODE; 2619 static uint32_t fxp_ucode_d102e[] = D102_E_RCVBUNDLE_UCODE; 2620 2621 #define UCODE(x) x, sizeof(x)/sizeof(uint32_t) 2622 2623 struct ucode { 2624 uint32_t revision; 2625 uint32_t *ucode; 2626 int length; 2627 u_short int_delay_offset; 2628 u_short bundle_max_offset; 2629 } ucode_table[] = { 2630 { FXP_REV_82558_A4, UCODE(fxp_ucode_d101a), D101_CPUSAVER_DWORD, 0 }, 2631 { FXP_REV_82558_B0, UCODE(fxp_ucode_d101b0), D101_CPUSAVER_DWORD, 0 }, 2632 { FXP_REV_82559_A0, UCODE(fxp_ucode_d101ma), 2633 D101M_CPUSAVER_DWORD, D101M_CPUSAVER_BUNDLE_MAX_DWORD }, 2634 { FXP_REV_82559S_A, UCODE(fxp_ucode_d101s), 2635 D101S_CPUSAVER_DWORD, D101S_CPUSAVER_BUNDLE_MAX_DWORD }, 2636 { FXP_REV_82550, UCODE(fxp_ucode_d102), 2637 D102_B_CPUSAVER_DWORD, D102_B_CPUSAVER_BUNDLE_MAX_DWORD }, 2638 { FXP_REV_82550_C, UCODE(fxp_ucode_d102c), 2639 D102_C_CPUSAVER_DWORD, D102_C_CPUSAVER_BUNDLE_MAX_DWORD }, 2640 { FXP_REV_82551_F, UCODE(fxp_ucode_d102e), 2641 D102_E_CPUSAVER_DWORD, D102_E_CPUSAVER_BUNDLE_MAX_DWORD }, 2642 { 0, NULL, 0, 0, 0 } 2643 }; 2644 2645 static void 2646 fxp_load_ucode(struct fxp_softc *sc) 2647 { 2648 struct ucode *uc; 2649 struct fxp_cb_ucode *cbp; 2650 int i; 2651 2652 for (uc = ucode_table; uc->ucode != NULL; uc++) 2653 if (sc->revision == uc->revision) 2654 break; 2655 if (uc->ucode == NULL) 2656 return; 2657 cbp = (struct fxp_cb_ucode *)sc->fxp_desc.cbl_list; 2658 cbp->cb_status = 0; 2659 cbp->cb_command = htole16(FXP_CB_COMMAND_UCODE | FXP_CB_COMMAND_EL); 2660 cbp->link_addr = 0xffffffff; /* (no) next command */ 2661 for (i = 0; i < uc->length; i++) 2662 cbp->ucode[i] = htole32(uc->ucode[i]); 2663 if (uc->int_delay_offset) 2664 *(uint16_t *)&cbp->ucode[uc->int_delay_offset] = 2665 htole16(sc->tunable_int_delay + sc->tunable_int_delay / 2); 2666 if (uc->bundle_max_offset) 2667 *(uint16_t *)&cbp->ucode[uc->bundle_max_offset] = 2668 htole16(sc->tunable_bundle_max); 2669 /* 2670 * Download the ucode to the chip. 2671 */ 2672 fxp_scb_wait(sc); 2673 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE); 2674 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->fxp_desc.cbl_addr); 2675 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2676 /* ...and wait for it to complete. */ 2677 fxp_dma_wait(sc, &cbp->cb_status, sc->cbl_tag, sc->cbl_map); 2678 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_POSTWRITE); 2679 device_printf(sc->dev, 2680 "Microcode loaded, int_delay: %d usec bundle_max: %d\n", 2681 sc->tunable_int_delay, 2682 uc->bundle_max_offset == 0 ? 0 : sc->tunable_bundle_max); 2683 sc->flags |= FXP_FLAG_UCODE; 2684 } 2685 2686 static int 2687 sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high) 2688 { 2689 int error, value; 2690 2691 value = *(int *)arg1; 2692 error = sysctl_handle_int(oidp, &value, 0, req); 2693 if (error || !req->newptr) 2694 return (error); 2695 if (value < low || value > high) 2696 return (EINVAL); 2697 *(int *)arg1 = value; 2698 return (0); 2699 } 2700 2701 /* 2702 * Interrupt delay is expressed in microseconds, a multiplier is used 2703 * to convert this to the appropriate clock ticks before using. 2704 */ 2705 static int 2706 sysctl_hw_fxp_int_delay(SYSCTL_HANDLER_ARGS) 2707 { 2708 return (sysctl_int_range(oidp, arg1, arg2, req, 300, 3000)); 2709 } 2710 2711 static int 2712 sysctl_hw_fxp_bundle_max(SYSCTL_HANDLER_ARGS) 2713 { 2714 return (sysctl_int_range(oidp, arg1, arg2, req, 1, 0xffff)); 2715 } 2716