1 /*- 2 * Copyright (c) 1995, David Greenman 3 * Copyright (c) 2001 Jonathan Lemon <jlemon@freebsd.org> 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice unmodified, this list of conditions, and the following 11 * disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 * 28 * $FreeBSD$ 29 */ 30 31 /* 32 * Intel EtherExpress Pro/100B PCI Fast Ethernet driver 33 */ 34 35 #include <sys/param.h> 36 #include <sys/systm.h> 37 #include <sys/mbuf.h> 38 /* #include <sys/mutex.h> */ 39 #include <sys/kernel.h> 40 #include <sys/socket.h> 41 #include <sys/sysctl.h> 42 43 #include <net/if.h> 44 #include <net/if_dl.h> 45 #include <net/if_media.h> 46 47 #include <net/bpf.h> 48 #include <sys/sockio.h> 49 #include <sys/bus.h> 50 #include <machine/bus.h> 51 #include <sys/rman.h> 52 #include <machine/resource.h> 53 54 #include <net/ethernet.h> 55 #include <net/if_arp.h> 56 57 #include <machine/clock.h> /* for DELAY */ 58 59 #include <net/if_types.h> 60 #include <net/if_vlan_var.h> 61 62 #ifdef FXP_IP_CSUM_WAR 63 #include <netinet/in.h> 64 #include <netinet/in_systm.h> 65 #include <netinet/ip.h> 66 #include <machine/in_cksum.h> 67 #endif 68 69 #include <pci/pcivar.h> 70 #include <pci/pcireg.h> /* for PCIM_CMD_xxx */ 71 72 #include <dev/mii/mii.h> 73 #include <dev/mii/miivar.h> 74 75 #include <dev/fxp/if_fxpreg.h> 76 #include <dev/fxp/if_fxpvar.h> 77 #include <dev/fxp/rcvbundl.h> 78 79 MODULE_DEPEND(fxp, miibus, 1, 1, 1); 80 #include "miibus_if.h" 81 82 /* 83 * NOTE! On the Alpha, we have an alignment constraint. The 84 * card DMAs the packet immediately following the RFA. However, 85 * the first thing in the packet is a 14-byte Ethernet header. 86 * This means that the packet is misaligned. To compensate, 87 * we actually offset the RFA 2 bytes into the cluster. This 88 * alignes the packet after the Ethernet header at a 32-bit 89 * boundary. HOWEVER! This means that the RFA is misaligned! 90 */ 91 #define RFA_ALIGNMENT_FUDGE 2 92 93 /* 94 * Set initial transmit threshold at 64 (512 bytes). This is 95 * increased by 64 (512 bytes) at a time, to maximum of 192 96 * (1536 bytes), if an underrun occurs. 97 */ 98 static int tx_threshold = 64; 99 100 /* 101 * The configuration byte map has several undefined fields which 102 * must be one or must be zero. Set up a template for these bits 103 * only, (assuming a 82557 chip) leaving the actual configuration 104 * to fxp_init. 105 * 106 * See struct fxp_cb_config for the bit definitions. 107 */ 108 static u_char fxp_cb_config_template[] = { 109 0x0, 0x0, /* cb_status */ 110 0x0, 0x0, /* cb_command */ 111 0x0, 0x0, 0x0, 0x0, /* link_addr */ 112 0x0, /* 0 */ 113 0x0, /* 1 */ 114 0x0, /* 2 */ 115 0x0, /* 3 */ 116 0x0, /* 4 */ 117 0x0, /* 5 */ 118 0x32, /* 6 */ 119 0x0, /* 7 */ 120 0x0, /* 8 */ 121 0x0, /* 9 */ 122 0x6, /* 10 */ 123 0x0, /* 11 */ 124 0x0, /* 12 */ 125 0x0, /* 13 */ 126 0xf2, /* 14 */ 127 0x48, /* 15 */ 128 0x0, /* 16 */ 129 0x40, /* 17 */ 130 0xf0, /* 18 */ 131 0x0, /* 19 */ 132 0x3f, /* 20 */ 133 0x5 /* 21 */ 134 }; 135 136 struct fxp_ident { 137 u_int16_t devid; 138 char *name; 139 }; 140 141 /* 142 * Claim various Intel PCI device identifiers for this driver. The 143 * sub-vendor and sub-device field are extensively used to identify 144 * particular variants, but we don't currently differentiate between 145 * them. 146 */ 147 static struct fxp_ident fxp_ident_table[] = { 148 { 0x1029, "Intel 82559 PCI/CardBus Pro/100" }, 149 { 0x1030, "Intel 82559 Pro/100 Ethernet" }, 150 { 0x1031, "Intel 82801CAM (ICH3) Pro/100 VE Ethernet" }, 151 { 0x1032, "Intel 82801CAM (ICH3) Pro/100 VE Ethernet" }, 152 { 0x1033, "Intel 82801CAM (ICH3) Pro/100 VM Ethernet" }, 153 { 0x1034, "Intel 82801CAM (ICH3) Pro/100 VM Ethernet" }, 154 { 0x1035, "Intel 82801CAM (ICH3) Pro/100 Ethernet" }, 155 { 0x1036, "Intel 82801CAM (ICH3) Pro/100 Ethernet" }, 156 { 0x1037, "Intel 82801CAM (ICH3) Pro/100 Ethernet" }, 157 { 0x1038, "Intel 82801CAM (ICH3) Pro/100 VM Ethernet" }, 158 { 0x1039, "Intel 82801DB (ICH4) Pro/100 VE Ethernet" }, 159 { 0x103A, "Intel 82801DB (ICH4) Pro/100 Ethernet" }, 160 { 0x103B, "Intel 82801DB (ICH4) Pro/100 VM Ethernet" }, 161 { 0x103C, "Intel 82801DB (ICH4) Pro/100 Ethernet" }, 162 { 0x103D, "Intel 82801DB (ICH4) Pro/100 VE Ethernet" }, 163 { 0x103E, "Intel 82801DB (ICH4) Pro/100 VM Ethernet" }, 164 { 0x1059, "Intel 82551QM Pro/100 M Mobile Connection" }, 165 { 0x1209, "Intel 82559ER Embedded 10/100 Ethernet" }, 166 { 0x1229, "Intel 82557/8/9 EtherExpress Pro/100(B) Ethernet" }, 167 { 0x2449, "Intel 82801BA/CAM (ICH2/3) Pro/100 Ethernet" }, 168 { 0, NULL }, 169 }; 170 171 #ifdef FXP_IP_CSUM_WAR 172 #define FXP_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 173 #else 174 #define FXP_CSUM_FEATURES (CSUM_TCP | CSUM_UDP) 175 #endif 176 177 static int fxp_probe(device_t dev); 178 static int fxp_attach(device_t dev); 179 static int fxp_detach(device_t dev); 180 static int fxp_shutdown(device_t dev); 181 static int fxp_suspend(device_t dev); 182 static int fxp_resume(device_t dev); 183 184 static void fxp_intr(void *xsc); 185 static void fxp_init(void *xsc); 186 static void fxp_tick(void *xsc); 187 static void fxp_powerstate_d0(device_t dev); 188 static void fxp_start(struct ifnet *ifp); 189 static void fxp_stop(struct fxp_softc *sc); 190 static void fxp_release(struct fxp_softc *sc); 191 static int fxp_ioctl(struct ifnet *ifp, u_long command, 192 caddr_t data); 193 static void fxp_watchdog(struct ifnet *ifp); 194 static int fxp_add_rfabuf(struct fxp_softc *sc, 195 struct fxp_rx *rxp); 196 static int fxp_mc_addrs(struct fxp_softc *sc); 197 static void fxp_mc_setup(struct fxp_softc *sc); 198 static u_int16_t fxp_eeprom_getword(struct fxp_softc *sc, int offset, 199 int autosize); 200 static void fxp_eeprom_putword(struct fxp_softc *sc, int offset, 201 u_int16_t data); 202 static void fxp_autosize_eeprom(struct fxp_softc *sc); 203 static void fxp_read_eeprom(struct fxp_softc *sc, u_short *data, 204 int offset, int words); 205 static void fxp_write_eeprom(struct fxp_softc *sc, u_short *data, 206 int offset, int words); 207 static int fxp_ifmedia_upd(struct ifnet *ifp); 208 static void fxp_ifmedia_sts(struct ifnet *ifp, 209 struct ifmediareq *ifmr); 210 static int fxp_serial_ifmedia_upd(struct ifnet *ifp); 211 static void fxp_serial_ifmedia_sts(struct ifnet *ifp, 212 struct ifmediareq *ifmr); 213 static volatile int fxp_miibus_readreg(device_t dev, int phy, int reg); 214 static void fxp_miibus_writereg(device_t dev, int phy, int reg, 215 int value); 216 static void fxp_load_ucode(struct fxp_softc *sc); 217 static int sysctl_int_range(SYSCTL_HANDLER_ARGS, 218 int low, int high); 219 static int sysctl_hw_fxp_bundle_max(SYSCTL_HANDLER_ARGS); 220 static int sysctl_hw_fxp_int_delay(SYSCTL_HANDLER_ARGS); 221 static __inline void fxp_lwcopy(volatile u_int32_t *src, 222 volatile u_int32_t *dst); 223 static __inline void fxp_scb_wait(struct fxp_softc *sc); 224 static __inline void fxp_scb_cmd(struct fxp_softc *sc, int cmd); 225 static __inline void fxp_dma_wait(volatile u_int16_t *status, 226 struct fxp_softc *sc); 227 228 static device_method_t fxp_methods[] = { 229 /* Device interface */ 230 DEVMETHOD(device_probe, fxp_probe), 231 DEVMETHOD(device_attach, fxp_attach), 232 DEVMETHOD(device_detach, fxp_detach), 233 DEVMETHOD(device_shutdown, fxp_shutdown), 234 DEVMETHOD(device_suspend, fxp_suspend), 235 DEVMETHOD(device_resume, fxp_resume), 236 237 /* MII interface */ 238 DEVMETHOD(miibus_readreg, fxp_miibus_readreg), 239 DEVMETHOD(miibus_writereg, fxp_miibus_writereg), 240 241 { 0, 0 } 242 }; 243 244 static driver_t fxp_driver = { 245 "fxp", 246 fxp_methods, 247 sizeof(struct fxp_softc), 248 }; 249 250 static devclass_t fxp_devclass; 251 252 DRIVER_MODULE(if_fxp, pci, fxp_driver, fxp_devclass, 0, 0); 253 DRIVER_MODULE(if_fxp, cardbus, fxp_driver, fxp_devclass, 0, 0); 254 DRIVER_MODULE(miibus, fxp, miibus_driver, miibus_devclass, 0, 0); 255 256 static int fxp_rnr; 257 SYSCTL_INT(_hw, OID_AUTO, fxp_rnr, CTLFLAG_RW, &fxp_rnr, 0, "fxp rnr events"); 258 259 /* 260 * Inline function to copy a 16-bit aligned 32-bit quantity. 261 */ 262 static __inline void 263 fxp_lwcopy(volatile u_int32_t *src, volatile u_int32_t *dst) 264 { 265 #ifdef __i386__ 266 *dst = *src; 267 #else 268 volatile u_int16_t *a = (volatile u_int16_t *)src; 269 volatile u_int16_t *b = (volatile u_int16_t *)dst; 270 271 b[0] = a[0]; 272 b[1] = a[1]; 273 #endif 274 } 275 276 /* 277 * Wait for the previous command to be accepted (but not necessarily 278 * completed). 279 */ 280 static __inline void 281 fxp_scb_wait(struct fxp_softc *sc) 282 { 283 int i = 10000; 284 285 while (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) && --i) 286 DELAY(2); 287 if (i == 0) 288 device_printf(sc->dev, "SCB timeout: 0x%x 0x%x 0x%x 0x%x\n", 289 CSR_READ_1(sc, FXP_CSR_SCB_COMMAND), 290 CSR_READ_1(sc, FXP_CSR_SCB_STATACK), 291 CSR_READ_1(sc, FXP_CSR_SCB_RUSCUS), 292 CSR_READ_2(sc, FXP_CSR_FLOWCONTROL)); 293 } 294 295 static __inline void 296 fxp_scb_cmd(struct fxp_softc *sc, int cmd) 297 { 298 299 if (cmd == FXP_SCB_COMMAND_CU_RESUME && sc->cu_resume_bug) { 300 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_CB_COMMAND_NOP); 301 fxp_scb_wait(sc); 302 } 303 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, cmd); 304 } 305 306 static __inline void 307 fxp_dma_wait(volatile u_int16_t *status, struct fxp_softc *sc) 308 { 309 int i = 10000; 310 311 while (!(*status & FXP_CB_STATUS_C) && --i) 312 DELAY(2); 313 if (i == 0) 314 device_printf(sc->dev, "DMA timeout\n"); 315 } 316 317 /* 318 * Return identification string if this is device is ours. 319 */ 320 static int 321 fxp_probe(device_t dev) 322 { 323 u_int16_t devid; 324 struct fxp_ident *ident; 325 326 if (pci_get_vendor(dev) == FXP_VENDORID_INTEL) { 327 devid = pci_get_device(dev); 328 for (ident = fxp_ident_table; ident->name != NULL; ident++) { 329 if (ident->devid == devid) { 330 device_set_desc(dev, ident->name); 331 return (0); 332 } 333 } 334 } 335 return (ENXIO); 336 } 337 338 static void 339 fxp_powerstate_d0(device_t dev) 340 { 341 #if __FreeBSD_version >= 430002 342 u_int32_t iobase, membase, irq; 343 344 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 345 /* Save important PCI config data. */ 346 iobase = pci_read_config(dev, FXP_PCI_IOBA, 4); 347 membase = pci_read_config(dev, FXP_PCI_MMBA, 4); 348 irq = pci_read_config(dev, PCIR_INTLINE, 4); 349 350 /* Reset the power state. */ 351 device_printf(dev, "chip is in D%d power mode " 352 "-- setting to D0\n", pci_get_powerstate(dev)); 353 354 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 355 356 /* Restore PCI config data. */ 357 pci_write_config(dev, FXP_PCI_IOBA, iobase, 4); 358 pci_write_config(dev, FXP_PCI_MMBA, membase, 4); 359 pci_write_config(dev, PCIR_INTLINE, irq, 4); 360 } 361 #endif 362 } 363 364 static void 365 fxp_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error) 366 { 367 u_int32_t *addr; 368 369 if (error) 370 return; 371 372 KASSERT(nseg == 1, ("too many DMA segments, %d should be 1", nseg)); 373 addr = arg; 374 *addr = segs->ds_addr; 375 } 376 377 static int 378 fxp_attach(device_t dev) 379 { 380 int error = 0; 381 struct fxp_softc *sc = device_get_softc(dev); 382 struct ifnet *ifp; 383 struct fxp_rx *rxp; 384 u_int32_t val; 385 u_int16_t data; 386 int i, rid, m1, m2, prefer_iomap; 387 int s; 388 389 bzero(sc, sizeof(*sc)); 390 sc->dev = dev; 391 callout_handle_init(&sc->stat_ch); 392 sysctl_ctx_init(&sc->sysctl_ctx); 393 mtx_init(&sc->sc_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 394 MTX_DEF | MTX_RECURSE); 395 396 s = splimp(); 397 398 /* 399 * Enable bus mastering. Enable memory space too, in case 400 * BIOS/Prom forgot about it. 401 */ 402 val = pci_read_config(dev, PCIR_COMMAND, 2); 403 val |= (PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN); 404 pci_write_config(dev, PCIR_COMMAND, val, 2); 405 val = pci_read_config(dev, PCIR_COMMAND, 2); 406 407 fxp_powerstate_d0(dev); 408 409 /* 410 * Figure out which we should try first - memory mapping or i/o mapping? 411 * We default to memory mapping. Then we accept an override from the 412 * command line. Then we check to see which one is enabled. 413 */ 414 m1 = PCIM_CMD_MEMEN; 415 m2 = PCIM_CMD_PORTEN; 416 prefer_iomap = 0; 417 if (resource_int_value(device_get_name(dev), device_get_unit(dev), 418 "prefer_iomap", &prefer_iomap) == 0 && prefer_iomap != 0) { 419 m1 = PCIM_CMD_PORTEN; 420 m2 = PCIM_CMD_MEMEN; 421 } 422 423 if (val & m1) { 424 sc->rtp = 425 (m1 == PCIM_CMD_MEMEN)? SYS_RES_MEMORY : SYS_RES_IOPORT; 426 sc->rgd = (m1 == PCIM_CMD_MEMEN)? FXP_PCI_MMBA : FXP_PCI_IOBA; 427 sc->mem = bus_alloc_resource(dev, sc->rtp, &sc->rgd, 428 0, ~0, 1, RF_ACTIVE); 429 } 430 if (sc->mem == NULL && (val & m2)) { 431 sc->rtp = 432 (m2 == PCIM_CMD_MEMEN)? SYS_RES_MEMORY : SYS_RES_IOPORT; 433 sc->rgd = (m2 == PCIM_CMD_MEMEN)? FXP_PCI_MMBA : FXP_PCI_IOBA; 434 sc->mem = bus_alloc_resource(dev, sc->rtp, &sc->rgd, 435 0, ~0, 1, RF_ACTIVE); 436 } 437 438 if (!sc->mem) { 439 device_printf(dev, "could not map device registers\n"); 440 error = ENXIO; 441 goto fail; 442 } 443 if (bootverbose) { 444 device_printf(dev, "using %s space register mapping\n", 445 sc->rtp == SYS_RES_MEMORY? "memory" : "I/O"); 446 } 447 448 sc->sc_st = rman_get_bustag(sc->mem); 449 sc->sc_sh = rman_get_bushandle(sc->mem); 450 451 /* 452 * Allocate our interrupt. 453 */ 454 rid = 0; 455 sc->irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 456 RF_SHAREABLE | RF_ACTIVE); 457 if (sc->irq == NULL) { 458 device_printf(dev, "could not map interrupt\n"); 459 error = ENXIO; 460 goto fail; 461 } 462 463 /* 464 * Reset to a stable state. 465 */ 466 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET); 467 DELAY(10); 468 469 /* 470 * Find out how large of an SEEPROM we have. 471 */ 472 fxp_autosize_eeprom(sc); 473 474 /* 475 * Determine whether we must use the 503 serial interface. 476 */ 477 fxp_read_eeprom(sc, &data, 6, 1); 478 if ((data & FXP_PHY_DEVICE_MASK) != 0 && 479 (data & FXP_PHY_SERIAL_ONLY)) 480 sc->flags |= FXP_FLAG_SERIAL_MEDIA; 481 482 /* 483 * Create the sysctl tree 484 */ 485 sc->sysctl_tree = SYSCTL_ADD_NODE(&sc->sysctl_ctx, 486 SYSCTL_STATIC_CHILDREN(_hw), OID_AUTO, 487 device_get_nameunit(dev), CTLFLAG_RD, 0, ""); 488 if (sc->sysctl_tree == NULL) 489 goto fail; 490 SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree), 491 OID_AUTO, "int_delay", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_PRISON, 492 &sc->tunable_int_delay, 0, sysctl_hw_fxp_int_delay, "I", 493 "FXP driver receive interrupt microcode bundling delay"); 494 SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree), 495 OID_AUTO, "bundle_max", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_PRISON, 496 &sc->tunable_bundle_max, 0, sysctl_hw_fxp_bundle_max, "I", 497 "FXP driver receive interrupt microcode bundle size limit"); 498 499 /* 500 * Pull in device tunables. 501 */ 502 sc->tunable_int_delay = TUNABLE_INT_DELAY; 503 sc->tunable_bundle_max = TUNABLE_BUNDLE_MAX; 504 (void) resource_int_value(device_get_name(dev), device_get_unit(dev), 505 "int_delay", &sc->tunable_int_delay); 506 (void) resource_int_value(device_get_name(dev), device_get_unit(dev), 507 "bundle_max", &sc->tunable_bundle_max); 508 509 /* 510 * Find out the chip revision; lump all 82557 revs together. 511 */ 512 fxp_read_eeprom(sc, &data, 5, 1); 513 if ((data >> 8) == 1) 514 sc->revision = FXP_REV_82557; 515 else 516 sc->revision = pci_get_revid(dev); 517 518 /* 519 * Enable workarounds for certain chip revision deficiencies. 520 * 521 * Systems based on the ICH2/ICH2-M chip from Intel, and possibly 522 * some systems based a normal 82559 design, have a defect where 523 * the chip can cause a PCI protocol violation if it receives 524 * a CU_RESUME command when it is entering the IDLE state. The 525 * workaround is to disable Dynamic Standby Mode, so the chip never 526 * deasserts CLKRUN#, and always remains in an active state. 527 * 528 * See Intel 82801BA/82801BAM Specification Update, Errata #30. 529 */ 530 i = pci_get_device(dev); 531 if (i == 0x2449 || (i > 0x1030 && i < 0x1039) || 532 sc->revision >= FXP_REV_82559_A0) { 533 fxp_read_eeprom(sc, &data, 10, 1); 534 if (data & 0x02) { /* STB enable */ 535 u_int16_t cksum; 536 int i; 537 538 device_printf(dev, 539 "Disabling dynamic standby mode in EEPROM\n"); 540 data &= ~0x02; 541 fxp_write_eeprom(sc, &data, 10, 1); 542 device_printf(dev, "New EEPROM ID: 0x%x\n", data); 543 cksum = 0; 544 for (i = 0; i < (1 << sc->eeprom_size) - 1; i++) { 545 fxp_read_eeprom(sc, &data, i, 1); 546 cksum += data; 547 } 548 i = (1 << sc->eeprom_size) - 1; 549 cksum = 0xBABA - cksum; 550 fxp_read_eeprom(sc, &data, i, 1); 551 fxp_write_eeprom(sc, &cksum, i, 1); 552 device_printf(dev, 553 "EEPROM checksum @ 0x%x: 0x%x -> 0x%x\n", 554 i, data, cksum); 555 #if 1 556 /* 557 * If the user elects to continue, try the software 558 * workaround, as it is better than nothing. 559 */ 560 sc->flags |= FXP_FLAG_CU_RESUME_BUG; 561 #endif 562 } 563 } 564 565 /* 566 * If we are not a 82557 chip, we can enable extended features. 567 */ 568 if (sc->revision != FXP_REV_82557) { 569 /* 570 * If MWI is enabled in the PCI configuration, and there 571 * is a valid cacheline size (8 or 16 dwords), then tell 572 * the board to turn on MWI. 573 */ 574 if (val & PCIM_CMD_MWRICEN && 575 pci_read_config(dev, PCIR_CACHELNSZ, 1) != 0) 576 sc->flags |= FXP_FLAG_MWI_ENABLE; 577 578 /* turn on the extended TxCB feature */ 579 sc->flags |= FXP_FLAG_EXT_TXCB; 580 581 /* enable reception of long frames for VLAN */ 582 sc->flags |= FXP_FLAG_LONG_PKT_EN; 583 } 584 585 /* 586 * Enable use of extended RFDs and TCBs for 82550 587 * and later chips. Note: we need extended TXCB support 588 * too, but that's already enabled by the code above. 589 * Be careful to do this only on the right devices. 590 */ 591 592 if (sc->revision == FXP_REV_82550 || sc->revision == FXP_REV_82550_C) { 593 sc->rfa_size = sizeof (struct fxp_rfa); 594 sc->tx_cmd = FXP_CB_COMMAND_IPCBXMIT; 595 sc->flags |= FXP_FLAG_EXT_RFA; 596 } else { 597 sc->rfa_size = sizeof (struct fxp_rfa) - FXP_RFAX_LEN; 598 sc->tx_cmd = FXP_CB_COMMAND_XMIT; 599 } 600 601 /* 602 * Allocate DMA tags and DMA safe memory. 603 */ 604 error = bus_dma_tag_create(NULL, 2, 0, BUS_SPACE_MAXADDR_32BIT, 605 BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES, 606 sc->flags & FXP_FLAG_EXT_RFA ? FXP_NTXSEG - 1 : FXP_NTXSEG, 607 BUS_SPACE_MAXSIZE_32BIT, 0, &sc->fxp_mtag); 608 if (error) { 609 device_printf(dev, "could not allocate dma tag\n"); 610 goto fail; 611 } 612 613 error = bus_dma_tag_create(NULL, 4, 0, BUS_SPACE_MAXADDR_32BIT, 614 BUS_SPACE_MAXADDR, NULL, NULL, sizeof(struct fxp_stats), 1, 615 BUS_SPACE_MAXSIZE_32BIT, 0, &sc->fxp_stag); 616 if (error) { 617 device_printf(dev, "could not allocate dma tag\n"); 618 goto fail; 619 } 620 621 error = bus_dmamem_alloc(sc->fxp_stag, (void **)&sc->fxp_stats, 622 BUS_DMA_NOWAIT, &sc->fxp_smap); 623 if (error) 624 goto failmem; 625 error = bus_dmamap_load(sc->fxp_stag, sc->fxp_smap, sc->fxp_stats, 626 sizeof(struct fxp_stats), fxp_dma_map_addr, &sc->stats_addr, 0); 627 if (error) { 628 device_printf(dev, "could not map the stats buffer\n"); 629 goto fail; 630 } 631 bzero(sc->fxp_stats, sizeof(struct fxp_stats)); 632 633 error = bus_dma_tag_create(NULL, 4, 0, BUS_SPACE_MAXADDR_32BIT, 634 BUS_SPACE_MAXADDR, NULL, NULL, FXP_TXCB_SZ, 1, 635 BUS_SPACE_MAXSIZE_32BIT, 0, &sc->cbl_tag); 636 if (error) { 637 device_printf(dev, "could not allocate dma tag\n"); 638 goto fail; 639 } 640 641 error = bus_dmamem_alloc(sc->cbl_tag, (void **)&sc->fxp_desc.cbl_list, 642 BUS_DMA_NOWAIT, &sc->cbl_map); 643 if (error) 644 goto failmem; 645 bzero(sc->fxp_desc.cbl_list, FXP_TXCB_SZ); 646 647 error = bus_dmamap_load(sc->cbl_tag, sc->cbl_map, 648 sc->fxp_desc.cbl_list, FXP_TXCB_SZ, fxp_dma_map_addr, 649 &sc->fxp_desc.cbl_addr, 0); 650 if (error) { 651 device_printf(dev, "could not map DMA memory\n"); 652 goto fail; 653 } 654 655 error = bus_dma_tag_create(NULL, 4, 0, BUS_SPACE_MAXADDR_32BIT, 656 BUS_SPACE_MAXADDR, NULL, NULL, sizeof(struct fxp_cb_mcs), 1, 657 BUS_SPACE_MAXSIZE_32BIT, 0, &sc->mcs_tag); 658 if (error) { 659 device_printf(dev, "could not allocate dma tag\n"); 660 goto fail; 661 } 662 663 error = bus_dmamem_alloc(sc->mcs_tag, (void **)&sc->mcsp, 664 BUS_DMA_NOWAIT, &sc->mcs_map); 665 if (error) 666 goto failmem; 667 error = bus_dmamap_load(sc->mcs_tag, sc->mcs_map, sc->mcsp, 668 sizeof(struct fxp_cb_mcs), fxp_dma_map_addr, &sc->mcs_addr, 0); 669 if (error) { 670 device_printf(dev, "can't map the multicast setup command\n"); 671 goto fail; 672 } 673 674 /* 675 * Pre-allocate the TX DMA maps. 676 */ 677 for (i = 0; i < FXP_NTXCB; i++) { 678 error = bus_dmamap_create(sc->fxp_mtag, 0, 679 &sc->fxp_desc.tx_list[i].tx_map); 680 if (error) { 681 device_printf(dev, "can't create DMA map for TX\n"); 682 goto fail; 683 } 684 } 685 error = bus_dmamap_create(sc->fxp_mtag, 0, &sc->spare_map); 686 if (error) { 687 device_printf(dev, "can't create spare DMA map\n"); 688 goto fail; 689 } 690 691 /* 692 * Pre-allocate our receive buffers. 693 */ 694 sc->fxp_desc.rx_head = sc->fxp_desc.rx_tail = NULL; 695 for (i = 0; i < FXP_NRFABUFS; i++) { 696 rxp = &sc->fxp_desc.rx_list[i]; 697 error = bus_dmamap_create(sc->fxp_mtag, 0, &rxp->rx_map); 698 if (error) { 699 device_printf(dev, "can't create DMA map for RX\n"); 700 goto fail; 701 } 702 if (fxp_add_rfabuf(sc, rxp) != 0) 703 goto failmem; 704 } 705 706 /* 707 * Read MAC address. 708 */ 709 fxp_read_eeprom(sc, (u_int16_t *)sc->arpcom.ac_enaddr, 0, 3); 710 device_printf(dev, "Ethernet address %6D%s\n", 711 sc->arpcom.ac_enaddr, ":", 712 sc->flags & FXP_FLAG_SERIAL_MEDIA ? ", 10Mbps" : ""); 713 if (bootverbose) { 714 device_printf(dev, "PCI IDs: %04x %04x %04x %04x %04x\n", 715 pci_get_vendor(dev), pci_get_device(dev), 716 pci_get_subvendor(dev), pci_get_subdevice(dev), 717 pci_get_revid(dev)); 718 fxp_read_eeprom(sc, &data, 10, 1); 719 device_printf(dev, "Dynamic Standby mode is %s\n", 720 data & 0x02 ? "enabled" : "disabled"); 721 } 722 723 /* 724 * If this is only a 10Mbps device, then there is no MII, and 725 * the PHY will use a serial interface instead. 726 * 727 * The Seeq 80c24 AutoDUPLEX(tm) Ethernet Interface Adapter 728 * doesn't have a programming interface of any sort. The 729 * media is sensed automatically based on how the link partner 730 * is configured. This is, in essence, manual configuration. 731 */ 732 if (sc->flags & FXP_FLAG_SERIAL_MEDIA) { 733 ifmedia_init(&sc->sc_media, 0, fxp_serial_ifmedia_upd, 734 fxp_serial_ifmedia_sts); 735 ifmedia_add(&sc->sc_media, IFM_ETHER|IFM_MANUAL, 0, NULL); 736 ifmedia_set(&sc->sc_media, IFM_ETHER|IFM_MANUAL); 737 } else { 738 if (mii_phy_probe(dev, &sc->miibus, fxp_ifmedia_upd, 739 fxp_ifmedia_sts)) { 740 device_printf(dev, "MII without any PHY!\n"); 741 error = ENXIO; 742 goto fail; 743 } 744 } 745 746 ifp = &sc->arpcom.ac_if; 747 ifp->if_unit = device_get_unit(dev); 748 ifp->if_name = "fxp"; 749 ifp->if_output = ether_output; 750 ifp->if_baudrate = 100000000; 751 ifp->if_init = fxp_init; 752 ifp->if_softc = sc; 753 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 754 ifp->if_ioctl = fxp_ioctl; 755 ifp->if_start = fxp_start; 756 ifp->if_watchdog = fxp_watchdog; 757 758 /* Enable checksum offload for 82550 or better chips */ 759 760 if (sc->flags & FXP_FLAG_EXT_RFA) { 761 ifp->if_hwassist = FXP_CSUM_FEATURES; 762 ifp->if_capabilities = IFCAP_HWCSUM; 763 ifp->if_capenable = ifp->if_capabilities; 764 } 765 766 /* 767 * Tell the upper layer(s) we support long frames. 768 */ 769 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 770 ifp->if_capabilities |= IFCAP_VLAN_MTU; 771 772 /* 773 * Let the system queue as many packets as we have available 774 * TX descriptors. 775 */ 776 ifp->if_snd.ifq_maxlen = FXP_NTXCB - 1; 777 778 /* 779 * Attach the interface. 780 */ 781 ether_ifattach(ifp, sc->arpcom.ac_enaddr); 782 783 error = bus_setup_intr(dev, sc->irq, INTR_TYPE_NET, 784 fxp_intr, sc, &sc->ih); 785 if (error) { 786 device_printf(dev, "could not setup irq\n"); 787 goto fail; 788 } 789 790 splx(s); 791 return (0); 792 793 failmem: 794 device_printf(dev, "Failed to malloc memory\n"); 795 error = ENOMEM; 796 fail: 797 splx(s); 798 fxp_release(sc); 799 return (error); 800 } 801 802 /* 803 * release all resources 804 */ 805 static void 806 fxp_release(struct fxp_softc *sc) 807 { 808 struct fxp_rx *rxp; 809 struct fxp_tx *txp; 810 int i; 811 812 for (i = 0; i < FXP_NRFABUFS; i++) { 813 rxp = &sc->fxp_desc.rx_list[i]; 814 if (rxp->rx_mbuf != NULL) { 815 bus_dmamap_sync(sc->fxp_mtag, rxp->rx_map, 816 BUS_DMASYNC_POSTREAD); 817 bus_dmamap_unload(sc->fxp_mtag, rxp->rx_map); 818 m_freem(rxp->rx_mbuf); 819 } 820 bus_dmamap_destroy(sc->fxp_mtag, rxp->rx_map); 821 } 822 bus_dmamap_destroy(sc->fxp_mtag, sc->spare_map); 823 824 for (i = 0; i < FXP_NTXCB; i++) { 825 txp = &sc->fxp_desc.tx_list[i]; 826 if (txp->tx_mbuf != NULL) { 827 bus_dmamap_sync(sc->fxp_mtag, txp->tx_map, 828 BUS_DMASYNC_POSTWRITE); 829 bus_dmamap_unload(sc->fxp_mtag, txp->tx_map); 830 m_freem(txp->tx_mbuf); 831 } 832 bus_dmamap_destroy(sc->fxp_mtag, txp->tx_map); 833 } 834 835 bus_generic_detach(sc->dev); 836 if (sc->miibus) 837 device_delete_child(sc->dev, sc->miibus); 838 839 if (sc->fxp_desc.cbl_list) { 840 bus_dmamap_unload(sc->cbl_tag, sc->cbl_map); 841 bus_dmamem_free(sc->cbl_tag, sc->fxp_desc.cbl_list, 842 sc->cbl_map); 843 } 844 if (sc->fxp_stats) { 845 bus_dmamap_unload(sc->fxp_stag, sc->fxp_smap); 846 bus_dmamem_free(sc->fxp_stag, sc->fxp_stats, sc->fxp_smap); 847 } 848 if (sc->mcsp) { 849 bus_dmamap_unload(sc->mcs_tag, sc->mcs_map); 850 bus_dmamem_free(sc->mcs_tag, sc->mcsp, sc->mcs_map); 851 } 852 if (sc->ih) 853 bus_teardown_intr(sc->dev, sc->irq, sc->ih); 854 if (sc->irq) 855 bus_release_resource(sc->dev, SYS_RES_IRQ, 0, sc->irq); 856 if (sc->mem) 857 bus_release_resource(sc->dev, sc->rtp, sc->rgd, sc->mem); 858 if (sc->fxp_mtag) 859 bus_dma_tag_destroy(sc->fxp_mtag); 860 if (sc->fxp_stag) 861 bus_dma_tag_destroy(sc->fxp_stag); 862 if (sc->cbl_tag) 863 bus_dma_tag_destroy(sc->cbl_tag); 864 if (sc->mcs_tag) 865 bus_dma_tag_destroy(sc->mcs_tag); 866 867 sysctl_ctx_free(&sc->sysctl_ctx); 868 869 mtx_destroy(&sc->sc_mtx); 870 } 871 872 /* 873 * Detach interface. 874 */ 875 static int 876 fxp_detach(device_t dev) 877 { 878 struct fxp_softc *sc = device_get_softc(dev); 879 int s; 880 881 /* disable interrupts */ 882 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE); 883 884 s = splimp(); 885 886 /* 887 * Stop DMA and drop transmit queue. 888 */ 889 fxp_stop(sc); 890 891 /* 892 * Close down routes etc. 893 */ 894 ether_ifdetach(&sc->arpcom.ac_if); 895 896 /* 897 * Free all media structures. 898 */ 899 ifmedia_removeall(&sc->sc_media); 900 901 splx(s); 902 903 /* Release our allocated resources. */ 904 fxp_release(sc); 905 906 return (0); 907 } 908 909 /* 910 * Device shutdown routine. Called at system shutdown after sync. The 911 * main purpose of this routine is to shut off receiver DMA so that 912 * kernel memory doesn't get clobbered during warmboot. 913 */ 914 static int 915 fxp_shutdown(device_t dev) 916 { 917 /* 918 * Make sure that DMA is disabled prior to reboot. Not doing 919 * do could allow DMA to corrupt kernel memory during the 920 * reboot before the driver initializes. 921 */ 922 fxp_stop((struct fxp_softc *) device_get_softc(dev)); 923 return (0); 924 } 925 926 /* 927 * Device suspend routine. Stop the interface and save some PCI 928 * settings in case the BIOS doesn't restore them properly on 929 * resume. 930 */ 931 static int 932 fxp_suspend(device_t dev) 933 { 934 struct fxp_softc *sc = device_get_softc(dev); 935 int i, s; 936 937 s = splimp(); 938 939 fxp_stop(sc); 940 941 for (i = 0; i < 5; i++) 942 sc->saved_maps[i] = pci_read_config(dev, PCIR_MAPS + i * 4, 4); 943 sc->saved_biosaddr = pci_read_config(dev, PCIR_BIOS, 4); 944 sc->saved_intline = pci_read_config(dev, PCIR_INTLINE, 1); 945 sc->saved_cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1); 946 sc->saved_lattimer = pci_read_config(dev, PCIR_LATTIMER, 1); 947 948 sc->suspended = 1; 949 950 splx(s); 951 return (0); 952 } 953 954 /* 955 * Device resume routine. Restore some PCI settings in case the BIOS 956 * doesn't, re-enable busmastering, and restart the interface if 957 * appropriate. 958 */ 959 static int 960 fxp_resume(device_t dev) 961 { 962 struct fxp_softc *sc = device_get_softc(dev); 963 struct ifnet *ifp = &sc->sc_if; 964 u_int16_t pci_command; 965 int i, s; 966 967 s = splimp(); 968 969 fxp_powerstate_d0(dev); 970 971 /* better way to do this? */ 972 for (i = 0; i < 5; i++) 973 pci_write_config(dev, PCIR_MAPS + i * 4, sc->saved_maps[i], 4); 974 pci_write_config(dev, PCIR_BIOS, sc->saved_biosaddr, 4); 975 pci_write_config(dev, PCIR_INTLINE, sc->saved_intline, 1); 976 pci_write_config(dev, PCIR_CACHELNSZ, sc->saved_cachelnsz, 1); 977 pci_write_config(dev, PCIR_LATTIMER, sc->saved_lattimer, 1); 978 979 /* reenable busmastering */ 980 pci_command = pci_read_config(dev, PCIR_COMMAND, 2); 981 pci_command |= (PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN); 982 pci_write_config(dev, PCIR_COMMAND, pci_command, 2); 983 984 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET); 985 DELAY(10); 986 987 /* reinitialize interface if necessary */ 988 if (ifp->if_flags & IFF_UP) 989 fxp_init(sc); 990 991 sc->suspended = 0; 992 993 splx(s); 994 return (0); 995 } 996 997 static void 998 fxp_eeprom_shiftin(struct fxp_softc *sc, int data, int length) 999 { 1000 u_int16_t reg; 1001 int x; 1002 1003 /* 1004 * Shift in data. 1005 */ 1006 for (x = 1 << (length - 1); x; x >>= 1) { 1007 if (data & x) 1008 reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI; 1009 else 1010 reg = FXP_EEPROM_EECS; 1011 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 1012 DELAY(1); 1013 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK); 1014 DELAY(1); 1015 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 1016 DELAY(1); 1017 } 1018 } 1019 1020 /* 1021 * Read from the serial EEPROM. Basically, you manually shift in 1022 * the read opcode (one bit at a time) and then shift in the address, 1023 * and then you shift out the data (all of this one bit at a time). 1024 * The word size is 16 bits, so you have to provide the address for 1025 * every 16 bits of data. 1026 */ 1027 static u_int16_t 1028 fxp_eeprom_getword(struct fxp_softc *sc, int offset, int autosize) 1029 { 1030 u_int16_t reg, data; 1031 int x; 1032 1033 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 1034 /* 1035 * Shift in read opcode. 1036 */ 1037 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_READ, 3); 1038 /* 1039 * Shift in address. 1040 */ 1041 data = 0; 1042 for (x = 1 << (sc->eeprom_size - 1); x; x >>= 1) { 1043 if (offset & x) 1044 reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI; 1045 else 1046 reg = FXP_EEPROM_EECS; 1047 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 1048 DELAY(1); 1049 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK); 1050 DELAY(1); 1051 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 1052 DELAY(1); 1053 reg = CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO; 1054 data++; 1055 if (autosize && reg == 0) { 1056 sc->eeprom_size = data; 1057 break; 1058 } 1059 } 1060 /* 1061 * Shift out data. 1062 */ 1063 data = 0; 1064 reg = FXP_EEPROM_EECS; 1065 for (x = 1 << 15; x; x >>= 1) { 1066 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK); 1067 DELAY(1); 1068 if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO) 1069 data |= x; 1070 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 1071 DELAY(1); 1072 } 1073 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 1074 DELAY(1); 1075 1076 return (data); 1077 } 1078 1079 static void 1080 fxp_eeprom_putword(struct fxp_softc *sc, int offset, u_int16_t data) 1081 { 1082 int i; 1083 1084 /* 1085 * Erase/write enable. 1086 */ 1087 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 1088 fxp_eeprom_shiftin(sc, 0x4, 3); 1089 fxp_eeprom_shiftin(sc, 0x03 << (sc->eeprom_size - 2), sc->eeprom_size); 1090 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 1091 DELAY(1); 1092 /* 1093 * Shift in write opcode, address, data. 1094 */ 1095 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 1096 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_WRITE, 3); 1097 fxp_eeprom_shiftin(sc, offset, sc->eeprom_size); 1098 fxp_eeprom_shiftin(sc, data, 16); 1099 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 1100 DELAY(1); 1101 /* 1102 * Wait for EEPROM to finish up. 1103 */ 1104 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 1105 DELAY(1); 1106 for (i = 0; i < 1000; i++) { 1107 if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO) 1108 break; 1109 DELAY(50); 1110 } 1111 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 1112 DELAY(1); 1113 /* 1114 * Erase/write disable. 1115 */ 1116 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 1117 fxp_eeprom_shiftin(sc, 0x4, 3); 1118 fxp_eeprom_shiftin(sc, 0, sc->eeprom_size); 1119 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 1120 DELAY(1); 1121 } 1122 1123 /* 1124 * From NetBSD: 1125 * 1126 * Figure out EEPROM size. 1127 * 1128 * 559's can have either 64-word or 256-word EEPROMs, the 558 1129 * datasheet only talks about 64-word EEPROMs, and the 557 datasheet 1130 * talks about the existance of 16 to 256 word EEPROMs. 1131 * 1132 * The only known sizes are 64 and 256, where the 256 version is used 1133 * by CardBus cards to store CIS information. 1134 * 1135 * The address is shifted in msb-to-lsb, and after the last 1136 * address-bit the EEPROM is supposed to output a `dummy zero' bit, 1137 * after which follows the actual data. We try to detect this zero, by 1138 * probing the data-out bit in the EEPROM control register just after 1139 * having shifted in a bit. If the bit is zero, we assume we've 1140 * shifted enough address bits. The data-out should be tri-state, 1141 * before this, which should translate to a logical one. 1142 */ 1143 static void 1144 fxp_autosize_eeprom(struct fxp_softc *sc) 1145 { 1146 1147 /* guess maximum size of 256 words */ 1148 sc->eeprom_size = 8; 1149 1150 /* autosize */ 1151 (void) fxp_eeprom_getword(sc, 0, 1); 1152 } 1153 1154 static void 1155 fxp_read_eeprom(struct fxp_softc *sc, u_short *data, int offset, int words) 1156 { 1157 int i; 1158 1159 for (i = 0; i < words; i++) 1160 data[i] = fxp_eeprom_getword(sc, offset + i, 0); 1161 } 1162 1163 static void 1164 fxp_write_eeprom(struct fxp_softc *sc, u_short *data, int offset, int words) 1165 { 1166 int i; 1167 1168 for (i = 0; i < words; i++) 1169 fxp_eeprom_putword(sc, offset + i, data[i]); 1170 } 1171 1172 static void 1173 fxp_dma_map_txbuf(void *arg, bus_dma_segment_t *segs, int nseg, 1174 bus_size_t mapsize, int error) 1175 { 1176 struct fxp_softc *sc; 1177 struct fxp_cb_tx *txp; 1178 int i; 1179 1180 if (error) 1181 return; 1182 1183 KASSERT(nseg <= FXP_NTXSEG, ("too many DMA segments")); 1184 1185 sc = arg; 1186 txp = sc->fxp_desc.tx_last->tx_next->tx_cb; 1187 for (i = 0; i < nseg; i++) { 1188 KASSERT(segs[i].ds_len <= MCLBYTES, ("segment size too large")); 1189 /* 1190 * If this is an 82550/82551, then we're using extended 1191 * TxCBs _and_ we're using checksum offload. This means 1192 * that the TxCB is really an IPCB. One major difference 1193 * between the two is that with plain extended TxCBs, 1194 * the bottom half of the TxCB contains two entries from 1195 * the TBD array, whereas IPCBs contain just one entry: 1196 * one entry (8 bytes) has been sacrificed for the TCP/IP 1197 * checksum offload control bits. So to make things work 1198 * right, we have to start filling in the TBD array 1199 * starting from a different place depending on whether 1200 * the chip is an 82550/82551 or not. 1201 */ 1202 if (sc->flags & FXP_FLAG_EXT_RFA) { 1203 txp->tbd[i + 1].tb_addr = segs[i].ds_addr; 1204 txp->tbd[i + 1].tb_size = segs[i].ds_len; 1205 } else { 1206 txp->tbd[i].tb_addr = segs[i].ds_addr; 1207 txp->tbd[i].tb_size = segs[i].ds_len; 1208 } 1209 } 1210 txp->tbd_number = nseg; 1211 } 1212 1213 /* 1214 * Start packet transmission on the interface. 1215 */ 1216 static void 1217 fxp_start(struct ifnet *ifp) 1218 { 1219 struct fxp_softc *sc = ifp->if_softc; 1220 struct fxp_tx *txp; 1221 struct mbuf *mb_head; 1222 int error; 1223 1224 /* 1225 * See if we need to suspend xmit until the multicast filter 1226 * has been reprogrammed (which can only be done at the head 1227 * of the command chain). 1228 */ 1229 if (sc->need_mcsetup) { 1230 return; 1231 } 1232 1233 txp = NULL; 1234 1235 /* 1236 * We're finished if there is nothing more to add to the list or if 1237 * we're all filled up with buffers to transmit. 1238 * NOTE: One TxCB is reserved to guarantee that fxp_mc_setup() can add 1239 * a NOP command when needed. 1240 */ 1241 while (ifp->if_snd.ifq_head != NULL && sc->tx_queued < FXP_NTXCB - 1) { 1242 1243 /* 1244 * Grab a packet to transmit. 1245 */ 1246 IF_DEQUEUE(&ifp->if_snd, mb_head); 1247 1248 /* 1249 * Get pointer to next available tx desc. 1250 */ 1251 txp = sc->fxp_desc.tx_last->tx_next; 1252 1253 /* 1254 * Deal with TCP/IP checksum offload. Note that 1255 * in order for TCP checksum offload to work, 1256 * the pseudo header checksum must have already 1257 * been computed and stored in the checksum field 1258 * in the TCP header. The stack should have 1259 * already done this for us. 1260 */ 1261 1262 if (mb_head->m_pkthdr.csum_flags) { 1263 if (mb_head->m_pkthdr.csum_flags & CSUM_DELAY_DATA) { 1264 txp->tx_cb->ipcb_ip_activation_high = 1265 FXP_IPCB_HARDWAREPARSING_ENABLE; 1266 txp->tx_cb->ipcb_ip_schedule = 1267 FXP_IPCB_TCPUDP_CHECKSUM_ENABLE; 1268 if (mb_head->m_pkthdr.csum_flags & CSUM_TCP) 1269 txp->tx_cb->ipcb_ip_schedule |= 1270 FXP_IPCB_TCP_PACKET; 1271 } 1272 #ifdef FXP_IP_CSUM_WAR 1273 /* 1274 * XXX The 82550 chip appears to have trouble 1275 * dealing with IP header checksums in very small 1276 * datagrams, namely fragments from 1 to 3 bytes 1277 * in size. For example, say you want to transmit 1278 * a UDP packet of 1473 bytes. The packet will be 1279 * fragmented over two IP datagrams, the latter 1280 * containing only one byte of data. The 82550 will 1281 * botch the header checksum on the 1-byte fragment. 1282 * As long as the datagram contains 4 or more bytes 1283 * of data, you're ok. 1284 * 1285 * The following code attempts to work around this 1286 * problem: if the datagram is less than 38 bytes 1287 * in size (14 bytes ether header, 20 bytes IP header, 1288 * plus 4 bytes of data), we punt and compute the IP 1289 * header checksum by hand. This workaround doesn't 1290 * work very well, however, since it can be fooled 1291 * by things like VLAN tags and IP options that make 1292 * the header sizes/offsets vary. 1293 */ 1294 1295 if (mb_head->m_pkthdr.csum_flags & CSUM_IP) { 1296 if (mb_head->m_pkthdr.len < 38) { 1297 struct ip *ip; 1298 mb_head->m_data += ETHER_HDR_LEN; 1299 ip = mtod(mb_head, struct ip *); 1300 ip->ip_sum = in_cksum(mb_head, 1301 ip->ip_hl << 2); 1302 mb_head->m_data -= ETHER_HDR_LEN; 1303 } else { 1304 txp->tx_cb->ipcb_ip_activation_high = 1305 FXP_IPCB_HARDWAREPARSING_ENABLE; 1306 txp->tx_cb->ipcb_ip_schedule |= 1307 FXP_IPCB_IP_CHECKSUM_ENABLE; 1308 } 1309 } 1310 #endif 1311 } 1312 1313 /* 1314 * Go through each of the mbufs in the chain and initialize 1315 * the transmit buffer descriptors with the physical address 1316 * and size of the mbuf. 1317 */ 1318 error = bus_dmamap_load_mbuf(sc->fxp_mtag, txp->tx_map, 1319 mb_head, fxp_dma_map_txbuf, sc, 0); 1320 1321 if (error && error != EFBIG) { 1322 device_printf(sc->dev, "can't map mbuf (error %d)\n", 1323 error); 1324 m_freem(mb_head); 1325 break; 1326 } 1327 1328 if (error) { 1329 struct mbuf *mn; 1330 1331 /* 1332 * We ran out of segments. We have to recopy this 1333 * mbuf chain first. Bail out if we can't get the 1334 * new buffers. 1335 */ 1336 MGETHDR(mn, M_DONTWAIT, MT_DATA); 1337 if (mn == NULL) { 1338 m_freem(mb_head); 1339 break; 1340 } 1341 if (mb_head->m_pkthdr.len > MHLEN) { 1342 MCLGET(mn, M_DONTWAIT); 1343 if ((mn->m_flags & M_EXT) == 0) { 1344 m_freem(mn); 1345 m_freem(mb_head); 1346 break; 1347 } 1348 } 1349 m_copydata(mb_head, 0, mb_head->m_pkthdr.len, 1350 mtod(mn, caddr_t)); 1351 mn->m_pkthdr.len = mn->m_len = mb_head->m_pkthdr.len; 1352 m_freem(mb_head); 1353 mb_head = mn; 1354 error = bus_dmamap_load_mbuf(sc->fxp_mtag, txp->tx_map, 1355 mb_head, fxp_dma_map_txbuf, sc, 0); 1356 if (error) { 1357 device_printf(sc->dev, 1358 "can't map mbuf (error %d)\n", error); 1359 m_freem(mb_head); 1360 break; 1361 } 1362 } 1363 1364 bus_dmamap_sync(sc->fxp_mtag, txp->tx_map, 1365 BUS_DMASYNC_PREWRITE); 1366 1367 txp->tx_mbuf = mb_head; 1368 txp->tx_cb->cb_status = 0; 1369 txp->tx_cb->byte_count = 0; 1370 if (sc->tx_queued != FXP_CXINT_THRESH - 1) { 1371 txp->tx_cb->cb_command = 1372 sc->tx_cmd | FXP_CB_COMMAND_SF | 1373 FXP_CB_COMMAND_S; 1374 } else { 1375 txp->tx_cb->cb_command = 1376 sc->tx_cmd | FXP_CB_COMMAND_SF | 1377 FXP_CB_COMMAND_S | FXP_CB_COMMAND_I; 1378 /* 1379 * Set a 5 second timer just in case we don't hear 1380 * from the card again. 1381 */ 1382 ifp->if_timer = 5; 1383 } 1384 txp->tx_cb->tx_threshold = tx_threshold; 1385 1386 /* 1387 * Advance the end of list forward. 1388 */ 1389 1390 #ifdef __alpha__ 1391 /* 1392 * On platforms which can't access memory in 16-bit 1393 * granularities, we must prevent the card from DMA'ing 1394 * up the status while we update the command field. 1395 * This could cause us to overwrite the completion status. 1396 */ 1397 atomic_clear_short(&sc->fxp_desc.tx_last->tx_cb->cb_command, 1398 FXP_CB_COMMAND_S); 1399 #else 1400 sc->fxp_desc.tx_last->tx_cb->cb_command &= ~FXP_CB_COMMAND_S; 1401 #endif /*__alpha__*/ 1402 sc->fxp_desc.tx_last = txp; 1403 1404 /* 1405 * Advance the beginning of the list forward if there are 1406 * no other packets queued (when nothing is queued, tx_first 1407 * sits on the last TxCB that was sent out). 1408 */ 1409 if (sc->tx_queued == 0) 1410 sc->fxp_desc.tx_first = txp; 1411 1412 sc->tx_queued++; 1413 1414 /* 1415 * Pass packet to bpf if there is a listener. 1416 */ 1417 BPF_MTAP(ifp, mb_head); 1418 } 1419 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE); 1420 1421 /* 1422 * We're finished. If we added to the list, issue a RESUME to get DMA 1423 * going again if suspended. 1424 */ 1425 if (txp != NULL) { 1426 fxp_scb_wait(sc); 1427 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_RESUME); 1428 } 1429 } 1430 1431 static void fxp_intr_body(struct fxp_softc *sc, u_int8_t statack, int count); 1432 1433 #ifdef DEVICE_POLLING 1434 static poll_handler_t fxp_poll; 1435 1436 static void 1437 fxp_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 1438 { 1439 struct fxp_softc *sc = ifp->if_softc; 1440 u_int8_t statack; 1441 1442 if (cmd == POLL_DEREGISTER) { /* final call, enable interrupts */ 1443 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, 0); 1444 return; 1445 } 1446 statack = FXP_SCB_STATACK_CXTNO | FXP_SCB_STATACK_CNA | 1447 FXP_SCB_STATACK_FR; 1448 if (cmd == POLL_AND_CHECK_STATUS) { 1449 u_int8_t tmp; 1450 1451 tmp = CSR_READ_1(sc, FXP_CSR_SCB_STATACK); 1452 if (tmp == 0xff || tmp == 0) 1453 return; /* nothing to do */ 1454 tmp &= ~statack; 1455 /* ack what we can */ 1456 if (tmp != 0) 1457 CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, tmp); 1458 statack |= tmp; 1459 } 1460 fxp_intr_body(sc, statack, count); 1461 } 1462 #endif /* DEVICE_POLLING */ 1463 1464 /* 1465 * Process interface interrupts. 1466 */ 1467 static void 1468 fxp_intr(void *xsc) 1469 { 1470 struct fxp_softc *sc = xsc; 1471 u_int8_t statack; 1472 1473 #ifdef DEVICE_POLLING 1474 struct ifnet *ifp = &sc->sc_if; 1475 1476 if (ifp->if_flags & IFF_POLLING) 1477 return; 1478 if (ether_poll_register(fxp_poll, ifp)) { 1479 /* disable interrupts */ 1480 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE); 1481 fxp_poll(ifp, 0, 1); 1482 return; 1483 } 1484 #endif 1485 1486 if (sc->suspended) { 1487 return; 1488 } 1489 1490 while ((statack = CSR_READ_1(sc, FXP_CSR_SCB_STATACK)) != 0) { 1491 /* 1492 * It should not be possible to have all bits set; the 1493 * FXP_SCB_INTR_SWI bit always returns 0 on a read. If 1494 * all bits are set, this may indicate that the card has 1495 * been physically ejected, so ignore it. 1496 */ 1497 if (statack == 0xff) 1498 return; 1499 1500 /* 1501 * First ACK all the interrupts in this pass. 1502 */ 1503 CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, statack); 1504 fxp_intr_body(sc, statack, -1); 1505 } 1506 } 1507 1508 static void 1509 fxp_txeof(struct fxp_softc *sc) 1510 { 1511 struct fxp_tx *txp; 1512 1513 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREREAD); 1514 for (txp = sc->fxp_desc.tx_first; sc->tx_queued && 1515 (txp->tx_cb->cb_status & FXP_CB_STATUS_C) != 0; 1516 txp = txp->tx_next) { 1517 if (txp->tx_mbuf != NULL) { 1518 bus_dmamap_sync(sc->fxp_mtag, txp->tx_map, 1519 BUS_DMASYNC_POSTWRITE); 1520 bus_dmamap_unload(sc->fxp_mtag, txp->tx_map); 1521 m_freem(txp->tx_mbuf); 1522 txp->tx_mbuf = NULL; 1523 /* clear this to reset csum offload bits */ 1524 txp->tx_cb->tbd[0].tb_addr = 0; 1525 } 1526 sc->tx_queued--; 1527 } 1528 sc->fxp_desc.tx_first = txp; 1529 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE); 1530 } 1531 1532 static void 1533 fxp_intr_body(struct fxp_softc *sc, u_int8_t statack, int count) 1534 { 1535 struct ifnet *ifp = &sc->sc_if; 1536 struct mbuf *m; 1537 struct fxp_rx *rxp; 1538 struct fxp_rfa *rfa; 1539 int rnr = (statack & FXP_SCB_STATACK_RNR) ? 1 : 0; 1540 1541 if (rnr) 1542 fxp_rnr++; 1543 #ifdef DEVICE_POLLING 1544 /* Pick up a deferred RNR condition if `count' ran out last time. */ 1545 if (sc->flags & FXP_FLAG_DEFERRED_RNR) { 1546 sc->flags &= ~FXP_FLAG_DEFERRED_RNR; 1547 rnr = 1; 1548 } 1549 #endif 1550 1551 /* 1552 * Free any finished transmit mbuf chains. 1553 * 1554 * Handle the CNA event likt a CXTNO event. It used to 1555 * be that this event (control unit not ready) was not 1556 * encountered, but it is now with the SMPng modifications. 1557 * The exact sequence of events that occur when the interface 1558 * is brought up are different now, and if this event 1559 * goes unhandled, the configuration/rxfilter setup sequence 1560 * can stall for several seconds. The result is that no 1561 * packets go out onto the wire for about 5 to 10 seconds 1562 * after the interface is ifconfig'ed for the first time. 1563 */ 1564 if (statack & (FXP_SCB_STATACK_CXTNO | FXP_SCB_STATACK_CNA)) { 1565 fxp_txeof(sc); 1566 1567 ifp->if_timer = 0; 1568 if (sc->tx_queued == 0) { 1569 if (sc->need_mcsetup) 1570 fxp_mc_setup(sc); 1571 } 1572 /* 1573 * Try to start more packets transmitting. 1574 */ 1575 if (ifp->if_snd.ifq_head != NULL) 1576 fxp_start(ifp); 1577 } 1578 1579 /* 1580 * Just return if nothing happened on the receive side. 1581 */ 1582 if (!rnr && (statack & FXP_SCB_STATACK_FR) == 0) 1583 return; 1584 1585 /* 1586 * Process receiver interrupts. If a no-resource (RNR) 1587 * condition exists, get whatever packets we can and 1588 * re-start the receiver. 1589 * 1590 * When using polling, we do not process the list to completion, 1591 * so when we get an RNR interrupt we must defer the restart 1592 * until we hit the last buffer with the C bit set. 1593 * If we run out of cycles and rfa_headm has the C bit set, 1594 * record the pending RNR in the FXP_FLAG_DEFERRED_RNR flag so 1595 * that the info will be used in the subsequent polling cycle. 1596 */ 1597 for (;;) { 1598 rxp = sc->fxp_desc.rx_head; 1599 m = rxp->rx_mbuf; 1600 rfa = (struct fxp_rfa *)(m->m_ext.ext_buf + 1601 RFA_ALIGNMENT_FUDGE); 1602 bus_dmamap_sync(sc->fxp_mtag, rxp->rx_map, 1603 BUS_DMASYNC_POSTREAD); 1604 1605 #ifdef DEVICE_POLLING /* loop at most count times if count >=0 */ 1606 if (count >= 0 && count-- == 0) { 1607 if (rnr) { 1608 /* Defer RNR processing until the next time. */ 1609 sc->flags |= FXP_FLAG_DEFERRED_RNR; 1610 rnr = 0; 1611 } 1612 break; 1613 } 1614 #endif /* DEVICE_POLLING */ 1615 1616 if ((rfa->rfa_status & FXP_RFA_STATUS_C) == 0) 1617 break; 1618 1619 /* 1620 * Advance head forward. 1621 */ 1622 sc->fxp_desc.rx_head = rxp->rx_next; 1623 1624 /* 1625 * Add a new buffer to the receive chain. 1626 * If this fails, the old buffer is recycled 1627 * instead. 1628 */ 1629 if (fxp_add_rfabuf(sc, rxp) == 0) { 1630 int total_len; 1631 1632 /* 1633 * Fetch packet length (the top 2 bits of 1634 * actual_size are flags set by the controller 1635 * upon completion), and drop the packet in case 1636 * of bogus length or CRC errors. 1637 */ 1638 total_len = rfa->actual_size & 0x3fff; 1639 if (total_len < sizeof(struct ether_header) || 1640 total_len > MCLBYTES - RFA_ALIGNMENT_FUDGE - 1641 sc->rfa_size || 1642 rfa->rfa_status & FXP_RFA_STATUS_CRC) { 1643 m_freem(m); 1644 continue; 1645 } 1646 1647 /* Do IP checksum checking. */ 1648 if (rfa->rfa_status & FXP_RFA_STATUS_PARSE) { 1649 if (rfa->rfax_csum_sts & 1650 FXP_RFDX_CS_IP_CSUM_BIT_VALID) 1651 m->m_pkthdr.csum_flags |= 1652 CSUM_IP_CHECKED; 1653 if (rfa->rfax_csum_sts & 1654 FXP_RFDX_CS_IP_CSUM_VALID) 1655 m->m_pkthdr.csum_flags |= 1656 CSUM_IP_VALID; 1657 if ((rfa->rfax_csum_sts & 1658 FXP_RFDX_CS_TCPUDP_CSUM_BIT_VALID) && 1659 (rfa->rfax_csum_sts & 1660 FXP_RFDX_CS_TCPUDP_CSUM_VALID)) { 1661 m->m_pkthdr.csum_flags |= 1662 CSUM_DATA_VALID|CSUM_PSEUDO_HDR; 1663 m->m_pkthdr.csum_data = 0xffff; 1664 } 1665 } 1666 1667 m->m_pkthdr.len = m->m_len = total_len; 1668 m->m_pkthdr.rcvif = ifp; 1669 1670 (*ifp->if_input)(ifp, m); 1671 } 1672 } 1673 if (rnr) { 1674 fxp_scb_wait(sc); 1675 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 1676 sc->fxp_desc.rx_head->rx_addr); 1677 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_START); 1678 } 1679 } 1680 1681 /* 1682 * Update packet in/out/collision statistics. The i82557 doesn't 1683 * allow you to access these counters without doing a fairly 1684 * expensive DMA to get _all_ of the statistics it maintains, so 1685 * we do this operation here only once per second. The statistics 1686 * counters in the kernel are updated from the previous dump-stats 1687 * DMA and then a new dump-stats DMA is started. The on-chip 1688 * counters are zeroed when the DMA completes. If we can't start 1689 * the DMA immediately, we don't wait - we just prepare to read 1690 * them again next time. 1691 */ 1692 static void 1693 fxp_tick(void *xsc) 1694 { 1695 struct fxp_softc *sc = xsc; 1696 struct ifnet *ifp = &sc->sc_if; 1697 struct fxp_stats *sp = sc->fxp_stats; 1698 int s; 1699 1700 bus_dmamap_sync(sc->fxp_stag, sc->fxp_smap, BUS_DMASYNC_POSTREAD); 1701 ifp->if_opackets += sp->tx_good; 1702 ifp->if_collisions += sp->tx_total_collisions; 1703 if (sp->rx_good) { 1704 ifp->if_ipackets += sp->rx_good; 1705 sc->rx_idle_secs = 0; 1706 } else { 1707 /* 1708 * Receiver's been idle for another second. 1709 */ 1710 sc->rx_idle_secs++; 1711 } 1712 ifp->if_ierrors += 1713 sp->rx_crc_errors + 1714 sp->rx_alignment_errors + 1715 sp->rx_rnr_errors + 1716 sp->rx_overrun_errors; 1717 /* 1718 * If any transmit underruns occured, bump up the transmit 1719 * threshold by another 512 bytes (64 * 8). 1720 */ 1721 if (sp->tx_underruns) { 1722 ifp->if_oerrors += sp->tx_underruns; 1723 if (tx_threshold < 192) 1724 tx_threshold += 64; 1725 } 1726 s = splimp(); 1727 /* 1728 * Release any xmit buffers that have completed DMA. This isn't 1729 * strictly necessary to do here, but it's advantagous for mbufs 1730 * with external storage to be released in a timely manner rather 1731 * than being defered for a potentially long time. This limits 1732 * the delay to a maximum of one second. 1733 */ 1734 fxp_txeof(sc); 1735 1736 /* 1737 * If we haven't received any packets in FXP_MAC_RX_IDLE seconds, 1738 * then assume the receiver has locked up and attempt to clear 1739 * the condition by reprogramming the multicast filter. This is 1740 * a work-around for a bug in the 82557 where the receiver locks 1741 * up if it gets certain types of garbage in the syncronization 1742 * bits prior to the packet header. This bug is supposed to only 1743 * occur in 10Mbps mode, but has been seen to occur in 100Mbps 1744 * mode as well (perhaps due to a 10/100 speed transition). 1745 */ 1746 if (sc->rx_idle_secs > FXP_MAX_RX_IDLE) { 1747 sc->rx_idle_secs = 0; 1748 fxp_mc_setup(sc); 1749 } 1750 /* 1751 * If there is no pending command, start another stats 1752 * dump. Otherwise punt for now. 1753 */ 1754 if (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) == 0) { 1755 /* 1756 * Start another stats dump. 1757 */ 1758 bus_dmamap_sync(sc->fxp_stag, sc->fxp_smap, 1759 BUS_DMASYNC_PREREAD); 1760 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_DUMPRESET); 1761 } else { 1762 /* 1763 * A previous command is still waiting to be accepted. 1764 * Just zero our copy of the stats and wait for the 1765 * next timer event to update them. 1766 */ 1767 sp->tx_good = 0; 1768 sp->tx_underruns = 0; 1769 sp->tx_total_collisions = 0; 1770 1771 sp->rx_good = 0; 1772 sp->rx_crc_errors = 0; 1773 sp->rx_alignment_errors = 0; 1774 sp->rx_rnr_errors = 0; 1775 sp->rx_overrun_errors = 0; 1776 } 1777 if (sc->miibus != NULL) 1778 mii_tick(device_get_softc(sc->miibus)); 1779 splx(s); 1780 /* 1781 * Schedule another timeout one second from now. 1782 */ 1783 sc->stat_ch = timeout(fxp_tick, sc, hz); 1784 } 1785 1786 /* 1787 * Stop the interface. Cancels the statistics updater and resets 1788 * the interface. 1789 */ 1790 static void 1791 fxp_stop(struct fxp_softc *sc) 1792 { 1793 struct ifnet *ifp = &sc->sc_if; 1794 struct fxp_tx *txp; 1795 int i; 1796 1797 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1798 ifp->if_timer = 0; 1799 1800 #ifdef DEVICE_POLLING 1801 ether_poll_deregister(ifp); 1802 #endif 1803 /* 1804 * Cancel stats updater. 1805 */ 1806 untimeout(fxp_tick, sc, sc->stat_ch); 1807 1808 /* 1809 * Issue software reset, which also unloads the microcode. 1810 */ 1811 sc->flags &= ~FXP_FLAG_UCODE; 1812 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SOFTWARE_RESET); 1813 DELAY(50); 1814 1815 /* 1816 * Release any xmit buffers. 1817 */ 1818 txp = sc->fxp_desc.tx_list; 1819 if (txp != NULL) { 1820 for (i = 0; i < FXP_NTXCB; i++) { 1821 if (txp[i].tx_mbuf != NULL) { 1822 bus_dmamap_sync(sc->fxp_mtag, txp[i].tx_map, 1823 BUS_DMASYNC_POSTWRITE); 1824 bus_dmamap_unload(sc->fxp_mtag, txp[i].tx_map); 1825 m_freem(txp[i].tx_mbuf); 1826 txp[i].tx_mbuf = NULL; 1827 /* clear this to reset csum offload bits */ 1828 txp[i].tx_cb->tbd[0].tb_addr = 0; 1829 } 1830 } 1831 } 1832 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE); 1833 sc->tx_queued = 0; 1834 } 1835 1836 /* 1837 * Watchdog/transmission transmit timeout handler. Called when a 1838 * transmission is started on the interface, but no interrupt is 1839 * received before the timeout. This usually indicates that the 1840 * card has wedged for some reason. 1841 */ 1842 static void 1843 fxp_watchdog(struct ifnet *ifp) 1844 { 1845 struct fxp_softc *sc = ifp->if_softc; 1846 1847 device_printf(sc->dev, "device timeout\n"); 1848 ifp->if_oerrors++; 1849 1850 fxp_init(sc); 1851 } 1852 1853 static void 1854 fxp_init(void *xsc) 1855 { 1856 struct fxp_softc *sc = xsc; 1857 struct ifnet *ifp = &sc->sc_if; 1858 struct fxp_cb_config *cbp; 1859 struct fxp_cb_ias *cb_ias; 1860 struct fxp_cb_tx *tcbp; 1861 struct fxp_tx *txp; 1862 struct fxp_cb_mcs *mcsp; 1863 int i, prm, s; 1864 1865 s = splimp(); 1866 /* 1867 * Cancel any pending I/O 1868 */ 1869 fxp_stop(sc); 1870 1871 prm = (ifp->if_flags & IFF_PROMISC) ? 1 : 0; 1872 1873 /* 1874 * Initialize base of CBL and RFA memory. Loading with zero 1875 * sets it up for regular linear addressing. 1876 */ 1877 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 0); 1878 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_BASE); 1879 1880 fxp_scb_wait(sc); 1881 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_BASE); 1882 1883 /* 1884 * Initialize base of dump-stats buffer. 1885 */ 1886 fxp_scb_wait(sc); 1887 bus_dmamap_sync(sc->fxp_stag, sc->fxp_smap, BUS_DMASYNC_PREREAD); 1888 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->stats_addr); 1889 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_DUMP_ADR); 1890 1891 /* 1892 * Attempt to load microcode if requested. 1893 */ 1894 if (ifp->if_flags & IFF_LINK0 && (sc->flags & FXP_FLAG_UCODE) == 0) 1895 fxp_load_ucode(sc); 1896 1897 /* 1898 * Initialize the multicast address list. 1899 */ 1900 if (fxp_mc_addrs(sc)) { 1901 mcsp = sc->mcsp; 1902 mcsp->cb_status = 0; 1903 mcsp->cb_command = FXP_CB_COMMAND_MCAS | FXP_CB_COMMAND_EL; 1904 mcsp->link_addr = -1; 1905 /* 1906 * Start the multicast setup command. 1907 */ 1908 fxp_scb_wait(sc); 1909 bus_dmamap_sync(sc->mcs_tag, sc->mcs_map, BUS_DMASYNC_PREWRITE); 1910 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->mcs_addr); 1911 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 1912 /* ...and wait for it to complete. */ 1913 fxp_dma_wait(&mcsp->cb_status, sc); 1914 bus_dmamap_sync(sc->mcs_tag, sc->mcs_map, 1915 BUS_DMASYNC_POSTWRITE); 1916 } 1917 1918 /* 1919 * We temporarily use memory that contains the TxCB list to 1920 * construct the config CB. The TxCB list memory is rebuilt 1921 * later. 1922 */ 1923 cbp = (struct fxp_cb_config *)sc->fxp_desc.cbl_list; 1924 1925 /* 1926 * This bcopy is kind of disgusting, but there are a bunch of must be 1927 * zero and must be one bits in this structure and this is the easiest 1928 * way to initialize them all to proper values. 1929 */ 1930 bcopy(fxp_cb_config_template, cbp, sizeof(fxp_cb_config_template)); 1931 1932 cbp->cb_status = 0; 1933 cbp->cb_command = FXP_CB_COMMAND_CONFIG | FXP_CB_COMMAND_EL; 1934 cbp->link_addr = -1; /* (no) next command */ 1935 cbp->byte_count = sc->flags & FXP_FLAG_EXT_RFA ? 32 : 22; 1936 cbp->rx_fifo_limit = 8; /* rx fifo threshold (32 bytes) */ 1937 cbp->tx_fifo_limit = 0; /* tx fifo threshold (0 bytes) */ 1938 cbp->adaptive_ifs = 0; /* (no) adaptive interframe spacing */ 1939 cbp->mwi_enable = sc->flags & FXP_FLAG_MWI_ENABLE ? 1 : 0; 1940 cbp->type_enable = 0; /* actually reserved */ 1941 cbp->read_align_en = sc->flags & FXP_FLAG_READ_ALIGN ? 1 : 0; 1942 cbp->end_wr_on_cl = sc->flags & FXP_FLAG_WRITE_ALIGN ? 1 : 0; 1943 cbp->rx_dma_bytecount = 0; /* (no) rx DMA max */ 1944 cbp->tx_dma_bytecount = 0; /* (no) tx DMA max */ 1945 cbp->dma_mbce = 0; /* (disable) dma max counters */ 1946 cbp->late_scb = 0; /* (don't) defer SCB update */ 1947 cbp->direct_dma_dis = 1; /* disable direct rcv dma mode */ 1948 cbp->tno_int_or_tco_en =0; /* (disable) tx not okay interrupt */ 1949 cbp->ci_int = 1; /* interrupt on CU idle */ 1950 cbp->ext_txcb_dis = sc->flags & FXP_FLAG_EXT_TXCB ? 0 : 1; 1951 cbp->ext_stats_dis = 1; /* disable extended counters */ 1952 cbp->keep_overrun_rx = 0; /* don't pass overrun frames to host */ 1953 cbp->save_bf = sc->revision == FXP_REV_82557 ? 1 : prm; 1954 cbp->disc_short_rx = !prm; /* discard short packets */ 1955 cbp->underrun_retry = 1; /* retry mode (once) on DMA underrun */ 1956 cbp->two_frames = 0; /* do not limit FIFO to 2 frames */ 1957 cbp->dyn_tbd = 0; /* (no) dynamic TBD mode */ 1958 cbp->ext_rfa = sc->flags & FXP_FLAG_EXT_RFA ? 1 : 0; 1959 cbp->mediatype = sc->flags & FXP_FLAG_SERIAL_MEDIA ? 0 : 1; 1960 cbp->csma_dis = 0; /* (don't) disable link */ 1961 cbp->tcp_udp_cksum = 0; /* (don't) enable checksum */ 1962 cbp->vlan_tco = 0; /* (don't) enable vlan wakeup */ 1963 cbp->link_wake_en = 0; /* (don't) assert PME# on link change */ 1964 cbp->arp_wake_en = 0; /* (don't) assert PME# on arp */ 1965 cbp->mc_wake_en = 0; /* (don't) enable PME# on mcmatch */ 1966 cbp->nsai = 1; /* (don't) disable source addr insert */ 1967 cbp->preamble_length = 2; /* (7 byte) preamble */ 1968 cbp->loopback = 0; /* (don't) loopback */ 1969 cbp->linear_priority = 0; /* (normal CSMA/CD operation) */ 1970 cbp->linear_pri_mode = 0; /* (wait after xmit only) */ 1971 cbp->interfrm_spacing = 6; /* (96 bits of) interframe spacing */ 1972 cbp->promiscuous = prm; /* promiscuous mode */ 1973 cbp->bcast_disable = 0; /* (don't) disable broadcasts */ 1974 cbp->wait_after_win = 0; /* (don't) enable modified backoff alg*/ 1975 cbp->ignore_ul = 0; /* consider U/L bit in IA matching */ 1976 cbp->crc16_en = 0; /* (don't) enable crc-16 algorithm */ 1977 cbp->crscdt = sc->flags & FXP_FLAG_SERIAL_MEDIA ? 1 : 0; 1978 1979 cbp->stripping = !prm; /* truncate rx packet to byte count */ 1980 cbp->padding = 1; /* (do) pad short tx packets */ 1981 cbp->rcv_crc_xfer = 0; /* (don't) xfer CRC to host */ 1982 cbp->long_rx_en = sc->flags & FXP_FLAG_LONG_PKT_EN ? 1 : 0; 1983 cbp->ia_wake_en = 0; /* (don't) wake up on address match */ 1984 cbp->magic_pkt_dis = 0; /* (don't) disable magic packet */ 1985 /* must set wake_en in PMCSR also */ 1986 cbp->force_fdx = 0; /* (don't) force full duplex */ 1987 cbp->fdx_pin_en = 1; /* (enable) FDX# pin */ 1988 cbp->multi_ia = 0; /* (don't) accept multiple IAs */ 1989 cbp->mc_all = sc->flags & FXP_FLAG_ALL_MCAST ? 1 : 0; 1990 cbp->gamla_rx = sc->flags & FXP_FLAG_EXT_RFA ? 1 : 0; 1991 1992 if (sc->revision == FXP_REV_82557) { 1993 /* 1994 * The 82557 has no hardware flow control, the values 1995 * below are the defaults for the chip. 1996 */ 1997 cbp->fc_delay_lsb = 0; 1998 cbp->fc_delay_msb = 0x40; 1999 cbp->pri_fc_thresh = 3; 2000 cbp->tx_fc_dis = 0; 2001 cbp->rx_fc_restop = 0; 2002 cbp->rx_fc_restart = 0; 2003 cbp->fc_filter = 0; 2004 cbp->pri_fc_loc = 1; 2005 } else { 2006 cbp->fc_delay_lsb = 0x1f; 2007 cbp->fc_delay_msb = 0x01; 2008 cbp->pri_fc_thresh = 3; 2009 cbp->tx_fc_dis = 0; /* enable transmit FC */ 2010 cbp->rx_fc_restop = 1; /* enable FC restop frames */ 2011 cbp->rx_fc_restart = 1; /* enable FC restart frames */ 2012 cbp->fc_filter = !prm; /* drop FC frames to host */ 2013 cbp->pri_fc_loc = 1; /* FC pri location (byte31) */ 2014 } 2015 2016 /* 2017 * Start the config command/DMA. 2018 */ 2019 fxp_scb_wait(sc); 2020 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE); 2021 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->fxp_desc.cbl_addr); 2022 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2023 /* ...and wait for it to complete. */ 2024 fxp_dma_wait(&cbp->cb_status, sc); 2025 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_POSTWRITE); 2026 2027 /* 2028 * Now initialize the station address. Temporarily use the TxCB 2029 * memory area like we did above for the config CB. 2030 */ 2031 cb_ias = (struct fxp_cb_ias *)sc->fxp_desc.cbl_list; 2032 cb_ias->cb_status = 0; 2033 cb_ias->cb_command = FXP_CB_COMMAND_IAS | FXP_CB_COMMAND_EL; 2034 cb_ias->link_addr = -1; 2035 bcopy(sc->arpcom.ac_enaddr, cb_ias->macaddr, 2036 sizeof(sc->arpcom.ac_enaddr)); 2037 2038 /* 2039 * Start the IAS (Individual Address Setup) command/DMA. 2040 */ 2041 fxp_scb_wait(sc); 2042 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE); 2043 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2044 /* ...and wait for it to complete. */ 2045 fxp_dma_wait(&cb_ias->cb_status, sc); 2046 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_POSTWRITE); 2047 2048 /* 2049 * Initialize transmit control block (TxCB) list. 2050 */ 2051 txp = sc->fxp_desc.tx_list; 2052 tcbp = sc->fxp_desc.cbl_list; 2053 bzero(tcbp, FXP_TXCB_SZ); 2054 for (i = 0; i < FXP_NTXCB; i++) { 2055 txp[i].tx_cb = tcbp + i; 2056 txp[i].tx_mbuf = NULL; 2057 tcbp[i].cb_status = FXP_CB_STATUS_C | FXP_CB_STATUS_OK; 2058 tcbp[i].cb_command = FXP_CB_COMMAND_NOP; 2059 tcbp[i].link_addr = sc->fxp_desc.cbl_addr + 2060 (((i + 1) & FXP_TXCB_MASK) * sizeof(struct fxp_cb_tx)); 2061 if (sc->flags & FXP_FLAG_EXT_TXCB) 2062 tcbp[i].tbd_array_addr = 2063 FXP_TXCB_DMA_ADDR(sc, &tcbp[i].tbd[2]); 2064 else 2065 tcbp[i].tbd_array_addr = 2066 FXP_TXCB_DMA_ADDR(sc, &tcbp[i].tbd[0]); 2067 txp[i].tx_next = &txp[(i + 1) & FXP_TXCB_MASK]; 2068 } 2069 /* 2070 * Set the suspend flag on the first TxCB and start the control 2071 * unit. It will execute the NOP and then suspend. 2072 */ 2073 tcbp->cb_command = FXP_CB_COMMAND_NOP | FXP_CB_COMMAND_S; 2074 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE); 2075 sc->fxp_desc.tx_first = sc->fxp_desc.tx_last = txp; 2076 sc->tx_queued = 1; 2077 2078 fxp_scb_wait(sc); 2079 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2080 2081 /* 2082 * Initialize receiver buffer area - RFA. 2083 */ 2084 fxp_scb_wait(sc); 2085 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->fxp_desc.rx_head->rx_addr); 2086 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_START); 2087 2088 /* 2089 * Set current media. 2090 */ 2091 if (sc->miibus != NULL) 2092 mii_mediachg(device_get_softc(sc->miibus)); 2093 2094 ifp->if_flags |= IFF_RUNNING; 2095 ifp->if_flags &= ~IFF_OACTIVE; 2096 2097 /* 2098 * Enable interrupts. 2099 */ 2100 #ifdef DEVICE_POLLING 2101 /* 2102 * ... but only do that if we are not polling. And because (presumably) 2103 * the default is interrupts on, we need to disable them explicitly! 2104 */ 2105 if ( ifp->if_flags & IFF_POLLING ) 2106 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE); 2107 else 2108 #endif /* DEVICE_POLLING */ 2109 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, 0); 2110 splx(s); 2111 2112 /* 2113 * Start stats updater. 2114 */ 2115 sc->stat_ch = timeout(fxp_tick, sc, hz); 2116 } 2117 2118 static int 2119 fxp_serial_ifmedia_upd(struct ifnet *ifp) 2120 { 2121 2122 return (0); 2123 } 2124 2125 static void 2126 fxp_serial_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 2127 { 2128 2129 ifmr->ifm_active = IFM_ETHER|IFM_MANUAL; 2130 } 2131 2132 /* 2133 * Change media according to request. 2134 */ 2135 static int 2136 fxp_ifmedia_upd(struct ifnet *ifp) 2137 { 2138 struct fxp_softc *sc = ifp->if_softc; 2139 struct mii_data *mii; 2140 2141 mii = device_get_softc(sc->miibus); 2142 mii_mediachg(mii); 2143 return (0); 2144 } 2145 2146 /* 2147 * Notify the world which media we're using. 2148 */ 2149 static void 2150 fxp_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 2151 { 2152 struct fxp_softc *sc = ifp->if_softc; 2153 struct mii_data *mii; 2154 2155 mii = device_get_softc(sc->miibus); 2156 mii_pollstat(mii); 2157 ifmr->ifm_active = mii->mii_media_active; 2158 ifmr->ifm_status = mii->mii_media_status; 2159 2160 if (ifmr->ifm_status & IFM_10_T && sc->flags & FXP_FLAG_CU_RESUME_BUG) 2161 sc->cu_resume_bug = 1; 2162 else 2163 sc->cu_resume_bug = 0; 2164 } 2165 2166 /* 2167 * Add a buffer to the end of the RFA buffer list. 2168 * Return 0 if successful, 1 for failure. A failure results in 2169 * adding the 'oldm' (if non-NULL) on to the end of the list - 2170 * tossing out its old contents and recycling it. 2171 * The RFA struct is stuck at the beginning of mbuf cluster and the 2172 * data pointer is fixed up to point just past it. 2173 */ 2174 static int 2175 fxp_add_rfabuf(struct fxp_softc *sc, struct fxp_rx *rxp) 2176 { 2177 struct mbuf *m; 2178 struct fxp_rfa *rfa, *p_rfa; 2179 struct fxp_rx *p_rx; 2180 bus_dmamap_t tmp_map; 2181 u_int32_t v; 2182 int error; 2183 2184 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 2185 if (m == NULL) 2186 return (ENOBUFS); 2187 2188 /* 2189 * Move the data pointer up so that the incoming data packet 2190 * will be 32-bit aligned. 2191 */ 2192 m->m_data += RFA_ALIGNMENT_FUDGE; 2193 2194 /* 2195 * Get a pointer to the base of the mbuf cluster and move 2196 * data start past it. 2197 */ 2198 rfa = mtod(m, struct fxp_rfa *); 2199 m->m_data += sc->rfa_size; 2200 rfa->size = MCLBYTES - sc->rfa_size - RFA_ALIGNMENT_FUDGE; 2201 2202 /* 2203 * Initialize the rest of the RFA. Note that since the RFA 2204 * is misaligned, we cannot store values directly. Instead, 2205 * we use an optimized, inline copy. 2206 */ 2207 2208 rfa->rfa_status = 0; 2209 rfa->rfa_control = FXP_RFA_CONTROL_EL; 2210 rfa->actual_size = 0; 2211 2212 v = -1; 2213 fxp_lwcopy(&v, (volatile u_int32_t *) rfa->link_addr); 2214 fxp_lwcopy(&v, (volatile u_int32_t *) rfa->rbd_addr); 2215 2216 /* Map the RFA into DMA memory. */ 2217 error = bus_dmamap_load(sc->fxp_mtag, sc->spare_map, rfa, 2218 MCLBYTES - RFA_ALIGNMENT_FUDGE, fxp_dma_map_addr, 2219 &rxp->rx_addr, 0); 2220 if (error) { 2221 m_freem(m); 2222 return (error); 2223 } 2224 2225 bus_dmamap_unload(sc->fxp_mtag, rxp->rx_map); 2226 tmp_map = sc->spare_map; 2227 sc->spare_map = rxp->rx_map; 2228 rxp->rx_map = tmp_map; 2229 rxp->rx_mbuf = m; 2230 2231 bus_dmamap_sync(sc->fxp_mtag, rxp->rx_map, BUS_DMASYNC_PREWRITE); 2232 2233 /* 2234 * If there are other buffers already on the list, attach this 2235 * one to the end by fixing up the tail to point to this one. 2236 */ 2237 if (sc->fxp_desc.rx_head != NULL) { 2238 p_rx = sc->fxp_desc.rx_tail; 2239 p_rfa = (struct fxp_rfa *) 2240 (p_rx->rx_mbuf->m_ext.ext_buf + RFA_ALIGNMENT_FUDGE); 2241 p_rx->rx_next = rxp; 2242 fxp_lwcopy(&rxp->rx_addr, 2243 (volatile u_int32_t *)p_rfa->link_addr); 2244 p_rfa->rfa_control = 0; 2245 bus_dmamap_sync(sc->fxp_mtag, p_rx->rx_map, 2246 BUS_DMASYNC_PREWRITE); 2247 } else { 2248 rxp->rx_next = NULL; 2249 sc->fxp_desc.rx_head = rxp; 2250 } 2251 sc->fxp_desc.rx_tail = rxp; 2252 return (0); 2253 } 2254 2255 static volatile int 2256 fxp_miibus_readreg(device_t dev, int phy, int reg) 2257 { 2258 struct fxp_softc *sc = device_get_softc(dev); 2259 int count = 10000; 2260 int value; 2261 2262 CSR_WRITE_4(sc, FXP_CSR_MDICONTROL, 2263 (FXP_MDI_READ << 26) | (reg << 16) | (phy << 21)); 2264 2265 while (((value = CSR_READ_4(sc, FXP_CSR_MDICONTROL)) & 0x10000000) == 0 2266 && count--) 2267 DELAY(10); 2268 2269 if (count <= 0) 2270 device_printf(dev, "fxp_miibus_readreg: timed out\n"); 2271 2272 return (value & 0xffff); 2273 } 2274 2275 static void 2276 fxp_miibus_writereg(device_t dev, int phy, int reg, int value) 2277 { 2278 struct fxp_softc *sc = device_get_softc(dev); 2279 int count = 10000; 2280 2281 CSR_WRITE_4(sc, FXP_CSR_MDICONTROL, 2282 (FXP_MDI_WRITE << 26) | (reg << 16) | (phy << 21) | 2283 (value & 0xffff)); 2284 2285 while ((CSR_READ_4(sc, FXP_CSR_MDICONTROL) & 0x10000000) == 0 && 2286 count--) 2287 DELAY(10); 2288 2289 if (count <= 0) 2290 device_printf(dev, "fxp_miibus_writereg: timed out\n"); 2291 } 2292 2293 static int 2294 fxp_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 2295 { 2296 struct fxp_softc *sc = ifp->if_softc; 2297 struct ifreq *ifr = (struct ifreq *)data; 2298 struct mii_data *mii; 2299 int s, error = 0; 2300 2301 s = splimp(); 2302 2303 switch (command) { 2304 case SIOCSIFFLAGS: 2305 if (ifp->if_flags & IFF_ALLMULTI) 2306 sc->flags |= FXP_FLAG_ALL_MCAST; 2307 else 2308 sc->flags &= ~FXP_FLAG_ALL_MCAST; 2309 2310 /* 2311 * If interface is marked up and not running, then start it. 2312 * If it is marked down and running, stop it. 2313 * XXX If it's up then re-initialize it. This is so flags 2314 * such as IFF_PROMISC are handled. 2315 */ 2316 if (ifp->if_flags & IFF_UP) { 2317 fxp_init(sc); 2318 } else { 2319 if (ifp->if_flags & IFF_RUNNING) 2320 fxp_stop(sc); 2321 } 2322 break; 2323 2324 case SIOCADDMULTI: 2325 case SIOCDELMULTI: 2326 if (ifp->if_flags & IFF_ALLMULTI) 2327 sc->flags |= FXP_FLAG_ALL_MCAST; 2328 else 2329 sc->flags &= ~FXP_FLAG_ALL_MCAST; 2330 /* 2331 * Multicast list has changed; set the hardware filter 2332 * accordingly. 2333 */ 2334 if ((sc->flags & FXP_FLAG_ALL_MCAST) == 0) 2335 fxp_mc_setup(sc); 2336 /* 2337 * fxp_mc_setup() can set FXP_FLAG_ALL_MCAST, so check it 2338 * again rather than else {}. 2339 */ 2340 if (sc->flags & FXP_FLAG_ALL_MCAST) 2341 fxp_init(sc); 2342 error = 0; 2343 break; 2344 2345 case SIOCSIFMEDIA: 2346 case SIOCGIFMEDIA: 2347 if (sc->miibus != NULL) { 2348 mii = device_get_softc(sc->miibus); 2349 error = ifmedia_ioctl(ifp, ifr, 2350 &mii->mii_media, command); 2351 } else { 2352 error = ifmedia_ioctl(ifp, ifr, &sc->sc_media, command); 2353 } 2354 break; 2355 2356 default: 2357 error = ether_ioctl(ifp, command, data); 2358 } 2359 splx(s); 2360 return (error); 2361 } 2362 2363 /* 2364 * Fill in the multicast address list and return number of entries. 2365 */ 2366 static int 2367 fxp_mc_addrs(struct fxp_softc *sc) 2368 { 2369 struct fxp_cb_mcs *mcsp = sc->mcsp; 2370 struct ifnet *ifp = &sc->sc_if; 2371 struct ifmultiaddr *ifma; 2372 int nmcasts; 2373 2374 nmcasts = 0; 2375 if ((sc->flags & FXP_FLAG_ALL_MCAST) == 0) { 2376 #if __FreeBSD_version < 500000 2377 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 2378 #else 2379 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 2380 #endif 2381 if (ifma->ifma_addr->sa_family != AF_LINK) 2382 continue; 2383 if (nmcasts >= MAXMCADDR) { 2384 sc->flags |= FXP_FLAG_ALL_MCAST; 2385 nmcasts = 0; 2386 break; 2387 } 2388 bcopy(LLADDR((struct sockaddr_dl *)ifma->ifma_addr), 2389 &sc->mcsp->mc_addr[nmcasts][0], 6); 2390 nmcasts++; 2391 } 2392 } 2393 mcsp->mc_cnt = nmcasts * 6; 2394 return (nmcasts); 2395 } 2396 2397 /* 2398 * Program the multicast filter. 2399 * 2400 * We have an artificial restriction that the multicast setup command 2401 * must be the first command in the chain, so we take steps to ensure 2402 * this. By requiring this, it allows us to keep up the performance of 2403 * the pre-initialized command ring (esp. link pointers) by not actually 2404 * inserting the mcsetup command in the ring - i.e. its link pointer 2405 * points to the TxCB ring, but the mcsetup descriptor itself is not part 2406 * of it. We then can do 'CU_START' on the mcsetup descriptor and have it 2407 * lead into the regular TxCB ring when it completes. 2408 * 2409 * This function must be called at splimp. 2410 */ 2411 static void 2412 fxp_mc_setup(struct fxp_softc *sc) 2413 { 2414 struct fxp_cb_mcs *mcsp = sc->mcsp; 2415 struct ifnet *ifp = &sc->sc_if; 2416 struct fxp_tx *txp; 2417 int count; 2418 2419 /* 2420 * If there are queued commands, we must wait until they are all 2421 * completed. If we are already waiting, then add a NOP command 2422 * with interrupt option so that we're notified when all commands 2423 * have been completed - fxp_start() ensures that no additional 2424 * TX commands will be added when need_mcsetup is true. 2425 */ 2426 if (sc->tx_queued) { 2427 /* 2428 * need_mcsetup will be true if we are already waiting for the 2429 * NOP command to be completed (see below). In this case, bail. 2430 */ 2431 if (sc->need_mcsetup) 2432 return; 2433 sc->need_mcsetup = 1; 2434 2435 /* 2436 * Add a NOP command with interrupt so that we are notified 2437 * when all TX commands have been processed. 2438 */ 2439 txp = sc->fxp_desc.tx_last->tx_next; 2440 txp->tx_mbuf = NULL; 2441 txp->tx_cb->cb_status = 0; 2442 txp->tx_cb->cb_command = FXP_CB_COMMAND_NOP | 2443 FXP_CB_COMMAND_S | FXP_CB_COMMAND_I; 2444 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE); 2445 /* 2446 * Advance the end of list forward. 2447 */ 2448 sc->fxp_desc.tx_last->tx_cb->cb_command &= ~FXP_CB_COMMAND_S; 2449 sc->fxp_desc.tx_last = txp; 2450 sc->tx_queued++; 2451 /* 2452 * Issue a resume in case the CU has just suspended. 2453 */ 2454 fxp_scb_wait(sc); 2455 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_RESUME); 2456 /* 2457 * Set a 5 second timer just in case we don't hear from the 2458 * card again. 2459 */ 2460 ifp->if_timer = 5; 2461 2462 return; 2463 } 2464 sc->need_mcsetup = 0; 2465 2466 /* 2467 * Initialize multicast setup descriptor. 2468 */ 2469 mcsp->cb_status = 0; 2470 mcsp->cb_command = FXP_CB_COMMAND_MCAS | 2471 FXP_CB_COMMAND_S | FXP_CB_COMMAND_I; 2472 mcsp->link_addr = sc->fxp_desc.cbl_addr; 2473 txp = &sc->fxp_desc.mcs_tx; 2474 txp->tx_mbuf = NULL; 2475 txp->tx_cb = (struct fxp_cb_tx *)sc->mcsp; 2476 txp->tx_next = sc->fxp_desc.tx_list; 2477 (void) fxp_mc_addrs(sc); 2478 sc->fxp_desc.tx_first = sc->fxp_desc.tx_last = txp; 2479 sc->tx_queued = 1; 2480 2481 /* 2482 * Wait until command unit is not active. This should never 2483 * be the case when nothing is queued, but make sure anyway. 2484 */ 2485 count = 100; 2486 while ((CSR_READ_1(sc, FXP_CSR_SCB_RUSCUS) >> 6) == 2487 FXP_SCB_CUS_ACTIVE && --count) 2488 DELAY(10); 2489 if (count == 0) { 2490 device_printf(sc->dev, "command queue timeout\n"); 2491 return; 2492 } 2493 2494 /* 2495 * Start the multicast setup command. 2496 */ 2497 fxp_scb_wait(sc); 2498 bus_dmamap_sync(sc->mcs_tag, sc->mcs_map, BUS_DMASYNC_PREWRITE); 2499 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->mcs_addr); 2500 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2501 2502 ifp->if_timer = 2; 2503 return; 2504 } 2505 2506 static u_int32_t fxp_ucode_d101a[] = D101_A_RCVBUNDLE_UCODE; 2507 static u_int32_t fxp_ucode_d101b0[] = D101_B0_RCVBUNDLE_UCODE; 2508 static u_int32_t fxp_ucode_d101ma[] = D101M_B_RCVBUNDLE_UCODE; 2509 static u_int32_t fxp_ucode_d101s[] = D101S_RCVBUNDLE_UCODE; 2510 static u_int32_t fxp_ucode_d102[] = D102_B_RCVBUNDLE_UCODE; 2511 static u_int32_t fxp_ucode_d102c[] = D102_C_RCVBUNDLE_UCODE; 2512 2513 #define UCODE(x) x, sizeof(x) 2514 2515 struct ucode { 2516 u_int32_t revision; 2517 u_int32_t *ucode; 2518 int length; 2519 u_short int_delay_offset; 2520 u_short bundle_max_offset; 2521 } ucode_table[] = { 2522 { FXP_REV_82558_A4, UCODE(fxp_ucode_d101a), D101_CPUSAVER_DWORD, 0 }, 2523 { FXP_REV_82558_B0, UCODE(fxp_ucode_d101b0), D101_CPUSAVER_DWORD, 0 }, 2524 { FXP_REV_82559_A0, UCODE(fxp_ucode_d101ma), 2525 D101M_CPUSAVER_DWORD, D101M_CPUSAVER_BUNDLE_MAX_DWORD }, 2526 { FXP_REV_82559S_A, UCODE(fxp_ucode_d101s), 2527 D101S_CPUSAVER_DWORD, D101S_CPUSAVER_BUNDLE_MAX_DWORD }, 2528 { FXP_REV_82550, UCODE(fxp_ucode_d102), 2529 D102_B_CPUSAVER_DWORD, D102_B_CPUSAVER_BUNDLE_MAX_DWORD }, 2530 { FXP_REV_82550_C, UCODE(fxp_ucode_d102c), 2531 D102_C_CPUSAVER_DWORD, D102_C_CPUSAVER_BUNDLE_MAX_DWORD }, 2532 { 0, NULL, 0, 0, 0 } 2533 }; 2534 2535 static void 2536 fxp_load_ucode(struct fxp_softc *sc) 2537 { 2538 struct ucode *uc; 2539 struct fxp_cb_ucode *cbp; 2540 2541 for (uc = ucode_table; uc->ucode != NULL; uc++) 2542 if (sc->revision == uc->revision) 2543 break; 2544 if (uc->ucode == NULL) 2545 return; 2546 cbp = (struct fxp_cb_ucode *)sc->fxp_desc.cbl_list; 2547 cbp->cb_status = 0; 2548 cbp->cb_command = FXP_CB_COMMAND_UCODE | FXP_CB_COMMAND_EL; 2549 cbp->link_addr = -1; /* (no) next command */ 2550 memcpy(cbp->ucode, uc->ucode, uc->length); 2551 if (uc->int_delay_offset) 2552 *(u_short *)&cbp->ucode[uc->int_delay_offset] = 2553 sc->tunable_int_delay + sc->tunable_int_delay / 2; 2554 if (uc->bundle_max_offset) 2555 *(u_short *)&cbp->ucode[uc->bundle_max_offset] = 2556 sc->tunable_bundle_max; 2557 /* 2558 * Download the ucode to the chip. 2559 */ 2560 fxp_scb_wait(sc); 2561 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE); 2562 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->fxp_desc.cbl_addr); 2563 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2564 /* ...and wait for it to complete. */ 2565 fxp_dma_wait(&cbp->cb_status, sc); 2566 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_POSTWRITE); 2567 device_printf(sc->dev, 2568 "Microcode loaded, int_delay: %d usec bundle_max: %d\n", 2569 sc->tunable_int_delay, 2570 uc->bundle_max_offset == 0 ? 0 : sc->tunable_bundle_max); 2571 sc->flags |= FXP_FLAG_UCODE; 2572 } 2573 2574 static int 2575 sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high) 2576 { 2577 int error, value; 2578 2579 value = *(int *)arg1; 2580 error = sysctl_handle_int(oidp, &value, 0, req); 2581 if (error || !req->newptr) 2582 return (error); 2583 if (value < low || value > high) 2584 return (EINVAL); 2585 *(int *)arg1 = value; 2586 return (0); 2587 } 2588 2589 /* 2590 * Interrupt delay is expressed in microseconds, a multiplier is used 2591 * to convert this to the appropriate clock ticks before using. 2592 */ 2593 static int 2594 sysctl_hw_fxp_int_delay(SYSCTL_HANDLER_ARGS) 2595 { 2596 return (sysctl_int_range(oidp, arg1, arg2, req, 300, 3000)); 2597 } 2598 2599 static int 2600 sysctl_hw_fxp_bundle_max(SYSCTL_HANDLER_ARGS) 2601 { 2602 return (sysctl_int_range(oidp, arg1, arg2, req, 1, 0xffff)); 2603 } 2604