1 /*- 2 * Copyright (c) 1995, David Greenman 3 * Copyright (c) 2001 Jonathan Lemon <jlemon@freebsd.org> 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice unmodified, this list of conditions, and the following 11 * disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 * 28 */ 29 30 #include <sys/cdefs.h> 31 __FBSDID("$FreeBSD$"); 32 33 /* 34 * Intel EtherExpress Pro/100B PCI Fast Ethernet driver 35 */ 36 37 #ifdef HAVE_KERNEL_OPTION_HEADERS 38 #include "opt_device_polling.h" 39 #endif 40 41 #include <sys/param.h> 42 #include <sys/systm.h> 43 #include <sys/bus.h> 44 #include <sys/endian.h> 45 #include <sys/kernel.h> 46 #include <sys/mbuf.h> 47 #include <sys/module.h> 48 #include <sys/rman.h> 49 #include <sys/socket.h> 50 #include <sys/sockio.h> 51 #include <sys/sysctl.h> 52 53 #include <net/bpf.h> 54 #include <net/ethernet.h> 55 #include <net/if.h> 56 #include <net/if_arp.h> 57 #include <net/if_dl.h> 58 #include <net/if_media.h> 59 #include <net/if_types.h> 60 #include <net/if_vlan_var.h> 61 62 #include <netinet/in.h> 63 #include <netinet/in_systm.h> 64 #include <netinet/ip.h> 65 #include <netinet/tcp.h> 66 #include <netinet/udp.h> 67 68 #include <machine/bus.h> 69 #include <machine/in_cksum.h> 70 #include <machine/resource.h> 71 72 #include <dev/pci/pcivar.h> 73 #include <dev/pci/pcireg.h> /* for PCIM_CMD_xxx */ 74 75 #include <dev/mii/mii.h> 76 #include <dev/mii/miivar.h> 77 78 #include <dev/fxp/if_fxpreg.h> 79 #include <dev/fxp/if_fxpvar.h> 80 #include <dev/fxp/rcvbundl.h> 81 82 MODULE_DEPEND(fxp, pci, 1, 1, 1); 83 MODULE_DEPEND(fxp, ether, 1, 1, 1); 84 MODULE_DEPEND(fxp, miibus, 1, 1, 1); 85 #include "miibus_if.h" 86 87 /* 88 * NOTE! On the Alpha, we have an alignment constraint. The 89 * card DMAs the packet immediately following the RFA. However, 90 * the first thing in the packet is a 14-byte Ethernet header. 91 * This means that the packet is misaligned. To compensate, 92 * we actually offset the RFA 2 bytes into the cluster. This 93 * alignes the packet after the Ethernet header at a 32-bit 94 * boundary. HOWEVER! This means that the RFA is misaligned! 95 */ 96 #define RFA_ALIGNMENT_FUDGE 2 97 98 /* 99 * Set initial transmit threshold at 64 (512 bytes). This is 100 * increased by 64 (512 bytes) at a time, to maximum of 192 101 * (1536 bytes), if an underrun occurs. 102 */ 103 static int tx_threshold = 64; 104 105 /* 106 * The configuration byte map has several undefined fields which 107 * must be one or must be zero. Set up a template for these bits 108 * only, (assuming a 82557 chip) leaving the actual configuration 109 * to fxp_init. 110 * 111 * See struct fxp_cb_config for the bit definitions. 112 */ 113 static u_char fxp_cb_config_template[] = { 114 0x0, 0x0, /* cb_status */ 115 0x0, 0x0, /* cb_command */ 116 0x0, 0x0, 0x0, 0x0, /* link_addr */ 117 0x0, /* 0 */ 118 0x0, /* 1 */ 119 0x0, /* 2 */ 120 0x0, /* 3 */ 121 0x0, /* 4 */ 122 0x0, /* 5 */ 123 0x32, /* 6 */ 124 0x0, /* 7 */ 125 0x0, /* 8 */ 126 0x0, /* 9 */ 127 0x6, /* 10 */ 128 0x0, /* 11 */ 129 0x0, /* 12 */ 130 0x0, /* 13 */ 131 0xf2, /* 14 */ 132 0x48, /* 15 */ 133 0x0, /* 16 */ 134 0x40, /* 17 */ 135 0xf0, /* 18 */ 136 0x0, /* 19 */ 137 0x3f, /* 20 */ 138 0x5 /* 21 */ 139 }; 140 141 struct fxp_ident { 142 uint16_t devid; 143 int16_t revid; /* -1 matches anything */ 144 char *name; 145 }; 146 147 /* 148 * Claim various Intel PCI device identifiers for this driver. The 149 * sub-vendor and sub-device field are extensively used to identify 150 * particular variants, but we don't currently differentiate between 151 * them. 152 */ 153 static struct fxp_ident fxp_ident_table[] = { 154 { 0x1029, -1, "Intel 82559 PCI/CardBus Pro/100" }, 155 { 0x1030, -1, "Intel 82559 Pro/100 Ethernet" }, 156 { 0x1031, -1, "Intel 82801CAM (ICH3) Pro/100 VE Ethernet" }, 157 { 0x1032, -1, "Intel 82801CAM (ICH3) Pro/100 VE Ethernet" }, 158 { 0x1033, -1, "Intel 82801CAM (ICH3) Pro/100 VM Ethernet" }, 159 { 0x1034, -1, "Intel 82801CAM (ICH3) Pro/100 VM Ethernet" }, 160 { 0x1035, -1, "Intel 82801CAM (ICH3) Pro/100 Ethernet" }, 161 { 0x1036, -1, "Intel 82801CAM (ICH3) Pro/100 Ethernet" }, 162 { 0x1037, -1, "Intel 82801CAM (ICH3) Pro/100 Ethernet" }, 163 { 0x1038, -1, "Intel 82801CAM (ICH3) Pro/100 VM Ethernet" }, 164 { 0x1039, -1, "Intel 82801DB (ICH4) Pro/100 VE Ethernet" }, 165 { 0x103A, -1, "Intel 82801DB (ICH4) Pro/100 Ethernet" }, 166 { 0x103B, -1, "Intel 82801DB (ICH4) Pro/100 VM Ethernet" }, 167 { 0x103C, -1, "Intel 82801DB (ICH4) Pro/100 Ethernet" }, 168 { 0x103D, -1, "Intel 82801DB (ICH4) Pro/100 VE Ethernet" }, 169 { 0x103E, -1, "Intel 82801DB (ICH4) Pro/100 VM Ethernet" }, 170 { 0x1050, -1, "Intel 82801BA (D865) Pro/100 VE Ethernet" }, 171 { 0x1051, -1, "Intel 82562ET (ICH5/ICH5R) Pro/100 VE Ethernet" }, 172 { 0x1059, -1, "Intel 82551QM Pro/100 M Mobile Connection" }, 173 { 0x1064, -1, "Intel 82562EZ (ICH6)" }, 174 { 0x1065, -1, "Intel 82562ET/EZ/GT/GZ PRO/100 VE Ethernet" }, 175 { 0x1068, -1, "Intel 82801FBM (ICH6-M) Pro/100 VE Ethernet" }, 176 { 0x1069, -1, "Intel 82562EM/EX/GX Pro/100 Ethernet" }, 177 { 0x1091, -1, "Intel 82562GX Pro/100 Ethernet" }, 178 { 0x1092, -1, "Intel Pro/100 VE Network Connection" }, 179 { 0x1093, -1, "Intel Pro/100 VM Network Connection" }, 180 { 0x1094, -1, "Intel Pro/100 946GZ (ICH7) Network Connection" }, 181 { 0x1209, -1, "Intel 82559ER Embedded 10/100 Ethernet" }, 182 { 0x1229, 0x01, "Intel 82557 Pro/100 Ethernet" }, 183 { 0x1229, 0x02, "Intel 82557 Pro/100 Ethernet" }, 184 { 0x1229, 0x03, "Intel 82557 Pro/100 Ethernet" }, 185 { 0x1229, 0x04, "Intel 82558 Pro/100 Ethernet" }, 186 { 0x1229, 0x05, "Intel 82558 Pro/100 Ethernet" }, 187 { 0x1229, 0x06, "Intel 82559 Pro/100 Ethernet" }, 188 { 0x1229, 0x07, "Intel 82559 Pro/100 Ethernet" }, 189 { 0x1229, 0x08, "Intel 82559 Pro/100 Ethernet" }, 190 { 0x1229, 0x09, "Intel 82559ER Pro/100 Ethernet" }, 191 { 0x1229, 0x0c, "Intel 82550 Pro/100 Ethernet" }, 192 { 0x1229, 0x0d, "Intel 82550 Pro/100 Ethernet" }, 193 { 0x1229, 0x0e, "Intel 82550 Pro/100 Ethernet" }, 194 { 0x1229, 0x0f, "Intel 82551 Pro/100 Ethernet" }, 195 { 0x1229, 0x10, "Intel 82551 Pro/100 Ethernet" }, 196 { 0x1229, -1, "Intel 82557/8/9 Pro/100 Ethernet" }, 197 { 0x2449, -1, "Intel 82801BA/CAM (ICH2/3) Pro/100 Ethernet" }, 198 { 0x27dc, -1, "Intel 82801GB (ICH7) 10/100 Ethernet" }, 199 { 0, -1, NULL }, 200 }; 201 202 #ifdef FXP_IP_CSUM_WAR 203 #define FXP_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 204 #else 205 #define FXP_CSUM_FEATURES (CSUM_TCP | CSUM_UDP) 206 #endif 207 208 static int fxp_probe(device_t dev); 209 static int fxp_attach(device_t dev); 210 static int fxp_detach(device_t dev); 211 static int fxp_shutdown(device_t dev); 212 static int fxp_suspend(device_t dev); 213 static int fxp_resume(device_t dev); 214 215 static void fxp_intr(void *xsc); 216 static void fxp_rxcsum(struct fxp_softc *sc, struct ifnet *ifp, 217 struct mbuf *m, uint16_t status, int pos); 218 static void fxp_intr_body(struct fxp_softc *sc, struct ifnet *ifp, 219 uint8_t statack, int count); 220 static void fxp_init(void *xsc); 221 static void fxp_init_body(struct fxp_softc *sc); 222 static void fxp_tick(void *xsc); 223 static void fxp_start(struct ifnet *ifp); 224 static void fxp_start_body(struct ifnet *ifp); 225 static int fxp_encap(struct fxp_softc *sc, struct mbuf **m_head); 226 static void fxp_txeof(struct fxp_softc *sc); 227 static void fxp_stop(struct fxp_softc *sc); 228 static void fxp_release(struct fxp_softc *sc); 229 static int fxp_ioctl(struct ifnet *ifp, u_long command, 230 caddr_t data); 231 static void fxp_watchdog(struct fxp_softc *sc); 232 static void fxp_add_rfabuf(struct fxp_softc *sc, 233 struct fxp_rx *rxp); 234 static void fxp_discard_rfabuf(struct fxp_softc *sc, 235 struct fxp_rx *rxp); 236 static int fxp_new_rfabuf(struct fxp_softc *sc, 237 struct fxp_rx *rxp); 238 static int fxp_mc_addrs(struct fxp_softc *sc); 239 static void fxp_mc_setup(struct fxp_softc *sc); 240 static uint16_t fxp_eeprom_getword(struct fxp_softc *sc, int offset, 241 int autosize); 242 static void fxp_eeprom_putword(struct fxp_softc *sc, int offset, 243 uint16_t data); 244 static void fxp_autosize_eeprom(struct fxp_softc *sc); 245 static void fxp_read_eeprom(struct fxp_softc *sc, u_short *data, 246 int offset, int words); 247 static void fxp_write_eeprom(struct fxp_softc *sc, u_short *data, 248 int offset, int words); 249 static int fxp_ifmedia_upd(struct ifnet *ifp); 250 static void fxp_ifmedia_sts(struct ifnet *ifp, 251 struct ifmediareq *ifmr); 252 static int fxp_serial_ifmedia_upd(struct ifnet *ifp); 253 static void fxp_serial_ifmedia_sts(struct ifnet *ifp, 254 struct ifmediareq *ifmr); 255 static int fxp_miibus_readreg(device_t dev, int phy, int reg); 256 static void fxp_miibus_writereg(device_t dev, int phy, int reg, 257 int value); 258 static void fxp_load_ucode(struct fxp_softc *sc); 259 static int sysctl_int_range(SYSCTL_HANDLER_ARGS, 260 int low, int high); 261 static int sysctl_hw_fxp_bundle_max(SYSCTL_HANDLER_ARGS); 262 static int sysctl_hw_fxp_int_delay(SYSCTL_HANDLER_ARGS); 263 static void fxp_scb_wait(struct fxp_softc *sc); 264 static void fxp_scb_cmd(struct fxp_softc *sc, int cmd); 265 static void fxp_dma_wait(struct fxp_softc *sc, 266 volatile uint16_t *status, bus_dma_tag_t dmat, 267 bus_dmamap_t map); 268 269 static device_method_t fxp_methods[] = { 270 /* Device interface */ 271 DEVMETHOD(device_probe, fxp_probe), 272 DEVMETHOD(device_attach, fxp_attach), 273 DEVMETHOD(device_detach, fxp_detach), 274 DEVMETHOD(device_shutdown, fxp_shutdown), 275 DEVMETHOD(device_suspend, fxp_suspend), 276 DEVMETHOD(device_resume, fxp_resume), 277 278 /* MII interface */ 279 DEVMETHOD(miibus_readreg, fxp_miibus_readreg), 280 DEVMETHOD(miibus_writereg, fxp_miibus_writereg), 281 282 { 0, 0 } 283 }; 284 285 static driver_t fxp_driver = { 286 "fxp", 287 fxp_methods, 288 sizeof(struct fxp_softc), 289 }; 290 291 static devclass_t fxp_devclass; 292 293 DRIVER_MODULE(fxp, pci, fxp_driver, fxp_devclass, 0, 0); 294 DRIVER_MODULE(fxp, cardbus, fxp_driver, fxp_devclass, 0, 0); 295 DRIVER_MODULE(miibus, fxp, miibus_driver, miibus_devclass, 0, 0); 296 297 static struct resource_spec fxp_res_spec_mem[] = { 298 { SYS_RES_MEMORY, FXP_PCI_MMBA, RF_ACTIVE }, 299 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE }, 300 { -1, 0 } 301 }; 302 303 static struct resource_spec fxp_res_spec_io[] = { 304 { SYS_RES_IOPORT, FXP_PCI_IOBA, RF_ACTIVE }, 305 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE }, 306 { -1, 0 } 307 }; 308 309 /* 310 * Wait for the previous command to be accepted (but not necessarily 311 * completed). 312 */ 313 static void 314 fxp_scb_wait(struct fxp_softc *sc) 315 { 316 union { 317 uint16_t w; 318 uint8_t b[2]; 319 } flowctl; 320 int i = 10000; 321 322 while (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) && --i) 323 DELAY(2); 324 if (i == 0) { 325 flowctl.b[0] = CSR_READ_1(sc, FXP_CSR_FLOWCONTROL); 326 flowctl.b[1] = CSR_READ_1(sc, FXP_CSR_FLOWCONTROL + 1); 327 device_printf(sc->dev, "SCB timeout: 0x%x 0x%x 0x%x 0x%x\n", 328 CSR_READ_1(sc, FXP_CSR_SCB_COMMAND), 329 CSR_READ_1(sc, FXP_CSR_SCB_STATACK), 330 CSR_READ_1(sc, FXP_CSR_SCB_RUSCUS), flowctl.w); 331 } 332 } 333 334 static void 335 fxp_scb_cmd(struct fxp_softc *sc, int cmd) 336 { 337 338 if (cmd == FXP_SCB_COMMAND_CU_RESUME && sc->cu_resume_bug) { 339 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_CB_COMMAND_NOP); 340 fxp_scb_wait(sc); 341 } 342 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, cmd); 343 } 344 345 static void 346 fxp_dma_wait(struct fxp_softc *sc, volatile uint16_t *status, 347 bus_dma_tag_t dmat, bus_dmamap_t map) 348 { 349 int i = 10000; 350 351 bus_dmamap_sync(dmat, map, BUS_DMASYNC_POSTREAD); 352 while (!(le16toh(*status) & FXP_CB_STATUS_C) && --i) { 353 DELAY(2); 354 bus_dmamap_sync(dmat, map, BUS_DMASYNC_POSTREAD); 355 } 356 if (i == 0) 357 device_printf(sc->dev, "DMA timeout\n"); 358 } 359 360 /* 361 * Return identification string if this device is ours. 362 */ 363 static int 364 fxp_probe(device_t dev) 365 { 366 uint16_t devid; 367 uint8_t revid; 368 struct fxp_ident *ident; 369 370 if (pci_get_vendor(dev) == FXP_VENDORID_INTEL) { 371 devid = pci_get_device(dev); 372 revid = pci_get_revid(dev); 373 for (ident = fxp_ident_table; ident->name != NULL; ident++) { 374 if (ident->devid == devid && 375 (ident->revid == revid || ident->revid == -1)) { 376 device_set_desc(dev, ident->name); 377 return (BUS_PROBE_DEFAULT); 378 } 379 } 380 } 381 return (ENXIO); 382 } 383 384 static void 385 fxp_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error) 386 { 387 uint32_t *addr; 388 389 if (error) 390 return; 391 392 KASSERT(nseg == 1, ("too many DMA segments, %d should be 1", nseg)); 393 addr = arg; 394 *addr = segs->ds_addr; 395 } 396 397 static int 398 fxp_attach(device_t dev) 399 { 400 struct fxp_softc *sc; 401 struct fxp_cb_tx *tcbp; 402 struct fxp_tx *txp; 403 struct fxp_rx *rxp; 404 struct ifnet *ifp; 405 uint32_t val; 406 uint16_t data, myea[ETHER_ADDR_LEN / 2]; 407 u_char eaddr[ETHER_ADDR_LEN]; 408 int i, pmc, prefer_iomap; 409 int error; 410 411 error = 0; 412 sc = device_get_softc(dev); 413 sc->dev = dev; 414 mtx_init(&sc->sc_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 415 MTX_DEF); 416 callout_init_mtx(&sc->stat_ch, &sc->sc_mtx, 0); 417 ifmedia_init(&sc->sc_media, 0, fxp_serial_ifmedia_upd, 418 fxp_serial_ifmedia_sts); 419 420 ifp = sc->ifp = if_alloc(IFT_ETHER); 421 if (ifp == NULL) { 422 device_printf(dev, "can not if_alloc()\n"); 423 error = ENOSPC; 424 goto fail; 425 } 426 427 /* 428 * Enable bus mastering. 429 */ 430 pci_enable_busmaster(dev); 431 val = pci_read_config(dev, PCIR_COMMAND, 2); 432 433 /* 434 * Figure out which we should try first - memory mapping or i/o mapping? 435 * We default to memory mapping. Then we accept an override from the 436 * command line. Then we check to see which one is enabled. 437 */ 438 prefer_iomap = 0; 439 resource_int_value(device_get_name(dev), device_get_unit(dev), 440 "prefer_iomap", &prefer_iomap); 441 if (prefer_iomap) 442 sc->fxp_spec = fxp_res_spec_io; 443 else 444 sc->fxp_spec = fxp_res_spec_mem; 445 446 error = bus_alloc_resources(dev, sc->fxp_spec, sc->fxp_res); 447 if (error) { 448 if (sc->fxp_spec == fxp_res_spec_mem) 449 sc->fxp_spec = fxp_res_spec_io; 450 else 451 sc->fxp_spec = fxp_res_spec_mem; 452 error = bus_alloc_resources(dev, sc->fxp_spec, sc->fxp_res); 453 } 454 if (error) { 455 device_printf(dev, "could not allocate resources\n"); 456 error = ENXIO; 457 goto fail; 458 } 459 460 if (bootverbose) { 461 device_printf(dev, "using %s space register mapping\n", 462 sc->fxp_spec == fxp_res_spec_mem ? "memory" : "I/O"); 463 } 464 465 /* 466 * Reset to a stable state. 467 */ 468 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET); 469 DELAY(10); 470 471 /* 472 * Find out how large of an SEEPROM we have. 473 */ 474 fxp_autosize_eeprom(sc); 475 476 /* 477 * Find out the chip revision; lump all 82557 revs together. 478 */ 479 fxp_read_eeprom(sc, &data, 5, 1); 480 if ((data >> 8) == 1) 481 sc->revision = FXP_REV_82557; 482 else 483 sc->revision = pci_get_revid(dev); 484 485 /* 486 * Check availability of WOL. 82559ER does not support WOL. 487 */ 488 if (sc->revision >= FXP_REV_82558_A4 && 489 sc->revision != FXP_REV_82559S_A) { 490 fxp_read_eeprom(sc, &data, 10, 1); 491 if ((data & 0x20) != 0 && 492 pci_find_extcap(sc->dev, PCIY_PMG, &pmc) == 0) 493 sc->flags |= FXP_FLAG_WOLCAP; 494 } 495 496 /* 497 * Determine whether we must use the 503 serial interface. 498 */ 499 fxp_read_eeprom(sc, &data, 6, 1); 500 if (sc->revision == FXP_REV_82557 && (data & FXP_PHY_DEVICE_MASK) != 0 501 && (data & FXP_PHY_SERIAL_ONLY)) 502 sc->flags |= FXP_FLAG_SERIAL_MEDIA; 503 504 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 505 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 506 OID_AUTO, "int_delay", CTLTYPE_INT | CTLFLAG_RW, 507 &sc->tunable_int_delay, 0, sysctl_hw_fxp_int_delay, "I", 508 "FXP driver receive interrupt microcode bundling delay"); 509 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 510 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 511 OID_AUTO, "bundle_max", CTLTYPE_INT | CTLFLAG_RW, 512 &sc->tunable_bundle_max, 0, sysctl_hw_fxp_bundle_max, "I", 513 "FXP driver receive interrupt microcode bundle size limit"); 514 SYSCTL_ADD_INT(device_get_sysctl_ctx(dev), 515 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 516 OID_AUTO, "rnr", CTLFLAG_RD, &sc->rnr, 0, 517 "FXP RNR events"); 518 SYSCTL_ADD_INT(device_get_sysctl_ctx(dev), 519 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 520 OID_AUTO, "noflow", CTLFLAG_RW, &sc->tunable_noflow, 0, 521 "FXP flow control disabled"); 522 523 /* 524 * Pull in device tunables. 525 */ 526 sc->tunable_int_delay = TUNABLE_INT_DELAY; 527 sc->tunable_bundle_max = TUNABLE_BUNDLE_MAX; 528 sc->tunable_noflow = 1; 529 (void) resource_int_value(device_get_name(dev), device_get_unit(dev), 530 "int_delay", &sc->tunable_int_delay); 531 (void) resource_int_value(device_get_name(dev), device_get_unit(dev), 532 "bundle_max", &sc->tunable_bundle_max); 533 (void) resource_int_value(device_get_name(dev), device_get_unit(dev), 534 "noflow", &sc->tunable_noflow); 535 sc->rnr = 0; 536 537 /* 538 * Enable workarounds for certain chip revision deficiencies. 539 * 540 * Systems based on the ICH2/ICH2-M chip from Intel, and possibly 541 * some systems based a normal 82559 design, have a defect where 542 * the chip can cause a PCI protocol violation if it receives 543 * a CU_RESUME command when it is entering the IDLE state. The 544 * workaround is to disable Dynamic Standby Mode, so the chip never 545 * deasserts CLKRUN#, and always remains in an active state. 546 * 547 * See Intel 82801BA/82801BAM Specification Update, Errata #30. 548 */ 549 i = pci_get_device(dev); 550 if (i == 0x2449 || (i > 0x1030 && i < 0x1039) || 551 sc->revision >= FXP_REV_82559_A0) { 552 fxp_read_eeprom(sc, &data, 10, 1); 553 if (data & 0x02) { /* STB enable */ 554 uint16_t cksum; 555 int i; 556 557 device_printf(dev, 558 "Disabling dynamic standby mode in EEPROM\n"); 559 data &= ~0x02; 560 fxp_write_eeprom(sc, &data, 10, 1); 561 device_printf(dev, "New EEPROM ID: 0x%x\n", data); 562 cksum = 0; 563 for (i = 0; i < (1 << sc->eeprom_size) - 1; i++) { 564 fxp_read_eeprom(sc, &data, i, 1); 565 cksum += data; 566 } 567 i = (1 << sc->eeprom_size) - 1; 568 cksum = 0xBABA - cksum; 569 fxp_read_eeprom(sc, &data, i, 1); 570 fxp_write_eeprom(sc, &cksum, i, 1); 571 device_printf(dev, 572 "EEPROM checksum @ 0x%x: 0x%x -> 0x%x\n", 573 i, data, cksum); 574 #if 1 575 /* 576 * If the user elects to continue, try the software 577 * workaround, as it is better than nothing. 578 */ 579 sc->flags |= FXP_FLAG_CU_RESUME_BUG; 580 #endif 581 } 582 } 583 584 /* 585 * If we are not a 82557 chip, we can enable extended features. 586 */ 587 if (sc->revision != FXP_REV_82557) { 588 /* 589 * If MWI is enabled in the PCI configuration, and there 590 * is a valid cacheline size (8 or 16 dwords), then tell 591 * the board to turn on MWI. 592 */ 593 if (val & PCIM_CMD_MWRICEN && 594 pci_read_config(dev, PCIR_CACHELNSZ, 1) != 0) 595 sc->flags |= FXP_FLAG_MWI_ENABLE; 596 597 /* turn on the extended TxCB feature */ 598 sc->flags |= FXP_FLAG_EXT_TXCB; 599 600 /* enable reception of long frames for VLAN */ 601 sc->flags |= FXP_FLAG_LONG_PKT_EN; 602 } else { 603 /* a hack to get long VLAN frames on a 82557 */ 604 sc->flags |= FXP_FLAG_SAVE_BAD; 605 } 606 607 /* For 82559 or later chips, Rx checksum offload is supported. */ 608 if (sc->revision >= FXP_REV_82559_A0) 609 sc->flags |= FXP_FLAG_82559_RXCSUM; 610 /* 611 * Enable use of extended RFDs and TCBs for 82550 612 * and later chips. Note: we need extended TXCB support 613 * too, but that's already enabled by the code above. 614 * Be careful to do this only on the right devices. 615 */ 616 if (sc->revision == FXP_REV_82550 || sc->revision == FXP_REV_82550_C || 617 sc->revision == FXP_REV_82551_E || sc->revision == FXP_REV_82551_F 618 || sc->revision == FXP_REV_82551_10) { 619 sc->rfa_size = sizeof (struct fxp_rfa); 620 sc->tx_cmd = FXP_CB_COMMAND_IPCBXMIT; 621 sc->flags |= FXP_FLAG_EXT_RFA; 622 /* Use extended RFA instead of 82559 checksum mode. */ 623 sc->flags &= ~FXP_FLAG_82559_RXCSUM; 624 } else { 625 sc->rfa_size = sizeof (struct fxp_rfa) - FXP_RFAX_LEN; 626 sc->tx_cmd = FXP_CB_COMMAND_XMIT; 627 } 628 629 /* 630 * Allocate DMA tags and DMA safe memory. 631 */ 632 sc->maxtxseg = FXP_NTXSEG; 633 sc->maxsegsize = MCLBYTES; 634 if (sc->flags & FXP_FLAG_EXT_RFA) { 635 sc->maxtxseg--; 636 sc->maxsegsize = FXP_TSO_SEGSIZE; 637 } 638 error = bus_dma_tag_create(bus_get_dma_tag(dev), 2, 0, 639 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 640 sc->maxsegsize * sc->maxtxseg + sizeof(struct ether_vlan_header), 641 sc->maxtxseg, sc->maxsegsize, 0, 642 busdma_lock_mutex, &Giant, &sc->fxp_mtag); 643 if (error) { 644 device_printf(dev, "could not allocate dma tag\n"); 645 goto fail; 646 } 647 648 error = bus_dma_tag_create(bus_get_dma_tag(dev), 4, 0, 649 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 650 sizeof(struct fxp_stats), 1, sizeof(struct fxp_stats), 0, 651 busdma_lock_mutex, &Giant, &sc->fxp_stag); 652 if (error) { 653 device_printf(dev, "could not allocate dma tag\n"); 654 goto fail; 655 } 656 657 error = bus_dmamem_alloc(sc->fxp_stag, (void **)&sc->fxp_stats, 658 BUS_DMA_NOWAIT | BUS_DMA_ZERO, &sc->fxp_smap); 659 if (error) 660 goto fail; 661 error = bus_dmamap_load(sc->fxp_stag, sc->fxp_smap, sc->fxp_stats, 662 sizeof(struct fxp_stats), fxp_dma_map_addr, &sc->stats_addr, 0); 663 if (error) { 664 device_printf(dev, "could not map the stats buffer\n"); 665 goto fail; 666 } 667 668 error = bus_dma_tag_create(bus_get_dma_tag(dev), 4, 0, 669 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 670 FXP_TXCB_SZ, 1, FXP_TXCB_SZ, 0, 671 busdma_lock_mutex, &Giant, &sc->cbl_tag); 672 if (error) { 673 device_printf(dev, "could not allocate dma tag\n"); 674 goto fail; 675 } 676 677 error = bus_dmamem_alloc(sc->cbl_tag, (void **)&sc->fxp_desc.cbl_list, 678 BUS_DMA_NOWAIT | BUS_DMA_ZERO, &sc->cbl_map); 679 if (error) 680 goto fail; 681 682 error = bus_dmamap_load(sc->cbl_tag, sc->cbl_map, 683 sc->fxp_desc.cbl_list, FXP_TXCB_SZ, fxp_dma_map_addr, 684 &sc->fxp_desc.cbl_addr, 0); 685 if (error) { 686 device_printf(dev, "could not map DMA memory\n"); 687 goto fail; 688 } 689 690 error = bus_dma_tag_create(bus_get_dma_tag(dev), 4, 0, 691 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 692 sizeof(struct fxp_cb_mcs), 1, sizeof(struct fxp_cb_mcs), 0, 693 busdma_lock_mutex, &Giant, &sc->mcs_tag); 694 if (error) { 695 device_printf(dev, "could not allocate dma tag\n"); 696 goto fail; 697 } 698 699 error = bus_dmamem_alloc(sc->mcs_tag, (void **)&sc->mcsp, 700 BUS_DMA_NOWAIT, &sc->mcs_map); 701 if (error) 702 goto fail; 703 error = bus_dmamap_load(sc->mcs_tag, sc->mcs_map, sc->mcsp, 704 sizeof(struct fxp_cb_mcs), fxp_dma_map_addr, &sc->mcs_addr, 0); 705 if (error) { 706 device_printf(dev, "can't map the multicast setup command\n"); 707 goto fail; 708 } 709 710 /* 711 * Pre-allocate the TX DMA maps and setup the pointers to 712 * the TX command blocks. 713 */ 714 txp = sc->fxp_desc.tx_list; 715 tcbp = sc->fxp_desc.cbl_list; 716 for (i = 0; i < FXP_NTXCB; i++) { 717 txp[i].tx_cb = tcbp + i; 718 error = bus_dmamap_create(sc->fxp_mtag, 0, &txp[i].tx_map); 719 if (error) { 720 device_printf(dev, "can't create DMA map for TX\n"); 721 goto fail; 722 } 723 } 724 error = bus_dmamap_create(sc->fxp_mtag, 0, &sc->spare_map); 725 if (error) { 726 device_printf(dev, "can't create spare DMA map\n"); 727 goto fail; 728 } 729 730 /* 731 * Pre-allocate our receive buffers. 732 */ 733 sc->fxp_desc.rx_head = sc->fxp_desc.rx_tail = NULL; 734 for (i = 0; i < FXP_NRFABUFS; i++) { 735 rxp = &sc->fxp_desc.rx_list[i]; 736 error = bus_dmamap_create(sc->fxp_mtag, 0, &rxp->rx_map); 737 if (error) { 738 device_printf(dev, "can't create DMA map for RX\n"); 739 goto fail; 740 } 741 if (fxp_new_rfabuf(sc, rxp) != 0) { 742 error = ENOMEM; 743 goto fail; 744 } 745 fxp_add_rfabuf(sc, rxp); 746 } 747 748 /* 749 * Read MAC address. 750 */ 751 fxp_read_eeprom(sc, myea, 0, 3); 752 eaddr[0] = myea[0] & 0xff; 753 eaddr[1] = myea[0] >> 8; 754 eaddr[2] = myea[1] & 0xff; 755 eaddr[3] = myea[1] >> 8; 756 eaddr[4] = myea[2] & 0xff; 757 eaddr[5] = myea[2] >> 8; 758 if (bootverbose) { 759 device_printf(dev, "PCI IDs: %04x %04x %04x %04x %04x\n", 760 pci_get_vendor(dev), pci_get_device(dev), 761 pci_get_subvendor(dev), pci_get_subdevice(dev), 762 pci_get_revid(dev)); 763 fxp_read_eeprom(sc, &data, 10, 1); 764 device_printf(dev, "Dynamic Standby mode is %s\n", 765 data & 0x02 ? "enabled" : "disabled"); 766 } 767 768 /* 769 * If this is only a 10Mbps device, then there is no MII, and 770 * the PHY will use a serial interface instead. 771 * 772 * The Seeq 80c24 AutoDUPLEX(tm) Ethernet Interface Adapter 773 * doesn't have a programming interface of any sort. The 774 * media is sensed automatically based on how the link partner 775 * is configured. This is, in essence, manual configuration. 776 */ 777 if (sc->flags & FXP_FLAG_SERIAL_MEDIA) { 778 ifmedia_add(&sc->sc_media, IFM_ETHER|IFM_MANUAL, 0, NULL); 779 ifmedia_set(&sc->sc_media, IFM_ETHER|IFM_MANUAL); 780 } else { 781 if (mii_phy_probe(dev, &sc->miibus, fxp_ifmedia_upd, 782 fxp_ifmedia_sts)) { 783 device_printf(dev, "MII without any PHY!\n"); 784 error = ENXIO; 785 goto fail; 786 } 787 } 788 789 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 790 ifp->if_init = fxp_init; 791 ifp->if_softc = sc; 792 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 793 ifp->if_ioctl = fxp_ioctl; 794 ifp->if_start = fxp_start; 795 796 ifp->if_capabilities = ifp->if_capenable = 0; 797 798 /* Enable checksum offload/TSO for 82550 or better chips */ 799 if (sc->flags & FXP_FLAG_EXT_RFA) { 800 ifp->if_hwassist = FXP_CSUM_FEATURES | CSUM_TSO; 801 ifp->if_capabilities |= IFCAP_HWCSUM | IFCAP_TSO4; 802 ifp->if_capenable |= IFCAP_HWCSUM | IFCAP_TSO4; 803 } 804 805 if (sc->flags & FXP_FLAG_82559_RXCSUM) { 806 ifp->if_capabilities |= IFCAP_RXCSUM; 807 ifp->if_capenable |= IFCAP_RXCSUM; 808 } 809 810 if (sc->flags & FXP_FLAG_WOLCAP) { 811 ifp->if_capabilities |= IFCAP_WOL_MAGIC; 812 ifp->if_capenable |= IFCAP_WOL_MAGIC; 813 } 814 815 #ifdef DEVICE_POLLING 816 /* Inform the world we support polling. */ 817 ifp->if_capabilities |= IFCAP_POLLING; 818 #endif 819 820 /* 821 * Attach the interface. 822 */ 823 ether_ifattach(ifp, eaddr); 824 825 /* 826 * Tell the upper layer(s) we support long frames. 827 * Must appear after the call to ether_ifattach() because 828 * ether_ifattach() sets ifi_hdrlen to the default value. 829 */ 830 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 831 ifp->if_capabilities |= IFCAP_VLAN_MTU; 832 ifp->if_capenable |= IFCAP_VLAN_MTU; /* the hw bits already set */ 833 if ((sc->flags & FXP_FLAG_EXT_RFA) != 0) { 834 ifp->if_capabilities |= IFCAP_VLAN_HWTAGGING | 835 IFCAP_VLAN_HWCSUM; 836 ifp->if_capenable |= IFCAP_VLAN_HWTAGGING | 837 IFCAP_VLAN_HWCSUM; 838 } 839 840 /* 841 * Let the system queue as many packets as we have available 842 * TX descriptors. 843 */ 844 IFQ_SET_MAXLEN(&ifp->if_snd, FXP_NTXCB - 1); 845 ifp->if_snd.ifq_drv_maxlen = FXP_NTXCB - 1; 846 IFQ_SET_READY(&ifp->if_snd); 847 848 /* 849 * Hook our interrupt after all initialization is complete. 850 */ 851 error = bus_setup_intr(dev, sc->fxp_res[1], INTR_TYPE_NET | INTR_MPSAFE, 852 NULL, fxp_intr, sc, &sc->ih); 853 if (error) { 854 device_printf(dev, "could not setup irq\n"); 855 ether_ifdetach(sc->ifp); 856 goto fail; 857 } 858 859 /* 860 * Configure hardware to reject magic frames otherwise 861 * system will hang on recipt of magic frames. 862 */ 863 if ((sc->flags & FXP_FLAG_WOLCAP) != 0) { 864 FXP_LOCK(sc); 865 /* Clear wakeup events. */ 866 CSR_WRITE_1(sc, FXP_CSR_PMDR, CSR_READ_1(sc, FXP_CSR_PMDR)); 867 fxp_init_body(sc); 868 fxp_stop(sc); 869 FXP_UNLOCK(sc); 870 } 871 872 fail: 873 if (error) 874 fxp_release(sc); 875 return (error); 876 } 877 878 /* 879 * Release all resources. The softc lock should not be held and the 880 * interrupt should already be torn down. 881 */ 882 static void 883 fxp_release(struct fxp_softc *sc) 884 { 885 struct fxp_rx *rxp; 886 struct fxp_tx *txp; 887 int i; 888 889 FXP_LOCK_ASSERT(sc, MA_NOTOWNED); 890 KASSERT(sc->ih == NULL, 891 ("fxp_release() called with intr handle still active")); 892 if (sc->miibus) 893 device_delete_child(sc->dev, sc->miibus); 894 bus_generic_detach(sc->dev); 895 ifmedia_removeall(&sc->sc_media); 896 if (sc->fxp_desc.cbl_list) { 897 bus_dmamap_unload(sc->cbl_tag, sc->cbl_map); 898 bus_dmamem_free(sc->cbl_tag, sc->fxp_desc.cbl_list, 899 sc->cbl_map); 900 } 901 if (sc->fxp_stats) { 902 bus_dmamap_unload(sc->fxp_stag, sc->fxp_smap); 903 bus_dmamem_free(sc->fxp_stag, sc->fxp_stats, sc->fxp_smap); 904 } 905 if (sc->mcsp) { 906 bus_dmamap_unload(sc->mcs_tag, sc->mcs_map); 907 bus_dmamem_free(sc->mcs_tag, sc->mcsp, sc->mcs_map); 908 } 909 bus_release_resources(sc->dev, sc->fxp_spec, sc->fxp_res); 910 if (sc->fxp_mtag) { 911 for (i = 0; i < FXP_NRFABUFS; i++) { 912 rxp = &sc->fxp_desc.rx_list[i]; 913 if (rxp->rx_mbuf != NULL) { 914 bus_dmamap_sync(sc->fxp_mtag, rxp->rx_map, 915 BUS_DMASYNC_POSTREAD); 916 bus_dmamap_unload(sc->fxp_mtag, rxp->rx_map); 917 m_freem(rxp->rx_mbuf); 918 } 919 bus_dmamap_destroy(sc->fxp_mtag, rxp->rx_map); 920 } 921 bus_dmamap_destroy(sc->fxp_mtag, sc->spare_map); 922 for (i = 0; i < FXP_NTXCB; i++) { 923 txp = &sc->fxp_desc.tx_list[i]; 924 if (txp->tx_mbuf != NULL) { 925 bus_dmamap_sync(sc->fxp_mtag, txp->tx_map, 926 BUS_DMASYNC_POSTWRITE); 927 bus_dmamap_unload(sc->fxp_mtag, txp->tx_map); 928 m_freem(txp->tx_mbuf); 929 } 930 bus_dmamap_destroy(sc->fxp_mtag, txp->tx_map); 931 } 932 bus_dma_tag_destroy(sc->fxp_mtag); 933 } 934 if (sc->fxp_stag) 935 bus_dma_tag_destroy(sc->fxp_stag); 936 if (sc->cbl_tag) 937 bus_dma_tag_destroy(sc->cbl_tag); 938 if (sc->mcs_tag) 939 bus_dma_tag_destroy(sc->mcs_tag); 940 if (sc->ifp) 941 if_free(sc->ifp); 942 943 mtx_destroy(&sc->sc_mtx); 944 } 945 946 /* 947 * Detach interface. 948 */ 949 static int 950 fxp_detach(device_t dev) 951 { 952 struct fxp_softc *sc = device_get_softc(dev); 953 954 #ifdef DEVICE_POLLING 955 if (sc->ifp->if_capenable & IFCAP_POLLING) 956 ether_poll_deregister(sc->ifp); 957 #endif 958 959 FXP_LOCK(sc); 960 sc->suspended = 1; /* Do same thing as we do for suspend */ 961 /* 962 * Stop DMA and drop transmit queue, but disable interrupts first. 963 */ 964 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE); 965 fxp_stop(sc); 966 FXP_UNLOCK(sc); 967 callout_drain(&sc->stat_ch); 968 969 /* 970 * Close down routes etc. 971 */ 972 ether_ifdetach(sc->ifp); 973 974 /* 975 * Unhook interrupt before dropping lock. This is to prevent 976 * races with fxp_intr(). 977 */ 978 bus_teardown_intr(sc->dev, sc->fxp_res[1], sc->ih); 979 sc->ih = NULL; 980 981 /* Release our allocated resources. */ 982 fxp_release(sc); 983 return (0); 984 } 985 986 /* 987 * Device shutdown routine. Called at system shutdown after sync. The 988 * main purpose of this routine is to shut off receiver DMA so that 989 * kernel memory doesn't get clobbered during warmboot. 990 */ 991 static int 992 fxp_shutdown(device_t dev) 993 { 994 995 /* 996 * Make sure that DMA is disabled prior to reboot. Not doing 997 * do could allow DMA to corrupt kernel memory during the 998 * reboot before the driver initializes. 999 */ 1000 return (fxp_suspend(dev)); 1001 } 1002 1003 /* 1004 * Device suspend routine. Stop the interface and save some PCI 1005 * settings in case the BIOS doesn't restore them properly on 1006 * resume. 1007 */ 1008 static int 1009 fxp_suspend(device_t dev) 1010 { 1011 struct fxp_softc *sc = device_get_softc(dev); 1012 struct ifnet *ifp; 1013 int pmc; 1014 uint16_t pmstat; 1015 1016 FXP_LOCK(sc); 1017 1018 ifp = sc->ifp; 1019 if (pci_find_extcap(sc->dev, PCIY_PMG, &pmc) == 0) { 1020 pmstat = pci_read_config(sc->dev, pmc + PCIR_POWER_STATUS, 2); 1021 pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE); 1022 if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0) { 1023 /* Request PME. */ 1024 pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE; 1025 sc->flags |= FXP_FLAG_WOL; 1026 /* Reconfigure hardware to accept magic frames. */ 1027 fxp_init_body(sc); 1028 } 1029 pci_write_config(sc->dev, pmc + PCIR_POWER_STATUS, pmstat, 2); 1030 } 1031 fxp_stop(sc); 1032 1033 sc->suspended = 1; 1034 1035 FXP_UNLOCK(sc); 1036 return (0); 1037 } 1038 1039 /* 1040 * Device resume routine. re-enable busmastering, and restart the interface if 1041 * appropriate. 1042 */ 1043 static int 1044 fxp_resume(device_t dev) 1045 { 1046 struct fxp_softc *sc = device_get_softc(dev); 1047 struct ifnet *ifp = sc->ifp; 1048 int pmc; 1049 uint16_t pmstat; 1050 1051 FXP_LOCK(sc); 1052 1053 if (pci_find_extcap(sc->dev, PCIY_PMG, &pmc) == 0) { 1054 sc->flags &= ~FXP_FLAG_WOL; 1055 pmstat = pci_read_config(sc->dev, pmc + PCIR_POWER_STATUS, 2); 1056 /* Disable PME and clear PME status. */ 1057 pmstat &= ~PCIM_PSTAT_PMEENABLE; 1058 pci_write_config(sc->dev, pmc + PCIR_POWER_STATUS, pmstat, 2); 1059 if ((sc->flags & FXP_FLAG_WOLCAP) != 0) 1060 CSR_WRITE_1(sc, FXP_CSR_PMDR, 1061 CSR_READ_1(sc, FXP_CSR_PMDR)); 1062 } 1063 1064 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET); 1065 DELAY(10); 1066 1067 /* reinitialize interface if necessary */ 1068 if (ifp->if_flags & IFF_UP) 1069 fxp_init_body(sc); 1070 1071 sc->suspended = 0; 1072 1073 FXP_UNLOCK(sc); 1074 return (0); 1075 } 1076 1077 static void 1078 fxp_eeprom_shiftin(struct fxp_softc *sc, int data, int length) 1079 { 1080 uint16_t reg; 1081 int x; 1082 1083 /* 1084 * Shift in data. 1085 */ 1086 for (x = 1 << (length - 1); x; x >>= 1) { 1087 if (data & x) 1088 reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI; 1089 else 1090 reg = FXP_EEPROM_EECS; 1091 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 1092 DELAY(1); 1093 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK); 1094 DELAY(1); 1095 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 1096 DELAY(1); 1097 } 1098 } 1099 1100 /* 1101 * Read from the serial EEPROM. Basically, you manually shift in 1102 * the read opcode (one bit at a time) and then shift in the address, 1103 * and then you shift out the data (all of this one bit at a time). 1104 * The word size is 16 bits, so you have to provide the address for 1105 * every 16 bits of data. 1106 */ 1107 static uint16_t 1108 fxp_eeprom_getword(struct fxp_softc *sc, int offset, int autosize) 1109 { 1110 uint16_t reg, data; 1111 int x; 1112 1113 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 1114 /* 1115 * Shift in read opcode. 1116 */ 1117 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_READ, 3); 1118 /* 1119 * Shift in address. 1120 */ 1121 data = 0; 1122 for (x = 1 << (sc->eeprom_size - 1); x; x >>= 1) { 1123 if (offset & x) 1124 reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI; 1125 else 1126 reg = FXP_EEPROM_EECS; 1127 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 1128 DELAY(1); 1129 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK); 1130 DELAY(1); 1131 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 1132 DELAY(1); 1133 reg = CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO; 1134 data++; 1135 if (autosize && reg == 0) { 1136 sc->eeprom_size = data; 1137 break; 1138 } 1139 } 1140 /* 1141 * Shift out data. 1142 */ 1143 data = 0; 1144 reg = FXP_EEPROM_EECS; 1145 for (x = 1 << 15; x; x >>= 1) { 1146 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK); 1147 DELAY(1); 1148 if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO) 1149 data |= x; 1150 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 1151 DELAY(1); 1152 } 1153 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 1154 DELAY(1); 1155 1156 return (data); 1157 } 1158 1159 static void 1160 fxp_eeprom_putword(struct fxp_softc *sc, int offset, uint16_t data) 1161 { 1162 int i; 1163 1164 /* 1165 * Erase/write enable. 1166 */ 1167 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 1168 fxp_eeprom_shiftin(sc, 0x4, 3); 1169 fxp_eeprom_shiftin(sc, 0x03 << (sc->eeprom_size - 2), sc->eeprom_size); 1170 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 1171 DELAY(1); 1172 /* 1173 * Shift in write opcode, address, data. 1174 */ 1175 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 1176 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_WRITE, 3); 1177 fxp_eeprom_shiftin(sc, offset, sc->eeprom_size); 1178 fxp_eeprom_shiftin(sc, data, 16); 1179 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 1180 DELAY(1); 1181 /* 1182 * Wait for EEPROM to finish up. 1183 */ 1184 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 1185 DELAY(1); 1186 for (i = 0; i < 1000; i++) { 1187 if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO) 1188 break; 1189 DELAY(50); 1190 } 1191 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 1192 DELAY(1); 1193 /* 1194 * Erase/write disable. 1195 */ 1196 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 1197 fxp_eeprom_shiftin(sc, 0x4, 3); 1198 fxp_eeprom_shiftin(sc, 0, sc->eeprom_size); 1199 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 1200 DELAY(1); 1201 } 1202 1203 /* 1204 * From NetBSD: 1205 * 1206 * Figure out EEPROM size. 1207 * 1208 * 559's can have either 64-word or 256-word EEPROMs, the 558 1209 * datasheet only talks about 64-word EEPROMs, and the 557 datasheet 1210 * talks about the existance of 16 to 256 word EEPROMs. 1211 * 1212 * The only known sizes are 64 and 256, where the 256 version is used 1213 * by CardBus cards to store CIS information. 1214 * 1215 * The address is shifted in msb-to-lsb, and after the last 1216 * address-bit the EEPROM is supposed to output a `dummy zero' bit, 1217 * after which follows the actual data. We try to detect this zero, by 1218 * probing the data-out bit in the EEPROM control register just after 1219 * having shifted in a bit. If the bit is zero, we assume we've 1220 * shifted enough address bits. The data-out should be tri-state, 1221 * before this, which should translate to a logical one. 1222 */ 1223 static void 1224 fxp_autosize_eeprom(struct fxp_softc *sc) 1225 { 1226 1227 /* guess maximum size of 256 words */ 1228 sc->eeprom_size = 8; 1229 1230 /* autosize */ 1231 (void) fxp_eeprom_getword(sc, 0, 1); 1232 } 1233 1234 static void 1235 fxp_read_eeprom(struct fxp_softc *sc, u_short *data, int offset, int words) 1236 { 1237 int i; 1238 1239 for (i = 0; i < words; i++) 1240 data[i] = fxp_eeprom_getword(sc, offset + i, 0); 1241 } 1242 1243 static void 1244 fxp_write_eeprom(struct fxp_softc *sc, u_short *data, int offset, int words) 1245 { 1246 int i; 1247 1248 for (i = 0; i < words; i++) 1249 fxp_eeprom_putword(sc, offset + i, data[i]); 1250 } 1251 1252 /* 1253 * Grab the softc lock and call the real fxp_start_body() routine 1254 */ 1255 static void 1256 fxp_start(struct ifnet *ifp) 1257 { 1258 struct fxp_softc *sc = ifp->if_softc; 1259 1260 FXP_LOCK(sc); 1261 fxp_start_body(ifp); 1262 FXP_UNLOCK(sc); 1263 } 1264 1265 /* 1266 * Start packet transmission on the interface. 1267 * This routine must be called with the softc lock held, and is an 1268 * internal entry point only. 1269 */ 1270 static void 1271 fxp_start_body(struct ifnet *ifp) 1272 { 1273 struct fxp_softc *sc = ifp->if_softc; 1274 struct mbuf *mb_head; 1275 int txqueued; 1276 1277 FXP_LOCK_ASSERT(sc, MA_OWNED); 1278 1279 /* 1280 * See if we need to suspend xmit until the multicast filter 1281 * has been reprogrammed (which can only be done at the head 1282 * of the command chain). 1283 */ 1284 if (sc->need_mcsetup) 1285 return; 1286 1287 if (sc->tx_queued > FXP_NTXCB_HIWAT) 1288 fxp_txeof(sc); 1289 /* 1290 * We're finished if there is nothing more to add to the list or if 1291 * we're all filled up with buffers to transmit. 1292 * NOTE: One TxCB is reserved to guarantee that fxp_mc_setup() can add 1293 * a NOP command when needed. 1294 */ 1295 txqueued = 0; 1296 while (!IFQ_DRV_IS_EMPTY(&ifp->if_snd) && 1297 sc->tx_queued < FXP_NTXCB - 1) { 1298 1299 /* 1300 * Grab a packet to transmit. 1301 */ 1302 IFQ_DRV_DEQUEUE(&ifp->if_snd, mb_head); 1303 if (mb_head == NULL) 1304 break; 1305 1306 if (fxp_encap(sc, &mb_head)) { 1307 if (mb_head == NULL) 1308 break; 1309 IFQ_DRV_PREPEND(&ifp->if_snd, mb_head); 1310 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 1311 } 1312 txqueued++; 1313 /* 1314 * Pass packet to bpf if there is a listener. 1315 */ 1316 BPF_MTAP(ifp, mb_head); 1317 } 1318 1319 /* 1320 * We're finished. If we added to the list, issue a RESUME to get DMA 1321 * going again if suspended. 1322 */ 1323 if (txqueued > 0) { 1324 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE); 1325 fxp_scb_wait(sc); 1326 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_RESUME); 1327 /* 1328 * Set a 5 second timer just in case we don't hear 1329 * from the card again. 1330 */ 1331 sc->watchdog_timer = 5; 1332 } 1333 } 1334 1335 static int 1336 fxp_encap(struct fxp_softc *sc, struct mbuf **m_head) 1337 { 1338 struct ifnet *ifp; 1339 struct mbuf *m; 1340 struct fxp_tx *txp; 1341 struct fxp_cb_tx *cbp; 1342 struct tcphdr *tcp; 1343 bus_dma_segment_t segs[FXP_NTXSEG]; 1344 int error, i, nseg, tcp_payload; 1345 1346 FXP_LOCK_ASSERT(sc, MA_OWNED); 1347 ifp = sc->ifp; 1348 1349 tcp_payload = 0; 1350 tcp = NULL; 1351 /* 1352 * Get pointer to next available tx desc. 1353 */ 1354 txp = sc->fxp_desc.tx_last->tx_next; 1355 1356 /* 1357 * A note in Appendix B of the Intel 8255x 10/100 Mbps 1358 * Ethernet Controller Family Open Source Software 1359 * Developer Manual says: 1360 * Using software parsing is only allowed with legal 1361 * TCP/IP or UDP/IP packets. 1362 * ... 1363 * For all other datagrams, hardware parsing must 1364 * be used. 1365 * Software parsing appears to truncate ICMP and 1366 * fragmented UDP packets that contain one to three 1367 * bytes in the second (and final) mbuf of the packet. 1368 */ 1369 if (sc->flags & FXP_FLAG_EXT_RFA) 1370 txp->tx_cb->ipcb_ip_activation_high = 1371 FXP_IPCB_HARDWAREPARSING_ENABLE; 1372 1373 m = *m_head; 1374 /* 1375 * Deal with TCP/IP checksum offload. Note that 1376 * in order for TCP checksum offload to work, 1377 * the pseudo header checksum must have already 1378 * been computed and stored in the checksum field 1379 * in the TCP header. The stack should have 1380 * already done this for us. 1381 */ 1382 if (m->m_pkthdr.csum_flags & FXP_CSUM_FEATURES) { 1383 txp->tx_cb->ipcb_ip_schedule = FXP_IPCB_TCPUDP_CHECKSUM_ENABLE; 1384 if (m->m_pkthdr.csum_flags & CSUM_TCP) 1385 txp->tx_cb->ipcb_ip_schedule |= FXP_IPCB_TCP_PACKET; 1386 1387 #ifdef FXP_IP_CSUM_WAR 1388 /* 1389 * XXX The 82550 chip appears to have trouble 1390 * dealing with IP header checksums in very small 1391 * datagrams, namely fragments from 1 to 3 bytes 1392 * in size. For example, say you want to transmit 1393 * a UDP packet of 1473 bytes. The packet will be 1394 * fragmented over two IP datagrams, the latter 1395 * containing only one byte of data. The 82550 will 1396 * botch the header checksum on the 1-byte fragment. 1397 * As long as the datagram contains 4 or more bytes 1398 * of data, you're ok. 1399 * 1400 * The following code attempts to work around this 1401 * problem: if the datagram is less than 38 bytes 1402 * in size (14 bytes ether header, 20 bytes IP header, 1403 * plus 4 bytes of data), we punt and compute the IP 1404 * header checksum by hand. This workaround doesn't 1405 * work very well, however, since it can be fooled 1406 * by things like VLAN tags and IP options that make 1407 * the header sizes/offsets vary. 1408 */ 1409 1410 if (m->m_pkthdr.csum_flags & CSUM_IP) { 1411 if (m->m_pkthdr.len < 38) { 1412 struct ip *ip; 1413 m->m_data += ETHER_HDR_LEN; 1414 ip = mtod(m, struct ip *); 1415 ip->ip_sum = in_cksum(m, ip->ip_hl << 2); 1416 m->m_data -= ETHER_HDR_LEN; 1417 m->m_pkthdr.csum_flags &= ~CSUM_IP; 1418 } else { 1419 txp->tx_cb->ipcb_ip_activation_high = 1420 FXP_IPCB_HARDWAREPARSING_ENABLE; 1421 txp->tx_cb->ipcb_ip_schedule |= 1422 FXP_IPCB_IP_CHECKSUM_ENABLE; 1423 } 1424 } 1425 #endif 1426 } 1427 1428 if (m->m_pkthdr.csum_flags & CSUM_TSO) { 1429 /* 1430 * 82550/82551 requires ethernet/IP/TCP headers must be 1431 * contained in the first active transmit buffer. 1432 */ 1433 struct ether_header *eh; 1434 struct ip *ip; 1435 uint32_t ip_off, poff; 1436 1437 if (M_WRITABLE(*m_head) == 0) { 1438 /* Get a writable copy. */ 1439 m = m_dup(*m_head, M_DONTWAIT); 1440 m_freem(*m_head); 1441 if (m == NULL) { 1442 *m_head = NULL; 1443 return (ENOBUFS); 1444 } 1445 *m_head = m; 1446 } 1447 ip_off = sizeof(struct ether_header); 1448 m = m_pullup(*m_head, ip_off); 1449 if (m == NULL) { 1450 *m_head = NULL; 1451 return (ENOBUFS); 1452 } 1453 eh = mtod(m, struct ether_header *); 1454 /* Check the existence of VLAN tag. */ 1455 if (eh->ether_type == htons(ETHERTYPE_VLAN)) { 1456 ip_off = sizeof(struct ether_vlan_header); 1457 m = m_pullup(m, ip_off); 1458 if (m == NULL) { 1459 *m_head = NULL; 1460 return (ENOBUFS); 1461 } 1462 } 1463 m = m_pullup(m, ip_off + sizeof(struct ip)); 1464 if (m == NULL) { 1465 *m_head = NULL; 1466 return (ENOBUFS); 1467 } 1468 ip = (struct ip *)(mtod(m, char *) + ip_off); 1469 poff = ip_off + (ip->ip_hl << 2); 1470 m = m_pullup(m, poff + sizeof(struct tcphdr)); 1471 if (m == NULL) { 1472 *m_head = NULL; 1473 return (ENOBUFS); 1474 } 1475 tcp = (struct tcphdr *)(mtod(m, char *) + poff); 1476 m = m_pullup(m, poff + sizeof(struct tcphdr) + tcp->th_off); 1477 if (m == NULL) { 1478 *m_head = NULL; 1479 return (ENOBUFS); 1480 } 1481 1482 /* 1483 * Since 82550/82551 doesn't modify IP length and pseudo 1484 * checksum in the first frame driver should compute it. 1485 */ 1486 ip->ip_sum = 0; 1487 ip->ip_len = htons(ifp->if_mtu); 1488 tcp->th_sum = in_pseudo(ip->ip_src.s_addr, ip->ip_dst.s_addr, 1489 htons(IPPROTO_TCP + (tcp->th_off << 2) + 1490 m->m_pkthdr.tso_segsz)); 1491 /* Compute total TCP payload. */ 1492 tcp_payload = m->m_pkthdr.len - ip_off - (ip->ip_hl << 2); 1493 tcp_payload -= tcp->th_off << 2; 1494 *m_head = m; 1495 } 1496 1497 error = bus_dmamap_load_mbuf_sg(sc->fxp_mtag, txp->tx_map, *m_head, 1498 segs, &nseg, 0); 1499 if (error == EFBIG) { 1500 m = m_collapse(*m_head, M_DONTWAIT, sc->maxtxseg); 1501 if (m == NULL) { 1502 m_freem(*m_head); 1503 *m_head = NULL; 1504 return (ENOMEM); 1505 } 1506 *m_head = m; 1507 error = bus_dmamap_load_mbuf_sg(sc->fxp_mtag, txp->tx_map, 1508 *m_head, segs, &nseg, 0); 1509 if (error != 0) { 1510 m_freem(*m_head); 1511 *m_head = NULL; 1512 return (ENOMEM); 1513 } 1514 } else if (error != 0) 1515 return (error); 1516 if (nseg == 0) { 1517 m_freem(*m_head); 1518 *m_head = NULL; 1519 return (EIO); 1520 } 1521 1522 KASSERT(nseg <= sc->maxtxseg, ("too many DMA segments")); 1523 bus_dmamap_sync(sc->fxp_mtag, txp->tx_map, BUS_DMASYNC_PREWRITE); 1524 1525 cbp = txp->tx_cb; 1526 for (i = 0; i < nseg; i++) { 1527 /* 1528 * If this is an 82550/82551, then we're using extended 1529 * TxCBs _and_ we're using checksum offload. This means 1530 * that the TxCB is really an IPCB. One major difference 1531 * between the two is that with plain extended TxCBs, 1532 * the bottom half of the TxCB contains two entries from 1533 * the TBD array, whereas IPCBs contain just one entry: 1534 * one entry (8 bytes) has been sacrificed for the TCP/IP 1535 * checksum offload control bits. So to make things work 1536 * right, we have to start filling in the TBD array 1537 * starting from a different place depending on whether 1538 * the chip is an 82550/82551 or not. 1539 */ 1540 if (sc->flags & FXP_FLAG_EXT_RFA) { 1541 cbp->tbd[i + 2].tb_addr = htole32(segs[i].ds_addr); 1542 cbp->tbd[i + 2].tb_size = htole32(segs[i].ds_len); 1543 } else { 1544 cbp->tbd[i].tb_addr = htole32(segs[i].ds_addr); 1545 cbp->tbd[i].tb_size = htole32(segs[i].ds_len); 1546 } 1547 } 1548 if (sc->flags & FXP_FLAG_EXT_RFA) { 1549 /* Configure dynamic TBD for 82550/82551. */ 1550 cbp->tbd_number = 0xFF; 1551 cbp->tbd[nseg + 1].tb_size |= htole32(0x8000); 1552 } else 1553 cbp->tbd_number = nseg; 1554 /* Configure TSO. */ 1555 if (m->m_pkthdr.csum_flags & CSUM_TSO) { 1556 cbp->tbd[-1].tb_size = htole32(m->m_pkthdr.tso_segsz << 16); 1557 cbp->tbd[1].tb_size = htole32(tcp_payload << 16); 1558 cbp->ipcb_ip_schedule |= FXP_IPCB_LARGESEND_ENABLE | 1559 FXP_IPCB_IP_CHECKSUM_ENABLE | 1560 FXP_IPCB_TCP_PACKET | 1561 FXP_IPCB_TCPUDP_CHECKSUM_ENABLE; 1562 } 1563 /* Configure VLAN hardware tag insertion. */ 1564 if ((m->m_flags & M_VLANTAG) != 0) { 1565 cbp->ipcb_vlan_id = htons(m->m_pkthdr.ether_vtag); 1566 txp->tx_cb->ipcb_ip_activation_high |= 1567 FXP_IPCB_INSERTVLAN_ENABLE; 1568 } 1569 1570 txp->tx_mbuf = m; 1571 txp->tx_cb->cb_status = 0; 1572 txp->tx_cb->byte_count = 0; 1573 if (sc->tx_queued != FXP_CXINT_THRESH - 1) 1574 txp->tx_cb->cb_command = 1575 htole16(sc->tx_cmd | FXP_CB_COMMAND_SF | 1576 FXP_CB_COMMAND_S); 1577 else 1578 txp->tx_cb->cb_command = 1579 htole16(sc->tx_cmd | FXP_CB_COMMAND_SF | 1580 FXP_CB_COMMAND_S | FXP_CB_COMMAND_I); 1581 if ((m->m_pkthdr.csum_flags & CSUM_TSO) == 0) 1582 txp->tx_cb->tx_threshold = tx_threshold; 1583 1584 /* 1585 * Advance the end of list forward. 1586 */ 1587 1588 #ifdef __alpha__ 1589 /* 1590 * On platforms which can't access memory in 16-bit 1591 * granularities, we must prevent the card from DMA'ing 1592 * up the status while we update the command field. 1593 * This could cause us to overwrite the completion status. 1594 * XXX This is probably bogus and we're _not_ looking 1595 * for atomicity here. 1596 */ 1597 atomic_clear_16(&sc->fxp_desc.tx_last->tx_cb->cb_command, 1598 htole16(FXP_CB_COMMAND_S)); 1599 #else 1600 sc->fxp_desc.tx_last->tx_cb->cb_command &= htole16(~FXP_CB_COMMAND_S); 1601 #endif /*__alpha__*/ 1602 sc->fxp_desc.tx_last = txp; 1603 1604 /* 1605 * Advance the beginning of the list forward if there are 1606 * no other packets queued (when nothing is queued, tx_first 1607 * sits on the last TxCB that was sent out). 1608 */ 1609 if (sc->tx_queued == 0) 1610 sc->fxp_desc.tx_first = txp; 1611 1612 sc->tx_queued++; 1613 1614 return (0); 1615 } 1616 1617 #ifdef DEVICE_POLLING 1618 static poll_handler_t fxp_poll; 1619 1620 static void 1621 fxp_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 1622 { 1623 struct fxp_softc *sc = ifp->if_softc; 1624 uint8_t statack; 1625 1626 FXP_LOCK(sc); 1627 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) { 1628 FXP_UNLOCK(sc); 1629 return; 1630 } 1631 1632 statack = FXP_SCB_STATACK_CXTNO | FXP_SCB_STATACK_CNA | 1633 FXP_SCB_STATACK_FR; 1634 if (cmd == POLL_AND_CHECK_STATUS) { 1635 uint8_t tmp; 1636 1637 tmp = CSR_READ_1(sc, FXP_CSR_SCB_STATACK); 1638 if (tmp == 0xff || tmp == 0) { 1639 FXP_UNLOCK(sc); 1640 return; /* nothing to do */ 1641 } 1642 tmp &= ~statack; 1643 /* ack what we can */ 1644 if (tmp != 0) 1645 CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, tmp); 1646 statack |= tmp; 1647 } 1648 fxp_intr_body(sc, ifp, statack, count); 1649 FXP_UNLOCK(sc); 1650 } 1651 #endif /* DEVICE_POLLING */ 1652 1653 /* 1654 * Process interface interrupts. 1655 */ 1656 static void 1657 fxp_intr(void *xsc) 1658 { 1659 struct fxp_softc *sc = xsc; 1660 struct ifnet *ifp = sc->ifp; 1661 uint8_t statack; 1662 1663 FXP_LOCK(sc); 1664 if (sc->suspended) { 1665 FXP_UNLOCK(sc); 1666 return; 1667 } 1668 1669 #ifdef DEVICE_POLLING 1670 if (ifp->if_capenable & IFCAP_POLLING) { 1671 FXP_UNLOCK(sc); 1672 return; 1673 } 1674 #endif 1675 while ((statack = CSR_READ_1(sc, FXP_CSR_SCB_STATACK)) != 0) { 1676 /* 1677 * It should not be possible to have all bits set; the 1678 * FXP_SCB_INTR_SWI bit always returns 0 on a read. If 1679 * all bits are set, this may indicate that the card has 1680 * been physically ejected, so ignore it. 1681 */ 1682 if (statack == 0xff) { 1683 FXP_UNLOCK(sc); 1684 return; 1685 } 1686 1687 /* 1688 * First ACK all the interrupts in this pass. 1689 */ 1690 CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, statack); 1691 fxp_intr_body(sc, ifp, statack, -1); 1692 } 1693 FXP_UNLOCK(sc); 1694 } 1695 1696 static void 1697 fxp_txeof(struct fxp_softc *sc) 1698 { 1699 struct ifnet *ifp; 1700 struct fxp_tx *txp; 1701 1702 ifp = sc->ifp; 1703 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREREAD); 1704 for (txp = sc->fxp_desc.tx_first; sc->tx_queued && 1705 (le16toh(txp->tx_cb->cb_status) & FXP_CB_STATUS_C) != 0; 1706 txp = txp->tx_next) { 1707 if (txp->tx_mbuf != NULL) { 1708 bus_dmamap_sync(sc->fxp_mtag, txp->tx_map, 1709 BUS_DMASYNC_POSTWRITE); 1710 bus_dmamap_unload(sc->fxp_mtag, txp->tx_map); 1711 m_freem(txp->tx_mbuf); 1712 txp->tx_mbuf = NULL; 1713 /* clear this to reset csum offload bits */ 1714 txp->tx_cb->tbd[0].tb_addr = 0; 1715 } 1716 sc->tx_queued--; 1717 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1718 } 1719 sc->fxp_desc.tx_first = txp; 1720 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE); 1721 if (sc->tx_queued == 0) { 1722 sc->watchdog_timer = 0; 1723 if (sc->need_mcsetup) 1724 fxp_mc_setup(sc); 1725 } 1726 } 1727 1728 static void 1729 fxp_rxcsum(struct fxp_softc *sc, struct ifnet *ifp, struct mbuf *m, 1730 uint16_t status, int pos) 1731 { 1732 struct ether_header *eh; 1733 struct ip *ip; 1734 struct udphdr *uh; 1735 int32_t hlen, len, pktlen, temp32; 1736 uint16_t csum, *opts; 1737 1738 if ((sc->flags & FXP_FLAG_82559_RXCSUM) == 0) { 1739 if ((status & FXP_RFA_STATUS_PARSE) != 0) { 1740 if (status & FXP_RFDX_CS_IP_CSUM_BIT_VALID) 1741 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 1742 if (status & FXP_RFDX_CS_IP_CSUM_VALID) 1743 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 1744 if ((status & FXP_RFDX_CS_TCPUDP_CSUM_BIT_VALID) && 1745 (status & FXP_RFDX_CS_TCPUDP_CSUM_VALID)) { 1746 m->m_pkthdr.csum_flags |= CSUM_DATA_VALID | 1747 CSUM_PSEUDO_HDR; 1748 m->m_pkthdr.csum_data = 0xffff; 1749 } 1750 } 1751 return; 1752 } 1753 1754 pktlen = m->m_pkthdr.len; 1755 if (pktlen < sizeof(struct ether_header) + sizeof(struct ip)) 1756 return; 1757 eh = mtod(m, struct ether_header *); 1758 if (eh->ether_type != htons(ETHERTYPE_IP)) 1759 return; 1760 ip = (struct ip *)(eh + 1); 1761 if (ip->ip_v != IPVERSION) 1762 return; 1763 1764 hlen = ip->ip_hl << 2; 1765 pktlen -= sizeof(struct ether_header); 1766 if (hlen < sizeof(struct ip)) 1767 return; 1768 if (ntohs(ip->ip_len) < hlen) 1769 return; 1770 if (ntohs(ip->ip_len) != pktlen) 1771 return; 1772 if (ip->ip_off & htons(IP_MF | IP_OFFMASK)) 1773 return; /* can't handle fragmented packet */ 1774 1775 switch (ip->ip_p) { 1776 case IPPROTO_TCP: 1777 if (pktlen < (hlen + sizeof(struct tcphdr))) 1778 return; 1779 break; 1780 case IPPROTO_UDP: 1781 if (pktlen < (hlen + sizeof(struct udphdr))) 1782 return; 1783 uh = (struct udphdr *)((caddr_t)ip + hlen); 1784 if (uh->uh_sum == 0) 1785 return; /* no checksum */ 1786 break; 1787 default: 1788 return; 1789 } 1790 /* Extract computed checksum. */ 1791 csum = be16dec(mtod(m, char *) + pos); 1792 /* checksum fixup for IP options */ 1793 len = hlen - sizeof(struct ip); 1794 if (len > 0) { 1795 opts = (uint16_t *)(ip + 1); 1796 for (; len > 0; len -= sizeof(uint16_t), opts++) { 1797 temp32 = csum - *opts; 1798 temp32 = (temp32 >> 16) + (temp32 & 65535); 1799 csum = temp32 & 65535; 1800 } 1801 } 1802 m->m_pkthdr.csum_flags |= CSUM_DATA_VALID; 1803 m->m_pkthdr.csum_data = csum; 1804 } 1805 1806 static void 1807 fxp_intr_body(struct fxp_softc *sc, struct ifnet *ifp, uint8_t statack, 1808 int count) 1809 { 1810 struct mbuf *m; 1811 struct fxp_rx *rxp; 1812 struct fxp_rfa *rfa; 1813 int rnr = (statack & FXP_SCB_STATACK_RNR) ? 1 : 0; 1814 uint16_t status; 1815 1816 FXP_LOCK_ASSERT(sc, MA_OWNED); 1817 if (rnr) 1818 sc->rnr++; 1819 #ifdef DEVICE_POLLING 1820 /* Pick up a deferred RNR condition if `count' ran out last time. */ 1821 if (sc->flags & FXP_FLAG_DEFERRED_RNR) { 1822 sc->flags &= ~FXP_FLAG_DEFERRED_RNR; 1823 rnr = 1; 1824 } 1825 #endif 1826 1827 /* 1828 * Free any finished transmit mbuf chains. 1829 * 1830 * Handle the CNA event likt a CXTNO event. It used to 1831 * be that this event (control unit not ready) was not 1832 * encountered, but it is now with the SMPng modifications. 1833 * The exact sequence of events that occur when the interface 1834 * is brought up are different now, and if this event 1835 * goes unhandled, the configuration/rxfilter setup sequence 1836 * can stall for several seconds. The result is that no 1837 * packets go out onto the wire for about 5 to 10 seconds 1838 * after the interface is ifconfig'ed for the first time. 1839 */ 1840 if (statack & (FXP_SCB_STATACK_CXTNO | FXP_SCB_STATACK_CNA)) 1841 fxp_txeof(sc); 1842 1843 /* 1844 * Try to start more packets transmitting. 1845 */ 1846 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1847 fxp_start_body(ifp); 1848 1849 /* 1850 * Just return if nothing happened on the receive side. 1851 */ 1852 if (!rnr && (statack & FXP_SCB_STATACK_FR) == 0) 1853 return; 1854 1855 /* 1856 * Process receiver interrupts. If a no-resource (RNR) 1857 * condition exists, get whatever packets we can and 1858 * re-start the receiver. 1859 * 1860 * When using polling, we do not process the list to completion, 1861 * so when we get an RNR interrupt we must defer the restart 1862 * until we hit the last buffer with the C bit set. 1863 * If we run out of cycles and rfa_headm has the C bit set, 1864 * record the pending RNR in the FXP_FLAG_DEFERRED_RNR flag so 1865 * that the info will be used in the subsequent polling cycle. 1866 */ 1867 for (;;) { 1868 rxp = sc->fxp_desc.rx_head; 1869 m = rxp->rx_mbuf; 1870 rfa = (struct fxp_rfa *)(m->m_ext.ext_buf + 1871 RFA_ALIGNMENT_FUDGE); 1872 bus_dmamap_sync(sc->fxp_mtag, rxp->rx_map, 1873 BUS_DMASYNC_POSTREAD); 1874 1875 #ifdef DEVICE_POLLING /* loop at most count times if count >=0 */ 1876 if (count >= 0 && count-- == 0) { 1877 if (rnr) { 1878 /* Defer RNR processing until the next time. */ 1879 sc->flags |= FXP_FLAG_DEFERRED_RNR; 1880 rnr = 0; 1881 } 1882 break; 1883 } 1884 #endif /* DEVICE_POLLING */ 1885 1886 status = le16toh(rfa->rfa_status); 1887 if ((status & FXP_RFA_STATUS_C) == 0) 1888 break; 1889 1890 /* 1891 * Advance head forward. 1892 */ 1893 sc->fxp_desc.rx_head = rxp->rx_next; 1894 1895 /* 1896 * Add a new buffer to the receive chain. 1897 * If this fails, the old buffer is recycled 1898 * instead. 1899 */ 1900 if (fxp_new_rfabuf(sc, rxp) == 0) { 1901 int total_len; 1902 1903 /* 1904 * Fetch packet length (the top 2 bits of 1905 * actual_size are flags set by the controller 1906 * upon completion), and drop the packet in case 1907 * of bogus length or CRC errors. 1908 */ 1909 total_len = le16toh(rfa->actual_size) & 0x3fff; 1910 if ((sc->flags & FXP_FLAG_82559_RXCSUM) != 0 && 1911 (ifp->if_capenable & IFCAP_RXCSUM) != 0) { 1912 /* Adjust for appended checksum bytes. */ 1913 total_len -= 2; 1914 } 1915 if (total_len < sizeof(struct ether_header) || 1916 total_len > MCLBYTES - RFA_ALIGNMENT_FUDGE - 1917 sc->rfa_size || status & FXP_RFA_STATUS_CRC) { 1918 m_freem(m); 1919 continue; 1920 } 1921 1922 m->m_pkthdr.len = m->m_len = total_len; 1923 m->m_pkthdr.rcvif = ifp; 1924 1925 /* Do IP checksum checking. */ 1926 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0) 1927 fxp_rxcsum(sc, ifp, m, status, total_len); 1928 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0 && 1929 (status & FXP_RFA_STATUS_VLAN) != 0) { 1930 m->m_pkthdr.ether_vtag = 1931 ntohs(rfa->rfax_vlan_id); 1932 m->m_flags |= M_VLANTAG; 1933 } 1934 /* 1935 * Drop locks before calling if_input() since it 1936 * may re-enter fxp_start() in the netisr case. 1937 * This would result in a lock reversal. Better 1938 * performance might be obtained by chaining all 1939 * packets received, dropping the lock, and then 1940 * calling if_input() on each one. 1941 */ 1942 FXP_UNLOCK(sc); 1943 (*ifp->if_input)(ifp, m); 1944 FXP_LOCK(sc); 1945 } else { 1946 /* Reuse RFA and loaded DMA map. */ 1947 ifp->if_iqdrops++; 1948 fxp_discard_rfabuf(sc, rxp); 1949 } 1950 fxp_add_rfabuf(sc, rxp); 1951 } 1952 if (rnr) { 1953 fxp_scb_wait(sc); 1954 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 1955 sc->fxp_desc.rx_head->rx_addr); 1956 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_START); 1957 } 1958 } 1959 1960 /* 1961 * Update packet in/out/collision statistics. The i82557 doesn't 1962 * allow you to access these counters without doing a fairly 1963 * expensive DMA to get _all_ of the statistics it maintains, so 1964 * we do this operation here only once per second. The statistics 1965 * counters in the kernel are updated from the previous dump-stats 1966 * DMA and then a new dump-stats DMA is started. The on-chip 1967 * counters are zeroed when the DMA completes. If we can't start 1968 * the DMA immediately, we don't wait - we just prepare to read 1969 * them again next time. 1970 */ 1971 static void 1972 fxp_tick(void *xsc) 1973 { 1974 struct fxp_softc *sc = xsc; 1975 struct ifnet *ifp = sc->ifp; 1976 struct fxp_stats *sp = sc->fxp_stats; 1977 1978 FXP_LOCK_ASSERT(sc, MA_OWNED); 1979 bus_dmamap_sync(sc->fxp_stag, sc->fxp_smap, BUS_DMASYNC_POSTREAD); 1980 ifp->if_opackets += le32toh(sp->tx_good); 1981 ifp->if_collisions += le32toh(sp->tx_total_collisions); 1982 if (sp->rx_good) { 1983 ifp->if_ipackets += le32toh(sp->rx_good); 1984 sc->rx_idle_secs = 0; 1985 } else { 1986 /* 1987 * Receiver's been idle for another second. 1988 */ 1989 sc->rx_idle_secs++; 1990 } 1991 ifp->if_ierrors += 1992 le32toh(sp->rx_crc_errors) + 1993 le32toh(sp->rx_alignment_errors) + 1994 le32toh(sp->rx_rnr_errors) + 1995 le32toh(sp->rx_overrun_errors); 1996 /* 1997 * If any transmit underruns occured, bump up the transmit 1998 * threshold by another 512 bytes (64 * 8). 1999 */ 2000 if (sp->tx_underruns) { 2001 ifp->if_oerrors += le32toh(sp->tx_underruns); 2002 if (tx_threshold < 192) 2003 tx_threshold += 64; 2004 } 2005 2006 /* 2007 * Release any xmit buffers that have completed DMA. This isn't 2008 * strictly necessary to do here, but it's advantagous for mbufs 2009 * with external storage to be released in a timely manner rather 2010 * than being defered for a potentially long time. This limits 2011 * the delay to a maximum of one second. 2012 */ 2013 fxp_txeof(sc); 2014 2015 /* 2016 * If we haven't received any packets in FXP_MAC_RX_IDLE seconds, 2017 * then assume the receiver has locked up and attempt to clear 2018 * the condition by reprogramming the multicast filter. This is 2019 * a work-around for a bug in the 82557 where the receiver locks 2020 * up if it gets certain types of garbage in the syncronization 2021 * bits prior to the packet header. This bug is supposed to only 2022 * occur in 10Mbps mode, but has been seen to occur in 100Mbps 2023 * mode as well (perhaps due to a 10/100 speed transition). 2024 */ 2025 if (sc->rx_idle_secs > FXP_MAX_RX_IDLE) { 2026 sc->rx_idle_secs = 0; 2027 fxp_mc_setup(sc); 2028 } 2029 /* 2030 * If there is no pending command, start another stats 2031 * dump. Otherwise punt for now. 2032 */ 2033 if (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) == 0) { 2034 /* 2035 * Start another stats dump. 2036 */ 2037 bus_dmamap_sync(sc->fxp_stag, sc->fxp_smap, 2038 BUS_DMASYNC_PREREAD); 2039 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_DUMPRESET); 2040 } else { 2041 /* 2042 * A previous command is still waiting to be accepted. 2043 * Just zero our copy of the stats and wait for the 2044 * next timer event to update them. 2045 */ 2046 sp->tx_good = 0; 2047 sp->tx_underruns = 0; 2048 sp->tx_total_collisions = 0; 2049 2050 sp->rx_good = 0; 2051 sp->rx_crc_errors = 0; 2052 sp->rx_alignment_errors = 0; 2053 sp->rx_rnr_errors = 0; 2054 sp->rx_overrun_errors = 0; 2055 } 2056 if (sc->miibus != NULL) 2057 mii_tick(device_get_softc(sc->miibus)); 2058 2059 /* 2060 * Check that chip hasn't hung. 2061 */ 2062 fxp_watchdog(sc); 2063 2064 /* 2065 * Schedule another timeout one second from now. 2066 */ 2067 callout_reset(&sc->stat_ch, hz, fxp_tick, sc); 2068 } 2069 2070 /* 2071 * Stop the interface. Cancels the statistics updater and resets 2072 * the interface. 2073 */ 2074 static void 2075 fxp_stop(struct fxp_softc *sc) 2076 { 2077 struct ifnet *ifp = sc->ifp; 2078 struct fxp_tx *txp; 2079 int i; 2080 2081 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 2082 sc->watchdog_timer = 0; 2083 2084 /* 2085 * Cancel stats updater. 2086 */ 2087 callout_stop(&sc->stat_ch); 2088 2089 /* 2090 * Preserve PCI configuration, configure, IA/multicast 2091 * setup and put RU and CU into idle state. 2092 */ 2093 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET); 2094 DELAY(50); 2095 /* Disable interrupts. */ 2096 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE); 2097 2098 /* 2099 * Release any xmit buffers. 2100 */ 2101 txp = sc->fxp_desc.tx_list; 2102 if (txp != NULL) { 2103 for (i = 0; i < FXP_NTXCB; i++) { 2104 if (txp[i].tx_mbuf != NULL) { 2105 bus_dmamap_sync(sc->fxp_mtag, txp[i].tx_map, 2106 BUS_DMASYNC_POSTWRITE); 2107 bus_dmamap_unload(sc->fxp_mtag, txp[i].tx_map); 2108 m_freem(txp[i].tx_mbuf); 2109 txp[i].tx_mbuf = NULL; 2110 /* clear this to reset csum offload bits */ 2111 txp[i].tx_cb->tbd[0].tb_addr = 0; 2112 } 2113 } 2114 } 2115 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE); 2116 sc->tx_queued = 0; 2117 } 2118 2119 /* 2120 * Watchdog/transmission transmit timeout handler. Called when a 2121 * transmission is started on the interface, but no interrupt is 2122 * received before the timeout. This usually indicates that the 2123 * card has wedged for some reason. 2124 */ 2125 static void 2126 fxp_watchdog(struct fxp_softc *sc) 2127 { 2128 2129 FXP_LOCK_ASSERT(sc, MA_OWNED); 2130 2131 if (sc->watchdog_timer == 0 || --sc->watchdog_timer) 2132 return; 2133 2134 device_printf(sc->dev, "device timeout\n"); 2135 sc->ifp->if_oerrors++; 2136 2137 fxp_init_body(sc); 2138 } 2139 2140 /* 2141 * Acquire locks and then call the real initialization function. This 2142 * is necessary because ether_ioctl() calls if_init() and this would 2143 * result in mutex recursion if the mutex was held. 2144 */ 2145 static void 2146 fxp_init(void *xsc) 2147 { 2148 struct fxp_softc *sc = xsc; 2149 2150 FXP_LOCK(sc); 2151 fxp_init_body(sc); 2152 FXP_UNLOCK(sc); 2153 } 2154 2155 /* 2156 * Perform device initialization. This routine must be called with the 2157 * softc lock held. 2158 */ 2159 static void 2160 fxp_init_body(struct fxp_softc *sc) 2161 { 2162 struct ifnet *ifp = sc->ifp; 2163 struct fxp_cb_config *cbp; 2164 struct fxp_cb_ias *cb_ias; 2165 struct fxp_cb_tx *tcbp; 2166 struct fxp_tx *txp; 2167 struct fxp_cb_mcs *mcsp; 2168 int i, prm; 2169 2170 FXP_LOCK_ASSERT(sc, MA_OWNED); 2171 /* 2172 * Cancel any pending I/O 2173 */ 2174 fxp_stop(sc); 2175 2176 /* 2177 * Issue software reset, which also unloads the microcode. 2178 */ 2179 sc->flags &= ~FXP_FLAG_UCODE; 2180 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SOFTWARE_RESET); 2181 DELAY(50); 2182 2183 prm = (ifp->if_flags & IFF_PROMISC) ? 1 : 0; 2184 2185 /* 2186 * Initialize base of CBL and RFA memory. Loading with zero 2187 * sets it up for regular linear addressing. 2188 */ 2189 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 0); 2190 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_BASE); 2191 2192 fxp_scb_wait(sc); 2193 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_BASE); 2194 2195 /* 2196 * Initialize base of dump-stats buffer. 2197 */ 2198 fxp_scb_wait(sc); 2199 bus_dmamap_sync(sc->fxp_stag, sc->fxp_smap, BUS_DMASYNC_PREREAD); 2200 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->stats_addr); 2201 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_DUMP_ADR); 2202 2203 /* 2204 * Attempt to load microcode if requested. 2205 */ 2206 if (ifp->if_flags & IFF_LINK0 && (sc->flags & FXP_FLAG_UCODE) == 0) 2207 fxp_load_ucode(sc); 2208 2209 /* 2210 * Initialize the multicast address list. 2211 */ 2212 if (fxp_mc_addrs(sc)) { 2213 mcsp = sc->mcsp; 2214 mcsp->cb_status = 0; 2215 mcsp->cb_command = 2216 htole16(FXP_CB_COMMAND_MCAS | FXP_CB_COMMAND_EL); 2217 mcsp->link_addr = 0xffffffff; 2218 /* 2219 * Start the multicast setup command. 2220 */ 2221 fxp_scb_wait(sc); 2222 bus_dmamap_sync(sc->mcs_tag, sc->mcs_map, BUS_DMASYNC_PREWRITE); 2223 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->mcs_addr); 2224 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2225 /* ...and wait for it to complete. */ 2226 fxp_dma_wait(sc, &mcsp->cb_status, sc->mcs_tag, sc->mcs_map); 2227 bus_dmamap_sync(sc->mcs_tag, sc->mcs_map, 2228 BUS_DMASYNC_POSTWRITE); 2229 } 2230 2231 /* 2232 * We temporarily use memory that contains the TxCB list to 2233 * construct the config CB. The TxCB list memory is rebuilt 2234 * later. 2235 */ 2236 cbp = (struct fxp_cb_config *)sc->fxp_desc.cbl_list; 2237 2238 /* 2239 * This bcopy is kind of disgusting, but there are a bunch of must be 2240 * zero and must be one bits in this structure and this is the easiest 2241 * way to initialize them all to proper values. 2242 */ 2243 bcopy(fxp_cb_config_template, cbp, sizeof(fxp_cb_config_template)); 2244 2245 cbp->cb_status = 0; 2246 cbp->cb_command = htole16(FXP_CB_COMMAND_CONFIG | 2247 FXP_CB_COMMAND_EL); 2248 cbp->link_addr = 0xffffffff; /* (no) next command */ 2249 cbp->byte_count = sc->flags & FXP_FLAG_EXT_RFA ? 32 : 22; 2250 cbp->rx_fifo_limit = 8; /* rx fifo threshold (32 bytes) */ 2251 cbp->tx_fifo_limit = 0; /* tx fifo threshold (0 bytes) */ 2252 cbp->adaptive_ifs = 0; /* (no) adaptive interframe spacing */ 2253 cbp->mwi_enable = sc->flags & FXP_FLAG_MWI_ENABLE ? 1 : 0; 2254 cbp->type_enable = 0; /* actually reserved */ 2255 cbp->read_align_en = sc->flags & FXP_FLAG_READ_ALIGN ? 1 : 0; 2256 cbp->end_wr_on_cl = sc->flags & FXP_FLAG_WRITE_ALIGN ? 1 : 0; 2257 cbp->rx_dma_bytecount = 0; /* (no) rx DMA max */ 2258 cbp->tx_dma_bytecount = 0; /* (no) tx DMA max */ 2259 cbp->dma_mbce = 0; /* (disable) dma max counters */ 2260 cbp->late_scb = 0; /* (don't) defer SCB update */ 2261 cbp->direct_dma_dis = 1; /* disable direct rcv dma mode */ 2262 cbp->tno_int_or_tco_en =0; /* (disable) tx not okay interrupt */ 2263 cbp->ci_int = 1; /* interrupt on CU idle */ 2264 cbp->ext_txcb_dis = sc->flags & FXP_FLAG_EXT_TXCB ? 0 : 1; 2265 cbp->ext_stats_dis = 1; /* disable extended counters */ 2266 cbp->keep_overrun_rx = 0; /* don't pass overrun frames to host */ 2267 cbp->save_bf = sc->flags & FXP_FLAG_SAVE_BAD ? 1 : prm; 2268 cbp->disc_short_rx = !prm; /* discard short packets */ 2269 cbp->underrun_retry = 1; /* retry mode (once) on DMA underrun */ 2270 cbp->two_frames = 0; /* do not limit FIFO to 2 frames */ 2271 cbp->dyn_tbd = sc->flags & FXP_FLAG_EXT_RFA ? 1 : 0; 2272 cbp->ext_rfa = sc->flags & FXP_FLAG_EXT_RFA ? 1 : 0; 2273 cbp->mediatype = sc->flags & FXP_FLAG_SERIAL_MEDIA ? 0 : 1; 2274 cbp->csma_dis = 0; /* (don't) disable link */ 2275 cbp->tcp_udp_cksum = ((sc->flags & FXP_FLAG_82559_RXCSUM) != 0 && 2276 (ifp->if_capenable & IFCAP_RXCSUM) != 0) ? 1 : 0; 2277 cbp->vlan_tco = 0; /* (don't) enable vlan wakeup */ 2278 cbp->link_wake_en = 0; /* (don't) assert PME# on link change */ 2279 cbp->arp_wake_en = 0; /* (don't) assert PME# on arp */ 2280 cbp->mc_wake_en = 0; /* (don't) enable PME# on mcmatch */ 2281 cbp->nsai = 1; /* (don't) disable source addr insert */ 2282 cbp->preamble_length = 2; /* (7 byte) preamble */ 2283 cbp->loopback = 0; /* (don't) loopback */ 2284 cbp->linear_priority = 0; /* (normal CSMA/CD operation) */ 2285 cbp->linear_pri_mode = 0; /* (wait after xmit only) */ 2286 cbp->interfrm_spacing = 6; /* (96 bits of) interframe spacing */ 2287 cbp->promiscuous = prm; /* promiscuous mode */ 2288 cbp->bcast_disable = 0; /* (don't) disable broadcasts */ 2289 cbp->wait_after_win = 0; /* (don't) enable modified backoff alg*/ 2290 cbp->ignore_ul = 0; /* consider U/L bit in IA matching */ 2291 cbp->crc16_en = 0; /* (don't) enable crc-16 algorithm */ 2292 cbp->crscdt = sc->flags & FXP_FLAG_SERIAL_MEDIA ? 1 : 0; 2293 2294 cbp->stripping = !prm; /* truncate rx packet to byte count */ 2295 cbp->padding = 1; /* (do) pad short tx packets */ 2296 cbp->rcv_crc_xfer = 0; /* (don't) xfer CRC to host */ 2297 cbp->long_rx_en = sc->flags & FXP_FLAG_LONG_PKT_EN ? 1 : 0; 2298 cbp->ia_wake_en = 0; /* (don't) wake up on address match */ 2299 cbp->magic_pkt_dis = sc->flags & FXP_FLAG_WOL ? 0 : 1; 2300 cbp->force_fdx = 0; /* (don't) force full duplex */ 2301 cbp->fdx_pin_en = 1; /* (enable) FDX# pin */ 2302 cbp->multi_ia = 0; /* (don't) accept multiple IAs */ 2303 cbp->mc_all = sc->flags & FXP_FLAG_ALL_MCAST ? 1 : 0; 2304 cbp->gamla_rx = sc->flags & FXP_FLAG_EXT_RFA ? 1 : 0; 2305 cbp->vlan_strip_en = ((sc->flags & FXP_FLAG_EXT_RFA) != 0 && 2306 (ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0) ? 1 : 0; 2307 2308 if (sc->tunable_noflow || sc->revision == FXP_REV_82557) { 2309 /* 2310 * The 82557 has no hardware flow control, the values 2311 * below are the defaults for the chip. 2312 */ 2313 cbp->fc_delay_lsb = 0; 2314 cbp->fc_delay_msb = 0x40; 2315 cbp->pri_fc_thresh = 3; 2316 cbp->tx_fc_dis = 0; 2317 cbp->rx_fc_restop = 0; 2318 cbp->rx_fc_restart = 0; 2319 cbp->fc_filter = 0; 2320 cbp->pri_fc_loc = 1; 2321 } else { 2322 cbp->fc_delay_lsb = 0x1f; 2323 cbp->fc_delay_msb = 0x01; 2324 cbp->pri_fc_thresh = 3; 2325 cbp->tx_fc_dis = 0; /* enable transmit FC */ 2326 cbp->rx_fc_restop = 1; /* enable FC restop frames */ 2327 cbp->rx_fc_restart = 1; /* enable FC restart frames */ 2328 cbp->fc_filter = !prm; /* drop FC frames to host */ 2329 cbp->pri_fc_loc = 1; /* FC pri location (byte31) */ 2330 } 2331 2332 /* 2333 * Start the config command/DMA. 2334 */ 2335 fxp_scb_wait(sc); 2336 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE); 2337 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->fxp_desc.cbl_addr); 2338 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2339 /* ...and wait for it to complete. */ 2340 fxp_dma_wait(sc, &cbp->cb_status, sc->cbl_tag, sc->cbl_map); 2341 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_POSTWRITE); 2342 2343 /* 2344 * Now initialize the station address. Temporarily use the TxCB 2345 * memory area like we did above for the config CB. 2346 */ 2347 cb_ias = (struct fxp_cb_ias *)sc->fxp_desc.cbl_list; 2348 cb_ias->cb_status = 0; 2349 cb_ias->cb_command = htole16(FXP_CB_COMMAND_IAS | FXP_CB_COMMAND_EL); 2350 cb_ias->link_addr = 0xffffffff; 2351 bcopy(IF_LLADDR(sc->ifp), cb_ias->macaddr, ETHER_ADDR_LEN); 2352 2353 /* 2354 * Start the IAS (Individual Address Setup) command/DMA. 2355 */ 2356 fxp_scb_wait(sc); 2357 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE); 2358 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2359 /* ...and wait for it to complete. */ 2360 fxp_dma_wait(sc, &cb_ias->cb_status, sc->cbl_tag, sc->cbl_map); 2361 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_POSTWRITE); 2362 2363 /* 2364 * Initialize transmit control block (TxCB) list. 2365 */ 2366 txp = sc->fxp_desc.tx_list; 2367 tcbp = sc->fxp_desc.cbl_list; 2368 bzero(tcbp, FXP_TXCB_SZ); 2369 for (i = 0; i < FXP_NTXCB; i++) { 2370 txp[i].tx_mbuf = NULL; 2371 tcbp[i].cb_status = htole16(FXP_CB_STATUS_C | FXP_CB_STATUS_OK); 2372 tcbp[i].cb_command = htole16(FXP_CB_COMMAND_NOP); 2373 tcbp[i].link_addr = htole32(sc->fxp_desc.cbl_addr + 2374 (((i + 1) & FXP_TXCB_MASK) * sizeof(struct fxp_cb_tx))); 2375 if (sc->flags & FXP_FLAG_EXT_TXCB) 2376 tcbp[i].tbd_array_addr = 2377 htole32(FXP_TXCB_DMA_ADDR(sc, &tcbp[i].tbd[2])); 2378 else 2379 tcbp[i].tbd_array_addr = 2380 htole32(FXP_TXCB_DMA_ADDR(sc, &tcbp[i].tbd[0])); 2381 txp[i].tx_next = &txp[(i + 1) & FXP_TXCB_MASK]; 2382 } 2383 /* 2384 * Set the suspend flag on the first TxCB and start the control 2385 * unit. It will execute the NOP and then suspend. 2386 */ 2387 tcbp->cb_command = htole16(FXP_CB_COMMAND_NOP | FXP_CB_COMMAND_S); 2388 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE); 2389 sc->fxp_desc.tx_first = sc->fxp_desc.tx_last = txp; 2390 sc->tx_queued = 1; 2391 2392 fxp_scb_wait(sc); 2393 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2394 2395 /* 2396 * Initialize receiver buffer area - RFA. 2397 */ 2398 fxp_scb_wait(sc); 2399 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->fxp_desc.rx_head->rx_addr); 2400 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_START); 2401 2402 /* 2403 * Set current media. 2404 */ 2405 if (sc->miibus != NULL) 2406 mii_mediachg(device_get_softc(sc->miibus)); 2407 2408 ifp->if_drv_flags |= IFF_DRV_RUNNING; 2409 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 2410 2411 /* 2412 * Enable interrupts. 2413 */ 2414 #ifdef DEVICE_POLLING 2415 /* 2416 * ... but only do that if we are not polling. And because (presumably) 2417 * the default is interrupts on, we need to disable them explicitly! 2418 */ 2419 if (ifp->if_capenable & IFCAP_POLLING ) 2420 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE); 2421 else 2422 #endif /* DEVICE_POLLING */ 2423 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, 0); 2424 2425 /* 2426 * Start stats updater. 2427 */ 2428 callout_reset(&sc->stat_ch, hz, fxp_tick, sc); 2429 } 2430 2431 static int 2432 fxp_serial_ifmedia_upd(struct ifnet *ifp) 2433 { 2434 2435 return (0); 2436 } 2437 2438 static void 2439 fxp_serial_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 2440 { 2441 2442 ifmr->ifm_active = IFM_ETHER|IFM_MANUAL; 2443 } 2444 2445 /* 2446 * Change media according to request. 2447 */ 2448 static int 2449 fxp_ifmedia_upd(struct ifnet *ifp) 2450 { 2451 struct fxp_softc *sc = ifp->if_softc; 2452 struct mii_data *mii; 2453 2454 mii = device_get_softc(sc->miibus); 2455 FXP_LOCK(sc); 2456 if (mii->mii_instance) { 2457 struct mii_softc *miisc; 2458 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 2459 mii_phy_reset(miisc); 2460 } 2461 mii_mediachg(mii); 2462 FXP_UNLOCK(sc); 2463 return (0); 2464 } 2465 2466 /* 2467 * Notify the world which media we're using. 2468 */ 2469 static void 2470 fxp_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 2471 { 2472 struct fxp_softc *sc = ifp->if_softc; 2473 struct mii_data *mii; 2474 2475 mii = device_get_softc(sc->miibus); 2476 FXP_LOCK(sc); 2477 mii_pollstat(mii); 2478 ifmr->ifm_active = mii->mii_media_active; 2479 ifmr->ifm_status = mii->mii_media_status; 2480 2481 if (IFM_SUBTYPE(ifmr->ifm_active) == IFM_10_T && 2482 sc->flags & FXP_FLAG_CU_RESUME_BUG) 2483 sc->cu_resume_bug = 1; 2484 else 2485 sc->cu_resume_bug = 0; 2486 FXP_UNLOCK(sc); 2487 } 2488 2489 /* 2490 * Add a buffer to the end of the RFA buffer list. 2491 * Return 0 if successful, 1 for failure. A failure results in 2492 * reusing the RFA buffer. 2493 * The RFA struct is stuck at the beginning of mbuf cluster and the 2494 * data pointer is fixed up to point just past it. 2495 */ 2496 static int 2497 fxp_new_rfabuf(struct fxp_softc *sc, struct fxp_rx *rxp) 2498 { 2499 struct mbuf *m; 2500 struct fxp_rfa *rfa; 2501 bus_dmamap_t tmp_map; 2502 int error; 2503 2504 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 2505 if (m == NULL) 2506 return (ENOBUFS); 2507 2508 /* 2509 * Move the data pointer up so that the incoming data packet 2510 * will be 32-bit aligned. 2511 */ 2512 m->m_data += RFA_ALIGNMENT_FUDGE; 2513 2514 /* 2515 * Get a pointer to the base of the mbuf cluster and move 2516 * data start past it. 2517 */ 2518 rfa = mtod(m, struct fxp_rfa *); 2519 m->m_data += sc->rfa_size; 2520 rfa->size = htole16(MCLBYTES - sc->rfa_size - RFA_ALIGNMENT_FUDGE); 2521 2522 rfa->rfa_status = 0; 2523 rfa->rfa_control = htole16(FXP_RFA_CONTROL_EL); 2524 rfa->actual_size = 0; 2525 m->m_len = m->m_pkthdr.len = MCLBYTES - RFA_ALIGNMENT_FUDGE - 2526 sc->rfa_size; 2527 2528 /* 2529 * Initialize the rest of the RFA. Note that since the RFA 2530 * is misaligned, we cannot store values directly. We're thus 2531 * using the le32enc() function which handles endianness and 2532 * is also alignment-safe. 2533 */ 2534 le32enc(&rfa->link_addr, 0xffffffff); 2535 le32enc(&rfa->rbd_addr, 0xffffffff); 2536 2537 /* Map the RFA into DMA memory. */ 2538 error = bus_dmamap_load(sc->fxp_mtag, sc->spare_map, rfa, 2539 MCLBYTES - RFA_ALIGNMENT_FUDGE, fxp_dma_map_addr, 2540 &rxp->rx_addr, 0); 2541 if (error) { 2542 m_freem(m); 2543 return (error); 2544 } 2545 2546 bus_dmamap_unload(sc->fxp_mtag, rxp->rx_map); 2547 tmp_map = sc->spare_map; 2548 sc->spare_map = rxp->rx_map; 2549 rxp->rx_map = tmp_map; 2550 rxp->rx_mbuf = m; 2551 2552 bus_dmamap_sync(sc->fxp_mtag, rxp->rx_map, 2553 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2554 return (0); 2555 } 2556 2557 static void 2558 fxp_add_rfabuf(struct fxp_softc *sc, struct fxp_rx *rxp) 2559 { 2560 struct fxp_rfa *p_rfa; 2561 struct fxp_rx *p_rx; 2562 2563 /* 2564 * If there are other buffers already on the list, attach this 2565 * one to the end by fixing up the tail to point to this one. 2566 */ 2567 if (sc->fxp_desc.rx_head != NULL) { 2568 p_rx = sc->fxp_desc.rx_tail; 2569 p_rfa = (struct fxp_rfa *) 2570 (p_rx->rx_mbuf->m_ext.ext_buf + RFA_ALIGNMENT_FUDGE); 2571 p_rx->rx_next = rxp; 2572 le32enc(&p_rfa->link_addr, rxp->rx_addr); 2573 p_rfa->rfa_control = 0; 2574 bus_dmamap_sync(sc->fxp_mtag, p_rx->rx_map, 2575 BUS_DMASYNC_PREWRITE); 2576 } else { 2577 rxp->rx_next = NULL; 2578 sc->fxp_desc.rx_head = rxp; 2579 } 2580 sc->fxp_desc.rx_tail = rxp; 2581 } 2582 2583 static void 2584 fxp_discard_rfabuf(struct fxp_softc *sc, struct fxp_rx *rxp) 2585 { 2586 struct mbuf *m; 2587 struct fxp_rfa *rfa; 2588 2589 m = rxp->rx_mbuf; 2590 m->m_data = m->m_ext.ext_buf; 2591 /* 2592 * Move the data pointer up so that the incoming data packet 2593 * will be 32-bit aligned. 2594 */ 2595 m->m_data += RFA_ALIGNMENT_FUDGE; 2596 2597 /* 2598 * Get a pointer to the base of the mbuf cluster and move 2599 * data start past it. 2600 */ 2601 rfa = mtod(m, struct fxp_rfa *); 2602 m->m_data += sc->rfa_size; 2603 rfa->size = htole16(MCLBYTES - sc->rfa_size - RFA_ALIGNMENT_FUDGE); 2604 2605 rfa->rfa_status = 0; 2606 rfa->rfa_control = htole16(FXP_RFA_CONTROL_EL); 2607 rfa->actual_size = 0; 2608 2609 /* 2610 * Initialize the rest of the RFA. Note that since the RFA 2611 * is misaligned, we cannot store values directly. We're thus 2612 * using the le32enc() function which handles endianness and 2613 * is also alignment-safe. 2614 */ 2615 le32enc(&rfa->link_addr, 0xffffffff); 2616 le32enc(&rfa->rbd_addr, 0xffffffff); 2617 2618 bus_dmamap_sync(sc->fxp_mtag, rxp->rx_map, 2619 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2620 } 2621 2622 static int 2623 fxp_miibus_readreg(device_t dev, int phy, int reg) 2624 { 2625 struct fxp_softc *sc = device_get_softc(dev); 2626 int count = 10000; 2627 int value; 2628 2629 CSR_WRITE_4(sc, FXP_CSR_MDICONTROL, 2630 (FXP_MDI_READ << 26) | (reg << 16) | (phy << 21)); 2631 2632 while (((value = CSR_READ_4(sc, FXP_CSR_MDICONTROL)) & 0x10000000) == 0 2633 && count--) 2634 DELAY(10); 2635 2636 if (count <= 0) 2637 device_printf(dev, "fxp_miibus_readreg: timed out\n"); 2638 2639 return (value & 0xffff); 2640 } 2641 2642 static void 2643 fxp_miibus_writereg(device_t dev, int phy, int reg, int value) 2644 { 2645 struct fxp_softc *sc = device_get_softc(dev); 2646 int count = 10000; 2647 2648 CSR_WRITE_4(sc, FXP_CSR_MDICONTROL, 2649 (FXP_MDI_WRITE << 26) | (reg << 16) | (phy << 21) | 2650 (value & 0xffff)); 2651 2652 while ((CSR_READ_4(sc, FXP_CSR_MDICONTROL) & 0x10000000) == 0 && 2653 count--) 2654 DELAY(10); 2655 2656 if (count <= 0) 2657 device_printf(dev, "fxp_miibus_writereg: timed out\n"); 2658 } 2659 2660 static int 2661 fxp_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 2662 { 2663 struct fxp_softc *sc = ifp->if_softc; 2664 struct ifreq *ifr = (struct ifreq *)data; 2665 struct mii_data *mii; 2666 int flag, mask, error = 0, reinit; 2667 2668 switch (command) { 2669 case SIOCSIFFLAGS: 2670 FXP_LOCK(sc); 2671 if (ifp->if_flags & IFF_ALLMULTI) 2672 sc->flags |= FXP_FLAG_ALL_MCAST; 2673 else 2674 sc->flags &= ~FXP_FLAG_ALL_MCAST; 2675 2676 /* 2677 * If interface is marked up and not running, then start it. 2678 * If it is marked down and running, stop it. 2679 * XXX If it's up then re-initialize it. This is so flags 2680 * such as IFF_PROMISC are handled. 2681 */ 2682 if (ifp->if_flags & IFF_UP) { 2683 fxp_init_body(sc); 2684 } else { 2685 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 2686 fxp_stop(sc); 2687 } 2688 FXP_UNLOCK(sc); 2689 break; 2690 2691 case SIOCADDMULTI: 2692 case SIOCDELMULTI: 2693 FXP_LOCK(sc); 2694 if (ifp->if_flags & IFF_ALLMULTI) 2695 sc->flags |= FXP_FLAG_ALL_MCAST; 2696 else 2697 sc->flags &= ~FXP_FLAG_ALL_MCAST; 2698 /* 2699 * Multicast list has changed; set the hardware filter 2700 * accordingly. 2701 */ 2702 if ((sc->flags & FXP_FLAG_ALL_MCAST) == 0) 2703 fxp_mc_setup(sc); 2704 /* 2705 * fxp_mc_setup() can set FXP_FLAG_ALL_MCAST, so check it 2706 * again rather than else {}. 2707 */ 2708 if (sc->flags & FXP_FLAG_ALL_MCAST) 2709 fxp_init_body(sc); 2710 FXP_UNLOCK(sc); 2711 error = 0; 2712 break; 2713 2714 case SIOCSIFMEDIA: 2715 case SIOCGIFMEDIA: 2716 if (sc->miibus != NULL) { 2717 mii = device_get_softc(sc->miibus); 2718 error = ifmedia_ioctl(ifp, ifr, 2719 &mii->mii_media, command); 2720 } else { 2721 error = ifmedia_ioctl(ifp, ifr, &sc->sc_media, command); 2722 } 2723 break; 2724 2725 case SIOCSIFCAP: 2726 reinit = 0; 2727 mask = ifp->if_capenable ^ ifr->ifr_reqcap; 2728 #ifdef DEVICE_POLLING 2729 if (mask & IFCAP_POLLING) { 2730 if (ifr->ifr_reqcap & IFCAP_POLLING) { 2731 error = ether_poll_register(fxp_poll, ifp); 2732 if (error) 2733 return(error); 2734 FXP_LOCK(sc); 2735 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, 2736 FXP_SCB_INTR_DISABLE); 2737 ifp->if_capenable |= IFCAP_POLLING; 2738 FXP_UNLOCK(sc); 2739 } else { 2740 error = ether_poll_deregister(ifp); 2741 /* Enable interrupts in any case */ 2742 FXP_LOCK(sc); 2743 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, 0); 2744 ifp->if_capenable &= ~IFCAP_POLLING; 2745 FXP_UNLOCK(sc); 2746 } 2747 } 2748 #endif 2749 FXP_LOCK(sc); 2750 if ((mask & IFCAP_TXCSUM) != 0 && 2751 (ifp->if_capabilities & IFCAP_TXCSUM) != 0) { 2752 ifp->if_capenable ^= IFCAP_TXCSUM; 2753 if ((ifp->if_capenable & IFCAP_TXCSUM) != 0) 2754 ifp->if_hwassist |= FXP_CSUM_FEATURES; 2755 else 2756 ifp->if_hwassist &= ~FXP_CSUM_FEATURES; 2757 } 2758 if ((mask & IFCAP_RXCSUM) != 0 && 2759 (ifp->if_capabilities & IFCAP_RXCSUM) != 0) { 2760 ifp->if_capenable ^= IFCAP_RXCSUM; 2761 if ((sc->flags & FXP_FLAG_82559_RXCSUM) != 0) 2762 reinit++; 2763 } 2764 if ((mask & IFCAP_TSO4) != 0 && 2765 (ifp->if_capabilities & IFCAP_TSO4) != 0) { 2766 ifp->if_capenable ^= IFCAP_TSO4; 2767 if ((ifp->if_capenable & IFCAP_TSO4) != 0) 2768 ifp->if_hwassist |= CSUM_TSO; 2769 else 2770 ifp->if_hwassist &= ~CSUM_TSO; 2771 } 2772 if ((mask & IFCAP_WOL_MAGIC) != 0 && 2773 (ifp->if_capabilities & IFCAP_WOL_MAGIC) != 0) 2774 ifp->if_capenable ^= IFCAP_WOL_MAGIC; 2775 if ((mask & IFCAP_VLAN_MTU) != 0 && 2776 (ifp->if_capabilities & IFCAP_VLAN_MTU) != 0) { 2777 ifp->if_capenable ^= IFCAP_VLAN_MTU; 2778 if (sc->revision != FXP_REV_82557) 2779 flag = FXP_FLAG_LONG_PKT_EN; 2780 else /* a hack to get long frames on the old chip */ 2781 flag = FXP_FLAG_SAVE_BAD; 2782 sc->flags ^= flag; 2783 if (ifp->if_flags & IFF_UP) 2784 reinit++; 2785 } 2786 if ((mask & IFCAP_VLAN_HWTAGGING) != 0 && 2787 (ifp->if_capabilities & IFCAP_VLAN_HWTAGGING) != 0) { 2788 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING; 2789 reinit++; 2790 } 2791 if (reinit > 0 && ifp->if_flags & IFF_UP) 2792 fxp_init_body(sc); 2793 FXP_UNLOCK(sc); 2794 VLAN_CAPABILITIES(ifp); 2795 break; 2796 2797 default: 2798 error = ether_ioctl(ifp, command, data); 2799 } 2800 return (error); 2801 } 2802 2803 /* 2804 * Fill in the multicast address list and return number of entries. 2805 */ 2806 static int 2807 fxp_mc_addrs(struct fxp_softc *sc) 2808 { 2809 struct fxp_cb_mcs *mcsp = sc->mcsp; 2810 struct ifnet *ifp = sc->ifp; 2811 struct ifmultiaddr *ifma; 2812 int nmcasts; 2813 2814 nmcasts = 0; 2815 if ((sc->flags & FXP_FLAG_ALL_MCAST) == 0) { 2816 IF_ADDR_LOCK(ifp); 2817 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 2818 if (ifma->ifma_addr->sa_family != AF_LINK) 2819 continue; 2820 if (nmcasts >= MAXMCADDR) { 2821 sc->flags |= FXP_FLAG_ALL_MCAST; 2822 nmcasts = 0; 2823 break; 2824 } 2825 bcopy(LLADDR((struct sockaddr_dl *)ifma->ifma_addr), 2826 &sc->mcsp->mc_addr[nmcasts][0], ETHER_ADDR_LEN); 2827 nmcasts++; 2828 } 2829 IF_ADDR_UNLOCK(ifp); 2830 } 2831 mcsp->mc_cnt = htole16(nmcasts * ETHER_ADDR_LEN); 2832 return (nmcasts); 2833 } 2834 2835 /* 2836 * Program the multicast filter. 2837 * 2838 * We have an artificial restriction that the multicast setup command 2839 * must be the first command in the chain, so we take steps to ensure 2840 * this. By requiring this, it allows us to keep up the performance of 2841 * the pre-initialized command ring (esp. link pointers) by not actually 2842 * inserting the mcsetup command in the ring - i.e. its link pointer 2843 * points to the TxCB ring, but the mcsetup descriptor itself is not part 2844 * of it. We then can do 'CU_START' on the mcsetup descriptor and have it 2845 * lead into the regular TxCB ring when it completes. 2846 * 2847 * This function must be called at splimp. 2848 */ 2849 static void 2850 fxp_mc_setup(struct fxp_softc *sc) 2851 { 2852 struct fxp_cb_mcs *mcsp = sc->mcsp; 2853 struct fxp_tx *txp; 2854 int count; 2855 2856 FXP_LOCK_ASSERT(sc, MA_OWNED); 2857 /* 2858 * If there are queued commands, we must wait until they are all 2859 * completed. If we are already waiting, then add a NOP command 2860 * with interrupt option so that we're notified when all commands 2861 * have been completed - fxp_start() ensures that no additional 2862 * TX commands will be added when need_mcsetup is true. 2863 */ 2864 if (sc->tx_queued) { 2865 /* 2866 * need_mcsetup will be true if we are already waiting for the 2867 * NOP command to be completed (see below). In this case, bail. 2868 */ 2869 if (sc->need_mcsetup) 2870 return; 2871 sc->need_mcsetup = 1; 2872 2873 /* 2874 * Add a NOP command with interrupt so that we are notified 2875 * when all TX commands have been processed. 2876 */ 2877 txp = sc->fxp_desc.tx_last->tx_next; 2878 txp->tx_mbuf = NULL; 2879 txp->tx_cb->cb_status = 0; 2880 txp->tx_cb->cb_command = htole16(FXP_CB_COMMAND_NOP | 2881 FXP_CB_COMMAND_S | FXP_CB_COMMAND_I); 2882 /* 2883 * Advance the end of list forward. 2884 */ 2885 sc->fxp_desc.tx_last->tx_cb->cb_command &= 2886 htole16(~FXP_CB_COMMAND_S); 2887 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE); 2888 sc->fxp_desc.tx_last = txp; 2889 sc->tx_queued++; 2890 /* 2891 * Issue a resume in case the CU has just suspended. 2892 */ 2893 fxp_scb_wait(sc); 2894 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_RESUME); 2895 /* 2896 * Set a 5 second timer just in case we don't hear from the 2897 * card again. 2898 */ 2899 sc->watchdog_timer = 5; 2900 2901 return; 2902 } 2903 sc->need_mcsetup = 0; 2904 2905 /* 2906 * Initialize multicast setup descriptor. 2907 */ 2908 mcsp->cb_status = 0; 2909 mcsp->cb_command = htole16(FXP_CB_COMMAND_MCAS | 2910 FXP_CB_COMMAND_S | FXP_CB_COMMAND_I); 2911 mcsp->link_addr = htole32(sc->fxp_desc.cbl_addr); 2912 txp = &sc->fxp_desc.mcs_tx; 2913 txp->tx_mbuf = NULL; 2914 txp->tx_cb = (struct fxp_cb_tx *)sc->mcsp; 2915 txp->tx_next = sc->fxp_desc.tx_list; 2916 (void) fxp_mc_addrs(sc); 2917 sc->fxp_desc.tx_first = sc->fxp_desc.tx_last = txp; 2918 sc->tx_queued = 1; 2919 2920 /* 2921 * Wait until command unit is not active. This should never 2922 * be the case when nothing is queued, but make sure anyway. 2923 */ 2924 count = 100; 2925 while ((CSR_READ_1(sc, FXP_CSR_SCB_RUSCUS) >> 6) == 2926 FXP_SCB_CUS_ACTIVE && --count) 2927 DELAY(10); 2928 if (count == 0) { 2929 device_printf(sc->dev, "command queue timeout\n"); 2930 return; 2931 } 2932 2933 /* 2934 * Start the multicast setup command. 2935 */ 2936 fxp_scb_wait(sc); 2937 bus_dmamap_sync(sc->mcs_tag, sc->mcs_map, BUS_DMASYNC_PREWRITE); 2938 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->mcs_addr); 2939 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2940 2941 sc->watchdog_timer = 2; 2942 return; 2943 } 2944 2945 static uint32_t fxp_ucode_d101a[] = D101_A_RCVBUNDLE_UCODE; 2946 static uint32_t fxp_ucode_d101b0[] = D101_B0_RCVBUNDLE_UCODE; 2947 static uint32_t fxp_ucode_d101ma[] = D101M_B_RCVBUNDLE_UCODE; 2948 static uint32_t fxp_ucode_d101s[] = D101S_RCVBUNDLE_UCODE; 2949 static uint32_t fxp_ucode_d102[] = D102_B_RCVBUNDLE_UCODE; 2950 static uint32_t fxp_ucode_d102c[] = D102_C_RCVBUNDLE_UCODE; 2951 static uint32_t fxp_ucode_d102e[] = D102_E_RCVBUNDLE_UCODE; 2952 2953 #define UCODE(x) x, sizeof(x)/sizeof(uint32_t) 2954 2955 struct ucode { 2956 uint32_t revision; 2957 uint32_t *ucode; 2958 int length; 2959 u_short int_delay_offset; 2960 u_short bundle_max_offset; 2961 } ucode_table[] = { 2962 { FXP_REV_82558_A4, UCODE(fxp_ucode_d101a), D101_CPUSAVER_DWORD, 0 }, 2963 { FXP_REV_82558_B0, UCODE(fxp_ucode_d101b0), D101_CPUSAVER_DWORD, 0 }, 2964 { FXP_REV_82559_A0, UCODE(fxp_ucode_d101ma), 2965 D101M_CPUSAVER_DWORD, D101M_CPUSAVER_BUNDLE_MAX_DWORD }, 2966 { FXP_REV_82559S_A, UCODE(fxp_ucode_d101s), 2967 D101S_CPUSAVER_DWORD, D101S_CPUSAVER_BUNDLE_MAX_DWORD }, 2968 { FXP_REV_82550, UCODE(fxp_ucode_d102), 2969 D102_B_CPUSAVER_DWORD, D102_B_CPUSAVER_BUNDLE_MAX_DWORD }, 2970 { FXP_REV_82550_C, UCODE(fxp_ucode_d102c), 2971 D102_C_CPUSAVER_DWORD, D102_C_CPUSAVER_BUNDLE_MAX_DWORD }, 2972 { FXP_REV_82551_F, UCODE(fxp_ucode_d102e), 2973 D102_E_CPUSAVER_DWORD, D102_E_CPUSAVER_BUNDLE_MAX_DWORD }, 2974 { 0, NULL, 0, 0, 0 } 2975 }; 2976 2977 static void 2978 fxp_load_ucode(struct fxp_softc *sc) 2979 { 2980 struct ucode *uc; 2981 struct fxp_cb_ucode *cbp; 2982 int i; 2983 2984 for (uc = ucode_table; uc->ucode != NULL; uc++) 2985 if (sc->revision == uc->revision) 2986 break; 2987 if (uc->ucode == NULL) 2988 return; 2989 cbp = (struct fxp_cb_ucode *)sc->fxp_desc.cbl_list; 2990 cbp->cb_status = 0; 2991 cbp->cb_command = htole16(FXP_CB_COMMAND_UCODE | FXP_CB_COMMAND_EL); 2992 cbp->link_addr = 0xffffffff; /* (no) next command */ 2993 for (i = 0; i < uc->length; i++) 2994 cbp->ucode[i] = htole32(uc->ucode[i]); 2995 if (uc->int_delay_offset) 2996 *(uint16_t *)&cbp->ucode[uc->int_delay_offset] = 2997 htole16(sc->tunable_int_delay + sc->tunable_int_delay / 2); 2998 if (uc->bundle_max_offset) 2999 *(uint16_t *)&cbp->ucode[uc->bundle_max_offset] = 3000 htole16(sc->tunable_bundle_max); 3001 /* 3002 * Download the ucode to the chip. 3003 */ 3004 fxp_scb_wait(sc); 3005 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE); 3006 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->fxp_desc.cbl_addr); 3007 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 3008 /* ...and wait for it to complete. */ 3009 fxp_dma_wait(sc, &cbp->cb_status, sc->cbl_tag, sc->cbl_map); 3010 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_POSTWRITE); 3011 device_printf(sc->dev, 3012 "Microcode loaded, int_delay: %d usec bundle_max: %d\n", 3013 sc->tunable_int_delay, 3014 uc->bundle_max_offset == 0 ? 0 : sc->tunable_bundle_max); 3015 sc->flags |= FXP_FLAG_UCODE; 3016 } 3017 3018 static int 3019 sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high) 3020 { 3021 int error, value; 3022 3023 value = *(int *)arg1; 3024 error = sysctl_handle_int(oidp, &value, 0, req); 3025 if (error || !req->newptr) 3026 return (error); 3027 if (value < low || value > high) 3028 return (EINVAL); 3029 *(int *)arg1 = value; 3030 return (0); 3031 } 3032 3033 /* 3034 * Interrupt delay is expressed in microseconds, a multiplier is used 3035 * to convert this to the appropriate clock ticks before using. 3036 */ 3037 static int 3038 sysctl_hw_fxp_int_delay(SYSCTL_HANDLER_ARGS) 3039 { 3040 return (sysctl_int_range(oidp, arg1, arg2, req, 300, 3000)); 3041 } 3042 3043 static int 3044 sysctl_hw_fxp_bundle_max(SYSCTL_HANDLER_ARGS) 3045 { 3046 return (sysctl_int_range(oidp, arg1, arg2, req, 1, 0xffff)); 3047 } 3048