1 /*- 2 * Copyright (c) 1995, David Greenman 3 * Copyright (c) 2001 Jonathan Lemon <jlemon@freebsd.org> 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice unmodified, this list of conditions, and the following 11 * disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 * 28 */ 29 30 /* 31 * Intel EtherExpress Pro/100B PCI Fast Ethernet driver 32 */ 33 34 #include <sys/cdefs.h> 35 __FBSDID("$FreeBSD$"); 36 37 #include <sys/param.h> 38 #include <sys/systm.h> 39 #include <sys/endian.h> 40 #include <sys/mbuf.h> 41 /* #include <sys/mutex.h> */ 42 #include <sys/kernel.h> 43 #include <sys/socket.h> 44 #include <sys/sysctl.h> 45 46 #include <net/if.h> 47 #include <net/if_dl.h> 48 #include <net/if_media.h> 49 50 #include <net/bpf.h> 51 #include <sys/sockio.h> 52 #include <sys/bus.h> 53 #include <machine/bus.h> 54 #include <sys/rman.h> 55 #include <machine/resource.h> 56 57 #include <net/ethernet.h> 58 #include <net/if_arp.h> 59 60 #include <machine/clock.h> /* for DELAY */ 61 62 #include <net/if_types.h> 63 #include <net/if_vlan_var.h> 64 65 #ifdef FXP_IP_CSUM_WAR 66 #include <netinet/in.h> 67 #include <netinet/in_systm.h> 68 #include <netinet/ip.h> 69 #include <machine/in_cksum.h> 70 #endif 71 72 #include <pci/pcivar.h> 73 #include <pci/pcireg.h> /* for PCIM_CMD_xxx */ 74 75 #include <dev/mii/mii.h> 76 #include <dev/mii/miivar.h> 77 78 #include <dev/fxp/if_fxpreg.h> 79 #include <dev/fxp/if_fxpvar.h> 80 #include <dev/fxp/rcvbundl.h> 81 82 MODULE_DEPEND(fxp, pci, 1, 1, 1); 83 MODULE_DEPEND(fxp, ether, 1, 1, 1); 84 MODULE_DEPEND(fxp, miibus, 1, 1, 1); 85 #include "miibus_if.h" 86 87 /* 88 * NOTE! On the Alpha, we have an alignment constraint. The 89 * card DMAs the packet immediately following the RFA. However, 90 * the first thing in the packet is a 14-byte Ethernet header. 91 * This means that the packet is misaligned. To compensate, 92 * we actually offset the RFA 2 bytes into the cluster. This 93 * alignes the packet after the Ethernet header at a 32-bit 94 * boundary. HOWEVER! This means that the RFA is misaligned! 95 */ 96 #define RFA_ALIGNMENT_FUDGE 2 97 98 /* 99 * Set initial transmit threshold at 64 (512 bytes). This is 100 * increased by 64 (512 bytes) at a time, to maximum of 192 101 * (1536 bytes), if an underrun occurs. 102 */ 103 static int tx_threshold = 64; 104 105 /* 106 * The configuration byte map has several undefined fields which 107 * must be one or must be zero. Set up a template for these bits 108 * only, (assuming a 82557 chip) leaving the actual configuration 109 * to fxp_init. 110 * 111 * See struct fxp_cb_config for the bit definitions. 112 */ 113 static u_char fxp_cb_config_template[] = { 114 0x0, 0x0, /* cb_status */ 115 0x0, 0x0, /* cb_command */ 116 0x0, 0x0, 0x0, 0x0, /* link_addr */ 117 0x0, /* 0 */ 118 0x0, /* 1 */ 119 0x0, /* 2 */ 120 0x0, /* 3 */ 121 0x0, /* 4 */ 122 0x0, /* 5 */ 123 0x32, /* 6 */ 124 0x0, /* 7 */ 125 0x0, /* 8 */ 126 0x0, /* 9 */ 127 0x6, /* 10 */ 128 0x0, /* 11 */ 129 0x0, /* 12 */ 130 0x0, /* 13 */ 131 0xf2, /* 14 */ 132 0x48, /* 15 */ 133 0x0, /* 16 */ 134 0x40, /* 17 */ 135 0xf0, /* 18 */ 136 0x0, /* 19 */ 137 0x3f, /* 20 */ 138 0x5 /* 21 */ 139 }; 140 141 struct fxp_ident { 142 u_int16_t devid; 143 char *name; 144 }; 145 146 /* 147 * Claim various Intel PCI device identifiers for this driver. The 148 * sub-vendor and sub-device field are extensively used to identify 149 * particular variants, but we don't currently differentiate between 150 * them. 151 */ 152 static struct fxp_ident fxp_ident_table[] = { 153 { 0x1029, "Intel 82559 PCI/CardBus Pro/100" }, 154 { 0x1030, "Intel 82559 Pro/100 Ethernet" }, 155 { 0x1031, "Intel 82801CAM (ICH3) Pro/100 VE Ethernet" }, 156 { 0x1032, "Intel 82801CAM (ICH3) Pro/100 VE Ethernet" }, 157 { 0x1033, "Intel 82801CAM (ICH3) Pro/100 VM Ethernet" }, 158 { 0x1034, "Intel 82801CAM (ICH3) Pro/100 VM Ethernet" }, 159 { 0x1035, "Intel 82801CAM (ICH3) Pro/100 Ethernet" }, 160 { 0x1036, "Intel 82801CAM (ICH3) Pro/100 Ethernet" }, 161 { 0x1037, "Intel 82801CAM (ICH3) Pro/100 Ethernet" }, 162 { 0x1038, "Intel 82801CAM (ICH3) Pro/100 VM Ethernet" }, 163 { 0x1039, "Intel 82801DB (ICH4) Pro/100 VE Ethernet" }, 164 { 0x103A, "Intel 82801DB (ICH4) Pro/100 Ethernet" }, 165 { 0x103B, "Intel 82801DB (ICH4) Pro/100 VM Ethernet" }, 166 { 0x103C, "Intel 82801DB (ICH4) Pro/100 Ethernet" }, 167 { 0x103D, "Intel 82801DB (ICH4) Pro/100 VE Ethernet" }, 168 { 0x103E, "Intel 82801DB (ICH4) Pro/100 VM Ethernet" }, 169 { 0x1059, "Intel 82551QM Pro/100 M Mobile Connection" }, 170 { 0x1209, "Intel 82559ER Embedded 10/100 Ethernet" }, 171 { 0x1229, "Intel 82557/8/9 EtherExpress Pro/100(B) Ethernet" }, 172 { 0x2449, "Intel 82801BA/CAM (ICH2/3) Pro/100 Ethernet" }, 173 { 0, NULL }, 174 }; 175 176 #ifdef FXP_IP_CSUM_WAR 177 #define FXP_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 178 #else 179 #define FXP_CSUM_FEATURES (CSUM_TCP | CSUM_UDP) 180 #endif 181 182 static int fxp_probe(device_t dev); 183 static int fxp_attach(device_t dev); 184 static int fxp_detach(device_t dev); 185 static int fxp_shutdown(device_t dev); 186 static int fxp_suspend(device_t dev); 187 static int fxp_resume(device_t dev); 188 189 static void fxp_intr(void *xsc); 190 static void fxp_intr_body(struct fxp_softc *sc, struct ifnet *ifp, 191 u_int8_t statack, int count); 192 static void fxp_init(void *xsc); 193 static void fxp_init_body(struct fxp_softc *sc); 194 static void fxp_tick(void *xsc); 195 static void fxp_powerstate_d0(device_t dev); 196 static void fxp_start(struct ifnet *ifp); 197 static void fxp_start_body(struct ifnet *ifp); 198 static void fxp_stop(struct fxp_softc *sc); 199 static void fxp_release(struct fxp_softc *sc); 200 static int fxp_ioctl(struct ifnet *ifp, u_long command, 201 caddr_t data); 202 static void fxp_watchdog(struct ifnet *ifp); 203 static int fxp_add_rfabuf(struct fxp_softc *sc, 204 struct fxp_rx *rxp); 205 static int fxp_mc_addrs(struct fxp_softc *sc); 206 static void fxp_mc_setup(struct fxp_softc *sc); 207 static u_int16_t fxp_eeprom_getword(struct fxp_softc *sc, int offset, 208 int autosize); 209 static void fxp_eeprom_putword(struct fxp_softc *sc, int offset, 210 u_int16_t data); 211 static void fxp_autosize_eeprom(struct fxp_softc *sc); 212 static void fxp_read_eeprom(struct fxp_softc *sc, u_short *data, 213 int offset, int words); 214 static void fxp_write_eeprom(struct fxp_softc *sc, u_short *data, 215 int offset, int words); 216 static int fxp_ifmedia_upd(struct ifnet *ifp); 217 static void fxp_ifmedia_sts(struct ifnet *ifp, 218 struct ifmediareq *ifmr); 219 static int fxp_serial_ifmedia_upd(struct ifnet *ifp); 220 static void fxp_serial_ifmedia_sts(struct ifnet *ifp, 221 struct ifmediareq *ifmr); 222 static volatile int fxp_miibus_readreg(device_t dev, int phy, int reg); 223 static void fxp_miibus_writereg(device_t dev, int phy, int reg, 224 int value); 225 static void fxp_load_ucode(struct fxp_softc *sc); 226 static int sysctl_int_range(SYSCTL_HANDLER_ARGS, 227 int low, int high); 228 static int sysctl_hw_fxp_bundle_max(SYSCTL_HANDLER_ARGS); 229 static int sysctl_hw_fxp_int_delay(SYSCTL_HANDLER_ARGS); 230 static __inline void fxp_scb_wait(struct fxp_softc *sc); 231 static __inline void fxp_scb_cmd(struct fxp_softc *sc, int cmd); 232 static __inline void fxp_dma_wait(struct fxp_softc *sc, 233 volatile u_int16_t *status, bus_dma_tag_t dmat, 234 bus_dmamap_t map); 235 236 static device_method_t fxp_methods[] = { 237 /* Device interface */ 238 DEVMETHOD(device_probe, fxp_probe), 239 DEVMETHOD(device_attach, fxp_attach), 240 DEVMETHOD(device_detach, fxp_detach), 241 DEVMETHOD(device_shutdown, fxp_shutdown), 242 DEVMETHOD(device_suspend, fxp_suspend), 243 DEVMETHOD(device_resume, fxp_resume), 244 245 /* MII interface */ 246 DEVMETHOD(miibus_readreg, fxp_miibus_readreg), 247 DEVMETHOD(miibus_writereg, fxp_miibus_writereg), 248 249 { 0, 0 } 250 }; 251 252 static driver_t fxp_driver = { 253 "fxp", 254 fxp_methods, 255 sizeof(struct fxp_softc), 256 }; 257 258 static devclass_t fxp_devclass; 259 260 DRIVER_MODULE(fxp, pci, fxp_driver, fxp_devclass, 0, 0); 261 DRIVER_MODULE(fxp, cardbus, fxp_driver, fxp_devclass, 0, 0); 262 DRIVER_MODULE(miibus, fxp, miibus_driver, miibus_devclass, 0, 0); 263 264 static int fxp_rnr; 265 SYSCTL_INT(_hw, OID_AUTO, fxp_rnr, CTLFLAG_RW, &fxp_rnr, 0, "fxp rnr events"); 266 267 static int fxp_noflow; 268 SYSCTL_INT(_hw, OID_AUTO, fxp_noflow, CTLFLAG_RW, &fxp_noflow, 0, "fxp flow control disabled"); 269 TUNABLE_INT("hw.fxp_noflow", &fxp_noflow); 270 271 /* 272 * Wait for the previous command to be accepted (but not necessarily 273 * completed). 274 */ 275 static __inline void 276 fxp_scb_wait(struct fxp_softc *sc) 277 { 278 int i = 10000; 279 280 while (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) && --i) 281 DELAY(2); 282 if (i == 0) 283 device_printf(sc->dev, "SCB timeout: 0x%x 0x%x 0x%x 0x%x\n", 284 CSR_READ_1(sc, FXP_CSR_SCB_COMMAND), 285 CSR_READ_1(sc, FXP_CSR_SCB_STATACK), 286 CSR_READ_1(sc, FXP_CSR_SCB_RUSCUS), 287 CSR_READ_2(sc, FXP_CSR_FLOWCONTROL)); 288 } 289 290 static __inline void 291 fxp_scb_cmd(struct fxp_softc *sc, int cmd) 292 { 293 294 if (cmd == FXP_SCB_COMMAND_CU_RESUME && sc->cu_resume_bug) { 295 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_CB_COMMAND_NOP); 296 fxp_scb_wait(sc); 297 } 298 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, cmd); 299 } 300 301 static __inline void 302 fxp_dma_wait(struct fxp_softc *sc, volatile u_int16_t *status, 303 bus_dma_tag_t dmat, bus_dmamap_t map) 304 { 305 int i = 10000; 306 307 bus_dmamap_sync(dmat, map, BUS_DMASYNC_POSTREAD); 308 while (!(le16toh(*status) & FXP_CB_STATUS_C) && --i) { 309 DELAY(2); 310 bus_dmamap_sync(dmat, map, BUS_DMASYNC_POSTREAD); 311 } 312 if (i == 0) 313 device_printf(sc->dev, "DMA timeout\n"); 314 } 315 316 /* 317 * Return identification string if this is device is ours. 318 */ 319 static int 320 fxp_probe(device_t dev) 321 { 322 u_int16_t devid; 323 struct fxp_ident *ident; 324 325 if (pci_get_vendor(dev) == FXP_VENDORID_INTEL) { 326 devid = pci_get_device(dev); 327 for (ident = fxp_ident_table; ident->name != NULL; ident++) { 328 if (ident->devid == devid) { 329 device_set_desc(dev, ident->name); 330 return (0); 331 } 332 } 333 } 334 return (ENXIO); 335 } 336 337 static void 338 fxp_powerstate_d0(device_t dev) 339 { 340 #if __FreeBSD_version >= 430002 341 u_int32_t iobase, membase, irq; 342 343 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 344 /* Save important PCI config data. */ 345 iobase = pci_read_config(dev, FXP_PCI_IOBA, 4); 346 membase = pci_read_config(dev, FXP_PCI_MMBA, 4); 347 irq = pci_read_config(dev, PCIR_INTLINE, 4); 348 349 /* Reset the power state. */ 350 device_printf(dev, "chip is in D%d power mode " 351 "-- setting to D0\n", pci_get_powerstate(dev)); 352 353 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 354 355 /* Restore PCI config data. */ 356 pci_write_config(dev, FXP_PCI_IOBA, iobase, 4); 357 pci_write_config(dev, FXP_PCI_MMBA, membase, 4); 358 pci_write_config(dev, PCIR_INTLINE, irq, 4); 359 } 360 #endif 361 } 362 363 static void 364 fxp_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error) 365 { 366 u_int32_t *addr; 367 368 if (error) 369 return; 370 371 KASSERT(nseg == 1, ("too many DMA segments, %d should be 1", nseg)); 372 addr = arg; 373 *addr = segs->ds_addr; 374 } 375 376 static int 377 fxp_attach(device_t dev) 378 { 379 int error = 0; 380 struct fxp_softc *sc = device_get_softc(dev); 381 struct ifnet *ifp; 382 struct fxp_rx *rxp; 383 u_int32_t val; 384 u_int16_t data, myea[ETHER_ADDR_LEN / 2]; 385 int i, rid, m1, m2, prefer_iomap, maxtxseg; 386 int s, ipcbxmit_disable; 387 388 sc->dev = dev; 389 callout_handle_init(&sc->stat_ch); 390 sysctl_ctx_init(&sc->sysctl_ctx); 391 mtx_init(&sc->sc_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 392 MTX_DEF); 393 ifmedia_init(&sc->sc_media, 0, fxp_serial_ifmedia_upd, 394 fxp_serial_ifmedia_sts); 395 396 s = splimp(); 397 398 /* 399 * Enable bus mastering. 400 */ 401 pci_enable_busmaster(dev); 402 val = pci_read_config(dev, PCIR_COMMAND, 2); 403 404 fxp_powerstate_d0(dev); 405 406 /* 407 * Figure out which we should try first - memory mapping or i/o mapping? 408 * We default to memory mapping. Then we accept an override from the 409 * command line. Then we check to see which one is enabled. 410 */ 411 m1 = PCIM_CMD_MEMEN; 412 m2 = PCIM_CMD_PORTEN; 413 prefer_iomap = 0; 414 if (resource_int_value(device_get_name(dev), device_get_unit(dev), 415 "prefer_iomap", &prefer_iomap) == 0 && prefer_iomap != 0) { 416 m1 = PCIM_CMD_PORTEN; 417 m2 = PCIM_CMD_MEMEN; 418 } 419 420 sc->rtp = (m1 == PCIM_CMD_MEMEN)? SYS_RES_MEMORY : SYS_RES_IOPORT; 421 sc->rgd = (m1 == PCIM_CMD_MEMEN)? FXP_PCI_MMBA : FXP_PCI_IOBA; 422 sc->mem = bus_alloc_resource(dev, sc->rtp, &sc->rgd, 423 0, ~0, 1, RF_ACTIVE); 424 if (sc->mem == NULL) { 425 sc->rtp = 426 (m2 == PCIM_CMD_MEMEN)? SYS_RES_MEMORY : SYS_RES_IOPORT; 427 sc->rgd = (m2 == PCIM_CMD_MEMEN)? FXP_PCI_MMBA : FXP_PCI_IOBA; 428 sc->mem = bus_alloc_resource(dev, sc->rtp, &sc->rgd, 429 0, ~0, 1, RF_ACTIVE); 430 } 431 432 if (!sc->mem) { 433 error = ENXIO; 434 goto fail; 435 } 436 if (bootverbose) { 437 device_printf(dev, "using %s space register mapping\n", 438 sc->rtp == SYS_RES_MEMORY? "memory" : "I/O"); 439 } 440 441 sc->sc_st = rman_get_bustag(sc->mem); 442 sc->sc_sh = rman_get_bushandle(sc->mem); 443 444 /* 445 * Allocate our interrupt. 446 */ 447 rid = 0; 448 sc->irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 449 RF_SHAREABLE | RF_ACTIVE); 450 if (sc->irq == NULL) { 451 device_printf(dev, "could not map interrupt\n"); 452 error = ENXIO; 453 goto fail; 454 } 455 456 /* 457 * Reset to a stable state. 458 */ 459 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET); 460 DELAY(10); 461 462 /* 463 * Find out how large of an SEEPROM we have. 464 */ 465 fxp_autosize_eeprom(sc); 466 467 /* 468 * Determine whether we must use the 503 serial interface. 469 */ 470 fxp_read_eeprom(sc, &data, 6, 1); 471 if ((data & FXP_PHY_DEVICE_MASK) != 0 && 472 (data & FXP_PHY_SERIAL_ONLY)) 473 sc->flags |= FXP_FLAG_SERIAL_MEDIA; 474 475 /* 476 * Create the sysctl tree 477 */ 478 sc->sysctl_tree = SYSCTL_ADD_NODE(&sc->sysctl_ctx, 479 SYSCTL_STATIC_CHILDREN(_hw), OID_AUTO, 480 device_get_nameunit(dev), CTLFLAG_RD, 0, ""); 481 if (sc->sysctl_tree == NULL) { 482 error = ENXIO; 483 goto fail; 484 } 485 SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree), 486 OID_AUTO, "int_delay", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_PRISON, 487 &sc->tunable_int_delay, 0, sysctl_hw_fxp_int_delay, "I", 488 "FXP driver receive interrupt microcode bundling delay"); 489 SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree), 490 OID_AUTO, "bundle_max", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_PRISON, 491 &sc->tunable_bundle_max, 0, sysctl_hw_fxp_bundle_max, "I", 492 "FXP driver receive interrupt microcode bundle size limit"); 493 494 /* 495 * Pull in device tunables. 496 */ 497 sc->tunable_int_delay = TUNABLE_INT_DELAY; 498 sc->tunable_bundle_max = TUNABLE_BUNDLE_MAX; 499 (void) resource_int_value(device_get_name(dev), device_get_unit(dev), 500 "int_delay", &sc->tunable_int_delay); 501 (void) resource_int_value(device_get_name(dev), device_get_unit(dev), 502 "bundle_max", &sc->tunable_bundle_max); 503 504 /* 505 * Find out the chip revision; lump all 82557 revs together. 506 */ 507 fxp_read_eeprom(sc, &data, 5, 1); 508 if ((data >> 8) == 1) 509 sc->revision = FXP_REV_82557; 510 else 511 sc->revision = pci_get_revid(dev); 512 513 /* 514 * Enable workarounds for certain chip revision deficiencies. 515 * 516 * Systems based on the ICH2/ICH2-M chip from Intel, and possibly 517 * some systems based a normal 82559 design, have a defect where 518 * the chip can cause a PCI protocol violation if it receives 519 * a CU_RESUME command when it is entering the IDLE state. The 520 * workaround is to disable Dynamic Standby Mode, so the chip never 521 * deasserts CLKRUN#, and always remains in an active state. 522 * 523 * See Intel 82801BA/82801BAM Specification Update, Errata #30. 524 */ 525 i = pci_get_device(dev); 526 if (i == 0x2449 || (i > 0x1030 && i < 0x1039) || 527 sc->revision >= FXP_REV_82559_A0) { 528 fxp_read_eeprom(sc, &data, 10, 1); 529 if (data & 0x02) { /* STB enable */ 530 u_int16_t cksum; 531 int i; 532 533 device_printf(dev, 534 "Disabling dynamic standby mode in EEPROM\n"); 535 data &= ~0x02; 536 fxp_write_eeprom(sc, &data, 10, 1); 537 device_printf(dev, "New EEPROM ID: 0x%x\n", data); 538 cksum = 0; 539 for (i = 0; i < (1 << sc->eeprom_size) - 1; i++) { 540 fxp_read_eeprom(sc, &data, i, 1); 541 cksum += data; 542 } 543 i = (1 << sc->eeprom_size) - 1; 544 cksum = 0xBABA - cksum; 545 fxp_read_eeprom(sc, &data, i, 1); 546 fxp_write_eeprom(sc, &cksum, i, 1); 547 device_printf(dev, 548 "EEPROM checksum @ 0x%x: 0x%x -> 0x%x\n", 549 i, data, cksum); 550 #if 1 551 /* 552 * If the user elects to continue, try the software 553 * workaround, as it is better than nothing. 554 */ 555 sc->flags |= FXP_FLAG_CU_RESUME_BUG; 556 #endif 557 } 558 } 559 560 /* 561 * If we are not a 82557 chip, we can enable extended features. 562 */ 563 if (sc->revision != FXP_REV_82557) { 564 /* 565 * If MWI is enabled in the PCI configuration, and there 566 * is a valid cacheline size (8 or 16 dwords), then tell 567 * the board to turn on MWI. 568 */ 569 if (val & PCIM_CMD_MWRICEN && 570 pci_read_config(dev, PCIR_CACHELNSZ, 1) != 0) 571 sc->flags |= FXP_FLAG_MWI_ENABLE; 572 573 /* turn on the extended TxCB feature */ 574 sc->flags |= FXP_FLAG_EXT_TXCB; 575 576 /* enable reception of long frames for VLAN */ 577 sc->flags |= FXP_FLAG_LONG_PKT_EN; 578 } 579 580 /* 581 * Enable use of extended RFDs and TCBs for 82550 582 * and later chips. Note: we need extended TXCB support 583 * too, but that's already enabled by the code above. 584 * Be careful to do this only on the right devices. 585 * 586 * At least some 82550 cards probed as "chip=0x12298086 rev=0x0d" 587 * truncate packets that end with an mbuf containing 1 to 3 bytes 588 * when used with this feature enabled in the previous version of the 589 * driver. This problem appears to be fixed now that the driver 590 * always sets the hardware parse bit in the IPCB structure, which 591 * the "Intel 8255x 10/100 Mbps Ethernet Controller Family Open 592 * Source Software Developer Manual" says is necessary in the 593 * cases where packet truncation was observed. 594 * 595 * The device hint "hint.fxp.UNIT_NUMBER.ipcbxmit_disable" 596 * allows this feature to be disabled at boot time. 597 * 598 * If fxp is not compiled into the kernel, this feature may also 599 * be disabled at run time: 600 * # kldunload fxp 601 * # kenv hint.fxp.0.ipcbxmit_disable=1 602 * # kldload fxp 603 */ 604 605 if (resource_int_value("fxp", device_get_unit(dev), "ipcbxmit_disable", 606 &ipcbxmit_disable) != 0) 607 ipcbxmit_disable = 0; 608 if (ipcbxmit_disable == 0 && (sc->revision == FXP_REV_82550 || 609 sc->revision == FXP_REV_82550_C)) { 610 sc->rfa_size = sizeof (struct fxp_rfa); 611 sc->tx_cmd = FXP_CB_COMMAND_IPCBXMIT; 612 sc->flags |= FXP_FLAG_EXT_RFA; 613 } else { 614 sc->rfa_size = sizeof (struct fxp_rfa) - FXP_RFAX_LEN; 615 sc->tx_cmd = FXP_CB_COMMAND_XMIT; 616 } 617 618 /* 619 * Allocate DMA tags and DMA safe memory. 620 */ 621 maxtxseg = sc->flags & FXP_FLAG_EXT_RFA ? FXP_NTXSEG - 1 : FXP_NTXSEG; 622 error = bus_dma_tag_create(NULL, 2, 0, BUS_SPACE_MAXADDR_32BIT, 623 BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES * maxtxseg, 624 maxtxseg, MCLBYTES, 0, &sc->fxp_mtag); 625 if (error) { 626 device_printf(dev, "could not allocate dma tag\n"); 627 goto fail; 628 } 629 630 error = bus_dma_tag_create(NULL, 4, 0, BUS_SPACE_MAXADDR_32BIT, 631 BUS_SPACE_MAXADDR, NULL, NULL, sizeof(struct fxp_stats), 1, 632 sizeof(struct fxp_stats), 0, &sc->fxp_stag); 633 if (error) { 634 device_printf(dev, "could not allocate dma tag\n"); 635 goto fail; 636 } 637 638 error = bus_dmamem_alloc(sc->fxp_stag, (void **)&sc->fxp_stats, 639 BUS_DMA_NOWAIT, &sc->fxp_smap); 640 if (error) 641 goto fail; 642 error = bus_dmamap_load(sc->fxp_stag, sc->fxp_smap, sc->fxp_stats, 643 sizeof(struct fxp_stats), fxp_dma_map_addr, &sc->stats_addr, 0); 644 if (error) { 645 device_printf(dev, "could not map the stats buffer\n"); 646 goto fail; 647 } 648 bzero(sc->fxp_stats, sizeof(struct fxp_stats)); 649 650 error = bus_dma_tag_create(NULL, 4, 0, BUS_SPACE_MAXADDR_32BIT, 651 BUS_SPACE_MAXADDR, NULL, NULL, FXP_TXCB_SZ, 1, 652 FXP_TXCB_SZ, 0, &sc->cbl_tag); 653 if (error) { 654 device_printf(dev, "could not allocate dma tag\n"); 655 goto fail; 656 } 657 658 error = bus_dmamem_alloc(sc->cbl_tag, (void **)&sc->fxp_desc.cbl_list, 659 BUS_DMA_NOWAIT, &sc->cbl_map); 660 if (error) 661 goto fail; 662 bzero(sc->fxp_desc.cbl_list, FXP_TXCB_SZ); 663 664 error = bus_dmamap_load(sc->cbl_tag, sc->cbl_map, 665 sc->fxp_desc.cbl_list, FXP_TXCB_SZ, fxp_dma_map_addr, 666 &sc->fxp_desc.cbl_addr, 0); 667 if (error) { 668 device_printf(dev, "could not map DMA memory\n"); 669 goto fail; 670 } 671 672 error = bus_dma_tag_create(NULL, 4, 0, BUS_SPACE_MAXADDR_32BIT, 673 BUS_SPACE_MAXADDR, NULL, NULL, sizeof(struct fxp_cb_mcs), 1, 674 sizeof(struct fxp_cb_mcs), 0, &sc->mcs_tag); 675 if (error) { 676 device_printf(dev, "could not allocate dma tag\n"); 677 goto fail; 678 } 679 680 error = bus_dmamem_alloc(sc->mcs_tag, (void **)&sc->mcsp, 681 BUS_DMA_NOWAIT, &sc->mcs_map); 682 if (error) 683 goto fail; 684 error = bus_dmamap_load(sc->mcs_tag, sc->mcs_map, sc->mcsp, 685 sizeof(struct fxp_cb_mcs), fxp_dma_map_addr, &sc->mcs_addr, 0); 686 if (error) { 687 device_printf(dev, "can't map the multicast setup command\n"); 688 goto fail; 689 } 690 691 /* 692 * Pre-allocate the TX DMA maps. 693 */ 694 for (i = 0; i < FXP_NTXCB; i++) { 695 error = bus_dmamap_create(sc->fxp_mtag, 0, 696 &sc->fxp_desc.tx_list[i].tx_map); 697 if (error) { 698 device_printf(dev, "can't create DMA map for TX\n"); 699 goto fail; 700 } 701 } 702 error = bus_dmamap_create(sc->fxp_mtag, 0, &sc->spare_map); 703 if (error) { 704 device_printf(dev, "can't create spare DMA map\n"); 705 goto fail; 706 } 707 708 /* 709 * Pre-allocate our receive buffers. 710 */ 711 sc->fxp_desc.rx_head = sc->fxp_desc.rx_tail = NULL; 712 for (i = 0; i < FXP_NRFABUFS; i++) { 713 rxp = &sc->fxp_desc.rx_list[i]; 714 error = bus_dmamap_create(sc->fxp_mtag, 0, &rxp->rx_map); 715 if (error) { 716 device_printf(dev, "can't create DMA map for RX\n"); 717 goto fail; 718 } 719 if (fxp_add_rfabuf(sc, rxp) != 0) { 720 error = ENOMEM; 721 goto fail; 722 } 723 } 724 725 /* 726 * Read MAC address. 727 */ 728 fxp_read_eeprom(sc, myea, 0, 3); 729 sc->arpcom.ac_enaddr[0] = myea[0] & 0xff; 730 sc->arpcom.ac_enaddr[1] = myea[0] >> 8; 731 sc->arpcom.ac_enaddr[2] = myea[1] & 0xff; 732 sc->arpcom.ac_enaddr[3] = myea[1] >> 8; 733 sc->arpcom.ac_enaddr[4] = myea[2] & 0xff; 734 sc->arpcom.ac_enaddr[5] = myea[2] >> 8; 735 device_printf(dev, "Ethernet address %6D%s\n", 736 sc->arpcom.ac_enaddr, ":", 737 sc->flags & FXP_FLAG_SERIAL_MEDIA ? ", 10Mbps" : ""); 738 if (bootverbose) { 739 device_printf(dev, "PCI IDs: %04x %04x %04x %04x %04x\n", 740 pci_get_vendor(dev), pci_get_device(dev), 741 pci_get_subvendor(dev), pci_get_subdevice(dev), 742 pci_get_revid(dev)); 743 fxp_read_eeprom(sc, &data, 10, 1); 744 device_printf(dev, "Dynamic Standby mode is %s\n", 745 data & 0x02 ? "enabled" : "disabled"); 746 } 747 748 /* 749 * If this is only a 10Mbps device, then there is no MII, and 750 * the PHY will use a serial interface instead. 751 * 752 * The Seeq 80c24 AutoDUPLEX(tm) Ethernet Interface Adapter 753 * doesn't have a programming interface of any sort. The 754 * media is sensed automatically based on how the link partner 755 * is configured. This is, in essence, manual configuration. 756 */ 757 if (sc->flags & FXP_FLAG_SERIAL_MEDIA) { 758 ifmedia_add(&sc->sc_media, IFM_ETHER|IFM_MANUAL, 0, NULL); 759 ifmedia_set(&sc->sc_media, IFM_ETHER|IFM_MANUAL); 760 } else { 761 if (mii_phy_probe(dev, &sc->miibus, fxp_ifmedia_upd, 762 fxp_ifmedia_sts)) { 763 device_printf(dev, "MII without any PHY!\n"); 764 error = ENXIO; 765 goto fail; 766 } 767 } 768 769 ifp = &sc->arpcom.ac_if; 770 ifp->if_unit = device_get_unit(dev); 771 ifp->if_name = "fxp"; 772 ifp->if_output = ether_output; 773 ifp->if_baudrate = 100000000; 774 ifp->if_init = fxp_init; 775 ifp->if_softc = sc; 776 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 777 ifp->if_ioctl = fxp_ioctl; 778 ifp->if_start = fxp_start; 779 ifp->if_watchdog = fxp_watchdog; 780 781 /* Enable checksum offload for 82550 or better chips */ 782 if (sc->flags & FXP_FLAG_EXT_RFA) { 783 ifp->if_hwassist = FXP_CSUM_FEATURES; 784 ifp->if_capabilities = IFCAP_HWCSUM; 785 ifp->if_capenable = ifp->if_capabilities; 786 } 787 788 /* 789 * Attach the interface. 790 */ 791 ether_ifattach(ifp, sc->arpcom.ac_enaddr); 792 793 /* 794 * Tell the upper layer(s) we support long frames. 795 */ 796 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 797 ifp->if_capabilities |= IFCAP_VLAN_MTU; 798 799 /* 800 * Let the system queue as many packets as we have available 801 * TX descriptors. 802 */ 803 ifp->if_snd.ifq_maxlen = FXP_NTXCB - 1; 804 805 /* 806 * Hook our interrupt after all initialization is complete. 807 * XXX This driver has been tested with the INTR_MPSAFFE flag set 808 * however, ifp and its functions are not fully locked so MPSAFE 809 * should not be used unless you can handle potential data loss. 810 */ 811 error = bus_setup_intr(dev, sc->irq, INTR_TYPE_NET /*|INTR_MPSAFE*/, 812 fxp_intr, sc, &sc->ih); 813 if (error) { 814 device_printf(dev, "could not setup irq\n"); 815 ether_ifdetach(&sc->arpcom.ac_if); 816 goto fail; 817 } 818 819 fail: 820 splx(s); 821 if (error) 822 fxp_release(sc); 823 return (error); 824 } 825 826 /* 827 * Release all resources. The softc lock should not be held and the 828 * interrupt should already be torn down. 829 */ 830 static void 831 fxp_release(struct fxp_softc *sc) 832 { 833 struct fxp_rx *rxp; 834 struct fxp_tx *txp; 835 int i; 836 837 mtx_assert(&sc->sc_mtx, MA_NOTOWNED); 838 if (sc->ih) 839 panic("fxp_release() called with intr handle still active"); 840 if (sc->miibus) 841 device_delete_child(sc->dev, sc->miibus); 842 bus_generic_detach(sc->dev); 843 ifmedia_removeall(&sc->sc_media); 844 if (sc->fxp_desc.cbl_list) { 845 bus_dmamap_unload(sc->cbl_tag, sc->cbl_map); 846 bus_dmamem_free(sc->cbl_tag, sc->fxp_desc.cbl_list, 847 sc->cbl_map); 848 } 849 if (sc->fxp_stats) { 850 bus_dmamap_unload(sc->fxp_stag, sc->fxp_smap); 851 bus_dmamem_free(sc->fxp_stag, sc->fxp_stats, sc->fxp_smap); 852 } 853 if (sc->mcsp) { 854 bus_dmamap_unload(sc->mcs_tag, sc->mcs_map); 855 bus_dmamem_free(sc->mcs_tag, sc->mcsp, sc->mcs_map); 856 } 857 if (sc->irq) 858 bus_release_resource(sc->dev, SYS_RES_IRQ, 0, sc->irq); 859 if (sc->mem) 860 bus_release_resource(sc->dev, sc->rtp, sc->rgd, sc->mem); 861 if (sc->fxp_mtag) { 862 for (i = 0; i < FXP_NRFABUFS; i++) { 863 rxp = &sc->fxp_desc.rx_list[i]; 864 if (rxp->rx_mbuf != NULL) { 865 bus_dmamap_sync(sc->fxp_mtag, rxp->rx_map, 866 BUS_DMASYNC_POSTREAD); 867 bus_dmamap_unload(sc->fxp_mtag, rxp->rx_map); 868 m_freem(rxp->rx_mbuf); 869 } 870 bus_dmamap_destroy(sc->fxp_mtag, rxp->rx_map); 871 } 872 bus_dmamap_destroy(sc->fxp_mtag, sc->spare_map); 873 bus_dma_tag_destroy(sc->fxp_mtag); 874 } 875 if (sc->fxp_stag) { 876 for (i = 0; i < FXP_NTXCB; i++) { 877 txp = &sc->fxp_desc.tx_list[i]; 878 if (txp->tx_mbuf != NULL) { 879 bus_dmamap_sync(sc->fxp_mtag, txp->tx_map, 880 BUS_DMASYNC_POSTWRITE); 881 bus_dmamap_unload(sc->fxp_mtag, txp->tx_map); 882 m_freem(txp->tx_mbuf); 883 } 884 bus_dmamap_destroy(sc->fxp_mtag, txp->tx_map); 885 } 886 bus_dma_tag_destroy(sc->fxp_stag); 887 } 888 if (sc->cbl_tag) 889 bus_dma_tag_destroy(sc->cbl_tag); 890 if (sc->mcs_tag) 891 bus_dma_tag_destroy(sc->mcs_tag); 892 893 sysctl_ctx_free(&sc->sysctl_ctx); 894 895 mtx_destroy(&sc->sc_mtx); 896 } 897 898 /* 899 * Detach interface. 900 */ 901 static int 902 fxp_detach(device_t dev) 903 { 904 struct fxp_softc *sc = device_get_softc(dev); 905 int s; 906 907 FXP_LOCK(sc); 908 s = splimp(); 909 910 sc->suspended = 1; /* Do same thing as we do for suspend */ 911 /* 912 * Close down routes etc. 913 */ 914 ether_ifdetach(&sc->arpcom.ac_if); 915 916 /* 917 * Stop DMA and drop transmit queue, but disable interrupts first. 918 */ 919 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE); 920 fxp_stop(sc); 921 FXP_UNLOCK(sc); 922 923 /* 924 * Unhook interrupt before dropping lock. This is to prevent 925 * races with fxp_intr(). 926 */ 927 bus_teardown_intr(sc->dev, sc->irq, sc->ih); 928 sc->ih = NULL; 929 930 splx(s); 931 932 /* Release our allocated resources. */ 933 fxp_release(sc); 934 return (0); 935 } 936 937 /* 938 * Device shutdown routine. Called at system shutdown after sync. The 939 * main purpose of this routine is to shut off receiver DMA so that 940 * kernel memory doesn't get clobbered during warmboot. 941 */ 942 static int 943 fxp_shutdown(device_t dev) 944 { 945 /* 946 * Make sure that DMA is disabled prior to reboot. Not doing 947 * do could allow DMA to corrupt kernel memory during the 948 * reboot before the driver initializes. 949 */ 950 fxp_stop((struct fxp_softc *) device_get_softc(dev)); 951 return (0); 952 } 953 954 /* 955 * Device suspend routine. Stop the interface and save some PCI 956 * settings in case the BIOS doesn't restore them properly on 957 * resume. 958 */ 959 static int 960 fxp_suspend(device_t dev) 961 { 962 struct fxp_softc *sc = device_get_softc(dev); 963 int i, s; 964 965 FXP_LOCK(sc); 966 s = splimp(); 967 968 fxp_stop(sc); 969 970 for (i = 0; i < 5; i++) 971 sc->saved_maps[i] = pci_read_config(dev, PCIR_MAPS + i * 4, 4); 972 sc->saved_biosaddr = pci_read_config(dev, PCIR_BIOS, 4); 973 sc->saved_intline = pci_read_config(dev, PCIR_INTLINE, 1); 974 sc->saved_cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1); 975 sc->saved_lattimer = pci_read_config(dev, PCIR_LATTIMER, 1); 976 977 sc->suspended = 1; 978 979 FXP_UNLOCK(sc); 980 splx(s); 981 return (0); 982 } 983 984 /* 985 * Device resume routine. Restore some PCI settings in case the BIOS 986 * doesn't, re-enable busmastering, and restart the interface if 987 * appropriate. 988 */ 989 static int 990 fxp_resume(device_t dev) 991 { 992 struct fxp_softc *sc = device_get_softc(dev); 993 struct ifnet *ifp = &sc->sc_if; 994 u_int16_t pci_command; 995 int i, s; 996 997 FXP_LOCK(sc); 998 s = splimp(); 999 1000 fxp_powerstate_d0(dev); 1001 1002 /* better way to do this? */ 1003 for (i = 0; i < 5; i++) 1004 pci_write_config(dev, PCIR_MAPS + i * 4, sc->saved_maps[i], 4); 1005 pci_write_config(dev, PCIR_BIOS, sc->saved_biosaddr, 4); 1006 pci_write_config(dev, PCIR_INTLINE, sc->saved_intline, 1); 1007 pci_write_config(dev, PCIR_CACHELNSZ, sc->saved_cachelnsz, 1); 1008 pci_write_config(dev, PCIR_LATTIMER, sc->saved_lattimer, 1); 1009 1010 /* reenable busmastering */ 1011 pci_command = pci_read_config(dev, PCIR_COMMAND, 2); 1012 pci_command |= (PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN); 1013 pci_write_config(dev, PCIR_COMMAND, pci_command, 2); 1014 1015 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET); 1016 DELAY(10); 1017 1018 /* reinitialize interface if necessary */ 1019 if (ifp->if_flags & IFF_UP) 1020 fxp_init_body(sc); 1021 1022 sc->suspended = 0; 1023 1024 FXP_UNLOCK(sc); 1025 splx(s); 1026 return (0); 1027 } 1028 1029 static void 1030 fxp_eeprom_shiftin(struct fxp_softc *sc, int data, int length) 1031 { 1032 u_int16_t reg; 1033 int x; 1034 1035 /* 1036 * Shift in data. 1037 */ 1038 for (x = 1 << (length - 1); x; x >>= 1) { 1039 if (data & x) 1040 reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI; 1041 else 1042 reg = FXP_EEPROM_EECS; 1043 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 1044 DELAY(1); 1045 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK); 1046 DELAY(1); 1047 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 1048 DELAY(1); 1049 } 1050 } 1051 1052 /* 1053 * Read from the serial EEPROM. Basically, you manually shift in 1054 * the read opcode (one bit at a time) and then shift in the address, 1055 * and then you shift out the data (all of this one bit at a time). 1056 * The word size is 16 bits, so you have to provide the address for 1057 * every 16 bits of data. 1058 */ 1059 static u_int16_t 1060 fxp_eeprom_getword(struct fxp_softc *sc, int offset, int autosize) 1061 { 1062 u_int16_t reg, data; 1063 int x; 1064 1065 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 1066 /* 1067 * Shift in read opcode. 1068 */ 1069 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_READ, 3); 1070 /* 1071 * Shift in address. 1072 */ 1073 data = 0; 1074 for (x = 1 << (sc->eeprom_size - 1); x; x >>= 1) { 1075 if (offset & x) 1076 reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI; 1077 else 1078 reg = FXP_EEPROM_EECS; 1079 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 1080 DELAY(1); 1081 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK); 1082 DELAY(1); 1083 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 1084 DELAY(1); 1085 reg = CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO; 1086 data++; 1087 if (autosize && reg == 0) { 1088 sc->eeprom_size = data; 1089 break; 1090 } 1091 } 1092 /* 1093 * Shift out data. 1094 */ 1095 data = 0; 1096 reg = FXP_EEPROM_EECS; 1097 for (x = 1 << 15; x; x >>= 1) { 1098 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK); 1099 DELAY(1); 1100 if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO) 1101 data |= x; 1102 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 1103 DELAY(1); 1104 } 1105 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 1106 DELAY(1); 1107 1108 return (data); 1109 } 1110 1111 static void 1112 fxp_eeprom_putword(struct fxp_softc *sc, int offset, u_int16_t data) 1113 { 1114 int i; 1115 1116 /* 1117 * Erase/write enable. 1118 */ 1119 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 1120 fxp_eeprom_shiftin(sc, 0x4, 3); 1121 fxp_eeprom_shiftin(sc, 0x03 << (sc->eeprom_size - 2), sc->eeprom_size); 1122 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 1123 DELAY(1); 1124 /* 1125 * Shift in write opcode, address, data. 1126 */ 1127 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 1128 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_WRITE, 3); 1129 fxp_eeprom_shiftin(sc, offset, sc->eeprom_size); 1130 fxp_eeprom_shiftin(sc, data, 16); 1131 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 1132 DELAY(1); 1133 /* 1134 * Wait for EEPROM to finish up. 1135 */ 1136 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 1137 DELAY(1); 1138 for (i = 0; i < 1000; i++) { 1139 if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO) 1140 break; 1141 DELAY(50); 1142 } 1143 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 1144 DELAY(1); 1145 /* 1146 * Erase/write disable. 1147 */ 1148 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 1149 fxp_eeprom_shiftin(sc, 0x4, 3); 1150 fxp_eeprom_shiftin(sc, 0, sc->eeprom_size); 1151 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 1152 DELAY(1); 1153 } 1154 1155 /* 1156 * From NetBSD: 1157 * 1158 * Figure out EEPROM size. 1159 * 1160 * 559's can have either 64-word or 256-word EEPROMs, the 558 1161 * datasheet only talks about 64-word EEPROMs, and the 557 datasheet 1162 * talks about the existance of 16 to 256 word EEPROMs. 1163 * 1164 * The only known sizes are 64 and 256, where the 256 version is used 1165 * by CardBus cards to store CIS information. 1166 * 1167 * The address is shifted in msb-to-lsb, and after the last 1168 * address-bit the EEPROM is supposed to output a `dummy zero' bit, 1169 * after which follows the actual data. We try to detect this zero, by 1170 * probing the data-out bit in the EEPROM control register just after 1171 * having shifted in a bit. If the bit is zero, we assume we've 1172 * shifted enough address bits. The data-out should be tri-state, 1173 * before this, which should translate to a logical one. 1174 */ 1175 static void 1176 fxp_autosize_eeprom(struct fxp_softc *sc) 1177 { 1178 1179 /* guess maximum size of 256 words */ 1180 sc->eeprom_size = 8; 1181 1182 /* autosize */ 1183 (void) fxp_eeprom_getword(sc, 0, 1); 1184 } 1185 1186 static void 1187 fxp_read_eeprom(struct fxp_softc *sc, u_short *data, int offset, int words) 1188 { 1189 int i; 1190 1191 for (i = 0; i < words; i++) 1192 data[i] = fxp_eeprom_getword(sc, offset + i, 0); 1193 } 1194 1195 static void 1196 fxp_write_eeprom(struct fxp_softc *sc, u_short *data, int offset, int words) 1197 { 1198 int i; 1199 1200 for (i = 0; i < words; i++) 1201 fxp_eeprom_putword(sc, offset + i, data[i]); 1202 } 1203 1204 static void 1205 fxp_dma_map_txbuf(void *arg, bus_dma_segment_t *segs, int nseg, 1206 bus_size_t mapsize, int error) 1207 { 1208 struct fxp_softc *sc; 1209 struct fxp_cb_tx *txp; 1210 int i; 1211 1212 if (error) 1213 return; 1214 1215 KASSERT(nseg <= FXP_NTXSEG, ("too many DMA segments")); 1216 1217 sc = arg; 1218 txp = sc->fxp_desc.tx_last->tx_next->tx_cb; 1219 for (i = 0; i < nseg; i++) { 1220 KASSERT(segs[i].ds_len <= MCLBYTES, ("segment size too large")); 1221 /* 1222 * If this is an 82550/82551, then we're using extended 1223 * TxCBs _and_ we're using checksum offload. This means 1224 * that the TxCB is really an IPCB. One major difference 1225 * between the two is that with plain extended TxCBs, 1226 * the bottom half of the TxCB contains two entries from 1227 * the TBD array, whereas IPCBs contain just one entry: 1228 * one entry (8 bytes) has been sacrificed for the TCP/IP 1229 * checksum offload control bits. So to make things work 1230 * right, we have to start filling in the TBD array 1231 * starting from a different place depending on whether 1232 * the chip is an 82550/82551 or not. 1233 */ 1234 if (sc->flags & FXP_FLAG_EXT_RFA) { 1235 txp->tbd[i + 1].tb_addr = htole32(segs[i].ds_addr); 1236 txp->tbd[i + 1].tb_size = htole32(segs[i].ds_len); 1237 } else { 1238 txp->tbd[i].tb_addr = htole32(segs[i].ds_addr); 1239 txp->tbd[i].tb_size = htole32(segs[i].ds_len); 1240 } 1241 } 1242 txp->tbd_number = nseg; 1243 } 1244 1245 /* 1246 * Grab the softc lock and call the real fxp_start_body() routine 1247 */ 1248 static void 1249 fxp_start(struct ifnet *ifp) 1250 { 1251 struct fxp_softc *sc = ifp->if_softc; 1252 1253 FXP_LOCK(sc); 1254 fxp_start_body(ifp); 1255 FXP_UNLOCK(sc); 1256 } 1257 1258 /* 1259 * Start packet transmission on the interface. 1260 * This routine must be called with the softc lock held, and is an 1261 * internal entry point only. 1262 */ 1263 static void 1264 fxp_start_body(struct ifnet *ifp) 1265 { 1266 struct fxp_softc *sc = ifp->if_softc; 1267 struct fxp_tx *txp; 1268 struct mbuf *mb_head; 1269 int error; 1270 1271 mtx_assert(&sc->sc_mtx, MA_OWNED); 1272 /* 1273 * See if we need to suspend xmit until the multicast filter 1274 * has been reprogrammed (which can only be done at the head 1275 * of the command chain). 1276 */ 1277 if (sc->need_mcsetup) { 1278 return; 1279 } 1280 1281 txp = NULL; 1282 1283 /* 1284 * We're finished if there is nothing more to add to the list or if 1285 * we're all filled up with buffers to transmit. 1286 * NOTE: One TxCB is reserved to guarantee that fxp_mc_setup() can add 1287 * a NOP command when needed. 1288 */ 1289 while (ifp->if_snd.ifq_head != NULL && sc->tx_queued < FXP_NTXCB - 1) { 1290 1291 /* 1292 * Grab a packet to transmit. 1293 */ 1294 IF_DEQUEUE(&ifp->if_snd, mb_head); 1295 1296 /* 1297 * Get pointer to next available tx desc. 1298 */ 1299 txp = sc->fxp_desc.tx_last->tx_next; 1300 1301 /* 1302 * A note in Appendix B of the Intel 8255x 10/100 Mbps 1303 * Ethernet Controller Family Open Source Software 1304 * Developer Manual says: 1305 * Using software parsing is only allowed with legal 1306 * TCP/IP or UDP/IP packets. 1307 * ... 1308 * For all other datagrams, hardware parsing must 1309 * be used. 1310 * Software parsing appears to truncate ICMP and 1311 * fragmented UDP packets that contain one to three 1312 * bytes in the second (and final) mbuf of the packet. 1313 */ 1314 if (sc->flags & FXP_FLAG_EXT_RFA) 1315 txp->tx_cb->ipcb_ip_activation_high = 1316 FXP_IPCB_HARDWAREPARSING_ENABLE; 1317 1318 /* 1319 * Deal with TCP/IP checksum offload. Note that 1320 * in order for TCP checksum offload to work, 1321 * the pseudo header checksum must have already 1322 * been computed and stored in the checksum field 1323 * in the TCP header. The stack should have 1324 * already done this for us. 1325 */ 1326 1327 if (mb_head->m_pkthdr.csum_flags) { 1328 if (mb_head->m_pkthdr.csum_flags & CSUM_DELAY_DATA) { 1329 txp->tx_cb->ipcb_ip_schedule = 1330 FXP_IPCB_TCPUDP_CHECKSUM_ENABLE; 1331 if (mb_head->m_pkthdr.csum_flags & CSUM_TCP) 1332 txp->tx_cb->ipcb_ip_schedule |= 1333 FXP_IPCB_TCP_PACKET; 1334 } 1335 #ifdef FXP_IP_CSUM_WAR 1336 /* 1337 * XXX The 82550 chip appears to have trouble 1338 * dealing with IP header checksums in very small 1339 * datagrams, namely fragments from 1 to 3 bytes 1340 * in size. For example, say you want to transmit 1341 * a UDP packet of 1473 bytes. The packet will be 1342 * fragmented over two IP datagrams, the latter 1343 * containing only one byte of data. The 82550 will 1344 * botch the header checksum on the 1-byte fragment. 1345 * As long as the datagram contains 4 or more bytes 1346 * of data, you're ok. 1347 * 1348 * The following code attempts to work around this 1349 * problem: if the datagram is less than 38 bytes 1350 * in size (14 bytes ether header, 20 bytes IP header, 1351 * plus 4 bytes of data), we punt and compute the IP 1352 * header checksum by hand. This workaround doesn't 1353 * work very well, however, since it can be fooled 1354 * by things like VLAN tags and IP options that make 1355 * the header sizes/offsets vary. 1356 */ 1357 1358 if (mb_head->m_pkthdr.csum_flags & CSUM_IP) { 1359 if (mb_head->m_pkthdr.len < 38) { 1360 struct ip *ip; 1361 mb_head->m_data += ETHER_HDR_LEN; 1362 ip = mtod(mb_head, struct ip *); 1363 ip->ip_sum = in_cksum(mb_head, 1364 ip->ip_hl << 2); 1365 mb_head->m_data -= ETHER_HDR_LEN; 1366 } else { 1367 txp->tx_cb->ipcb_ip_activation_high = 1368 FXP_IPCB_HARDWAREPARSING_ENABLE; 1369 txp->tx_cb->ipcb_ip_schedule |= 1370 FXP_IPCB_IP_CHECKSUM_ENABLE; 1371 } 1372 } 1373 #endif 1374 } 1375 1376 /* 1377 * Go through each of the mbufs in the chain and initialize 1378 * the transmit buffer descriptors with the physical address 1379 * and size of the mbuf. 1380 */ 1381 error = bus_dmamap_load_mbuf(sc->fxp_mtag, txp->tx_map, 1382 mb_head, fxp_dma_map_txbuf, sc, 0); 1383 1384 if (error && error != EFBIG) { 1385 device_printf(sc->dev, "can't map mbuf (error %d)\n", 1386 error); 1387 m_freem(mb_head); 1388 break; 1389 } 1390 1391 if (error) { 1392 struct mbuf *mn; 1393 1394 /* 1395 * We ran out of segments. We have to recopy this 1396 * mbuf chain first. Bail out if we can't get the 1397 * new buffers. 1398 */ 1399 mn = m_defrag(mb_head, M_DONTWAIT); 1400 if (mn == NULL) { 1401 m_freem(mb_head); 1402 break; 1403 } else { 1404 mb_head = mn; 1405 } 1406 error = bus_dmamap_load_mbuf(sc->fxp_mtag, txp->tx_map, 1407 mb_head, fxp_dma_map_txbuf, sc, 0); 1408 if (error) { 1409 device_printf(sc->dev, 1410 "can't map mbuf (error %d)\n", error); 1411 m_freem(mb_head); 1412 break; 1413 } 1414 } 1415 1416 bus_dmamap_sync(sc->fxp_mtag, txp->tx_map, 1417 BUS_DMASYNC_PREWRITE); 1418 1419 txp->tx_mbuf = mb_head; 1420 txp->tx_cb->cb_status = 0; 1421 txp->tx_cb->byte_count = 0; 1422 if (sc->tx_queued != FXP_CXINT_THRESH - 1) { 1423 txp->tx_cb->cb_command = 1424 htole16(sc->tx_cmd | FXP_CB_COMMAND_SF | 1425 FXP_CB_COMMAND_S); 1426 } else { 1427 txp->tx_cb->cb_command = 1428 htole16(sc->tx_cmd | FXP_CB_COMMAND_SF | 1429 FXP_CB_COMMAND_S | FXP_CB_COMMAND_I); 1430 /* 1431 * Set a 5 second timer just in case we don't hear 1432 * from the card again. 1433 */ 1434 ifp->if_timer = 5; 1435 } 1436 txp->tx_cb->tx_threshold = tx_threshold; 1437 1438 /* 1439 * Advance the end of list forward. 1440 */ 1441 1442 #ifdef __alpha__ 1443 /* 1444 * On platforms which can't access memory in 16-bit 1445 * granularities, we must prevent the card from DMA'ing 1446 * up the status while we update the command field. 1447 * This could cause us to overwrite the completion status. 1448 * XXX This is probably bogus and we're _not_ looking 1449 * for atomicity here. 1450 */ 1451 atomic_clear_16(&sc->fxp_desc.tx_last->tx_cb->cb_command, 1452 htole16(FXP_CB_COMMAND_S)); 1453 #else 1454 sc->fxp_desc.tx_last->tx_cb->cb_command &= 1455 htole16(~FXP_CB_COMMAND_S); 1456 #endif /*__alpha__*/ 1457 sc->fxp_desc.tx_last = txp; 1458 1459 /* 1460 * Advance the beginning of the list forward if there are 1461 * no other packets queued (when nothing is queued, tx_first 1462 * sits on the last TxCB that was sent out). 1463 */ 1464 if (sc->tx_queued == 0) 1465 sc->fxp_desc.tx_first = txp; 1466 1467 sc->tx_queued++; 1468 1469 /* 1470 * Pass packet to bpf if there is a listener. 1471 */ 1472 BPF_MTAP(ifp, mb_head); 1473 } 1474 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE); 1475 1476 /* 1477 * We're finished. If we added to the list, issue a RESUME to get DMA 1478 * going again if suspended. 1479 */ 1480 if (txp != NULL) { 1481 fxp_scb_wait(sc); 1482 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_RESUME); 1483 } 1484 } 1485 1486 #ifdef DEVICE_POLLING 1487 static poll_handler_t fxp_poll; 1488 1489 static void 1490 fxp_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 1491 { 1492 struct fxp_softc *sc = ifp->if_softc; 1493 u_int8_t statack; 1494 1495 FXP_LOCK(sc); 1496 if (cmd == POLL_DEREGISTER) { /* final call, enable interrupts */ 1497 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, 0); 1498 FXP_UNLOCK(sc); 1499 return; 1500 } 1501 statack = FXP_SCB_STATACK_CXTNO | FXP_SCB_STATACK_CNA | 1502 FXP_SCB_STATACK_FR; 1503 if (cmd == POLL_AND_CHECK_STATUS) { 1504 u_int8_t tmp; 1505 1506 tmp = CSR_READ_1(sc, FXP_CSR_SCB_STATACK); 1507 if (tmp == 0xff || tmp == 0) { 1508 FXP_UNLOCK(sc); 1509 return; /* nothing to do */ 1510 } 1511 tmp &= ~statack; 1512 /* ack what we can */ 1513 if (tmp != 0) 1514 CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, tmp); 1515 statack |= tmp; 1516 } 1517 fxp_intr_body(sc, ifp, statack, count); 1518 FXP_UNLOCK(sc); 1519 } 1520 #endif /* DEVICE_POLLING */ 1521 1522 /* 1523 * Process interface interrupts. 1524 */ 1525 static void 1526 fxp_intr(void *xsc) 1527 { 1528 struct fxp_softc *sc = xsc; 1529 struct ifnet *ifp = &sc->sc_if; 1530 u_int8_t statack; 1531 1532 FXP_LOCK(sc); 1533 if (sc->suspended) { 1534 FXP_UNLOCK(sc); 1535 return; 1536 } 1537 1538 #ifdef DEVICE_POLLING 1539 if (ifp->if_flags & IFF_POLLING) { 1540 FXP_UNLOCK(sc); 1541 return; 1542 } 1543 if (ether_poll_register(fxp_poll, ifp)) { 1544 /* disable interrupts */ 1545 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE); 1546 fxp_poll(ifp, 0, 1); 1547 FXP_UNLOCK(sc); 1548 return; 1549 } 1550 #endif 1551 while ((statack = CSR_READ_1(sc, FXP_CSR_SCB_STATACK)) != 0) { 1552 /* 1553 * It should not be possible to have all bits set; the 1554 * FXP_SCB_INTR_SWI bit always returns 0 on a read. If 1555 * all bits are set, this may indicate that the card has 1556 * been physically ejected, so ignore it. 1557 */ 1558 if (statack == 0xff) { 1559 FXP_UNLOCK(sc); 1560 return; 1561 } 1562 1563 /* 1564 * First ACK all the interrupts in this pass. 1565 */ 1566 CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, statack); 1567 fxp_intr_body(sc, ifp, statack, -1); 1568 } 1569 FXP_UNLOCK(sc); 1570 } 1571 1572 static void 1573 fxp_txeof(struct fxp_softc *sc) 1574 { 1575 struct fxp_tx *txp; 1576 1577 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREREAD); 1578 for (txp = sc->fxp_desc.tx_first; sc->tx_queued && 1579 (le16toh(txp->tx_cb->cb_status) & FXP_CB_STATUS_C) != 0; 1580 txp = txp->tx_next) { 1581 if (txp->tx_mbuf != NULL) { 1582 bus_dmamap_sync(sc->fxp_mtag, txp->tx_map, 1583 BUS_DMASYNC_POSTWRITE); 1584 bus_dmamap_unload(sc->fxp_mtag, txp->tx_map); 1585 m_freem(txp->tx_mbuf); 1586 txp->tx_mbuf = NULL; 1587 /* clear this to reset csum offload bits */ 1588 txp->tx_cb->tbd[0].tb_addr = 0; 1589 } 1590 sc->tx_queued--; 1591 } 1592 sc->fxp_desc.tx_first = txp; 1593 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE); 1594 } 1595 1596 static void 1597 fxp_intr_body(struct fxp_softc *sc, struct ifnet *ifp, u_int8_t statack, 1598 int count) 1599 { 1600 struct mbuf *m; 1601 struct fxp_rx *rxp; 1602 struct fxp_rfa *rfa; 1603 int rnr = (statack & FXP_SCB_STATACK_RNR) ? 1 : 0; 1604 1605 mtx_assert(&sc->sc_mtx, MA_OWNED); 1606 if (rnr) 1607 fxp_rnr++; 1608 #ifdef DEVICE_POLLING 1609 /* Pick up a deferred RNR condition if `count' ran out last time. */ 1610 if (sc->flags & FXP_FLAG_DEFERRED_RNR) { 1611 sc->flags &= ~FXP_FLAG_DEFERRED_RNR; 1612 rnr = 1; 1613 } 1614 #endif 1615 1616 /* 1617 * Free any finished transmit mbuf chains. 1618 * 1619 * Handle the CNA event likt a CXTNO event. It used to 1620 * be that this event (control unit not ready) was not 1621 * encountered, but it is now with the SMPng modifications. 1622 * The exact sequence of events that occur when the interface 1623 * is brought up are different now, and if this event 1624 * goes unhandled, the configuration/rxfilter setup sequence 1625 * can stall for several seconds. The result is that no 1626 * packets go out onto the wire for about 5 to 10 seconds 1627 * after the interface is ifconfig'ed for the first time. 1628 */ 1629 if (statack & (FXP_SCB_STATACK_CXTNO | FXP_SCB_STATACK_CNA)) { 1630 fxp_txeof(sc); 1631 1632 ifp->if_timer = 0; 1633 if (sc->tx_queued == 0) { 1634 if (sc->need_mcsetup) 1635 fxp_mc_setup(sc); 1636 } 1637 /* 1638 * Try to start more packets transmitting. 1639 */ 1640 if (ifp->if_snd.ifq_head != NULL) 1641 fxp_start_body(ifp); 1642 } 1643 1644 /* 1645 * Just return if nothing happened on the receive side. 1646 */ 1647 if (!rnr && (statack & FXP_SCB_STATACK_FR) == 0) 1648 return; 1649 1650 /* 1651 * Process receiver interrupts. If a no-resource (RNR) 1652 * condition exists, get whatever packets we can and 1653 * re-start the receiver. 1654 * 1655 * When using polling, we do not process the list to completion, 1656 * so when we get an RNR interrupt we must defer the restart 1657 * until we hit the last buffer with the C bit set. 1658 * If we run out of cycles and rfa_headm has the C bit set, 1659 * record the pending RNR in the FXP_FLAG_DEFERRED_RNR flag so 1660 * that the info will be used in the subsequent polling cycle. 1661 */ 1662 for (;;) { 1663 rxp = sc->fxp_desc.rx_head; 1664 m = rxp->rx_mbuf; 1665 rfa = (struct fxp_rfa *)(m->m_ext.ext_buf + 1666 RFA_ALIGNMENT_FUDGE); 1667 bus_dmamap_sync(sc->fxp_mtag, rxp->rx_map, 1668 BUS_DMASYNC_POSTREAD); 1669 1670 #ifdef DEVICE_POLLING /* loop at most count times if count >=0 */ 1671 if (count >= 0 && count-- == 0) { 1672 if (rnr) { 1673 /* Defer RNR processing until the next time. */ 1674 sc->flags |= FXP_FLAG_DEFERRED_RNR; 1675 rnr = 0; 1676 } 1677 break; 1678 } 1679 #endif /* DEVICE_POLLING */ 1680 1681 if ((le16toh(rfa->rfa_status) & FXP_RFA_STATUS_C) == 0) 1682 break; 1683 1684 /* 1685 * Advance head forward. 1686 */ 1687 sc->fxp_desc.rx_head = rxp->rx_next; 1688 1689 /* 1690 * Add a new buffer to the receive chain. 1691 * If this fails, the old buffer is recycled 1692 * instead. 1693 */ 1694 if (fxp_add_rfabuf(sc, rxp) == 0) { 1695 int total_len; 1696 1697 /* 1698 * Fetch packet length (the top 2 bits of 1699 * actual_size are flags set by the controller 1700 * upon completion), and drop the packet in case 1701 * of bogus length or CRC errors. 1702 */ 1703 total_len = le16toh(rfa->actual_size) & 0x3fff; 1704 if (total_len < sizeof(struct ether_header) || 1705 total_len > MCLBYTES - RFA_ALIGNMENT_FUDGE - 1706 sc->rfa_size || 1707 le16toh(rfa->rfa_status) & FXP_RFA_STATUS_CRC) { 1708 m_freem(m); 1709 continue; 1710 } 1711 1712 /* Do IP checksum checking. */ 1713 if (le16toh(rfa->rfa_status) & FXP_RFA_STATUS_PARSE) { 1714 if (rfa->rfax_csum_sts & 1715 FXP_RFDX_CS_IP_CSUM_BIT_VALID) 1716 m->m_pkthdr.csum_flags |= 1717 CSUM_IP_CHECKED; 1718 if (rfa->rfax_csum_sts & 1719 FXP_RFDX_CS_IP_CSUM_VALID) 1720 m->m_pkthdr.csum_flags |= 1721 CSUM_IP_VALID; 1722 if ((rfa->rfax_csum_sts & 1723 FXP_RFDX_CS_TCPUDP_CSUM_BIT_VALID) && 1724 (rfa->rfax_csum_sts & 1725 FXP_RFDX_CS_TCPUDP_CSUM_VALID)) { 1726 m->m_pkthdr.csum_flags |= 1727 CSUM_DATA_VALID|CSUM_PSEUDO_HDR; 1728 m->m_pkthdr.csum_data = 0xffff; 1729 } 1730 } 1731 1732 m->m_pkthdr.len = m->m_len = total_len; 1733 m->m_pkthdr.rcvif = ifp; 1734 1735 (*ifp->if_input)(ifp, m); 1736 } 1737 } 1738 if (rnr) { 1739 fxp_scb_wait(sc); 1740 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 1741 sc->fxp_desc.rx_head->rx_addr); 1742 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_START); 1743 } 1744 } 1745 1746 /* 1747 * Update packet in/out/collision statistics. The i82557 doesn't 1748 * allow you to access these counters without doing a fairly 1749 * expensive DMA to get _all_ of the statistics it maintains, so 1750 * we do this operation here only once per second. The statistics 1751 * counters in the kernel are updated from the previous dump-stats 1752 * DMA and then a new dump-stats DMA is started. The on-chip 1753 * counters are zeroed when the DMA completes. If we can't start 1754 * the DMA immediately, we don't wait - we just prepare to read 1755 * them again next time. 1756 */ 1757 static void 1758 fxp_tick(void *xsc) 1759 { 1760 struct fxp_softc *sc = xsc; 1761 struct ifnet *ifp = &sc->sc_if; 1762 struct fxp_stats *sp = sc->fxp_stats; 1763 int s; 1764 1765 FXP_LOCK(sc); 1766 s = splimp(); 1767 bus_dmamap_sync(sc->fxp_stag, sc->fxp_smap, BUS_DMASYNC_POSTREAD); 1768 ifp->if_opackets += le32toh(sp->tx_good); 1769 ifp->if_collisions += le32toh(sp->tx_total_collisions); 1770 if (sp->rx_good) { 1771 ifp->if_ipackets += le32toh(sp->rx_good); 1772 sc->rx_idle_secs = 0; 1773 } else { 1774 /* 1775 * Receiver's been idle for another second. 1776 */ 1777 sc->rx_idle_secs++; 1778 } 1779 ifp->if_ierrors += 1780 le32toh(sp->rx_crc_errors) + 1781 le32toh(sp->rx_alignment_errors) + 1782 le32toh(sp->rx_rnr_errors) + 1783 le32toh(sp->rx_overrun_errors); 1784 /* 1785 * If any transmit underruns occured, bump up the transmit 1786 * threshold by another 512 bytes (64 * 8). 1787 */ 1788 if (sp->tx_underruns) { 1789 ifp->if_oerrors += le32toh(sp->tx_underruns); 1790 if (tx_threshold < 192) 1791 tx_threshold += 64; 1792 } 1793 1794 /* 1795 * Release any xmit buffers that have completed DMA. This isn't 1796 * strictly necessary to do here, but it's advantagous for mbufs 1797 * with external storage to be released in a timely manner rather 1798 * than being defered for a potentially long time. This limits 1799 * the delay to a maximum of one second. 1800 */ 1801 fxp_txeof(sc); 1802 1803 /* 1804 * If we haven't received any packets in FXP_MAC_RX_IDLE seconds, 1805 * then assume the receiver has locked up and attempt to clear 1806 * the condition by reprogramming the multicast filter. This is 1807 * a work-around for a bug in the 82557 where the receiver locks 1808 * up if it gets certain types of garbage in the syncronization 1809 * bits prior to the packet header. This bug is supposed to only 1810 * occur in 10Mbps mode, but has been seen to occur in 100Mbps 1811 * mode as well (perhaps due to a 10/100 speed transition). 1812 */ 1813 if (sc->rx_idle_secs > FXP_MAX_RX_IDLE) { 1814 sc->rx_idle_secs = 0; 1815 fxp_mc_setup(sc); 1816 } 1817 /* 1818 * If there is no pending command, start another stats 1819 * dump. Otherwise punt for now. 1820 */ 1821 if (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) == 0) { 1822 /* 1823 * Start another stats dump. 1824 */ 1825 bus_dmamap_sync(sc->fxp_stag, sc->fxp_smap, 1826 BUS_DMASYNC_PREREAD); 1827 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_DUMPRESET); 1828 } else { 1829 /* 1830 * A previous command is still waiting to be accepted. 1831 * Just zero our copy of the stats and wait for the 1832 * next timer event to update them. 1833 */ 1834 sp->tx_good = 0; 1835 sp->tx_underruns = 0; 1836 sp->tx_total_collisions = 0; 1837 1838 sp->rx_good = 0; 1839 sp->rx_crc_errors = 0; 1840 sp->rx_alignment_errors = 0; 1841 sp->rx_rnr_errors = 0; 1842 sp->rx_overrun_errors = 0; 1843 } 1844 if (sc->miibus != NULL) 1845 mii_tick(device_get_softc(sc->miibus)); 1846 1847 /* 1848 * Schedule another timeout one second from now. 1849 */ 1850 sc->stat_ch = timeout(fxp_tick, sc, hz); 1851 FXP_UNLOCK(sc); 1852 splx(s); 1853 } 1854 1855 /* 1856 * Stop the interface. Cancels the statistics updater and resets 1857 * the interface. 1858 */ 1859 static void 1860 fxp_stop(struct fxp_softc *sc) 1861 { 1862 struct ifnet *ifp = &sc->sc_if; 1863 struct fxp_tx *txp; 1864 int i; 1865 1866 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1867 ifp->if_timer = 0; 1868 1869 #ifdef DEVICE_POLLING 1870 ether_poll_deregister(ifp); 1871 #endif 1872 /* 1873 * Cancel stats updater. 1874 */ 1875 untimeout(fxp_tick, sc, sc->stat_ch); 1876 1877 /* 1878 * Issue software reset, which also unloads the microcode. 1879 */ 1880 sc->flags &= ~FXP_FLAG_UCODE; 1881 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SOFTWARE_RESET); 1882 DELAY(50); 1883 1884 /* 1885 * Release any xmit buffers. 1886 */ 1887 txp = sc->fxp_desc.tx_list; 1888 if (txp != NULL) { 1889 for (i = 0; i < FXP_NTXCB; i++) { 1890 if (txp[i].tx_mbuf != NULL) { 1891 bus_dmamap_sync(sc->fxp_mtag, txp[i].tx_map, 1892 BUS_DMASYNC_POSTWRITE); 1893 bus_dmamap_unload(sc->fxp_mtag, txp[i].tx_map); 1894 m_freem(txp[i].tx_mbuf); 1895 txp[i].tx_mbuf = NULL; 1896 /* clear this to reset csum offload bits */ 1897 txp[i].tx_cb->tbd[0].tb_addr = 0; 1898 } 1899 } 1900 } 1901 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE); 1902 sc->tx_queued = 0; 1903 } 1904 1905 /* 1906 * Watchdog/transmission transmit timeout handler. Called when a 1907 * transmission is started on the interface, but no interrupt is 1908 * received before the timeout. This usually indicates that the 1909 * card has wedged for some reason. 1910 */ 1911 static void 1912 fxp_watchdog(struct ifnet *ifp) 1913 { 1914 struct fxp_softc *sc = ifp->if_softc; 1915 1916 FXP_LOCK(sc); 1917 device_printf(sc->dev, "device timeout\n"); 1918 ifp->if_oerrors++; 1919 1920 fxp_init_body(sc); 1921 FXP_UNLOCK(sc); 1922 } 1923 1924 /* 1925 * Acquire locks and then call the real initialization function. This 1926 * is necessary because ether_ioctl() calls if_init() and this would 1927 * result in mutex recursion if the mutex was held. 1928 */ 1929 static void 1930 fxp_init(void *xsc) 1931 { 1932 struct fxp_softc *sc = xsc; 1933 1934 FXP_LOCK(sc); 1935 fxp_init_body(sc); 1936 FXP_UNLOCK(sc); 1937 } 1938 1939 /* 1940 * Perform device initialization. This routine must be called with the 1941 * softc lock held. 1942 */ 1943 static void 1944 fxp_init_body(struct fxp_softc *sc) 1945 { 1946 struct ifnet *ifp = &sc->sc_if; 1947 struct fxp_cb_config *cbp; 1948 struct fxp_cb_ias *cb_ias; 1949 struct fxp_cb_tx *tcbp; 1950 struct fxp_tx *txp; 1951 struct fxp_cb_mcs *mcsp; 1952 int i, prm, s; 1953 1954 mtx_assert(&sc->sc_mtx, MA_OWNED); 1955 s = splimp(); 1956 /* 1957 * Cancel any pending I/O 1958 */ 1959 fxp_stop(sc); 1960 1961 prm = (ifp->if_flags & IFF_PROMISC) ? 1 : 0; 1962 1963 /* 1964 * Initialize base of CBL and RFA memory. Loading with zero 1965 * sets it up for regular linear addressing. 1966 */ 1967 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 0); 1968 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_BASE); 1969 1970 fxp_scb_wait(sc); 1971 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_BASE); 1972 1973 /* 1974 * Initialize base of dump-stats buffer. 1975 */ 1976 fxp_scb_wait(sc); 1977 bus_dmamap_sync(sc->fxp_stag, sc->fxp_smap, BUS_DMASYNC_PREREAD); 1978 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->stats_addr); 1979 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_DUMP_ADR); 1980 1981 /* 1982 * Attempt to load microcode if requested. 1983 */ 1984 if (ifp->if_flags & IFF_LINK0 && (sc->flags & FXP_FLAG_UCODE) == 0) 1985 fxp_load_ucode(sc); 1986 1987 /* 1988 * Initialize the multicast address list. 1989 */ 1990 if (fxp_mc_addrs(sc)) { 1991 mcsp = sc->mcsp; 1992 mcsp->cb_status = 0; 1993 mcsp->cb_command = 1994 htole16(FXP_CB_COMMAND_MCAS | FXP_CB_COMMAND_EL); 1995 mcsp->link_addr = 0xffffffff; 1996 /* 1997 * Start the multicast setup command. 1998 */ 1999 fxp_scb_wait(sc); 2000 bus_dmamap_sync(sc->mcs_tag, sc->mcs_map, BUS_DMASYNC_PREWRITE); 2001 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->mcs_addr); 2002 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2003 /* ...and wait for it to complete. */ 2004 fxp_dma_wait(sc, &mcsp->cb_status, sc->mcs_tag, sc->mcs_map); 2005 bus_dmamap_sync(sc->mcs_tag, sc->mcs_map, 2006 BUS_DMASYNC_POSTWRITE); 2007 } 2008 2009 /* 2010 * We temporarily use memory that contains the TxCB list to 2011 * construct the config CB. The TxCB list memory is rebuilt 2012 * later. 2013 */ 2014 cbp = (struct fxp_cb_config *)sc->fxp_desc.cbl_list; 2015 2016 /* 2017 * This bcopy is kind of disgusting, but there are a bunch of must be 2018 * zero and must be one bits in this structure and this is the easiest 2019 * way to initialize them all to proper values. 2020 */ 2021 bcopy(fxp_cb_config_template, cbp, sizeof(fxp_cb_config_template)); 2022 2023 cbp->cb_status = 0; 2024 cbp->cb_command = htole16(FXP_CB_COMMAND_CONFIG | 2025 FXP_CB_COMMAND_EL); 2026 cbp->link_addr = 0xffffffff; /* (no) next command */ 2027 cbp->byte_count = sc->flags & FXP_FLAG_EXT_RFA ? 32 : 22; 2028 cbp->rx_fifo_limit = 8; /* rx fifo threshold (32 bytes) */ 2029 cbp->tx_fifo_limit = 0; /* tx fifo threshold (0 bytes) */ 2030 cbp->adaptive_ifs = 0; /* (no) adaptive interframe spacing */ 2031 cbp->mwi_enable = sc->flags & FXP_FLAG_MWI_ENABLE ? 1 : 0; 2032 cbp->type_enable = 0; /* actually reserved */ 2033 cbp->read_align_en = sc->flags & FXP_FLAG_READ_ALIGN ? 1 : 0; 2034 cbp->end_wr_on_cl = sc->flags & FXP_FLAG_WRITE_ALIGN ? 1 : 0; 2035 cbp->rx_dma_bytecount = 0; /* (no) rx DMA max */ 2036 cbp->tx_dma_bytecount = 0; /* (no) tx DMA max */ 2037 cbp->dma_mbce = 0; /* (disable) dma max counters */ 2038 cbp->late_scb = 0; /* (don't) defer SCB update */ 2039 cbp->direct_dma_dis = 1; /* disable direct rcv dma mode */ 2040 cbp->tno_int_or_tco_en =0; /* (disable) tx not okay interrupt */ 2041 cbp->ci_int = 1; /* interrupt on CU idle */ 2042 cbp->ext_txcb_dis = sc->flags & FXP_FLAG_EXT_TXCB ? 0 : 1; 2043 cbp->ext_stats_dis = 1; /* disable extended counters */ 2044 cbp->keep_overrun_rx = 0; /* don't pass overrun frames to host */ 2045 cbp->save_bf = sc->revision == FXP_REV_82557 ? 1 : prm; 2046 cbp->disc_short_rx = !prm; /* discard short packets */ 2047 cbp->underrun_retry = 1; /* retry mode (once) on DMA underrun */ 2048 cbp->two_frames = 0; /* do not limit FIFO to 2 frames */ 2049 cbp->dyn_tbd = 0; /* (no) dynamic TBD mode */ 2050 cbp->ext_rfa = sc->flags & FXP_FLAG_EXT_RFA ? 1 : 0; 2051 cbp->mediatype = sc->flags & FXP_FLAG_SERIAL_MEDIA ? 0 : 1; 2052 cbp->csma_dis = 0; /* (don't) disable link */ 2053 cbp->tcp_udp_cksum = 0; /* (don't) enable checksum */ 2054 cbp->vlan_tco = 0; /* (don't) enable vlan wakeup */ 2055 cbp->link_wake_en = 0; /* (don't) assert PME# on link change */ 2056 cbp->arp_wake_en = 0; /* (don't) assert PME# on arp */ 2057 cbp->mc_wake_en = 0; /* (don't) enable PME# on mcmatch */ 2058 cbp->nsai = 1; /* (don't) disable source addr insert */ 2059 cbp->preamble_length = 2; /* (7 byte) preamble */ 2060 cbp->loopback = 0; /* (don't) loopback */ 2061 cbp->linear_priority = 0; /* (normal CSMA/CD operation) */ 2062 cbp->linear_pri_mode = 0; /* (wait after xmit only) */ 2063 cbp->interfrm_spacing = 6; /* (96 bits of) interframe spacing */ 2064 cbp->promiscuous = prm; /* promiscuous mode */ 2065 cbp->bcast_disable = 0; /* (don't) disable broadcasts */ 2066 cbp->wait_after_win = 0; /* (don't) enable modified backoff alg*/ 2067 cbp->ignore_ul = 0; /* consider U/L bit in IA matching */ 2068 cbp->crc16_en = 0; /* (don't) enable crc-16 algorithm */ 2069 cbp->crscdt = sc->flags & FXP_FLAG_SERIAL_MEDIA ? 1 : 0; 2070 2071 cbp->stripping = !prm; /* truncate rx packet to byte count */ 2072 cbp->padding = 1; /* (do) pad short tx packets */ 2073 cbp->rcv_crc_xfer = 0; /* (don't) xfer CRC to host */ 2074 cbp->long_rx_en = sc->flags & FXP_FLAG_LONG_PKT_EN ? 1 : 0; 2075 cbp->ia_wake_en = 0; /* (don't) wake up on address match */ 2076 cbp->magic_pkt_dis = 0; /* (don't) disable magic packet */ 2077 /* must set wake_en in PMCSR also */ 2078 cbp->force_fdx = 0; /* (don't) force full duplex */ 2079 cbp->fdx_pin_en = 1; /* (enable) FDX# pin */ 2080 cbp->multi_ia = 0; /* (don't) accept multiple IAs */ 2081 cbp->mc_all = sc->flags & FXP_FLAG_ALL_MCAST ? 1 : 0; 2082 cbp->gamla_rx = sc->flags & FXP_FLAG_EXT_RFA ? 1 : 0; 2083 2084 if (fxp_noflow || sc->revision == FXP_REV_82557) { 2085 /* 2086 * The 82557 has no hardware flow control, the values 2087 * below are the defaults for the chip. 2088 */ 2089 cbp->fc_delay_lsb = 0; 2090 cbp->fc_delay_msb = 0x40; 2091 cbp->pri_fc_thresh = 3; 2092 cbp->tx_fc_dis = 0; 2093 cbp->rx_fc_restop = 0; 2094 cbp->rx_fc_restart = 0; 2095 cbp->fc_filter = 0; 2096 cbp->pri_fc_loc = 1; 2097 } else { 2098 cbp->fc_delay_lsb = 0x1f; 2099 cbp->fc_delay_msb = 0x01; 2100 cbp->pri_fc_thresh = 3; 2101 cbp->tx_fc_dis = 0; /* enable transmit FC */ 2102 cbp->rx_fc_restop = 1; /* enable FC restop frames */ 2103 cbp->rx_fc_restart = 1; /* enable FC restart frames */ 2104 cbp->fc_filter = !prm; /* drop FC frames to host */ 2105 cbp->pri_fc_loc = 1; /* FC pri location (byte31) */ 2106 } 2107 2108 /* 2109 * Start the config command/DMA. 2110 */ 2111 fxp_scb_wait(sc); 2112 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE); 2113 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->fxp_desc.cbl_addr); 2114 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2115 /* ...and wait for it to complete. */ 2116 fxp_dma_wait(sc, &cbp->cb_status, sc->cbl_tag, sc->cbl_map); 2117 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_POSTWRITE); 2118 2119 /* 2120 * Now initialize the station address. Temporarily use the TxCB 2121 * memory area like we did above for the config CB. 2122 */ 2123 cb_ias = (struct fxp_cb_ias *)sc->fxp_desc.cbl_list; 2124 cb_ias->cb_status = 0; 2125 cb_ias->cb_command = htole16(FXP_CB_COMMAND_IAS | FXP_CB_COMMAND_EL); 2126 cb_ias->link_addr = 0xffffffff; 2127 bcopy(sc->arpcom.ac_enaddr, cb_ias->macaddr, 2128 sizeof(sc->arpcom.ac_enaddr)); 2129 2130 /* 2131 * Start the IAS (Individual Address Setup) command/DMA. 2132 */ 2133 fxp_scb_wait(sc); 2134 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE); 2135 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2136 /* ...and wait for it to complete. */ 2137 fxp_dma_wait(sc, &cb_ias->cb_status, sc->cbl_tag, sc->cbl_map); 2138 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_POSTWRITE); 2139 2140 /* 2141 * Initialize transmit control block (TxCB) list. 2142 */ 2143 txp = sc->fxp_desc.tx_list; 2144 tcbp = sc->fxp_desc.cbl_list; 2145 bzero(tcbp, FXP_TXCB_SZ); 2146 for (i = 0; i < FXP_NTXCB; i++) { 2147 txp[i].tx_cb = tcbp + i; 2148 txp[i].tx_mbuf = NULL; 2149 tcbp[i].cb_status = htole16(FXP_CB_STATUS_C | FXP_CB_STATUS_OK); 2150 tcbp[i].cb_command = htole16(FXP_CB_COMMAND_NOP); 2151 tcbp[i].link_addr = htole32(sc->fxp_desc.cbl_addr + 2152 (((i + 1) & FXP_TXCB_MASK) * sizeof(struct fxp_cb_tx))); 2153 if (sc->flags & FXP_FLAG_EXT_TXCB) 2154 tcbp[i].tbd_array_addr = 2155 htole32(FXP_TXCB_DMA_ADDR(sc, &tcbp[i].tbd[2])); 2156 else 2157 tcbp[i].tbd_array_addr = 2158 htole32(FXP_TXCB_DMA_ADDR(sc, &tcbp[i].tbd[0])); 2159 txp[i].tx_next = &txp[(i + 1) & FXP_TXCB_MASK]; 2160 } 2161 /* 2162 * Set the suspend flag on the first TxCB and start the control 2163 * unit. It will execute the NOP and then suspend. 2164 */ 2165 tcbp->cb_command = htole16(FXP_CB_COMMAND_NOP | FXP_CB_COMMAND_S); 2166 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE); 2167 sc->fxp_desc.tx_first = sc->fxp_desc.tx_last = txp; 2168 sc->tx_queued = 1; 2169 2170 fxp_scb_wait(sc); 2171 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2172 2173 /* 2174 * Initialize receiver buffer area - RFA. 2175 */ 2176 fxp_scb_wait(sc); 2177 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->fxp_desc.rx_head->rx_addr); 2178 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_START); 2179 2180 /* 2181 * Set current media. 2182 */ 2183 if (sc->miibus != NULL) 2184 mii_mediachg(device_get_softc(sc->miibus)); 2185 2186 ifp->if_flags |= IFF_RUNNING; 2187 ifp->if_flags &= ~IFF_OACTIVE; 2188 2189 /* 2190 * Enable interrupts. 2191 */ 2192 #ifdef DEVICE_POLLING 2193 /* 2194 * ... but only do that if we are not polling. And because (presumably) 2195 * the default is interrupts on, we need to disable them explicitly! 2196 */ 2197 if ( ifp->if_flags & IFF_POLLING ) 2198 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE); 2199 else 2200 #endif /* DEVICE_POLLING */ 2201 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, 0); 2202 2203 /* 2204 * Start stats updater. 2205 */ 2206 sc->stat_ch = timeout(fxp_tick, sc, hz); 2207 splx(s); 2208 } 2209 2210 static int 2211 fxp_serial_ifmedia_upd(struct ifnet *ifp) 2212 { 2213 2214 return (0); 2215 } 2216 2217 static void 2218 fxp_serial_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 2219 { 2220 2221 ifmr->ifm_active = IFM_ETHER|IFM_MANUAL; 2222 } 2223 2224 /* 2225 * Change media according to request. 2226 */ 2227 static int 2228 fxp_ifmedia_upd(struct ifnet *ifp) 2229 { 2230 struct fxp_softc *sc = ifp->if_softc; 2231 struct mii_data *mii; 2232 2233 mii = device_get_softc(sc->miibus); 2234 mii_mediachg(mii); 2235 return (0); 2236 } 2237 2238 /* 2239 * Notify the world which media we're using. 2240 */ 2241 static void 2242 fxp_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 2243 { 2244 struct fxp_softc *sc = ifp->if_softc; 2245 struct mii_data *mii; 2246 2247 mii = device_get_softc(sc->miibus); 2248 mii_pollstat(mii); 2249 ifmr->ifm_active = mii->mii_media_active; 2250 ifmr->ifm_status = mii->mii_media_status; 2251 2252 if (ifmr->ifm_status & IFM_10_T && sc->flags & FXP_FLAG_CU_RESUME_BUG) 2253 sc->cu_resume_bug = 1; 2254 else 2255 sc->cu_resume_bug = 0; 2256 } 2257 2258 /* 2259 * Add a buffer to the end of the RFA buffer list. 2260 * Return 0 if successful, 1 for failure. A failure results in 2261 * adding the 'oldm' (if non-NULL) on to the end of the list - 2262 * tossing out its old contents and recycling it. 2263 * The RFA struct is stuck at the beginning of mbuf cluster and the 2264 * data pointer is fixed up to point just past it. 2265 */ 2266 static int 2267 fxp_add_rfabuf(struct fxp_softc *sc, struct fxp_rx *rxp) 2268 { 2269 struct mbuf *m; 2270 struct fxp_rfa *rfa, *p_rfa; 2271 struct fxp_rx *p_rx; 2272 bus_dmamap_t tmp_map; 2273 int error; 2274 2275 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 2276 if (m == NULL) 2277 return (ENOBUFS); 2278 2279 /* 2280 * Move the data pointer up so that the incoming data packet 2281 * will be 32-bit aligned. 2282 */ 2283 m->m_data += RFA_ALIGNMENT_FUDGE; 2284 2285 /* 2286 * Get a pointer to the base of the mbuf cluster and move 2287 * data start past it. 2288 */ 2289 rfa = mtod(m, struct fxp_rfa *); 2290 m->m_data += sc->rfa_size; 2291 rfa->size = htole16(MCLBYTES - sc->rfa_size - RFA_ALIGNMENT_FUDGE); 2292 2293 /* 2294 * Initialize the rest of the RFA. Note that since the RFA 2295 * is misaligned, we cannot store values directly. Instead, 2296 * we use an optimized, inline copy. 2297 */ 2298 2299 rfa->rfa_status = 0; 2300 rfa->rfa_control = htole16(FXP_RFA_CONTROL_EL); 2301 rfa->actual_size = 0; 2302 2303 le32enc(&rfa->link_addr, 0xffffffff); 2304 le32enc(&rfa->rbd_addr, 0xffffffff); 2305 2306 /* Map the RFA into DMA memory. */ 2307 error = bus_dmamap_load(sc->fxp_mtag, sc->spare_map, rfa, 2308 MCLBYTES - RFA_ALIGNMENT_FUDGE, fxp_dma_map_addr, 2309 &rxp->rx_addr, 0); 2310 if (error) { 2311 m_freem(m); 2312 return (error); 2313 } 2314 2315 bus_dmamap_unload(sc->fxp_mtag, rxp->rx_map); 2316 tmp_map = sc->spare_map; 2317 sc->spare_map = rxp->rx_map; 2318 rxp->rx_map = tmp_map; 2319 rxp->rx_mbuf = m; 2320 2321 bus_dmamap_sync(sc->fxp_mtag, rxp->rx_map, 2322 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2323 2324 /* 2325 * If there are other buffers already on the list, attach this 2326 * one to the end by fixing up the tail to point to this one. 2327 */ 2328 if (sc->fxp_desc.rx_head != NULL) { 2329 p_rx = sc->fxp_desc.rx_tail; 2330 p_rfa = (struct fxp_rfa *) 2331 (p_rx->rx_mbuf->m_ext.ext_buf + RFA_ALIGNMENT_FUDGE); 2332 p_rx->rx_next = rxp; 2333 le32enc(&p_rfa->link_addr, rxp->rx_addr); 2334 p_rfa->rfa_control = 0; 2335 bus_dmamap_sync(sc->fxp_mtag, p_rx->rx_map, 2336 BUS_DMASYNC_PREWRITE); 2337 } else { 2338 rxp->rx_next = NULL; 2339 sc->fxp_desc.rx_head = rxp; 2340 } 2341 sc->fxp_desc.rx_tail = rxp; 2342 return (0); 2343 } 2344 2345 static volatile int 2346 fxp_miibus_readreg(device_t dev, int phy, int reg) 2347 { 2348 struct fxp_softc *sc = device_get_softc(dev); 2349 int count = 10000; 2350 int value; 2351 2352 CSR_WRITE_4(sc, FXP_CSR_MDICONTROL, 2353 (FXP_MDI_READ << 26) | (reg << 16) | (phy << 21)); 2354 2355 while (((value = CSR_READ_4(sc, FXP_CSR_MDICONTROL)) & 0x10000000) == 0 2356 && count--) 2357 DELAY(10); 2358 2359 if (count <= 0) 2360 device_printf(dev, "fxp_miibus_readreg: timed out\n"); 2361 2362 return (value & 0xffff); 2363 } 2364 2365 static void 2366 fxp_miibus_writereg(device_t dev, int phy, int reg, int value) 2367 { 2368 struct fxp_softc *sc = device_get_softc(dev); 2369 int count = 10000; 2370 2371 CSR_WRITE_4(sc, FXP_CSR_MDICONTROL, 2372 (FXP_MDI_WRITE << 26) | (reg << 16) | (phy << 21) | 2373 (value & 0xffff)); 2374 2375 while ((CSR_READ_4(sc, FXP_CSR_MDICONTROL) & 0x10000000) == 0 && 2376 count--) 2377 DELAY(10); 2378 2379 if (count <= 0) 2380 device_printf(dev, "fxp_miibus_writereg: timed out\n"); 2381 } 2382 2383 static int 2384 fxp_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 2385 { 2386 struct fxp_softc *sc = ifp->if_softc; 2387 struct ifreq *ifr = (struct ifreq *)data; 2388 struct mii_data *mii; 2389 int s, error = 0; 2390 2391 /* 2392 * Detaching causes us to call ioctl with the mutex owned. Preclude 2393 * that by saying we're busy if the lock is already held. 2394 */ 2395 if (mtx_owned(&sc->sc_mtx)) 2396 return (EBUSY); 2397 2398 FXP_LOCK(sc); 2399 s = splimp(); 2400 2401 switch (command) { 2402 case SIOCSIFFLAGS: 2403 if (ifp->if_flags & IFF_ALLMULTI) 2404 sc->flags |= FXP_FLAG_ALL_MCAST; 2405 else 2406 sc->flags &= ~FXP_FLAG_ALL_MCAST; 2407 2408 /* 2409 * If interface is marked up and not running, then start it. 2410 * If it is marked down and running, stop it. 2411 * XXX If it's up then re-initialize it. This is so flags 2412 * such as IFF_PROMISC are handled. 2413 */ 2414 if (ifp->if_flags & IFF_UP) { 2415 fxp_init_body(sc); 2416 } else { 2417 if (ifp->if_flags & IFF_RUNNING) 2418 fxp_stop(sc); 2419 } 2420 break; 2421 2422 case SIOCADDMULTI: 2423 case SIOCDELMULTI: 2424 if (ifp->if_flags & IFF_ALLMULTI) 2425 sc->flags |= FXP_FLAG_ALL_MCAST; 2426 else 2427 sc->flags &= ~FXP_FLAG_ALL_MCAST; 2428 /* 2429 * Multicast list has changed; set the hardware filter 2430 * accordingly. 2431 */ 2432 if ((sc->flags & FXP_FLAG_ALL_MCAST) == 0) 2433 fxp_mc_setup(sc); 2434 /* 2435 * fxp_mc_setup() can set FXP_FLAG_ALL_MCAST, so check it 2436 * again rather than else {}. 2437 */ 2438 if (sc->flags & FXP_FLAG_ALL_MCAST) 2439 fxp_init_body(sc); 2440 error = 0; 2441 break; 2442 2443 case SIOCSIFMEDIA: 2444 case SIOCGIFMEDIA: 2445 if (sc->miibus != NULL) { 2446 mii = device_get_softc(sc->miibus); 2447 error = ifmedia_ioctl(ifp, ifr, 2448 &mii->mii_media, command); 2449 } else { 2450 error = ifmedia_ioctl(ifp, ifr, &sc->sc_media, command); 2451 } 2452 break; 2453 2454 default: 2455 /* 2456 * ether_ioctl() will eventually call fxp_start() which 2457 * will result in mutex recursion so drop it first. 2458 */ 2459 FXP_UNLOCK(sc); 2460 error = ether_ioctl(ifp, command, data); 2461 } 2462 if (mtx_owned(&sc->sc_mtx)) 2463 FXP_UNLOCK(sc); 2464 splx(s); 2465 return (error); 2466 } 2467 2468 /* 2469 * Fill in the multicast address list and return number of entries. 2470 */ 2471 static int 2472 fxp_mc_addrs(struct fxp_softc *sc) 2473 { 2474 struct fxp_cb_mcs *mcsp = sc->mcsp; 2475 struct ifnet *ifp = &sc->sc_if; 2476 struct ifmultiaddr *ifma; 2477 int nmcasts; 2478 2479 nmcasts = 0; 2480 if ((sc->flags & FXP_FLAG_ALL_MCAST) == 0) { 2481 #if __FreeBSD_version < 500000 2482 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 2483 #else 2484 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 2485 #endif 2486 if (ifma->ifma_addr->sa_family != AF_LINK) 2487 continue; 2488 if (nmcasts >= MAXMCADDR) { 2489 sc->flags |= FXP_FLAG_ALL_MCAST; 2490 nmcasts = 0; 2491 break; 2492 } 2493 bcopy(LLADDR((struct sockaddr_dl *)ifma->ifma_addr), 2494 &sc->mcsp->mc_addr[nmcasts][0], ETHER_ADDR_LEN); 2495 nmcasts++; 2496 } 2497 } 2498 mcsp->mc_cnt = htole16(nmcasts * ETHER_ADDR_LEN); 2499 return (nmcasts); 2500 } 2501 2502 /* 2503 * Program the multicast filter. 2504 * 2505 * We have an artificial restriction that the multicast setup command 2506 * must be the first command in the chain, so we take steps to ensure 2507 * this. By requiring this, it allows us to keep up the performance of 2508 * the pre-initialized command ring (esp. link pointers) by not actually 2509 * inserting the mcsetup command in the ring - i.e. its link pointer 2510 * points to the TxCB ring, but the mcsetup descriptor itself is not part 2511 * of it. We then can do 'CU_START' on the mcsetup descriptor and have it 2512 * lead into the regular TxCB ring when it completes. 2513 * 2514 * This function must be called at splimp. 2515 */ 2516 static void 2517 fxp_mc_setup(struct fxp_softc *sc) 2518 { 2519 struct fxp_cb_mcs *mcsp = sc->mcsp; 2520 struct ifnet *ifp = &sc->sc_if; 2521 struct fxp_tx *txp; 2522 int count; 2523 2524 /* 2525 * If there are queued commands, we must wait until they are all 2526 * completed. If we are already waiting, then add a NOP command 2527 * with interrupt option so that we're notified when all commands 2528 * have been completed - fxp_start() ensures that no additional 2529 * TX commands will be added when need_mcsetup is true. 2530 */ 2531 if (sc->tx_queued) { 2532 /* 2533 * need_mcsetup will be true if we are already waiting for the 2534 * NOP command to be completed (see below). In this case, bail. 2535 */ 2536 if (sc->need_mcsetup) 2537 return; 2538 sc->need_mcsetup = 1; 2539 2540 /* 2541 * Add a NOP command with interrupt so that we are notified 2542 * when all TX commands have been processed. 2543 */ 2544 txp = sc->fxp_desc.tx_last->tx_next; 2545 txp->tx_mbuf = NULL; 2546 txp->tx_cb->cb_status = 0; 2547 txp->tx_cb->cb_command = htole16(FXP_CB_COMMAND_NOP | 2548 FXP_CB_COMMAND_S | FXP_CB_COMMAND_I); 2549 /* 2550 * Advance the end of list forward. 2551 */ 2552 sc->fxp_desc.tx_last->tx_cb->cb_command &= 2553 htole16(~FXP_CB_COMMAND_S); 2554 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE); 2555 sc->fxp_desc.tx_last = txp; 2556 sc->tx_queued++; 2557 /* 2558 * Issue a resume in case the CU has just suspended. 2559 */ 2560 fxp_scb_wait(sc); 2561 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_RESUME); 2562 /* 2563 * Set a 5 second timer just in case we don't hear from the 2564 * card again. 2565 */ 2566 ifp->if_timer = 5; 2567 2568 return; 2569 } 2570 sc->need_mcsetup = 0; 2571 2572 /* 2573 * Initialize multicast setup descriptor. 2574 */ 2575 mcsp->cb_status = 0; 2576 mcsp->cb_command = htole16(FXP_CB_COMMAND_MCAS | 2577 FXP_CB_COMMAND_S | FXP_CB_COMMAND_I); 2578 mcsp->link_addr = htole32(sc->fxp_desc.cbl_addr); 2579 txp = &sc->fxp_desc.mcs_tx; 2580 txp->tx_mbuf = NULL; 2581 txp->tx_cb = (struct fxp_cb_tx *)sc->mcsp; 2582 txp->tx_next = sc->fxp_desc.tx_list; 2583 (void) fxp_mc_addrs(sc); 2584 sc->fxp_desc.tx_first = sc->fxp_desc.tx_last = txp; 2585 sc->tx_queued = 1; 2586 2587 /* 2588 * Wait until command unit is not active. This should never 2589 * be the case when nothing is queued, but make sure anyway. 2590 */ 2591 count = 100; 2592 while ((CSR_READ_1(sc, FXP_CSR_SCB_RUSCUS) >> 6) == 2593 FXP_SCB_CUS_ACTIVE && --count) 2594 DELAY(10); 2595 if (count == 0) { 2596 device_printf(sc->dev, "command queue timeout\n"); 2597 return; 2598 } 2599 2600 /* 2601 * Start the multicast setup command. 2602 */ 2603 fxp_scb_wait(sc); 2604 bus_dmamap_sync(sc->mcs_tag, sc->mcs_map, BUS_DMASYNC_PREWRITE); 2605 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->mcs_addr); 2606 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2607 2608 ifp->if_timer = 2; 2609 return; 2610 } 2611 2612 static u_int32_t fxp_ucode_d101a[] = D101_A_RCVBUNDLE_UCODE; 2613 static u_int32_t fxp_ucode_d101b0[] = D101_B0_RCVBUNDLE_UCODE; 2614 static u_int32_t fxp_ucode_d101ma[] = D101M_B_RCVBUNDLE_UCODE; 2615 static u_int32_t fxp_ucode_d101s[] = D101S_RCVBUNDLE_UCODE; 2616 static u_int32_t fxp_ucode_d102[] = D102_B_RCVBUNDLE_UCODE; 2617 static u_int32_t fxp_ucode_d102c[] = D102_C_RCVBUNDLE_UCODE; 2618 2619 #define UCODE(x) x, sizeof(x) 2620 2621 struct ucode { 2622 u_int32_t revision; 2623 u_int32_t *ucode; 2624 int length; 2625 u_short int_delay_offset; 2626 u_short bundle_max_offset; 2627 } ucode_table[] = { 2628 { FXP_REV_82558_A4, UCODE(fxp_ucode_d101a), D101_CPUSAVER_DWORD, 0 }, 2629 { FXP_REV_82558_B0, UCODE(fxp_ucode_d101b0), D101_CPUSAVER_DWORD, 0 }, 2630 { FXP_REV_82559_A0, UCODE(fxp_ucode_d101ma), 2631 D101M_CPUSAVER_DWORD, D101M_CPUSAVER_BUNDLE_MAX_DWORD }, 2632 { FXP_REV_82559S_A, UCODE(fxp_ucode_d101s), 2633 D101S_CPUSAVER_DWORD, D101S_CPUSAVER_BUNDLE_MAX_DWORD }, 2634 { FXP_REV_82550, UCODE(fxp_ucode_d102), 2635 D102_B_CPUSAVER_DWORD, D102_B_CPUSAVER_BUNDLE_MAX_DWORD }, 2636 { FXP_REV_82550_C, UCODE(fxp_ucode_d102c), 2637 D102_C_CPUSAVER_DWORD, D102_C_CPUSAVER_BUNDLE_MAX_DWORD }, 2638 { 0, NULL, 0, 0, 0 } 2639 }; 2640 2641 static void 2642 fxp_load_ucode(struct fxp_softc *sc) 2643 { 2644 struct ucode *uc; 2645 struct fxp_cb_ucode *cbp; 2646 2647 for (uc = ucode_table; uc->ucode != NULL; uc++) 2648 if (sc->revision == uc->revision) 2649 break; 2650 if (uc->ucode == NULL) 2651 return; 2652 cbp = (struct fxp_cb_ucode *)sc->fxp_desc.cbl_list; 2653 cbp->cb_status = 0; 2654 cbp->cb_command = htole16(FXP_CB_COMMAND_UCODE | FXP_CB_COMMAND_EL); 2655 cbp->link_addr = 0xffffffff; /* (no) next command */ 2656 memcpy(cbp->ucode, uc->ucode, uc->length); 2657 if (uc->int_delay_offset) 2658 *(u_int16_t *)&cbp->ucode[uc->int_delay_offset] = 2659 htole16(sc->tunable_int_delay + sc->tunable_int_delay / 2); 2660 if (uc->bundle_max_offset) 2661 *(u_int16_t *)&cbp->ucode[uc->bundle_max_offset] = 2662 htole16(sc->tunable_bundle_max); 2663 /* 2664 * Download the ucode to the chip. 2665 */ 2666 fxp_scb_wait(sc); 2667 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE); 2668 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->fxp_desc.cbl_addr); 2669 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2670 /* ...and wait for it to complete. */ 2671 fxp_dma_wait(sc, &cbp->cb_status, sc->cbl_tag, sc->cbl_map); 2672 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_POSTWRITE); 2673 device_printf(sc->dev, 2674 "Microcode loaded, int_delay: %d usec bundle_max: %d\n", 2675 sc->tunable_int_delay, 2676 uc->bundle_max_offset == 0 ? 0 : sc->tunable_bundle_max); 2677 sc->flags |= FXP_FLAG_UCODE; 2678 } 2679 2680 static int 2681 sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high) 2682 { 2683 int error, value; 2684 2685 value = *(int *)arg1; 2686 error = sysctl_handle_int(oidp, &value, 0, req); 2687 if (error || !req->newptr) 2688 return (error); 2689 if (value < low || value > high) 2690 return (EINVAL); 2691 *(int *)arg1 = value; 2692 return (0); 2693 } 2694 2695 /* 2696 * Interrupt delay is expressed in microseconds, a multiplier is used 2697 * to convert this to the appropriate clock ticks before using. 2698 */ 2699 static int 2700 sysctl_hw_fxp_int_delay(SYSCTL_HANDLER_ARGS) 2701 { 2702 return (sysctl_int_range(oidp, arg1, arg2, req, 300, 3000)); 2703 } 2704 2705 static int 2706 sysctl_hw_fxp_bundle_max(SYSCTL_HANDLER_ARGS) 2707 { 2708 return (sysctl_int_range(oidp, arg1, arg2, req, 1, 0xffff)); 2709 } 2710