1 /*- 2 * Copyright (c) 1995, David Greenman 3 * Copyright (c) 2001 Jonathan Lemon <jlemon@freebsd.org> 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice unmodified, this list of conditions, and the following 11 * disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 * 28 */ 29 30 #include <sys/cdefs.h> 31 __FBSDID("$FreeBSD$"); 32 33 /* 34 * Intel EtherExpress Pro/100B PCI Fast Ethernet driver 35 */ 36 37 #include <sys/param.h> 38 #include <sys/systm.h> 39 #include <sys/endian.h> 40 #include <sys/mbuf.h> 41 /* #include <sys/mutex.h> */ 42 #include <sys/kernel.h> 43 #include <sys/module.h> 44 #include <sys/socket.h> 45 #include <sys/sysctl.h> 46 47 #include <net/if.h> 48 #include <net/if_dl.h> 49 #include <net/if_media.h> 50 51 #include <net/bpf.h> 52 #include <sys/sockio.h> 53 #include <sys/bus.h> 54 #include <machine/bus.h> 55 #include <sys/rman.h> 56 #include <machine/resource.h> 57 58 #include <net/ethernet.h> 59 #include <net/if_arp.h> 60 61 #include <machine/clock.h> /* for DELAY */ 62 63 #include <net/if_types.h> 64 #include <net/if_vlan_var.h> 65 66 #ifdef FXP_IP_CSUM_WAR 67 #include <netinet/in.h> 68 #include <netinet/in_systm.h> 69 #include <netinet/ip.h> 70 #include <machine/in_cksum.h> 71 #endif 72 73 #include <dev/pci/pcivar.h> 74 #include <dev/pci/pcireg.h> /* for PCIM_CMD_xxx */ 75 76 #include <dev/mii/mii.h> 77 #include <dev/mii/miivar.h> 78 79 #include <dev/fxp/if_fxpreg.h> 80 #include <dev/fxp/if_fxpvar.h> 81 #include <dev/fxp/rcvbundl.h> 82 83 MODULE_DEPEND(fxp, pci, 1, 1, 1); 84 MODULE_DEPEND(fxp, ether, 1, 1, 1); 85 MODULE_DEPEND(fxp, miibus, 1, 1, 1); 86 #include "miibus_if.h" 87 88 /* 89 * NOTE! On the Alpha, we have an alignment constraint. The 90 * card DMAs the packet immediately following the RFA. However, 91 * the first thing in the packet is a 14-byte Ethernet header. 92 * This means that the packet is misaligned. To compensate, 93 * we actually offset the RFA 2 bytes into the cluster. This 94 * alignes the packet after the Ethernet header at a 32-bit 95 * boundary. HOWEVER! This means that the RFA is misaligned! 96 */ 97 #define RFA_ALIGNMENT_FUDGE 2 98 99 /* 100 * Set initial transmit threshold at 64 (512 bytes). This is 101 * increased by 64 (512 bytes) at a time, to maximum of 192 102 * (1536 bytes), if an underrun occurs. 103 */ 104 static int tx_threshold = 64; 105 106 /* 107 * The configuration byte map has several undefined fields which 108 * must be one or must be zero. Set up a template for these bits 109 * only, (assuming a 82557 chip) leaving the actual configuration 110 * to fxp_init. 111 * 112 * See struct fxp_cb_config for the bit definitions. 113 */ 114 static u_char fxp_cb_config_template[] = { 115 0x0, 0x0, /* cb_status */ 116 0x0, 0x0, /* cb_command */ 117 0x0, 0x0, 0x0, 0x0, /* link_addr */ 118 0x0, /* 0 */ 119 0x0, /* 1 */ 120 0x0, /* 2 */ 121 0x0, /* 3 */ 122 0x0, /* 4 */ 123 0x0, /* 5 */ 124 0x32, /* 6 */ 125 0x0, /* 7 */ 126 0x0, /* 8 */ 127 0x0, /* 9 */ 128 0x6, /* 10 */ 129 0x0, /* 11 */ 130 0x0, /* 12 */ 131 0x0, /* 13 */ 132 0xf2, /* 14 */ 133 0x48, /* 15 */ 134 0x0, /* 16 */ 135 0x40, /* 17 */ 136 0xf0, /* 18 */ 137 0x0, /* 19 */ 138 0x3f, /* 20 */ 139 0x5 /* 21 */ 140 }; 141 142 struct fxp_ident { 143 uint16_t devid; 144 int16_t revid; /* -1 matches anything */ 145 char *name; 146 }; 147 148 /* 149 * Claim various Intel PCI device identifiers for this driver. The 150 * sub-vendor and sub-device field are extensively used to identify 151 * particular variants, but we don't currently differentiate between 152 * them. 153 */ 154 static struct fxp_ident fxp_ident_table[] = { 155 { 0x1029, -1, "Intel 82559 PCI/CardBus Pro/100" }, 156 { 0x1030, -1, "Intel 82559 Pro/100 Ethernet" }, 157 { 0x1031, -1, "Intel 82801CAM (ICH3) Pro/100 VE Ethernet" }, 158 { 0x1032, -1, "Intel 82801CAM (ICH3) Pro/100 VE Ethernet" }, 159 { 0x1033, -1, "Intel 82801CAM (ICH3) Pro/100 VM Ethernet" }, 160 { 0x1034, -1, "Intel 82801CAM (ICH3) Pro/100 VM Ethernet" }, 161 { 0x1035, -1, "Intel 82801CAM (ICH3) Pro/100 Ethernet" }, 162 { 0x1036, -1, "Intel 82801CAM (ICH3) Pro/100 Ethernet" }, 163 { 0x1037, -1, "Intel 82801CAM (ICH3) Pro/100 Ethernet" }, 164 { 0x1038, -1, "Intel 82801CAM (ICH3) Pro/100 VM Ethernet" }, 165 { 0x1039, -1, "Intel 82801DB (ICH4) Pro/100 VE Ethernet" }, 166 { 0x103A, -1, "Intel 82801DB (ICH4) Pro/100 Ethernet" }, 167 { 0x103B, -1, "Intel 82801DB (ICH4) Pro/100 VM Ethernet" }, 168 { 0x103C, -1, "Intel 82801DB (ICH4) Pro/100 Ethernet" }, 169 { 0x103D, -1, "Intel 82801DB (ICH4) Pro/100 VE Ethernet" }, 170 { 0x103E, -1, "Intel 82801DB (ICH4) Pro/100 VM Ethernet" }, 171 { 0x1050, -1, "Intel 82801BA (D865) Pro/100 VE Ethernet" }, 172 { 0x1051, -1, "Intel 82562ET (ICH5/ICH5R) Pro/100 VE Ethernet" }, 173 { 0x1059, -1, "Intel 82551QM Pro/100 M Mobile Connection" }, 174 { 0x1064, -1, "Intel 82562EZ (ICH6)" }, 175 { 0x1068, -1, "Intel 82801FBM (ICH6-M) Pro/100 VE Ethernet" }, 176 { 0x1209, -1, "Intel 82559ER Embedded 10/100 Ethernet" }, 177 { 0x1229, 0x01, "Intel 82557 Pro/100 Ethernet" }, 178 { 0x1229, 0x02, "Intel 82557 Pro/100 Ethernet" }, 179 { 0x1229, 0x03, "Intel 82557 Pro/100 Ethernet" }, 180 { 0x1229, 0x04, "Intel 82558 Pro/100 Ethernet" }, 181 { 0x1229, 0x05, "Intel 82558 Pro/100 Ethernet" }, 182 { 0x1229, 0x06, "Intel 82559 Pro/100 Ethernet" }, 183 { 0x1229, 0x07, "Intel 82559 Pro/100 Ethernet" }, 184 { 0x1229, 0x08, "Intel 82559 Pro/100 Ethernet" }, 185 { 0x1229, 0x09, "Intel 82559ER Pro/100 Ethernet" }, 186 { 0x1229, 0x0c, "Intel 82550 Pro/100 Ethernet" }, 187 { 0x1229, 0x0d, "Intel 82550 Pro/100 Ethernet" }, 188 { 0x1229, 0x0e, "Intel 82550 Pro/100 Ethernet" }, 189 { 0x1229, 0x0f, "Intel 82551 Pro/100 Ethernet" }, 190 { 0x1229, 0x10, "Intel 82551 Pro/100 Ethernet" }, 191 { 0x1229, -1, "Intel 82557/8/9 Pro/100 Ethernet" }, 192 { 0x2449, -1, "Intel 82801BA/CAM (ICH2/3) Pro/100 Ethernet" }, 193 { 0x27dc, -1, "Intel 82801GB (ICH7) 10/100 Ethernet" }, 194 { 0, -1, NULL }, 195 }; 196 197 #ifdef FXP_IP_CSUM_WAR 198 #define FXP_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 199 #else 200 #define FXP_CSUM_FEATURES (CSUM_TCP | CSUM_UDP) 201 #endif 202 203 static int fxp_probe(device_t dev); 204 static int fxp_attach(device_t dev); 205 static int fxp_detach(device_t dev); 206 static int fxp_shutdown(device_t dev); 207 static int fxp_suspend(device_t dev); 208 static int fxp_resume(device_t dev); 209 210 static void fxp_intr(void *xsc); 211 static void fxp_intr_body(struct fxp_softc *sc, struct ifnet *ifp, 212 uint8_t statack, int count); 213 static void fxp_init(void *xsc); 214 static void fxp_init_body(struct fxp_softc *sc); 215 static void fxp_tick(void *xsc); 216 static void fxp_start(struct ifnet *ifp); 217 static void fxp_start_body(struct ifnet *ifp); 218 static int fxp_encap(struct fxp_softc *sc, struct mbuf *m_head); 219 static void fxp_stop(struct fxp_softc *sc); 220 static void fxp_release(struct fxp_softc *sc); 221 static int fxp_ioctl(struct ifnet *ifp, u_long command, 222 caddr_t data); 223 static void fxp_watchdog(struct ifnet *ifp); 224 static int fxp_add_rfabuf(struct fxp_softc *sc, 225 struct fxp_rx *rxp); 226 static int fxp_mc_addrs(struct fxp_softc *sc); 227 static void fxp_mc_setup(struct fxp_softc *sc); 228 static uint16_t fxp_eeprom_getword(struct fxp_softc *sc, int offset, 229 int autosize); 230 static void fxp_eeprom_putword(struct fxp_softc *sc, int offset, 231 uint16_t data); 232 static void fxp_autosize_eeprom(struct fxp_softc *sc); 233 static void fxp_read_eeprom(struct fxp_softc *sc, u_short *data, 234 int offset, int words); 235 static void fxp_write_eeprom(struct fxp_softc *sc, u_short *data, 236 int offset, int words); 237 static int fxp_ifmedia_upd(struct ifnet *ifp); 238 static void fxp_ifmedia_sts(struct ifnet *ifp, 239 struct ifmediareq *ifmr); 240 static int fxp_serial_ifmedia_upd(struct ifnet *ifp); 241 static void fxp_serial_ifmedia_sts(struct ifnet *ifp, 242 struct ifmediareq *ifmr); 243 static volatile int fxp_miibus_readreg(device_t dev, int phy, int reg); 244 static void fxp_miibus_writereg(device_t dev, int phy, int reg, 245 int value); 246 static void fxp_load_ucode(struct fxp_softc *sc); 247 static int sysctl_int_range(SYSCTL_HANDLER_ARGS, 248 int low, int high); 249 static int sysctl_hw_fxp_bundle_max(SYSCTL_HANDLER_ARGS); 250 static int sysctl_hw_fxp_int_delay(SYSCTL_HANDLER_ARGS); 251 static void fxp_scb_wait(struct fxp_softc *sc); 252 static void fxp_scb_cmd(struct fxp_softc *sc, int cmd); 253 static void fxp_dma_wait(struct fxp_softc *sc, 254 volatile uint16_t *status, bus_dma_tag_t dmat, 255 bus_dmamap_t map); 256 257 static device_method_t fxp_methods[] = { 258 /* Device interface */ 259 DEVMETHOD(device_probe, fxp_probe), 260 DEVMETHOD(device_attach, fxp_attach), 261 DEVMETHOD(device_detach, fxp_detach), 262 DEVMETHOD(device_shutdown, fxp_shutdown), 263 DEVMETHOD(device_suspend, fxp_suspend), 264 DEVMETHOD(device_resume, fxp_resume), 265 266 /* MII interface */ 267 DEVMETHOD(miibus_readreg, fxp_miibus_readreg), 268 DEVMETHOD(miibus_writereg, fxp_miibus_writereg), 269 270 { 0, 0 } 271 }; 272 273 static driver_t fxp_driver = { 274 "fxp", 275 fxp_methods, 276 sizeof(struct fxp_softc), 277 }; 278 279 static devclass_t fxp_devclass; 280 281 DRIVER_MODULE(fxp, pci, fxp_driver, fxp_devclass, 0, 0); 282 DRIVER_MODULE(fxp, cardbus, fxp_driver, fxp_devclass, 0, 0); 283 DRIVER_MODULE(miibus, fxp, miibus_driver, miibus_devclass, 0, 0); 284 285 /* 286 * Wait for the previous command to be accepted (but not necessarily 287 * completed). 288 */ 289 static void 290 fxp_scb_wait(struct fxp_softc *sc) 291 { 292 int i = 10000; 293 294 while (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) && --i) 295 DELAY(2); 296 if (i == 0) 297 device_printf(sc->dev, "SCB timeout: 0x%x 0x%x 0x%x 0x%x\n", 298 CSR_READ_1(sc, FXP_CSR_SCB_COMMAND), 299 CSR_READ_1(sc, FXP_CSR_SCB_STATACK), 300 CSR_READ_1(sc, FXP_CSR_SCB_RUSCUS), 301 CSR_READ_2(sc, FXP_CSR_FLOWCONTROL)); 302 } 303 304 static void 305 fxp_scb_cmd(struct fxp_softc *sc, int cmd) 306 { 307 308 if (cmd == FXP_SCB_COMMAND_CU_RESUME && sc->cu_resume_bug) { 309 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_CB_COMMAND_NOP); 310 fxp_scb_wait(sc); 311 } 312 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, cmd); 313 } 314 315 static void 316 fxp_dma_wait(struct fxp_softc *sc, volatile uint16_t *status, 317 bus_dma_tag_t dmat, bus_dmamap_t map) 318 { 319 int i = 10000; 320 321 bus_dmamap_sync(dmat, map, BUS_DMASYNC_POSTREAD); 322 while (!(le16toh(*status) & FXP_CB_STATUS_C) && --i) { 323 DELAY(2); 324 bus_dmamap_sync(dmat, map, BUS_DMASYNC_POSTREAD); 325 } 326 if (i == 0) 327 device_printf(sc->dev, "DMA timeout\n"); 328 } 329 330 /* 331 * Return identification string if this device is ours. 332 */ 333 static int 334 fxp_probe(device_t dev) 335 { 336 uint16_t devid; 337 uint8_t revid; 338 struct fxp_ident *ident; 339 340 if (pci_get_vendor(dev) == FXP_VENDORID_INTEL) { 341 devid = pci_get_device(dev); 342 revid = pci_get_revid(dev); 343 for (ident = fxp_ident_table; ident->name != NULL; ident++) { 344 if (ident->devid == devid && 345 (ident->revid == revid || ident->revid == -1)) { 346 device_set_desc(dev, ident->name); 347 return (BUS_PROBE_DEFAULT); 348 } 349 } 350 } 351 return (ENXIO); 352 } 353 354 static void 355 fxp_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error) 356 { 357 uint32_t *addr; 358 359 if (error) 360 return; 361 362 KASSERT(nseg == 1, ("too many DMA segments, %d should be 1", nseg)); 363 addr = arg; 364 *addr = segs->ds_addr; 365 } 366 367 static int 368 fxp_attach(device_t dev) 369 { 370 struct fxp_softc *sc; 371 struct fxp_cb_tx *tcbp; 372 struct fxp_tx *txp; 373 struct fxp_rx *rxp; 374 struct ifnet *ifp; 375 uint32_t val; 376 uint16_t data, myea[ETHER_ADDR_LEN / 2]; 377 u_char eaddr[ETHER_ADDR_LEN]; 378 int i, rid, m1, m2, prefer_iomap; 379 int error; 380 381 error = 0; 382 sc = device_get_softc(dev); 383 sc->dev = dev; 384 mtx_init(&sc->sc_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 385 MTX_DEF); 386 callout_init_mtx(&sc->stat_ch, &sc->sc_mtx, 0); 387 ifmedia_init(&sc->sc_media, 0, fxp_serial_ifmedia_upd, 388 fxp_serial_ifmedia_sts); 389 390 ifp = sc->ifp = if_alloc(IFT_ETHER); 391 if (ifp == NULL) { 392 device_printf(dev, "can not if_alloc()\n"); 393 error = ENOSPC; 394 goto fail; 395 } 396 397 /* 398 * Enable bus mastering. 399 */ 400 pci_enable_busmaster(dev); 401 val = pci_read_config(dev, PCIR_COMMAND, 2); 402 403 /* 404 * Figure out which we should try first - memory mapping or i/o mapping? 405 * We default to memory mapping. Then we accept an override from the 406 * command line. Then we check to see which one is enabled. 407 */ 408 m1 = PCIM_CMD_MEMEN; 409 m2 = PCIM_CMD_PORTEN; 410 prefer_iomap = 0; 411 if (resource_int_value(device_get_name(dev), device_get_unit(dev), 412 "prefer_iomap", &prefer_iomap) == 0 && prefer_iomap != 0) { 413 m1 = PCIM_CMD_PORTEN; 414 m2 = PCIM_CMD_MEMEN; 415 } 416 417 sc->rtp = (m1 == PCIM_CMD_MEMEN)? SYS_RES_MEMORY : SYS_RES_IOPORT; 418 sc->rgd = (m1 == PCIM_CMD_MEMEN)? FXP_PCI_MMBA : FXP_PCI_IOBA; 419 sc->mem = bus_alloc_resource_any(dev, sc->rtp, &sc->rgd, RF_ACTIVE); 420 if (sc->mem == NULL) { 421 sc->rtp = 422 (m2 == PCIM_CMD_MEMEN)? SYS_RES_MEMORY : SYS_RES_IOPORT; 423 sc->rgd = (m2 == PCIM_CMD_MEMEN)? FXP_PCI_MMBA : FXP_PCI_IOBA; 424 sc->mem = bus_alloc_resource_any(dev, sc->rtp, &sc->rgd, 425 RF_ACTIVE); 426 } 427 428 if (!sc->mem) { 429 error = ENXIO; 430 goto fail; 431 } 432 if (bootverbose) { 433 device_printf(dev, "using %s space register mapping\n", 434 sc->rtp == SYS_RES_MEMORY? "memory" : "I/O"); 435 } 436 437 sc->sc_st = rman_get_bustag(sc->mem); 438 sc->sc_sh = rman_get_bushandle(sc->mem); 439 440 /* 441 * Allocate our interrupt. 442 */ 443 rid = 0; 444 sc->irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 445 RF_SHAREABLE | RF_ACTIVE); 446 if (sc->irq == NULL) { 447 device_printf(dev, "could not map interrupt\n"); 448 error = ENXIO; 449 goto fail; 450 } 451 452 /* 453 * Reset to a stable state. 454 */ 455 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET); 456 DELAY(10); 457 458 /* 459 * Find out how large of an SEEPROM we have. 460 */ 461 fxp_autosize_eeprom(sc); 462 463 /* 464 * Find out the chip revision; lump all 82557 revs together. 465 */ 466 fxp_read_eeprom(sc, &data, 5, 1); 467 if ((data >> 8) == 1) 468 sc->revision = FXP_REV_82557; 469 else 470 sc->revision = pci_get_revid(dev); 471 472 /* 473 * Determine whether we must use the 503 serial interface. 474 */ 475 fxp_read_eeprom(sc, &data, 6, 1); 476 if (sc->revision == FXP_REV_82557 && (data & FXP_PHY_DEVICE_MASK) != 0 477 && (data & FXP_PHY_SERIAL_ONLY)) 478 sc->flags |= FXP_FLAG_SERIAL_MEDIA; 479 480 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 481 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 482 OID_AUTO, "int_delay", CTLTYPE_INT | CTLFLAG_RW, 483 &sc->tunable_int_delay, 0, sysctl_hw_fxp_int_delay, "I", 484 "FXP driver receive interrupt microcode bundling delay"); 485 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 486 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 487 OID_AUTO, "bundle_max", CTLTYPE_INT | CTLFLAG_RW, 488 &sc->tunable_bundle_max, 0, sysctl_hw_fxp_bundle_max, "I", 489 "FXP driver receive interrupt microcode bundle size limit"); 490 SYSCTL_ADD_INT(device_get_sysctl_ctx(dev), 491 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 492 OID_AUTO, "rnr", CTLFLAG_RD, &sc->rnr, 0, 493 "FXP RNR events"); 494 SYSCTL_ADD_INT(device_get_sysctl_ctx(dev), 495 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 496 OID_AUTO, "noflow", CTLFLAG_RW, &sc->tunable_noflow, 0, 497 "FXP flow control disabled"); 498 499 /* 500 * Pull in device tunables. 501 */ 502 sc->tunable_int_delay = TUNABLE_INT_DELAY; 503 sc->tunable_bundle_max = TUNABLE_BUNDLE_MAX; 504 sc->tunable_noflow = 1; 505 (void) resource_int_value(device_get_name(dev), device_get_unit(dev), 506 "int_delay", &sc->tunable_int_delay); 507 (void) resource_int_value(device_get_name(dev), device_get_unit(dev), 508 "bundle_max", &sc->tunable_bundle_max); 509 (void) resource_int_value(device_get_name(dev), device_get_unit(dev), 510 "noflow", &sc->tunable_noflow); 511 sc->rnr = 0; 512 513 /* 514 * Enable workarounds for certain chip revision deficiencies. 515 * 516 * Systems based on the ICH2/ICH2-M chip from Intel, and possibly 517 * some systems based a normal 82559 design, have a defect where 518 * the chip can cause a PCI protocol violation if it receives 519 * a CU_RESUME command when it is entering the IDLE state. The 520 * workaround is to disable Dynamic Standby Mode, so the chip never 521 * deasserts CLKRUN#, and always remains in an active state. 522 * 523 * See Intel 82801BA/82801BAM Specification Update, Errata #30. 524 */ 525 i = pci_get_device(dev); 526 if (i == 0x2449 || (i > 0x1030 && i < 0x1039) || 527 sc->revision >= FXP_REV_82559_A0) { 528 fxp_read_eeprom(sc, &data, 10, 1); 529 if (data & 0x02) { /* STB enable */ 530 uint16_t cksum; 531 int i; 532 533 device_printf(dev, 534 "Disabling dynamic standby mode in EEPROM\n"); 535 data &= ~0x02; 536 fxp_write_eeprom(sc, &data, 10, 1); 537 device_printf(dev, "New EEPROM ID: 0x%x\n", data); 538 cksum = 0; 539 for (i = 0; i < (1 << sc->eeprom_size) - 1; i++) { 540 fxp_read_eeprom(sc, &data, i, 1); 541 cksum += data; 542 } 543 i = (1 << sc->eeprom_size) - 1; 544 cksum = 0xBABA - cksum; 545 fxp_read_eeprom(sc, &data, i, 1); 546 fxp_write_eeprom(sc, &cksum, i, 1); 547 device_printf(dev, 548 "EEPROM checksum @ 0x%x: 0x%x -> 0x%x\n", 549 i, data, cksum); 550 #if 1 551 /* 552 * If the user elects to continue, try the software 553 * workaround, as it is better than nothing. 554 */ 555 sc->flags |= FXP_FLAG_CU_RESUME_BUG; 556 #endif 557 } 558 } 559 560 /* 561 * If we are not a 82557 chip, we can enable extended features. 562 */ 563 if (sc->revision != FXP_REV_82557) { 564 /* 565 * If MWI is enabled in the PCI configuration, and there 566 * is a valid cacheline size (8 or 16 dwords), then tell 567 * the board to turn on MWI. 568 */ 569 if (val & PCIM_CMD_MWRICEN && 570 pci_read_config(dev, PCIR_CACHELNSZ, 1) != 0) 571 sc->flags |= FXP_FLAG_MWI_ENABLE; 572 573 /* turn on the extended TxCB feature */ 574 sc->flags |= FXP_FLAG_EXT_TXCB; 575 576 /* enable reception of long frames for VLAN */ 577 sc->flags |= FXP_FLAG_LONG_PKT_EN; 578 } else { 579 /* a hack to get long VLAN frames on a 82557 */ 580 sc->flags |= FXP_FLAG_SAVE_BAD; 581 } 582 583 /* 584 * Enable use of extended RFDs and TCBs for 82550 585 * and later chips. Note: we need extended TXCB support 586 * too, but that's already enabled by the code above. 587 * Be careful to do this only on the right devices. 588 */ 589 if (sc->revision == FXP_REV_82550 || sc->revision == FXP_REV_82550_C || 590 sc->revision == FXP_REV_82551_E || sc->revision == FXP_REV_82551_F 591 || sc->revision == FXP_REV_82551_10) { 592 sc->rfa_size = sizeof (struct fxp_rfa); 593 sc->tx_cmd = FXP_CB_COMMAND_IPCBXMIT; 594 sc->flags |= FXP_FLAG_EXT_RFA; 595 } else { 596 sc->rfa_size = sizeof (struct fxp_rfa) - FXP_RFAX_LEN; 597 sc->tx_cmd = FXP_CB_COMMAND_XMIT; 598 } 599 600 /* 601 * Allocate DMA tags and DMA safe memory. 602 */ 603 sc->maxtxseg = FXP_NTXSEG; 604 if (sc->flags & FXP_FLAG_EXT_RFA) 605 sc->maxtxseg--; 606 error = bus_dma_tag_create(NULL, 2, 0, BUS_SPACE_MAXADDR_32BIT, 607 BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES * sc->maxtxseg, 608 sc->maxtxseg, MCLBYTES, 0, busdma_lock_mutex, &Giant, 609 &sc->fxp_mtag); 610 if (error) { 611 device_printf(dev, "could not allocate dma tag\n"); 612 goto fail; 613 } 614 615 error = bus_dma_tag_create(NULL, 4, 0, BUS_SPACE_MAXADDR_32BIT, 616 BUS_SPACE_MAXADDR, NULL, NULL, sizeof(struct fxp_stats), 1, 617 sizeof(struct fxp_stats), 0, busdma_lock_mutex, &Giant, 618 &sc->fxp_stag); 619 if (error) { 620 device_printf(dev, "could not allocate dma tag\n"); 621 goto fail; 622 } 623 624 error = bus_dmamem_alloc(sc->fxp_stag, (void **)&sc->fxp_stats, 625 BUS_DMA_NOWAIT | BUS_DMA_ZERO, &sc->fxp_smap); 626 if (error) 627 goto fail; 628 error = bus_dmamap_load(sc->fxp_stag, sc->fxp_smap, sc->fxp_stats, 629 sizeof(struct fxp_stats), fxp_dma_map_addr, &sc->stats_addr, 0); 630 if (error) { 631 device_printf(dev, "could not map the stats buffer\n"); 632 goto fail; 633 } 634 635 error = bus_dma_tag_create(NULL, 4, 0, BUS_SPACE_MAXADDR_32BIT, 636 BUS_SPACE_MAXADDR, NULL, NULL, FXP_TXCB_SZ, 1, 637 FXP_TXCB_SZ, 0, busdma_lock_mutex, &Giant, &sc->cbl_tag); 638 if (error) { 639 device_printf(dev, "could not allocate dma tag\n"); 640 goto fail; 641 } 642 643 error = bus_dmamem_alloc(sc->cbl_tag, (void **)&sc->fxp_desc.cbl_list, 644 BUS_DMA_NOWAIT | BUS_DMA_ZERO, &sc->cbl_map); 645 if (error) 646 goto fail; 647 648 error = bus_dmamap_load(sc->cbl_tag, sc->cbl_map, 649 sc->fxp_desc.cbl_list, FXP_TXCB_SZ, fxp_dma_map_addr, 650 &sc->fxp_desc.cbl_addr, 0); 651 if (error) { 652 device_printf(dev, "could not map DMA memory\n"); 653 goto fail; 654 } 655 656 error = bus_dma_tag_create(NULL, 4, 0, BUS_SPACE_MAXADDR_32BIT, 657 BUS_SPACE_MAXADDR, NULL, NULL, sizeof(struct fxp_cb_mcs), 1, 658 sizeof(struct fxp_cb_mcs), 0, busdma_lock_mutex, &Giant, 659 &sc->mcs_tag); 660 if (error) { 661 device_printf(dev, "could not allocate dma tag\n"); 662 goto fail; 663 } 664 665 error = bus_dmamem_alloc(sc->mcs_tag, (void **)&sc->mcsp, 666 BUS_DMA_NOWAIT, &sc->mcs_map); 667 if (error) 668 goto fail; 669 error = bus_dmamap_load(sc->mcs_tag, sc->mcs_map, sc->mcsp, 670 sizeof(struct fxp_cb_mcs), fxp_dma_map_addr, &sc->mcs_addr, 0); 671 if (error) { 672 device_printf(dev, "can't map the multicast setup command\n"); 673 goto fail; 674 } 675 676 /* 677 * Pre-allocate the TX DMA maps and setup the pointers to 678 * the TX command blocks. 679 */ 680 txp = sc->fxp_desc.tx_list; 681 tcbp = sc->fxp_desc.cbl_list; 682 for (i = 0; i < FXP_NTXCB; i++) { 683 txp[i].tx_cb = tcbp + i; 684 error = bus_dmamap_create(sc->fxp_mtag, 0, &txp[i].tx_map); 685 if (error) { 686 device_printf(dev, "can't create DMA map for TX\n"); 687 goto fail; 688 } 689 } 690 error = bus_dmamap_create(sc->fxp_mtag, 0, &sc->spare_map); 691 if (error) { 692 device_printf(dev, "can't create spare DMA map\n"); 693 goto fail; 694 } 695 696 /* 697 * Pre-allocate our receive buffers. 698 */ 699 sc->fxp_desc.rx_head = sc->fxp_desc.rx_tail = NULL; 700 for (i = 0; i < FXP_NRFABUFS; i++) { 701 rxp = &sc->fxp_desc.rx_list[i]; 702 error = bus_dmamap_create(sc->fxp_mtag, 0, &rxp->rx_map); 703 if (error) { 704 device_printf(dev, "can't create DMA map for RX\n"); 705 goto fail; 706 } 707 if (fxp_add_rfabuf(sc, rxp) != 0) { 708 error = ENOMEM; 709 goto fail; 710 } 711 } 712 713 /* 714 * Read MAC address. 715 */ 716 fxp_read_eeprom(sc, myea, 0, 3); 717 eaddr[0] = myea[0] & 0xff; 718 eaddr[1] = myea[0] >> 8; 719 eaddr[2] = myea[1] & 0xff; 720 eaddr[3] = myea[1] >> 8; 721 eaddr[4] = myea[2] & 0xff; 722 eaddr[5] = myea[2] >> 8; 723 if (bootverbose) { 724 device_printf(dev, "PCI IDs: %04x %04x %04x %04x %04x\n", 725 pci_get_vendor(dev), pci_get_device(dev), 726 pci_get_subvendor(dev), pci_get_subdevice(dev), 727 pci_get_revid(dev)); 728 fxp_read_eeprom(sc, &data, 10, 1); 729 device_printf(dev, "Dynamic Standby mode is %s\n", 730 data & 0x02 ? "enabled" : "disabled"); 731 } 732 733 /* 734 * If this is only a 10Mbps device, then there is no MII, and 735 * the PHY will use a serial interface instead. 736 * 737 * The Seeq 80c24 AutoDUPLEX(tm) Ethernet Interface Adapter 738 * doesn't have a programming interface of any sort. The 739 * media is sensed automatically based on how the link partner 740 * is configured. This is, in essence, manual configuration. 741 */ 742 if (sc->flags & FXP_FLAG_SERIAL_MEDIA) { 743 ifmedia_add(&sc->sc_media, IFM_ETHER|IFM_MANUAL, 0, NULL); 744 ifmedia_set(&sc->sc_media, IFM_ETHER|IFM_MANUAL); 745 } else { 746 if (mii_phy_probe(dev, &sc->miibus, fxp_ifmedia_upd, 747 fxp_ifmedia_sts)) { 748 device_printf(dev, "MII without any PHY!\n"); 749 error = ENXIO; 750 goto fail; 751 } 752 } 753 754 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 755 ifp->if_baudrate = 100000000; 756 ifp->if_init = fxp_init; 757 ifp->if_softc = sc; 758 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 759 ifp->if_ioctl = fxp_ioctl; 760 ifp->if_start = fxp_start; 761 ifp->if_watchdog = fxp_watchdog; 762 763 ifp->if_capabilities = ifp->if_capenable = 0; 764 765 /* Enable checksum offload for 82550 or better chips */ 766 if (sc->flags & FXP_FLAG_EXT_RFA) { 767 ifp->if_hwassist = FXP_CSUM_FEATURES; 768 ifp->if_capabilities |= IFCAP_HWCSUM; 769 ifp->if_capenable |= IFCAP_HWCSUM; 770 } 771 772 #ifdef DEVICE_POLLING 773 /* Inform the world we support polling. */ 774 ifp->if_capabilities |= IFCAP_POLLING; 775 ifp->if_capenable |= IFCAP_POLLING; 776 #endif 777 778 /* 779 * Attach the interface. 780 */ 781 ether_ifattach(ifp, eaddr); 782 783 /* 784 * Tell the upper layer(s) we support long frames. 785 * Must appear after the call to ether_ifattach() because 786 * ether_ifattach() sets ifi_hdrlen to the default value. 787 */ 788 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 789 ifp->if_capabilities |= IFCAP_VLAN_MTU; 790 ifp->if_capenable |= IFCAP_VLAN_MTU; /* the hw bits already set */ 791 792 /* 793 * Let the system queue as many packets as we have available 794 * TX descriptors. 795 */ 796 IFQ_SET_MAXLEN(&ifp->if_snd, FXP_NTXCB - 1); 797 ifp->if_snd.ifq_drv_maxlen = FXP_NTXCB - 1; 798 IFQ_SET_READY(&ifp->if_snd); 799 800 /* 801 * Hook our interrupt after all initialization is complete. 802 */ 803 error = bus_setup_intr(dev, sc->irq, INTR_TYPE_NET | INTR_MPSAFE, 804 fxp_intr, sc, &sc->ih); 805 if (error) { 806 device_printf(dev, "could not setup irq\n"); 807 ether_ifdetach(sc->ifp); 808 goto fail; 809 } 810 811 fail: 812 if (error) 813 fxp_release(sc); 814 return (error); 815 } 816 817 /* 818 * Release all resources. The softc lock should not be held and the 819 * interrupt should already be torn down. 820 */ 821 static void 822 fxp_release(struct fxp_softc *sc) 823 { 824 struct fxp_rx *rxp; 825 struct fxp_tx *txp; 826 int i; 827 828 FXP_LOCK_ASSERT(sc, MA_NOTOWNED); 829 KASSERT(sc->ih == NULL, 830 ("fxp_release() called with intr handle still active")); 831 if (sc->miibus) 832 device_delete_child(sc->dev, sc->miibus); 833 bus_generic_detach(sc->dev); 834 ifmedia_removeall(&sc->sc_media); 835 if (sc->fxp_desc.cbl_list) { 836 bus_dmamap_unload(sc->cbl_tag, sc->cbl_map); 837 bus_dmamem_free(sc->cbl_tag, sc->fxp_desc.cbl_list, 838 sc->cbl_map); 839 } 840 if (sc->fxp_stats) { 841 bus_dmamap_unload(sc->fxp_stag, sc->fxp_smap); 842 bus_dmamem_free(sc->fxp_stag, sc->fxp_stats, sc->fxp_smap); 843 } 844 if (sc->mcsp) { 845 bus_dmamap_unload(sc->mcs_tag, sc->mcs_map); 846 bus_dmamem_free(sc->mcs_tag, sc->mcsp, sc->mcs_map); 847 } 848 if (sc->irq) 849 bus_release_resource(sc->dev, SYS_RES_IRQ, 0, sc->irq); 850 if (sc->mem) 851 bus_release_resource(sc->dev, sc->rtp, sc->rgd, sc->mem); 852 if (sc->fxp_mtag) { 853 for (i = 0; i < FXP_NRFABUFS; i++) { 854 rxp = &sc->fxp_desc.rx_list[i]; 855 if (rxp->rx_mbuf != NULL) { 856 bus_dmamap_sync(sc->fxp_mtag, rxp->rx_map, 857 BUS_DMASYNC_POSTREAD); 858 bus_dmamap_unload(sc->fxp_mtag, rxp->rx_map); 859 m_freem(rxp->rx_mbuf); 860 } 861 bus_dmamap_destroy(sc->fxp_mtag, rxp->rx_map); 862 } 863 bus_dmamap_destroy(sc->fxp_mtag, sc->spare_map); 864 for (i = 0; i < FXP_NTXCB; i++) { 865 txp = &sc->fxp_desc.tx_list[i]; 866 if (txp->tx_mbuf != NULL) { 867 bus_dmamap_sync(sc->fxp_mtag, txp->tx_map, 868 BUS_DMASYNC_POSTWRITE); 869 bus_dmamap_unload(sc->fxp_mtag, txp->tx_map); 870 m_freem(txp->tx_mbuf); 871 } 872 bus_dmamap_destroy(sc->fxp_mtag, txp->tx_map); 873 } 874 bus_dma_tag_destroy(sc->fxp_mtag); 875 } 876 if (sc->fxp_stag) 877 bus_dma_tag_destroy(sc->fxp_stag); 878 if (sc->cbl_tag) 879 bus_dma_tag_destroy(sc->cbl_tag); 880 if (sc->mcs_tag) 881 bus_dma_tag_destroy(sc->mcs_tag); 882 if (sc->ifp) 883 if_free(sc->ifp); 884 885 mtx_destroy(&sc->sc_mtx); 886 } 887 888 /* 889 * Detach interface. 890 */ 891 static int 892 fxp_detach(device_t dev) 893 { 894 struct fxp_softc *sc = device_get_softc(dev); 895 896 FXP_LOCK(sc); 897 sc->suspended = 1; /* Do same thing as we do for suspend */ 898 /* 899 * Stop DMA and drop transmit queue, but disable interrupts first. 900 */ 901 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE); 902 fxp_stop(sc); 903 FXP_UNLOCK(sc); 904 callout_drain(&sc->stat_ch); 905 906 /* 907 * Close down routes etc. 908 */ 909 ether_ifdetach(sc->ifp); 910 911 /* 912 * Unhook interrupt before dropping lock. This is to prevent 913 * races with fxp_intr(). 914 */ 915 bus_teardown_intr(sc->dev, sc->irq, sc->ih); 916 sc->ih = NULL; 917 918 /* Release our allocated resources. */ 919 fxp_release(sc); 920 return (0); 921 } 922 923 /* 924 * Device shutdown routine. Called at system shutdown after sync. The 925 * main purpose of this routine is to shut off receiver DMA so that 926 * kernel memory doesn't get clobbered during warmboot. 927 */ 928 static int 929 fxp_shutdown(device_t dev) 930 { 931 struct fxp_softc *sc = device_get_softc(dev); 932 933 /* 934 * Make sure that DMA is disabled prior to reboot. Not doing 935 * do could allow DMA to corrupt kernel memory during the 936 * reboot before the driver initializes. 937 */ 938 FXP_LOCK(sc); 939 fxp_stop(sc); 940 FXP_UNLOCK(sc); 941 return (0); 942 } 943 944 /* 945 * Device suspend routine. Stop the interface and save some PCI 946 * settings in case the BIOS doesn't restore them properly on 947 * resume. 948 */ 949 static int 950 fxp_suspend(device_t dev) 951 { 952 struct fxp_softc *sc = device_get_softc(dev); 953 954 FXP_LOCK(sc); 955 956 fxp_stop(sc); 957 958 sc->suspended = 1; 959 960 FXP_UNLOCK(sc); 961 return (0); 962 } 963 964 /* 965 * Device resume routine. re-enable busmastering, and restart the interface if 966 * appropriate. 967 */ 968 static int 969 fxp_resume(device_t dev) 970 { 971 struct fxp_softc *sc = device_get_softc(dev); 972 struct ifnet *ifp = sc->ifp; 973 974 FXP_LOCK(sc); 975 976 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET); 977 DELAY(10); 978 979 /* reinitialize interface if necessary */ 980 if (ifp->if_flags & IFF_UP) 981 fxp_init_body(sc); 982 983 sc->suspended = 0; 984 985 FXP_UNLOCK(sc); 986 return (0); 987 } 988 989 static void 990 fxp_eeprom_shiftin(struct fxp_softc *sc, int data, int length) 991 { 992 uint16_t reg; 993 int x; 994 995 /* 996 * Shift in data. 997 */ 998 for (x = 1 << (length - 1); x; x >>= 1) { 999 if (data & x) 1000 reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI; 1001 else 1002 reg = FXP_EEPROM_EECS; 1003 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 1004 DELAY(1); 1005 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK); 1006 DELAY(1); 1007 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 1008 DELAY(1); 1009 } 1010 } 1011 1012 /* 1013 * Read from the serial EEPROM. Basically, you manually shift in 1014 * the read opcode (one bit at a time) and then shift in the address, 1015 * and then you shift out the data (all of this one bit at a time). 1016 * The word size is 16 bits, so you have to provide the address for 1017 * every 16 bits of data. 1018 */ 1019 static uint16_t 1020 fxp_eeprom_getword(struct fxp_softc *sc, int offset, int autosize) 1021 { 1022 uint16_t reg, data; 1023 int x; 1024 1025 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 1026 /* 1027 * Shift in read opcode. 1028 */ 1029 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_READ, 3); 1030 /* 1031 * Shift in address. 1032 */ 1033 data = 0; 1034 for (x = 1 << (sc->eeprom_size - 1); x; x >>= 1) { 1035 if (offset & x) 1036 reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI; 1037 else 1038 reg = FXP_EEPROM_EECS; 1039 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 1040 DELAY(1); 1041 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK); 1042 DELAY(1); 1043 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 1044 DELAY(1); 1045 reg = CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO; 1046 data++; 1047 if (autosize && reg == 0) { 1048 sc->eeprom_size = data; 1049 break; 1050 } 1051 } 1052 /* 1053 * Shift out data. 1054 */ 1055 data = 0; 1056 reg = FXP_EEPROM_EECS; 1057 for (x = 1 << 15; x; x >>= 1) { 1058 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK); 1059 DELAY(1); 1060 if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO) 1061 data |= x; 1062 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 1063 DELAY(1); 1064 } 1065 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 1066 DELAY(1); 1067 1068 return (data); 1069 } 1070 1071 static void 1072 fxp_eeprom_putword(struct fxp_softc *sc, int offset, uint16_t data) 1073 { 1074 int i; 1075 1076 /* 1077 * Erase/write enable. 1078 */ 1079 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 1080 fxp_eeprom_shiftin(sc, 0x4, 3); 1081 fxp_eeprom_shiftin(sc, 0x03 << (sc->eeprom_size - 2), sc->eeprom_size); 1082 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 1083 DELAY(1); 1084 /* 1085 * Shift in write opcode, address, data. 1086 */ 1087 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 1088 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_WRITE, 3); 1089 fxp_eeprom_shiftin(sc, offset, sc->eeprom_size); 1090 fxp_eeprom_shiftin(sc, data, 16); 1091 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 1092 DELAY(1); 1093 /* 1094 * Wait for EEPROM to finish up. 1095 */ 1096 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 1097 DELAY(1); 1098 for (i = 0; i < 1000; i++) { 1099 if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO) 1100 break; 1101 DELAY(50); 1102 } 1103 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 1104 DELAY(1); 1105 /* 1106 * Erase/write disable. 1107 */ 1108 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 1109 fxp_eeprom_shiftin(sc, 0x4, 3); 1110 fxp_eeprom_shiftin(sc, 0, sc->eeprom_size); 1111 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 1112 DELAY(1); 1113 } 1114 1115 /* 1116 * From NetBSD: 1117 * 1118 * Figure out EEPROM size. 1119 * 1120 * 559's can have either 64-word or 256-word EEPROMs, the 558 1121 * datasheet only talks about 64-word EEPROMs, and the 557 datasheet 1122 * talks about the existance of 16 to 256 word EEPROMs. 1123 * 1124 * The only known sizes are 64 and 256, where the 256 version is used 1125 * by CardBus cards to store CIS information. 1126 * 1127 * The address is shifted in msb-to-lsb, and after the last 1128 * address-bit the EEPROM is supposed to output a `dummy zero' bit, 1129 * after which follows the actual data. We try to detect this zero, by 1130 * probing the data-out bit in the EEPROM control register just after 1131 * having shifted in a bit. If the bit is zero, we assume we've 1132 * shifted enough address bits. The data-out should be tri-state, 1133 * before this, which should translate to a logical one. 1134 */ 1135 static void 1136 fxp_autosize_eeprom(struct fxp_softc *sc) 1137 { 1138 1139 /* guess maximum size of 256 words */ 1140 sc->eeprom_size = 8; 1141 1142 /* autosize */ 1143 (void) fxp_eeprom_getword(sc, 0, 1); 1144 } 1145 1146 static void 1147 fxp_read_eeprom(struct fxp_softc *sc, u_short *data, int offset, int words) 1148 { 1149 int i; 1150 1151 for (i = 0; i < words; i++) 1152 data[i] = fxp_eeprom_getword(sc, offset + i, 0); 1153 } 1154 1155 static void 1156 fxp_write_eeprom(struct fxp_softc *sc, u_short *data, int offset, int words) 1157 { 1158 int i; 1159 1160 for (i = 0; i < words; i++) 1161 fxp_eeprom_putword(sc, offset + i, data[i]); 1162 } 1163 1164 /* 1165 * Grab the softc lock and call the real fxp_start_body() routine 1166 */ 1167 static void 1168 fxp_start(struct ifnet *ifp) 1169 { 1170 struct fxp_softc *sc = ifp->if_softc; 1171 1172 FXP_LOCK(sc); 1173 fxp_start_body(ifp); 1174 FXP_UNLOCK(sc); 1175 } 1176 1177 /* 1178 * Start packet transmission on the interface. 1179 * This routine must be called with the softc lock held, and is an 1180 * internal entry point only. 1181 */ 1182 static void 1183 fxp_start_body(struct ifnet *ifp) 1184 { 1185 struct fxp_softc *sc = ifp->if_softc; 1186 struct mbuf *mb_head; 1187 int error, txqueued; 1188 1189 FXP_LOCK_ASSERT(sc, MA_OWNED); 1190 1191 /* 1192 * See if we need to suspend xmit until the multicast filter 1193 * has been reprogrammed (which can only be done at the head 1194 * of the command chain). 1195 */ 1196 if (sc->need_mcsetup) 1197 return; 1198 1199 /* 1200 * We're finished if there is nothing more to add to the list or if 1201 * we're all filled up with buffers to transmit. 1202 * NOTE: One TxCB is reserved to guarantee that fxp_mc_setup() can add 1203 * a NOP command when needed. 1204 */ 1205 txqueued = 0; 1206 while (!IFQ_DRV_IS_EMPTY(&ifp->if_snd) && 1207 sc->tx_queued < FXP_NTXCB - 1) { 1208 1209 /* 1210 * Grab a packet to transmit. 1211 */ 1212 IFQ_DRV_DEQUEUE(&ifp->if_snd, mb_head); 1213 if (mb_head == NULL) 1214 break; 1215 1216 error = fxp_encap(sc, mb_head); 1217 if (error) 1218 break; 1219 txqueued = 1; 1220 } 1221 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE); 1222 1223 /* 1224 * We're finished. If we added to the list, issue a RESUME to get DMA 1225 * going again if suspended. 1226 */ 1227 if (txqueued) { 1228 fxp_scb_wait(sc); 1229 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_RESUME); 1230 } 1231 } 1232 1233 static int 1234 fxp_encap(struct fxp_softc *sc, struct mbuf *m_head) 1235 { 1236 struct ifnet *ifp; 1237 struct mbuf *m; 1238 struct fxp_tx *txp; 1239 struct fxp_cb_tx *cbp; 1240 bus_dma_segment_t segs[FXP_NTXSEG]; 1241 int chainlen, error, i, nseg; 1242 1243 FXP_LOCK_ASSERT(sc, MA_OWNED); 1244 ifp = sc->ifp; 1245 1246 /* 1247 * Get pointer to next available tx desc. 1248 */ 1249 txp = sc->fxp_desc.tx_last->tx_next; 1250 1251 /* 1252 * A note in Appendix B of the Intel 8255x 10/100 Mbps 1253 * Ethernet Controller Family Open Source Software 1254 * Developer Manual says: 1255 * Using software parsing is only allowed with legal 1256 * TCP/IP or UDP/IP packets. 1257 * ... 1258 * For all other datagrams, hardware parsing must 1259 * be used. 1260 * Software parsing appears to truncate ICMP and 1261 * fragmented UDP packets that contain one to three 1262 * bytes in the second (and final) mbuf of the packet. 1263 */ 1264 if (sc->flags & FXP_FLAG_EXT_RFA) 1265 txp->tx_cb->ipcb_ip_activation_high = 1266 FXP_IPCB_HARDWAREPARSING_ENABLE; 1267 1268 /* 1269 * Deal with TCP/IP checksum offload. Note that 1270 * in order for TCP checksum offload to work, 1271 * the pseudo header checksum must have already 1272 * been computed and stored in the checksum field 1273 * in the TCP header. The stack should have 1274 * already done this for us. 1275 */ 1276 if (m_head->m_pkthdr.csum_flags) { 1277 if (m_head->m_pkthdr.csum_flags & CSUM_DELAY_DATA) { 1278 txp->tx_cb->ipcb_ip_schedule = 1279 FXP_IPCB_TCPUDP_CHECKSUM_ENABLE; 1280 if (m_head->m_pkthdr.csum_flags & CSUM_TCP) 1281 txp->tx_cb->ipcb_ip_schedule |= 1282 FXP_IPCB_TCP_PACKET; 1283 } 1284 1285 #ifdef FXP_IP_CSUM_WAR 1286 /* 1287 * XXX The 82550 chip appears to have trouble 1288 * dealing with IP header checksums in very small 1289 * datagrams, namely fragments from 1 to 3 bytes 1290 * in size. For example, say you want to transmit 1291 * a UDP packet of 1473 bytes. The packet will be 1292 * fragmented over two IP datagrams, the latter 1293 * containing only one byte of data. The 82550 will 1294 * botch the header checksum on the 1-byte fragment. 1295 * As long as the datagram contains 4 or more bytes 1296 * of data, you're ok. 1297 * 1298 * The following code attempts to work around this 1299 * problem: if the datagram is less than 38 bytes 1300 * in size (14 bytes ether header, 20 bytes IP header, 1301 * plus 4 bytes of data), we punt and compute the IP 1302 * header checksum by hand. This workaround doesn't 1303 * work very well, however, since it can be fooled 1304 * by things like VLAN tags and IP options that make 1305 * the header sizes/offsets vary. 1306 */ 1307 1308 if (m_head->m_pkthdr.csum_flags & CSUM_IP) { 1309 if (m_head->m_pkthdr.len < 38) { 1310 struct ip *ip; 1311 m_head->m_data += ETHER_HDR_LEN; 1312 ip = mtod(mb_head, struct ip *); 1313 ip->ip_sum = in_cksum(mb_head, ip->ip_hl << 2); 1314 m_head->m_data -= ETHER_HDR_LEN; 1315 } else { 1316 txp->tx_cb->ipcb_ip_activation_high = 1317 FXP_IPCB_HARDWAREPARSING_ENABLE; 1318 txp->tx_cb->ipcb_ip_schedule |= 1319 FXP_IPCB_IP_CHECKSUM_ENABLE; 1320 } 1321 } 1322 #endif 1323 } 1324 1325 chainlen = 0; 1326 for (m = m_head; m != NULL && chainlen <= sc->maxtxseg; m = m->m_next) 1327 chainlen++; 1328 if (chainlen > sc->maxtxseg) { 1329 struct mbuf *mn; 1330 1331 /* 1332 * We ran out of segments. We have to recopy this 1333 * mbuf chain first. Bail out if we can't get the 1334 * new buffers. 1335 */ 1336 mn = m_defrag(m_head, M_DONTWAIT); 1337 if (mn == NULL) { 1338 m_freem(m_head); 1339 return (-1); 1340 } else { 1341 m_head = mn; 1342 } 1343 } 1344 1345 /* 1346 * Go through each of the mbufs in the chain and initialize 1347 * the transmit buffer descriptors with the physical address 1348 * and size of the mbuf. 1349 */ 1350 error = bus_dmamap_load_mbuf_sg(sc->fxp_mtag, txp->tx_map, 1351 m_head, segs, &nseg, 0); 1352 if (error) { 1353 device_printf(sc->dev, "can't map mbuf (error %d)\n", error); 1354 m_freem(m_head); 1355 return (-1); 1356 } 1357 1358 KASSERT(nseg <= sc->maxtxseg, ("too many DMA segments")); 1359 1360 cbp = txp->tx_cb; 1361 for (i = 0; i < nseg; i++) { 1362 KASSERT(segs[i].ds_len <= MCLBYTES, ("segment size too large")); 1363 /* 1364 * If this is an 82550/82551, then we're using extended 1365 * TxCBs _and_ we're using checksum offload. This means 1366 * that the TxCB is really an IPCB. One major difference 1367 * between the two is that with plain extended TxCBs, 1368 * the bottom half of the TxCB contains two entries from 1369 * the TBD array, whereas IPCBs contain just one entry: 1370 * one entry (8 bytes) has been sacrificed for the TCP/IP 1371 * checksum offload control bits. So to make things work 1372 * right, we have to start filling in the TBD array 1373 * starting from a different place depending on whether 1374 * the chip is an 82550/82551 or not. 1375 */ 1376 if (sc->flags & FXP_FLAG_EXT_RFA) { 1377 cbp->tbd[i + 1].tb_addr = htole32(segs[i].ds_addr); 1378 cbp->tbd[i + 1].tb_size = htole32(segs[i].ds_len); 1379 } else { 1380 cbp->tbd[i].tb_addr = htole32(segs[i].ds_addr); 1381 cbp->tbd[i].tb_size = htole32(segs[i].ds_len); 1382 } 1383 } 1384 cbp->tbd_number = nseg; 1385 1386 bus_dmamap_sync(sc->fxp_mtag, txp->tx_map, BUS_DMASYNC_PREWRITE); 1387 txp->tx_mbuf = m_head; 1388 txp->tx_cb->cb_status = 0; 1389 txp->tx_cb->byte_count = 0; 1390 if (sc->tx_queued != FXP_CXINT_THRESH - 1) { 1391 txp->tx_cb->cb_command = 1392 htole16(sc->tx_cmd | FXP_CB_COMMAND_SF | 1393 FXP_CB_COMMAND_S); 1394 } else { 1395 txp->tx_cb->cb_command = 1396 htole16(sc->tx_cmd | FXP_CB_COMMAND_SF | 1397 FXP_CB_COMMAND_S | FXP_CB_COMMAND_I); 1398 /* 1399 * Set a 5 second timer just in case we don't hear 1400 * from the card again. 1401 */ 1402 ifp->if_timer = 5; 1403 } 1404 txp->tx_cb->tx_threshold = tx_threshold; 1405 1406 /* 1407 * Advance the end of list forward. 1408 */ 1409 1410 #ifdef __alpha__ 1411 /* 1412 * On platforms which can't access memory in 16-bit 1413 * granularities, we must prevent the card from DMA'ing 1414 * up the status while we update the command field. 1415 * This could cause us to overwrite the completion status. 1416 * XXX This is probably bogus and we're _not_ looking 1417 * for atomicity here. 1418 */ 1419 atomic_clear_16(&sc->fxp_desc.tx_last->tx_cb->cb_command, 1420 htole16(FXP_CB_COMMAND_S)); 1421 #else 1422 sc->fxp_desc.tx_last->tx_cb->cb_command &= htole16(~FXP_CB_COMMAND_S); 1423 #endif /*__alpha__*/ 1424 sc->fxp_desc.tx_last = txp; 1425 1426 /* 1427 * Advance the beginning of the list forward if there are 1428 * no other packets queued (when nothing is queued, tx_first 1429 * sits on the last TxCB that was sent out). 1430 */ 1431 if (sc->tx_queued == 0) 1432 sc->fxp_desc.tx_first = txp; 1433 1434 sc->tx_queued++; 1435 1436 /* 1437 * Pass packet to bpf if there is a listener. 1438 */ 1439 BPF_MTAP(ifp, m_head); 1440 return (0); 1441 } 1442 1443 #ifdef DEVICE_POLLING 1444 static poll_handler_t fxp_poll; 1445 1446 static void 1447 fxp_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 1448 { 1449 struct fxp_softc *sc = ifp->if_softc; 1450 uint8_t statack; 1451 1452 FXP_LOCK(sc); 1453 if (!(ifp->if_capenable & IFCAP_POLLING)) { 1454 ether_poll_deregister(ifp); 1455 cmd = POLL_DEREGISTER; 1456 } 1457 if (cmd == POLL_DEREGISTER) { /* final call, enable interrupts */ 1458 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, 0); 1459 FXP_UNLOCK(sc); 1460 return; 1461 } 1462 statack = FXP_SCB_STATACK_CXTNO | FXP_SCB_STATACK_CNA | 1463 FXP_SCB_STATACK_FR; 1464 if (cmd == POLL_AND_CHECK_STATUS) { 1465 uint8_t tmp; 1466 1467 tmp = CSR_READ_1(sc, FXP_CSR_SCB_STATACK); 1468 if (tmp == 0xff || tmp == 0) { 1469 FXP_UNLOCK(sc); 1470 return; /* nothing to do */ 1471 } 1472 tmp &= ~statack; 1473 /* ack what we can */ 1474 if (tmp != 0) 1475 CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, tmp); 1476 statack |= tmp; 1477 } 1478 fxp_intr_body(sc, ifp, statack, count); 1479 FXP_UNLOCK(sc); 1480 } 1481 #endif /* DEVICE_POLLING */ 1482 1483 /* 1484 * Process interface interrupts. 1485 */ 1486 static void 1487 fxp_intr(void *xsc) 1488 { 1489 struct fxp_softc *sc = xsc; 1490 struct ifnet *ifp = sc->ifp; 1491 uint8_t statack; 1492 1493 FXP_LOCK(sc); 1494 if (sc->suspended) { 1495 FXP_UNLOCK(sc); 1496 return; 1497 } 1498 1499 #ifdef DEVICE_POLLING 1500 if (ifp->if_flags & IFF_POLLING) { 1501 FXP_UNLOCK(sc); 1502 return; 1503 } 1504 if ((ifp->if_capenable & IFCAP_POLLING) && 1505 ether_poll_register(fxp_poll, ifp)) { 1506 /* disable interrupts */ 1507 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE); 1508 FXP_UNLOCK(sc); 1509 fxp_poll(ifp, 0, 1); 1510 return; 1511 } 1512 #endif 1513 while ((statack = CSR_READ_1(sc, FXP_CSR_SCB_STATACK)) != 0) { 1514 /* 1515 * It should not be possible to have all bits set; the 1516 * FXP_SCB_INTR_SWI bit always returns 0 on a read. If 1517 * all bits are set, this may indicate that the card has 1518 * been physically ejected, so ignore it. 1519 */ 1520 if (statack == 0xff) { 1521 FXP_UNLOCK(sc); 1522 return; 1523 } 1524 1525 /* 1526 * First ACK all the interrupts in this pass. 1527 */ 1528 CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, statack); 1529 fxp_intr_body(sc, ifp, statack, -1); 1530 } 1531 FXP_UNLOCK(sc); 1532 } 1533 1534 static void 1535 fxp_txeof(struct fxp_softc *sc) 1536 { 1537 struct fxp_tx *txp; 1538 1539 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREREAD); 1540 for (txp = sc->fxp_desc.tx_first; sc->tx_queued && 1541 (le16toh(txp->tx_cb->cb_status) & FXP_CB_STATUS_C) != 0; 1542 txp = txp->tx_next) { 1543 if (txp->tx_mbuf != NULL) { 1544 bus_dmamap_sync(sc->fxp_mtag, txp->tx_map, 1545 BUS_DMASYNC_POSTWRITE); 1546 bus_dmamap_unload(sc->fxp_mtag, txp->tx_map); 1547 m_freem(txp->tx_mbuf); 1548 txp->tx_mbuf = NULL; 1549 /* clear this to reset csum offload bits */ 1550 txp->tx_cb->tbd[0].tb_addr = 0; 1551 } 1552 sc->tx_queued--; 1553 } 1554 sc->fxp_desc.tx_first = txp; 1555 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE); 1556 } 1557 1558 static void 1559 fxp_intr_body(struct fxp_softc *sc, struct ifnet *ifp, uint8_t statack, 1560 int count) 1561 { 1562 struct mbuf *m; 1563 struct fxp_rx *rxp; 1564 struct fxp_rfa *rfa; 1565 int rnr = (statack & FXP_SCB_STATACK_RNR) ? 1 : 0; 1566 int fxp_rc = 0; 1567 1568 FXP_LOCK_ASSERT(sc, MA_OWNED); 1569 if (rnr) 1570 sc->rnr++; 1571 #ifdef DEVICE_POLLING 1572 /* Pick up a deferred RNR condition if `count' ran out last time. */ 1573 if (sc->flags & FXP_FLAG_DEFERRED_RNR) { 1574 sc->flags &= ~FXP_FLAG_DEFERRED_RNR; 1575 rnr = 1; 1576 } 1577 #endif 1578 1579 /* 1580 * Free any finished transmit mbuf chains. 1581 * 1582 * Handle the CNA event likt a CXTNO event. It used to 1583 * be that this event (control unit not ready) was not 1584 * encountered, but it is now with the SMPng modifications. 1585 * The exact sequence of events that occur when the interface 1586 * is brought up are different now, and if this event 1587 * goes unhandled, the configuration/rxfilter setup sequence 1588 * can stall for several seconds. The result is that no 1589 * packets go out onto the wire for about 5 to 10 seconds 1590 * after the interface is ifconfig'ed for the first time. 1591 */ 1592 if (statack & (FXP_SCB_STATACK_CXTNO | FXP_SCB_STATACK_CNA)) { 1593 fxp_txeof(sc); 1594 1595 ifp->if_timer = 0; 1596 if (sc->tx_queued == 0) { 1597 if (sc->need_mcsetup) 1598 fxp_mc_setup(sc); 1599 } 1600 /* 1601 * Try to start more packets transmitting. 1602 */ 1603 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1604 fxp_start_body(ifp); 1605 } 1606 1607 /* 1608 * Just return if nothing happened on the receive side. 1609 */ 1610 if (!rnr && (statack & FXP_SCB_STATACK_FR) == 0) 1611 return; 1612 1613 /* 1614 * Process receiver interrupts. If a no-resource (RNR) 1615 * condition exists, get whatever packets we can and 1616 * re-start the receiver. 1617 * 1618 * When using polling, we do not process the list to completion, 1619 * so when we get an RNR interrupt we must defer the restart 1620 * until we hit the last buffer with the C bit set. 1621 * If we run out of cycles and rfa_headm has the C bit set, 1622 * record the pending RNR in the FXP_FLAG_DEFERRED_RNR flag so 1623 * that the info will be used in the subsequent polling cycle. 1624 */ 1625 for (;;) { 1626 rxp = sc->fxp_desc.rx_head; 1627 m = rxp->rx_mbuf; 1628 rfa = (struct fxp_rfa *)(m->m_ext.ext_buf + 1629 RFA_ALIGNMENT_FUDGE); 1630 bus_dmamap_sync(sc->fxp_mtag, rxp->rx_map, 1631 BUS_DMASYNC_POSTREAD); 1632 1633 #ifdef DEVICE_POLLING /* loop at most count times if count >=0 */ 1634 if (count >= 0 && count-- == 0) { 1635 if (rnr) { 1636 /* Defer RNR processing until the next time. */ 1637 sc->flags |= FXP_FLAG_DEFERRED_RNR; 1638 rnr = 0; 1639 } 1640 break; 1641 } 1642 #endif /* DEVICE_POLLING */ 1643 1644 if ((le16toh(rfa->rfa_status) & FXP_RFA_STATUS_C) == 0) 1645 break; 1646 1647 /* 1648 * Advance head forward. 1649 */ 1650 sc->fxp_desc.rx_head = rxp->rx_next; 1651 1652 /* 1653 * Add a new buffer to the receive chain. 1654 * If this fails, the old buffer is recycled 1655 * instead. 1656 */ 1657 fxp_rc = fxp_add_rfabuf(sc, rxp); 1658 if (fxp_rc == 0) { 1659 int total_len; 1660 1661 /* 1662 * Fetch packet length (the top 2 bits of 1663 * actual_size are flags set by the controller 1664 * upon completion), and drop the packet in case 1665 * of bogus length or CRC errors. 1666 */ 1667 total_len = le16toh(rfa->actual_size) & 0x3fff; 1668 if (total_len < sizeof(struct ether_header) || 1669 total_len > MCLBYTES - RFA_ALIGNMENT_FUDGE - 1670 sc->rfa_size || 1671 le16toh(rfa->rfa_status) & FXP_RFA_STATUS_CRC) { 1672 m_freem(m); 1673 continue; 1674 } 1675 1676 /* Do IP checksum checking. */ 1677 if (le16toh(rfa->rfa_status) & FXP_RFA_STATUS_PARSE) { 1678 if (rfa->rfax_csum_sts & 1679 FXP_RFDX_CS_IP_CSUM_BIT_VALID) 1680 m->m_pkthdr.csum_flags |= 1681 CSUM_IP_CHECKED; 1682 if (rfa->rfax_csum_sts & 1683 FXP_RFDX_CS_IP_CSUM_VALID) 1684 m->m_pkthdr.csum_flags |= 1685 CSUM_IP_VALID; 1686 if ((rfa->rfax_csum_sts & 1687 FXP_RFDX_CS_TCPUDP_CSUM_BIT_VALID) && 1688 (rfa->rfax_csum_sts & 1689 FXP_RFDX_CS_TCPUDP_CSUM_VALID)) { 1690 m->m_pkthdr.csum_flags |= 1691 CSUM_DATA_VALID|CSUM_PSEUDO_HDR; 1692 m->m_pkthdr.csum_data = 0xffff; 1693 } 1694 } 1695 1696 m->m_pkthdr.len = m->m_len = total_len; 1697 m->m_pkthdr.rcvif = ifp; 1698 1699 /* 1700 * Drop locks before calling if_input() since it 1701 * may re-enter fxp_start() in the netisr case. 1702 * This would result in a lock reversal. Better 1703 * performance might be obtained by chaining all 1704 * packets received, dropping the lock, and then 1705 * calling if_input() on each one. 1706 */ 1707 FXP_UNLOCK(sc); 1708 (*ifp->if_input)(ifp, m); 1709 FXP_LOCK(sc); 1710 } else if (fxp_rc == ENOBUFS) { 1711 rnr = 0; 1712 break; 1713 } 1714 } 1715 if (rnr) { 1716 fxp_scb_wait(sc); 1717 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 1718 sc->fxp_desc.rx_head->rx_addr); 1719 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_START); 1720 } 1721 } 1722 1723 /* 1724 * Update packet in/out/collision statistics. The i82557 doesn't 1725 * allow you to access these counters without doing a fairly 1726 * expensive DMA to get _all_ of the statistics it maintains, so 1727 * we do this operation here only once per second. The statistics 1728 * counters in the kernel are updated from the previous dump-stats 1729 * DMA and then a new dump-stats DMA is started. The on-chip 1730 * counters are zeroed when the DMA completes. If we can't start 1731 * the DMA immediately, we don't wait - we just prepare to read 1732 * them again next time. 1733 */ 1734 static void 1735 fxp_tick(void *xsc) 1736 { 1737 struct fxp_softc *sc = xsc; 1738 struct ifnet *ifp = sc->ifp; 1739 struct fxp_stats *sp = sc->fxp_stats; 1740 1741 FXP_LOCK_ASSERT(sc, MA_OWNED); 1742 bus_dmamap_sync(sc->fxp_stag, sc->fxp_smap, BUS_DMASYNC_POSTREAD); 1743 ifp->if_opackets += le32toh(sp->tx_good); 1744 ifp->if_collisions += le32toh(sp->tx_total_collisions); 1745 if (sp->rx_good) { 1746 ifp->if_ipackets += le32toh(sp->rx_good); 1747 sc->rx_idle_secs = 0; 1748 } else { 1749 /* 1750 * Receiver's been idle for another second. 1751 */ 1752 sc->rx_idle_secs++; 1753 } 1754 ifp->if_ierrors += 1755 le32toh(sp->rx_crc_errors) + 1756 le32toh(sp->rx_alignment_errors) + 1757 le32toh(sp->rx_rnr_errors) + 1758 le32toh(sp->rx_overrun_errors); 1759 /* 1760 * If any transmit underruns occured, bump up the transmit 1761 * threshold by another 512 bytes (64 * 8). 1762 */ 1763 if (sp->tx_underruns) { 1764 ifp->if_oerrors += le32toh(sp->tx_underruns); 1765 if (tx_threshold < 192) 1766 tx_threshold += 64; 1767 } 1768 1769 /* 1770 * Release any xmit buffers that have completed DMA. This isn't 1771 * strictly necessary to do here, but it's advantagous for mbufs 1772 * with external storage to be released in a timely manner rather 1773 * than being defered for a potentially long time. This limits 1774 * the delay to a maximum of one second. 1775 */ 1776 fxp_txeof(sc); 1777 1778 /* 1779 * If we haven't received any packets in FXP_MAC_RX_IDLE seconds, 1780 * then assume the receiver has locked up and attempt to clear 1781 * the condition by reprogramming the multicast filter. This is 1782 * a work-around for a bug in the 82557 where the receiver locks 1783 * up if it gets certain types of garbage in the syncronization 1784 * bits prior to the packet header. This bug is supposed to only 1785 * occur in 10Mbps mode, but has been seen to occur in 100Mbps 1786 * mode as well (perhaps due to a 10/100 speed transition). 1787 */ 1788 if (sc->rx_idle_secs > FXP_MAX_RX_IDLE) { 1789 sc->rx_idle_secs = 0; 1790 fxp_mc_setup(sc); 1791 } 1792 /* 1793 * If there is no pending command, start another stats 1794 * dump. Otherwise punt for now. 1795 */ 1796 if (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) == 0) { 1797 /* 1798 * Start another stats dump. 1799 */ 1800 bus_dmamap_sync(sc->fxp_stag, sc->fxp_smap, 1801 BUS_DMASYNC_PREREAD); 1802 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_DUMPRESET); 1803 } else { 1804 /* 1805 * A previous command is still waiting to be accepted. 1806 * Just zero our copy of the stats and wait for the 1807 * next timer event to update them. 1808 */ 1809 sp->tx_good = 0; 1810 sp->tx_underruns = 0; 1811 sp->tx_total_collisions = 0; 1812 1813 sp->rx_good = 0; 1814 sp->rx_crc_errors = 0; 1815 sp->rx_alignment_errors = 0; 1816 sp->rx_rnr_errors = 0; 1817 sp->rx_overrun_errors = 0; 1818 } 1819 if (sc->miibus != NULL) 1820 mii_tick(device_get_softc(sc->miibus)); 1821 1822 /* 1823 * Schedule another timeout one second from now. 1824 */ 1825 callout_reset(&sc->stat_ch, hz, fxp_tick, sc); 1826 } 1827 1828 /* 1829 * Stop the interface. Cancels the statistics updater and resets 1830 * the interface. 1831 */ 1832 static void 1833 fxp_stop(struct fxp_softc *sc) 1834 { 1835 struct ifnet *ifp = sc->ifp; 1836 struct fxp_tx *txp; 1837 int i; 1838 1839 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 1840 ifp->if_timer = 0; 1841 1842 #ifdef DEVICE_POLLING 1843 ether_poll_deregister(ifp); 1844 #endif 1845 /* 1846 * Cancel stats updater. 1847 */ 1848 callout_stop(&sc->stat_ch); 1849 1850 /* 1851 * Issue software reset, which also unloads the microcode. 1852 */ 1853 sc->flags &= ~FXP_FLAG_UCODE; 1854 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SOFTWARE_RESET); 1855 DELAY(50); 1856 1857 /* 1858 * Release any xmit buffers. 1859 */ 1860 txp = sc->fxp_desc.tx_list; 1861 if (txp != NULL) { 1862 for (i = 0; i < FXP_NTXCB; i++) { 1863 if (txp[i].tx_mbuf != NULL) { 1864 bus_dmamap_sync(sc->fxp_mtag, txp[i].tx_map, 1865 BUS_DMASYNC_POSTWRITE); 1866 bus_dmamap_unload(sc->fxp_mtag, txp[i].tx_map); 1867 m_freem(txp[i].tx_mbuf); 1868 txp[i].tx_mbuf = NULL; 1869 /* clear this to reset csum offload bits */ 1870 txp[i].tx_cb->tbd[0].tb_addr = 0; 1871 } 1872 } 1873 } 1874 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE); 1875 sc->tx_queued = 0; 1876 } 1877 1878 /* 1879 * Watchdog/transmission transmit timeout handler. Called when a 1880 * transmission is started on the interface, but no interrupt is 1881 * received before the timeout. This usually indicates that the 1882 * card has wedged for some reason. 1883 */ 1884 static void 1885 fxp_watchdog(struct ifnet *ifp) 1886 { 1887 struct fxp_softc *sc = ifp->if_softc; 1888 1889 FXP_LOCK(sc); 1890 device_printf(sc->dev, "device timeout\n"); 1891 ifp->if_oerrors++; 1892 1893 fxp_init_body(sc); 1894 FXP_UNLOCK(sc); 1895 } 1896 1897 /* 1898 * Acquire locks and then call the real initialization function. This 1899 * is necessary because ether_ioctl() calls if_init() and this would 1900 * result in mutex recursion if the mutex was held. 1901 */ 1902 static void 1903 fxp_init(void *xsc) 1904 { 1905 struct fxp_softc *sc = xsc; 1906 1907 FXP_LOCK(sc); 1908 fxp_init_body(sc); 1909 FXP_UNLOCK(sc); 1910 } 1911 1912 /* 1913 * Perform device initialization. This routine must be called with the 1914 * softc lock held. 1915 */ 1916 static void 1917 fxp_init_body(struct fxp_softc *sc) 1918 { 1919 struct ifnet *ifp = sc->ifp; 1920 struct fxp_cb_config *cbp; 1921 struct fxp_cb_ias *cb_ias; 1922 struct fxp_cb_tx *tcbp; 1923 struct fxp_tx *txp; 1924 struct fxp_cb_mcs *mcsp; 1925 int i, prm; 1926 1927 FXP_LOCK_ASSERT(sc, MA_OWNED); 1928 /* 1929 * Cancel any pending I/O 1930 */ 1931 fxp_stop(sc); 1932 1933 prm = (ifp->if_flags & IFF_PROMISC) ? 1 : 0; 1934 1935 /* 1936 * Initialize base of CBL and RFA memory. Loading with zero 1937 * sets it up for regular linear addressing. 1938 */ 1939 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 0); 1940 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_BASE); 1941 1942 fxp_scb_wait(sc); 1943 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_BASE); 1944 1945 /* 1946 * Initialize base of dump-stats buffer. 1947 */ 1948 fxp_scb_wait(sc); 1949 bus_dmamap_sync(sc->fxp_stag, sc->fxp_smap, BUS_DMASYNC_PREREAD); 1950 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->stats_addr); 1951 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_DUMP_ADR); 1952 1953 /* 1954 * Attempt to load microcode if requested. 1955 */ 1956 if (ifp->if_flags & IFF_LINK0 && (sc->flags & FXP_FLAG_UCODE) == 0) 1957 fxp_load_ucode(sc); 1958 1959 /* 1960 * Initialize the multicast address list. 1961 */ 1962 if (fxp_mc_addrs(sc)) { 1963 mcsp = sc->mcsp; 1964 mcsp->cb_status = 0; 1965 mcsp->cb_command = 1966 htole16(FXP_CB_COMMAND_MCAS | FXP_CB_COMMAND_EL); 1967 mcsp->link_addr = 0xffffffff; 1968 /* 1969 * Start the multicast setup command. 1970 */ 1971 fxp_scb_wait(sc); 1972 bus_dmamap_sync(sc->mcs_tag, sc->mcs_map, BUS_DMASYNC_PREWRITE); 1973 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->mcs_addr); 1974 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 1975 /* ...and wait for it to complete. */ 1976 fxp_dma_wait(sc, &mcsp->cb_status, sc->mcs_tag, sc->mcs_map); 1977 bus_dmamap_sync(sc->mcs_tag, sc->mcs_map, 1978 BUS_DMASYNC_POSTWRITE); 1979 } 1980 1981 /* 1982 * We temporarily use memory that contains the TxCB list to 1983 * construct the config CB. The TxCB list memory is rebuilt 1984 * later. 1985 */ 1986 cbp = (struct fxp_cb_config *)sc->fxp_desc.cbl_list; 1987 1988 /* 1989 * This bcopy is kind of disgusting, but there are a bunch of must be 1990 * zero and must be one bits in this structure and this is the easiest 1991 * way to initialize them all to proper values. 1992 */ 1993 bcopy(fxp_cb_config_template, cbp, sizeof(fxp_cb_config_template)); 1994 1995 cbp->cb_status = 0; 1996 cbp->cb_command = htole16(FXP_CB_COMMAND_CONFIG | 1997 FXP_CB_COMMAND_EL); 1998 cbp->link_addr = 0xffffffff; /* (no) next command */ 1999 cbp->byte_count = sc->flags & FXP_FLAG_EXT_RFA ? 32 : 22; 2000 cbp->rx_fifo_limit = 8; /* rx fifo threshold (32 bytes) */ 2001 cbp->tx_fifo_limit = 0; /* tx fifo threshold (0 bytes) */ 2002 cbp->adaptive_ifs = 0; /* (no) adaptive interframe spacing */ 2003 cbp->mwi_enable = sc->flags & FXP_FLAG_MWI_ENABLE ? 1 : 0; 2004 cbp->type_enable = 0; /* actually reserved */ 2005 cbp->read_align_en = sc->flags & FXP_FLAG_READ_ALIGN ? 1 : 0; 2006 cbp->end_wr_on_cl = sc->flags & FXP_FLAG_WRITE_ALIGN ? 1 : 0; 2007 cbp->rx_dma_bytecount = 0; /* (no) rx DMA max */ 2008 cbp->tx_dma_bytecount = 0; /* (no) tx DMA max */ 2009 cbp->dma_mbce = 0; /* (disable) dma max counters */ 2010 cbp->late_scb = 0; /* (don't) defer SCB update */ 2011 cbp->direct_dma_dis = 1; /* disable direct rcv dma mode */ 2012 cbp->tno_int_or_tco_en =0; /* (disable) tx not okay interrupt */ 2013 cbp->ci_int = 1; /* interrupt on CU idle */ 2014 cbp->ext_txcb_dis = sc->flags & FXP_FLAG_EXT_TXCB ? 0 : 1; 2015 cbp->ext_stats_dis = 1; /* disable extended counters */ 2016 cbp->keep_overrun_rx = 0; /* don't pass overrun frames to host */ 2017 cbp->save_bf = sc->flags & FXP_FLAG_SAVE_BAD ? 1 : prm; 2018 cbp->disc_short_rx = !prm; /* discard short packets */ 2019 cbp->underrun_retry = 1; /* retry mode (once) on DMA underrun */ 2020 cbp->two_frames = 0; /* do not limit FIFO to 2 frames */ 2021 cbp->dyn_tbd = 0; /* (no) dynamic TBD mode */ 2022 cbp->ext_rfa = sc->flags & FXP_FLAG_EXT_RFA ? 1 : 0; 2023 cbp->mediatype = sc->flags & FXP_FLAG_SERIAL_MEDIA ? 0 : 1; 2024 cbp->csma_dis = 0; /* (don't) disable link */ 2025 cbp->tcp_udp_cksum = 0; /* (don't) enable checksum */ 2026 cbp->vlan_tco = 0; /* (don't) enable vlan wakeup */ 2027 cbp->link_wake_en = 0; /* (don't) assert PME# on link change */ 2028 cbp->arp_wake_en = 0; /* (don't) assert PME# on arp */ 2029 cbp->mc_wake_en = 0; /* (don't) enable PME# on mcmatch */ 2030 cbp->nsai = 1; /* (don't) disable source addr insert */ 2031 cbp->preamble_length = 2; /* (7 byte) preamble */ 2032 cbp->loopback = 0; /* (don't) loopback */ 2033 cbp->linear_priority = 0; /* (normal CSMA/CD operation) */ 2034 cbp->linear_pri_mode = 0; /* (wait after xmit only) */ 2035 cbp->interfrm_spacing = 6; /* (96 bits of) interframe spacing */ 2036 cbp->promiscuous = prm; /* promiscuous mode */ 2037 cbp->bcast_disable = 0; /* (don't) disable broadcasts */ 2038 cbp->wait_after_win = 0; /* (don't) enable modified backoff alg*/ 2039 cbp->ignore_ul = 0; /* consider U/L bit in IA matching */ 2040 cbp->crc16_en = 0; /* (don't) enable crc-16 algorithm */ 2041 cbp->crscdt = sc->flags & FXP_FLAG_SERIAL_MEDIA ? 1 : 0; 2042 2043 cbp->stripping = !prm; /* truncate rx packet to byte count */ 2044 cbp->padding = 1; /* (do) pad short tx packets */ 2045 cbp->rcv_crc_xfer = 0; /* (don't) xfer CRC to host */ 2046 cbp->long_rx_en = sc->flags & FXP_FLAG_LONG_PKT_EN ? 1 : 0; 2047 cbp->ia_wake_en = 0; /* (don't) wake up on address match */ 2048 cbp->magic_pkt_dis = 0; /* (don't) disable magic packet */ 2049 /* must set wake_en in PMCSR also */ 2050 cbp->force_fdx = 0; /* (don't) force full duplex */ 2051 cbp->fdx_pin_en = 1; /* (enable) FDX# pin */ 2052 cbp->multi_ia = 0; /* (don't) accept multiple IAs */ 2053 cbp->mc_all = sc->flags & FXP_FLAG_ALL_MCAST ? 1 : 0; 2054 cbp->gamla_rx = sc->flags & FXP_FLAG_EXT_RFA ? 1 : 0; 2055 2056 if (sc->tunable_noflow || sc->revision == FXP_REV_82557) { 2057 /* 2058 * The 82557 has no hardware flow control, the values 2059 * below are the defaults for the chip. 2060 */ 2061 cbp->fc_delay_lsb = 0; 2062 cbp->fc_delay_msb = 0x40; 2063 cbp->pri_fc_thresh = 3; 2064 cbp->tx_fc_dis = 0; 2065 cbp->rx_fc_restop = 0; 2066 cbp->rx_fc_restart = 0; 2067 cbp->fc_filter = 0; 2068 cbp->pri_fc_loc = 1; 2069 } else { 2070 cbp->fc_delay_lsb = 0x1f; 2071 cbp->fc_delay_msb = 0x01; 2072 cbp->pri_fc_thresh = 3; 2073 cbp->tx_fc_dis = 0; /* enable transmit FC */ 2074 cbp->rx_fc_restop = 1; /* enable FC restop frames */ 2075 cbp->rx_fc_restart = 1; /* enable FC restart frames */ 2076 cbp->fc_filter = !prm; /* drop FC frames to host */ 2077 cbp->pri_fc_loc = 1; /* FC pri location (byte31) */ 2078 } 2079 2080 /* 2081 * Start the config command/DMA. 2082 */ 2083 fxp_scb_wait(sc); 2084 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE); 2085 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->fxp_desc.cbl_addr); 2086 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2087 /* ...and wait for it to complete. */ 2088 fxp_dma_wait(sc, &cbp->cb_status, sc->cbl_tag, sc->cbl_map); 2089 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_POSTWRITE); 2090 2091 /* 2092 * Now initialize the station address. Temporarily use the TxCB 2093 * memory area like we did above for the config CB. 2094 */ 2095 cb_ias = (struct fxp_cb_ias *)sc->fxp_desc.cbl_list; 2096 cb_ias->cb_status = 0; 2097 cb_ias->cb_command = htole16(FXP_CB_COMMAND_IAS | FXP_CB_COMMAND_EL); 2098 cb_ias->link_addr = 0xffffffff; 2099 bcopy(IFP2ENADDR(sc->ifp), cb_ias->macaddr, 2100 sizeof(IFP2ENADDR(sc->ifp))); 2101 2102 /* 2103 * Start the IAS (Individual Address Setup) command/DMA. 2104 */ 2105 fxp_scb_wait(sc); 2106 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE); 2107 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2108 /* ...and wait for it to complete. */ 2109 fxp_dma_wait(sc, &cb_ias->cb_status, sc->cbl_tag, sc->cbl_map); 2110 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_POSTWRITE); 2111 2112 /* 2113 * Initialize transmit control block (TxCB) list. 2114 */ 2115 txp = sc->fxp_desc.tx_list; 2116 tcbp = sc->fxp_desc.cbl_list; 2117 bzero(tcbp, FXP_TXCB_SZ); 2118 for (i = 0; i < FXP_NTXCB; i++) { 2119 txp[i].tx_mbuf = NULL; 2120 tcbp[i].cb_status = htole16(FXP_CB_STATUS_C | FXP_CB_STATUS_OK); 2121 tcbp[i].cb_command = htole16(FXP_CB_COMMAND_NOP); 2122 tcbp[i].link_addr = htole32(sc->fxp_desc.cbl_addr + 2123 (((i + 1) & FXP_TXCB_MASK) * sizeof(struct fxp_cb_tx))); 2124 if (sc->flags & FXP_FLAG_EXT_TXCB) 2125 tcbp[i].tbd_array_addr = 2126 htole32(FXP_TXCB_DMA_ADDR(sc, &tcbp[i].tbd[2])); 2127 else 2128 tcbp[i].tbd_array_addr = 2129 htole32(FXP_TXCB_DMA_ADDR(sc, &tcbp[i].tbd[0])); 2130 txp[i].tx_next = &txp[(i + 1) & FXP_TXCB_MASK]; 2131 } 2132 /* 2133 * Set the suspend flag on the first TxCB and start the control 2134 * unit. It will execute the NOP and then suspend. 2135 */ 2136 tcbp->cb_command = htole16(FXP_CB_COMMAND_NOP | FXP_CB_COMMAND_S); 2137 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE); 2138 sc->fxp_desc.tx_first = sc->fxp_desc.tx_last = txp; 2139 sc->tx_queued = 1; 2140 2141 fxp_scb_wait(sc); 2142 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2143 2144 /* 2145 * Initialize receiver buffer area - RFA. 2146 */ 2147 fxp_scb_wait(sc); 2148 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->fxp_desc.rx_head->rx_addr); 2149 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_START); 2150 2151 /* 2152 * Set current media. 2153 */ 2154 if (sc->miibus != NULL) 2155 mii_mediachg(device_get_softc(sc->miibus)); 2156 2157 ifp->if_drv_flags |= IFF_DRV_RUNNING; 2158 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 2159 2160 /* 2161 * Enable interrupts. 2162 */ 2163 #ifdef DEVICE_POLLING 2164 /* 2165 * ... but only do that if we are not polling. And because (presumably) 2166 * the default is interrupts on, we need to disable them explicitly! 2167 */ 2168 if ( ifp->if_flags & IFF_POLLING ) 2169 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE); 2170 else 2171 #endif /* DEVICE_POLLING */ 2172 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, 0); 2173 2174 /* 2175 * Start stats updater. 2176 */ 2177 callout_reset(&sc->stat_ch, hz, fxp_tick, sc); 2178 } 2179 2180 static int 2181 fxp_serial_ifmedia_upd(struct ifnet *ifp) 2182 { 2183 2184 return (0); 2185 } 2186 2187 static void 2188 fxp_serial_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 2189 { 2190 2191 ifmr->ifm_active = IFM_ETHER|IFM_MANUAL; 2192 } 2193 2194 /* 2195 * Change media according to request. 2196 */ 2197 static int 2198 fxp_ifmedia_upd(struct ifnet *ifp) 2199 { 2200 struct fxp_softc *sc = ifp->if_softc; 2201 struct mii_data *mii; 2202 2203 mii = device_get_softc(sc->miibus); 2204 FXP_LOCK(sc); 2205 mii_mediachg(mii); 2206 FXP_UNLOCK(sc); 2207 return (0); 2208 } 2209 2210 /* 2211 * Notify the world which media we're using. 2212 */ 2213 static void 2214 fxp_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 2215 { 2216 struct fxp_softc *sc = ifp->if_softc; 2217 struct mii_data *mii; 2218 2219 mii = device_get_softc(sc->miibus); 2220 FXP_LOCK(sc); 2221 mii_pollstat(mii); 2222 ifmr->ifm_active = mii->mii_media_active; 2223 ifmr->ifm_status = mii->mii_media_status; 2224 2225 if (ifmr->ifm_status & IFM_10_T && sc->flags & FXP_FLAG_CU_RESUME_BUG) 2226 sc->cu_resume_bug = 1; 2227 else 2228 sc->cu_resume_bug = 0; 2229 FXP_UNLOCK(sc); 2230 } 2231 2232 /* 2233 * Add a buffer to the end of the RFA buffer list. 2234 * Return 0 if successful, 1 for failure. A failure results in 2235 * adding the 'oldm' (if non-NULL) on to the end of the list - 2236 * tossing out its old contents and recycling it. 2237 * The RFA struct is stuck at the beginning of mbuf cluster and the 2238 * data pointer is fixed up to point just past it. 2239 */ 2240 static int 2241 fxp_add_rfabuf(struct fxp_softc *sc, struct fxp_rx *rxp) 2242 { 2243 struct mbuf *m; 2244 struct fxp_rfa *rfa, *p_rfa; 2245 struct fxp_rx *p_rx; 2246 bus_dmamap_t tmp_map; 2247 int error; 2248 2249 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 2250 if (m == NULL) 2251 return (ENOBUFS); 2252 2253 /* 2254 * Move the data pointer up so that the incoming data packet 2255 * will be 32-bit aligned. 2256 */ 2257 m->m_data += RFA_ALIGNMENT_FUDGE; 2258 2259 /* 2260 * Get a pointer to the base of the mbuf cluster and move 2261 * data start past it. 2262 */ 2263 rfa = mtod(m, struct fxp_rfa *); 2264 m->m_data += sc->rfa_size; 2265 rfa->size = htole16(MCLBYTES - sc->rfa_size - RFA_ALIGNMENT_FUDGE); 2266 2267 rfa->rfa_status = 0; 2268 rfa->rfa_control = htole16(FXP_RFA_CONTROL_EL); 2269 rfa->actual_size = 0; 2270 2271 /* 2272 * Initialize the rest of the RFA. Note that since the RFA 2273 * is misaligned, we cannot store values directly. We're thus 2274 * using the le32enc() function which handles endianness and 2275 * is also alignment-safe. 2276 */ 2277 le32enc(&rfa->link_addr, 0xffffffff); 2278 le32enc(&rfa->rbd_addr, 0xffffffff); 2279 2280 /* Map the RFA into DMA memory. */ 2281 error = bus_dmamap_load(sc->fxp_mtag, sc->spare_map, rfa, 2282 MCLBYTES - RFA_ALIGNMENT_FUDGE, fxp_dma_map_addr, 2283 &rxp->rx_addr, 0); 2284 if (error) { 2285 m_freem(m); 2286 return (error); 2287 } 2288 2289 bus_dmamap_unload(sc->fxp_mtag, rxp->rx_map); 2290 tmp_map = sc->spare_map; 2291 sc->spare_map = rxp->rx_map; 2292 rxp->rx_map = tmp_map; 2293 rxp->rx_mbuf = m; 2294 2295 bus_dmamap_sync(sc->fxp_mtag, rxp->rx_map, 2296 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2297 2298 /* 2299 * If there are other buffers already on the list, attach this 2300 * one to the end by fixing up the tail to point to this one. 2301 */ 2302 if (sc->fxp_desc.rx_head != NULL) { 2303 p_rx = sc->fxp_desc.rx_tail; 2304 p_rfa = (struct fxp_rfa *) 2305 (p_rx->rx_mbuf->m_ext.ext_buf + RFA_ALIGNMENT_FUDGE); 2306 p_rx->rx_next = rxp; 2307 le32enc(&p_rfa->link_addr, rxp->rx_addr); 2308 p_rfa->rfa_control = 0; 2309 bus_dmamap_sync(sc->fxp_mtag, p_rx->rx_map, 2310 BUS_DMASYNC_PREWRITE); 2311 } else { 2312 rxp->rx_next = NULL; 2313 sc->fxp_desc.rx_head = rxp; 2314 } 2315 sc->fxp_desc.rx_tail = rxp; 2316 return (0); 2317 } 2318 2319 static volatile int 2320 fxp_miibus_readreg(device_t dev, int phy, int reg) 2321 { 2322 struct fxp_softc *sc = device_get_softc(dev); 2323 int count = 10000; 2324 int value; 2325 2326 CSR_WRITE_4(sc, FXP_CSR_MDICONTROL, 2327 (FXP_MDI_READ << 26) | (reg << 16) | (phy << 21)); 2328 2329 while (((value = CSR_READ_4(sc, FXP_CSR_MDICONTROL)) & 0x10000000) == 0 2330 && count--) 2331 DELAY(10); 2332 2333 if (count <= 0) 2334 device_printf(dev, "fxp_miibus_readreg: timed out\n"); 2335 2336 return (value & 0xffff); 2337 } 2338 2339 static void 2340 fxp_miibus_writereg(device_t dev, int phy, int reg, int value) 2341 { 2342 struct fxp_softc *sc = device_get_softc(dev); 2343 int count = 10000; 2344 2345 CSR_WRITE_4(sc, FXP_CSR_MDICONTROL, 2346 (FXP_MDI_WRITE << 26) | (reg << 16) | (phy << 21) | 2347 (value & 0xffff)); 2348 2349 while ((CSR_READ_4(sc, FXP_CSR_MDICONTROL) & 0x10000000) == 0 && 2350 count--) 2351 DELAY(10); 2352 2353 if (count <= 0) 2354 device_printf(dev, "fxp_miibus_writereg: timed out\n"); 2355 } 2356 2357 static int 2358 fxp_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 2359 { 2360 struct fxp_softc *sc = ifp->if_softc; 2361 struct ifreq *ifr = (struct ifreq *)data; 2362 struct mii_data *mii; 2363 int flag, mask, error = 0; 2364 2365 switch (command) { 2366 case SIOCSIFFLAGS: 2367 FXP_LOCK(sc); 2368 if (ifp->if_flags & IFF_ALLMULTI) 2369 sc->flags |= FXP_FLAG_ALL_MCAST; 2370 else 2371 sc->flags &= ~FXP_FLAG_ALL_MCAST; 2372 2373 /* 2374 * If interface is marked up and not running, then start it. 2375 * If it is marked down and running, stop it. 2376 * XXX If it's up then re-initialize it. This is so flags 2377 * such as IFF_PROMISC are handled. 2378 */ 2379 if (ifp->if_flags & IFF_UP) { 2380 fxp_init_body(sc); 2381 } else { 2382 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 2383 fxp_stop(sc); 2384 } 2385 FXP_UNLOCK(sc); 2386 break; 2387 2388 case SIOCADDMULTI: 2389 case SIOCDELMULTI: 2390 FXP_LOCK(sc); 2391 if (ifp->if_flags & IFF_ALLMULTI) 2392 sc->flags |= FXP_FLAG_ALL_MCAST; 2393 else 2394 sc->flags &= ~FXP_FLAG_ALL_MCAST; 2395 /* 2396 * Multicast list has changed; set the hardware filter 2397 * accordingly. 2398 */ 2399 if ((sc->flags & FXP_FLAG_ALL_MCAST) == 0) 2400 fxp_mc_setup(sc); 2401 /* 2402 * fxp_mc_setup() can set FXP_FLAG_ALL_MCAST, so check it 2403 * again rather than else {}. 2404 */ 2405 if (sc->flags & FXP_FLAG_ALL_MCAST) 2406 fxp_init_body(sc); 2407 FXP_UNLOCK(sc); 2408 error = 0; 2409 break; 2410 2411 case SIOCSIFMEDIA: 2412 case SIOCGIFMEDIA: 2413 if (sc->miibus != NULL) { 2414 mii = device_get_softc(sc->miibus); 2415 error = ifmedia_ioctl(ifp, ifr, 2416 &mii->mii_media, command); 2417 } else { 2418 error = ifmedia_ioctl(ifp, ifr, &sc->sc_media, command); 2419 } 2420 break; 2421 2422 case SIOCSIFCAP: 2423 FXP_LOCK(sc); 2424 mask = ifp->if_capenable ^ ifr->ifr_reqcap; 2425 if (mask & IFCAP_POLLING) 2426 ifp->if_capenable ^= IFCAP_POLLING; 2427 if (mask & IFCAP_VLAN_MTU) { 2428 ifp->if_capenable ^= IFCAP_VLAN_MTU; 2429 if (sc->revision != FXP_REV_82557) 2430 flag = FXP_FLAG_LONG_PKT_EN; 2431 else /* a hack to get long frames on the old chip */ 2432 flag = FXP_FLAG_SAVE_BAD; 2433 sc->flags ^= flag; 2434 if (ifp->if_flags & IFF_UP) 2435 fxp_init_body(sc); 2436 } 2437 FXP_UNLOCK(sc); 2438 break; 2439 2440 default: 2441 error = ether_ioctl(ifp, command, data); 2442 } 2443 return (error); 2444 } 2445 2446 /* 2447 * Fill in the multicast address list and return number of entries. 2448 */ 2449 static int 2450 fxp_mc_addrs(struct fxp_softc *sc) 2451 { 2452 struct fxp_cb_mcs *mcsp = sc->mcsp; 2453 struct ifnet *ifp = sc->ifp; 2454 struct ifmultiaddr *ifma; 2455 int nmcasts; 2456 2457 nmcasts = 0; 2458 if ((sc->flags & FXP_FLAG_ALL_MCAST) == 0) { 2459 IF_ADDR_LOCK(ifp); 2460 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 2461 if (ifma->ifma_addr->sa_family != AF_LINK) 2462 continue; 2463 if (nmcasts >= MAXMCADDR) { 2464 sc->flags |= FXP_FLAG_ALL_MCAST; 2465 nmcasts = 0; 2466 break; 2467 } 2468 bcopy(LLADDR((struct sockaddr_dl *)ifma->ifma_addr), 2469 &sc->mcsp->mc_addr[nmcasts][0], ETHER_ADDR_LEN); 2470 nmcasts++; 2471 } 2472 IF_ADDR_UNLOCK(ifp); 2473 } 2474 mcsp->mc_cnt = htole16(nmcasts * ETHER_ADDR_LEN); 2475 return (nmcasts); 2476 } 2477 2478 /* 2479 * Program the multicast filter. 2480 * 2481 * We have an artificial restriction that the multicast setup command 2482 * must be the first command in the chain, so we take steps to ensure 2483 * this. By requiring this, it allows us to keep up the performance of 2484 * the pre-initialized command ring (esp. link pointers) by not actually 2485 * inserting the mcsetup command in the ring - i.e. its link pointer 2486 * points to the TxCB ring, but the mcsetup descriptor itself is not part 2487 * of it. We then can do 'CU_START' on the mcsetup descriptor and have it 2488 * lead into the regular TxCB ring when it completes. 2489 * 2490 * This function must be called at splimp. 2491 */ 2492 static void 2493 fxp_mc_setup(struct fxp_softc *sc) 2494 { 2495 struct fxp_cb_mcs *mcsp = sc->mcsp; 2496 struct ifnet *ifp = sc->ifp; 2497 struct fxp_tx *txp; 2498 int count; 2499 2500 FXP_LOCK_ASSERT(sc, MA_OWNED); 2501 /* 2502 * If there are queued commands, we must wait until they are all 2503 * completed. If we are already waiting, then add a NOP command 2504 * with interrupt option so that we're notified when all commands 2505 * have been completed - fxp_start() ensures that no additional 2506 * TX commands will be added when need_mcsetup is true. 2507 */ 2508 if (sc->tx_queued) { 2509 /* 2510 * need_mcsetup will be true if we are already waiting for the 2511 * NOP command to be completed (see below). In this case, bail. 2512 */ 2513 if (sc->need_mcsetup) 2514 return; 2515 sc->need_mcsetup = 1; 2516 2517 /* 2518 * Add a NOP command with interrupt so that we are notified 2519 * when all TX commands have been processed. 2520 */ 2521 txp = sc->fxp_desc.tx_last->tx_next; 2522 txp->tx_mbuf = NULL; 2523 txp->tx_cb->cb_status = 0; 2524 txp->tx_cb->cb_command = htole16(FXP_CB_COMMAND_NOP | 2525 FXP_CB_COMMAND_S | FXP_CB_COMMAND_I); 2526 /* 2527 * Advance the end of list forward. 2528 */ 2529 sc->fxp_desc.tx_last->tx_cb->cb_command &= 2530 htole16(~FXP_CB_COMMAND_S); 2531 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE); 2532 sc->fxp_desc.tx_last = txp; 2533 sc->tx_queued++; 2534 /* 2535 * Issue a resume in case the CU has just suspended. 2536 */ 2537 fxp_scb_wait(sc); 2538 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_RESUME); 2539 /* 2540 * Set a 5 second timer just in case we don't hear from the 2541 * card again. 2542 */ 2543 ifp->if_timer = 5; 2544 2545 return; 2546 } 2547 sc->need_mcsetup = 0; 2548 2549 /* 2550 * Initialize multicast setup descriptor. 2551 */ 2552 mcsp->cb_status = 0; 2553 mcsp->cb_command = htole16(FXP_CB_COMMAND_MCAS | 2554 FXP_CB_COMMAND_S | FXP_CB_COMMAND_I); 2555 mcsp->link_addr = htole32(sc->fxp_desc.cbl_addr); 2556 txp = &sc->fxp_desc.mcs_tx; 2557 txp->tx_mbuf = NULL; 2558 txp->tx_cb = (struct fxp_cb_tx *)sc->mcsp; 2559 txp->tx_next = sc->fxp_desc.tx_list; 2560 (void) fxp_mc_addrs(sc); 2561 sc->fxp_desc.tx_first = sc->fxp_desc.tx_last = txp; 2562 sc->tx_queued = 1; 2563 2564 /* 2565 * Wait until command unit is not active. This should never 2566 * be the case when nothing is queued, but make sure anyway. 2567 */ 2568 count = 100; 2569 while ((CSR_READ_1(sc, FXP_CSR_SCB_RUSCUS) >> 6) == 2570 FXP_SCB_CUS_ACTIVE && --count) 2571 DELAY(10); 2572 if (count == 0) { 2573 device_printf(sc->dev, "command queue timeout\n"); 2574 return; 2575 } 2576 2577 /* 2578 * Start the multicast setup command. 2579 */ 2580 fxp_scb_wait(sc); 2581 bus_dmamap_sync(sc->mcs_tag, sc->mcs_map, BUS_DMASYNC_PREWRITE); 2582 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->mcs_addr); 2583 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2584 2585 ifp->if_timer = 2; 2586 return; 2587 } 2588 2589 static uint32_t fxp_ucode_d101a[] = D101_A_RCVBUNDLE_UCODE; 2590 static uint32_t fxp_ucode_d101b0[] = D101_B0_RCVBUNDLE_UCODE; 2591 static uint32_t fxp_ucode_d101ma[] = D101M_B_RCVBUNDLE_UCODE; 2592 static uint32_t fxp_ucode_d101s[] = D101S_RCVBUNDLE_UCODE; 2593 static uint32_t fxp_ucode_d102[] = D102_B_RCVBUNDLE_UCODE; 2594 static uint32_t fxp_ucode_d102c[] = D102_C_RCVBUNDLE_UCODE; 2595 static uint32_t fxp_ucode_d102e[] = D102_E_RCVBUNDLE_UCODE; 2596 2597 #define UCODE(x) x, sizeof(x)/sizeof(uint32_t) 2598 2599 struct ucode { 2600 uint32_t revision; 2601 uint32_t *ucode; 2602 int length; 2603 u_short int_delay_offset; 2604 u_short bundle_max_offset; 2605 } ucode_table[] = { 2606 { FXP_REV_82558_A4, UCODE(fxp_ucode_d101a), D101_CPUSAVER_DWORD, 0 }, 2607 { FXP_REV_82558_B0, UCODE(fxp_ucode_d101b0), D101_CPUSAVER_DWORD, 0 }, 2608 { FXP_REV_82559_A0, UCODE(fxp_ucode_d101ma), 2609 D101M_CPUSAVER_DWORD, D101M_CPUSAVER_BUNDLE_MAX_DWORD }, 2610 { FXP_REV_82559S_A, UCODE(fxp_ucode_d101s), 2611 D101S_CPUSAVER_DWORD, D101S_CPUSAVER_BUNDLE_MAX_DWORD }, 2612 { FXP_REV_82550, UCODE(fxp_ucode_d102), 2613 D102_B_CPUSAVER_DWORD, D102_B_CPUSAVER_BUNDLE_MAX_DWORD }, 2614 { FXP_REV_82550_C, UCODE(fxp_ucode_d102c), 2615 D102_C_CPUSAVER_DWORD, D102_C_CPUSAVER_BUNDLE_MAX_DWORD }, 2616 { FXP_REV_82551_F, UCODE(fxp_ucode_d102e), 2617 D102_E_CPUSAVER_DWORD, D102_E_CPUSAVER_BUNDLE_MAX_DWORD }, 2618 { 0, NULL, 0, 0, 0 } 2619 }; 2620 2621 static void 2622 fxp_load_ucode(struct fxp_softc *sc) 2623 { 2624 struct ucode *uc; 2625 struct fxp_cb_ucode *cbp; 2626 int i; 2627 2628 for (uc = ucode_table; uc->ucode != NULL; uc++) 2629 if (sc->revision == uc->revision) 2630 break; 2631 if (uc->ucode == NULL) 2632 return; 2633 cbp = (struct fxp_cb_ucode *)sc->fxp_desc.cbl_list; 2634 cbp->cb_status = 0; 2635 cbp->cb_command = htole16(FXP_CB_COMMAND_UCODE | FXP_CB_COMMAND_EL); 2636 cbp->link_addr = 0xffffffff; /* (no) next command */ 2637 for (i = 0; i < uc->length; i++) 2638 cbp->ucode[i] = htole32(uc->ucode[i]); 2639 if (uc->int_delay_offset) 2640 *(uint16_t *)&cbp->ucode[uc->int_delay_offset] = 2641 htole16(sc->tunable_int_delay + sc->tunable_int_delay / 2); 2642 if (uc->bundle_max_offset) 2643 *(uint16_t *)&cbp->ucode[uc->bundle_max_offset] = 2644 htole16(sc->tunable_bundle_max); 2645 /* 2646 * Download the ucode to the chip. 2647 */ 2648 fxp_scb_wait(sc); 2649 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE); 2650 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->fxp_desc.cbl_addr); 2651 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2652 /* ...and wait for it to complete. */ 2653 fxp_dma_wait(sc, &cbp->cb_status, sc->cbl_tag, sc->cbl_map); 2654 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_POSTWRITE); 2655 device_printf(sc->dev, 2656 "Microcode loaded, int_delay: %d usec bundle_max: %d\n", 2657 sc->tunable_int_delay, 2658 uc->bundle_max_offset == 0 ? 0 : sc->tunable_bundle_max); 2659 sc->flags |= FXP_FLAG_UCODE; 2660 } 2661 2662 static int 2663 sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high) 2664 { 2665 int error, value; 2666 2667 value = *(int *)arg1; 2668 error = sysctl_handle_int(oidp, &value, 0, req); 2669 if (error || !req->newptr) 2670 return (error); 2671 if (value < low || value > high) 2672 return (EINVAL); 2673 *(int *)arg1 = value; 2674 return (0); 2675 } 2676 2677 /* 2678 * Interrupt delay is expressed in microseconds, a multiplier is used 2679 * to convert this to the appropriate clock ticks before using. 2680 */ 2681 static int 2682 sysctl_hw_fxp_int_delay(SYSCTL_HANDLER_ARGS) 2683 { 2684 return (sysctl_int_range(oidp, arg1, arg2, req, 300, 3000)); 2685 } 2686 2687 static int 2688 sysctl_hw_fxp_bundle_max(SYSCTL_HANDLER_ARGS) 2689 { 2690 return (sysctl_int_range(oidp, arg1, arg2, req, 1, 0xffff)); 2691 } 2692