1 /*- 2 * Copyright (c) 1995, David Greenman 3 * Copyright (c) 2001 Jonathan Lemon <jlemon@freebsd.org> 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice unmodified, this list of conditions, and the following 11 * disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 * 28 */ 29 30 #include <sys/cdefs.h> 31 __FBSDID("$FreeBSD$"); 32 33 /* 34 * Intel EtherExpress Pro/100B PCI Fast Ethernet driver 35 */ 36 37 #ifdef HAVE_KERNEL_OPTION_HEADERS 38 #include "opt_device_polling.h" 39 #endif 40 41 #include <sys/param.h> 42 #include <sys/systm.h> 43 #include <sys/bus.h> 44 #include <sys/endian.h> 45 #include <sys/kernel.h> 46 #include <sys/mbuf.h> 47 #include <sys/module.h> 48 #include <sys/rman.h> 49 #include <sys/socket.h> 50 #include <sys/sockio.h> 51 #include <sys/sysctl.h> 52 53 #include <net/bpf.h> 54 #include <net/ethernet.h> 55 #include <net/if.h> 56 #include <net/if_arp.h> 57 #include <net/if_dl.h> 58 #include <net/if_media.h> 59 #include <net/if_types.h> 60 #include <net/if_vlan_var.h> 61 62 #include <netinet/in.h> 63 #include <netinet/in_systm.h> 64 #include <netinet/ip.h> 65 #include <netinet/tcp.h> 66 #include <netinet/udp.h> 67 68 #include <machine/bus.h> 69 #include <machine/in_cksum.h> 70 #include <machine/resource.h> 71 72 #include <dev/pci/pcivar.h> 73 #include <dev/pci/pcireg.h> /* for PCIM_CMD_xxx */ 74 75 #include <dev/mii/mii.h> 76 #include <dev/mii/miivar.h> 77 78 #include <dev/fxp/if_fxpreg.h> 79 #include <dev/fxp/if_fxpvar.h> 80 #include <dev/fxp/rcvbundl.h> 81 82 MODULE_DEPEND(fxp, pci, 1, 1, 1); 83 MODULE_DEPEND(fxp, ether, 1, 1, 1); 84 MODULE_DEPEND(fxp, miibus, 1, 1, 1); 85 #include "miibus_if.h" 86 87 /* 88 * NOTE! On the Alpha, we have an alignment constraint. The 89 * card DMAs the packet immediately following the RFA. However, 90 * the first thing in the packet is a 14-byte Ethernet header. 91 * This means that the packet is misaligned. To compensate, 92 * we actually offset the RFA 2 bytes into the cluster. This 93 * alignes the packet after the Ethernet header at a 32-bit 94 * boundary. HOWEVER! This means that the RFA is misaligned! 95 */ 96 #define RFA_ALIGNMENT_FUDGE 2 97 98 /* 99 * Set initial transmit threshold at 64 (512 bytes). This is 100 * increased by 64 (512 bytes) at a time, to maximum of 192 101 * (1536 bytes), if an underrun occurs. 102 */ 103 static int tx_threshold = 64; 104 105 /* 106 * The configuration byte map has several undefined fields which 107 * must be one or must be zero. Set up a template for these bits 108 * only, (assuming a 82557 chip) leaving the actual configuration 109 * to fxp_init. 110 * 111 * See struct fxp_cb_config for the bit definitions. 112 */ 113 static u_char fxp_cb_config_template[] = { 114 0x0, 0x0, /* cb_status */ 115 0x0, 0x0, /* cb_command */ 116 0x0, 0x0, 0x0, 0x0, /* link_addr */ 117 0x0, /* 0 */ 118 0x0, /* 1 */ 119 0x0, /* 2 */ 120 0x0, /* 3 */ 121 0x0, /* 4 */ 122 0x0, /* 5 */ 123 0x32, /* 6 */ 124 0x0, /* 7 */ 125 0x0, /* 8 */ 126 0x0, /* 9 */ 127 0x6, /* 10 */ 128 0x0, /* 11 */ 129 0x0, /* 12 */ 130 0x0, /* 13 */ 131 0xf2, /* 14 */ 132 0x48, /* 15 */ 133 0x0, /* 16 */ 134 0x40, /* 17 */ 135 0xf0, /* 18 */ 136 0x0, /* 19 */ 137 0x3f, /* 20 */ 138 0x5 /* 21 */ 139 }; 140 141 struct fxp_ident { 142 uint16_t devid; 143 int16_t revid; /* -1 matches anything */ 144 char *name; 145 }; 146 147 /* 148 * Claim various Intel PCI device identifiers for this driver. The 149 * sub-vendor and sub-device field are extensively used to identify 150 * particular variants, but we don't currently differentiate between 151 * them. 152 */ 153 static struct fxp_ident fxp_ident_table[] = { 154 { 0x1029, -1, "Intel 82559 PCI/CardBus Pro/100" }, 155 { 0x1030, -1, "Intel 82559 Pro/100 Ethernet" }, 156 { 0x1031, -1, "Intel 82801CAM (ICH3) Pro/100 VE Ethernet" }, 157 { 0x1032, -1, "Intel 82801CAM (ICH3) Pro/100 VE Ethernet" }, 158 { 0x1033, -1, "Intel 82801CAM (ICH3) Pro/100 VM Ethernet" }, 159 { 0x1034, -1, "Intel 82801CAM (ICH3) Pro/100 VM Ethernet" }, 160 { 0x1035, -1, "Intel 82801CAM (ICH3) Pro/100 Ethernet" }, 161 { 0x1036, -1, "Intel 82801CAM (ICH3) Pro/100 Ethernet" }, 162 { 0x1037, -1, "Intel 82801CAM (ICH3) Pro/100 Ethernet" }, 163 { 0x1038, -1, "Intel 82801CAM (ICH3) Pro/100 VM Ethernet" }, 164 { 0x1039, -1, "Intel 82801DB (ICH4) Pro/100 VE Ethernet" }, 165 { 0x103A, -1, "Intel 82801DB (ICH4) Pro/100 Ethernet" }, 166 { 0x103B, -1, "Intel 82801DB (ICH4) Pro/100 VM Ethernet" }, 167 { 0x103C, -1, "Intel 82801DB (ICH4) Pro/100 Ethernet" }, 168 { 0x103D, -1, "Intel 82801DB (ICH4) Pro/100 VE Ethernet" }, 169 { 0x103E, -1, "Intel 82801DB (ICH4) Pro/100 VM Ethernet" }, 170 { 0x1050, -1, "Intel 82801BA (D865) Pro/100 VE Ethernet" }, 171 { 0x1051, -1, "Intel 82562ET (ICH5/ICH5R) Pro/100 VE Ethernet" }, 172 { 0x1059, -1, "Intel 82551QM Pro/100 M Mobile Connection" }, 173 { 0x1064, -1, "Intel 82562EZ (ICH6)" }, 174 { 0x1065, -1, "Intel 82562ET/EZ/GT/GZ PRO/100 VE Ethernet" }, 175 { 0x1068, -1, "Intel 82801FBM (ICH6-M) Pro/100 VE Ethernet" }, 176 { 0x1069, -1, "Intel 82562EM/EX/GX Pro/100 Ethernet" }, 177 { 0x1091, -1, "Intel 82562GX Pro/100 Ethernet" }, 178 { 0x1092, -1, "Intel Pro/100 VE Network Connection" }, 179 { 0x1093, -1, "Intel Pro/100 VM Network Connection" }, 180 { 0x1094, -1, "Intel Pro/100 946GZ (ICH7) Network Connection" }, 181 { 0x1209, -1, "Intel 82559ER Embedded 10/100 Ethernet" }, 182 { 0x1229, 0x01, "Intel 82557 Pro/100 Ethernet" }, 183 { 0x1229, 0x02, "Intel 82557 Pro/100 Ethernet" }, 184 { 0x1229, 0x03, "Intel 82557 Pro/100 Ethernet" }, 185 { 0x1229, 0x04, "Intel 82558 Pro/100 Ethernet" }, 186 { 0x1229, 0x05, "Intel 82558 Pro/100 Ethernet" }, 187 { 0x1229, 0x06, "Intel 82559 Pro/100 Ethernet" }, 188 { 0x1229, 0x07, "Intel 82559 Pro/100 Ethernet" }, 189 { 0x1229, 0x08, "Intel 82559 Pro/100 Ethernet" }, 190 { 0x1229, 0x09, "Intel 82559ER Pro/100 Ethernet" }, 191 { 0x1229, 0x0c, "Intel 82550 Pro/100 Ethernet" }, 192 { 0x1229, 0x0d, "Intel 82550 Pro/100 Ethernet" }, 193 { 0x1229, 0x0e, "Intel 82550 Pro/100 Ethernet" }, 194 { 0x1229, 0x0f, "Intel 82551 Pro/100 Ethernet" }, 195 { 0x1229, 0x10, "Intel 82551 Pro/100 Ethernet" }, 196 { 0x1229, -1, "Intel 82557/8/9 Pro/100 Ethernet" }, 197 { 0x2449, -1, "Intel 82801BA/CAM (ICH2/3) Pro/100 Ethernet" }, 198 { 0x27dc, -1, "Intel 82801GB (ICH7) 10/100 Ethernet" }, 199 { 0, -1, NULL }, 200 }; 201 202 #ifdef FXP_IP_CSUM_WAR 203 #define FXP_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 204 #else 205 #define FXP_CSUM_FEATURES (CSUM_TCP | CSUM_UDP) 206 #endif 207 208 static int fxp_probe(device_t dev); 209 static int fxp_attach(device_t dev); 210 static int fxp_detach(device_t dev); 211 static int fxp_shutdown(device_t dev); 212 static int fxp_suspend(device_t dev); 213 static int fxp_resume(device_t dev); 214 215 static void fxp_intr(void *xsc); 216 static void fxp_rxcsum(struct fxp_softc *sc, struct ifnet *ifp, 217 struct mbuf *m, uint16_t status, int pos); 218 static void fxp_intr_body(struct fxp_softc *sc, struct ifnet *ifp, 219 uint8_t statack, int count); 220 static void fxp_init(void *xsc); 221 static void fxp_init_body(struct fxp_softc *sc); 222 static void fxp_tick(void *xsc); 223 static void fxp_start(struct ifnet *ifp); 224 static void fxp_start_body(struct ifnet *ifp); 225 static int fxp_encap(struct fxp_softc *sc, struct mbuf **m_head); 226 static void fxp_txeof(struct fxp_softc *sc); 227 static void fxp_stop(struct fxp_softc *sc); 228 static void fxp_release(struct fxp_softc *sc); 229 static int fxp_ioctl(struct ifnet *ifp, u_long command, 230 caddr_t data); 231 static void fxp_watchdog(struct fxp_softc *sc); 232 static void fxp_add_rfabuf(struct fxp_softc *sc, 233 struct fxp_rx *rxp); 234 static void fxp_discard_rfabuf(struct fxp_softc *sc, 235 struct fxp_rx *rxp); 236 static int fxp_new_rfabuf(struct fxp_softc *sc, 237 struct fxp_rx *rxp); 238 static int fxp_mc_addrs(struct fxp_softc *sc); 239 static void fxp_mc_setup(struct fxp_softc *sc); 240 static uint16_t fxp_eeprom_getword(struct fxp_softc *sc, int offset, 241 int autosize); 242 static void fxp_eeprom_putword(struct fxp_softc *sc, int offset, 243 uint16_t data); 244 static void fxp_autosize_eeprom(struct fxp_softc *sc); 245 static void fxp_read_eeprom(struct fxp_softc *sc, u_short *data, 246 int offset, int words); 247 static void fxp_write_eeprom(struct fxp_softc *sc, u_short *data, 248 int offset, int words); 249 static int fxp_ifmedia_upd(struct ifnet *ifp); 250 static void fxp_ifmedia_sts(struct ifnet *ifp, 251 struct ifmediareq *ifmr); 252 static int fxp_serial_ifmedia_upd(struct ifnet *ifp); 253 static void fxp_serial_ifmedia_sts(struct ifnet *ifp, 254 struct ifmediareq *ifmr); 255 static int fxp_miibus_readreg(device_t dev, int phy, int reg); 256 static void fxp_miibus_writereg(device_t dev, int phy, int reg, 257 int value); 258 static void fxp_load_ucode(struct fxp_softc *sc); 259 static int sysctl_int_range(SYSCTL_HANDLER_ARGS, 260 int low, int high); 261 static int sysctl_hw_fxp_bundle_max(SYSCTL_HANDLER_ARGS); 262 static int sysctl_hw_fxp_int_delay(SYSCTL_HANDLER_ARGS); 263 static void fxp_scb_wait(struct fxp_softc *sc); 264 static void fxp_scb_cmd(struct fxp_softc *sc, int cmd); 265 static void fxp_dma_wait(struct fxp_softc *sc, 266 volatile uint16_t *status, bus_dma_tag_t dmat, 267 bus_dmamap_t map); 268 269 static device_method_t fxp_methods[] = { 270 /* Device interface */ 271 DEVMETHOD(device_probe, fxp_probe), 272 DEVMETHOD(device_attach, fxp_attach), 273 DEVMETHOD(device_detach, fxp_detach), 274 DEVMETHOD(device_shutdown, fxp_shutdown), 275 DEVMETHOD(device_suspend, fxp_suspend), 276 DEVMETHOD(device_resume, fxp_resume), 277 278 /* MII interface */ 279 DEVMETHOD(miibus_readreg, fxp_miibus_readreg), 280 DEVMETHOD(miibus_writereg, fxp_miibus_writereg), 281 282 { 0, 0 } 283 }; 284 285 static driver_t fxp_driver = { 286 "fxp", 287 fxp_methods, 288 sizeof(struct fxp_softc), 289 }; 290 291 static devclass_t fxp_devclass; 292 293 DRIVER_MODULE(fxp, pci, fxp_driver, fxp_devclass, 0, 0); 294 DRIVER_MODULE(fxp, cardbus, fxp_driver, fxp_devclass, 0, 0); 295 DRIVER_MODULE(miibus, fxp, miibus_driver, miibus_devclass, 0, 0); 296 297 static struct resource_spec fxp_res_spec_mem[] = { 298 { SYS_RES_MEMORY, FXP_PCI_MMBA, RF_ACTIVE }, 299 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE }, 300 { -1, 0 } 301 }; 302 303 static struct resource_spec fxp_res_spec_io[] = { 304 { SYS_RES_IOPORT, FXP_PCI_IOBA, RF_ACTIVE }, 305 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE }, 306 { -1, 0 } 307 }; 308 309 /* 310 * Wait for the previous command to be accepted (but not necessarily 311 * completed). 312 */ 313 static void 314 fxp_scb_wait(struct fxp_softc *sc) 315 { 316 union { 317 uint16_t w; 318 uint8_t b[2]; 319 } flowctl; 320 int i = 10000; 321 322 while (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) && --i) 323 DELAY(2); 324 if (i == 0) { 325 flowctl.b[0] = CSR_READ_1(sc, FXP_CSR_FLOWCONTROL); 326 flowctl.b[1] = CSR_READ_1(sc, FXP_CSR_FLOWCONTROL + 1); 327 device_printf(sc->dev, "SCB timeout: 0x%x 0x%x 0x%x 0x%x\n", 328 CSR_READ_1(sc, FXP_CSR_SCB_COMMAND), 329 CSR_READ_1(sc, FXP_CSR_SCB_STATACK), 330 CSR_READ_1(sc, FXP_CSR_SCB_RUSCUS), flowctl.w); 331 } 332 } 333 334 static void 335 fxp_scb_cmd(struct fxp_softc *sc, int cmd) 336 { 337 338 if (cmd == FXP_SCB_COMMAND_CU_RESUME && sc->cu_resume_bug) { 339 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_CB_COMMAND_NOP); 340 fxp_scb_wait(sc); 341 } 342 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, cmd); 343 } 344 345 static void 346 fxp_dma_wait(struct fxp_softc *sc, volatile uint16_t *status, 347 bus_dma_tag_t dmat, bus_dmamap_t map) 348 { 349 int i = 10000; 350 351 bus_dmamap_sync(dmat, map, BUS_DMASYNC_POSTREAD); 352 while (!(le16toh(*status) & FXP_CB_STATUS_C) && --i) { 353 DELAY(2); 354 bus_dmamap_sync(dmat, map, BUS_DMASYNC_POSTREAD); 355 } 356 if (i == 0) 357 device_printf(sc->dev, "DMA timeout\n"); 358 } 359 360 /* 361 * Return identification string if this device is ours. 362 */ 363 static int 364 fxp_probe(device_t dev) 365 { 366 uint16_t devid; 367 uint8_t revid; 368 struct fxp_ident *ident; 369 370 if (pci_get_vendor(dev) == FXP_VENDORID_INTEL) { 371 devid = pci_get_device(dev); 372 revid = pci_get_revid(dev); 373 for (ident = fxp_ident_table; ident->name != NULL; ident++) { 374 if (ident->devid == devid && 375 (ident->revid == revid || ident->revid == -1)) { 376 device_set_desc(dev, ident->name); 377 return (BUS_PROBE_DEFAULT); 378 } 379 } 380 } 381 return (ENXIO); 382 } 383 384 static void 385 fxp_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error) 386 { 387 uint32_t *addr; 388 389 if (error) 390 return; 391 392 KASSERT(nseg == 1, ("too many DMA segments, %d should be 1", nseg)); 393 addr = arg; 394 *addr = segs->ds_addr; 395 } 396 397 static int 398 fxp_attach(device_t dev) 399 { 400 struct fxp_softc *sc; 401 struct fxp_cb_tx *tcbp; 402 struct fxp_tx *txp; 403 struct fxp_rx *rxp; 404 struct ifnet *ifp; 405 uint32_t val; 406 uint16_t data, myea[ETHER_ADDR_LEN / 2]; 407 u_char eaddr[ETHER_ADDR_LEN]; 408 int i, pmc, prefer_iomap; 409 int error; 410 411 error = 0; 412 sc = device_get_softc(dev); 413 sc->dev = dev; 414 mtx_init(&sc->sc_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 415 MTX_DEF); 416 callout_init_mtx(&sc->stat_ch, &sc->sc_mtx, 0); 417 ifmedia_init(&sc->sc_media, 0, fxp_serial_ifmedia_upd, 418 fxp_serial_ifmedia_sts); 419 420 ifp = sc->ifp = if_alloc(IFT_ETHER); 421 if (ifp == NULL) { 422 device_printf(dev, "can not if_alloc()\n"); 423 error = ENOSPC; 424 goto fail; 425 } 426 427 /* 428 * Enable bus mastering. 429 */ 430 pci_enable_busmaster(dev); 431 val = pci_read_config(dev, PCIR_COMMAND, 2); 432 433 /* 434 * Figure out which we should try first - memory mapping or i/o mapping? 435 * We default to memory mapping. Then we accept an override from the 436 * command line. Then we check to see which one is enabled. 437 */ 438 prefer_iomap = 0; 439 resource_int_value(device_get_name(dev), device_get_unit(dev), 440 "prefer_iomap", &prefer_iomap); 441 if (prefer_iomap) 442 sc->fxp_spec = fxp_res_spec_io; 443 else 444 sc->fxp_spec = fxp_res_spec_mem; 445 446 error = bus_alloc_resources(dev, sc->fxp_spec, sc->fxp_res); 447 if (error) { 448 if (sc->fxp_spec == fxp_res_spec_mem) 449 sc->fxp_spec = fxp_res_spec_io; 450 else 451 sc->fxp_spec = fxp_res_spec_mem; 452 error = bus_alloc_resources(dev, sc->fxp_spec, sc->fxp_res); 453 } 454 if (error) { 455 device_printf(dev, "could not allocate resources\n"); 456 error = ENXIO; 457 goto fail; 458 } 459 460 if (bootverbose) { 461 device_printf(dev, "using %s space register mapping\n", 462 sc->fxp_spec == fxp_res_spec_mem ? "memory" : "I/O"); 463 } 464 465 /* 466 * Reset to a stable state. 467 */ 468 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET); 469 DELAY(10); 470 471 /* 472 * Find out how large of an SEEPROM we have. 473 */ 474 fxp_autosize_eeprom(sc); 475 476 /* 477 * Find out the chip revision; lump all 82557 revs together. 478 */ 479 fxp_read_eeprom(sc, &data, 5, 1); 480 if ((data >> 8) == 1) 481 sc->revision = FXP_REV_82557; 482 else 483 sc->revision = pci_get_revid(dev); 484 485 /* 486 * Check availability of WOL. 82559ER does not support WOL. 487 */ 488 if (sc->revision >= FXP_REV_82558_A4 && 489 sc->revision != FXP_REV_82559S_A) { 490 fxp_read_eeprom(sc, &data, 10, 1); 491 if ((data & 0x20) != 0 && 492 pci_find_extcap(sc->dev, PCIY_PMG, &pmc) == 0) 493 sc->flags |= FXP_FLAG_WOLCAP; 494 } 495 496 /* 497 * Determine whether we must use the 503 serial interface. 498 */ 499 fxp_read_eeprom(sc, &data, 6, 1); 500 if (sc->revision == FXP_REV_82557 && (data & FXP_PHY_DEVICE_MASK) != 0 501 && (data & FXP_PHY_SERIAL_ONLY)) 502 sc->flags |= FXP_FLAG_SERIAL_MEDIA; 503 504 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 505 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 506 OID_AUTO, "int_delay", CTLTYPE_INT | CTLFLAG_RW, 507 &sc->tunable_int_delay, 0, sysctl_hw_fxp_int_delay, "I", 508 "FXP driver receive interrupt microcode bundling delay"); 509 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 510 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 511 OID_AUTO, "bundle_max", CTLTYPE_INT | CTLFLAG_RW, 512 &sc->tunable_bundle_max, 0, sysctl_hw_fxp_bundle_max, "I", 513 "FXP driver receive interrupt microcode bundle size limit"); 514 SYSCTL_ADD_INT(device_get_sysctl_ctx(dev), 515 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 516 OID_AUTO, "rnr", CTLFLAG_RD, &sc->rnr, 0, 517 "FXP RNR events"); 518 SYSCTL_ADD_INT(device_get_sysctl_ctx(dev), 519 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 520 OID_AUTO, "noflow", CTLFLAG_RW, &sc->tunable_noflow, 0, 521 "FXP flow control disabled"); 522 523 /* 524 * Pull in device tunables. 525 */ 526 sc->tunable_int_delay = TUNABLE_INT_DELAY; 527 sc->tunable_bundle_max = TUNABLE_BUNDLE_MAX; 528 sc->tunable_noflow = 1; 529 (void) resource_int_value(device_get_name(dev), device_get_unit(dev), 530 "int_delay", &sc->tunable_int_delay); 531 (void) resource_int_value(device_get_name(dev), device_get_unit(dev), 532 "bundle_max", &sc->tunable_bundle_max); 533 (void) resource_int_value(device_get_name(dev), device_get_unit(dev), 534 "noflow", &sc->tunable_noflow); 535 sc->rnr = 0; 536 537 /* 538 * Enable workarounds for certain chip revision deficiencies. 539 * 540 * Systems based on the ICH2/ICH2-M chip from Intel, and possibly 541 * some systems based a normal 82559 design, have a defect where 542 * the chip can cause a PCI protocol violation if it receives 543 * a CU_RESUME command when it is entering the IDLE state. The 544 * workaround is to disable Dynamic Standby Mode, so the chip never 545 * deasserts CLKRUN#, and always remains in an active state. 546 * 547 * See Intel 82801BA/82801BAM Specification Update, Errata #30. 548 */ 549 i = pci_get_device(dev); 550 if (i == 0x2449 || (i > 0x1030 && i < 0x1039) || 551 sc->revision >= FXP_REV_82559_A0) { 552 fxp_read_eeprom(sc, &data, 10, 1); 553 if (data & 0x02) { /* STB enable */ 554 uint16_t cksum; 555 int i; 556 557 device_printf(dev, 558 "Disabling dynamic standby mode in EEPROM\n"); 559 data &= ~0x02; 560 fxp_write_eeprom(sc, &data, 10, 1); 561 device_printf(dev, "New EEPROM ID: 0x%x\n", data); 562 cksum = 0; 563 for (i = 0; i < (1 << sc->eeprom_size) - 1; i++) { 564 fxp_read_eeprom(sc, &data, i, 1); 565 cksum += data; 566 } 567 i = (1 << sc->eeprom_size) - 1; 568 cksum = 0xBABA - cksum; 569 fxp_read_eeprom(sc, &data, i, 1); 570 fxp_write_eeprom(sc, &cksum, i, 1); 571 device_printf(dev, 572 "EEPROM checksum @ 0x%x: 0x%x -> 0x%x\n", 573 i, data, cksum); 574 #if 1 575 /* 576 * If the user elects to continue, try the software 577 * workaround, as it is better than nothing. 578 */ 579 sc->flags |= FXP_FLAG_CU_RESUME_BUG; 580 #endif 581 } 582 } 583 584 /* 585 * If we are not a 82557 chip, we can enable extended features. 586 */ 587 if (sc->revision != FXP_REV_82557) { 588 /* 589 * If MWI is enabled in the PCI configuration, and there 590 * is a valid cacheline size (8 or 16 dwords), then tell 591 * the board to turn on MWI. 592 */ 593 if (val & PCIM_CMD_MWRICEN && 594 pci_read_config(dev, PCIR_CACHELNSZ, 1) != 0) 595 sc->flags |= FXP_FLAG_MWI_ENABLE; 596 597 /* turn on the extended TxCB feature */ 598 sc->flags |= FXP_FLAG_EXT_TXCB; 599 600 /* enable reception of long frames for VLAN */ 601 sc->flags |= FXP_FLAG_LONG_PKT_EN; 602 } else { 603 /* a hack to get long VLAN frames on a 82557 */ 604 sc->flags |= FXP_FLAG_SAVE_BAD; 605 } 606 607 /* For 82559 or later chips, Rx checksum offload is supported. */ 608 if (sc->revision >= FXP_REV_82559_A0) 609 sc->flags |= FXP_FLAG_82559_RXCSUM; 610 /* 611 * Enable use of extended RFDs and TCBs for 82550 612 * and later chips. Note: we need extended TXCB support 613 * too, but that's already enabled by the code above. 614 * Be careful to do this only on the right devices. 615 */ 616 if (sc->revision == FXP_REV_82550 || sc->revision == FXP_REV_82550_C || 617 sc->revision == FXP_REV_82551_E || sc->revision == FXP_REV_82551_F 618 || sc->revision == FXP_REV_82551_10) { 619 sc->rfa_size = sizeof (struct fxp_rfa); 620 sc->tx_cmd = FXP_CB_COMMAND_IPCBXMIT; 621 sc->flags |= FXP_FLAG_EXT_RFA; 622 /* Use extended RFA instead of 82559 checksum mode. */ 623 sc->flags &= ~FXP_FLAG_82559_RXCSUM; 624 } else { 625 sc->rfa_size = sizeof (struct fxp_rfa) - FXP_RFAX_LEN; 626 sc->tx_cmd = FXP_CB_COMMAND_XMIT; 627 } 628 629 /* 630 * Allocate DMA tags and DMA safe memory. 631 */ 632 sc->maxtxseg = FXP_NTXSEG; 633 sc->maxsegsize = MCLBYTES; 634 if (sc->flags & FXP_FLAG_EXT_RFA) { 635 sc->maxtxseg--; 636 sc->maxsegsize = FXP_TSO_SEGSIZE; 637 } 638 error = bus_dma_tag_create(bus_get_dma_tag(dev), 2, 0, 639 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 640 sc->maxsegsize * sc->maxtxseg + sizeof(struct ether_vlan_header), 641 sc->maxtxseg, sc->maxsegsize, 0, 642 busdma_lock_mutex, &Giant, &sc->fxp_mtag); 643 if (error) { 644 device_printf(dev, "could not allocate dma tag\n"); 645 goto fail; 646 } 647 648 error = bus_dma_tag_create(bus_get_dma_tag(dev), 4, 0, 649 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 650 sizeof(struct fxp_stats), 1, sizeof(struct fxp_stats), 0, 651 busdma_lock_mutex, &Giant, &sc->fxp_stag); 652 if (error) { 653 device_printf(dev, "could not allocate dma tag\n"); 654 goto fail; 655 } 656 657 error = bus_dmamem_alloc(sc->fxp_stag, (void **)&sc->fxp_stats, 658 BUS_DMA_NOWAIT | BUS_DMA_ZERO, &sc->fxp_smap); 659 if (error) 660 goto fail; 661 error = bus_dmamap_load(sc->fxp_stag, sc->fxp_smap, sc->fxp_stats, 662 sizeof(struct fxp_stats), fxp_dma_map_addr, &sc->stats_addr, 0); 663 if (error) { 664 device_printf(dev, "could not map the stats buffer\n"); 665 goto fail; 666 } 667 668 error = bus_dma_tag_create(bus_get_dma_tag(dev), 4, 0, 669 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 670 FXP_TXCB_SZ, 1, FXP_TXCB_SZ, 0, 671 busdma_lock_mutex, &Giant, &sc->cbl_tag); 672 if (error) { 673 device_printf(dev, "could not allocate dma tag\n"); 674 goto fail; 675 } 676 677 error = bus_dmamem_alloc(sc->cbl_tag, (void **)&sc->fxp_desc.cbl_list, 678 BUS_DMA_NOWAIT | BUS_DMA_ZERO, &sc->cbl_map); 679 if (error) 680 goto fail; 681 682 error = bus_dmamap_load(sc->cbl_tag, sc->cbl_map, 683 sc->fxp_desc.cbl_list, FXP_TXCB_SZ, fxp_dma_map_addr, 684 &sc->fxp_desc.cbl_addr, 0); 685 if (error) { 686 device_printf(dev, "could not map DMA memory\n"); 687 goto fail; 688 } 689 690 error = bus_dma_tag_create(bus_get_dma_tag(dev), 4, 0, 691 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 692 sizeof(struct fxp_cb_mcs), 1, sizeof(struct fxp_cb_mcs), 0, 693 busdma_lock_mutex, &Giant, &sc->mcs_tag); 694 if (error) { 695 device_printf(dev, "could not allocate dma tag\n"); 696 goto fail; 697 } 698 699 error = bus_dmamem_alloc(sc->mcs_tag, (void **)&sc->mcsp, 700 BUS_DMA_NOWAIT, &sc->mcs_map); 701 if (error) 702 goto fail; 703 error = bus_dmamap_load(sc->mcs_tag, sc->mcs_map, sc->mcsp, 704 sizeof(struct fxp_cb_mcs), fxp_dma_map_addr, &sc->mcs_addr, 0); 705 if (error) { 706 device_printf(dev, "can't map the multicast setup command\n"); 707 goto fail; 708 } 709 710 /* 711 * Pre-allocate the TX DMA maps and setup the pointers to 712 * the TX command blocks. 713 */ 714 txp = sc->fxp_desc.tx_list; 715 tcbp = sc->fxp_desc.cbl_list; 716 for (i = 0; i < FXP_NTXCB; i++) { 717 txp[i].tx_cb = tcbp + i; 718 error = bus_dmamap_create(sc->fxp_mtag, 0, &txp[i].tx_map); 719 if (error) { 720 device_printf(dev, "can't create DMA map for TX\n"); 721 goto fail; 722 } 723 } 724 error = bus_dmamap_create(sc->fxp_mtag, 0, &sc->spare_map); 725 if (error) { 726 device_printf(dev, "can't create spare DMA map\n"); 727 goto fail; 728 } 729 730 /* 731 * Pre-allocate our receive buffers. 732 */ 733 sc->fxp_desc.rx_head = sc->fxp_desc.rx_tail = NULL; 734 for (i = 0; i < FXP_NRFABUFS; i++) { 735 rxp = &sc->fxp_desc.rx_list[i]; 736 error = bus_dmamap_create(sc->fxp_mtag, 0, &rxp->rx_map); 737 if (error) { 738 device_printf(dev, "can't create DMA map for RX\n"); 739 goto fail; 740 } 741 if (fxp_new_rfabuf(sc, rxp) != 0) { 742 error = ENOMEM; 743 goto fail; 744 } 745 fxp_add_rfabuf(sc, rxp); 746 } 747 748 /* 749 * Read MAC address. 750 */ 751 fxp_read_eeprom(sc, myea, 0, 3); 752 eaddr[0] = myea[0] & 0xff; 753 eaddr[1] = myea[0] >> 8; 754 eaddr[2] = myea[1] & 0xff; 755 eaddr[3] = myea[1] >> 8; 756 eaddr[4] = myea[2] & 0xff; 757 eaddr[5] = myea[2] >> 8; 758 if (bootverbose) { 759 device_printf(dev, "PCI IDs: %04x %04x %04x %04x %04x\n", 760 pci_get_vendor(dev), pci_get_device(dev), 761 pci_get_subvendor(dev), pci_get_subdevice(dev), 762 pci_get_revid(dev)); 763 fxp_read_eeprom(sc, &data, 10, 1); 764 device_printf(dev, "Dynamic Standby mode is %s\n", 765 data & 0x02 ? "enabled" : "disabled"); 766 } 767 768 /* 769 * If this is only a 10Mbps device, then there is no MII, and 770 * the PHY will use a serial interface instead. 771 * 772 * The Seeq 80c24 AutoDUPLEX(tm) Ethernet Interface Adapter 773 * doesn't have a programming interface of any sort. The 774 * media is sensed automatically based on how the link partner 775 * is configured. This is, in essence, manual configuration. 776 */ 777 if (sc->flags & FXP_FLAG_SERIAL_MEDIA) { 778 ifmedia_add(&sc->sc_media, IFM_ETHER|IFM_MANUAL, 0, NULL); 779 ifmedia_set(&sc->sc_media, IFM_ETHER|IFM_MANUAL); 780 } else { 781 if (mii_phy_probe(dev, &sc->miibus, fxp_ifmedia_upd, 782 fxp_ifmedia_sts)) { 783 device_printf(dev, "MII without any PHY!\n"); 784 error = ENXIO; 785 goto fail; 786 } 787 } 788 789 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 790 ifp->if_init = fxp_init; 791 ifp->if_softc = sc; 792 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 793 ifp->if_ioctl = fxp_ioctl; 794 ifp->if_start = fxp_start; 795 796 ifp->if_capabilities = ifp->if_capenable = 0; 797 798 /* Enable checksum offload/TSO for 82550 or better chips */ 799 if (sc->flags & FXP_FLAG_EXT_RFA) { 800 ifp->if_hwassist = FXP_CSUM_FEATURES | CSUM_TSO; 801 ifp->if_capabilities |= IFCAP_HWCSUM | IFCAP_TSO4; 802 ifp->if_capenable |= IFCAP_HWCSUM | IFCAP_TSO4; 803 } 804 805 if (sc->flags & FXP_FLAG_82559_RXCSUM) { 806 ifp->if_capabilities |= IFCAP_RXCSUM; 807 ifp->if_capenable |= IFCAP_RXCSUM; 808 } 809 810 if (sc->flags & FXP_FLAG_WOLCAP) { 811 ifp->if_capabilities |= IFCAP_WOL_MAGIC; 812 ifp->if_capenable |= IFCAP_WOL_MAGIC; 813 } 814 815 #ifdef DEVICE_POLLING 816 /* Inform the world we support polling. */ 817 ifp->if_capabilities |= IFCAP_POLLING; 818 #endif 819 820 /* 821 * Attach the interface. 822 */ 823 ether_ifattach(ifp, eaddr); 824 825 /* 826 * Tell the upper layer(s) we support long frames. 827 * Must appear after the call to ether_ifattach() because 828 * ether_ifattach() sets ifi_hdrlen to the default value. 829 */ 830 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 831 ifp->if_capabilities |= IFCAP_VLAN_MTU; 832 ifp->if_capenable |= IFCAP_VLAN_MTU; /* the hw bits already set */ 833 834 /* 835 * Let the system queue as many packets as we have available 836 * TX descriptors. 837 */ 838 IFQ_SET_MAXLEN(&ifp->if_snd, FXP_NTXCB - 1); 839 ifp->if_snd.ifq_drv_maxlen = FXP_NTXCB - 1; 840 IFQ_SET_READY(&ifp->if_snd); 841 842 /* 843 * Hook our interrupt after all initialization is complete. 844 */ 845 error = bus_setup_intr(dev, sc->fxp_res[1], INTR_TYPE_NET | INTR_MPSAFE, 846 NULL, fxp_intr, sc, &sc->ih); 847 if (error) { 848 device_printf(dev, "could not setup irq\n"); 849 ether_ifdetach(sc->ifp); 850 goto fail; 851 } 852 853 /* 854 * Configure hardware to reject magic frames otherwise 855 * system will hang on recipt of magic frames. 856 */ 857 if ((sc->flags & FXP_FLAG_WOLCAP) != 0) { 858 FXP_LOCK(sc); 859 /* Clear wakeup events. */ 860 CSR_READ_1(sc, FXP_CSR_PMDR); 861 fxp_init_body(sc); 862 fxp_stop(sc); 863 FXP_UNLOCK(sc); 864 } 865 866 fail: 867 if (error) 868 fxp_release(sc); 869 return (error); 870 } 871 872 /* 873 * Release all resources. The softc lock should not be held and the 874 * interrupt should already be torn down. 875 */ 876 static void 877 fxp_release(struct fxp_softc *sc) 878 { 879 struct fxp_rx *rxp; 880 struct fxp_tx *txp; 881 int i; 882 883 FXP_LOCK_ASSERT(sc, MA_NOTOWNED); 884 KASSERT(sc->ih == NULL, 885 ("fxp_release() called with intr handle still active")); 886 if (sc->miibus) 887 device_delete_child(sc->dev, sc->miibus); 888 bus_generic_detach(sc->dev); 889 ifmedia_removeall(&sc->sc_media); 890 if (sc->fxp_desc.cbl_list) { 891 bus_dmamap_unload(sc->cbl_tag, sc->cbl_map); 892 bus_dmamem_free(sc->cbl_tag, sc->fxp_desc.cbl_list, 893 sc->cbl_map); 894 } 895 if (sc->fxp_stats) { 896 bus_dmamap_unload(sc->fxp_stag, sc->fxp_smap); 897 bus_dmamem_free(sc->fxp_stag, sc->fxp_stats, sc->fxp_smap); 898 } 899 if (sc->mcsp) { 900 bus_dmamap_unload(sc->mcs_tag, sc->mcs_map); 901 bus_dmamem_free(sc->mcs_tag, sc->mcsp, sc->mcs_map); 902 } 903 bus_release_resources(sc->dev, sc->fxp_spec, sc->fxp_res); 904 if (sc->fxp_mtag) { 905 for (i = 0; i < FXP_NRFABUFS; i++) { 906 rxp = &sc->fxp_desc.rx_list[i]; 907 if (rxp->rx_mbuf != NULL) { 908 bus_dmamap_sync(sc->fxp_mtag, rxp->rx_map, 909 BUS_DMASYNC_POSTREAD); 910 bus_dmamap_unload(sc->fxp_mtag, rxp->rx_map); 911 m_freem(rxp->rx_mbuf); 912 } 913 bus_dmamap_destroy(sc->fxp_mtag, rxp->rx_map); 914 } 915 bus_dmamap_destroy(sc->fxp_mtag, sc->spare_map); 916 for (i = 0; i < FXP_NTXCB; i++) { 917 txp = &sc->fxp_desc.tx_list[i]; 918 if (txp->tx_mbuf != NULL) { 919 bus_dmamap_sync(sc->fxp_mtag, txp->tx_map, 920 BUS_DMASYNC_POSTWRITE); 921 bus_dmamap_unload(sc->fxp_mtag, txp->tx_map); 922 m_freem(txp->tx_mbuf); 923 } 924 bus_dmamap_destroy(sc->fxp_mtag, txp->tx_map); 925 } 926 bus_dma_tag_destroy(sc->fxp_mtag); 927 } 928 if (sc->fxp_stag) 929 bus_dma_tag_destroy(sc->fxp_stag); 930 if (sc->cbl_tag) 931 bus_dma_tag_destroy(sc->cbl_tag); 932 if (sc->mcs_tag) 933 bus_dma_tag_destroy(sc->mcs_tag); 934 if (sc->ifp) 935 if_free(sc->ifp); 936 937 mtx_destroy(&sc->sc_mtx); 938 } 939 940 /* 941 * Detach interface. 942 */ 943 static int 944 fxp_detach(device_t dev) 945 { 946 struct fxp_softc *sc = device_get_softc(dev); 947 948 #ifdef DEVICE_POLLING 949 if (sc->ifp->if_capenable & IFCAP_POLLING) 950 ether_poll_deregister(sc->ifp); 951 #endif 952 953 FXP_LOCK(sc); 954 sc->suspended = 1; /* Do same thing as we do for suspend */ 955 /* 956 * Stop DMA and drop transmit queue, but disable interrupts first. 957 */ 958 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE); 959 fxp_stop(sc); 960 FXP_UNLOCK(sc); 961 callout_drain(&sc->stat_ch); 962 963 /* 964 * Close down routes etc. 965 */ 966 ether_ifdetach(sc->ifp); 967 968 /* 969 * Unhook interrupt before dropping lock. This is to prevent 970 * races with fxp_intr(). 971 */ 972 bus_teardown_intr(sc->dev, sc->fxp_res[1], sc->ih); 973 sc->ih = NULL; 974 975 /* Release our allocated resources. */ 976 fxp_release(sc); 977 return (0); 978 } 979 980 /* 981 * Device shutdown routine. Called at system shutdown after sync. The 982 * main purpose of this routine is to shut off receiver DMA so that 983 * kernel memory doesn't get clobbered during warmboot. 984 */ 985 static int 986 fxp_shutdown(device_t dev) 987 { 988 989 /* 990 * Make sure that DMA is disabled prior to reboot. Not doing 991 * do could allow DMA to corrupt kernel memory during the 992 * reboot before the driver initializes. 993 */ 994 return (fxp_suspend(dev)); 995 } 996 997 /* 998 * Device suspend routine. Stop the interface and save some PCI 999 * settings in case the BIOS doesn't restore them properly on 1000 * resume. 1001 */ 1002 static int 1003 fxp_suspend(device_t dev) 1004 { 1005 struct fxp_softc *sc = device_get_softc(dev); 1006 struct ifnet *ifp; 1007 int pmc; 1008 uint16_t pmstat; 1009 1010 FXP_LOCK(sc); 1011 1012 ifp = sc->ifp; 1013 if (pci_find_extcap(sc->dev, PCIY_PMG, &pmc) == 0) { 1014 pmstat = pci_read_config(sc->dev, pmc + PCIR_POWER_STATUS, 2); 1015 pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE); 1016 if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0) { 1017 /* Request PME. */ 1018 pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE; 1019 sc->flags |= FXP_FLAG_WOL; 1020 /* Reconfigure hardware to accept magic frames. */ 1021 fxp_init_body(sc); 1022 } 1023 pci_write_config(sc->dev, pmc + PCIR_POWER_STATUS, pmstat, 2); 1024 } 1025 fxp_stop(sc); 1026 1027 sc->suspended = 1; 1028 1029 FXP_UNLOCK(sc); 1030 return (0); 1031 } 1032 1033 /* 1034 * Device resume routine. re-enable busmastering, and restart the interface if 1035 * appropriate. 1036 */ 1037 static int 1038 fxp_resume(device_t dev) 1039 { 1040 struct fxp_softc *sc = device_get_softc(dev); 1041 struct ifnet *ifp = sc->ifp; 1042 int pmc; 1043 uint16_t pmstat; 1044 1045 FXP_LOCK(sc); 1046 1047 if (pci_find_extcap(sc->dev, PCIY_PMG, &pmc) == 0) { 1048 sc->flags &= ~FXP_FLAG_WOL; 1049 pmstat = pci_read_config(sc->dev, pmc + PCIR_POWER_STATUS, 2); 1050 /* Disable PME and clear PME status. */ 1051 pmstat &= ~PCIM_PSTAT_PMEENABLE; 1052 pci_write_config(sc->dev, pmc + PCIR_POWER_STATUS, pmstat, 2); 1053 if ((sc->flags & FXP_FLAG_WOLCAP) != 0) { 1054 /* Clear wakeup events. */ 1055 CSR_READ_1(sc, FXP_CSR_PMDR); 1056 } 1057 } 1058 1059 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET); 1060 DELAY(10); 1061 1062 /* reinitialize interface if necessary */ 1063 if (ifp->if_flags & IFF_UP) 1064 fxp_init_body(sc); 1065 1066 sc->suspended = 0; 1067 1068 FXP_UNLOCK(sc); 1069 return (0); 1070 } 1071 1072 static void 1073 fxp_eeprom_shiftin(struct fxp_softc *sc, int data, int length) 1074 { 1075 uint16_t reg; 1076 int x; 1077 1078 /* 1079 * Shift in data. 1080 */ 1081 for (x = 1 << (length - 1); x; x >>= 1) { 1082 if (data & x) 1083 reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI; 1084 else 1085 reg = FXP_EEPROM_EECS; 1086 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 1087 DELAY(1); 1088 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK); 1089 DELAY(1); 1090 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 1091 DELAY(1); 1092 } 1093 } 1094 1095 /* 1096 * Read from the serial EEPROM. Basically, you manually shift in 1097 * the read opcode (one bit at a time) and then shift in the address, 1098 * and then you shift out the data (all of this one bit at a time). 1099 * The word size is 16 bits, so you have to provide the address for 1100 * every 16 bits of data. 1101 */ 1102 static uint16_t 1103 fxp_eeprom_getword(struct fxp_softc *sc, int offset, int autosize) 1104 { 1105 uint16_t reg, data; 1106 int x; 1107 1108 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 1109 /* 1110 * Shift in read opcode. 1111 */ 1112 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_READ, 3); 1113 /* 1114 * Shift in address. 1115 */ 1116 data = 0; 1117 for (x = 1 << (sc->eeprom_size - 1); x; x >>= 1) { 1118 if (offset & x) 1119 reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI; 1120 else 1121 reg = FXP_EEPROM_EECS; 1122 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 1123 DELAY(1); 1124 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK); 1125 DELAY(1); 1126 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 1127 DELAY(1); 1128 reg = CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO; 1129 data++; 1130 if (autosize && reg == 0) { 1131 sc->eeprom_size = data; 1132 break; 1133 } 1134 } 1135 /* 1136 * Shift out data. 1137 */ 1138 data = 0; 1139 reg = FXP_EEPROM_EECS; 1140 for (x = 1 << 15; x; x >>= 1) { 1141 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK); 1142 DELAY(1); 1143 if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO) 1144 data |= x; 1145 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 1146 DELAY(1); 1147 } 1148 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 1149 DELAY(1); 1150 1151 return (data); 1152 } 1153 1154 static void 1155 fxp_eeprom_putword(struct fxp_softc *sc, int offset, uint16_t data) 1156 { 1157 int i; 1158 1159 /* 1160 * Erase/write enable. 1161 */ 1162 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 1163 fxp_eeprom_shiftin(sc, 0x4, 3); 1164 fxp_eeprom_shiftin(sc, 0x03 << (sc->eeprom_size - 2), sc->eeprom_size); 1165 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 1166 DELAY(1); 1167 /* 1168 * Shift in write opcode, address, data. 1169 */ 1170 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 1171 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_WRITE, 3); 1172 fxp_eeprom_shiftin(sc, offset, sc->eeprom_size); 1173 fxp_eeprom_shiftin(sc, data, 16); 1174 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 1175 DELAY(1); 1176 /* 1177 * Wait for EEPROM to finish up. 1178 */ 1179 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 1180 DELAY(1); 1181 for (i = 0; i < 1000; i++) { 1182 if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO) 1183 break; 1184 DELAY(50); 1185 } 1186 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 1187 DELAY(1); 1188 /* 1189 * Erase/write disable. 1190 */ 1191 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 1192 fxp_eeprom_shiftin(sc, 0x4, 3); 1193 fxp_eeprom_shiftin(sc, 0, sc->eeprom_size); 1194 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 1195 DELAY(1); 1196 } 1197 1198 /* 1199 * From NetBSD: 1200 * 1201 * Figure out EEPROM size. 1202 * 1203 * 559's can have either 64-word or 256-word EEPROMs, the 558 1204 * datasheet only talks about 64-word EEPROMs, and the 557 datasheet 1205 * talks about the existance of 16 to 256 word EEPROMs. 1206 * 1207 * The only known sizes are 64 and 256, where the 256 version is used 1208 * by CardBus cards to store CIS information. 1209 * 1210 * The address is shifted in msb-to-lsb, and after the last 1211 * address-bit the EEPROM is supposed to output a `dummy zero' bit, 1212 * after which follows the actual data. We try to detect this zero, by 1213 * probing the data-out bit in the EEPROM control register just after 1214 * having shifted in a bit. If the bit is zero, we assume we've 1215 * shifted enough address bits. The data-out should be tri-state, 1216 * before this, which should translate to a logical one. 1217 */ 1218 static void 1219 fxp_autosize_eeprom(struct fxp_softc *sc) 1220 { 1221 1222 /* guess maximum size of 256 words */ 1223 sc->eeprom_size = 8; 1224 1225 /* autosize */ 1226 (void) fxp_eeprom_getword(sc, 0, 1); 1227 } 1228 1229 static void 1230 fxp_read_eeprom(struct fxp_softc *sc, u_short *data, int offset, int words) 1231 { 1232 int i; 1233 1234 for (i = 0; i < words; i++) 1235 data[i] = fxp_eeprom_getword(sc, offset + i, 0); 1236 } 1237 1238 static void 1239 fxp_write_eeprom(struct fxp_softc *sc, u_short *data, int offset, int words) 1240 { 1241 int i; 1242 1243 for (i = 0; i < words; i++) 1244 fxp_eeprom_putword(sc, offset + i, data[i]); 1245 } 1246 1247 /* 1248 * Grab the softc lock and call the real fxp_start_body() routine 1249 */ 1250 static void 1251 fxp_start(struct ifnet *ifp) 1252 { 1253 struct fxp_softc *sc = ifp->if_softc; 1254 1255 FXP_LOCK(sc); 1256 fxp_start_body(ifp); 1257 FXP_UNLOCK(sc); 1258 } 1259 1260 /* 1261 * Start packet transmission on the interface. 1262 * This routine must be called with the softc lock held, and is an 1263 * internal entry point only. 1264 */ 1265 static void 1266 fxp_start_body(struct ifnet *ifp) 1267 { 1268 struct fxp_softc *sc = ifp->if_softc; 1269 struct mbuf *mb_head; 1270 int txqueued; 1271 1272 FXP_LOCK_ASSERT(sc, MA_OWNED); 1273 1274 /* 1275 * See if we need to suspend xmit until the multicast filter 1276 * has been reprogrammed (which can only be done at the head 1277 * of the command chain). 1278 */ 1279 if (sc->need_mcsetup) 1280 return; 1281 1282 if (sc->tx_queued > FXP_NTXCB_HIWAT) 1283 fxp_txeof(sc); 1284 /* 1285 * We're finished if there is nothing more to add to the list or if 1286 * we're all filled up with buffers to transmit. 1287 * NOTE: One TxCB is reserved to guarantee that fxp_mc_setup() can add 1288 * a NOP command when needed. 1289 */ 1290 txqueued = 0; 1291 while (!IFQ_DRV_IS_EMPTY(&ifp->if_snd) && 1292 sc->tx_queued < FXP_NTXCB - 1) { 1293 1294 /* 1295 * Grab a packet to transmit. 1296 */ 1297 IFQ_DRV_DEQUEUE(&ifp->if_snd, mb_head); 1298 if (mb_head == NULL) 1299 break; 1300 1301 if (fxp_encap(sc, &mb_head)) { 1302 if (mb_head == NULL) 1303 break; 1304 IFQ_DRV_PREPEND(&ifp->if_snd, mb_head); 1305 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 1306 } 1307 txqueued++; 1308 /* 1309 * Pass packet to bpf if there is a listener. 1310 */ 1311 BPF_MTAP(ifp, mb_head); 1312 } 1313 1314 /* 1315 * We're finished. If we added to the list, issue a RESUME to get DMA 1316 * going again if suspended. 1317 */ 1318 if (txqueued > 0) { 1319 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE); 1320 fxp_scb_wait(sc); 1321 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_RESUME); 1322 /* 1323 * Set a 5 second timer just in case we don't hear 1324 * from the card again. 1325 */ 1326 sc->watchdog_timer = 5; 1327 } 1328 } 1329 1330 static int 1331 fxp_encap(struct fxp_softc *sc, struct mbuf **m_head) 1332 { 1333 struct ifnet *ifp; 1334 struct mbuf *m; 1335 struct fxp_tx *txp; 1336 struct fxp_cb_tx *cbp; 1337 struct tcphdr *tcp; 1338 bus_dma_segment_t segs[FXP_NTXSEG]; 1339 int error, i, nseg, tcp_payload; 1340 1341 FXP_LOCK_ASSERT(sc, MA_OWNED); 1342 ifp = sc->ifp; 1343 1344 tcp_payload = 0; 1345 tcp = NULL; 1346 /* 1347 * Get pointer to next available tx desc. 1348 */ 1349 txp = sc->fxp_desc.tx_last->tx_next; 1350 1351 /* 1352 * A note in Appendix B of the Intel 8255x 10/100 Mbps 1353 * Ethernet Controller Family Open Source Software 1354 * Developer Manual says: 1355 * Using software parsing is only allowed with legal 1356 * TCP/IP or UDP/IP packets. 1357 * ... 1358 * For all other datagrams, hardware parsing must 1359 * be used. 1360 * Software parsing appears to truncate ICMP and 1361 * fragmented UDP packets that contain one to three 1362 * bytes in the second (and final) mbuf of the packet. 1363 */ 1364 if (sc->flags & FXP_FLAG_EXT_RFA) 1365 txp->tx_cb->ipcb_ip_activation_high = 1366 FXP_IPCB_HARDWAREPARSING_ENABLE; 1367 1368 m = *m_head; 1369 /* 1370 * Deal with TCP/IP checksum offload. Note that 1371 * in order for TCP checksum offload to work, 1372 * the pseudo header checksum must have already 1373 * been computed and stored in the checksum field 1374 * in the TCP header. The stack should have 1375 * already done this for us. 1376 */ 1377 if (m->m_pkthdr.csum_flags & FXP_CSUM_FEATURES) { 1378 txp->tx_cb->ipcb_ip_schedule = FXP_IPCB_TCPUDP_CHECKSUM_ENABLE; 1379 if (m->m_pkthdr.csum_flags & CSUM_TCP) 1380 txp->tx_cb->ipcb_ip_schedule |= FXP_IPCB_TCP_PACKET; 1381 1382 #ifdef FXP_IP_CSUM_WAR 1383 /* 1384 * XXX The 82550 chip appears to have trouble 1385 * dealing with IP header checksums in very small 1386 * datagrams, namely fragments from 1 to 3 bytes 1387 * in size. For example, say you want to transmit 1388 * a UDP packet of 1473 bytes. The packet will be 1389 * fragmented over two IP datagrams, the latter 1390 * containing only one byte of data. The 82550 will 1391 * botch the header checksum on the 1-byte fragment. 1392 * As long as the datagram contains 4 or more bytes 1393 * of data, you're ok. 1394 * 1395 * The following code attempts to work around this 1396 * problem: if the datagram is less than 38 bytes 1397 * in size (14 bytes ether header, 20 bytes IP header, 1398 * plus 4 bytes of data), we punt and compute the IP 1399 * header checksum by hand. This workaround doesn't 1400 * work very well, however, since it can be fooled 1401 * by things like VLAN tags and IP options that make 1402 * the header sizes/offsets vary. 1403 */ 1404 1405 if (m->m_pkthdr.csum_flags & CSUM_IP) { 1406 if (m->m_pkthdr.len < 38) { 1407 struct ip *ip; 1408 m->m_data += ETHER_HDR_LEN; 1409 ip = mtod(m, struct ip *); 1410 ip->ip_sum = in_cksum(m, ip->ip_hl << 2); 1411 m->m_data -= ETHER_HDR_LEN; 1412 m->m_pkthdr.csum_flags &= ~CSUM_IP; 1413 } else { 1414 txp->tx_cb->ipcb_ip_activation_high = 1415 FXP_IPCB_HARDWAREPARSING_ENABLE; 1416 txp->tx_cb->ipcb_ip_schedule |= 1417 FXP_IPCB_IP_CHECKSUM_ENABLE; 1418 } 1419 } 1420 #endif 1421 } 1422 1423 if (m->m_pkthdr.csum_flags & CSUM_TSO) { 1424 /* 1425 * 82550/82551 requires ethernet/IP/TCP headers must be 1426 * contained in the first active transmit buffer. 1427 */ 1428 struct ether_header *eh; 1429 struct ip *ip; 1430 uint32_t ip_off, poff; 1431 1432 if (M_WRITABLE(*m_head) == 0) { 1433 /* Get a writable copy. */ 1434 m = m_dup(*m_head, M_DONTWAIT); 1435 m_freem(*m_head); 1436 if (m == NULL) { 1437 *m_head = NULL; 1438 return (ENOBUFS); 1439 } 1440 *m_head = m; 1441 } 1442 ip_off = sizeof(struct ether_header); 1443 m = m_pullup(*m_head, ip_off); 1444 if (m == NULL) { 1445 *m_head = NULL; 1446 return (ENOBUFS); 1447 } 1448 eh = mtod(m, struct ether_header *); 1449 /* Check the existence of VLAN tag. */ 1450 if (eh->ether_type == htons(ETHERTYPE_VLAN)) { 1451 ip_off = sizeof(struct ether_vlan_header); 1452 m = m_pullup(m, ip_off); 1453 if (m == NULL) { 1454 *m_head = NULL; 1455 return (ENOBUFS); 1456 } 1457 } 1458 m = m_pullup(m, ip_off + sizeof(struct ip)); 1459 if (m == NULL) { 1460 *m_head = NULL; 1461 return (ENOBUFS); 1462 } 1463 ip = (struct ip *)(mtod(m, char *) + ip_off); 1464 poff = ip_off + (ip->ip_hl << 2); 1465 m = m_pullup(m, poff + sizeof(struct tcphdr)); 1466 if (m == NULL) { 1467 *m_head = NULL; 1468 return (ENOBUFS); 1469 } 1470 tcp = (struct tcphdr *)(mtod(m, char *) + poff); 1471 m = m_pullup(m, poff + sizeof(struct tcphdr) + tcp->th_off); 1472 if (m == NULL) { 1473 *m_head = NULL; 1474 return (ENOBUFS); 1475 } 1476 1477 /* 1478 * Since 82550/82551 doesn't modify IP length and pseudo 1479 * checksum in the first frame driver should compute it. 1480 */ 1481 ip->ip_sum = 0; 1482 ip->ip_len = htons(ifp->if_mtu); 1483 tcp->th_sum = in_pseudo(ip->ip_src.s_addr, ip->ip_dst.s_addr, 1484 htons(IPPROTO_TCP + (tcp->th_off << 2) + 1485 m->m_pkthdr.tso_segsz)); 1486 /* Compute total TCP payload. */ 1487 tcp_payload = m->m_pkthdr.len - ip_off - (ip->ip_hl << 2); 1488 tcp_payload -= tcp->th_off << 2; 1489 *m_head = m; 1490 } 1491 1492 error = bus_dmamap_load_mbuf_sg(sc->fxp_mtag, txp->tx_map, *m_head, 1493 segs, &nseg, 0); 1494 if (error == EFBIG) { 1495 m = m_collapse(*m_head, M_DONTWAIT, sc->maxtxseg); 1496 if (m == NULL) { 1497 m_freem(*m_head); 1498 *m_head = NULL; 1499 return (ENOMEM); 1500 } 1501 *m_head = m; 1502 error = bus_dmamap_load_mbuf_sg(sc->fxp_mtag, txp->tx_map, 1503 *m_head, segs, &nseg, 0); 1504 if (error != 0) { 1505 m_freem(*m_head); 1506 *m_head = NULL; 1507 return (ENOMEM); 1508 } 1509 } else if (error != 0) 1510 return (error); 1511 if (nseg == 0) { 1512 m_freem(*m_head); 1513 *m_head = NULL; 1514 return (EIO); 1515 } 1516 1517 KASSERT(nseg <= sc->maxtxseg, ("too many DMA segments")); 1518 bus_dmamap_sync(sc->fxp_mtag, txp->tx_map, BUS_DMASYNC_PREWRITE); 1519 1520 cbp = txp->tx_cb; 1521 for (i = 0; i < nseg; i++) { 1522 /* 1523 * If this is an 82550/82551, then we're using extended 1524 * TxCBs _and_ we're using checksum offload. This means 1525 * that the TxCB is really an IPCB. One major difference 1526 * between the two is that with plain extended TxCBs, 1527 * the bottom half of the TxCB contains two entries from 1528 * the TBD array, whereas IPCBs contain just one entry: 1529 * one entry (8 bytes) has been sacrificed for the TCP/IP 1530 * checksum offload control bits. So to make things work 1531 * right, we have to start filling in the TBD array 1532 * starting from a different place depending on whether 1533 * the chip is an 82550/82551 or not. 1534 */ 1535 if (sc->flags & FXP_FLAG_EXT_RFA) { 1536 cbp->tbd[i + 2].tb_addr = htole32(segs[i].ds_addr); 1537 cbp->tbd[i + 2].tb_size = htole32(segs[i].ds_len); 1538 } else { 1539 cbp->tbd[i].tb_addr = htole32(segs[i].ds_addr); 1540 cbp->tbd[i].tb_size = htole32(segs[i].ds_len); 1541 } 1542 } 1543 if (sc->flags & FXP_FLAG_EXT_RFA) { 1544 /* Configure dynamic TBD for 82550/82551. */ 1545 cbp->tbd_number = 0xFF; 1546 cbp->tbd[nseg + 1].tb_size |= htole32(0x8000); 1547 } else 1548 cbp->tbd_number = nseg; 1549 /* Configure TSO. */ 1550 if (m->m_pkthdr.csum_flags & CSUM_TSO) { 1551 cbp->tbd[-1].tb_size = htole32(m->m_pkthdr.tso_segsz << 16); 1552 cbp->tbd[1].tb_size = htole32(tcp_payload << 16); 1553 cbp->ipcb_ip_schedule |= FXP_IPCB_LARGESEND_ENABLE | 1554 FXP_IPCB_IP_CHECKSUM_ENABLE | 1555 FXP_IPCB_TCP_PACKET | 1556 FXP_IPCB_TCPUDP_CHECKSUM_ENABLE; 1557 } 1558 1559 txp->tx_mbuf = m; 1560 txp->tx_cb->cb_status = 0; 1561 txp->tx_cb->byte_count = 0; 1562 if (sc->tx_queued != FXP_CXINT_THRESH - 1) 1563 txp->tx_cb->cb_command = 1564 htole16(sc->tx_cmd | FXP_CB_COMMAND_SF | 1565 FXP_CB_COMMAND_S); 1566 else 1567 txp->tx_cb->cb_command = 1568 htole16(sc->tx_cmd | FXP_CB_COMMAND_SF | 1569 FXP_CB_COMMAND_S | FXP_CB_COMMAND_I); 1570 if ((m->m_pkthdr.csum_flags & CSUM_TSO) == 0) 1571 txp->tx_cb->tx_threshold = tx_threshold; 1572 1573 /* 1574 * Advance the end of list forward. 1575 */ 1576 1577 #ifdef __alpha__ 1578 /* 1579 * On platforms which can't access memory in 16-bit 1580 * granularities, we must prevent the card from DMA'ing 1581 * up the status while we update the command field. 1582 * This could cause us to overwrite the completion status. 1583 * XXX This is probably bogus and we're _not_ looking 1584 * for atomicity here. 1585 */ 1586 atomic_clear_16(&sc->fxp_desc.tx_last->tx_cb->cb_command, 1587 htole16(FXP_CB_COMMAND_S)); 1588 #else 1589 sc->fxp_desc.tx_last->tx_cb->cb_command &= htole16(~FXP_CB_COMMAND_S); 1590 #endif /*__alpha__*/ 1591 sc->fxp_desc.tx_last = txp; 1592 1593 /* 1594 * Advance the beginning of the list forward if there are 1595 * no other packets queued (when nothing is queued, tx_first 1596 * sits on the last TxCB that was sent out). 1597 */ 1598 if (sc->tx_queued == 0) 1599 sc->fxp_desc.tx_first = txp; 1600 1601 sc->tx_queued++; 1602 1603 return (0); 1604 } 1605 1606 #ifdef DEVICE_POLLING 1607 static poll_handler_t fxp_poll; 1608 1609 static void 1610 fxp_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 1611 { 1612 struct fxp_softc *sc = ifp->if_softc; 1613 uint8_t statack; 1614 1615 FXP_LOCK(sc); 1616 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) { 1617 FXP_UNLOCK(sc); 1618 return; 1619 } 1620 1621 statack = FXP_SCB_STATACK_CXTNO | FXP_SCB_STATACK_CNA | 1622 FXP_SCB_STATACK_FR; 1623 if (cmd == POLL_AND_CHECK_STATUS) { 1624 uint8_t tmp; 1625 1626 tmp = CSR_READ_1(sc, FXP_CSR_SCB_STATACK); 1627 if (tmp == 0xff || tmp == 0) { 1628 FXP_UNLOCK(sc); 1629 return; /* nothing to do */ 1630 } 1631 tmp &= ~statack; 1632 /* ack what we can */ 1633 if (tmp != 0) 1634 CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, tmp); 1635 statack |= tmp; 1636 } 1637 fxp_intr_body(sc, ifp, statack, count); 1638 FXP_UNLOCK(sc); 1639 } 1640 #endif /* DEVICE_POLLING */ 1641 1642 /* 1643 * Process interface interrupts. 1644 */ 1645 static void 1646 fxp_intr(void *xsc) 1647 { 1648 struct fxp_softc *sc = xsc; 1649 struct ifnet *ifp = sc->ifp; 1650 uint8_t statack; 1651 1652 FXP_LOCK(sc); 1653 if (sc->suspended) { 1654 FXP_UNLOCK(sc); 1655 return; 1656 } 1657 1658 #ifdef DEVICE_POLLING 1659 if (ifp->if_capenable & IFCAP_POLLING) { 1660 FXP_UNLOCK(sc); 1661 return; 1662 } 1663 #endif 1664 while ((statack = CSR_READ_1(sc, FXP_CSR_SCB_STATACK)) != 0) { 1665 /* 1666 * It should not be possible to have all bits set; the 1667 * FXP_SCB_INTR_SWI bit always returns 0 on a read. If 1668 * all bits are set, this may indicate that the card has 1669 * been physically ejected, so ignore it. 1670 */ 1671 if (statack == 0xff) { 1672 FXP_UNLOCK(sc); 1673 return; 1674 } 1675 1676 /* 1677 * First ACK all the interrupts in this pass. 1678 */ 1679 CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, statack); 1680 fxp_intr_body(sc, ifp, statack, -1); 1681 } 1682 FXP_UNLOCK(sc); 1683 } 1684 1685 static void 1686 fxp_txeof(struct fxp_softc *sc) 1687 { 1688 struct ifnet *ifp; 1689 struct fxp_tx *txp; 1690 1691 ifp = sc->ifp; 1692 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREREAD); 1693 for (txp = sc->fxp_desc.tx_first; sc->tx_queued && 1694 (le16toh(txp->tx_cb->cb_status) & FXP_CB_STATUS_C) != 0; 1695 txp = txp->tx_next) { 1696 if (txp->tx_mbuf != NULL) { 1697 bus_dmamap_sync(sc->fxp_mtag, txp->tx_map, 1698 BUS_DMASYNC_POSTWRITE); 1699 bus_dmamap_unload(sc->fxp_mtag, txp->tx_map); 1700 m_freem(txp->tx_mbuf); 1701 txp->tx_mbuf = NULL; 1702 /* clear this to reset csum offload bits */ 1703 txp->tx_cb->tbd[0].tb_addr = 0; 1704 } 1705 sc->tx_queued--; 1706 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1707 } 1708 sc->fxp_desc.tx_first = txp; 1709 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE); 1710 if (sc->tx_queued == 0) { 1711 sc->watchdog_timer = 0; 1712 if (sc->need_mcsetup) 1713 fxp_mc_setup(sc); 1714 } 1715 } 1716 1717 static void 1718 fxp_rxcsum(struct fxp_softc *sc, struct ifnet *ifp, struct mbuf *m, 1719 uint16_t status, int pos) 1720 { 1721 struct ether_header *eh; 1722 struct ip *ip; 1723 struct udphdr *uh; 1724 int32_t hlen, len, pktlen, temp32; 1725 uint16_t csum, *opts; 1726 1727 if ((sc->flags & FXP_FLAG_82559_RXCSUM) == 0) { 1728 if ((status & FXP_RFA_STATUS_PARSE) != 0) { 1729 if (status & FXP_RFDX_CS_IP_CSUM_BIT_VALID) 1730 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 1731 if (status & FXP_RFDX_CS_IP_CSUM_VALID) 1732 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 1733 if ((status & FXP_RFDX_CS_TCPUDP_CSUM_BIT_VALID) && 1734 (status & FXP_RFDX_CS_TCPUDP_CSUM_VALID)) { 1735 m->m_pkthdr.csum_flags |= CSUM_DATA_VALID | 1736 CSUM_PSEUDO_HDR; 1737 m->m_pkthdr.csum_data = 0xffff; 1738 } 1739 } 1740 return; 1741 } 1742 1743 pktlen = m->m_pkthdr.len; 1744 if (pktlen < sizeof(struct ether_header) + sizeof(struct ip)) 1745 return; 1746 eh = mtod(m, struct ether_header *); 1747 if (eh->ether_type != htons(ETHERTYPE_IP)) 1748 return; 1749 ip = (struct ip *)(eh + 1); 1750 if (ip->ip_v != IPVERSION) 1751 return; 1752 1753 hlen = ip->ip_hl << 2; 1754 pktlen -= sizeof(struct ether_header); 1755 if (hlen < sizeof(struct ip)) 1756 return; 1757 if (ntohs(ip->ip_len) < hlen) 1758 return; 1759 if (ntohs(ip->ip_len) != pktlen) 1760 return; 1761 if (ip->ip_off & htons(IP_MF | IP_OFFMASK)) 1762 return; /* can't handle fragmented packet */ 1763 1764 switch (ip->ip_p) { 1765 case IPPROTO_TCP: 1766 if (pktlen < (hlen + sizeof(struct tcphdr))) 1767 return; 1768 break; 1769 case IPPROTO_UDP: 1770 if (pktlen < (hlen + sizeof(struct udphdr))) 1771 return; 1772 uh = (struct udphdr *)((caddr_t)ip + hlen); 1773 if (uh->uh_sum == 0) 1774 return; /* no checksum */ 1775 break; 1776 default: 1777 return; 1778 } 1779 /* Extract computed checksum. */ 1780 csum = be16dec(mtod(m, char *) + pos); 1781 /* checksum fixup for IP options */ 1782 len = hlen - sizeof(struct ip); 1783 if (len > 0) { 1784 opts = (uint16_t *)(ip + 1); 1785 for (; len > 0; len -= sizeof(uint16_t), opts++) { 1786 temp32 = csum - *opts; 1787 temp32 = (temp32 >> 16) + (temp32 & 65535); 1788 csum = temp32 & 65535; 1789 } 1790 } 1791 m->m_pkthdr.csum_flags |= CSUM_DATA_VALID; 1792 m->m_pkthdr.csum_data = csum; 1793 } 1794 1795 static void 1796 fxp_intr_body(struct fxp_softc *sc, struct ifnet *ifp, uint8_t statack, 1797 int count) 1798 { 1799 struct mbuf *m; 1800 struct fxp_rx *rxp; 1801 struct fxp_rfa *rfa; 1802 int rnr = (statack & FXP_SCB_STATACK_RNR) ? 1 : 0; 1803 uint16_t status; 1804 1805 FXP_LOCK_ASSERT(sc, MA_OWNED); 1806 if (rnr) 1807 sc->rnr++; 1808 #ifdef DEVICE_POLLING 1809 /* Pick up a deferred RNR condition if `count' ran out last time. */ 1810 if (sc->flags & FXP_FLAG_DEFERRED_RNR) { 1811 sc->flags &= ~FXP_FLAG_DEFERRED_RNR; 1812 rnr = 1; 1813 } 1814 #endif 1815 1816 /* 1817 * Free any finished transmit mbuf chains. 1818 * 1819 * Handle the CNA event likt a CXTNO event. It used to 1820 * be that this event (control unit not ready) was not 1821 * encountered, but it is now with the SMPng modifications. 1822 * The exact sequence of events that occur when the interface 1823 * is brought up are different now, and if this event 1824 * goes unhandled, the configuration/rxfilter setup sequence 1825 * can stall for several seconds. The result is that no 1826 * packets go out onto the wire for about 5 to 10 seconds 1827 * after the interface is ifconfig'ed for the first time. 1828 */ 1829 if (statack & (FXP_SCB_STATACK_CXTNO | FXP_SCB_STATACK_CNA)) 1830 fxp_txeof(sc); 1831 1832 /* 1833 * Try to start more packets transmitting. 1834 */ 1835 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1836 fxp_start_body(ifp); 1837 1838 /* 1839 * Just return if nothing happened on the receive side. 1840 */ 1841 if (!rnr && (statack & FXP_SCB_STATACK_FR) == 0) 1842 return; 1843 1844 /* 1845 * Process receiver interrupts. If a no-resource (RNR) 1846 * condition exists, get whatever packets we can and 1847 * re-start the receiver. 1848 * 1849 * When using polling, we do not process the list to completion, 1850 * so when we get an RNR interrupt we must defer the restart 1851 * until we hit the last buffer with the C bit set. 1852 * If we run out of cycles and rfa_headm has the C bit set, 1853 * record the pending RNR in the FXP_FLAG_DEFERRED_RNR flag so 1854 * that the info will be used in the subsequent polling cycle. 1855 */ 1856 for (;;) { 1857 rxp = sc->fxp_desc.rx_head; 1858 m = rxp->rx_mbuf; 1859 rfa = (struct fxp_rfa *)(m->m_ext.ext_buf + 1860 RFA_ALIGNMENT_FUDGE); 1861 bus_dmamap_sync(sc->fxp_mtag, rxp->rx_map, 1862 BUS_DMASYNC_POSTREAD); 1863 1864 #ifdef DEVICE_POLLING /* loop at most count times if count >=0 */ 1865 if (count >= 0 && count-- == 0) { 1866 if (rnr) { 1867 /* Defer RNR processing until the next time. */ 1868 sc->flags |= FXP_FLAG_DEFERRED_RNR; 1869 rnr = 0; 1870 } 1871 break; 1872 } 1873 #endif /* DEVICE_POLLING */ 1874 1875 status = le16toh(rfa->rfa_status); 1876 if ((status & FXP_RFA_STATUS_C) == 0) 1877 break; 1878 1879 /* 1880 * Advance head forward. 1881 */ 1882 sc->fxp_desc.rx_head = rxp->rx_next; 1883 1884 /* 1885 * Add a new buffer to the receive chain. 1886 * If this fails, the old buffer is recycled 1887 * instead. 1888 */ 1889 if (fxp_new_rfabuf(sc, rxp) == 0) { 1890 int total_len; 1891 1892 /* 1893 * Fetch packet length (the top 2 bits of 1894 * actual_size are flags set by the controller 1895 * upon completion), and drop the packet in case 1896 * of bogus length or CRC errors. 1897 */ 1898 total_len = le16toh(rfa->actual_size) & 0x3fff; 1899 if ((sc->flags & FXP_FLAG_82559_RXCSUM) != 0 && 1900 (ifp->if_capenable & IFCAP_RXCSUM) != 0) { 1901 /* Adjust for appended checksum bytes. */ 1902 total_len -= 2; 1903 } 1904 if (total_len < sizeof(struct ether_header) || 1905 total_len > MCLBYTES - RFA_ALIGNMENT_FUDGE - 1906 sc->rfa_size || status & FXP_RFA_STATUS_CRC) { 1907 m_freem(m); 1908 continue; 1909 } 1910 1911 m->m_pkthdr.len = m->m_len = total_len; 1912 m->m_pkthdr.rcvif = ifp; 1913 1914 /* Do IP checksum checking. */ 1915 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0) 1916 fxp_rxcsum(sc, ifp, m, status, total_len); 1917 /* 1918 * Drop locks before calling if_input() since it 1919 * may re-enter fxp_start() in the netisr case. 1920 * This would result in a lock reversal. Better 1921 * performance might be obtained by chaining all 1922 * packets received, dropping the lock, and then 1923 * calling if_input() on each one. 1924 */ 1925 FXP_UNLOCK(sc); 1926 (*ifp->if_input)(ifp, m); 1927 FXP_LOCK(sc); 1928 } else { 1929 /* Reuse RFA and loaded DMA map. */ 1930 ifp->if_iqdrops++; 1931 fxp_discard_rfabuf(sc, rxp); 1932 } 1933 fxp_add_rfabuf(sc, rxp); 1934 } 1935 if (rnr) { 1936 fxp_scb_wait(sc); 1937 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 1938 sc->fxp_desc.rx_head->rx_addr); 1939 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_START); 1940 } 1941 } 1942 1943 /* 1944 * Update packet in/out/collision statistics. The i82557 doesn't 1945 * allow you to access these counters without doing a fairly 1946 * expensive DMA to get _all_ of the statistics it maintains, so 1947 * we do this operation here only once per second. The statistics 1948 * counters in the kernel are updated from the previous dump-stats 1949 * DMA and then a new dump-stats DMA is started. The on-chip 1950 * counters are zeroed when the DMA completes. If we can't start 1951 * the DMA immediately, we don't wait - we just prepare to read 1952 * them again next time. 1953 */ 1954 static void 1955 fxp_tick(void *xsc) 1956 { 1957 struct fxp_softc *sc = xsc; 1958 struct ifnet *ifp = sc->ifp; 1959 struct fxp_stats *sp = sc->fxp_stats; 1960 1961 FXP_LOCK_ASSERT(sc, MA_OWNED); 1962 bus_dmamap_sync(sc->fxp_stag, sc->fxp_smap, BUS_DMASYNC_POSTREAD); 1963 ifp->if_opackets += le32toh(sp->tx_good); 1964 ifp->if_collisions += le32toh(sp->tx_total_collisions); 1965 if (sp->rx_good) { 1966 ifp->if_ipackets += le32toh(sp->rx_good); 1967 sc->rx_idle_secs = 0; 1968 } else { 1969 /* 1970 * Receiver's been idle for another second. 1971 */ 1972 sc->rx_idle_secs++; 1973 } 1974 ifp->if_ierrors += 1975 le32toh(sp->rx_crc_errors) + 1976 le32toh(sp->rx_alignment_errors) + 1977 le32toh(sp->rx_rnr_errors) + 1978 le32toh(sp->rx_overrun_errors); 1979 /* 1980 * If any transmit underruns occured, bump up the transmit 1981 * threshold by another 512 bytes (64 * 8). 1982 */ 1983 if (sp->tx_underruns) { 1984 ifp->if_oerrors += le32toh(sp->tx_underruns); 1985 if (tx_threshold < 192) 1986 tx_threshold += 64; 1987 } 1988 1989 /* 1990 * Release any xmit buffers that have completed DMA. This isn't 1991 * strictly necessary to do here, but it's advantagous for mbufs 1992 * with external storage to be released in a timely manner rather 1993 * than being defered for a potentially long time. This limits 1994 * the delay to a maximum of one second. 1995 */ 1996 fxp_txeof(sc); 1997 1998 /* 1999 * If we haven't received any packets in FXP_MAC_RX_IDLE seconds, 2000 * then assume the receiver has locked up and attempt to clear 2001 * the condition by reprogramming the multicast filter. This is 2002 * a work-around for a bug in the 82557 where the receiver locks 2003 * up if it gets certain types of garbage in the syncronization 2004 * bits prior to the packet header. This bug is supposed to only 2005 * occur in 10Mbps mode, but has been seen to occur in 100Mbps 2006 * mode as well (perhaps due to a 10/100 speed transition). 2007 */ 2008 if (sc->rx_idle_secs > FXP_MAX_RX_IDLE) { 2009 sc->rx_idle_secs = 0; 2010 fxp_mc_setup(sc); 2011 } 2012 /* 2013 * If there is no pending command, start another stats 2014 * dump. Otherwise punt for now. 2015 */ 2016 if (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) == 0) { 2017 /* 2018 * Start another stats dump. 2019 */ 2020 bus_dmamap_sync(sc->fxp_stag, sc->fxp_smap, 2021 BUS_DMASYNC_PREREAD); 2022 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_DUMPRESET); 2023 } else { 2024 /* 2025 * A previous command is still waiting to be accepted. 2026 * Just zero our copy of the stats and wait for the 2027 * next timer event to update them. 2028 */ 2029 sp->tx_good = 0; 2030 sp->tx_underruns = 0; 2031 sp->tx_total_collisions = 0; 2032 2033 sp->rx_good = 0; 2034 sp->rx_crc_errors = 0; 2035 sp->rx_alignment_errors = 0; 2036 sp->rx_rnr_errors = 0; 2037 sp->rx_overrun_errors = 0; 2038 } 2039 if (sc->miibus != NULL) 2040 mii_tick(device_get_softc(sc->miibus)); 2041 2042 /* 2043 * Check that chip hasn't hung. 2044 */ 2045 fxp_watchdog(sc); 2046 2047 /* 2048 * Schedule another timeout one second from now. 2049 */ 2050 callout_reset(&sc->stat_ch, hz, fxp_tick, sc); 2051 } 2052 2053 /* 2054 * Stop the interface. Cancels the statistics updater and resets 2055 * the interface. 2056 */ 2057 static void 2058 fxp_stop(struct fxp_softc *sc) 2059 { 2060 struct ifnet *ifp = sc->ifp; 2061 struct fxp_tx *txp; 2062 int i; 2063 2064 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 2065 sc->watchdog_timer = 0; 2066 2067 /* 2068 * Cancel stats updater. 2069 */ 2070 callout_stop(&sc->stat_ch); 2071 2072 /* 2073 * Preserve PCI configuration, configure, IA/multicast 2074 * setup and put RU and CU into idle state. 2075 */ 2076 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET); 2077 DELAY(50); 2078 /* Disable interrupts. */ 2079 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE); 2080 2081 /* 2082 * Release any xmit buffers. 2083 */ 2084 txp = sc->fxp_desc.tx_list; 2085 if (txp != NULL) { 2086 for (i = 0; i < FXP_NTXCB; i++) { 2087 if (txp[i].tx_mbuf != NULL) { 2088 bus_dmamap_sync(sc->fxp_mtag, txp[i].tx_map, 2089 BUS_DMASYNC_POSTWRITE); 2090 bus_dmamap_unload(sc->fxp_mtag, txp[i].tx_map); 2091 m_freem(txp[i].tx_mbuf); 2092 txp[i].tx_mbuf = NULL; 2093 /* clear this to reset csum offload bits */ 2094 txp[i].tx_cb->tbd[0].tb_addr = 0; 2095 } 2096 } 2097 } 2098 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE); 2099 sc->tx_queued = 0; 2100 } 2101 2102 /* 2103 * Watchdog/transmission transmit timeout handler. Called when a 2104 * transmission is started on the interface, but no interrupt is 2105 * received before the timeout. This usually indicates that the 2106 * card has wedged for some reason. 2107 */ 2108 static void 2109 fxp_watchdog(struct fxp_softc *sc) 2110 { 2111 2112 FXP_LOCK_ASSERT(sc, MA_OWNED); 2113 2114 if (sc->watchdog_timer == 0 || --sc->watchdog_timer) 2115 return; 2116 2117 device_printf(sc->dev, "device timeout\n"); 2118 sc->ifp->if_oerrors++; 2119 2120 fxp_init_body(sc); 2121 } 2122 2123 /* 2124 * Acquire locks and then call the real initialization function. This 2125 * is necessary because ether_ioctl() calls if_init() and this would 2126 * result in mutex recursion if the mutex was held. 2127 */ 2128 static void 2129 fxp_init(void *xsc) 2130 { 2131 struct fxp_softc *sc = xsc; 2132 2133 FXP_LOCK(sc); 2134 fxp_init_body(sc); 2135 FXP_UNLOCK(sc); 2136 } 2137 2138 /* 2139 * Perform device initialization. This routine must be called with the 2140 * softc lock held. 2141 */ 2142 static void 2143 fxp_init_body(struct fxp_softc *sc) 2144 { 2145 struct ifnet *ifp = sc->ifp; 2146 struct fxp_cb_config *cbp; 2147 struct fxp_cb_ias *cb_ias; 2148 struct fxp_cb_tx *tcbp; 2149 struct fxp_tx *txp; 2150 struct fxp_cb_mcs *mcsp; 2151 int i, prm; 2152 2153 FXP_LOCK_ASSERT(sc, MA_OWNED); 2154 /* 2155 * Cancel any pending I/O 2156 */ 2157 fxp_stop(sc); 2158 2159 /* 2160 * Issue software reset, which also unloads the microcode. 2161 */ 2162 sc->flags &= ~FXP_FLAG_UCODE; 2163 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SOFTWARE_RESET); 2164 DELAY(50); 2165 2166 prm = (ifp->if_flags & IFF_PROMISC) ? 1 : 0; 2167 2168 /* 2169 * Initialize base of CBL and RFA memory. Loading with zero 2170 * sets it up for regular linear addressing. 2171 */ 2172 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 0); 2173 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_BASE); 2174 2175 fxp_scb_wait(sc); 2176 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_BASE); 2177 2178 /* 2179 * Initialize base of dump-stats buffer. 2180 */ 2181 fxp_scb_wait(sc); 2182 bus_dmamap_sync(sc->fxp_stag, sc->fxp_smap, BUS_DMASYNC_PREREAD); 2183 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->stats_addr); 2184 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_DUMP_ADR); 2185 2186 /* 2187 * Attempt to load microcode if requested. 2188 */ 2189 if (ifp->if_flags & IFF_LINK0 && (sc->flags & FXP_FLAG_UCODE) == 0) 2190 fxp_load_ucode(sc); 2191 2192 /* 2193 * Initialize the multicast address list. 2194 */ 2195 if (fxp_mc_addrs(sc)) { 2196 mcsp = sc->mcsp; 2197 mcsp->cb_status = 0; 2198 mcsp->cb_command = 2199 htole16(FXP_CB_COMMAND_MCAS | FXP_CB_COMMAND_EL); 2200 mcsp->link_addr = 0xffffffff; 2201 /* 2202 * Start the multicast setup command. 2203 */ 2204 fxp_scb_wait(sc); 2205 bus_dmamap_sync(sc->mcs_tag, sc->mcs_map, BUS_DMASYNC_PREWRITE); 2206 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->mcs_addr); 2207 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2208 /* ...and wait for it to complete. */ 2209 fxp_dma_wait(sc, &mcsp->cb_status, sc->mcs_tag, sc->mcs_map); 2210 bus_dmamap_sync(sc->mcs_tag, sc->mcs_map, 2211 BUS_DMASYNC_POSTWRITE); 2212 } 2213 2214 /* 2215 * We temporarily use memory that contains the TxCB list to 2216 * construct the config CB. The TxCB list memory is rebuilt 2217 * later. 2218 */ 2219 cbp = (struct fxp_cb_config *)sc->fxp_desc.cbl_list; 2220 2221 /* 2222 * This bcopy is kind of disgusting, but there are a bunch of must be 2223 * zero and must be one bits in this structure and this is the easiest 2224 * way to initialize them all to proper values. 2225 */ 2226 bcopy(fxp_cb_config_template, cbp, sizeof(fxp_cb_config_template)); 2227 2228 cbp->cb_status = 0; 2229 cbp->cb_command = htole16(FXP_CB_COMMAND_CONFIG | 2230 FXP_CB_COMMAND_EL); 2231 cbp->link_addr = 0xffffffff; /* (no) next command */ 2232 cbp->byte_count = sc->flags & FXP_FLAG_EXT_RFA ? 32 : 22; 2233 cbp->rx_fifo_limit = 8; /* rx fifo threshold (32 bytes) */ 2234 cbp->tx_fifo_limit = 0; /* tx fifo threshold (0 bytes) */ 2235 cbp->adaptive_ifs = 0; /* (no) adaptive interframe spacing */ 2236 cbp->mwi_enable = sc->flags & FXP_FLAG_MWI_ENABLE ? 1 : 0; 2237 cbp->type_enable = 0; /* actually reserved */ 2238 cbp->read_align_en = sc->flags & FXP_FLAG_READ_ALIGN ? 1 : 0; 2239 cbp->end_wr_on_cl = sc->flags & FXP_FLAG_WRITE_ALIGN ? 1 : 0; 2240 cbp->rx_dma_bytecount = 0; /* (no) rx DMA max */ 2241 cbp->tx_dma_bytecount = 0; /* (no) tx DMA max */ 2242 cbp->dma_mbce = 0; /* (disable) dma max counters */ 2243 cbp->late_scb = 0; /* (don't) defer SCB update */ 2244 cbp->direct_dma_dis = 1; /* disable direct rcv dma mode */ 2245 cbp->tno_int_or_tco_en =0; /* (disable) tx not okay interrupt */ 2246 cbp->ci_int = 1; /* interrupt on CU idle */ 2247 cbp->ext_txcb_dis = sc->flags & FXP_FLAG_EXT_TXCB ? 0 : 1; 2248 cbp->ext_stats_dis = 1; /* disable extended counters */ 2249 cbp->keep_overrun_rx = 0; /* don't pass overrun frames to host */ 2250 cbp->save_bf = sc->flags & FXP_FLAG_SAVE_BAD ? 1 : prm; 2251 cbp->disc_short_rx = !prm; /* discard short packets */ 2252 cbp->underrun_retry = 1; /* retry mode (once) on DMA underrun */ 2253 cbp->two_frames = 0; /* do not limit FIFO to 2 frames */ 2254 cbp->dyn_tbd = sc->flags & FXP_FLAG_EXT_RFA ? 1 : 0; 2255 cbp->ext_rfa = sc->flags & FXP_FLAG_EXT_RFA ? 1 : 0; 2256 cbp->mediatype = sc->flags & FXP_FLAG_SERIAL_MEDIA ? 0 : 1; 2257 cbp->csma_dis = 0; /* (don't) disable link */ 2258 cbp->tcp_udp_cksum = ((sc->flags & FXP_FLAG_82559_RXCSUM) != 0 && 2259 (ifp->if_capenable & IFCAP_RXCSUM) != 0) ? 1 : 0; 2260 cbp->vlan_tco = 0; /* (don't) enable vlan wakeup */ 2261 cbp->link_wake_en = 0; /* (don't) assert PME# on link change */ 2262 cbp->arp_wake_en = 0; /* (don't) assert PME# on arp */ 2263 cbp->mc_wake_en = 0; /* (don't) enable PME# on mcmatch */ 2264 cbp->nsai = 1; /* (don't) disable source addr insert */ 2265 cbp->preamble_length = 2; /* (7 byte) preamble */ 2266 cbp->loopback = 0; /* (don't) loopback */ 2267 cbp->linear_priority = 0; /* (normal CSMA/CD operation) */ 2268 cbp->linear_pri_mode = 0; /* (wait after xmit only) */ 2269 cbp->interfrm_spacing = 6; /* (96 bits of) interframe spacing */ 2270 cbp->promiscuous = prm; /* promiscuous mode */ 2271 cbp->bcast_disable = 0; /* (don't) disable broadcasts */ 2272 cbp->wait_after_win = 0; /* (don't) enable modified backoff alg*/ 2273 cbp->ignore_ul = 0; /* consider U/L bit in IA matching */ 2274 cbp->crc16_en = 0; /* (don't) enable crc-16 algorithm */ 2275 cbp->crscdt = sc->flags & FXP_FLAG_SERIAL_MEDIA ? 1 : 0; 2276 2277 cbp->stripping = !prm; /* truncate rx packet to byte count */ 2278 cbp->padding = 1; /* (do) pad short tx packets */ 2279 cbp->rcv_crc_xfer = 0; /* (don't) xfer CRC to host */ 2280 cbp->long_rx_en = sc->flags & FXP_FLAG_LONG_PKT_EN ? 1 : 0; 2281 cbp->ia_wake_en = 0; /* (don't) wake up on address match */ 2282 cbp->magic_pkt_dis = sc->flags & FXP_FLAG_WOL ? 0 : 1; 2283 cbp->force_fdx = 0; /* (don't) force full duplex */ 2284 cbp->fdx_pin_en = 1; /* (enable) FDX# pin */ 2285 cbp->multi_ia = 0; /* (don't) accept multiple IAs */ 2286 cbp->mc_all = sc->flags & FXP_FLAG_ALL_MCAST ? 1 : 0; 2287 cbp->gamla_rx = sc->flags & FXP_FLAG_EXT_RFA ? 1 : 0; 2288 2289 if (sc->tunable_noflow || sc->revision == FXP_REV_82557) { 2290 /* 2291 * The 82557 has no hardware flow control, the values 2292 * below are the defaults for the chip. 2293 */ 2294 cbp->fc_delay_lsb = 0; 2295 cbp->fc_delay_msb = 0x40; 2296 cbp->pri_fc_thresh = 3; 2297 cbp->tx_fc_dis = 0; 2298 cbp->rx_fc_restop = 0; 2299 cbp->rx_fc_restart = 0; 2300 cbp->fc_filter = 0; 2301 cbp->pri_fc_loc = 1; 2302 } else { 2303 cbp->fc_delay_lsb = 0x1f; 2304 cbp->fc_delay_msb = 0x01; 2305 cbp->pri_fc_thresh = 3; 2306 cbp->tx_fc_dis = 0; /* enable transmit FC */ 2307 cbp->rx_fc_restop = 1; /* enable FC restop frames */ 2308 cbp->rx_fc_restart = 1; /* enable FC restart frames */ 2309 cbp->fc_filter = !prm; /* drop FC frames to host */ 2310 cbp->pri_fc_loc = 1; /* FC pri location (byte31) */ 2311 } 2312 2313 /* 2314 * Start the config command/DMA. 2315 */ 2316 fxp_scb_wait(sc); 2317 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE); 2318 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->fxp_desc.cbl_addr); 2319 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2320 /* ...and wait for it to complete. */ 2321 fxp_dma_wait(sc, &cbp->cb_status, sc->cbl_tag, sc->cbl_map); 2322 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_POSTWRITE); 2323 2324 /* 2325 * Now initialize the station address. Temporarily use the TxCB 2326 * memory area like we did above for the config CB. 2327 */ 2328 cb_ias = (struct fxp_cb_ias *)sc->fxp_desc.cbl_list; 2329 cb_ias->cb_status = 0; 2330 cb_ias->cb_command = htole16(FXP_CB_COMMAND_IAS | FXP_CB_COMMAND_EL); 2331 cb_ias->link_addr = 0xffffffff; 2332 bcopy(IF_LLADDR(sc->ifp), cb_ias->macaddr, ETHER_ADDR_LEN); 2333 2334 /* 2335 * Start the IAS (Individual Address Setup) command/DMA. 2336 */ 2337 fxp_scb_wait(sc); 2338 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE); 2339 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2340 /* ...and wait for it to complete. */ 2341 fxp_dma_wait(sc, &cb_ias->cb_status, sc->cbl_tag, sc->cbl_map); 2342 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_POSTWRITE); 2343 2344 /* 2345 * Initialize transmit control block (TxCB) list. 2346 */ 2347 txp = sc->fxp_desc.tx_list; 2348 tcbp = sc->fxp_desc.cbl_list; 2349 bzero(tcbp, FXP_TXCB_SZ); 2350 for (i = 0; i < FXP_NTXCB; i++) { 2351 txp[i].tx_mbuf = NULL; 2352 tcbp[i].cb_status = htole16(FXP_CB_STATUS_C | FXP_CB_STATUS_OK); 2353 tcbp[i].cb_command = htole16(FXP_CB_COMMAND_NOP); 2354 tcbp[i].link_addr = htole32(sc->fxp_desc.cbl_addr + 2355 (((i + 1) & FXP_TXCB_MASK) * sizeof(struct fxp_cb_tx))); 2356 if (sc->flags & FXP_FLAG_EXT_TXCB) 2357 tcbp[i].tbd_array_addr = 2358 htole32(FXP_TXCB_DMA_ADDR(sc, &tcbp[i].tbd[2])); 2359 else 2360 tcbp[i].tbd_array_addr = 2361 htole32(FXP_TXCB_DMA_ADDR(sc, &tcbp[i].tbd[0])); 2362 txp[i].tx_next = &txp[(i + 1) & FXP_TXCB_MASK]; 2363 } 2364 /* 2365 * Set the suspend flag on the first TxCB and start the control 2366 * unit. It will execute the NOP and then suspend. 2367 */ 2368 tcbp->cb_command = htole16(FXP_CB_COMMAND_NOP | FXP_CB_COMMAND_S); 2369 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE); 2370 sc->fxp_desc.tx_first = sc->fxp_desc.tx_last = txp; 2371 sc->tx_queued = 1; 2372 2373 fxp_scb_wait(sc); 2374 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2375 2376 /* 2377 * Initialize receiver buffer area - RFA. 2378 */ 2379 fxp_scb_wait(sc); 2380 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->fxp_desc.rx_head->rx_addr); 2381 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_START); 2382 2383 /* 2384 * Set current media. 2385 */ 2386 if (sc->miibus != NULL) 2387 mii_mediachg(device_get_softc(sc->miibus)); 2388 2389 ifp->if_drv_flags |= IFF_DRV_RUNNING; 2390 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 2391 2392 /* 2393 * Enable interrupts. 2394 */ 2395 #ifdef DEVICE_POLLING 2396 /* 2397 * ... but only do that if we are not polling. And because (presumably) 2398 * the default is interrupts on, we need to disable them explicitly! 2399 */ 2400 if (ifp->if_capenable & IFCAP_POLLING ) 2401 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE); 2402 else 2403 #endif /* DEVICE_POLLING */ 2404 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, 0); 2405 2406 /* 2407 * Start stats updater. 2408 */ 2409 callout_reset(&sc->stat_ch, hz, fxp_tick, sc); 2410 } 2411 2412 static int 2413 fxp_serial_ifmedia_upd(struct ifnet *ifp) 2414 { 2415 2416 return (0); 2417 } 2418 2419 static void 2420 fxp_serial_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 2421 { 2422 2423 ifmr->ifm_active = IFM_ETHER|IFM_MANUAL; 2424 } 2425 2426 /* 2427 * Change media according to request. 2428 */ 2429 static int 2430 fxp_ifmedia_upd(struct ifnet *ifp) 2431 { 2432 struct fxp_softc *sc = ifp->if_softc; 2433 struct mii_data *mii; 2434 2435 mii = device_get_softc(sc->miibus); 2436 FXP_LOCK(sc); 2437 if (mii->mii_instance) { 2438 struct mii_softc *miisc; 2439 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 2440 mii_phy_reset(miisc); 2441 } 2442 mii_mediachg(mii); 2443 FXP_UNLOCK(sc); 2444 return (0); 2445 } 2446 2447 /* 2448 * Notify the world which media we're using. 2449 */ 2450 static void 2451 fxp_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 2452 { 2453 struct fxp_softc *sc = ifp->if_softc; 2454 struct mii_data *mii; 2455 2456 mii = device_get_softc(sc->miibus); 2457 FXP_LOCK(sc); 2458 mii_pollstat(mii); 2459 ifmr->ifm_active = mii->mii_media_active; 2460 ifmr->ifm_status = mii->mii_media_status; 2461 2462 if (IFM_SUBTYPE(ifmr->ifm_active) == IFM_10_T && 2463 sc->flags & FXP_FLAG_CU_RESUME_BUG) 2464 sc->cu_resume_bug = 1; 2465 else 2466 sc->cu_resume_bug = 0; 2467 FXP_UNLOCK(sc); 2468 } 2469 2470 /* 2471 * Add a buffer to the end of the RFA buffer list. 2472 * Return 0 if successful, 1 for failure. A failure results in 2473 * reusing the RFA buffer. 2474 * The RFA struct is stuck at the beginning of mbuf cluster and the 2475 * data pointer is fixed up to point just past it. 2476 */ 2477 static int 2478 fxp_new_rfabuf(struct fxp_softc *sc, struct fxp_rx *rxp) 2479 { 2480 struct mbuf *m; 2481 struct fxp_rfa *rfa; 2482 bus_dmamap_t tmp_map; 2483 int error; 2484 2485 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 2486 if (m == NULL) 2487 return (ENOBUFS); 2488 2489 /* 2490 * Move the data pointer up so that the incoming data packet 2491 * will be 32-bit aligned. 2492 */ 2493 m->m_data += RFA_ALIGNMENT_FUDGE; 2494 2495 /* 2496 * Get a pointer to the base of the mbuf cluster and move 2497 * data start past it. 2498 */ 2499 rfa = mtod(m, struct fxp_rfa *); 2500 m->m_data += sc->rfa_size; 2501 rfa->size = htole16(MCLBYTES - sc->rfa_size - RFA_ALIGNMENT_FUDGE); 2502 2503 rfa->rfa_status = 0; 2504 rfa->rfa_control = htole16(FXP_RFA_CONTROL_EL); 2505 rfa->actual_size = 0; 2506 m->m_len = m->m_pkthdr.len = MCLBYTES - RFA_ALIGNMENT_FUDGE - 2507 sc->rfa_size; 2508 2509 /* 2510 * Initialize the rest of the RFA. Note that since the RFA 2511 * is misaligned, we cannot store values directly. We're thus 2512 * using the le32enc() function which handles endianness and 2513 * is also alignment-safe. 2514 */ 2515 le32enc(&rfa->link_addr, 0xffffffff); 2516 le32enc(&rfa->rbd_addr, 0xffffffff); 2517 2518 /* Map the RFA into DMA memory. */ 2519 error = bus_dmamap_load(sc->fxp_mtag, sc->spare_map, rfa, 2520 MCLBYTES - RFA_ALIGNMENT_FUDGE, fxp_dma_map_addr, 2521 &rxp->rx_addr, 0); 2522 if (error) { 2523 m_freem(m); 2524 return (error); 2525 } 2526 2527 bus_dmamap_unload(sc->fxp_mtag, rxp->rx_map); 2528 tmp_map = sc->spare_map; 2529 sc->spare_map = rxp->rx_map; 2530 rxp->rx_map = tmp_map; 2531 rxp->rx_mbuf = m; 2532 2533 bus_dmamap_sync(sc->fxp_mtag, rxp->rx_map, 2534 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2535 return (0); 2536 } 2537 2538 static void 2539 fxp_add_rfabuf(struct fxp_softc *sc, struct fxp_rx *rxp) 2540 { 2541 struct fxp_rfa *p_rfa; 2542 struct fxp_rx *p_rx; 2543 2544 /* 2545 * If there are other buffers already on the list, attach this 2546 * one to the end by fixing up the tail to point to this one. 2547 */ 2548 if (sc->fxp_desc.rx_head != NULL) { 2549 p_rx = sc->fxp_desc.rx_tail; 2550 p_rfa = (struct fxp_rfa *) 2551 (p_rx->rx_mbuf->m_ext.ext_buf + RFA_ALIGNMENT_FUDGE); 2552 p_rx->rx_next = rxp; 2553 le32enc(&p_rfa->link_addr, rxp->rx_addr); 2554 p_rfa->rfa_control = 0; 2555 bus_dmamap_sync(sc->fxp_mtag, p_rx->rx_map, 2556 BUS_DMASYNC_PREWRITE); 2557 } else { 2558 rxp->rx_next = NULL; 2559 sc->fxp_desc.rx_head = rxp; 2560 } 2561 sc->fxp_desc.rx_tail = rxp; 2562 } 2563 2564 static void 2565 fxp_discard_rfabuf(struct fxp_softc *sc, struct fxp_rx *rxp) 2566 { 2567 struct mbuf *m; 2568 struct fxp_rfa *rfa; 2569 2570 m = rxp->rx_mbuf; 2571 m->m_data = m->m_ext.ext_buf; 2572 /* 2573 * Move the data pointer up so that the incoming data packet 2574 * will be 32-bit aligned. 2575 */ 2576 m->m_data += RFA_ALIGNMENT_FUDGE; 2577 2578 /* 2579 * Get a pointer to the base of the mbuf cluster and move 2580 * data start past it. 2581 */ 2582 rfa = mtod(m, struct fxp_rfa *); 2583 m->m_data += sc->rfa_size; 2584 rfa->size = htole16(MCLBYTES - sc->rfa_size - RFA_ALIGNMENT_FUDGE); 2585 2586 rfa->rfa_status = 0; 2587 rfa->rfa_control = htole16(FXP_RFA_CONTROL_EL); 2588 rfa->actual_size = 0; 2589 2590 /* 2591 * Initialize the rest of the RFA. Note that since the RFA 2592 * is misaligned, we cannot store values directly. We're thus 2593 * using the le32enc() function which handles endianness and 2594 * is also alignment-safe. 2595 */ 2596 le32enc(&rfa->link_addr, 0xffffffff); 2597 le32enc(&rfa->rbd_addr, 0xffffffff); 2598 2599 bus_dmamap_sync(sc->fxp_mtag, rxp->rx_map, 2600 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2601 } 2602 2603 static int 2604 fxp_miibus_readreg(device_t dev, int phy, int reg) 2605 { 2606 struct fxp_softc *sc = device_get_softc(dev); 2607 int count = 10000; 2608 int value; 2609 2610 CSR_WRITE_4(sc, FXP_CSR_MDICONTROL, 2611 (FXP_MDI_READ << 26) | (reg << 16) | (phy << 21)); 2612 2613 while (((value = CSR_READ_4(sc, FXP_CSR_MDICONTROL)) & 0x10000000) == 0 2614 && count--) 2615 DELAY(10); 2616 2617 if (count <= 0) 2618 device_printf(dev, "fxp_miibus_readreg: timed out\n"); 2619 2620 return (value & 0xffff); 2621 } 2622 2623 static void 2624 fxp_miibus_writereg(device_t dev, int phy, int reg, int value) 2625 { 2626 struct fxp_softc *sc = device_get_softc(dev); 2627 int count = 10000; 2628 2629 CSR_WRITE_4(sc, FXP_CSR_MDICONTROL, 2630 (FXP_MDI_WRITE << 26) | (reg << 16) | (phy << 21) | 2631 (value & 0xffff)); 2632 2633 while ((CSR_READ_4(sc, FXP_CSR_MDICONTROL) & 0x10000000) == 0 && 2634 count--) 2635 DELAY(10); 2636 2637 if (count <= 0) 2638 device_printf(dev, "fxp_miibus_writereg: timed out\n"); 2639 } 2640 2641 static int 2642 fxp_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 2643 { 2644 struct fxp_softc *sc = ifp->if_softc; 2645 struct ifreq *ifr = (struct ifreq *)data; 2646 struct mii_data *mii; 2647 int flag, mask, error = 0, reinit; 2648 2649 switch (command) { 2650 case SIOCSIFFLAGS: 2651 FXP_LOCK(sc); 2652 if (ifp->if_flags & IFF_ALLMULTI) 2653 sc->flags |= FXP_FLAG_ALL_MCAST; 2654 else 2655 sc->flags &= ~FXP_FLAG_ALL_MCAST; 2656 2657 /* 2658 * If interface is marked up and not running, then start it. 2659 * If it is marked down and running, stop it. 2660 * XXX If it's up then re-initialize it. This is so flags 2661 * such as IFF_PROMISC are handled. 2662 */ 2663 if (ifp->if_flags & IFF_UP) { 2664 fxp_init_body(sc); 2665 } else { 2666 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 2667 fxp_stop(sc); 2668 } 2669 FXP_UNLOCK(sc); 2670 break; 2671 2672 case SIOCADDMULTI: 2673 case SIOCDELMULTI: 2674 FXP_LOCK(sc); 2675 if (ifp->if_flags & IFF_ALLMULTI) 2676 sc->flags |= FXP_FLAG_ALL_MCAST; 2677 else 2678 sc->flags &= ~FXP_FLAG_ALL_MCAST; 2679 /* 2680 * Multicast list has changed; set the hardware filter 2681 * accordingly. 2682 */ 2683 if ((sc->flags & FXP_FLAG_ALL_MCAST) == 0) 2684 fxp_mc_setup(sc); 2685 /* 2686 * fxp_mc_setup() can set FXP_FLAG_ALL_MCAST, so check it 2687 * again rather than else {}. 2688 */ 2689 if (sc->flags & FXP_FLAG_ALL_MCAST) 2690 fxp_init_body(sc); 2691 FXP_UNLOCK(sc); 2692 error = 0; 2693 break; 2694 2695 case SIOCSIFMEDIA: 2696 case SIOCGIFMEDIA: 2697 if (sc->miibus != NULL) { 2698 mii = device_get_softc(sc->miibus); 2699 error = ifmedia_ioctl(ifp, ifr, 2700 &mii->mii_media, command); 2701 } else { 2702 error = ifmedia_ioctl(ifp, ifr, &sc->sc_media, command); 2703 } 2704 break; 2705 2706 case SIOCSIFCAP: 2707 reinit = 0; 2708 mask = ifp->if_capenable ^ ifr->ifr_reqcap; 2709 #ifdef DEVICE_POLLING 2710 if (mask & IFCAP_POLLING) { 2711 if (ifr->ifr_reqcap & IFCAP_POLLING) { 2712 error = ether_poll_register(fxp_poll, ifp); 2713 if (error) 2714 return(error); 2715 FXP_LOCK(sc); 2716 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, 2717 FXP_SCB_INTR_DISABLE); 2718 ifp->if_capenable |= IFCAP_POLLING; 2719 FXP_UNLOCK(sc); 2720 } else { 2721 error = ether_poll_deregister(ifp); 2722 /* Enable interrupts in any case */ 2723 FXP_LOCK(sc); 2724 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, 0); 2725 ifp->if_capenable &= ~IFCAP_POLLING; 2726 FXP_UNLOCK(sc); 2727 } 2728 } 2729 #endif 2730 FXP_LOCK(sc); 2731 if ((mask & IFCAP_TXCSUM) != 0 && 2732 (ifp->if_capabilities & IFCAP_TXCSUM) != 0) { 2733 ifp->if_capenable ^= IFCAP_TXCSUM; 2734 if ((ifp->if_capenable & IFCAP_TXCSUM) != 0) 2735 ifp->if_hwassist |= FXP_CSUM_FEATURES; 2736 else 2737 ifp->if_hwassist &= ~FXP_CSUM_FEATURES; 2738 } 2739 if ((mask & IFCAP_RXCSUM) != 0 && 2740 (ifp->if_capabilities & IFCAP_RXCSUM) != 0) { 2741 ifp->if_capenable ^= IFCAP_RXCSUM; 2742 if ((sc->flags & FXP_FLAG_82559_RXCSUM) != 0) 2743 reinit++; 2744 } 2745 if ((mask & IFCAP_TSO4) != 0 && 2746 (ifp->if_capabilities & IFCAP_TSO4) != 0) { 2747 ifp->if_capenable ^= IFCAP_TSO4; 2748 if ((ifp->if_capenable & IFCAP_TSO4) != 0) 2749 ifp->if_hwassist |= CSUM_TSO; 2750 else 2751 ifp->if_hwassist &= ~CSUM_TSO; 2752 } 2753 if ((mask & IFCAP_WOL_MAGIC) != 0 && 2754 (ifp->if_capabilities & IFCAP_WOL_MAGIC) != 0) 2755 ifp->if_capenable ^= IFCAP_WOL_MAGIC; 2756 if ((mask & IFCAP_VLAN_MTU) != 0 && 2757 (ifp->if_capabilities & IFCAP_VLAN_MTU) != 0) { 2758 ifp->if_capenable ^= IFCAP_VLAN_MTU; 2759 if (sc->revision != FXP_REV_82557) 2760 flag = FXP_FLAG_LONG_PKT_EN; 2761 else /* a hack to get long frames on the old chip */ 2762 flag = FXP_FLAG_SAVE_BAD; 2763 sc->flags ^= flag; 2764 if (ifp->if_flags & IFF_UP) 2765 reinit++; 2766 } 2767 if (reinit > 0) 2768 fxp_init_body(sc); 2769 FXP_UNLOCK(sc); 2770 break; 2771 2772 default: 2773 error = ether_ioctl(ifp, command, data); 2774 } 2775 return (error); 2776 } 2777 2778 /* 2779 * Fill in the multicast address list and return number of entries. 2780 */ 2781 static int 2782 fxp_mc_addrs(struct fxp_softc *sc) 2783 { 2784 struct fxp_cb_mcs *mcsp = sc->mcsp; 2785 struct ifnet *ifp = sc->ifp; 2786 struct ifmultiaddr *ifma; 2787 int nmcasts; 2788 2789 nmcasts = 0; 2790 if ((sc->flags & FXP_FLAG_ALL_MCAST) == 0) { 2791 IF_ADDR_LOCK(ifp); 2792 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 2793 if (ifma->ifma_addr->sa_family != AF_LINK) 2794 continue; 2795 if (nmcasts >= MAXMCADDR) { 2796 sc->flags |= FXP_FLAG_ALL_MCAST; 2797 nmcasts = 0; 2798 break; 2799 } 2800 bcopy(LLADDR((struct sockaddr_dl *)ifma->ifma_addr), 2801 &sc->mcsp->mc_addr[nmcasts][0], ETHER_ADDR_LEN); 2802 nmcasts++; 2803 } 2804 IF_ADDR_UNLOCK(ifp); 2805 } 2806 mcsp->mc_cnt = htole16(nmcasts * ETHER_ADDR_LEN); 2807 return (nmcasts); 2808 } 2809 2810 /* 2811 * Program the multicast filter. 2812 * 2813 * We have an artificial restriction that the multicast setup command 2814 * must be the first command in the chain, so we take steps to ensure 2815 * this. By requiring this, it allows us to keep up the performance of 2816 * the pre-initialized command ring (esp. link pointers) by not actually 2817 * inserting the mcsetup command in the ring - i.e. its link pointer 2818 * points to the TxCB ring, but the mcsetup descriptor itself is not part 2819 * of it. We then can do 'CU_START' on the mcsetup descriptor and have it 2820 * lead into the regular TxCB ring when it completes. 2821 * 2822 * This function must be called at splimp. 2823 */ 2824 static void 2825 fxp_mc_setup(struct fxp_softc *sc) 2826 { 2827 struct fxp_cb_mcs *mcsp = sc->mcsp; 2828 struct fxp_tx *txp; 2829 int count; 2830 2831 FXP_LOCK_ASSERT(sc, MA_OWNED); 2832 /* 2833 * If there are queued commands, we must wait until they are all 2834 * completed. If we are already waiting, then add a NOP command 2835 * with interrupt option so that we're notified when all commands 2836 * have been completed - fxp_start() ensures that no additional 2837 * TX commands will be added when need_mcsetup is true. 2838 */ 2839 if (sc->tx_queued) { 2840 /* 2841 * need_mcsetup will be true if we are already waiting for the 2842 * NOP command to be completed (see below). In this case, bail. 2843 */ 2844 if (sc->need_mcsetup) 2845 return; 2846 sc->need_mcsetup = 1; 2847 2848 /* 2849 * Add a NOP command with interrupt so that we are notified 2850 * when all TX commands have been processed. 2851 */ 2852 txp = sc->fxp_desc.tx_last->tx_next; 2853 txp->tx_mbuf = NULL; 2854 txp->tx_cb->cb_status = 0; 2855 txp->tx_cb->cb_command = htole16(FXP_CB_COMMAND_NOP | 2856 FXP_CB_COMMAND_S | FXP_CB_COMMAND_I); 2857 /* 2858 * Advance the end of list forward. 2859 */ 2860 sc->fxp_desc.tx_last->tx_cb->cb_command &= 2861 htole16(~FXP_CB_COMMAND_S); 2862 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE); 2863 sc->fxp_desc.tx_last = txp; 2864 sc->tx_queued++; 2865 /* 2866 * Issue a resume in case the CU has just suspended. 2867 */ 2868 fxp_scb_wait(sc); 2869 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_RESUME); 2870 /* 2871 * Set a 5 second timer just in case we don't hear from the 2872 * card again. 2873 */ 2874 sc->watchdog_timer = 5; 2875 2876 return; 2877 } 2878 sc->need_mcsetup = 0; 2879 2880 /* 2881 * Initialize multicast setup descriptor. 2882 */ 2883 mcsp->cb_status = 0; 2884 mcsp->cb_command = htole16(FXP_CB_COMMAND_MCAS | 2885 FXP_CB_COMMAND_S | FXP_CB_COMMAND_I); 2886 mcsp->link_addr = htole32(sc->fxp_desc.cbl_addr); 2887 txp = &sc->fxp_desc.mcs_tx; 2888 txp->tx_mbuf = NULL; 2889 txp->tx_cb = (struct fxp_cb_tx *)sc->mcsp; 2890 txp->tx_next = sc->fxp_desc.tx_list; 2891 (void) fxp_mc_addrs(sc); 2892 sc->fxp_desc.tx_first = sc->fxp_desc.tx_last = txp; 2893 sc->tx_queued = 1; 2894 2895 /* 2896 * Wait until command unit is not active. This should never 2897 * be the case when nothing is queued, but make sure anyway. 2898 */ 2899 count = 100; 2900 while ((CSR_READ_1(sc, FXP_CSR_SCB_RUSCUS) >> 6) == 2901 FXP_SCB_CUS_ACTIVE && --count) 2902 DELAY(10); 2903 if (count == 0) { 2904 device_printf(sc->dev, "command queue timeout\n"); 2905 return; 2906 } 2907 2908 /* 2909 * Start the multicast setup command. 2910 */ 2911 fxp_scb_wait(sc); 2912 bus_dmamap_sync(sc->mcs_tag, sc->mcs_map, BUS_DMASYNC_PREWRITE); 2913 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->mcs_addr); 2914 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2915 2916 sc->watchdog_timer = 2; 2917 return; 2918 } 2919 2920 static uint32_t fxp_ucode_d101a[] = D101_A_RCVBUNDLE_UCODE; 2921 static uint32_t fxp_ucode_d101b0[] = D101_B0_RCVBUNDLE_UCODE; 2922 static uint32_t fxp_ucode_d101ma[] = D101M_B_RCVBUNDLE_UCODE; 2923 static uint32_t fxp_ucode_d101s[] = D101S_RCVBUNDLE_UCODE; 2924 static uint32_t fxp_ucode_d102[] = D102_B_RCVBUNDLE_UCODE; 2925 static uint32_t fxp_ucode_d102c[] = D102_C_RCVBUNDLE_UCODE; 2926 static uint32_t fxp_ucode_d102e[] = D102_E_RCVBUNDLE_UCODE; 2927 2928 #define UCODE(x) x, sizeof(x)/sizeof(uint32_t) 2929 2930 struct ucode { 2931 uint32_t revision; 2932 uint32_t *ucode; 2933 int length; 2934 u_short int_delay_offset; 2935 u_short bundle_max_offset; 2936 } ucode_table[] = { 2937 { FXP_REV_82558_A4, UCODE(fxp_ucode_d101a), D101_CPUSAVER_DWORD, 0 }, 2938 { FXP_REV_82558_B0, UCODE(fxp_ucode_d101b0), D101_CPUSAVER_DWORD, 0 }, 2939 { FXP_REV_82559_A0, UCODE(fxp_ucode_d101ma), 2940 D101M_CPUSAVER_DWORD, D101M_CPUSAVER_BUNDLE_MAX_DWORD }, 2941 { FXP_REV_82559S_A, UCODE(fxp_ucode_d101s), 2942 D101S_CPUSAVER_DWORD, D101S_CPUSAVER_BUNDLE_MAX_DWORD }, 2943 { FXP_REV_82550, UCODE(fxp_ucode_d102), 2944 D102_B_CPUSAVER_DWORD, D102_B_CPUSAVER_BUNDLE_MAX_DWORD }, 2945 { FXP_REV_82550_C, UCODE(fxp_ucode_d102c), 2946 D102_C_CPUSAVER_DWORD, D102_C_CPUSAVER_BUNDLE_MAX_DWORD }, 2947 { FXP_REV_82551_F, UCODE(fxp_ucode_d102e), 2948 D102_E_CPUSAVER_DWORD, D102_E_CPUSAVER_BUNDLE_MAX_DWORD }, 2949 { 0, NULL, 0, 0, 0 } 2950 }; 2951 2952 static void 2953 fxp_load_ucode(struct fxp_softc *sc) 2954 { 2955 struct ucode *uc; 2956 struct fxp_cb_ucode *cbp; 2957 int i; 2958 2959 for (uc = ucode_table; uc->ucode != NULL; uc++) 2960 if (sc->revision == uc->revision) 2961 break; 2962 if (uc->ucode == NULL) 2963 return; 2964 cbp = (struct fxp_cb_ucode *)sc->fxp_desc.cbl_list; 2965 cbp->cb_status = 0; 2966 cbp->cb_command = htole16(FXP_CB_COMMAND_UCODE | FXP_CB_COMMAND_EL); 2967 cbp->link_addr = 0xffffffff; /* (no) next command */ 2968 for (i = 0; i < uc->length; i++) 2969 cbp->ucode[i] = htole32(uc->ucode[i]); 2970 if (uc->int_delay_offset) 2971 *(uint16_t *)&cbp->ucode[uc->int_delay_offset] = 2972 htole16(sc->tunable_int_delay + sc->tunable_int_delay / 2); 2973 if (uc->bundle_max_offset) 2974 *(uint16_t *)&cbp->ucode[uc->bundle_max_offset] = 2975 htole16(sc->tunable_bundle_max); 2976 /* 2977 * Download the ucode to the chip. 2978 */ 2979 fxp_scb_wait(sc); 2980 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE); 2981 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->fxp_desc.cbl_addr); 2982 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2983 /* ...and wait for it to complete. */ 2984 fxp_dma_wait(sc, &cbp->cb_status, sc->cbl_tag, sc->cbl_map); 2985 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_POSTWRITE); 2986 device_printf(sc->dev, 2987 "Microcode loaded, int_delay: %d usec bundle_max: %d\n", 2988 sc->tunable_int_delay, 2989 uc->bundle_max_offset == 0 ? 0 : sc->tunable_bundle_max); 2990 sc->flags |= FXP_FLAG_UCODE; 2991 } 2992 2993 static int 2994 sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high) 2995 { 2996 int error, value; 2997 2998 value = *(int *)arg1; 2999 error = sysctl_handle_int(oidp, &value, 0, req); 3000 if (error || !req->newptr) 3001 return (error); 3002 if (value < low || value > high) 3003 return (EINVAL); 3004 *(int *)arg1 = value; 3005 return (0); 3006 } 3007 3008 /* 3009 * Interrupt delay is expressed in microseconds, a multiplier is used 3010 * to convert this to the appropriate clock ticks before using. 3011 */ 3012 static int 3013 sysctl_hw_fxp_int_delay(SYSCTL_HANDLER_ARGS) 3014 { 3015 return (sysctl_int_range(oidp, arg1, arg2, req, 300, 3000)); 3016 } 3017 3018 static int 3019 sysctl_hw_fxp_bundle_max(SYSCTL_HANDLER_ARGS) 3020 { 3021 return (sysctl_int_range(oidp, arg1, arg2, req, 1, 0xffff)); 3022 } 3023