1 /*- 2 * Copyright (c) 1995, David Greenman 3 * Copyright (c) 2001 Jonathan Lemon <jlemon@freebsd.org> 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice unmodified, this list of conditions, and the following 11 * disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 * 28 * $FreeBSD$ 29 */ 30 31 /* 32 * Intel EtherExpress Pro/100B PCI Fast Ethernet driver 33 */ 34 35 #include <sys/param.h> 36 #include <sys/systm.h> 37 #include <sys/mbuf.h> 38 #include <sys/malloc.h> 39 /* #include <sys/mutex.h> */ 40 #include <sys/kernel.h> 41 #include <sys/socket.h> 42 #include <sys/sysctl.h> 43 44 #include <net/if.h> 45 #include <net/if_dl.h> 46 #include <net/if_media.h> 47 48 #ifdef NS 49 #include <netns/ns.h> 50 #include <netns/ns_if.h> 51 #endif 52 53 #include <net/bpf.h> 54 #include <sys/sockio.h> 55 #include <sys/bus.h> 56 #include <machine/bus.h> 57 #include <sys/rman.h> 58 #include <machine/resource.h> 59 60 #include <net/ethernet.h> 61 #include <net/if_arp.h> 62 63 #include <vm/vm.h> /* for vtophys */ 64 #include <vm/pmap.h> /* for vtophys */ 65 #include <machine/clock.h> /* for DELAY */ 66 67 #include <net/if_types.h> 68 #include <net/if_vlan_var.h> 69 70 #include <pci/pcivar.h> 71 #include <pci/pcireg.h> /* for PCIM_CMD_xxx */ 72 73 #include <dev/mii/mii.h> 74 #include <dev/mii/miivar.h> 75 76 #include <dev/fxp/if_fxpreg.h> 77 #include <dev/fxp/if_fxpvar.h> 78 #include <dev/fxp/rcvbundl.h> 79 80 MODULE_DEPEND(fxp, miibus, 1, 1, 1); 81 #include "miibus_if.h" 82 83 /* 84 * NOTE! On the Alpha, we have an alignment constraint. The 85 * card DMAs the packet immediately following the RFA. However, 86 * the first thing in the packet is a 14-byte Ethernet header. 87 * This means that the packet is misaligned. To compensate, 88 * we actually offset the RFA 2 bytes into the cluster. This 89 * alignes the packet after the Ethernet header at a 32-bit 90 * boundary. HOWEVER! This means that the RFA is misaligned! 91 */ 92 #define RFA_ALIGNMENT_FUDGE 2 93 94 /* 95 * Set initial transmit threshold at 64 (512 bytes). This is 96 * increased by 64 (512 bytes) at a time, to maximum of 192 97 * (1536 bytes), if an underrun occurs. 98 */ 99 static int tx_threshold = 64; 100 101 /* 102 * The configuration byte map has several undefined fields which 103 * must be one or must be zero. Set up a template for these bits 104 * only, (assuming a 82557 chip) leaving the actual configuration 105 * to fxp_init. 106 * 107 * See struct fxp_cb_config for the bit definitions. 108 */ 109 static u_char fxp_cb_config_template[] = { 110 0x0, 0x0, /* cb_status */ 111 0x0, 0x0, /* cb_command */ 112 0x0, 0x0, 0x0, 0x0, /* link_addr */ 113 0x0, /* 0 */ 114 0x0, /* 1 */ 115 0x0, /* 2 */ 116 0x0, /* 3 */ 117 0x0, /* 4 */ 118 0x0, /* 5 */ 119 0x32, /* 6 */ 120 0x0, /* 7 */ 121 0x0, /* 8 */ 122 0x0, /* 9 */ 123 0x6, /* 10 */ 124 0x0, /* 11 */ 125 0x0, /* 12 */ 126 0x0, /* 13 */ 127 0xf2, /* 14 */ 128 0x48, /* 15 */ 129 0x0, /* 16 */ 130 0x40, /* 17 */ 131 0xf0, /* 18 */ 132 0x0, /* 19 */ 133 0x3f, /* 20 */ 134 0x5 /* 21 */ 135 }; 136 137 struct fxp_ident { 138 u_int16_t devid; 139 char *name; 140 }; 141 142 /* 143 * Claim various Intel PCI device identifiers for this driver. The 144 * sub-vendor and sub-device field are extensively used to identify 145 * particular variants, but we don't currently differentiate between 146 * them. 147 */ 148 static struct fxp_ident fxp_ident_table[] = { 149 { 0x1229, "Intel Pro 10/100B/100+ Ethernet" }, 150 { 0x2449, "Intel Pro/100 Ethernet" }, 151 { 0x1209, "Intel Embedded 10/100 Ethernet" }, 152 { 0x1029, "Intel Pro/100 Ethernet" }, 153 { 0x1030, "Intel Pro/100 Ethernet" }, 154 { 0x1031, "Intel Pro/100 Ethernet" }, 155 { 0x1032, "Intel Pro/100 Ethernet" }, 156 { 0x1033, "Intel Pro/100 Ethernet" }, 157 { 0x1034, "Intel Pro/100 Ethernet" }, 158 { 0x1035, "Intel Pro/100 Ethernet" }, 159 { 0x1036, "Intel Pro/100 Ethernet" }, 160 { 0x1037, "Intel Pro/100 Ethernet" }, 161 { 0x1038, "Intel Pro/100 Ethernet" }, 162 { 0, NULL }, 163 }; 164 165 static int fxp_probe(device_t dev); 166 static int fxp_attach(device_t dev); 167 static int fxp_detach(device_t dev); 168 static int fxp_shutdown(device_t dev); 169 static int fxp_suspend(device_t dev); 170 static int fxp_resume(device_t dev); 171 172 static void fxp_intr(void *xsc); 173 static void fxp_init(void *xsc); 174 static void fxp_tick(void *xsc); 175 static void fxp_powerstate_d0(device_t dev); 176 static void fxp_start(struct ifnet *ifp); 177 static void fxp_stop(struct fxp_softc *sc); 178 static void fxp_release(struct fxp_softc *sc); 179 static int fxp_ioctl(struct ifnet *ifp, u_long command, 180 caddr_t data); 181 static void fxp_watchdog(struct ifnet *ifp); 182 static int fxp_add_rfabuf(struct fxp_softc *sc, struct mbuf *oldm); 183 static int fxp_mc_addrs(struct fxp_softc *sc); 184 static void fxp_mc_setup(struct fxp_softc *sc); 185 static u_int16_t fxp_eeprom_getword(struct fxp_softc *sc, int offset, 186 int autosize); 187 static void fxp_eeprom_putword(struct fxp_softc *sc, int offset, 188 u_int16_t data); 189 static void fxp_autosize_eeprom(struct fxp_softc *sc); 190 static void fxp_read_eeprom(struct fxp_softc *sc, u_short *data, 191 int offset, int words); 192 static void fxp_write_eeprom(struct fxp_softc *sc, u_short *data, 193 int offset, int words); 194 static int fxp_ifmedia_upd(struct ifnet *ifp); 195 static void fxp_ifmedia_sts(struct ifnet *ifp, 196 struct ifmediareq *ifmr); 197 static int fxp_serial_ifmedia_upd(struct ifnet *ifp); 198 static void fxp_serial_ifmedia_sts(struct ifnet *ifp, 199 struct ifmediareq *ifmr); 200 static volatile int fxp_miibus_readreg(device_t dev, int phy, int reg); 201 static void fxp_miibus_writereg(device_t dev, int phy, int reg, 202 int value); 203 static void fxp_load_ucode(struct fxp_softc *sc); 204 static int sysctl_int_range(SYSCTL_HANDLER_ARGS, 205 int low, int high); 206 static int sysctl_hw_fxp_bundle_max(SYSCTL_HANDLER_ARGS); 207 static int sysctl_hw_fxp_int_delay(SYSCTL_HANDLER_ARGS); 208 static __inline void fxp_lwcopy(volatile u_int32_t *src, 209 volatile u_int32_t *dst); 210 static __inline void fxp_scb_wait(struct fxp_softc *sc); 211 static __inline void fxp_scb_cmd(struct fxp_softc *sc, int cmd); 212 static __inline void fxp_dma_wait(volatile u_int16_t *status, 213 struct fxp_softc *sc); 214 215 static device_method_t fxp_methods[] = { 216 /* Device interface */ 217 DEVMETHOD(device_probe, fxp_probe), 218 DEVMETHOD(device_attach, fxp_attach), 219 DEVMETHOD(device_detach, fxp_detach), 220 DEVMETHOD(device_shutdown, fxp_shutdown), 221 DEVMETHOD(device_suspend, fxp_suspend), 222 DEVMETHOD(device_resume, fxp_resume), 223 224 /* MII interface */ 225 DEVMETHOD(miibus_readreg, fxp_miibus_readreg), 226 DEVMETHOD(miibus_writereg, fxp_miibus_writereg), 227 228 { 0, 0 } 229 }; 230 231 static driver_t fxp_driver = { 232 "fxp", 233 fxp_methods, 234 sizeof(struct fxp_softc), 235 }; 236 237 static devclass_t fxp_devclass; 238 239 DRIVER_MODULE(if_fxp, pci, fxp_driver, fxp_devclass, 0, 0); 240 DRIVER_MODULE(if_fxp, cardbus, fxp_driver, fxp_devclass, 0, 0); 241 DRIVER_MODULE(miibus, fxp, miibus_driver, miibus_devclass, 0, 0); 242 243 /* 244 * Inline function to copy a 16-bit aligned 32-bit quantity. 245 */ 246 static __inline void 247 fxp_lwcopy(volatile u_int32_t *src, volatile u_int32_t *dst) 248 { 249 #ifdef __i386__ 250 *dst = *src; 251 #else 252 volatile u_int16_t *a = (volatile u_int16_t *)src; 253 volatile u_int16_t *b = (volatile u_int16_t *)dst; 254 255 b[0] = a[0]; 256 b[1] = a[1]; 257 #endif 258 } 259 260 /* 261 * Wait for the previous command to be accepted (but not necessarily 262 * completed). 263 */ 264 static __inline void 265 fxp_scb_wait(struct fxp_softc *sc) 266 { 267 int i = 10000; 268 269 while (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) && --i) 270 DELAY(2); 271 if (i == 0) 272 device_printf(sc->dev, "SCB timeout: 0x%x 0x%x 0x%x 0x%x\n", 273 CSR_READ_1(sc, FXP_CSR_SCB_COMMAND), 274 CSR_READ_1(sc, FXP_CSR_SCB_STATACK), 275 CSR_READ_1(sc, FXP_CSR_SCB_RUSCUS), 276 CSR_READ_2(sc, FXP_CSR_FLOWCONTROL)); 277 } 278 279 static __inline void 280 fxp_scb_cmd(struct fxp_softc *sc, int cmd) 281 { 282 283 if (cmd == FXP_SCB_COMMAND_CU_RESUME && sc->cu_resume_bug) { 284 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_CB_COMMAND_NOP); 285 fxp_scb_wait(sc); 286 } 287 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, cmd); 288 } 289 290 static __inline void 291 fxp_dma_wait(volatile u_int16_t *status, struct fxp_softc *sc) 292 { 293 int i = 10000; 294 295 while (!(*status & FXP_CB_STATUS_C) && --i) 296 DELAY(2); 297 if (i == 0) 298 device_printf(sc->dev, "DMA timeout\n"); 299 } 300 301 /* 302 * Return identification string if this is device is ours. 303 */ 304 static int 305 fxp_probe(device_t dev) 306 { 307 u_int16_t devid; 308 struct fxp_ident *ident; 309 310 if (pci_get_vendor(dev) == FXP_VENDORID_INTEL) { 311 devid = pci_get_device(dev); 312 for (ident = fxp_ident_table; ident->name != NULL; ident++) { 313 if (ident->devid == devid) { 314 device_set_desc(dev, ident->name); 315 return (0); 316 } 317 } 318 } 319 return (ENXIO); 320 } 321 322 static void 323 fxp_powerstate_d0(device_t dev) 324 { 325 #if __FreeBSD_version >= 430002 326 u_int32_t iobase, membase, irq; 327 328 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 329 /* Save important PCI config data. */ 330 iobase = pci_read_config(dev, FXP_PCI_IOBA, 4); 331 membase = pci_read_config(dev, FXP_PCI_MMBA, 4); 332 irq = pci_read_config(dev, PCIR_INTLINE, 4); 333 334 /* Reset the power state. */ 335 device_printf(dev, "chip is in D%d power mode " 336 "-- setting to D0\n", pci_get_powerstate(dev)); 337 338 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 339 340 /* Restore PCI config data. */ 341 pci_write_config(dev, FXP_PCI_IOBA, iobase, 4); 342 pci_write_config(dev, FXP_PCI_MMBA, membase, 4); 343 pci_write_config(dev, PCIR_INTLINE, irq, 4); 344 } 345 #endif 346 } 347 348 static int 349 fxp_attach(device_t dev) 350 { 351 int error = 0; 352 struct fxp_softc *sc = device_get_softc(dev); 353 struct ifnet *ifp; 354 u_int32_t val; 355 u_int16_t data; 356 int i, rid, m1, m2, prefer_iomap; 357 int s; 358 359 bzero(sc, sizeof(*sc)); 360 sc->dev = dev; 361 callout_handle_init(&sc->stat_ch); 362 sysctl_ctx_init(&sc->sysctl_ctx); 363 mtx_init(&sc->sc_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 364 MTX_DEF | MTX_RECURSE); 365 366 s = splimp(); 367 368 /* 369 * Enable bus mastering. Enable memory space too, in case 370 * BIOS/Prom forgot about it. 371 */ 372 val = pci_read_config(dev, PCIR_COMMAND, 2); 373 val |= (PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN); 374 pci_write_config(dev, PCIR_COMMAND, val, 2); 375 val = pci_read_config(dev, PCIR_COMMAND, 2); 376 377 fxp_powerstate_d0(dev); 378 379 /* 380 * Figure out which we should try first - memory mapping or i/o mapping? 381 * We default to memory mapping. Then we accept an override from the 382 * command line. Then we check to see which one is enabled. 383 */ 384 m1 = PCIM_CMD_MEMEN; 385 m2 = PCIM_CMD_PORTEN; 386 prefer_iomap = 0; 387 if (resource_int_value(device_get_name(dev), device_get_unit(dev), 388 "prefer_iomap", &prefer_iomap) == 0 && prefer_iomap != 0) { 389 m1 = PCIM_CMD_PORTEN; 390 m2 = PCIM_CMD_MEMEN; 391 } 392 393 if (val & m1) { 394 sc->rtp = 395 (m1 == PCIM_CMD_MEMEN)? SYS_RES_MEMORY : SYS_RES_IOPORT; 396 sc->rgd = (m1 == PCIM_CMD_MEMEN)? FXP_PCI_MMBA : FXP_PCI_IOBA; 397 sc->mem = bus_alloc_resource(dev, sc->rtp, &sc->rgd, 398 0, ~0, 1, RF_ACTIVE); 399 } 400 if (sc->mem == NULL && (val & m2)) { 401 sc->rtp = 402 (m2 == PCIM_CMD_MEMEN)? SYS_RES_MEMORY : SYS_RES_IOPORT; 403 sc->rgd = (m2 == PCIM_CMD_MEMEN)? FXP_PCI_MMBA : FXP_PCI_IOBA; 404 sc->mem = bus_alloc_resource(dev, sc->rtp, &sc->rgd, 405 0, ~0, 1, RF_ACTIVE); 406 } 407 408 if (!sc->mem) { 409 device_printf(dev, "could not map device registers\n"); 410 error = ENXIO; 411 goto fail; 412 } 413 if (bootverbose) { 414 device_printf(dev, "using %s space register mapping\n", 415 sc->rtp == SYS_RES_MEMORY? "memory" : "I/O"); 416 } 417 418 sc->sc_st = rman_get_bustag(sc->mem); 419 sc->sc_sh = rman_get_bushandle(sc->mem); 420 421 /* 422 * Allocate our interrupt. 423 */ 424 rid = 0; 425 sc->irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 426 RF_SHAREABLE | RF_ACTIVE); 427 if (sc->irq == NULL) { 428 device_printf(dev, "could not map interrupt\n"); 429 error = ENXIO; 430 goto fail; 431 } 432 433 error = bus_setup_intr(dev, sc->irq, INTR_TYPE_NET, 434 fxp_intr, sc, &sc->ih); 435 if (error) { 436 device_printf(dev, "could not setup irq\n"); 437 goto fail; 438 } 439 440 /* 441 * Reset to a stable state. 442 */ 443 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET); 444 DELAY(10); 445 446 sc->cbl_base = malloc(sizeof(struct fxp_cb_tx) * FXP_NTXCB, 447 M_DEVBUF, M_NOWAIT | M_ZERO); 448 if (sc->cbl_base == NULL) 449 goto failmem; 450 451 sc->fxp_stats = malloc(sizeof(struct fxp_stats), M_DEVBUF, 452 M_NOWAIT | M_ZERO); 453 if (sc->fxp_stats == NULL) 454 goto failmem; 455 456 sc->mcsp = malloc(sizeof(struct fxp_cb_mcs), M_DEVBUF, M_NOWAIT); 457 if (sc->mcsp == NULL) 458 goto failmem; 459 460 /* 461 * Pre-allocate our receive buffers. 462 */ 463 for (i = 0; i < FXP_NRFABUFS; i++) { 464 if (fxp_add_rfabuf(sc, NULL) != 0) { 465 goto failmem; 466 } 467 } 468 469 /* 470 * Find out how large of an SEEPROM we have. 471 */ 472 fxp_autosize_eeprom(sc); 473 474 /* 475 * Determine whether we must use the 503 serial interface. 476 */ 477 fxp_read_eeprom(sc, &data, 6, 1); 478 if ((data & FXP_PHY_DEVICE_MASK) != 0 && 479 (data & FXP_PHY_SERIAL_ONLY)) 480 sc->flags |= FXP_FLAG_SERIAL_MEDIA; 481 482 /* 483 * Create the sysctl tree 484 */ 485 sc->sysctl_tree = SYSCTL_ADD_NODE(&sc->sysctl_ctx, 486 SYSCTL_STATIC_CHILDREN(_hw), OID_AUTO, 487 device_get_nameunit(dev), CTLFLAG_RD, 0, ""); 488 if (sc->sysctl_tree == NULL) 489 goto fail; 490 SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree), 491 OID_AUTO, "int_delay", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_PRISON, 492 &sc->tunable_int_delay, 0, &sysctl_hw_fxp_int_delay, "I", 493 "FXP driver receive interrupt microcode bundling delay"); 494 SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree), 495 OID_AUTO, "bundle_max", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_PRISON, 496 &sc->tunable_bundle_max, 0, &sysctl_hw_fxp_bundle_max, "I", 497 "FXP driver receive interrupt microcode bundle size limit"); 498 499 /* 500 * Pull in device tunables. 501 */ 502 sc->tunable_int_delay = TUNABLE_INT_DELAY; 503 sc->tunable_bundle_max = TUNABLE_BUNDLE_MAX; 504 (void) resource_int_value(device_get_name(dev), device_get_unit(dev), 505 "int_delay", &sc->tunable_int_delay); 506 (void) resource_int_value(device_get_name(dev), device_get_unit(dev), 507 "bundle_max", &sc->tunable_bundle_max); 508 509 /* 510 * Find out the chip revision; lump all 82557 revs together. 511 */ 512 fxp_read_eeprom(sc, &data, 5, 1); 513 if ((data >> 8) == 1) 514 sc->revision = FXP_REV_82557; 515 else 516 sc->revision = pci_get_revid(dev); 517 518 /* 519 * Enable workarounds for certain chip revision deficiencies. 520 * 521 * Systems based on the ICH2/ICH2-M chip from Intel, and possibly 522 * some systems based a normal 82559 design, have a defect where 523 * the chip can cause a PCI protocol violation if it receives 524 * a CU_RESUME command when it is entering the IDLE state. The 525 * workaround is to disable Dynamic Standby Mode, so the chip never 526 * deasserts CLKRUN#, and always remains in an active state. 527 * 528 * See Intel 82801BA/82801BAM Specification Update, Errata #30. 529 */ 530 i = pci_get_device(dev); 531 if (i == 0x2449 || (i > 0x1030 && i < 0x1039) || 532 sc->revision >= FXP_REV_82559_A0) { 533 fxp_read_eeprom(sc, &data, 10, 1); 534 if (data & 0x02) { /* STB enable */ 535 u_int16_t cksum; 536 int i; 537 538 device_printf(dev, 539 "Disabling dynamic standby mode in EEPROM\n"); 540 data &= ~0x02; 541 fxp_write_eeprom(sc, &data, 10, 1); 542 device_printf(dev, "New EEPROM ID: 0x%x\n", data); 543 cksum = 0; 544 for (i = 0; i < (1 << sc->eeprom_size) - 1; i++) { 545 fxp_read_eeprom(sc, &data, i, 1); 546 cksum += data; 547 } 548 i = (1 << sc->eeprom_size) - 1; 549 cksum = 0xBABA - cksum; 550 fxp_read_eeprom(sc, &data, i, 1); 551 fxp_write_eeprom(sc, &cksum, i, 1); 552 device_printf(dev, 553 "EEPROM checksum @ 0x%x: 0x%x -> 0x%x\n", 554 i, data, cksum); 555 #if 1 556 /* 557 * If the user elects to continue, try the software 558 * workaround, as it is better than nothing. 559 */ 560 sc->flags |= FXP_FLAG_CU_RESUME_BUG; 561 #endif 562 } 563 } 564 565 /* 566 * If we are not a 82557 chip, we can enable extended features. 567 */ 568 if (sc->revision != FXP_REV_82557) { 569 /* 570 * If MWI is enabled in the PCI configuration, and there 571 * is a valid cacheline size (8 or 16 dwords), then tell 572 * the board to turn on MWI. 573 */ 574 if (val & PCIM_CMD_MWRICEN && 575 pci_read_config(dev, PCIR_CACHELNSZ, 1) != 0) 576 sc->flags |= FXP_FLAG_MWI_ENABLE; 577 578 /* turn on the extended TxCB feature */ 579 sc->flags |= FXP_FLAG_EXT_TXCB; 580 581 /* enable reception of long frames for VLAN */ 582 sc->flags |= FXP_FLAG_LONG_PKT_EN; 583 } 584 585 /* 586 * Read MAC address. 587 */ 588 fxp_read_eeprom(sc, (u_int16_t *)sc->arpcom.ac_enaddr, 0, 3); 589 device_printf(dev, "Ethernet address %6D%s\n", 590 sc->arpcom.ac_enaddr, ":", 591 sc->flags & FXP_FLAG_SERIAL_MEDIA ? ", 10Mbps" : ""); 592 if (bootverbose) { 593 device_printf(dev, "PCI IDs: %04x %04x %04x %04x %04x\n", 594 pci_get_vendor(dev), pci_get_device(dev), 595 pci_get_subvendor(dev), pci_get_subdevice(dev), 596 pci_get_revid(dev)); 597 fxp_read_eeprom(sc, &data, 10, 1); 598 device_printf(dev, "Dynamic Standby mode is %s\n", 599 data & 0x02 ? "enabled" : "disabled"); 600 } 601 602 /* 603 * If this is only a 10Mbps device, then there is no MII, and 604 * the PHY will use a serial interface instead. 605 * 606 * The Seeq 80c24 AutoDUPLEX(tm) Ethernet Interface Adapter 607 * doesn't have a programming interface of any sort. The 608 * media is sensed automatically based on how the link partner 609 * is configured. This is, in essence, manual configuration. 610 */ 611 if (sc->flags & FXP_FLAG_SERIAL_MEDIA) { 612 ifmedia_init(&sc->sc_media, 0, fxp_serial_ifmedia_upd, 613 fxp_serial_ifmedia_sts); 614 ifmedia_add(&sc->sc_media, IFM_ETHER|IFM_MANUAL, 0, NULL); 615 ifmedia_set(&sc->sc_media, IFM_ETHER|IFM_MANUAL); 616 } else { 617 if (mii_phy_probe(dev, &sc->miibus, fxp_ifmedia_upd, 618 fxp_ifmedia_sts)) { 619 device_printf(dev, "MII without any PHY!\n"); 620 error = ENXIO; 621 goto fail; 622 } 623 } 624 625 ifp = &sc->arpcom.ac_if; 626 ifp->if_unit = device_get_unit(dev); 627 ifp->if_name = "fxp"; 628 ifp->if_output = ether_output; 629 ifp->if_baudrate = 100000000; 630 ifp->if_init = fxp_init; 631 ifp->if_softc = sc; 632 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 633 ifp->if_ioctl = fxp_ioctl; 634 ifp->if_start = fxp_start; 635 ifp->if_watchdog = fxp_watchdog; 636 637 /* 638 * Attach the interface. 639 */ 640 ether_ifattach(ifp, ETHER_BPF_SUPPORTED); 641 642 /* 643 * Tell the upper layer(s) we support long frames. 644 */ 645 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 646 647 /* 648 * Let the system queue as many packets as we have available 649 * TX descriptors. 650 */ 651 ifp->if_snd.ifq_maxlen = FXP_NTXCB - 1; 652 653 splx(s); 654 return (0); 655 656 failmem: 657 device_printf(dev, "Failed to malloc memory\n"); 658 error = ENOMEM; 659 fail: 660 splx(s); 661 fxp_release(sc); 662 return (error); 663 } 664 665 /* 666 * release all resources 667 */ 668 static void 669 fxp_release(struct fxp_softc *sc) 670 { 671 672 bus_generic_detach(sc->dev); 673 if (sc->miibus) 674 device_delete_child(sc->dev, sc->miibus); 675 676 if (sc->cbl_base) 677 free(sc->cbl_base, M_DEVBUF); 678 if (sc->fxp_stats) 679 free(sc->fxp_stats, M_DEVBUF); 680 if (sc->mcsp) 681 free(sc->mcsp, M_DEVBUF); 682 if (sc->rfa_headm) 683 m_freem(sc->rfa_headm); 684 685 if (sc->ih) 686 bus_teardown_intr(sc->dev, sc->irq, sc->ih); 687 if (sc->irq) 688 bus_release_resource(sc->dev, SYS_RES_IRQ, 0, sc->irq); 689 if (sc->mem) 690 bus_release_resource(sc->dev, sc->rtp, sc->rgd, sc->mem); 691 692 sysctl_ctx_free(&sc->sysctl_ctx); 693 694 mtx_destroy(&sc->sc_mtx); 695 } 696 697 /* 698 * Detach interface. 699 */ 700 static int 701 fxp_detach(device_t dev) 702 { 703 struct fxp_softc *sc = device_get_softc(dev); 704 int s; 705 706 /* disable interrupts */ 707 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE); 708 709 s = splimp(); 710 711 /* 712 * Stop DMA and drop transmit queue. 713 */ 714 fxp_stop(sc); 715 716 /* 717 * Close down routes etc. 718 */ 719 ether_ifdetach(&sc->arpcom.ac_if, ETHER_BPF_SUPPORTED); 720 721 /* 722 * Free all media structures. 723 */ 724 ifmedia_removeall(&sc->sc_media); 725 726 splx(s); 727 728 /* Release our allocated resources. */ 729 fxp_release(sc); 730 731 return (0); 732 } 733 734 /* 735 * Device shutdown routine. Called at system shutdown after sync. The 736 * main purpose of this routine is to shut off receiver DMA so that 737 * kernel memory doesn't get clobbered during warmboot. 738 */ 739 static int 740 fxp_shutdown(device_t dev) 741 { 742 /* 743 * Make sure that DMA is disabled prior to reboot. Not doing 744 * do could allow DMA to corrupt kernel memory during the 745 * reboot before the driver initializes. 746 */ 747 fxp_stop((struct fxp_softc *) device_get_softc(dev)); 748 return (0); 749 } 750 751 /* 752 * Device suspend routine. Stop the interface and save some PCI 753 * settings in case the BIOS doesn't restore them properly on 754 * resume. 755 */ 756 static int 757 fxp_suspend(device_t dev) 758 { 759 struct fxp_softc *sc = device_get_softc(dev); 760 int i, s; 761 762 s = splimp(); 763 764 fxp_stop(sc); 765 766 for (i = 0; i < 5; i++) 767 sc->saved_maps[i] = pci_read_config(dev, PCIR_MAPS + i * 4, 4); 768 sc->saved_biosaddr = pci_read_config(dev, PCIR_BIOS, 4); 769 sc->saved_intline = pci_read_config(dev, PCIR_INTLINE, 1); 770 sc->saved_cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1); 771 sc->saved_lattimer = pci_read_config(dev, PCIR_LATTIMER, 1); 772 773 sc->suspended = 1; 774 775 splx(s); 776 return (0); 777 } 778 779 /* 780 * Device resume routine. Restore some PCI settings in case the BIOS 781 * doesn't, re-enable busmastering, and restart the interface if 782 * appropriate. 783 */ 784 static int 785 fxp_resume(device_t dev) 786 { 787 struct fxp_softc *sc = device_get_softc(dev); 788 struct ifnet *ifp = &sc->sc_if; 789 u_int16_t pci_command; 790 int i, s; 791 792 s = splimp(); 793 794 fxp_powerstate_d0(dev); 795 796 /* better way to do this? */ 797 for (i = 0; i < 5; i++) 798 pci_write_config(dev, PCIR_MAPS + i * 4, sc->saved_maps[i], 4); 799 pci_write_config(dev, PCIR_BIOS, sc->saved_biosaddr, 4); 800 pci_write_config(dev, PCIR_INTLINE, sc->saved_intline, 1); 801 pci_write_config(dev, PCIR_CACHELNSZ, sc->saved_cachelnsz, 1); 802 pci_write_config(dev, PCIR_LATTIMER, sc->saved_lattimer, 1); 803 804 /* reenable busmastering */ 805 pci_command = pci_read_config(dev, PCIR_COMMAND, 2); 806 pci_command |= (PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN); 807 pci_write_config(dev, PCIR_COMMAND, pci_command, 2); 808 809 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET); 810 DELAY(10); 811 812 /* reinitialize interface if necessary */ 813 if (ifp->if_flags & IFF_UP) 814 fxp_init(sc); 815 816 sc->suspended = 0; 817 818 splx(s); 819 return (0); 820 } 821 822 static void 823 fxp_eeprom_shiftin(struct fxp_softc *sc, int data, int length) 824 { 825 u_int16_t reg; 826 int x; 827 828 /* 829 * Shift in data. 830 */ 831 for (x = 1 << (length - 1); x; x >>= 1) { 832 if (data & x) 833 reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI; 834 else 835 reg = FXP_EEPROM_EECS; 836 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 837 DELAY(1); 838 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK); 839 DELAY(1); 840 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 841 DELAY(1); 842 } 843 } 844 845 /* 846 * Read from the serial EEPROM. Basically, you manually shift in 847 * the read opcode (one bit at a time) and then shift in the address, 848 * and then you shift out the data (all of this one bit at a time). 849 * The word size is 16 bits, so you have to provide the address for 850 * every 16 bits of data. 851 */ 852 static u_int16_t 853 fxp_eeprom_getword(struct fxp_softc *sc, int offset, int autosize) 854 { 855 u_int16_t reg, data; 856 int x; 857 858 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 859 /* 860 * Shift in read opcode. 861 */ 862 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_READ, 3); 863 /* 864 * Shift in address. 865 */ 866 data = 0; 867 for (x = 1 << (sc->eeprom_size - 1); x; x >>= 1) { 868 if (offset & x) 869 reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI; 870 else 871 reg = FXP_EEPROM_EECS; 872 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 873 DELAY(1); 874 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK); 875 DELAY(1); 876 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 877 DELAY(1); 878 reg = CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO; 879 data++; 880 if (autosize && reg == 0) { 881 sc->eeprom_size = data; 882 break; 883 } 884 } 885 /* 886 * Shift out data. 887 */ 888 data = 0; 889 reg = FXP_EEPROM_EECS; 890 for (x = 1 << 15; x; x >>= 1) { 891 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK); 892 DELAY(1); 893 if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO) 894 data |= x; 895 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 896 DELAY(1); 897 } 898 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 899 DELAY(1); 900 901 return (data); 902 } 903 904 static void 905 fxp_eeprom_putword(struct fxp_softc *sc, int offset, u_int16_t data) 906 { 907 int i; 908 909 /* 910 * Erase/write enable. 911 */ 912 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 913 fxp_eeprom_shiftin(sc, 0x4, 3); 914 fxp_eeprom_shiftin(sc, 0x03 << (sc->eeprom_size - 2), sc->eeprom_size); 915 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 916 DELAY(1); 917 /* 918 * Shift in write opcode, address, data. 919 */ 920 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 921 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_WRITE, 3); 922 fxp_eeprom_shiftin(sc, offset, sc->eeprom_size); 923 fxp_eeprom_shiftin(sc, data, 16); 924 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 925 DELAY(1); 926 /* 927 * Wait for EEPROM to finish up. 928 */ 929 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 930 DELAY(1); 931 for (i = 0; i < 1000; i++) { 932 if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO) 933 break; 934 DELAY(50); 935 } 936 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 937 DELAY(1); 938 /* 939 * Erase/write disable. 940 */ 941 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 942 fxp_eeprom_shiftin(sc, 0x4, 3); 943 fxp_eeprom_shiftin(sc, 0, sc->eeprom_size); 944 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 945 DELAY(1); 946 } 947 948 /* 949 * From NetBSD: 950 * 951 * Figure out EEPROM size. 952 * 953 * 559's can have either 64-word or 256-word EEPROMs, the 558 954 * datasheet only talks about 64-word EEPROMs, and the 557 datasheet 955 * talks about the existance of 16 to 256 word EEPROMs. 956 * 957 * The only known sizes are 64 and 256, where the 256 version is used 958 * by CardBus cards to store CIS information. 959 * 960 * The address is shifted in msb-to-lsb, and after the last 961 * address-bit the EEPROM is supposed to output a `dummy zero' bit, 962 * after which follows the actual data. We try to detect this zero, by 963 * probing the data-out bit in the EEPROM control register just after 964 * having shifted in a bit. If the bit is zero, we assume we've 965 * shifted enough address bits. The data-out should be tri-state, 966 * before this, which should translate to a logical one. 967 */ 968 static void 969 fxp_autosize_eeprom(struct fxp_softc *sc) 970 { 971 972 /* guess maximum size of 256 words */ 973 sc->eeprom_size = 8; 974 975 /* autosize */ 976 (void) fxp_eeprom_getword(sc, 0, 1); 977 } 978 979 static void 980 fxp_read_eeprom(struct fxp_softc *sc, u_short *data, int offset, int words) 981 { 982 int i; 983 984 for (i = 0; i < words; i++) 985 data[i] = fxp_eeprom_getword(sc, offset + i, 0); 986 } 987 988 static void 989 fxp_write_eeprom(struct fxp_softc *sc, u_short *data, int offset, int words) 990 { 991 int i; 992 993 for (i = 0; i < words; i++) 994 fxp_eeprom_putword(sc, offset + i, data[i]); 995 } 996 997 /* 998 * Start packet transmission on the interface. 999 */ 1000 static void 1001 fxp_start(struct ifnet *ifp) 1002 { 1003 struct fxp_softc *sc = ifp->if_softc; 1004 struct fxp_cb_tx *txp; 1005 1006 /* 1007 * See if we need to suspend xmit until the multicast filter 1008 * has been reprogrammed (which can only be done at the head 1009 * of the command chain). 1010 */ 1011 if (sc->need_mcsetup) { 1012 return; 1013 } 1014 1015 txp = NULL; 1016 1017 /* 1018 * We're finished if there is nothing more to add to the list or if 1019 * we're all filled up with buffers to transmit. 1020 * NOTE: One TxCB is reserved to guarantee that fxp_mc_setup() can add 1021 * a NOP command when needed. 1022 */ 1023 while (ifp->if_snd.ifq_head != NULL && sc->tx_queued < FXP_NTXCB - 1) { 1024 struct mbuf *m, *mb_head; 1025 int segment; 1026 1027 /* 1028 * Grab a packet to transmit. 1029 */ 1030 IF_DEQUEUE(&ifp->if_snd, mb_head); 1031 1032 /* 1033 * Get pointer to next available tx desc. 1034 */ 1035 txp = sc->cbl_last->next; 1036 1037 /* 1038 * Go through each of the mbufs in the chain and initialize 1039 * the transmit buffer descriptors with the physical address 1040 * and size of the mbuf. 1041 */ 1042 tbdinit: 1043 for (m = mb_head, segment = 0; m != NULL; m = m->m_next) { 1044 if (m->m_len != 0) { 1045 if (segment == FXP_NTXSEG) 1046 break; 1047 txp->tbd[segment].tb_addr = 1048 vtophys(mtod(m, vm_offset_t)); 1049 txp->tbd[segment].tb_size = m->m_len; 1050 segment++; 1051 } 1052 } 1053 if (m != NULL) { 1054 struct mbuf *mn; 1055 1056 /* 1057 * We ran out of segments. We have to recopy this 1058 * mbuf chain first. Bail out if we can't get the 1059 * new buffers. 1060 */ 1061 MGETHDR(mn, M_DONTWAIT, MT_DATA); 1062 if (mn == NULL) { 1063 m_freem(mb_head); 1064 break; 1065 } 1066 if (mb_head->m_pkthdr.len > MHLEN) { 1067 MCLGET(mn, M_DONTWAIT); 1068 if ((mn->m_flags & M_EXT) == 0) { 1069 m_freem(mn); 1070 m_freem(mb_head); 1071 break; 1072 } 1073 } 1074 m_copydata(mb_head, 0, mb_head->m_pkthdr.len, 1075 mtod(mn, caddr_t)); 1076 mn->m_pkthdr.len = mn->m_len = mb_head->m_pkthdr.len; 1077 m_freem(mb_head); 1078 mb_head = mn; 1079 goto tbdinit; 1080 } 1081 1082 txp->tbd_number = segment; 1083 txp->mb_head = mb_head; 1084 txp->cb_status = 0; 1085 if (sc->tx_queued != FXP_CXINT_THRESH - 1) { 1086 txp->cb_command = 1087 FXP_CB_COMMAND_XMIT | FXP_CB_COMMAND_SF | 1088 FXP_CB_COMMAND_S; 1089 } else { 1090 txp->cb_command = 1091 FXP_CB_COMMAND_XMIT | FXP_CB_COMMAND_SF | 1092 FXP_CB_COMMAND_S | FXP_CB_COMMAND_I; 1093 /* 1094 * Set a 5 second timer just in case we don't hear 1095 * from the card again. 1096 */ 1097 ifp->if_timer = 5; 1098 } 1099 txp->tx_threshold = tx_threshold; 1100 1101 /* 1102 * Advance the end of list forward. 1103 */ 1104 1105 #ifdef __alpha__ 1106 /* 1107 * On platforms which can't access memory in 16-bit 1108 * granularities, we must prevent the card from DMA'ing 1109 * up the status while we update the command field. 1110 * This could cause us to overwrite the completion status. 1111 */ 1112 atomic_clear_short(&sc->cbl_last->cb_command, 1113 FXP_CB_COMMAND_S); 1114 #else 1115 sc->cbl_last->cb_command &= ~FXP_CB_COMMAND_S; 1116 #endif /*__alpha__*/ 1117 sc->cbl_last = txp; 1118 1119 /* 1120 * Advance the beginning of the list forward if there are 1121 * no other packets queued (when nothing is queued, cbl_first 1122 * sits on the last TxCB that was sent out). 1123 */ 1124 if (sc->tx_queued == 0) 1125 sc->cbl_first = txp; 1126 1127 sc->tx_queued++; 1128 1129 /* 1130 * Pass packet to bpf if there is a listener. 1131 */ 1132 if (ifp->if_bpf) 1133 bpf_mtap(ifp, mb_head); 1134 } 1135 1136 /* 1137 * We're finished. If we added to the list, issue a RESUME to get DMA 1138 * going again if suspended. 1139 */ 1140 if (txp != NULL) { 1141 fxp_scb_wait(sc); 1142 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_RESUME); 1143 } 1144 } 1145 1146 static void fxp_intr_body(struct fxp_softc *sc, u_int8_t statack, int count); 1147 1148 #ifdef DEVICE_POLLING 1149 static poll_handler_t fxp_poll; 1150 1151 static void 1152 fxp_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 1153 { 1154 struct fxp_softc *sc = ifp->if_softc; 1155 u_int8_t statack; 1156 1157 if (cmd == POLL_DEREGISTER) { /* final call, enable interrupts */ 1158 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, 0); 1159 return; 1160 } 1161 statack = FXP_SCB_STATACK_CXTNO | FXP_SCB_STATACK_CNA | 1162 FXP_SCB_STATACK_FR; 1163 if (cmd == POLL_AND_CHECK_STATUS) { 1164 u_int8_t tmp; 1165 1166 tmp = CSR_READ_1(sc, FXP_CSR_SCB_STATACK); 1167 if (tmp == 0xff || tmp == 0) 1168 return; /* nothing to do */ 1169 tmp &= ~statack; 1170 /* ack what we can */ 1171 if (tmp != 0) 1172 CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, tmp); 1173 statack |= tmp; 1174 } 1175 fxp_intr_body(sc, statack, count); 1176 } 1177 #endif /* DEVICE_POLLING */ 1178 1179 /* 1180 * Process interface interrupts. 1181 */ 1182 static void 1183 fxp_intr(void *xsc) 1184 { 1185 struct fxp_softc *sc = xsc; 1186 u_int8_t statack; 1187 1188 #ifdef DEVICE_POLLING 1189 struct ifnet *ifp = &sc->sc_if; 1190 1191 if (ifp->if_ipending & IFF_POLLING) 1192 return; 1193 if (ether_poll_register(fxp_poll, ifp)) { 1194 /* disable interrupts */ 1195 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE); 1196 fxp_poll(ifp, 0, 1); 1197 return; 1198 } 1199 #endif 1200 1201 if (sc->suspended) { 1202 return; 1203 } 1204 1205 while ((statack = CSR_READ_1(sc, FXP_CSR_SCB_STATACK)) != 0) { 1206 /* 1207 * It should not be possible to have all bits set; the 1208 * FXP_SCB_INTR_SWI bit always returns 0 on a read. If 1209 * all bits are set, this may indicate that the card has 1210 * been physically ejected, so ignore it. 1211 */ 1212 if (statack == 0xff) 1213 return; 1214 1215 /* 1216 * First ACK all the interrupts in this pass. 1217 */ 1218 CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, statack); 1219 fxp_intr_body(sc, statack, -1); 1220 } 1221 } 1222 1223 static void 1224 fxp_intr_body(struct fxp_softc *sc, u_int8_t statack, int count) 1225 { 1226 struct ifnet *ifp = &sc->sc_if; 1227 1228 /* 1229 * Free any finished transmit mbuf chains. 1230 * 1231 * Handle the CNA event likt a CXTNO event. It used to 1232 * be that this event (control unit not ready) was not 1233 * encountered, but it is now with the SMPng modifications. 1234 * The exact sequence of events that occur when the interface 1235 * is brought up are different now, and if this event 1236 * goes unhandled, the configuration/rxfilter setup sequence 1237 * can stall for several seconds. The result is that no 1238 * packets go out onto the wire for about 5 to 10 seconds 1239 * after the interface is ifconfig'ed for the first time. 1240 */ 1241 if (statack & (FXP_SCB_STATACK_CXTNO | FXP_SCB_STATACK_CNA)) { 1242 struct fxp_cb_tx *txp; 1243 1244 for (txp = sc->cbl_first; sc->tx_queued && 1245 (txp->cb_status & FXP_CB_STATUS_C) != 0; 1246 txp = txp->next) { 1247 if (txp->mb_head != NULL) { 1248 m_freem(txp->mb_head); 1249 txp->mb_head = NULL; 1250 } 1251 sc->tx_queued--; 1252 } 1253 sc->cbl_first = txp; 1254 ifp->if_timer = 0; 1255 if (sc->tx_queued == 0) { 1256 if (sc->need_mcsetup) 1257 fxp_mc_setup(sc); 1258 } 1259 /* 1260 * Try to start more packets transmitting. 1261 */ 1262 if (ifp->if_snd.ifq_head != NULL) 1263 fxp_start(ifp); 1264 } 1265 /* 1266 * Process receiver interrupts. If a no-resource (RNR) 1267 * condition exists, get whatever packets we can and 1268 * re-start the receiver. 1269 */ 1270 if (statack & (FXP_SCB_STATACK_FR | FXP_SCB_STATACK_RNR)) { 1271 struct mbuf *m; 1272 struct fxp_rfa *rfa; 1273 rcvloop: 1274 m = sc->rfa_headm; 1275 rfa = (struct fxp_rfa *)(m->m_ext.ext_buf + 1276 RFA_ALIGNMENT_FUDGE); 1277 1278 #ifdef DEVICE_POLLING /* loop at most count times if count >=0 */ 1279 if (count < 0 || count-- > 0) 1280 #endif 1281 if (rfa->rfa_status & FXP_RFA_STATUS_C) { 1282 /* 1283 * Remove first packet from the chain. 1284 */ 1285 sc->rfa_headm = m->m_next; 1286 m->m_next = NULL; 1287 1288 /* 1289 * Add a new buffer to the receive chain. 1290 * If this fails, the old buffer is recycled 1291 * instead. 1292 */ 1293 if (fxp_add_rfabuf(sc, m) == 0) { 1294 struct ether_header *eh; 1295 int total_len; 1296 1297 total_len = rfa->actual_size & 1298 (MCLBYTES - 1); 1299 if (total_len < 1300 sizeof(struct ether_header)) { 1301 m_freem(m); 1302 goto rcvloop; 1303 } 1304 1305 /* 1306 * Drop the packet if it has CRC 1307 * errors. This test is only needed 1308 * when doing 802.1q VLAN on the 82557 1309 * chip. 1310 */ 1311 if (rfa->rfa_status & 1312 FXP_RFA_STATUS_CRC) { 1313 m_freem(m); 1314 goto rcvloop; 1315 } 1316 1317 m->m_pkthdr.rcvif = ifp; 1318 m->m_pkthdr.len = m->m_len = total_len; 1319 eh = mtod(m, struct ether_header *); 1320 m->m_data += 1321 sizeof(struct ether_header); 1322 m->m_len -= 1323 sizeof(struct ether_header); 1324 m->m_pkthdr.len = m->m_len; 1325 ether_input(ifp, eh, m); 1326 } 1327 goto rcvloop; 1328 } 1329 if (statack & FXP_SCB_STATACK_RNR) { 1330 fxp_scb_wait(sc); 1331 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 1332 vtophys(sc->rfa_headm->m_ext.ext_buf) + 1333 RFA_ALIGNMENT_FUDGE); 1334 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_START); 1335 } 1336 } 1337 } 1338 1339 /* 1340 * Update packet in/out/collision statistics. The i82557 doesn't 1341 * allow you to access these counters without doing a fairly 1342 * expensive DMA to get _all_ of the statistics it maintains, so 1343 * we do this operation here only once per second. The statistics 1344 * counters in the kernel are updated from the previous dump-stats 1345 * DMA and then a new dump-stats DMA is started. The on-chip 1346 * counters are zeroed when the DMA completes. If we can't start 1347 * the DMA immediately, we don't wait - we just prepare to read 1348 * them again next time. 1349 */ 1350 static void 1351 fxp_tick(void *xsc) 1352 { 1353 struct fxp_softc *sc = xsc; 1354 struct ifnet *ifp = &sc->sc_if; 1355 struct fxp_stats *sp = sc->fxp_stats; 1356 struct fxp_cb_tx *txp; 1357 int s; 1358 1359 ifp->if_opackets += sp->tx_good; 1360 ifp->if_collisions += sp->tx_total_collisions; 1361 if (sp->rx_good) { 1362 ifp->if_ipackets += sp->rx_good; 1363 sc->rx_idle_secs = 0; 1364 } else { 1365 /* 1366 * Receiver's been idle for another second. 1367 */ 1368 sc->rx_idle_secs++; 1369 } 1370 ifp->if_ierrors += 1371 sp->rx_crc_errors + 1372 sp->rx_alignment_errors + 1373 sp->rx_rnr_errors + 1374 sp->rx_overrun_errors; 1375 /* 1376 * If any transmit underruns occured, bump up the transmit 1377 * threshold by another 512 bytes (64 * 8). 1378 */ 1379 if (sp->tx_underruns) { 1380 ifp->if_oerrors += sp->tx_underruns; 1381 if (tx_threshold < 192) 1382 tx_threshold += 64; 1383 } 1384 s = splimp(); 1385 /* 1386 * Release any xmit buffers that have completed DMA. This isn't 1387 * strictly necessary to do here, but it's advantagous for mbufs 1388 * with external storage to be released in a timely manner rather 1389 * than being defered for a potentially long time. This limits 1390 * the delay to a maximum of one second. 1391 */ 1392 for (txp = sc->cbl_first; sc->tx_queued && 1393 (txp->cb_status & FXP_CB_STATUS_C) != 0; 1394 txp = txp->next) { 1395 if (txp->mb_head != NULL) { 1396 m_freem(txp->mb_head); 1397 txp->mb_head = NULL; 1398 } 1399 sc->tx_queued--; 1400 } 1401 sc->cbl_first = txp; 1402 /* 1403 * If we haven't received any packets in FXP_MAC_RX_IDLE seconds, 1404 * then assume the receiver has locked up and attempt to clear 1405 * the condition by reprogramming the multicast filter. This is 1406 * a work-around for a bug in the 82557 where the receiver locks 1407 * up if it gets certain types of garbage in the syncronization 1408 * bits prior to the packet header. This bug is supposed to only 1409 * occur in 10Mbps mode, but has been seen to occur in 100Mbps 1410 * mode as well (perhaps due to a 10/100 speed transition). 1411 */ 1412 if (sc->rx_idle_secs > FXP_MAX_RX_IDLE) { 1413 sc->rx_idle_secs = 0; 1414 fxp_mc_setup(sc); 1415 } 1416 /* 1417 * If there is no pending command, start another stats 1418 * dump. Otherwise punt for now. 1419 */ 1420 if (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) == 0) { 1421 /* 1422 * Start another stats dump. 1423 */ 1424 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_DUMPRESET); 1425 } else { 1426 /* 1427 * A previous command is still waiting to be accepted. 1428 * Just zero our copy of the stats and wait for the 1429 * next timer event to update them. 1430 */ 1431 sp->tx_good = 0; 1432 sp->tx_underruns = 0; 1433 sp->tx_total_collisions = 0; 1434 1435 sp->rx_good = 0; 1436 sp->rx_crc_errors = 0; 1437 sp->rx_alignment_errors = 0; 1438 sp->rx_rnr_errors = 0; 1439 sp->rx_overrun_errors = 0; 1440 } 1441 if (sc->miibus != NULL) 1442 mii_tick(device_get_softc(sc->miibus)); 1443 splx(s); 1444 /* 1445 * Schedule another timeout one second from now. 1446 */ 1447 sc->stat_ch = timeout(fxp_tick, sc, hz); 1448 } 1449 1450 /* 1451 * Stop the interface. Cancels the statistics updater and resets 1452 * the interface. 1453 */ 1454 static void 1455 fxp_stop(struct fxp_softc *sc) 1456 { 1457 struct ifnet *ifp = &sc->sc_if; 1458 struct fxp_cb_tx *txp; 1459 int i; 1460 1461 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1462 ifp->if_timer = 0; 1463 1464 #ifdef DEVICE_POLLING 1465 ether_poll_deregister(ifp); 1466 #endif 1467 /* 1468 * Cancel stats updater. 1469 */ 1470 untimeout(fxp_tick, sc, sc->stat_ch); 1471 1472 /* 1473 * Issue software reset, which also unloads the microcode. 1474 */ 1475 sc->flags &= ~FXP_FLAG_UCODE; 1476 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SOFTWARE_RESET); 1477 DELAY(50); 1478 1479 /* 1480 * Release any xmit buffers. 1481 */ 1482 txp = sc->cbl_base; 1483 if (txp != NULL) { 1484 for (i = 0; i < FXP_NTXCB; i++) { 1485 if (txp[i].mb_head != NULL) { 1486 m_freem(txp[i].mb_head); 1487 txp[i].mb_head = NULL; 1488 } 1489 } 1490 } 1491 sc->tx_queued = 0; 1492 1493 /* 1494 * Free all the receive buffers then reallocate/reinitialize 1495 */ 1496 if (sc->rfa_headm != NULL) 1497 m_freem(sc->rfa_headm); 1498 sc->rfa_headm = NULL; 1499 sc->rfa_tailm = NULL; 1500 for (i = 0; i < FXP_NRFABUFS; i++) { 1501 if (fxp_add_rfabuf(sc, NULL) != 0) { 1502 /* 1503 * This "can't happen" - we're at splimp() 1504 * and we just freed all the buffers we need 1505 * above. 1506 */ 1507 panic("fxp_stop: no buffers!"); 1508 } 1509 } 1510 } 1511 1512 /* 1513 * Watchdog/transmission transmit timeout handler. Called when a 1514 * transmission is started on the interface, but no interrupt is 1515 * received before the timeout. This usually indicates that the 1516 * card has wedged for some reason. 1517 */ 1518 static void 1519 fxp_watchdog(struct ifnet *ifp) 1520 { 1521 struct fxp_softc *sc = ifp->if_softc; 1522 1523 device_printf(sc->dev, "device timeout\n"); 1524 ifp->if_oerrors++; 1525 1526 fxp_init(sc); 1527 } 1528 1529 static void 1530 fxp_init(void *xsc) 1531 { 1532 struct fxp_softc *sc = xsc; 1533 struct ifnet *ifp = &sc->sc_if; 1534 struct fxp_cb_config *cbp; 1535 struct fxp_cb_ias *cb_ias; 1536 struct fxp_cb_tx *txp; 1537 struct fxp_cb_mcs *mcsp; 1538 int i, prm, s; 1539 1540 s = splimp(); 1541 /* 1542 * Cancel any pending I/O 1543 */ 1544 fxp_stop(sc); 1545 1546 prm = (ifp->if_flags & IFF_PROMISC) ? 1 : 0; 1547 1548 /* 1549 * Initialize base of CBL and RFA memory. Loading with zero 1550 * sets it up for regular linear addressing. 1551 */ 1552 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 0); 1553 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_BASE); 1554 1555 fxp_scb_wait(sc); 1556 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_BASE); 1557 1558 /* 1559 * Initialize base of dump-stats buffer. 1560 */ 1561 fxp_scb_wait(sc); 1562 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, vtophys(sc->fxp_stats)); 1563 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_DUMP_ADR); 1564 1565 /* 1566 * Attempt to load microcode if requested. 1567 */ 1568 if (ifp->if_flags & IFF_LINK0 && (sc->flags & FXP_FLAG_UCODE) == 0) 1569 fxp_load_ucode(sc); 1570 1571 /* 1572 * Initialize the multicast address list. 1573 */ 1574 if (fxp_mc_addrs(sc)) { 1575 mcsp = sc->mcsp; 1576 mcsp->cb_status = 0; 1577 mcsp->cb_command = FXP_CB_COMMAND_MCAS | FXP_CB_COMMAND_EL; 1578 mcsp->link_addr = -1; 1579 /* 1580 * Start the multicast setup command. 1581 */ 1582 fxp_scb_wait(sc); 1583 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, vtophys(&mcsp->cb_status)); 1584 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 1585 /* ...and wait for it to complete. */ 1586 fxp_dma_wait(&mcsp->cb_status, sc); 1587 } 1588 1589 /* 1590 * We temporarily use memory that contains the TxCB list to 1591 * construct the config CB. The TxCB list memory is rebuilt 1592 * later. 1593 */ 1594 cbp = (struct fxp_cb_config *) sc->cbl_base; 1595 1596 /* 1597 * This bcopy is kind of disgusting, but there are a bunch of must be 1598 * zero and must be one bits in this structure and this is the easiest 1599 * way to initialize them all to proper values. 1600 */ 1601 bcopy(fxp_cb_config_template, 1602 (void *)(uintptr_t)(volatile void *)&cbp->cb_status, 1603 sizeof(fxp_cb_config_template)); 1604 1605 cbp->cb_status = 0; 1606 cbp->cb_command = FXP_CB_COMMAND_CONFIG | FXP_CB_COMMAND_EL; 1607 cbp->link_addr = -1; /* (no) next command */ 1608 cbp->byte_count = 22; /* (22) bytes to config */ 1609 cbp->rx_fifo_limit = 8; /* rx fifo threshold (32 bytes) */ 1610 cbp->tx_fifo_limit = 0; /* tx fifo threshold (0 bytes) */ 1611 cbp->adaptive_ifs = 0; /* (no) adaptive interframe spacing */ 1612 cbp->mwi_enable = sc->flags & FXP_FLAG_MWI_ENABLE ? 1 : 0; 1613 cbp->type_enable = 0; /* actually reserved */ 1614 cbp->read_align_en = sc->flags & FXP_FLAG_READ_ALIGN ? 1 : 0; 1615 cbp->end_wr_on_cl = sc->flags & FXP_FLAG_WRITE_ALIGN ? 1 : 0; 1616 cbp->rx_dma_bytecount = 0; /* (no) rx DMA max */ 1617 cbp->tx_dma_bytecount = 0; /* (no) tx DMA max */ 1618 cbp->dma_mbce = 0; /* (disable) dma max counters */ 1619 cbp->late_scb = 0; /* (don't) defer SCB update */ 1620 cbp->direct_dma_dis = 1; /* disable direct rcv dma mode */ 1621 cbp->tno_int_or_tco_en =0; /* (disable) tx not okay interrupt */ 1622 cbp->ci_int = 1; /* interrupt on CU idle */ 1623 cbp->ext_txcb_dis = sc->flags & FXP_FLAG_EXT_TXCB ? 0 : 1; 1624 cbp->ext_stats_dis = 1; /* disable extended counters */ 1625 cbp->keep_overrun_rx = 0; /* don't pass overrun frames to host */ 1626 cbp->save_bf = sc->revision == FXP_REV_82557 ? 1 : prm; 1627 cbp->disc_short_rx = !prm; /* discard short packets */ 1628 cbp->underrun_retry = 1; /* retry mode (once) on DMA underrun */ 1629 cbp->two_frames = 0; /* do not limit FIFO to 2 frames */ 1630 cbp->dyn_tbd = 0; /* (no) dynamic TBD mode */ 1631 cbp->mediatype = sc->flags & FXP_FLAG_SERIAL_MEDIA ? 0 : 1; 1632 cbp->csma_dis = 0; /* (don't) disable link */ 1633 cbp->tcp_udp_cksum = 0; /* (don't) enable checksum */ 1634 cbp->vlan_tco = 0; /* (don't) enable vlan wakeup */ 1635 cbp->link_wake_en = 0; /* (don't) assert PME# on link change */ 1636 cbp->arp_wake_en = 0; /* (don't) assert PME# on arp */ 1637 cbp->mc_wake_en = 0; /* (don't) enable PME# on mcmatch */ 1638 cbp->nsai = 1; /* (don't) disable source addr insert */ 1639 cbp->preamble_length = 2; /* (7 byte) preamble */ 1640 cbp->loopback = 0; /* (don't) loopback */ 1641 cbp->linear_priority = 0; /* (normal CSMA/CD operation) */ 1642 cbp->linear_pri_mode = 0; /* (wait after xmit only) */ 1643 cbp->interfrm_spacing = 6; /* (96 bits of) interframe spacing */ 1644 cbp->promiscuous = prm; /* promiscuous mode */ 1645 cbp->bcast_disable = 0; /* (don't) disable broadcasts */ 1646 cbp->wait_after_win = 0; /* (don't) enable modified backoff alg*/ 1647 cbp->ignore_ul = 0; /* consider U/L bit in IA matching */ 1648 cbp->crc16_en = 0; /* (don't) enable crc-16 algorithm */ 1649 cbp->crscdt = sc->flags & FXP_FLAG_SERIAL_MEDIA ? 1 : 0; 1650 1651 cbp->stripping = !prm; /* truncate rx packet to byte count */ 1652 cbp->padding = 1; /* (do) pad short tx packets */ 1653 cbp->rcv_crc_xfer = 0; /* (don't) xfer CRC to host */ 1654 cbp->long_rx_en = sc->flags & FXP_FLAG_LONG_PKT_EN ? 1 : 0; 1655 cbp->ia_wake_en = 0; /* (don't) wake up on address match */ 1656 cbp->magic_pkt_dis = 0; /* (don't) disable magic packet */ 1657 /* must set wake_en in PMCSR also */ 1658 cbp->force_fdx = 0; /* (don't) force full duplex */ 1659 cbp->fdx_pin_en = 1; /* (enable) FDX# pin */ 1660 cbp->multi_ia = 0; /* (don't) accept multiple IAs */ 1661 cbp->mc_all = sc->flags & FXP_FLAG_ALL_MCAST ? 1 : 0; 1662 1663 if (sc->revision == FXP_REV_82557) { 1664 /* 1665 * The 82557 has no hardware flow control, the values 1666 * below are the defaults for the chip. 1667 */ 1668 cbp->fc_delay_lsb = 0; 1669 cbp->fc_delay_msb = 0x40; 1670 cbp->pri_fc_thresh = 3; 1671 cbp->tx_fc_dis = 0; 1672 cbp->rx_fc_restop = 0; 1673 cbp->rx_fc_restart = 0; 1674 cbp->fc_filter = 0; 1675 cbp->pri_fc_loc = 1; 1676 } else { 1677 cbp->fc_delay_lsb = 0x1f; 1678 cbp->fc_delay_msb = 0x01; 1679 cbp->pri_fc_thresh = 3; 1680 cbp->tx_fc_dis = 0; /* enable transmit FC */ 1681 cbp->rx_fc_restop = 1; /* enable FC restop frames */ 1682 cbp->rx_fc_restart = 1; /* enable FC restart frames */ 1683 cbp->fc_filter = !prm; /* drop FC frames to host */ 1684 cbp->pri_fc_loc = 1; /* FC pri location (byte31) */ 1685 } 1686 1687 /* 1688 * Start the config command/DMA. 1689 */ 1690 fxp_scb_wait(sc); 1691 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, vtophys(&cbp->cb_status)); 1692 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 1693 /* ...and wait for it to complete. */ 1694 fxp_dma_wait(&cbp->cb_status, sc); 1695 1696 /* 1697 * Now initialize the station address. Temporarily use the TxCB 1698 * memory area like we did above for the config CB. 1699 */ 1700 cb_ias = (struct fxp_cb_ias *) sc->cbl_base; 1701 cb_ias->cb_status = 0; 1702 cb_ias->cb_command = FXP_CB_COMMAND_IAS | FXP_CB_COMMAND_EL; 1703 cb_ias->link_addr = -1; 1704 bcopy(sc->arpcom.ac_enaddr, 1705 (void *)(uintptr_t)(volatile void *)cb_ias->macaddr, 1706 sizeof(sc->arpcom.ac_enaddr)); 1707 1708 /* 1709 * Start the IAS (Individual Address Setup) command/DMA. 1710 */ 1711 fxp_scb_wait(sc); 1712 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 1713 /* ...and wait for it to complete. */ 1714 fxp_dma_wait(&cb_ias->cb_status, sc); 1715 1716 /* 1717 * Initialize transmit control block (TxCB) list. 1718 */ 1719 1720 txp = sc->cbl_base; 1721 bzero(txp, sizeof(struct fxp_cb_tx) * FXP_NTXCB); 1722 for (i = 0; i < FXP_NTXCB; i++) { 1723 txp[i].cb_status = FXP_CB_STATUS_C | FXP_CB_STATUS_OK; 1724 txp[i].cb_command = FXP_CB_COMMAND_NOP; 1725 txp[i].link_addr = 1726 vtophys(&txp[(i + 1) & FXP_TXCB_MASK].cb_status); 1727 if (sc->flags & FXP_FLAG_EXT_TXCB) 1728 txp[i].tbd_array_addr = vtophys(&txp[i].tbd[2]); 1729 else 1730 txp[i].tbd_array_addr = vtophys(&txp[i].tbd[0]); 1731 txp[i].next = &txp[(i + 1) & FXP_TXCB_MASK]; 1732 } 1733 /* 1734 * Set the suspend flag on the first TxCB and start the control 1735 * unit. It will execute the NOP and then suspend. 1736 */ 1737 txp->cb_command = FXP_CB_COMMAND_NOP | FXP_CB_COMMAND_S; 1738 sc->cbl_first = sc->cbl_last = txp; 1739 sc->tx_queued = 1; 1740 1741 fxp_scb_wait(sc); 1742 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 1743 1744 /* 1745 * Initialize receiver buffer area - RFA. 1746 */ 1747 fxp_scb_wait(sc); 1748 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 1749 vtophys(sc->rfa_headm->m_ext.ext_buf) + RFA_ALIGNMENT_FUDGE); 1750 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_START); 1751 1752 /* 1753 * Set current media. 1754 */ 1755 if (sc->miibus != NULL) 1756 mii_mediachg(device_get_softc(sc->miibus)); 1757 1758 ifp->if_flags |= IFF_RUNNING; 1759 ifp->if_flags &= ~IFF_OACTIVE; 1760 1761 /* 1762 * Enable interrupts. 1763 */ 1764 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, 0); 1765 splx(s); 1766 1767 /* 1768 * Start stats updater. 1769 */ 1770 sc->stat_ch = timeout(fxp_tick, sc, hz); 1771 } 1772 1773 static int 1774 fxp_serial_ifmedia_upd(struct ifnet *ifp) 1775 { 1776 1777 return (0); 1778 } 1779 1780 static void 1781 fxp_serial_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 1782 { 1783 1784 ifmr->ifm_active = IFM_ETHER|IFM_MANUAL; 1785 } 1786 1787 /* 1788 * Change media according to request. 1789 */ 1790 static int 1791 fxp_ifmedia_upd(struct ifnet *ifp) 1792 { 1793 struct fxp_softc *sc = ifp->if_softc; 1794 struct mii_data *mii; 1795 1796 mii = device_get_softc(sc->miibus); 1797 mii_mediachg(mii); 1798 return (0); 1799 } 1800 1801 /* 1802 * Notify the world which media we're using. 1803 */ 1804 static void 1805 fxp_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 1806 { 1807 struct fxp_softc *sc = ifp->if_softc; 1808 struct mii_data *mii; 1809 1810 mii = device_get_softc(sc->miibus); 1811 mii_pollstat(mii); 1812 ifmr->ifm_active = mii->mii_media_active; 1813 ifmr->ifm_status = mii->mii_media_status; 1814 1815 if (ifmr->ifm_status & IFM_10_T && sc->flags & FXP_FLAG_CU_RESUME_BUG) 1816 sc->cu_resume_bug = 1; 1817 else 1818 sc->cu_resume_bug = 0; 1819 } 1820 1821 /* 1822 * Add a buffer to the end of the RFA buffer list. 1823 * Return 0 if successful, 1 for failure. A failure results in 1824 * adding the 'oldm' (if non-NULL) on to the end of the list - 1825 * tossing out its old contents and recycling it. 1826 * The RFA struct is stuck at the beginning of mbuf cluster and the 1827 * data pointer is fixed up to point just past it. 1828 */ 1829 static int 1830 fxp_add_rfabuf(struct fxp_softc *sc, struct mbuf *oldm) 1831 { 1832 u_int32_t v; 1833 struct mbuf *m; 1834 struct fxp_rfa *rfa, *p_rfa; 1835 1836 MGETHDR(m, M_DONTWAIT, MT_DATA); 1837 if (m != NULL) { 1838 MCLGET(m, M_DONTWAIT); 1839 if ((m->m_flags & M_EXT) == 0) { 1840 m_freem(m); 1841 if (oldm == NULL) 1842 return 1; 1843 m = oldm; 1844 m->m_data = m->m_ext.ext_buf; 1845 } 1846 } else { 1847 if (oldm == NULL) 1848 return 1; 1849 m = oldm; 1850 m->m_data = m->m_ext.ext_buf; 1851 } 1852 1853 /* 1854 * Move the data pointer up so that the incoming data packet 1855 * will be 32-bit aligned. 1856 */ 1857 m->m_data += RFA_ALIGNMENT_FUDGE; 1858 1859 /* 1860 * Get a pointer to the base of the mbuf cluster and move 1861 * data start past it. 1862 */ 1863 rfa = mtod(m, struct fxp_rfa *); 1864 m->m_data += sizeof(struct fxp_rfa); 1865 rfa->size = (u_int16_t)(MCLBYTES - sizeof(struct fxp_rfa) - RFA_ALIGNMENT_FUDGE); 1866 1867 /* 1868 * Initialize the rest of the RFA. Note that since the RFA 1869 * is misaligned, we cannot store values directly. Instead, 1870 * we use an optimized, inline copy. 1871 */ 1872 1873 rfa->rfa_status = 0; 1874 rfa->rfa_control = FXP_RFA_CONTROL_EL; 1875 rfa->actual_size = 0; 1876 1877 v = -1; 1878 fxp_lwcopy(&v, (volatile u_int32_t *) rfa->link_addr); 1879 fxp_lwcopy(&v, (volatile u_int32_t *) rfa->rbd_addr); 1880 1881 /* 1882 * If there are other buffers already on the list, attach this 1883 * one to the end by fixing up the tail to point to this one. 1884 */ 1885 if (sc->rfa_headm != NULL) { 1886 p_rfa = (struct fxp_rfa *) (sc->rfa_tailm->m_ext.ext_buf + 1887 RFA_ALIGNMENT_FUDGE); 1888 sc->rfa_tailm->m_next = m; 1889 v = vtophys(rfa); 1890 fxp_lwcopy(&v, (volatile u_int32_t *) p_rfa->link_addr); 1891 p_rfa->rfa_control = 0; 1892 } else { 1893 sc->rfa_headm = m; 1894 } 1895 sc->rfa_tailm = m; 1896 1897 return (m == oldm); 1898 } 1899 1900 static volatile int 1901 fxp_miibus_readreg(device_t dev, int phy, int reg) 1902 { 1903 struct fxp_softc *sc = device_get_softc(dev); 1904 int count = 10000; 1905 int value; 1906 1907 CSR_WRITE_4(sc, FXP_CSR_MDICONTROL, 1908 (FXP_MDI_READ << 26) | (reg << 16) | (phy << 21)); 1909 1910 while (((value = CSR_READ_4(sc, FXP_CSR_MDICONTROL)) & 0x10000000) == 0 1911 && count--) 1912 DELAY(10); 1913 1914 if (count <= 0) 1915 device_printf(dev, "fxp_miibus_readreg: timed out\n"); 1916 1917 return (value & 0xffff); 1918 } 1919 1920 static void 1921 fxp_miibus_writereg(device_t dev, int phy, int reg, int value) 1922 { 1923 struct fxp_softc *sc = device_get_softc(dev); 1924 int count = 10000; 1925 1926 CSR_WRITE_4(sc, FXP_CSR_MDICONTROL, 1927 (FXP_MDI_WRITE << 26) | (reg << 16) | (phy << 21) | 1928 (value & 0xffff)); 1929 1930 while ((CSR_READ_4(sc, FXP_CSR_MDICONTROL) & 0x10000000) == 0 && 1931 count--) 1932 DELAY(10); 1933 1934 if (count <= 0) 1935 device_printf(dev, "fxp_miibus_writereg: timed out\n"); 1936 } 1937 1938 static int 1939 fxp_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 1940 { 1941 struct fxp_softc *sc = ifp->if_softc; 1942 struct ifreq *ifr = (struct ifreq *)data; 1943 struct mii_data *mii; 1944 int s, error = 0; 1945 1946 s = splimp(); 1947 1948 switch (command) { 1949 case SIOCSIFADDR: 1950 case SIOCGIFADDR: 1951 case SIOCSIFMTU: 1952 error = ether_ioctl(ifp, command, data); 1953 break; 1954 1955 case SIOCSIFFLAGS: 1956 if (ifp->if_flags & IFF_ALLMULTI) 1957 sc->flags |= FXP_FLAG_ALL_MCAST; 1958 else 1959 sc->flags &= ~FXP_FLAG_ALL_MCAST; 1960 1961 /* 1962 * If interface is marked up and not running, then start it. 1963 * If it is marked down and running, stop it. 1964 * XXX If it's up then re-initialize it. This is so flags 1965 * such as IFF_PROMISC are handled. 1966 */ 1967 if (ifp->if_flags & IFF_UP) { 1968 fxp_init(sc); 1969 } else { 1970 if (ifp->if_flags & IFF_RUNNING) 1971 fxp_stop(sc); 1972 } 1973 break; 1974 1975 case SIOCADDMULTI: 1976 case SIOCDELMULTI: 1977 if (ifp->if_flags & IFF_ALLMULTI) 1978 sc->flags |= FXP_FLAG_ALL_MCAST; 1979 else 1980 sc->flags &= ~FXP_FLAG_ALL_MCAST; 1981 /* 1982 * Multicast list has changed; set the hardware filter 1983 * accordingly. 1984 */ 1985 if ((sc->flags & FXP_FLAG_ALL_MCAST) == 0) 1986 fxp_mc_setup(sc); 1987 /* 1988 * fxp_mc_setup() can set FXP_FLAG_ALL_MCAST, so check it 1989 * again rather than else {}. 1990 */ 1991 if (sc->flags & FXP_FLAG_ALL_MCAST) 1992 fxp_init(sc); 1993 error = 0; 1994 break; 1995 1996 case SIOCSIFMEDIA: 1997 case SIOCGIFMEDIA: 1998 if (sc->miibus != NULL) { 1999 mii = device_get_softc(sc->miibus); 2000 error = ifmedia_ioctl(ifp, ifr, 2001 &mii->mii_media, command); 2002 } else { 2003 error = ifmedia_ioctl(ifp, ifr, &sc->sc_media, command); 2004 } 2005 break; 2006 2007 default: 2008 error = EINVAL; 2009 } 2010 splx(s); 2011 return (error); 2012 } 2013 2014 /* 2015 * Fill in the multicast address list and return number of entries. 2016 */ 2017 static int 2018 fxp_mc_addrs(struct fxp_softc *sc) 2019 { 2020 struct fxp_cb_mcs *mcsp = sc->mcsp; 2021 struct ifnet *ifp = &sc->sc_if; 2022 struct ifmultiaddr *ifma; 2023 int nmcasts; 2024 2025 nmcasts = 0; 2026 if ((sc->flags & FXP_FLAG_ALL_MCAST) == 0) { 2027 #if __FreeBSD_version < 500000 2028 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 2029 #else 2030 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 2031 #endif 2032 if (ifma->ifma_addr->sa_family != AF_LINK) 2033 continue; 2034 if (nmcasts >= MAXMCADDR) { 2035 sc->flags |= FXP_FLAG_ALL_MCAST; 2036 nmcasts = 0; 2037 break; 2038 } 2039 bcopy(LLADDR((struct sockaddr_dl *)ifma->ifma_addr), 2040 (void *)(uintptr_t)(volatile void *) 2041 &sc->mcsp->mc_addr[nmcasts][0], 6); 2042 nmcasts++; 2043 } 2044 } 2045 mcsp->mc_cnt = nmcasts * 6; 2046 return (nmcasts); 2047 } 2048 2049 /* 2050 * Program the multicast filter. 2051 * 2052 * We have an artificial restriction that the multicast setup command 2053 * must be the first command in the chain, so we take steps to ensure 2054 * this. By requiring this, it allows us to keep up the performance of 2055 * the pre-initialized command ring (esp. link pointers) by not actually 2056 * inserting the mcsetup command in the ring - i.e. its link pointer 2057 * points to the TxCB ring, but the mcsetup descriptor itself is not part 2058 * of it. We then can do 'CU_START' on the mcsetup descriptor and have it 2059 * lead into the regular TxCB ring when it completes. 2060 * 2061 * This function must be called at splimp. 2062 */ 2063 static void 2064 fxp_mc_setup(struct fxp_softc *sc) 2065 { 2066 struct fxp_cb_mcs *mcsp = sc->mcsp; 2067 struct ifnet *ifp = &sc->sc_if; 2068 int count; 2069 2070 /* 2071 * If there are queued commands, we must wait until they are all 2072 * completed. If we are already waiting, then add a NOP command 2073 * with interrupt option so that we're notified when all commands 2074 * have been completed - fxp_start() ensures that no additional 2075 * TX commands will be added when need_mcsetup is true. 2076 */ 2077 if (sc->tx_queued) { 2078 struct fxp_cb_tx *txp; 2079 2080 /* 2081 * need_mcsetup will be true if we are already waiting for the 2082 * NOP command to be completed (see below). In this case, bail. 2083 */ 2084 if (sc->need_mcsetup) 2085 return; 2086 sc->need_mcsetup = 1; 2087 2088 /* 2089 * Add a NOP command with interrupt so that we are notified 2090 * when all TX commands have been processed. 2091 */ 2092 txp = sc->cbl_last->next; 2093 txp->mb_head = NULL; 2094 txp->cb_status = 0; 2095 txp->cb_command = FXP_CB_COMMAND_NOP | 2096 FXP_CB_COMMAND_S | FXP_CB_COMMAND_I; 2097 /* 2098 * Advance the end of list forward. 2099 */ 2100 sc->cbl_last->cb_command &= ~FXP_CB_COMMAND_S; 2101 sc->cbl_last = txp; 2102 sc->tx_queued++; 2103 /* 2104 * Issue a resume in case the CU has just suspended. 2105 */ 2106 fxp_scb_wait(sc); 2107 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_RESUME); 2108 /* 2109 * Set a 5 second timer just in case we don't hear from the 2110 * card again. 2111 */ 2112 ifp->if_timer = 5; 2113 2114 return; 2115 } 2116 sc->need_mcsetup = 0; 2117 2118 /* 2119 * Initialize multicast setup descriptor. 2120 */ 2121 mcsp->next = sc->cbl_base; 2122 mcsp->mb_head = NULL; 2123 mcsp->cb_status = 0; 2124 mcsp->cb_command = FXP_CB_COMMAND_MCAS | 2125 FXP_CB_COMMAND_S | FXP_CB_COMMAND_I; 2126 mcsp->link_addr = vtophys(&sc->cbl_base->cb_status); 2127 (void) fxp_mc_addrs(sc); 2128 sc->cbl_first = sc->cbl_last = (struct fxp_cb_tx *) mcsp; 2129 sc->tx_queued = 1; 2130 2131 /* 2132 * Wait until command unit is not active. This should never 2133 * be the case when nothing is queued, but make sure anyway. 2134 */ 2135 count = 100; 2136 while ((CSR_READ_1(sc, FXP_CSR_SCB_RUSCUS) >> 6) == 2137 FXP_SCB_CUS_ACTIVE && --count) 2138 DELAY(10); 2139 if (count == 0) { 2140 device_printf(sc->dev, "command queue timeout\n"); 2141 return; 2142 } 2143 2144 /* 2145 * Start the multicast setup command. 2146 */ 2147 fxp_scb_wait(sc); 2148 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, vtophys(&mcsp->cb_status)); 2149 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2150 2151 ifp->if_timer = 2; 2152 return; 2153 } 2154 2155 static u_int32_t fxp_ucode_d101a[] = D101_A_RCVBUNDLE_UCODE; 2156 static u_int32_t fxp_ucode_d101b0[] = D101_B0_RCVBUNDLE_UCODE; 2157 static u_int32_t fxp_ucode_d101ma[] = D101M_B_RCVBUNDLE_UCODE; 2158 static u_int32_t fxp_ucode_d101s[] = D101S_RCVBUNDLE_UCODE; 2159 static u_int32_t fxp_ucode_d102[] = D102_B_RCVBUNDLE_UCODE; 2160 static u_int32_t fxp_ucode_d102c[] = D102_C_RCVBUNDLE_UCODE; 2161 2162 #define UCODE(x) x, sizeof(x) 2163 2164 struct ucode { 2165 u_int32_t revision; 2166 u_int32_t *ucode; 2167 int length; 2168 u_short int_delay_offset; 2169 u_short bundle_max_offset; 2170 } ucode_table[] = { 2171 { FXP_REV_82558_A4, UCODE(fxp_ucode_d101a), D101_CPUSAVER_DWORD, 0 }, 2172 { FXP_REV_82558_B0, UCODE(fxp_ucode_d101b0), D101_CPUSAVER_DWORD, 0 }, 2173 { FXP_REV_82559_A0, UCODE(fxp_ucode_d101ma), 2174 D101M_CPUSAVER_DWORD, D101M_CPUSAVER_BUNDLE_MAX_DWORD }, 2175 { FXP_REV_82559S_A, UCODE(fxp_ucode_d101s), 2176 D101S_CPUSAVER_DWORD, D101S_CPUSAVER_BUNDLE_MAX_DWORD }, 2177 { FXP_REV_82550, UCODE(fxp_ucode_d102), 2178 D102_B_CPUSAVER_DWORD, D102_B_CPUSAVER_BUNDLE_MAX_DWORD }, 2179 { FXP_REV_82550_C, UCODE(fxp_ucode_d102c), 2180 D102_C_CPUSAVER_DWORD, D102_C_CPUSAVER_BUNDLE_MAX_DWORD }, 2181 { 0, NULL, 0, 0, 0 } 2182 }; 2183 2184 static void 2185 fxp_load_ucode(struct fxp_softc *sc) 2186 { 2187 struct ucode *uc; 2188 struct fxp_cb_ucode *cbp; 2189 2190 for (uc = ucode_table; uc->ucode != NULL; uc++) 2191 if (sc->revision == uc->revision) 2192 break; 2193 if (uc->ucode == NULL) 2194 return; 2195 cbp = (struct fxp_cb_ucode *)sc->cbl_base; 2196 cbp->cb_status = 0; 2197 cbp->cb_command = FXP_CB_COMMAND_UCODE | FXP_CB_COMMAND_EL; 2198 cbp->link_addr = -1; /* (no) next command */ 2199 memcpy(cbp->ucode, uc->ucode, uc->length); 2200 if (uc->int_delay_offset) 2201 *(u_short *)&cbp->ucode[uc->int_delay_offset] = 2202 sc->tunable_int_delay + sc->tunable_int_delay / 2; 2203 if (uc->bundle_max_offset) 2204 *(u_short *)&cbp->ucode[uc->bundle_max_offset] = 2205 sc->tunable_bundle_max; 2206 /* 2207 * Download the ucode to the chip. 2208 */ 2209 fxp_scb_wait(sc); 2210 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, vtophys(&cbp->cb_status)); 2211 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2212 /* ...and wait for it to complete. */ 2213 fxp_dma_wait(&cbp->cb_status, sc); 2214 device_printf(sc->dev, 2215 "Microcode loaded, int_delay: %d usec bundle_max: %d\n", 2216 sc->tunable_int_delay, 2217 uc->bundle_max_offset == 0 ? 0 : sc->tunable_bundle_max); 2218 sc->flags |= FXP_FLAG_UCODE; 2219 } 2220 2221 static int 2222 sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high) 2223 { 2224 int error, value; 2225 2226 value = *(int *)arg1; 2227 error = sysctl_handle_int(oidp, &value, 0, req); 2228 if (error || !req->newptr) 2229 return (error); 2230 if (value < low || value > high) 2231 return (EINVAL); 2232 *(int *)arg1 = value; 2233 return (0); 2234 } 2235 2236 /* 2237 * Interrupt delay is expressed in microseconds, a multiplier is used 2238 * to convert this to the appropriate clock ticks before using. 2239 */ 2240 static int 2241 sysctl_hw_fxp_int_delay(SYSCTL_HANDLER_ARGS) 2242 { 2243 return (sysctl_int_range(oidp, arg1, arg2, req, 300, 3000)); 2244 } 2245 2246 static int 2247 sysctl_hw_fxp_bundle_max(SYSCTL_HANDLER_ARGS) 2248 { 2249 return (sysctl_int_range(oidp, arg1, arg2, req, 1, 0xffff)); 2250 } 2251