1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 1995, David Greenman 5 * Copyright (c) 2001 Jonathan Lemon <jlemon@freebsd.org> 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice unmodified, this list of conditions, and the following 13 * disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 * 30 */ 31 32 #include <sys/cdefs.h> 33 /* 34 * Intel EtherExpress Pro/100B PCI Fast Ethernet driver 35 */ 36 37 #ifdef HAVE_KERNEL_OPTION_HEADERS 38 #include "opt_device_polling.h" 39 #endif 40 41 #include <sys/param.h> 42 #include <sys/systm.h> 43 #include <sys/bus.h> 44 #include <sys/endian.h> 45 #include <sys/kernel.h> 46 #include <sys/mbuf.h> 47 #include <sys/lock.h> 48 #include <sys/malloc.h> 49 #include <sys/module.h> 50 #include <sys/mutex.h> 51 #include <sys/rman.h> 52 #include <sys/socket.h> 53 #include <sys/sockio.h> 54 #include <sys/sysctl.h> 55 56 #include <net/bpf.h> 57 #include <net/ethernet.h> 58 #include <net/if.h> 59 #include <net/if_var.h> 60 #include <net/if_arp.h> 61 #include <net/if_dl.h> 62 #include <net/if_media.h> 63 #include <net/if_types.h> 64 #include <net/if_vlan_var.h> 65 66 #include <netinet/in.h> 67 #include <netinet/in_systm.h> 68 #include <netinet/ip.h> 69 #include <netinet/tcp.h> 70 #include <netinet/udp.h> 71 72 #include <machine/bus.h> 73 #include <machine/in_cksum.h> 74 #include <machine/resource.h> 75 76 #include <dev/pci/pcivar.h> 77 #include <dev/pci/pcireg.h> /* for PCIM_CMD_xxx */ 78 79 #include <dev/mii/mii.h> 80 #include <dev/mii/miivar.h> 81 82 #include <dev/fxp/if_fxpreg.h> 83 #include <dev/fxp/if_fxpvar.h> 84 #include <dev/fxp/rcvbundl.h> 85 86 MODULE_DEPEND(fxp, pci, 1, 1, 1); 87 MODULE_DEPEND(fxp, ether, 1, 1, 1); 88 MODULE_DEPEND(fxp, miibus, 1, 1, 1); 89 #include "miibus_if.h" 90 91 /* 92 * NOTE! On !x86 we typically have an alignment constraint. The 93 * card DMAs the packet immediately following the RFA. However, 94 * the first thing in the packet is a 14-byte Ethernet header. 95 * This means that the packet is misaligned. To compensate, 96 * we actually offset the RFA 2 bytes into the cluster. This 97 * alignes the packet after the Ethernet header at a 32-bit 98 * boundary. HOWEVER! This means that the RFA is misaligned! 99 */ 100 #define RFA_ALIGNMENT_FUDGE 2 101 102 /* 103 * Set initial transmit threshold at 64 (512 bytes). This is 104 * increased by 64 (512 bytes) at a time, to maximum of 192 105 * (1536 bytes), if an underrun occurs. 106 */ 107 static int tx_threshold = 64; 108 109 /* 110 * The configuration byte map has several undefined fields which 111 * must be one or must be zero. Set up a template for these bits. 112 * The actual configuration is performed in fxp_init_body. 113 * 114 * See struct fxp_cb_config for the bit definitions. 115 */ 116 static const u_char fxp_cb_config_template[] = { 117 0x0, 0x0, /* cb_status */ 118 0x0, 0x0, /* cb_command */ 119 0x0, 0x0, 0x0, 0x0, /* link_addr */ 120 0x0, /* 0 */ 121 0x0, /* 1 */ 122 0x0, /* 2 */ 123 0x0, /* 3 */ 124 0x0, /* 4 */ 125 0x0, /* 5 */ 126 0x32, /* 6 */ 127 0x0, /* 7 */ 128 0x0, /* 8 */ 129 0x0, /* 9 */ 130 0x6, /* 10 */ 131 0x0, /* 11 */ 132 0x0, /* 12 */ 133 0x0, /* 13 */ 134 0xf2, /* 14 */ 135 0x48, /* 15 */ 136 0x0, /* 16 */ 137 0x40, /* 17 */ 138 0xf0, /* 18 */ 139 0x0, /* 19 */ 140 0x3f, /* 20 */ 141 0x5, /* 21 */ 142 0x0, /* 22 */ 143 0x0, /* 23 */ 144 0x0, /* 24 */ 145 0x0, /* 25 */ 146 0x0, /* 26 */ 147 0x0, /* 27 */ 148 0x0, /* 28 */ 149 0x0, /* 29 */ 150 0x0, /* 30 */ 151 0x0 /* 31 */ 152 }; 153 154 /* 155 * Claim various Intel PCI device identifiers for this driver. The 156 * sub-vendor and sub-device field are extensively used to identify 157 * particular variants, but we don't currently differentiate between 158 * them. 159 */ 160 static const struct fxp_ident fxp_ident_table[] = { 161 { 0x8086, 0x1029, -1, 0, "Intel 82559 PCI/CardBus Pro/100" }, 162 { 0x8086, 0x1030, -1, 0, "Intel 82559 Pro/100 Ethernet" }, 163 { 0x8086, 0x1031, -1, 3, "Intel 82801CAM (ICH3) Pro/100 VE Ethernet" }, 164 { 0x8086, 0x1032, -1, 3, "Intel 82801CAM (ICH3) Pro/100 VE Ethernet" }, 165 { 0x8086, 0x1033, -1, 3, "Intel 82801CAM (ICH3) Pro/100 VM Ethernet" }, 166 { 0x8086, 0x1034, -1, 3, "Intel 82801CAM (ICH3) Pro/100 VM Ethernet" }, 167 { 0x8086, 0x1035, -1, 3, "Intel 82801CAM (ICH3) Pro/100 Ethernet" }, 168 { 0x8086, 0x1036, -1, 3, "Intel 82801CAM (ICH3) Pro/100 Ethernet" }, 169 { 0x8086, 0x1037, -1, 3, "Intel 82801CAM (ICH3) Pro/100 Ethernet" }, 170 { 0x8086, 0x1038, -1, 3, "Intel 82801CAM (ICH3) Pro/100 VM Ethernet" }, 171 { 0x8086, 0x1039, -1, 4, "Intel 82801DB (ICH4) Pro/100 VE Ethernet" }, 172 { 0x8086, 0x103A, -1, 4, "Intel 82801DB (ICH4) Pro/100 Ethernet" }, 173 { 0x8086, 0x103B, -1, 4, "Intel 82801DB (ICH4) Pro/100 VM Ethernet" }, 174 { 0x8086, 0x103C, -1, 4, "Intel 82801DB (ICH4) Pro/100 Ethernet" }, 175 { 0x8086, 0x103D, -1, 4, "Intel 82801DB (ICH4) Pro/100 VE Ethernet" }, 176 { 0x8086, 0x103E, -1, 4, "Intel 82801DB (ICH4) Pro/100 VM Ethernet" }, 177 { 0x8086, 0x1050, -1, 5, "Intel 82801BA (D865) Pro/100 VE Ethernet" }, 178 { 0x8086, 0x1051, -1, 5, "Intel 82562ET (ICH5/ICH5R) Pro/100 VE Ethernet" }, 179 { 0x8086, 0x1059, -1, 0, "Intel 82551QM Pro/100 M Mobile Connection" }, 180 { 0x8086, 0x1064, -1, 6, "Intel 82562EZ (ICH6)" }, 181 { 0x8086, 0x1065, -1, 6, "Intel 82562ET/EZ/GT/GZ PRO/100 VE Ethernet" }, 182 { 0x8086, 0x1068, -1, 6, "Intel 82801FBM (ICH6-M) Pro/100 VE Ethernet" }, 183 { 0x8086, 0x1069, -1, 6, "Intel 82562EM/EX/GX Pro/100 Ethernet" }, 184 { 0x8086, 0x1091, -1, 7, "Intel 82562GX Pro/100 Ethernet" }, 185 { 0x8086, 0x1092, -1, 7, "Intel Pro/100 VE Network Connection" }, 186 { 0x8086, 0x1093, -1, 7, "Intel Pro/100 VM Network Connection" }, 187 { 0x8086, 0x1094, -1, 7, "Intel Pro/100 946GZ (ICH7) Network Connection" }, 188 { 0x8086, 0x1209, -1, 0, "Intel 82559ER Embedded 10/100 Ethernet" }, 189 { 0x8086, 0x1229, 0x01, 0, "Intel 82557 Pro/100 Ethernet" }, 190 { 0x8086, 0x1229, 0x02, 0, "Intel 82557 Pro/100 Ethernet" }, 191 { 0x8086, 0x1229, 0x03, 0, "Intel 82557 Pro/100 Ethernet" }, 192 { 0x8086, 0x1229, 0x04, 0, "Intel 82558 Pro/100 Ethernet" }, 193 { 0x8086, 0x1229, 0x05, 0, "Intel 82558 Pro/100 Ethernet" }, 194 { 0x8086, 0x1229, 0x06, 0, "Intel 82559 Pro/100 Ethernet" }, 195 { 0x8086, 0x1229, 0x07, 0, "Intel 82559 Pro/100 Ethernet" }, 196 { 0x8086, 0x1229, 0x08, 0, "Intel 82559 Pro/100 Ethernet" }, 197 { 0x8086, 0x1229, 0x09, 0, "Intel 82559ER Pro/100 Ethernet" }, 198 { 0x8086, 0x1229, 0x0c, 0, "Intel 82550 Pro/100 Ethernet" }, 199 { 0x8086, 0x1229, 0x0d, 0, "Intel 82550C Pro/100 Ethernet" }, 200 { 0x8086, 0x1229, 0x0e, 0, "Intel 82550 Pro/100 Ethernet" }, 201 { 0x8086, 0x1229, 0x0f, 0, "Intel 82551 Pro/100 Ethernet" }, 202 { 0x8086, 0x1229, 0x10, 0, "Intel 82551 Pro/100 Ethernet" }, 203 { 0x8086, 0x1229, -1, 0, "Intel 82557/8/9 Pro/100 Ethernet" }, 204 { 0x8086, 0x2449, -1, 2, "Intel 82801BA/CAM (ICH2/3) Pro/100 Ethernet" }, 205 { 0x8086, 0x27dc, -1, 7, "Intel 82801GB (ICH7) 10/100 Ethernet" }, 206 { 0, 0, -1, 0, NULL }, 207 }; 208 209 #ifdef FXP_IP_CSUM_WAR 210 #define FXP_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 211 #else 212 #define FXP_CSUM_FEATURES (CSUM_TCP | CSUM_UDP) 213 #endif 214 215 static int fxp_probe(device_t dev); 216 static int fxp_attach(device_t dev); 217 static int fxp_detach(device_t dev); 218 static int fxp_shutdown(device_t dev); 219 static int fxp_suspend(device_t dev); 220 static int fxp_resume(device_t dev); 221 222 static const struct fxp_ident *fxp_find_ident(device_t dev); 223 static void fxp_intr(void *xsc); 224 static void fxp_rxcsum(struct fxp_softc *sc, if_t ifp, 225 struct mbuf *m, uint16_t status, int pos); 226 static int fxp_intr_body(struct fxp_softc *sc, if_t ifp, 227 uint8_t statack, int count); 228 static void fxp_init(void *xsc); 229 static void fxp_init_body(struct fxp_softc *sc, int); 230 static void fxp_tick(void *xsc); 231 static void fxp_start(if_t ifp); 232 static void fxp_start_body(if_t ifp); 233 static int fxp_encap(struct fxp_softc *sc, struct mbuf **m_head); 234 static void fxp_txeof(struct fxp_softc *sc); 235 static void fxp_stop(struct fxp_softc *sc); 236 static void fxp_release(struct fxp_softc *sc); 237 static int fxp_ioctl(if_t ifp, u_long command, 238 caddr_t data); 239 static void fxp_watchdog(struct fxp_softc *sc); 240 static void fxp_add_rfabuf(struct fxp_softc *sc, 241 struct fxp_rx *rxp); 242 static void fxp_discard_rfabuf(struct fxp_softc *sc, 243 struct fxp_rx *rxp); 244 static int fxp_new_rfabuf(struct fxp_softc *sc, 245 struct fxp_rx *rxp); 246 static void fxp_mc_addrs(struct fxp_softc *sc); 247 static void fxp_mc_setup(struct fxp_softc *sc); 248 static uint16_t fxp_eeprom_getword(struct fxp_softc *sc, int offset, 249 int autosize); 250 static void fxp_eeprom_putword(struct fxp_softc *sc, int offset, 251 uint16_t data); 252 static void fxp_autosize_eeprom(struct fxp_softc *sc); 253 static void fxp_load_eeprom(struct fxp_softc *sc); 254 static void fxp_read_eeprom(struct fxp_softc *sc, u_short *data, 255 int offset, int words); 256 static void fxp_write_eeprom(struct fxp_softc *sc, u_short *data, 257 int offset, int words); 258 static int fxp_ifmedia_upd(if_t ifp); 259 static void fxp_ifmedia_sts(if_t ifp, 260 struct ifmediareq *ifmr); 261 static int fxp_serial_ifmedia_upd(if_t ifp); 262 static void fxp_serial_ifmedia_sts(if_t ifp, 263 struct ifmediareq *ifmr); 264 static int fxp_miibus_readreg(device_t dev, int phy, int reg); 265 static int fxp_miibus_writereg(device_t dev, int phy, int reg, 266 int value); 267 static void fxp_miibus_statchg(device_t dev); 268 static void fxp_load_ucode(struct fxp_softc *sc); 269 static void fxp_update_stats(struct fxp_softc *sc); 270 static void fxp_sysctl_node(struct fxp_softc *sc); 271 static int sysctl_int_range(SYSCTL_HANDLER_ARGS, 272 int low, int high); 273 static int sysctl_hw_fxp_bundle_max(SYSCTL_HANDLER_ARGS); 274 static int sysctl_hw_fxp_int_delay(SYSCTL_HANDLER_ARGS); 275 static void fxp_scb_wait(struct fxp_softc *sc); 276 static void fxp_scb_cmd(struct fxp_softc *sc, int cmd); 277 static void fxp_dma_wait(struct fxp_softc *sc, 278 volatile uint16_t *status, bus_dma_tag_t dmat, 279 bus_dmamap_t map); 280 281 static device_method_t fxp_methods[] = { 282 /* Device interface */ 283 DEVMETHOD(device_probe, fxp_probe), 284 DEVMETHOD(device_attach, fxp_attach), 285 DEVMETHOD(device_detach, fxp_detach), 286 DEVMETHOD(device_shutdown, fxp_shutdown), 287 DEVMETHOD(device_suspend, fxp_suspend), 288 DEVMETHOD(device_resume, fxp_resume), 289 290 /* MII interface */ 291 DEVMETHOD(miibus_readreg, fxp_miibus_readreg), 292 DEVMETHOD(miibus_writereg, fxp_miibus_writereg), 293 DEVMETHOD(miibus_statchg, fxp_miibus_statchg), 294 295 DEVMETHOD_END 296 }; 297 298 static driver_t fxp_driver = { 299 "fxp", 300 fxp_methods, 301 sizeof(struct fxp_softc), 302 }; 303 304 DRIVER_MODULE_ORDERED(fxp, pci, fxp_driver, NULL, NULL, SI_ORDER_ANY); 305 MODULE_PNP_INFO("U16:vendor;U16:device", pci, fxp, fxp_ident_table, 306 nitems(fxp_ident_table) - 1); 307 DRIVER_MODULE(miibus, fxp, miibus_driver, NULL, NULL); 308 309 static struct resource_spec fxp_res_spec_mem[] = { 310 { SYS_RES_MEMORY, FXP_PCI_MMBA, RF_ACTIVE }, 311 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE }, 312 { -1, 0 } 313 }; 314 315 static struct resource_spec fxp_res_spec_io[] = { 316 { SYS_RES_IOPORT, FXP_PCI_IOBA, RF_ACTIVE }, 317 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE }, 318 { -1, 0 } 319 }; 320 321 /* 322 * Wait for the previous command to be accepted (but not necessarily 323 * completed). 324 */ 325 static void 326 fxp_scb_wait(struct fxp_softc *sc) 327 { 328 union { 329 uint16_t w; 330 uint8_t b[2]; 331 } flowctl; 332 int i = 10000; 333 334 while (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) && --i) 335 DELAY(2); 336 if (i == 0) { 337 flowctl.b[0] = CSR_READ_1(sc, FXP_CSR_FC_THRESH); 338 flowctl.b[1] = CSR_READ_1(sc, FXP_CSR_FC_STATUS); 339 device_printf(sc->dev, "SCB timeout: 0x%x 0x%x 0x%x 0x%x\n", 340 CSR_READ_1(sc, FXP_CSR_SCB_COMMAND), 341 CSR_READ_1(sc, FXP_CSR_SCB_STATACK), 342 CSR_READ_1(sc, FXP_CSR_SCB_RUSCUS), flowctl.w); 343 } 344 } 345 346 static void 347 fxp_scb_cmd(struct fxp_softc *sc, int cmd) 348 { 349 350 if (cmd == FXP_SCB_COMMAND_CU_RESUME && sc->cu_resume_bug) { 351 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_CB_COMMAND_NOP); 352 fxp_scb_wait(sc); 353 } 354 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, cmd); 355 } 356 357 static void 358 fxp_dma_wait(struct fxp_softc *sc, volatile uint16_t *status, 359 bus_dma_tag_t dmat, bus_dmamap_t map) 360 { 361 int i; 362 363 for (i = 10000; i > 0; i--) { 364 DELAY(2); 365 bus_dmamap_sync(dmat, map, 366 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 367 if ((le16toh(*status) & FXP_CB_STATUS_C) != 0) 368 break; 369 } 370 if (i == 0) 371 device_printf(sc->dev, "DMA timeout\n"); 372 } 373 374 static const struct fxp_ident * 375 fxp_find_ident(device_t dev) 376 { 377 uint16_t vendor; 378 uint16_t device; 379 uint8_t revid; 380 const struct fxp_ident *ident; 381 382 vendor = pci_get_vendor(dev); 383 device = pci_get_device(dev); 384 revid = pci_get_revid(dev); 385 for (ident = fxp_ident_table; ident->name != NULL; ident++) { 386 if (ident->vendor == vendor && ident->device == device && 387 (ident->revid == revid || ident->revid == -1)) { 388 return (ident); 389 } 390 } 391 return (NULL); 392 } 393 394 /* 395 * Return identification string if this device is ours. 396 */ 397 static int 398 fxp_probe(device_t dev) 399 { 400 const struct fxp_ident *ident; 401 402 ident = fxp_find_ident(dev); 403 if (ident != NULL) { 404 device_set_desc(dev, ident->name); 405 return (BUS_PROBE_DEFAULT); 406 } 407 return (ENXIO); 408 } 409 410 static void 411 fxp_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error) 412 { 413 uint32_t *addr; 414 415 if (error) 416 return; 417 418 KASSERT(nseg == 1, ("too many DMA segments, %d should be 1", nseg)); 419 addr = arg; 420 *addr = segs->ds_addr; 421 } 422 423 static int 424 fxp_attach(device_t dev) 425 { 426 struct fxp_softc *sc; 427 struct fxp_cb_tx *tcbp; 428 struct fxp_tx *txp; 429 struct fxp_rx *rxp; 430 if_t ifp; 431 uint32_t val; 432 uint16_t data; 433 u_char eaddr[ETHER_ADDR_LEN]; 434 int error, flags, i, pmc, prefer_iomap; 435 436 error = 0; 437 sc = device_get_softc(dev); 438 sc->dev = dev; 439 mtx_init(&sc->sc_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 440 MTX_DEF); 441 callout_init_mtx(&sc->stat_ch, &sc->sc_mtx, 0); 442 ifmedia_init(&sc->sc_media, 0, fxp_serial_ifmedia_upd, 443 fxp_serial_ifmedia_sts); 444 445 ifp = sc->ifp = if_gethandle(IFT_ETHER); 446 447 /* 448 * Enable bus mastering. 449 */ 450 pci_enable_busmaster(dev); 451 452 /* 453 * Figure out which we should try first - memory mapping or i/o mapping? 454 * We default to memory mapping. Then we accept an override from the 455 * command line. Then we check to see which one is enabled. 456 */ 457 prefer_iomap = 0; 458 resource_int_value(device_get_name(dev), device_get_unit(dev), 459 "prefer_iomap", &prefer_iomap); 460 if (prefer_iomap) 461 sc->fxp_spec = fxp_res_spec_io; 462 else 463 sc->fxp_spec = fxp_res_spec_mem; 464 465 error = bus_alloc_resources(dev, sc->fxp_spec, sc->fxp_res); 466 if (error) { 467 if (sc->fxp_spec == fxp_res_spec_mem) 468 sc->fxp_spec = fxp_res_spec_io; 469 else 470 sc->fxp_spec = fxp_res_spec_mem; 471 error = bus_alloc_resources(dev, sc->fxp_spec, sc->fxp_res); 472 } 473 if (error) { 474 device_printf(dev, "could not allocate resources\n"); 475 error = ENXIO; 476 goto fail; 477 } 478 479 if (bootverbose) { 480 device_printf(dev, "using %s space register mapping\n", 481 sc->fxp_spec == fxp_res_spec_mem ? "memory" : "I/O"); 482 } 483 484 /* 485 * Put CU/RU idle state and prepare full reset. 486 */ 487 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET); 488 DELAY(10); 489 /* Full reset and disable interrupts. */ 490 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SOFTWARE_RESET); 491 DELAY(10); 492 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE); 493 494 /* 495 * Find out how large of an SEEPROM we have. 496 */ 497 fxp_autosize_eeprom(sc); 498 fxp_load_eeprom(sc); 499 500 /* 501 * Find out the chip revision; lump all 82557 revs together. 502 */ 503 sc->ident = fxp_find_ident(dev); 504 if (sc->ident->ich > 0) { 505 /* Assume ICH controllers are 82559. */ 506 sc->revision = FXP_REV_82559_A0; 507 } else { 508 data = sc->eeprom[FXP_EEPROM_MAP_CNTR]; 509 if ((data >> 8) == 1) 510 sc->revision = FXP_REV_82557; 511 else 512 sc->revision = pci_get_revid(dev); 513 } 514 515 /* 516 * Check availability of WOL. 82559ER does not support WOL. 517 */ 518 if (sc->revision >= FXP_REV_82558_A4 && 519 sc->revision != FXP_REV_82559S_A) { 520 data = sc->eeprom[FXP_EEPROM_MAP_ID]; 521 if ((data & 0x20) != 0 && 522 pci_find_cap(sc->dev, PCIY_PMG, &pmc) == 0) 523 sc->flags |= FXP_FLAG_WOLCAP; 524 } 525 526 if (sc->revision == FXP_REV_82550_C) { 527 /* 528 * 82550C with server extension requires microcode to 529 * receive fragmented UDP datagrams. However if the 530 * microcode is used for client-only featured 82550C 531 * it locks up controller. 532 */ 533 data = sc->eeprom[FXP_EEPROM_MAP_COMPAT]; 534 if ((data & 0x0400) == 0) 535 sc->flags |= FXP_FLAG_NO_UCODE; 536 } 537 538 /* Receiver lock-up workaround detection. */ 539 if (sc->revision < FXP_REV_82558_A4) { 540 data = sc->eeprom[FXP_EEPROM_MAP_COMPAT]; 541 if ((data & 0x03) != 0x03) { 542 sc->flags |= FXP_FLAG_RXBUG; 543 device_printf(dev, "Enabling Rx lock-up workaround\n"); 544 } 545 } 546 547 /* 548 * Determine whether we must use the 503 serial interface. 549 */ 550 data = sc->eeprom[FXP_EEPROM_MAP_PRI_PHY]; 551 if (sc->revision == FXP_REV_82557 && (data & FXP_PHY_DEVICE_MASK) != 0 552 && (data & FXP_PHY_SERIAL_ONLY)) 553 sc->flags |= FXP_FLAG_SERIAL_MEDIA; 554 555 fxp_sysctl_node(sc); 556 /* 557 * Enable workarounds for certain chip revision deficiencies. 558 * 559 * Systems based on the ICH2/ICH2-M chip from Intel, and possibly 560 * some systems based a normal 82559 design, have a defect where 561 * the chip can cause a PCI protocol violation if it receives 562 * a CU_RESUME command when it is entering the IDLE state. The 563 * workaround is to disable Dynamic Standby Mode, so the chip never 564 * deasserts CLKRUN#, and always remains in an active state. 565 * 566 * See Intel 82801BA/82801BAM Specification Update, Errata #30. 567 */ 568 if ((sc->ident->ich >= 2 && sc->ident->ich <= 3) || 569 (sc->ident->ich == 0 && sc->revision >= FXP_REV_82559_A0)) { 570 data = sc->eeprom[FXP_EEPROM_MAP_ID]; 571 if (data & 0x02) { /* STB enable */ 572 uint16_t cksum; 573 int i; 574 575 device_printf(dev, 576 "Disabling dynamic standby mode in EEPROM\n"); 577 data &= ~0x02; 578 sc->eeprom[FXP_EEPROM_MAP_ID] = data; 579 fxp_write_eeprom(sc, &data, FXP_EEPROM_MAP_ID, 1); 580 device_printf(dev, "New EEPROM ID: 0x%x\n", data); 581 cksum = 0; 582 for (i = 0; i < (1 << sc->eeprom_size) - 1; i++) 583 cksum += sc->eeprom[i]; 584 i = (1 << sc->eeprom_size) - 1; 585 cksum = 0xBABA - cksum; 586 fxp_write_eeprom(sc, &cksum, i, 1); 587 device_printf(dev, 588 "EEPROM checksum @ 0x%x: 0x%x -> 0x%x\n", 589 i, sc->eeprom[i], cksum); 590 sc->eeprom[i] = cksum; 591 /* 592 * If the user elects to continue, try the software 593 * workaround, as it is better than nothing. 594 */ 595 sc->flags |= FXP_FLAG_CU_RESUME_BUG; 596 } 597 } 598 599 /* 600 * If we are not a 82557 chip, we can enable extended features. 601 */ 602 if (sc->revision != FXP_REV_82557) { 603 /* 604 * If MWI is enabled in the PCI configuration, and there 605 * is a valid cacheline size (8 or 16 dwords), then tell 606 * the board to turn on MWI. 607 */ 608 val = pci_read_config(dev, PCIR_COMMAND, 2); 609 if (val & PCIM_CMD_MWRICEN && 610 pci_read_config(dev, PCIR_CACHELNSZ, 1) != 0) 611 sc->flags |= FXP_FLAG_MWI_ENABLE; 612 613 /* turn on the extended TxCB feature */ 614 sc->flags |= FXP_FLAG_EXT_TXCB; 615 616 /* enable reception of long frames for VLAN */ 617 sc->flags |= FXP_FLAG_LONG_PKT_EN; 618 } else { 619 /* a hack to get long VLAN frames on a 82557 */ 620 sc->flags |= FXP_FLAG_SAVE_BAD; 621 } 622 623 /* For 82559 or later chips, Rx checksum offload is supported. */ 624 if (sc->revision >= FXP_REV_82559_A0) { 625 /* 82559ER does not support Rx checksum offloading. */ 626 if (sc->ident->device != 0x1209) 627 sc->flags |= FXP_FLAG_82559_RXCSUM; 628 } 629 /* 630 * Enable use of extended RFDs and TCBs for 82550 631 * and later chips. Note: we need extended TXCB support 632 * too, but that's already enabled by the code above. 633 * Be careful to do this only on the right devices. 634 */ 635 if (sc->revision == FXP_REV_82550 || sc->revision == FXP_REV_82550_C || 636 sc->revision == FXP_REV_82551_E || sc->revision == FXP_REV_82551_F 637 || sc->revision == FXP_REV_82551_10) { 638 sc->rfa_size = sizeof (struct fxp_rfa); 639 sc->tx_cmd = FXP_CB_COMMAND_IPCBXMIT; 640 sc->flags |= FXP_FLAG_EXT_RFA; 641 /* Use extended RFA instead of 82559 checksum mode. */ 642 sc->flags &= ~FXP_FLAG_82559_RXCSUM; 643 } else { 644 sc->rfa_size = sizeof (struct fxp_rfa) - FXP_RFAX_LEN; 645 sc->tx_cmd = FXP_CB_COMMAND_XMIT; 646 } 647 648 /* 649 * Allocate DMA tags and DMA safe memory. 650 */ 651 sc->maxtxseg = FXP_NTXSEG; 652 sc->maxsegsize = MCLBYTES; 653 if (sc->flags & FXP_FLAG_EXT_RFA) { 654 sc->maxtxseg--; 655 sc->maxsegsize = FXP_TSO_SEGSIZE; 656 } 657 error = bus_dma_tag_create(bus_get_dma_tag(dev), 2, 0, 658 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 659 sc->maxsegsize * sc->maxtxseg + sizeof(struct ether_vlan_header), 660 sc->maxtxseg, sc->maxsegsize, 0, NULL, NULL, &sc->fxp_txmtag); 661 if (error) { 662 device_printf(dev, "could not create TX DMA tag\n"); 663 goto fail; 664 } 665 666 error = bus_dma_tag_create(bus_get_dma_tag(dev), 2, 0, 667 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 668 MCLBYTES, 1, MCLBYTES, 0, NULL, NULL, &sc->fxp_rxmtag); 669 if (error) { 670 device_printf(dev, "could not create RX DMA tag\n"); 671 goto fail; 672 } 673 674 error = bus_dma_tag_create(bus_get_dma_tag(dev), 4, 0, 675 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 676 sizeof(struct fxp_stats), 1, sizeof(struct fxp_stats), 0, 677 NULL, NULL, &sc->fxp_stag); 678 if (error) { 679 device_printf(dev, "could not create stats DMA tag\n"); 680 goto fail; 681 } 682 683 error = bus_dmamem_alloc(sc->fxp_stag, (void **)&sc->fxp_stats, 684 BUS_DMA_NOWAIT | BUS_DMA_COHERENT | BUS_DMA_ZERO, &sc->fxp_smap); 685 if (error) { 686 device_printf(dev, "could not allocate stats DMA memory\n"); 687 goto fail; 688 } 689 error = bus_dmamap_load(sc->fxp_stag, sc->fxp_smap, sc->fxp_stats, 690 sizeof(struct fxp_stats), fxp_dma_map_addr, &sc->stats_addr, 691 BUS_DMA_NOWAIT); 692 if (error) { 693 device_printf(dev, "could not load the stats DMA buffer\n"); 694 goto fail; 695 } 696 697 error = bus_dma_tag_create(bus_get_dma_tag(dev), 4, 0, 698 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 699 FXP_TXCB_SZ, 1, FXP_TXCB_SZ, 0, NULL, NULL, &sc->cbl_tag); 700 if (error) { 701 device_printf(dev, "could not create TxCB DMA tag\n"); 702 goto fail; 703 } 704 705 error = bus_dmamem_alloc(sc->cbl_tag, (void **)&sc->fxp_desc.cbl_list, 706 BUS_DMA_NOWAIT | BUS_DMA_COHERENT | BUS_DMA_ZERO, &sc->cbl_map); 707 if (error) { 708 device_printf(dev, "could not allocate TxCB DMA memory\n"); 709 goto fail; 710 } 711 712 error = bus_dmamap_load(sc->cbl_tag, sc->cbl_map, 713 sc->fxp_desc.cbl_list, FXP_TXCB_SZ, fxp_dma_map_addr, 714 &sc->fxp_desc.cbl_addr, BUS_DMA_NOWAIT); 715 if (error) { 716 device_printf(dev, "could not load TxCB DMA buffer\n"); 717 goto fail; 718 } 719 720 error = bus_dma_tag_create(bus_get_dma_tag(dev), 4, 0, 721 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 722 sizeof(struct fxp_cb_mcs), 1, sizeof(struct fxp_cb_mcs), 0, 723 NULL, NULL, &sc->mcs_tag); 724 if (error) { 725 device_printf(dev, 726 "could not create multicast setup DMA tag\n"); 727 goto fail; 728 } 729 730 error = bus_dmamem_alloc(sc->mcs_tag, (void **)&sc->mcsp, 731 BUS_DMA_NOWAIT | BUS_DMA_COHERENT | BUS_DMA_ZERO, &sc->mcs_map); 732 if (error) { 733 device_printf(dev, 734 "could not allocate multicast setup DMA memory\n"); 735 goto fail; 736 } 737 error = bus_dmamap_load(sc->mcs_tag, sc->mcs_map, sc->mcsp, 738 sizeof(struct fxp_cb_mcs), fxp_dma_map_addr, &sc->mcs_addr, 739 BUS_DMA_NOWAIT); 740 if (error) { 741 device_printf(dev, 742 "can't load the multicast setup DMA buffer\n"); 743 goto fail; 744 } 745 746 /* 747 * Pre-allocate the TX DMA maps and setup the pointers to 748 * the TX command blocks. 749 */ 750 txp = sc->fxp_desc.tx_list; 751 tcbp = sc->fxp_desc.cbl_list; 752 for (i = 0; i < FXP_NTXCB; i++) { 753 txp[i].tx_cb = tcbp + i; 754 error = bus_dmamap_create(sc->fxp_txmtag, 0, &txp[i].tx_map); 755 if (error) { 756 device_printf(dev, "can't create DMA map for TX\n"); 757 goto fail; 758 } 759 } 760 error = bus_dmamap_create(sc->fxp_rxmtag, 0, &sc->spare_map); 761 if (error) { 762 device_printf(dev, "can't create spare DMA map\n"); 763 goto fail; 764 } 765 766 /* 767 * Pre-allocate our receive buffers. 768 */ 769 sc->fxp_desc.rx_head = sc->fxp_desc.rx_tail = NULL; 770 for (i = 0; i < FXP_NRFABUFS; i++) { 771 rxp = &sc->fxp_desc.rx_list[i]; 772 error = bus_dmamap_create(sc->fxp_rxmtag, 0, &rxp->rx_map); 773 if (error) { 774 device_printf(dev, "can't create DMA map for RX\n"); 775 goto fail; 776 } 777 if (fxp_new_rfabuf(sc, rxp) != 0) { 778 error = ENOMEM; 779 goto fail; 780 } 781 fxp_add_rfabuf(sc, rxp); 782 } 783 784 /* 785 * Read MAC address. 786 */ 787 eaddr[0] = sc->eeprom[FXP_EEPROM_MAP_IA0] & 0xff; 788 eaddr[1] = sc->eeprom[FXP_EEPROM_MAP_IA0] >> 8; 789 eaddr[2] = sc->eeprom[FXP_EEPROM_MAP_IA1] & 0xff; 790 eaddr[3] = sc->eeprom[FXP_EEPROM_MAP_IA1] >> 8; 791 eaddr[4] = sc->eeprom[FXP_EEPROM_MAP_IA2] & 0xff; 792 eaddr[5] = sc->eeprom[FXP_EEPROM_MAP_IA2] >> 8; 793 if (bootverbose) { 794 device_printf(dev, "PCI IDs: %04x %04x %04x %04x %04x\n", 795 pci_get_vendor(dev), pci_get_device(dev), 796 pci_get_subvendor(dev), pci_get_subdevice(dev), 797 pci_get_revid(dev)); 798 device_printf(dev, "Dynamic Standby mode is %s\n", 799 sc->eeprom[FXP_EEPROM_MAP_ID] & 0x02 ? "enabled" : 800 "disabled"); 801 } 802 803 /* 804 * If this is only a 10Mbps device, then there is no MII, and 805 * the PHY will use a serial interface instead. 806 * 807 * The Seeq 80c24 AutoDUPLEX(tm) Ethernet Interface Adapter 808 * doesn't have a programming interface of any sort. The 809 * media is sensed automatically based on how the link partner 810 * is configured. This is, in essence, manual configuration. 811 */ 812 if (sc->flags & FXP_FLAG_SERIAL_MEDIA) { 813 ifmedia_add(&sc->sc_media, IFM_ETHER|IFM_MANUAL, 0, NULL); 814 ifmedia_set(&sc->sc_media, IFM_ETHER|IFM_MANUAL); 815 } else { 816 /* 817 * i82557 wedge when isolating all of their PHYs. 818 */ 819 flags = MIIF_NOISOLATE; 820 if (sc->revision >= FXP_REV_82558_A4) 821 flags |= MIIF_DOPAUSE; 822 error = mii_attach(dev, &sc->miibus, ifp, 823 (ifm_change_cb_t)fxp_ifmedia_upd, 824 (ifm_stat_cb_t)fxp_ifmedia_sts, BMSR_DEFCAPMASK, 825 MII_PHY_ANY, MII_OFFSET_ANY, flags); 826 if (error != 0) { 827 device_printf(dev, "attaching PHYs failed\n"); 828 goto fail; 829 } 830 } 831 832 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 833 if_setdev(ifp, dev); 834 if_setinitfn(ifp, fxp_init); 835 if_setsoftc(ifp, sc); 836 if_setflags(ifp, IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST); 837 if_setioctlfn(ifp, fxp_ioctl); 838 if_setstartfn(ifp, fxp_start); 839 840 if_setcapabilities(ifp, 0); 841 if_setcapenable(ifp, 0); 842 843 /* Enable checksum offload/TSO for 82550 or better chips */ 844 if (sc->flags & FXP_FLAG_EXT_RFA) { 845 if_sethwassist(ifp, FXP_CSUM_FEATURES | CSUM_TSO); 846 if_setcapabilitiesbit(ifp, IFCAP_HWCSUM | IFCAP_TSO4, 0); 847 if_setcapenablebit(ifp, IFCAP_HWCSUM | IFCAP_TSO4, 0); 848 } 849 850 if (sc->flags & FXP_FLAG_82559_RXCSUM) { 851 if_setcapabilitiesbit(ifp, IFCAP_RXCSUM, 0); 852 if_setcapenablebit(ifp, IFCAP_RXCSUM, 0); 853 } 854 855 if (sc->flags & FXP_FLAG_WOLCAP) { 856 if_setcapabilitiesbit(ifp, IFCAP_WOL_MAGIC, 0); 857 if_setcapenablebit(ifp, IFCAP_WOL_MAGIC, 0); 858 } 859 860 #ifdef DEVICE_POLLING 861 /* Inform the world we support polling. */ 862 if_setcapabilitiesbit(ifp, IFCAP_POLLING, 0); 863 #endif 864 865 /* 866 * Attach the interface. 867 */ 868 ether_ifattach(ifp, eaddr); 869 870 /* 871 * Tell the upper layer(s) we support long frames. 872 * Must appear after the call to ether_ifattach() because 873 * ether_ifattach() sets ifi_hdrlen to the default value. 874 */ 875 if_setifheaderlen(ifp, sizeof(struct ether_vlan_header)); 876 if_setcapabilitiesbit(ifp, IFCAP_VLAN_MTU, 0); 877 if_setcapenablebit(ifp, IFCAP_VLAN_MTU, 0); 878 if ((sc->flags & FXP_FLAG_EXT_RFA) != 0) { 879 if_setcapabilitiesbit(ifp, IFCAP_VLAN_HWTAGGING | 880 IFCAP_VLAN_HWCSUM | IFCAP_VLAN_HWTSO, 0); 881 if_setcapenablebit(ifp, IFCAP_VLAN_HWTAGGING | 882 IFCAP_VLAN_HWCSUM | IFCAP_VLAN_HWTSO, 0); 883 } 884 885 /* 886 * Let the system queue as many packets as we have available 887 * TX descriptors. 888 */ 889 if_setsendqlen(ifp, FXP_NTXCB - 1); 890 if_setsendqready(ifp); 891 892 /* 893 * Hook our interrupt after all initialization is complete. 894 */ 895 error = bus_setup_intr(dev, sc->fxp_res[1], INTR_TYPE_NET | INTR_MPSAFE, 896 NULL, fxp_intr, sc, &sc->ih); 897 if (error) { 898 device_printf(dev, "could not setup irq\n"); 899 ether_ifdetach(sc->ifp); 900 goto fail; 901 } 902 903 /* 904 * Configure hardware to reject magic frames otherwise 905 * system will hang on recipt of magic frames. 906 */ 907 if ((sc->flags & FXP_FLAG_WOLCAP) != 0) { 908 FXP_LOCK(sc); 909 /* Clear wakeup events. */ 910 CSR_WRITE_1(sc, FXP_CSR_PMDR, CSR_READ_1(sc, FXP_CSR_PMDR)); 911 fxp_init_body(sc, 0); 912 fxp_stop(sc); 913 FXP_UNLOCK(sc); 914 } 915 916 fail: 917 if (error) 918 fxp_release(sc); 919 return (error); 920 } 921 922 /* 923 * Release all resources. The softc lock should not be held and the 924 * interrupt should already be torn down. 925 */ 926 static void 927 fxp_release(struct fxp_softc *sc) 928 { 929 struct fxp_rx *rxp; 930 struct fxp_tx *txp; 931 int i; 932 933 FXP_LOCK_ASSERT(sc, MA_NOTOWNED); 934 KASSERT(sc->ih == NULL, 935 ("fxp_release() called with intr handle still active")); 936 if (sc->miibus) 937 device_delete_child(sc->dev, sc->miibus); 938 bus_generic_detach(sc->dev); 939 ifmedia_removeall(&sc->sc_media); 940 if (sc->fxp_desc.cbl_list) { 941 bus_dmamap_unload(sc->cbl_tag, sc->cbl_map); 942 bus_dmamem_free(sc->cbl_tag, sc->fxp_desc.cbl_list, 943 sc->cbl_map); 944 } 945 if (sc->fxp_stats) { 946 bus_dmamap_unload(sc->fxp_stag, sc->fxp_smap); 947 bus_dmamem_free(sc->fxp_stag, sc->fxp_stats, sc->fxp_smap); 948 } 949 if (sc->mcsp) { 950 bus_dmamap_unload(sc->mcs_tag, sc->mcs_map); 951 bus_dmamem_free(sc->mcs_tag, sc->mcsp, sc->mcs_map); 952 } 953 bus_release_resources(sc->dev, sc->fxp_spec, sc->fxp_res); 954 if (sc->fxp_rxmtag) { 955 for (i = 0; i < FXP_NRFABUFS; i++) { 956 rxp = &sc->fxp_desc.rx_list[i]; 957 if (rxp->rx_mbuf != NULL) { 958 bus_dmamap_sync(sc->fxp_rxmtag, rxp->rx_map, 959 BUS_DMASYNC_POSTREAD); 960 bus_dmamap_unload(sc->fxp_rxmtag, rxp->rx_map); 961 m_freem(rxp->rx_mbuf); 962 } 963 bus_dmamap_destroy(sc->fxp_rxmtag, rxp->rx_map); 964 } 965 bus_dmamap_destroy(sc->fxp_rxmtag, sc->spare_map); 966 bus_dma_tag_destroy(sc->fxp_rxmtag); 967 } 968 if (sc->fxp_txmtag) { 969 for (i = 0; i < FXP_NTXCB; i++) { 970 txp = &sc->fxp_desc.tx_list[i]; 971 if (txp->tx_mbuf != NULL) { 972 bus_dmamap_sync(sc->fxp_txmtag, txp->tx_map, 973 BUS_DMASYNC_POSTWRITE); 974 bus_dmamap_unload(sc->fxp_txmtag, txp->tx_map); 975 m_freem(txp->tx_mbuf); 976 } 977 bus_dmamap_destroy(sc->fxp_txmtag, txp->tx_map); 978 } 979 bus_dma_tag_destroy(sc->fxp_txmtag); 980 } 981 if (sc->fxp_stag) 982 bus_dma_tag_destroy(sc->fxp_stag); 983 if (sc->cbl_tag) 984 bus_dma_tag_destroy(sc->cbl_tag); 985 if (sc->mcs_tag) 986 bus_dma_tag_destroy(sc->mcs_tag); 987 if (sc->ifp) 988 if_free(sc->ifp); 989 990 mtx_destroy(&sc->sc_mtx); 991 } 992 993 /* 994 * Detach interface. 995 */ 996 static int 997 fxp_detach(device_t dev) 998 { 999 struct fxp_softc *sc = device_get_softc(dev); 1000 1001 #ifdef DEVICE_POLLING 1002 if (if_getcapenable(sc->ifp) & IFCAP_POLLING) 1003 ether_poll_deregister(sc->ifp); 1004 #endif 1005 1006 FXP_LOCK(sc); 1007 /* 1008 * Stop DMA and drop transmit queue, but disable interrupts first. 1009 */ 1010 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE); 1011 fxp_stop(sc); 1012 FXP_UNLOCK(sc); 1013 callout_drain(&sc->stat_ch); 1014 1015 /* 1016 * Close down routes etc. 1017 */ 1018 ether_ifdetach(sc->ifp); 1019 1020 /* 1021 * Unhook interrupt before dropping lock. This is to prevent 1022 * races with fxp_intr(). 1023 */ 1024 bus_teardown_intr(sc->dev, sc->fxp_res[1], sc->ih); 1025 sc->ih = NULL; 1026 1027 /* Release our allocated resources. */ 1028 fxp_release(sc); 1029 return (0); 1030 } 1031 1032 /* 1033 * Device shutdown routine. Called at system shutdown after sync. The 1034 * main purpose of this routine is to shut off receiver DMA so that 1035 * kernel memory doesn't get clobbered during warmboot. 1036 */ 1037 static int 1038 fxp_shutdown(device_t dev) 1039 { 1040 1041 /* 1042 * Make sure that DMA is disabled prior to reboot. Not doing 1043 * do could allow DMA to corrupt kernel memory during the 1044 * reboot before the driver initializes. 1045 */ 1046 return (fxp_suspend(dev)); 1047 } 1048 1049 /* 1050 * Device suspend routine. Stop the interface and save some PCI 1051 * settings in case the BIOS doesn't restore them properly on 1052 * resume. 1053 */ 1054 static int 1055 fxp_suspend(device_t dev) 1056 { 1057 struct fxp_softc *sc = device_get_softc(dev); 1058 if_t ifp; 1059 int pmc; 1060 uint16_t pmstat; 1061 1062 FXP_LOCK(sc); 1063 1064 ifp = sc->ifp; 1065 if (pci_find_cap(sc->dev, PCIY_PMG, &pmc) == 0) { 1066 pmstat = pci_read_config(sc->dev, pmc + PCIR_POWER_STATUS, 2); 1067 pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE); 1068 if ((if_getcapenable(ifp) & IFCAP_WOL_MAGIC) != 0) { 1069 /* Request PME. */ 1070 pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE; 1071 sc->flags |= FXP_FLAG_WOL; 1072 /* Reconfigure hardware to accept magic frames. */ 1073 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 1074 fxp_init_body(sc, 0); 1075 } 1076 pci_write_config(sc->dev, pmc + PCIR_POWER_STATUS, pmstat, 2); 1077 } 1078 fxp_stop(sc); 1079 1080 sc->suspended = 1; 1081 1082 FXP_UNLOCK(sc); 1083 return (0); 1084 } 1085 1086 /* 1087 * Device resume routine. re-enable busmastering, and restart the interface if 1088 * appropriate. 1089 */ 1090 static int 1091 fxp_resume(device_t dev) 1092 { 1093 struct fxp_softc *sc = device_get_softc(dev); 1094 if_t ifp = sc->ifp; 1095 int pmc; 1096 uint16_t pmstat; 1097 1098 FXP_LOCK(sc); 1099 1100 if (pci_find_cap(sc->dev, PCIY_PMG, &pmc) == 0) { 1101 sc->flags &= ~FXP_FLAG_WOL; 1102 pmstat = pci_read_config(sc->dev, pmc + PCIR_POWER_STATUS, 2); 1103 /* Disable PME and clear PME status. */ 1104 pmstat &= ~PCIM_PSTAT_PMEENABLE; 1105 pci_write_config(sc->dev, pmc + PCIR_POWER_STATUS, pmstat, 2); 1106 if ((sc->flags & FXP_FLAG_WOLCAP) != 0) 1107 CSR_WRITE_1(sc, FXP_CSR_PMDR, 1108 CSR_READ_1(sc, FXP_CSR_PMDR)); 1109 } 1110 1111 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET); 1112 DELAY(10); 1113 1114 /* reinitialize interface if necessary */ 1115 if (if_getflags(ifp) & IFF_UP) 1116 fxp_init_body(sc, 1); 1117 1118 sc->suspended = 0; 1119 1120 FXP_UNLOCK(sc); 1121 return (0); 1122 } 1123 1124 static void 1125 fxp_eeprom_shiftin(struct fxp_softc *sc, int data, int length) 1126 { 1127 uint16_t reg; 1128 int x; 1129 1130 /* 1131 * Shift in data. 1132 */ 1133 for (x = 1 << (length - 1); x; x >>= 1) { 1134 if (data & x) 1135 reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI; 1136 else 1137 reg = FXP_EEPROM_EECS; 1138 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 1139 DELAY(1); 1140 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK); 1141 DELAY(1); 1142 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 1143 DELAY(1); 1144 } 1145 } 1146 1147 /* 1148 * Read from the serial EEPROM. Basically, you manually shift in 1149 * the read opcode (one bit at a time) and then shift in the address, 1150 * and then you shift out the data (all of this one bit at a time). 1151 * The word size is 16 bits, so you have to provide the address for 1152 * every 16 bits of data. 1153 */ 1154 static uint16_t 1155 fxp_eeprom_getword(struct fxp_softc *sc, int offset, int autosize) 1156 { 1157 uint16_t reg, data; 1158 int x; 1159 1160 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 1161 /* 1162 * Shift in read opcode. 1163 */ 1164 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_READ, 3); 1165 /* 1166 * Shift in address. 1167 */ 1168 data = 0; 1169 for (x = 1 << (sc->eeprom_size - 1); x; x >>= 1) { 1170 if (offset & x) 1171 reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI; 1172 else 1173 reg = FXP_EEPROM_EECS; 1174 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 1175 DELAY(1); 1176 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK); 1177 DELAY(1); 1178 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 1179 DELAY(1); 1180 reg = CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO; 1181 data++; 1182 if (autosize && reg == 0) { 1183 sc->eeprom_size = data; 1184 break; 1185 } 1186 } 1187 /* 1188 * Shift out data. 1189 */ 1190 data = 0; 1191 reg = FXP_EEPROM_EECS; 1192 for (x = 1 << 15; x; x >>= 1) { 1193 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK); 1194 DELAY(1); 1195 if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO) 1196 data |= x; 1197 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 1198 DELAY(1); 1199 } 1200 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 1201 DELAY(1); 1202 1203 return (data); 1204 } 1205 1206 static void 1207 fxp_eeprom_putword(struct fxp_softc *sc, int offset, uint16_t data) 1208 { 1209 int i; 1210 1211 /* 1212 * Erase/write enable. 1213 */ 1214 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 1215 fxp_eeprom_shiftin(sc, 0x4, 3); 1216 fxp_eeprom_shiftin(sc, 0x03 << (sc->eeprom_size - 2), sc->eeprom_size); 1217 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 1218 DELAY(1); 1219 /* 1220 * Shift in write opcode, address, data. 1221 */ 1222 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 1223 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_WRITE, 3); 1224 fxp_eeprom_shiftin(sc, offset, sc->eeprom_size); 1225 fxp_eeprom_shiftin(sc, data, 16); 1226 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 1227 DELAY(1); 1228 /* 1229 * Wait for EEPROM to finish up. 1230 */ 1231 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 1232 DELAY(1); 1233 for (i = 0; i < 1000; i++) { 1234 if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO) 1235 break; 1236 DELAY(50); 1237 } 1238 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 1239 DELAY(1); 1240 /* 1241 * Erase/write disable. 1242 */ 1243 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 1244 fxp_eeprom_shiftin(sc, 0x4, 3); 1245 fxp_eeprom_shiftin(sc, 0, sc->eeprom_size); 1246 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 1247 DELAY(1); 1248 } 1249 1250 /* 1251 * From NetBSD: 1252 * 1253 * Figure out EEPROM size. 1254 * 1255 * 559's can have either 64-word or 256-word EEPROMs, the 558 1256 * datasheet only talks about 64-word EEPROMs, and the 557 datasheet 1257 * talks about the existence of 16 to 256 word EEPROMs. 1258 * 1259 * The only known sizes are 64 and 256, where the 256 version is used 1260 * by CardBus cards to store CIS information. 1261 * 1262 * The address is shifted in msb-to-lsb, and after the last 1263 * address-bit the EEPROM is supposed to output a `dummy zero' bit, 1264 * after which follows the actual data. We try to detect this zero, by 1265 * probing the data-out bit in the EEPROM control register just after 1266 * having shifted in a bit. If the bit is zero, we assume we've 1267 * shifted enough address bits. The data-out should be tri-state, 1268 * before this, which should translate to a logical one. 1269 */ 1270 static void 1271 fxp_autosize_eeprom(struct fxp_softc *sc) 1272 { 1273 1274 /* guess maximum size of 256 words */ 1275 sc->eeprom_size = 8; 1276 1277 /* autosize */ 1278 (void) fxp_eeprom_getword(sc, 0, 1); 1279 } 1280 1281 static void 1282 fxp_read_eeprom(struct fxp_softc *sc, u_short *data, int offset, int words) 1283 { 1284 int i; 1285 1286 for (i = 0; i < words; i++) 1287 data[i] = fxp_eeprom_getword(sc, offset + i, 0); 1288 } 1289 1290 static void 1291 fxp_write_eeprom(struct fxp_softc *sc, u_short *data, int offset, int words) 1292 { 1293 int i; 1294 1295 for (i = 0; i < words; i++) 1296 fxp_eeprom_putword(sc, offset + i, data[i]); 1297 } 1298 1299 static void 1300 fxp_load_eeprom(struct fxp_softc *sc) 1301 { 1302 int i; 1303 uint16_t cksum; 1304 1305 fxp_read_eeprom(sc, sc->eeprom, 0, 1 << sc->eeprom_size); 1306 cksum = 0; 1307 for (i = 0; i < (1 << sc->eeprom_size) - 1; i++) 1308 cksum += sc->eeprom[i]; 1309 cksum = 0xBABA - cksum; 1310 if (cksum != sc->eeprom[(1 << sc->eeprom_size) - 1]) 1311 device_printf(sc->dev, 1312 "EEPROM checksum mismatch! (0x%04x -> 0x%04x)\n", 1313 cksum, sc->eeprom[(1 << sc->eeprom_size) - 1]); 1314 } 1315 1316 /* 1317 * Grab the softc lock and call the real fxp_start_body() routine 1318 */ 1319 static void 1320 fxp_start(if_t ifp) 1321 { 1322 struct fxp_softc *sc = if_getsoftc(ifp); 1323 1324 FXP_LOCK(sc); 1325 fxp_start_body(ifp); 1326 FXP_UNLOCK(sc); 1327 } 1328 1329 /* 1330 * Start packet transmission on the interface. 1331 * This routine must be called with the softc lock held, and is an 1332 * internal entry point only. 1333 */ 1334 static void 1335 fxp_start_body(if_t ifp) 1336 { 1337 struct fxp_softc *sc = if_getsoftc(ifp); 1338 struct mbuf *mb_head; 1339 int txqueued; 1340 1341 FXP_LOCK_ASSERT(sc, MA_OWNED); 1342 1343 if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 1344 IFF_DRV_RUNNING) 1345 return; 1346 1347 if (sc->tx_queued > FXP_NTXCB_HIWAT) 1348 fxp_txeof(sc); 1349 /* 1350 * We're finished if there is nothing more to add to the list or if 1351 * we're all filled up with buffers to transmit. 1352 * NOTE: One TxCB is reserved to guarantee that fxp_mc_setup() can add 1353 * a NOP command when needed. 1354 */ 1355 txqueued = 0; 1356 while (!if_sendq_empty(ifp) && sc->tx_queued < FXP_NTXCB - 1) { 1357 1358 /* 1359 * Grab a packet to transmit. 1360 */ 1361 mb_head = if_dequeue(ifp); 1362 if (mb_head == NULL) 1363 break; 1364 1365 if (fxp_encap(sc, &mb_head)) { 1366 if (mb_head == NULL) 1367 break; 1368 if_sendq_prepend(ifp, mb_head); 1369 if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, 0); 1370 } 1371 txqueued++; 1372 /* 1373 * Pass packet to bpf if there is a listener. 1374 */ 1375 bpf_mtap_if(ifp, mb_head); 1376 } 1377 1378 /* 1379 * We're finished. If we added to the list, issue a RESUME to get DMA 1380 * going again if suspended. 1381 */ 1382 if (txqueued > 0) { 1383 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, 1384 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1385 fxp_scb_wait(sc); 1386 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_RESUME); 1387 /* 1388 * Set a 5 second timer just in case we don't hear 1389 * from the card again. 1390 */ 1391 sc->watchdog_timer = 5; 1392 } 1393 } 1394 1395 static int 1396 fxp_encap(struct fxp_softc *sc, struct mbuf **m_head) 1397 { 1398 struct mbuf *m; 1399 struct fxp_tx *txp; 1400 struct fxp_cb_tx *cbp; 1401 struct tcphdr *tcp; 1402 bus_dma_segment_t segs[FXP_NTXSEG]; 1403 int error, i, nseg, tcp_payload; 1404 1405 FXP_LOCK_ASSERT(sc, MA_OWNED); 1406 1407 tcp_payload = 0; 1408 tcp = NULL; 1409 /* 1410 * Get pointer to next available tx desc. 1411 */ 1412 txp = sc->fxp_desc.tx_last->tx_next; 1413 1414 /* 1415 * A note in Appendix B of the Intel 8255x 10/100 Mbps 1416 * Ethernet Controller Family Open Source Software 1417 * Developer Manual says: 1418 * Using software parsing is only allowed with legal 1419 * TCP/IP or UDP/IP packets. 1420 * ... 1421 * For all other datagrams, hardware parsing must 1422 * be used. 1423 * Software parsing appears to truncate ICMP and 1424 * fragmented UDP packets that contain one to three 1425 * bytes in the second (and final) mbuf of the packet. 1426 */ 1427 if (sc->flags & FXP_FLAG_EXT_RFA) 1428 txp->tx_cb->ipcb_ip_activation_high = 1429 FXP_IPCB_HARDWAREPARSING_ENABLE; 1430 1431 m = *m_head; 1432 if (m->m_pkthdr.csum_flags & CSUM_TSO) { 1433 /* 1434 * 82550/82551 requires ethernet/IP/TCP headers must be 1435 * contained in the first active transmit buffer. 1436 */ 1437 struct ether_header *eh; 1438 struct ip *ip; 1439 uint32_t ip_off, poff; 1440 1441 if (M_WRITABLE(*m_head) == 0) { 1442 /* Get a writable copy. */ 1443 m = m_dup(*m_head, M_NOWAIT); 1444 m_freem(*m_head); 1445 if (m == NULL) { 1446 *m_head = NULL; 1447 return (ENOBUFS); 1448 } 1449 *m_head = m; 1450 } 1451 ip_off = sizeof(struct ether_header); 1452 m = m_pullup(*m_head, ip_off); 1453 if (m == NULL) { 1454 *m_head = NULL; 1455 return (ENOBUFS); 1456 } 1457 eh = mtod(m, struct ether_header *); 1458 /* Check the existence of VLAN tag. */ 1459 if (eh->ether_type == htons(ETHERTYPE_VLAN)) { 1460 ip_off = sizeof(struct ether_vlan_header); 1461 m = m_pullup(m, ip_off); 1462 if (m == NULL) { 1463 *m_head = NULL; 1464 return (ENOBUFS); 1465 } 1466 } 1467 m = m_pullup(m, ip_off + sizeof(struct ip)); 1468 if (m == NULL) { 1469 *m_head = NULL; 1470 return (ENOBUFS); 1471 } 1472 ip = (struct ip *)(mtod(m, char *) + ip_off); 1473 poff = ip_off + (ip->ip_hl << 2); 1474 m = m_pullup(m, poff + sizeof(struct tcphdr)); 1475 if (m == NULL) { 1476 *m_head = NULL; 1477 return (ENOBUFS); 1478 } 1479 tcp = (struct tcphdr *)(mtod(m, char *) + poff); 1480 m = m_pullup(m, poff + (tcp->th_off << 2)); 1481 if (m == NULL) { 1482 *m_head = NULL; 1483 return (ENOBUFS); 1484 } 1485 1486 /* 1487 * Since 82550/82551 doesn't modify IP length and pseudo 1488 * checksum in the first frame driver should compute it. 1489 */ 1490 ip = (struct ip *)(mtod(m, char *) + ip_off); 1491 tcp = (struct tcphdr *)(mtod(m, char *) + poff); 1492 ip->ip_sum = 0; 1493 ip->ip_len = htons(m->m_pkthdr.tso_segsz + (ip->ip_hl << 2) + 1494 (tcp->th_off << 2)); 1495 tcp->th_sum = in_pseudo(ip->ip_src.s_addr, ip->ip_dst.s_addr, 1496 htons(IPPROTO_TCP + (tcp->th_off << 2) + 1497 m->m_pkthdr.tso_segsz)); 1498 /* Compute total TCP payload. */ 1499 tcp_payload = m->m_pkthdr.len - ip_off - (ip->ip_hl << 2); 1500 tcp_payload -= tcp->th_off << 2; 1501 *m_head = m; 1502 } else if (m->m_pkthdr.csum_flags & FXP_CSUM_FEATURES) { 1503 /* 1504 * Deal with TCP/IP checksum offload. Note that 1505 * in order for TCP checksum offload to work, 1506 * the pseudo header checksum must have already 1507 * been computed and stored in the checksum field 1508 * in the TCP header. The stack should have 1509 * already done this for us. 1510 */ 1511 txp->tx_cb->ipcb_ip_schedule = FXP_IPCB_TCPUDP_CHECKSUM_ENABLE; 1512 if (m->m_pkthdr.csum_flags & CSUM_TCP) 1513 txp->tx_cb->ipcb_ip_schedule |= FXP_IPCB_TCP_PACKET; 1514 1515 #ifdef FXP_IP_CSUM_WAR 1516 /* 1517 * XXX The 82550 chip appears to have trouble 1518 * dealing with IP header checksums in very small 1519 * datagrams, namely fragments from 1 to 3 bytes 1520 * in size. For example, say you want to transmit 1521 * a UDP packet of 1473 bytes. The packet will be 1522 * fragmented over two IP datagrams, the latter 1523 * containing only one byte of data. The 82550 will 1524 * botch the header checksum on the 1-byte fragment. 1525 * As long as the datagram contains 4 or more bytes 1526 * of data, you're ok. 1527 * 1528 * The following code attempts to work around this 1529 * problem: if the datagram is less than 38 bytes 1530 * in size (14 bytes ether header, 20 bytes IP header, 1531 * plus 4 bytes of data), we punt and compute the IP 1532 * header checksum by hand. This workaround doesn't 1533 * work very well, however, since it can be fooled 1534 * by things like VLAN tags and IP options that make 1535 * the header sizes/offsets vary. 1536 */ 1537 1538 if (m->m_pkthdr.csum_flags & CSUM_IP) { 1539 if (m->m_pkthdr.len < 38) { 1540 struct ip *ip; 1541 m->m_data += ETHER_HDR_LEN; 1542 ip = mtod(m, struct ip *); 1543 ip->ip_sum = in_cksum(m, ip->ip_hl << 2); 1544 m->m_data -= ETHER_HDR_LEN; 1545 m->m_pkthdr.csum_flags &= ~CSUM_IP; 1546 } else { 1547 txp->tx_cb->ipcb_ip_activation_high = 1548 FXP_IPCB_HARDWAREPARSING_ENABLE; 1549 txp->tx_cb->ipcb_ip_schedule |= 1550 FXP_IPCB_IP_CHECKSUM_ENABLE; 1551 } 1552 } 1553 #endif 1554 } 1555 1556 error = bus_dmamap_load_mbuf_sg(sc->fxp_txmtag, txp->tx_map, *m_head, 1557 segs, &nseg, 0); 1558 if (error == EFBIG) { 1559 m = m_collapse(*m_head, M_NOWAIT, sc->maxtxseg); 1560 if (m == NULL) { 1561 m_freem(*m_head); 1562 *m_head = NULL; 1563 return (ENOMEM); 1564 } 1565 *m_head = m; 1566 error = bus_dmamap_load_mbuf_sg(sc->fxp_txmtag, txp->tx_map, 1567 *m_head, segs, &nseg, 0); 1568 if (error != 0) { 1569 m_freem(*m_head); 1570 *m_head = NULL; 1571 return (ENOMEM); 1572 } 1573 } else if (error != 0) 1574 return (error); 1575 if (nseg == 0) { 1576 m_freem(*m_head); 1577 *m_head = NULL; 1578 return (EIO); 1579 } 1580 1581 KASSERT(nseg <= sc->maxtxseg, ("too many DMA segments")); 1582 bus_dmamap_sync(sc->fxp_txmtag, txp->tx_map, BUS_DMASYNC_PREWRITE); 1583 1584 cbp = txp->tx_cb; 1585 for (i = 0; i < nseg; i++) { 1586 /* 1587 * If this is an 82550/82551, then we're using extended 1588 * TxCBs _and_ we're using checksum offload. This means 1589 * that the TxCB is really an IPCB. One major difference 1590 * between the two is that with plain extended TxCBs, 1591 * the bottom half of the TxCB contains two entries from 1592 * the TBD array, whereas IPCBs contain just one entry: 1593 * one entry (8 bytes) has been sacrificed for the TCP/IP 1594 * checksum offload control bits. So to make things work 1595 * right, we have to start filling in the TBD array 1596 * starting from a different place depending on whether 1597 * the chip is an 82550/82551 or not. 1598 */ 1599 if (sc->flags & FXP_FLAG_EXT_RFA) { 1600 cbp->tbd[i + 1].tb_addr = htole32(segs[i].ds_addr); 1601 cbp->tbd[i + 1].tb_size = htole32(segs[i].ds_len); 1602 } else { 1603 cbp->tbd[i].tb_addr = htole32(segs[i].ds_addr); 1604 cbp->tbd[i].tb_size = htole32(segs[i].ds_len); 1605 } 1606 } 1607 if (sc->flags & FXP_FLAG_EXT_RFA) { 1608 /* Configure dynamic TBD for 82550/82551. */ 1609 cbp->tbd_number = 0xFF; 1610 cbp->tbd[nseg].tb_size |= htole32(0x8000); 1611 } else 1612 cbp->tbd_number = nseg; 1613 /* Configure TSO. */ 1614 if (m->m_pkthdr.csum_flags & CSUM_TSO) { 1615 cbp->tbdtso.tb_size = htole32(m->m_pkthdr.tso_segsz << 16); 1616 cbp->tbd[1].tb_size |= htole32(tcp_payload << 16); 1617 cbp->ipcb_ip_schedule |= FXP_IPCB_LARGESEND_ENABLE | 1618 FXP_IPCB_IP_CHECKSUM_ENABLE | 1619 FXP_IPCB_TCP_PACKET | 1620 FXP_IPCB_TCPUDP_CHECKSUM_ENABLE; 1621 } 1622 /* Configure VLAN hardware tag insertion. */ 1623 if ((m->m_flags & M_VLANTAG) != 0) { 1624 cbp->ipcb_vlan_id = htons(m->m_pkthdr.ether_vtag); 1625 txp->tx_cb->ipcb_ip_activation_high |= 1626 FXP_IPCB_INSERTVLAN_ENABLE; 1627 } 1628 1629 txp->tx_mbuf = m; 1630 txp->tx_cb->cb_status = 0; 1631 txp->tx_cb->byte_count = 0; 1632 if (sc->tx_queued != FXP_CXINT_THRESH - 1) 1633 txp->tx_cb->cb_command = 1634 htole16(sc->tx_cmd | FXP_CB_COMMAND_SF | 1635 FXP_CB_COMMAND_S); 1636 else 1637 txp->tx_cb->cb_command = 1638 htole16(sc->tx_cmd | FXP_CB_COMMAND_SF | 1639 FXP_CB_COMMAND_S | FXP_CB_COMMAND_I); 1640 if ((m->m_pkthdr.csum_flags & CSUM_TSO) == 0) 1641 txp->tx_cb->tx_threshold = tx_threshold; 1642 1643 /* 1644 * Advance the end of list forward. 1645 */ 1646 sc->fxp_desc.tx_last->tx_cb->cb_command &= htole16(~FXP_CB_COMMAND_S); 1647 sc->fxp_desc.tx_last = txp; 1648 1649 /* 1650 * Advance the beginning of the list forward if there are 1651 * no other packets queued (when nothing is queued, tx_first 1652 * sits on the last TxCB that was sent out). 1653 */ 1654 if (sc->tx_queued == 0) 1655 sc->fxp_desc.tx_first = txp; 1656 1657 sc->tx_queued++; 1658 1659 return (0); 1660 } 1661 1662 #ifdef DEVICE_POLLING 1663 static poll_handler_t fxp_poll; 1664 1665 static int 1666 fxp_poll(if_t ifp, enum poll_cmd cmd, int count) 1667 { 1668 struct fxp_softc *sc = if_getsoftc(ifp); 1669 uint8_t statack; 1670 int rx_npkts = 0; 1671 1672 FXP_LOCK(sc); 1673 if (!(if_getdrvflags(ifp) & IFF_DRV_RUNNING)) { 1674 FXP_UNLOCK(sc); 1675 return (rx_npkts); 1676 } 1677 1678 statack = FXP_SCB_STATACK_CXTNO | FXP_SCB_STATACK_CNA | 1679 FXP_SCB_STATACK_FR; 1680 if (cmd == POLL_AND_CHECK_STATUS) { 1681 uint8_t tmp; 1682 1683 tmp = CSR_READ_1(sc, FXP_CSR_SCB_STATACK); 1684 if (tmp == 0xff || tmp == 0) { 1685 FXP_UNLOCK(sc); 1686 return (rx_npkts); /* nothing to do */ 1687 } 1688 tmp &= ~statack; 1689 /* ack what we can */ 1690 if (tmp != 0) 1691 CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, tmp); 1692 statack |= tmp; 1693 } 1694 rx_npkts = fxp_intr_body(sc, ifp, statack, count); 1695 FXP_UNLOCK(sc); 1696 return (rx_npkts); 1697 } 1698 #endif /* DEVICE_POLLING */ 1699 1700 /* 1701 * Process interface interrupts. 1702 */ 1703 static void 1704 fxp_intr(void *xsc) 1705 { 1706 struct fxp_softc *sc = xsc; 1707 if_t ifp = sc->ifp; 1708 uint8_t statack; 1709 1710 FXP_LOCK(sc); 1711 if (sc->suspended) { 1712 FXP_UNLOCK(sc); 1713 return; 1714 } 1715 1716 #ifdef DEVICE_POLLING 1717 if (if_getcapenable(ifp) & IFCAP_POLLING) { 1718 FXP_UNLOCK(sc); 1719 return; 1720 } 1721 #endif 1722 while ((statack = CSR_READ_1(sc, FXP_CSR_SCB_STATACK)) != 0) { 1723 /* 1724 * It should not be possible to have all bits set; the 1725 * FXP_SCB_INTR_SWI bit always returns 0 on a read. If 1726 * all bits are set, this may indicate that the card has 1727 * been physically ejected, so ignore it. 1728 */ 1729 if (statack == 0xff) { 1730 FXP_UNLOCK(sc); 1731 return; 1732 } 1733 1734 /* 1735 * First ACK all the interrupts in this pass. 1736 */ 1737 CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, statack); 1738 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) 1739 fxp_intr_body(sc, ifp, statack, -1); 1740 } 1741 FXP_UNLOCK(sc); 1742 } 1743 1744 static void 1745 fxp_txeof(struct fxp_softc *sc) 1746 { 1747 if_t ifp; 1748 struct fxp_tx *txp; 1749 1750 ifp = sc->ifp; 1751 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, 1752 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1753 for (txp = sc->fxp_desc.tx_first; sc->tx_queued && 1754 (le16toh(txp->tx_cb->cb_status) & FXP_CB_STATUS_C) != 0; 1755 txp = txp->tx_next) { 1756 if (txp->tx_mbuf != NULL) { 1757 bus_dmamap_sync(sc->fxp_txmtag, txp->tx_map, 1758 BUS_DMASYNC_POSTWRITE); 1759 bus_dmamap_unload(sc->fxp_txmtag, txp->tx_map); 1760 m_freem(txp->tx_mbuf); 1761 txp->tx_mbuf = NULL; 1762 /* clear this to reset csum offload bits */ 1763 txp->tx_cb->tbd[0].tb_addr = 0; 1764 } 1765 sc->tx_queued--; 1766 if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE); 1767 } 1768 sc->fxp_desc.tx_first = txp; 1769 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, 1770 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1771 if (sc->tx_queued == 0) 1772 sc->watchdog_timer = 0; 1773 } 1774 1775 static void 1776 fxp_rxcsum(struct fxp_softc *sc, if_t ifp, struct mbuf *m, 1777 uint16_t status, int pos) 1778 { 1779 struct ether_header *eh; 1780 struct ip *ip; 1781 struct udphdr *uh; 1782 int32_t hlen, len, pktlen, temp32; 1783 uint16_t csum, *opts; 1784 1785 if ((sc->flags & FXP_FLAG_82559_RXCSUM) == 0) { 1786 if ((status & FXP_RFA_STATUS_PARSE) != 0) { 1787 if (status & FXP_RFDX_CS_IP_CSUM_BIT_VALID) 1788 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 1789 if (status & FXP_RFDX_CS_IP_CSUM_VALID) 1790 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 1791 if ((status & FXP_RFDX_CS_TCPUDP_CSUM_BIT_VALID) && 1792 (status & FXP_RFDX_CS_TCPUDP_CSUM_VALID)) { 1793 m->m_pkthdr.csum_flags |= CSUM_DATA_VALID | 1794 CSUM_PSEUDO_HDR; 1795 m->m_pkthdr.csum_data = 0xffff; 1796 } 1797 } 1798 return; 1799 } 1800 1801 pktlen = m->m_pkthdr.len; 1802 if (pktlen < sizeof(struct ether_header) + sizeof(struct ip)) 1803 return; 1804 eh = mtod(m, struct ether_header *); 1805 if (eh->ether_type != htons(ETHERTYPE_IP)) 1806 return; 1807 ip = (struct ip *)(eh + 1); 1808 if (ip->ip_v != IPVERSION) 1809 return; 1810 1811 hlen = ip->ip_hl << 2; 1812 pktlen -= sizeof(struct ether_header); 1813 if (hlen < sizeof(struct ip)) 1814 return; 1815 if (ntohs(ip->ip_len) < hlen) 1816 return; 1817 if (ntohs(ip->ip_len) != pktlen) 1818 return; 1819 if (ip->ip_off & htons(IP_MF | IP_OFFMASK)) 1820 return; /* can't handle fragmented packet */ 1821 1822 switch (ip->ip_p) { 1823 case IPPROTO_TCP: 1824 if (pktlen < (hlen + sizeof(struct tcphdr))) 1825 return; 1826 break; 1827 case IPPROTO_UDP: 1828 if (pktlen < (hlen + sizeof(struct udphdr))) 1829 return; 1830 uh = (struct udphdr *)((caddr_t)ip + hlen); 1831 if (uh->uh_sum == 0) 1832 return; /* no checksum */ 1833 break; 1834 default: 1835 return; 1836 } 1837 /* Extract computed checksum. */ 1838 csum = be16dec(mtod(m, char *) + pos); 1839 /* checksum fixup for IP options */ 1840 len = hlen - sizeof(struct ip); 1841 if (len > 0) { 1842 opts = (uint16_t *)(ip + 1); 1843 for (; len > 0; len -= sizeof(uint16_t), opts++) { 1844 temp32 = csum - *opts; 1845 temp32 = (temp32 >> 16) + (temp32 & 65535); 1846 csum = temp32 & 65535; 1847 } 1848 } 1849 m->m_pkthdr.csum_flags |= CSUM_DATA_VALID; 1850 m->m_pkthdr.csum_data = csum; 1851 } 1852 1853 static int 1854 fxp_intr_body(struct fxp_softc *sc, if_t ifp, uint8_t statack, 1855 int count) 1856 { 1857 struct mbuf *m; 1858 struct fxp_rx *rxp; 1859 struct fxp_rfa *rfa; 1860 int rnr = (statack & FXP_SCB_STATACK_RNR) ? 1 : 0; 1861 int rx_npkts; 1862 uint16_t status; 1863 1864 rx_npkts = 0; 1865 FXP_LOCK_ASSERT(sc, MA_OWNED); 1866 1867 if (rnr) 1868 sc->rnr++; 1869 #ifdef DEVICE_POLLING 1870 /* Pick up a deferred RNR condition if `count' ran out last time. */ 1871 if (sc->flags & FXP_FLAG_DEFERRED_RNR) { 1872 sc->flags &= ~FXP_FLAG_DEFERRED_RNR; 1873 rnr = 1; 1874 } 1875 #endif 1876 1877 /* 1878 * Free any finished transmit mbuf chains. 1879 * 1880 * Handle the CNA event likt a CXTNO event. It used to 1881 * be that this event (control unit not ready) was not 1882 * encountered, but it is now with the SMPng modifications. 1883 * The exact sequence of events that occur when the interface 1884 * is brought up are different now, and if this event 1885 * goes unhandled, the configuration/rxfilter setup sequence 1886 * can stall for several seconds. The result is that no 1887 * packets go out onto the wire for about 5 to 10 seconds 1888 * after the interface is ifconfig'ed for the first time. 1889 */ 1890 if (statack & (FXP_SCB_STATACK_CXTNO | FXP_SCB_STATACK_CNA)) 1891 fxp_txeof(sc); 1892 1893 /* 1894 * Try to start more packets transmitting. 1895 */ 1896 if (!if_sendq_empty(ifp)) 1897 fxp_start_body(ifp); 1898 1899 /* 1900 * Just return if nothing happened on the receive side. 1901 */ 1902 if (!rnr && (statack & FXP_SCB_STATACK_FR) == 0) 1903 return (rx_npkts); 1904 1905 /* 1906 * Process receiver interrupts. If a no-resource (RNR) 1907 * condition exists, get whatever packets we can and 1908 * re-start the receiver. 1909 * 1910 * When using polling, we do not process the list to completion, 1911 * so when we get an RNR interrupt we must defer the restart 1912 * until we hit the last buffer with the C bit set. 1913 * If we run out of cycles and rfa_headm has the C bit set, 1914 * record the pending RNR in the FXP_FLAG_DEFERRED_RNR flag so 1915 * that the info will be used in the subsequent polling cycle. 1916 */ 1917 for (;;) { 1918 rxp = sc->fxp_desc.rx_head; 1919 m = rxp->rx_mbuf; 1920 rfa = (struct fxp_rfa *)(m->m_ext.ext_buf + 1921 RFA_ALIGNMENT_FUDGE); 1922 bus_dmamap_sync(sc->fxp_rxmtag, rxp->rx_map, 1923 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1924 1925 #ifdef DEVICE_POLLING /* loop at most count times if count >=0 */ 1926 if (count >= 0 && count-- == 0) { 1927 if (rnr) { 1928 /* Defer RNR processing until the next time. */ 1929 sc->flags |= FXP_FLAG_DEFERRED_RNR; 1930 rnr = 0; 1931 } 1932 break; 1933 } 1934 #endif /* DEVICE_POLLING */ 1935 1936 status = le16toh(rfa->rfa_status); 1937 if ((status & FXP_RFA_STATUS_C) == 0) 1938 break; 1939 1940 if ((status & FXP_RFA_STATUS_RNR) != 0) 1941 rnr++; 1942 /* 1943 * Advance head forward. 1944 */ 1945 sc->fxp_desc.rx_head = rxp->rx_next; 1946 1947 /* 1948 * Add a new buffer to the receive chain. 1949 * If this fails, the old buffer is recycled 1950 * instead. 1951 */ 1952 if (fxp_new_rfabuf(sc, rxp) == 0) { 1953 int total_len; 1954 1955 /* 1956 * Fetch packet length (the top 2 bits of 1957 * actual_size are flags set by the controller 1958 * upon completion), and drop the packet in case 1959 * of bogus length or CRC errors. 1960 */ 1961 total_len = le16toh(rfa->actual_size) & 0x3fff; 1962 if ((sc->flags & FXP_FLAG_82559_RXCSUM) != 0 && 1963 (if_getcapenable(ifp) & IFCAP_RXCSUM) != 0) { 1964 /* Adjust for appended checksum bytes. */ 1965 total_len -= 2; 1966 } 1967 if (total_len < (int)sizeof(struct ether_header) || 1968 total_len > (MCLBYTES - RFA_ALIGNMENT_FUDGE - 1969 sc->rfa_size) || 1970 status & (FXP_RFA_STATUS_CRC | 1971 FXP_RFA_STATUS_ALIGN | FXP_RFA_STATUS_OVERRUN)) { 1972 m_freem(m); 1973 fxp_add_rfabuf(sc, rxp); 1974 continue; 1975 } 1976 1977 m->m_pkthdr.len = m->m_len = total_len; 1978 if_setrcvif(m, ifp); 1979 1980 /* Do IP checksum checking. */ 1981 if ((if_getcapenable(ifp) & IFCAP_RXCSUM) != 0) 1982 fxp_rxcsum(sc, ifp, m, status, total_len); 1983 if ((if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING) != 0 && 1984 (status & FXP_RFA_STATUS_VLAN) != 0) { 1985 m->m_pkthdr.ether_vtag = 1986 ntohs(rfa->rfax_vlan_id); 1987 m->m_flags |= M_VLANTAG; 1988 } 1989 /* 1990 * Drop locks before calling if_input() since it 1991 * may re-enter fxp_start() in the netisr case. 1992 * This would result in a lock reversal. Better 1993 * performance might be obtained by chaining all 1994 * packets received, dropping the lock, and then 1995 * calling if_input() on each one. 1996 */ 1997 FXP_UNLOCK(sc); 1998 if_input(ifp, m); 1999 FXP_LOCK(sc); 2000 rx_npkts++; 2001 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) == 0) 2002 return (rx_npkts); 2003 } else { 2004 /* Reuse RFA and loaded DMA map. */ 2005 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1); 2006 fxp_discard_rfabuf(sc, rxp); 2007 } 2008 fxp_add_rfabuf(sc, rxp); 2009 } 2010 if (rnr) { 2011 fxp_scb_wait(sc); 2012 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 2013 sc->fxp_desc.rx_head->rx_addr); 2014 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_START); 2015 } 2016 return (rx_npkts); 2017 } 2018 2019 static void 2020 fxp_update_stats(struct fxp_softc *sc) 2021 { 2022 if_t ifp = sc->ifp; 2023 struct fxp_stats *sp = sc->fxp_stats; 2024 struct fxp_hwstats *hsp; 2025 uint32_t *status; 2026 2027 FXP_LOCK_ASSERT(sc, MA_OWNED); 2028 2029 bus_dmamap_sync(sc->fxp_stag, sc->fxp_smap, 2030 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2031 /* Update statistical counters. */ 2032 if (sc->revision >= FXP_REV_82559_A0) 2033 status = &sp->completion_status; 2034 else if (sc->revision >= FXP_REV_82558_A4) 2035 status = (uint32_t *)&sp->tx_tco; 2036 else 2037 status = &sp->tx_pause; 2038 if (*status == htole32(FXP_STATS_DR_COMPLETE)) { 2039 hsp = &sc->fxp_hwstats; 2040 hsp->tx_good += le32toh(sp->tx_good); 2041 hsp->tx_maxcols += le32toh(sp->tx_maxcols); 2042 hsp->tx_latecols += le32toh(sp->tx_latecols); 2043 hsp->tx_underruns += le32toh(sp->tx_underruns); 2044 hsp->tx_lostcrs += le32toh(sp->tx_lostcrs); 2045 hsp->tx_deffered += le32toh(sp->tx_deffered); 2046 hsp->tx_single_collisions += le32toh(sp->tx_single_collisions); 2047 hsp->tx_multiple_collisions += 2048 le32toh(sp->tx_multiple_collisions); 2049 hsp->tx_total_collisions += le32toh(sp->tx_total_collisions); 2050 hsp->rx_good += le32toh(sp->rx_good); 2051 hsp->rx_crc_errors += le32toh(sp->rx_crc_errors); 2052 hsp->rx_alignment_errors += le32toh(sp->rx_alignment_errors); 2053 hsp->rx_rnr_errors += le32toh(sp->rx_rnr_errors); 2054 hsp->rx_overrun_errors += le32toh(sp->rx_overrun_errors); 2055 hsp->rx_cdt_errors += le32toh(sp->rx_cdt_errors); 2056 hsp->rx_shortframes += le32toh(sp->rx_shortframes); 2057 hsp->tx_pause += le32toh(sp->tx_pause); 2058 hsp->rx_pause += le32toh(sp->rx_pause); 2059 hsp->rx_controls += le32toh(sp->rx_controls); 2060 hsp->tx_tco += le16toh(sp->tx_tco); 2061 hsp->rx_tco += le16toh(sp->rx_tco); 2062 2063 if_inc_counter(ifp, IFCOUNTER_OPACKETS, le32toh(sp->tx_good)); 2064 if_inc_counter(ifp, IFCOUNTER_COLLISIONS, 2065 le32toh(sp->tx_total_collisions)); 2066 if (sp->rx_good) { 2067 if_inc_counter(ifp, IFCOUNTER_IPACKETS, 2068 le32toh(sp->rx_good)); 2069 sc->rx_idle_secs = 0; 2070 } else if (sc->flags & FXP_FLAG_RXBUG) { 2071 /* 2072 * Receiver's been idle for another second. 2073 */ 2074 sc->rx_idle_secs++; 2075 } 2076 if_inc_counter(ifp, IFCOUNTER_IERRORS, 2077 le32toh(sp->rx_crc_errors) + 2078 le32toh(sp->rx_alignment_errors) + 2079 le32toh(sp->rx_rnr_errors) + 2080 le32toh(sp->rx_overrun_errors)); 2081 /* 2082 * If any transmit underruns occurred, bump up the transmit 2083 * threshold by another 512 bytes (64 * 8). 2084 */ 2085 if (sp->tx_underruns) { 2086 if_inc_counter(ifp, IFCOUNTER_OERRORS, 2087 le32toh(sp->tx_underruns)); 2088 if (tx_threshold < 192) 2089 tx_threshold += 64; 2090 } 2091 *status = 0; 2092 bus_dmamap_sync(sc->fxp_stag, sc->fxp_smap, 2093 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2094 } 2095 } 2096 2097 /* 2098 * Update packet in/out/collision statistics. The i82557 doesn't 2099 * allow you to access these counters without doing a fairly 2100 * expensive DMA to get _all_ of the statistics it maintains, so 2101 * we do this operation here only once per second. The statistics 2102 * counters in the kernel are updated from the previous dump-stats 2103 * DMA and then a new dump-stats DMA is started. The on-chip 2104 * counters are zeroed when the DMA completes. If we can't start 2105 * the DMA immediately, we don't wait - we just prepare to read 2106 * them again next time. 2107 */ 2108 static void 2109 fxp_tick(void *xsc) 2110 { 2111 struct fxp_softc *sc = xsc; 2112 if_t ifp = sc->ifp; 2113 2114 FXP_LOCK_ASSERT(sc, MA_OWNED); 2115 2116 /* Update statistical counters. */ 2117 fxp_update_stats(sc); 2118 2119 /* 2120 * Release any xmit buffers that have completed DMA. This isn't 2121 * strictly necessary to do here, but it's advantagous for mbufs 2122 * with external storage to be released in a timely manner rather 2123 * than being defered for a potentially long time. This limits 2124 * the delay to a maximum of one second. 2125 */ 2126 fxp_txeof(sc); 2127 2128 /* 2129 * If we haven't received any packets in FXP_MAC_RX_IDLE seconds, 2130 * then assume the receiver has locked up and attempt to clear 2131 * the condition by reprogramming the multicast filter. This is 2132 * a work-around for a bug in the 82557 where the receiver locks 2133 * up if it gets certain types of garbage in the synchronization 2134 * bits prior to the packet header. This bug is supposed to only 2135 * occur in 10Mbps mode, but has been seen to occur in 100Mbps 2136 * mode as well (perhaps due to a 10/100 speed transition). 2137 */ 2138 if (sc->rx_idle_secs > FXP_MAX_RX_IDLE) { 2139 sc->rx_idle_secs = 0; 2140 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) { 2141 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 2142 fxp_init_body(sc, 1); 2143 } 2144 return; 2145 } 2146 /* 2147 * If there is no pending command, start another stats 2148 * dump. Otherwise punt for now. 2149 */ 2150 if (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) == 0) { 2151 /* 2152 * Start another stats dump. 2153 */ 2154 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_DUMPRESET); 2155 } 2156 if (sc->miibus != NULL) 2157 mii_tick(device_get_softc(sc->miibus)); 2158 2159 /* 2160 * Check that chip hasn't hung. 2161 */ 2162 fxp_watchdog(sc); 2163 2164 /* 2165 * Schedule another timeout one second from now. 2166 */ 2167 callout_reset(&sc->stat_ch, hz, fxp_tick, sc); 2168 } 2169 2170 /* 2171 * Stop the interface. Cancels the statistics updater and resets 2172 * the interface. 2173 */ 2174 static void 2175 fxp_stop(struct fxp_softc *sc) 2176 { 2177 if_t ifp = sc->ifp; 2178 struct fxp_tx *txp; 2179 int i; 2180 2181 if_setdrvflagbits(ifp, 0, (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)); 2182 sc->watchdog_timer = 0; 2183 2184 /* 2185 * Cancel stats updater. 2186 */ 2187 callout_stop(&sc->stat_ch); 2188 2189 /* 2190 * Preserve PCI configuration, configure, IA/multicast 2191 * setup and put RU and CU into idle state. 2192 */ 2193 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET); 2194 DELAY(50); 2195 /* Disable interrupts. */ 2196 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE); 2197 2198 fxp_update_stats(sc); 2199 2200 /* 2201 * Release any xmit buffers. 2202 */ 2203 txp = sc->fxp_desc.tx_list; 2204 for (i = 0; i < FXP_NTXCB; i++) { 2205 if (txp[i].tx_mbuf != NULL) { 2206 bus_dmamap_sync(sc->fxp_txmtag, txp[i].tx_map, 2207 BUS_DMASYNC_POSTWRITE); 2208 bus_dmamap_unload(sc->fxp_txmtag, txp[i].tx_map); 2209 m_freem(txp[i].tx_mbuf); 2210 txp[i].tx_mbuf = NULL; 2211 /* clear this to reset csum offload bits */ 2212 txp[i].tx_cb->tbd[0].tb_addr = 0; 2213 } 2214 } 2215 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, 2216 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2217 sc->tx_queued = 0; 2218 } 2219 2220 /* 2221 * Watchdog/transmission transmit timeout handler. Called when a 2222 * transmission is started on the interface, but no interrupt is 2223 * received before the timeout. This usually indicates that the 2224 * card has wedged for some reason. 2225 */ 2226 static void 2227 fxp_watchdog(struct fxp_softc *sc) 2228 { 2229 if_t ifp = sc->ifp; 2230 2231 FXP_LOCK_ASSERT(sc, MA_OWNED); 2232 2233 if (sc->watchdog_timer == 0 || --sc->watchdog_timer) 2234 return; 2235 2236 device_printf(sc->dev, "device timeout\n"); 2237 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 2238 2239 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 2240 fxp_init_body(sc, 1); 2241 } 2242 2243 /* 2244 * Acquire locks and then call the real initialization function. This 2245 * is necessary because ether_ioctl() calls if_init() and this would 2246 * result in mutex recursion if the mutex was held. 2247 */ 2248 static void 2249 fxp_init(void *xsc) 2250 { 2251 struct fxp_softc *sc = xsc; 2252 2253 FXP_LOCK(sc); 2254 fxp_init_body(sc, 1); 2255 FXP_UNLOCK(sc); 2256 } 2257 2258 /* 2259 * Perform device initialization. This routine must be called with the 2260 * softc lock held. 2261 */ 2262 static void 2263 fxp_init_body(struct fxp_softc *sc, int setmedia) 2264 { 2265 if_t ifp = sc->ifp; 2266 struct mii_data *mii; 2267 struct fxp_cb_config *cbp; 2268 struct fxp_cb_ias *cb_ias; 2269 struct fxp_cb_tx *tcbp; 2270 struct fxp_tx *txp; 2271 int i, prm; 2272 2273 FXP_LOCK_ASSERT(sc, MA_OWNED); 2274 2275 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) 2276 return; 2277 2278 /* 2279 * Cancel any pending I/O 2280 */ 2281 fxp_stop(sc); 2282 2283 /* 2284 * Issue software reset, which also unloads the microcode. 2285 */ 2286 sc->flags &= ~FXP_FLAG_UCODE; 2287 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SOFTWARE_RESET); 2288 DELAY(50); 2289 2290 prm = (if_getflags(ifp) & IFF_PROMISC) ? 1 : 0; 2291 2292 /* 2293 * Initialize base of CBL and RFA memory. Loading with zero 2294 * sets it up for regular linear addressing. 2295 */ 2296 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 0); 2297 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_BASE); 2298 2299 fxp_scb_wait(sc); 2300 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_BASE); 2301 2302 /* 2303 * Initialize base of dump-stats buffer. 2304 */ 2305 fxp_scb_wait(sc); 2306 bzero(sc->fxp_stats, sizeof(struct fxp_stats)); 2307 bus_dmamap_sync(sc->fxp_stag, sc->fxp_smap, 2308 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2309 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->stats_addr); 2310 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_DUMP_ADR); 2311 2312 /* 2313 * Attempt to load microcode if requested. 2314 * For ICH based controllers do not load microcode. 2315 */ 2316 if (sc->ident->ich == 0) { 2317 if (if_getflags(ifp) & IFF_LINK0 && 2318 (sc->flags & FXP_FLAG_UCODE) == 0) 2319 fxp_load_ucode(sc); 2320 } 2321 2322 /* 2323 * Set IFF_ALLMULTI status. It's needed in configure action 2324 * command. 2325 */ 2326 fxp_mc_addrs(sc); 2327 2328 /* 2329 * We temporarily use memory that contains the TxCB list to 2330 * construct the config CB. The TxCB list memory is rebuilt 2331 * later. 2332 */ 2333 cbp = (struct fxp_cb_config *)sc->fxp_desc.cbl_list; 2334 2335 /* 2336 * This bcopy is kind of disgusting, but there are a bunch of must be 2337 * zero and must be one bits in this structure and this is the easiest 2338 * way to initialize them all to proper values. 2339 */ 2340 bcopy(fxp_cb_config_template, cbp, sizeof(fxp_cb_config_template)); 2341 2342 cbp->cb_status = 0; 2343 cbp->cb_command = htole16(FXP_CB_COMMAND_CONFIG | 2344 FXP_CB_COMMAND_EL); 2345 cbp->link_addr = 0xffffffff; /* (no) next command */ 2346 cbp->byte_count = sc->flags & FXP_FLAG_EXT_RFA ? 32 : 22; 2347 cbp->rx_fifo_limit = 8; /* rx fifo threshold (32 bytes) */ 2348 cbp->tx_fifo_limit = 0; /* tx fifo threshold (0 bytes) */ 2349 cbp->adaptive_ifs = 0; /* (no) adaptive interframe spacing */ 2350 cbp->mwi_enable = sc->flags & FXP_FLAG_MWI_ENABLE ? 1 : 0; 2351 cbp->type_enable = 0; /* actually reserved */ 2352 cbp->read_align_en = sc->flags & FXP_FLAG_READ_ALIGN ? 1 : 0; 2353 cbp->end_wr_on_cl = sc->flags & FXP_FLAG_WRITE_ALIGN ? 1 : 0; 2354 cbp->rx_dma_bytecount = 0; /* (no) rx DMA max */ 2355 cbp->tx_dma_bytecount = 0; /* (no) tx DMA max */ 2356 cbp->dma_mbce = 0; /* (disable) dma max counters */ 2357 cbp->late_scb = 0; /* (don't) defer SCB update */ 2358 cbp->direct_dma_dis = 1; /* disable direct rcv dma mode */ 2359 cbp->tno_int_or_tco_en =0; /* (disable) tx not okay interrupt */ 2360 cbp->ci_int = 1; /* interrupt on CU idle */ 2361 cbp->ext_txcb_dis = sc->flags & FXP_FLAG_EXT_TXCB ? 0 : 1; 2362 cbp->ext_stats_dis = 1; /* disable extended counters */ 2363 cbp->keep_overrun_rx = 0; /* don't pass overrun frames to host */ 2364 cbp->save_bf = sc->flags & FXP_FLAG_SAVE_BAD ? 1 : prm; 2365 cbp->disc_short_rx = !prm; /* discard short packets */ 2366 cbp->underrun_retry = 1; /* retry mode (once) on DMA underrun */ 2367 cbp->two_frames = 0; /* do not limit FIFO to 2 frames */ 2368 cbp->dyn_tbd = sc->flags & FXP_FLAG_EXT_RFA ? 1 : 0; 2369 cbp->ext_rfa = sc->flags & FXP_FLAG_EXT_RFA ? 1 : 0; 2370 cbp->mediatype = sc->flags & FXP_FLAG_SERIAL_MEDIA ? 0 : 1; 2371 cbp->csma_dis = 0; /* (don't) disable link */ 2372 cbp->tcp_udp_cksum = ((sc->flags & FXP_FLAG_82559_RXCSUM) != 0 && 2373 (if_getcapenable(ifp) & IFCAP_RXCSUM) != 0) ? 1 : 0; 2374 cbp->vlan_tco = 0; /* (don't) enable vlan wakeup */ 2375 cbp->link_wake_en = 0; /* (don't) assert PME# on link change */ 2376 cbp->arp_wake_en = 0; /* (don't) assert PME# on arp */ 2377 cbp->mc_wake_en = 0; /* (don't) enable PME# on mcmatch */ 2378 cbp->nsai = 1; /* (don't) disable source addr insert */ 2379 cbp->preamble_length = 2; /* (7 byte) preamble */ 2380 cbp->loopback = 0; /* (don't) loopback */ 2381 cbp->linear_priority = 0; /* (normal CSMA/CD operation) */ 2382 cbp->linear_pri_mode = 0; /* (wait after xmit only) */ 2383 cbp->interfrm_spacing = 6; /* (96 bits of) interframe spacing */ 2384 cbp->promiscuous = prm; /* promiscuous mode */ 2385 cbp->bcast_disable = 0; /* (don't) disable broadcasts */ 2386 cbp->wait_after_win = 0; /* (don't) enable modified backoff alg*/ 2387 cbp->ignore_ul = 0; /* consider U/L bit in IA matching */ 2388 cbp->crc16_en = 0; /* (don't) enable crc-16 algorithm */ 2389 cbp->crscdt = sc->flags & FXP_FLAG_SERIAL_MEDIA ? 1 : 0; 2390 2391 cbp->stripping = !prm; /* truncate rx packet to byte count */ 2392 cbp->padding = 1; /* (do) pad short tx packets */ 2393 cbp->rcv_crc_xfer = 0; /* (don't) xfer CRC to host */ 2394 cbp->long_rx_en = sc->flags & FXP_FLAG_LONG_PKT_EN ? 1 : 0; 2395 cbp->ia_wake_en = 0; /* (don't) wake up on address match */ 2396 cbp->magic_pkt_dis = sc->flags & FXP_FLAG_WOL ? 0 : 1; 2397 cbp->force_fdx = 0; /* (don't) force full duplex */ 2398 cbp->fdx_pin_en = 1; /* (enable) FDX# pin */ 2399 cbp->multi_ia = 0; /* (don't) accept multiple IAs */ 2400 cbp->mc_all = if_getflags(ifp) & IFF_ALLMULTI ? 1 : prm; 2401 cbp->gamla_rx = sc->flags & FXP_FLAG_EXT_RFA ? 1 : 0; 2402 cbp->vlan_strip_en = ((sc->flags & FXP_FLAG_EXT_RFA) != 0 && 2403 (if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING) != 0) ? 1 : 0; 2404 2405 if (sc->revision == FXP_REV_82557) { 2406 /* 2407 * The 82557 has no hardware flow control, the values 2408 * below are the defaults for the chip. 2409 */ 2410 cbp->fc_delay_lsb = 0; 2411 cbp->fc_delay_msb = 0x40; 2412 cbp->pri_fc_thresh = 3; 2413 cbp->tx_fc_dis = 0; 2414 cbp->rx_fc_restop = 0; 2415 cbp->rx_fc_restart = 0; 2416 cbp->fc_filter = 0; 2417 cbp->pri_fc_loc = 1; 2418 } else { 2419 /* Set pause RX FIFO threshold to 1KB. */ 2420 CSR_WRITE_1(sc, FXP_CSR_FC_THRESH, 1); 2421 /* Set pause time. */ 2422 cbp->fc_delay_lsb = 0xff; 2423 cbp->fc_delay_msb = 0xff; 2424 cbp->pri_fc_thresh = 3; 2425 mii = device_get_softc(sc->miibus); 2426 if ((IFM_OPTIONS(mii->mii_media_active) & 2427 IFM_ETH_TXPAUSE) != 0) 2428 /* enable transmit FC */ 2429 cbp->tx_fc_dis = 0; 2430 else 2431 /* disable transmit FC */ 2432 cbp->tx_fc_dis = 1; 2433 if ((IFM_OPTIONS(mii->mii_media_active) & 2434 IFM_ETH_RXPAUSE) != 0) { 2435 /* enable FC restart/restop frames */ 2436 cbp->rx_fc_restart = 1; 2437 cbp->rx_fc_restop = 1; 2438 } else { 2439 /* disable FC restart/restop frames */ 2440 cbp->rx_fc_restart = 0; 2441 cbp->rx_fc_restop = 0; 2442 } 2443 cbp->fc_filter = !prm; /* drop FC frames to host */ 2444 cbp->pri_fc_loc = 1; /* FC pri location (byte31) */ 2445 } 2446 2447 /* Enable 82558 and 82559 extended statistics functionality. */ 2448 if (sc->revision >= FXP_REV_82558_A4) { 2449 if (sc->revision >= FXP_REV_82559_A0) { 2450 /* 2451 * Extend configuration table size to 32 2452 * to include TCO configuration. 2453 */ 2454 cbp->byte_count = 32; 2455 cbp->ext_stats_dis = 1; 2456 /* Enable TCO stats. */ 2457 cbp->tno_int_or_tco_en = 1; 2458 cbp->gamla_rx = 1; 2459 } else 2460 cbp->ext_stats_dis = 0; 2461 } 2462 2463 /* 2464 * Start the config command/DMA. 2465 */ 2466 fxp_scb_wait(sc); 2467 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, 2468 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2469 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->fxp_desc.cbl_addr); 2470 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2471 /* ...and wait for it to complete. */ 2472 fxp_dma_wait(sc, &cbp->cb_status, sc->cbl_tag, sc->cbl_map); 2473 2474 /* 2475 * Now initialize the station address. Temporarily use the TxCB 2476 * memory area like we did above for the config CB. 2477 */ 2478 cb_ias = (struct fxp_cb_ias *)sc->fxp_desc.cbl_list; 2479 cb_ias->cb_status = 0; 2480 cb_ias->cb_command = htole16(FXP_CB_COMMAND_IAS | FXP_CB_COMMAND_EL); 2481 cb_ias->link_addr = 0xffffffff; 2482 bcopy(if_getlladdr(sc->ifp), cb_ias->macaddr, ETHER_ADDR_LEN); 2483 2484 /* 2485 * Start the IAS (Individual Address Setup) command/DMA. 2486 */ 2487 fxp_scb_wait(sc); 2488 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, 2489 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2490 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->fxp_desc.cbl_addr); 2491 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2492 /* ...and wait for it to complete. */ 2493 fxp_dma_wait(sc, &cb_ias->cb_status, sc->cbl_tag, sc->cbl_map); 2494 2495 /* 2496 * Initialize the multicast address list. 2497 */ 2498 fxp_mc_setup(sc); 2499 2500 /* 2501 * Initialize transmit control block (TxCB) list. 2502 */ 2503 txp = sc->fxp_desc.tx_list; 2504 tcbp = sc->fxp_desc.cbl_list; 2505 bzero(tcbp, FXP_TXCB_SZ); 2506 for (i = 0; i < FXP_NTXCB; i++) { 2507 txp[i].tx_mbuf = NULL; 2508 tcbp[i].cb_status = htole16(FXP_CB_STATUS_C | FXP_CB_STATUS_OK); 2509 tcbp[i].cb_command = htole16(FXP_CB_COMMAND_NOP); 2510 tcbp[i].link_addr = htole32(sc->fxp_desc.cbl_addr + 2511 (((i + 1) & FXP_TXCB_MASK) * sizeof(struct fxp_cb_tx))); 2512 if (sc->flags & FXP_FLAG_EXT_TXCB) 2513 tcbp[i].tbd_array_addr = 2514 htole32(FXP_TXCB_DMA_ADDR(sc, &tcbp[i].tbd[2])); 2515 else 2516 tcbp[i].tbd_array_addr = 2517 htole32(FXP_TXCB_DMA_ADDR(sc, &tcbp[i].tbd[0])); 2518 txp[i].tx_next = &txp[(i + 1) & FXP_TXCB_MASK]; 2519 } 2520 /* 2521 * Set the suspend flag on the first TxCB and start the control 2522 * unit. It will execute the NOP and then suspend. 2523 */ 2524 tcbp->cb_command = htole16(FXP_CB_COMMAND_NOP | FXP_CB_COMMAND_S); 2525 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, 2526 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2527 sc->fxp_desc.tx_first = sc->fxp_desc.tx_last = txp; 2528 sc->tx_queued = 1; 2529 2530 fxp_scb_wait(sc); 2531 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->fxp_desc.cbl_addr); 2532 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2533 2534 /* 2535 * Initialize receiver buffer area - RFA. 2536 */ 2537 fxp_scb_wait(sc); 2538 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->fxp_desc.rx_head->rx_addr); 2539 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_START); 2540 2541 if (sc->miibus != NULL && setmedia != 0) 2542 mii_mediachg(device_get_softc(sc->miibus)); 2543 2544 if_setdrvflagbits(ifp, IFF_DRV_RUNNING, IFF_DRV_OACTIVE); 2545 2546 /* 2547 * Enable interrupts. 2548 */ 2549 #ifdef DEVICE_POLLING 2550 /* 2551 * ... but only do that if we are not polling. And because (presumably) 2552 * the default is interrupts on, we need to disable them explicitly! 2553 */ 2554 if (if_getcapenable(ifp) & IFCAP_POLLING ) 2555 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE); 2556 else 2557 #endif /* DEVICE_POLLING */ 2558 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, 0); 2559 2560 /* 2561 * Start stats updater. 2562 */ 2563 callout_reset(&sc->stat_ch, hz, fxp_tick, sc); 2564 } 2565 2566 static int 2567 fxp_serial_ifmedia_upd(if_t ifp) 2568 { 2569 2570 return (0); 2571 } 2572 2573 static void 2574 fxp_serial_ifmedia_sts(if_t ifp, struct ifmediareq *ifmr) 2575 { 2576 2577 ifmr->ifm_active = IFM_ETHER|IFM_MANUAL; 2578 } 2579 2580 /* 2581 * Change media according to request. 2582 */ 2583 static int 2584 fxp_ifmedia_upd(if_t ifp) 2585 { 2586 struct fxp_softc *sc = if_getsoftc(ifp); 2587 struct mii_data *mii; 2588 struct mii_softc *miisc; 2589 2590 mii = device_get_softc(sc->miibus); 2591 FXP_LOCK(sc); 2592 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 2593 PHY_RESET(miisc); 2594 mii_mediachg(mii); 2595 FXP_UNLOCK(sc); 2596 return (0); 2597 } 2598 2599 /* 2600 * Notify the world which media we're using. 2601 */ 2602 static void 2603 fxp_ifmedia_sts(if_t ifp, struct ifmediareq *ifmr) 2604 { 2605 struct fxp_softc *sc = if_getsoftc(ifp); 2606 struct mii_data *mii; 2607 2608 mii = device_get_softc(sc->miibus); 2609 FXP_LOCK(sc); 2610 mii_pollstat(mii); 2611 ifmr->ifm_active = mii->mii_media_active; 2612 ifmr->ifm_status = mii->mii_media_status; 2613 FXP_UNLOCK(sc); 2614 } 2615 2616 /* 2617 * Add a buffer to the end of the RFA buffer list. 2618 * Return 0 if successful, 1 for failure. A failure results in 2619 * reusing the RFA buffer. 2620 * The RFA struct is stuck at the beginning of mbuf cluster and the 2621 * data pointer is fixed up to point just past it. 2622 */ 2623 static int 2624 fxp_new_rfabuf(struct fxp_softc *sc, struct fxp_rx *rxp) 2625 { 2626 struct mbuf *m; 2627 struct fxp_rfa *rfa; 2628 bus_dmamap_t tmp_map; 2629 int error; 2630 2631 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 2632 if (m == NULL) 2633 return (ENOBUFS); 2634 2635 /* 2636 * Move the data pointer up so that the incoming data packet 2637 * will be 32-bit aligned. 2638 */ 2639 m->m_data += RFA_ALIGNMENT_FUDGE; 2640 2641 /* 2642 * Get a pointer to the base of the mbuf cluster and move 2643 * data start past it. 2644 */ 2645 rfa = mtod(m, struct fxp_rfa *); 2646 m->m_data += sc->rfa_size; 2647 rfa->size = htole16(MCLBYTES - sc->rfa_size - RFA_ALIGNMENT_FUDGE); 2648 2649 rfa->rfa_status = 0; 2650 rfa->rfa_control = htole16(FXP_RFA_CONTROL_EL); 2651 rfa->actual_size = 0; 2652 m->m_len = m->m_pkthdr.len = MCLBYTES - RFA_ALIGNMENT_FUDGE - 2653 sc->rfa_size; 2654 2655 /* 2656 * Initialize the rest of the RFA. Note that since the RFA 2657 * is misaligned, we cannot store values directly. We're thus 2658 * using the le32enc() function which handles endianness and 2659 * is also alignment-safe. 2660 */ 2661 le32enc(&rfa->link_addr, 0xffffffff); 2662 le32enc(&rfa->rbd_addr, 0xffffffff); 2663 2664 /* Map the RFA into DMA memory. */ 2665 error = bus_dmamap_load(sc->fxp_rxmtag, sc->spare_map, rfa, 2666 MCLBYTES - RFA_ALIGNMENT_FUDGE, fxp_dma_map_addr, 2667 &rxp->rx_addr, BUS_DMA_NOWAIT); 2668 if (error) { 2669 m_freem(m); 2670 return (error); 2671 } 2672 2673 if (rxp->rx_mbuf != NULL) 2674 bus_dmamap_unload(sc->fxp_rxmtag, rxp->rx_map); 2675 tmp_map = sc->spare_map; 2676 sc->spare_map = rxp->rx_map; 2677 rxp->rx_map = tmp_map; 2678 rxp->rx_mbuf = m; 2679 2680 bus_dmamap_sync(sc->fxp_rxmtag, rxp->rx_map, 2681 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2682 return (0); 2683 } 2684 2685 static void 2686 fxp_add_rfabuf(struct fxp_softc *sc, struct fxp_rx *rxp) 2687 { 2688 struct fxp_rfa *p_rfa; 2689 struct fxp_rx *p_rx; 2690 2691 /* 2692 * If there are other buffers already on the list, attach this 2693 * one to the end by fixing up the tail to point to this one. 2694 */ 2695 if (sc->fxp_desc.rx_head != NULL) { 2696 p_rx = sc->fxp_desc.rx_tail; 2697 p_rfa = (struct fxp_rfa *) 2698 (p_rx->rx_mbuf->m_ext.ext_buf + RFA_ALIGNMENT_FUDGE); 2699 p_rx->rx_next = rxp; 2700 le32enc(&p_rfa->link_addr, rxp->rx_addr); 2701 p_rfa->rfa_control = 0; 2702 bus_dmamap_sync(sc->fxp_rxmtag, p_rx->rx_map, 2703 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2704 } else { 2705 rxp->rx_next = NULL; 2706 sc->fxp_desc.rx_head = rxp; 2707 } 2708 sc->fxp_desc.rx_tail = rxp; 2709 } 2710 2711 static void 2712 fxp_discard_rfabuf(struct fxp_softc *sc, struct fxp_rx *rxp) 2713 { 2714 struct mbuf *m; 2715 struct fxp_rfa *rfa; 2716 2717 m = rxp->rx_mbuf; 2718 m->m_data = m->m_ext.ext_buf; 2719 /* 2720 * Move the data pointer up so that the incoming data packet 2721 * will be 32-bit aligned. 2722 */ 2723 m->m_data += RFA_ALIGNMENT_FUDGE; 2724 2725 /* 2726 * Get a pointer to the base of the mbuf cluster and move 2727 * data start past it. 2728 */ 2729 rfa = mtod(m, struct fxp_rfa *); 2730 m->m_data += sc->rfa_size; 2731 rfa->size = htole16(MCLBYTES - sc->rfa_size - RFA_ALIGNMENT_FUDGE); 2732 2733 rfa->rfa_status = 0; 2734 rfa->rfa_control = htole16(FXP_RFA_CONTROL_EL); 2735 rfa->actual_size = 0; 2736 2737 /* 2738 * Initialize the rest of the RFA. Note that since the RFA 2739 * is misaligned, we cannot store values directly. We're thus 2740 * using the le32enc() function which handles endianness and 2741 * is also alignment-safe. 2742 */ 2743 le32enc(&rfa->link_addr, 0xffffffff); 2744 le32enc(&rfa->rbd_addr, 0xffffffff); 2745 2746 bus_dmamap_sync(sc->fxp_rxmtag, rxp->rx_map, 2747 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2748 } 2749 2750 static int 2751 fxp_miibus_readreg(device_t dev, int phy, int reg) 2752 { 2753 struct fxp_softc *sc = device_get_softc(dev); 2754 int count = 10000; 2755 int value; 2756 2757 CSR_WRITE_4(sc, FXP_CSR_MDICONTROL, 2758 (FXP_MDI_READ << 26) | (reg << 16) | (phy << 21)); 2759 2760 while (((value = CSR_READ_4(sc, FXP_CSR_MDICONTROL)) & 0x10000000) == 0 2761 && count--) 2762 DELAY(10); 2763 2764 if (count <= 0) 2765 device_printf(dev, "fxp_miibus_readreg: timed out\n"); 2766 2767 return (value & 0xffff); 2768 } 2769 2770 static int 2771 fxp_miibus_writereg(device_t dev, int phy, int reg, int value) 2772 { 2773 struct fxp_softc *sc = device_get_softc(dev); 2774 int count = 10000; 2775 2776 CSR_WRITE_4(sc, FXP_CSR_MDICONTROL, 2777 (FXP_MDI_WRITE << 26) | (reg << 16) | (phy << 21) | 2778 (value & 0xffff)); 2779 2780 while ((CSR_READ_4(sc, FXP_CSR_MDICONTROL) & 0x10000000) == 0 && 2781 count--) 2782 DELAY(10); 2783 2784 if (count <= 0) 2785 device_printf(dev, "fxp_miibus_writereg: timed out\n"); 2786 return (0); 2787 } 2788 2789 static void 2790 fxp_miibus_statchg(device_t dev) 2791 { 2792 struct fxp_softc *sc; 2793 struct mii_data *mii; 2794 if_t ifp; 2795 2796 sc = device_get_softc(dev); 2797 mii = device_get_softc(sc->miibus); 2798 ifp = sc->ifp; 2799 if (mii == NULL || ifp == (void *)NULL || 2800 (if_getdrvflags(ifp) & IFF_DRV_RUNNING) == 0 || 2801 (mii->mii_media_status & (IFM_AVALID | IFM_ACTIVE)) != 2802 (IFM_AVALID | IFM_ACTIVE)) 2803 return; 2804 2805 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_10_T && 2806 sc->flags & FXP_FLAG_CU_RESUME_BUG) 2807 sc->cu_resume_bug = 1; 2808 else 2809 sc->cu_resume_bug = 0; 2810 /* 2811 * Call fxp_init_body in order to adjust the flow control settings. 2812 * Note that the 82557 doesn't support hardware flow control. 2813 */ 2814 if (sc->revision == FXP_REV_82557) 2815 return; 2816 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 2817 fxp_init_body(sc, 0); 2818 } 2819 2820 static int 2821 fxp_ioctl(if_t ifp, u_long command, caddr_t data) 2822 { 2823 struct fxp_softc *sc = if_getsoftc(ifp); 2824 struct ifreq *ifr = (struct ifreq *)data; 2825 struct mii_data *mii; 2826 int flag, mask, error = 0, reinit; 2827 2828 switch (command) { 2829 case SIOCSIFFLAGS: 2830 FXP_LOCK(sc); 2831 /* 2832 * If interface is marked up and not running, then start it. 2833 * If it is marked down and running, stop it. 2834 * XXX If it's up then re-initialize it. This is so flags 2835 * such as IFF_PROMISC are handled. 2836 */ 2837 if (if_getflags(ifp) & IFF_UP) { 2838 if (((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) && 2839 ((if_getflags(ifp) ^ sc->if_flags) & 2840 (IFF_PROMISC | IFF_ALLMULTI | IFF_LINK0)) != 0) { 2841 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 2842 fxp_init_body(sc, 0); 2843 } else if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) == 0) 2844 fxp_init_body(sc, 1); 2845 } else { 2846 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) 2847 fxp_stop(sc); 2848 } 2849 sc->if_flags = if_getflags(ifp); 2850 FXP_UNLOCK(sc); 2851 break; 2852 2853 case SIOCADDMULTI: 2854 case SIOCDELMULTI: 2855 FXP_LOCK(sc); 2856 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) { 2857 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 2858 fxp_init_body(sc, 0); 2859 } 2860 FXP_UNLOCK(sc); 2861 break; 2862 2863 case SIOCSIFMEDIA: 2864 case SIOCGIFMEDIA: 2865 if (sc->miibus != NULL) { 2866 mii = device_get_softc(sc->miibus); 2867 error = ifmedia_ioctl(ifp, ifr, 2868 &mii->mii_media, command); 2869 } else { 2870 error = ifmedia_ioctl(ifp, ifr, &sc->sc_media, command); 2871 } 2872 break; 2873 2874 case SIOCSIFCAP: 2875 reinit = 0; 2876 mask = if_getcapenable(ifp) ^ ifr->ifr_reqcap; 2877 #ifdef DEVICE_POLLING 2878 if (mask & IFCAP_POLLING) { 2879 if (ifr->ifr_reqcap & IFCAP_POLLING) { 2880 error = ether_poll_register(fxp_poll, ifp); 2881 if (error) 2882 return(error); 2883 FXP_LOCK(sc); 2884 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, 2885 FXP_SCB_INTR_DISABLE); 2886 if_setcapenablebit(ifp, IFCAP_POLLING, 0); 2887 FXP_UNLOCK(sc); 2888 } else { 2889 error = ether_poll_deregister(ifp); 2890 /* Enable interrupts in any case */ 2891 FXP_LOCK(sc); 2892 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, 0); 2893 if_setcapenablebit(ifp, 0, IFCAP_POLLING); 2894 FXP_UNLOCK(sc); 2895 } 2896 } 2897 #endif 2898 FXP_LOCK(sc); 2899 if ((mask & IFCAP_TXCSUM) != 0 && 2900 (if_getcapabilities(ifp) & IFCAP_TXCSUM) != 0) { 2901 if_togglecapenable(ifp, IFCAP_TXCSUM); 2902 if ((if_getcapenable(ifp) & IFCAP_TXCSUM) != 0) 2903 if_sethwassistbits(ifp, FXP_CSUM_FEATURES, 0); 2904 else 2905 if_sethwassistbits(ifp, 0, FXP_CSUM_FEATURES); 2906 } 2907 if ((mask & IFCAP_RXCSUM) != 0 && 2908 (if_getcapabilities(ifp) & IFCAP_RXCSUM) != 0) { 2909 if_togglecapenable(ifp, IFCAP_RXCSUM); 2910 if ((sc->flags & FXP_FLAG_82559_RXCSUM) != 0) 2911 reinit++; 2912 } 2913 if ((mask & IFCAP_TSO4) != 0 && 2914 (if_getcapabilities(ifp) & IFCAP_TSO4) != 0) { 2915 if_togglecapenable(ifp, IFCAP_TSO4); 2916 if ((if_getcapenable(ifp) & IFCAP_TSO4) != 0) 2917 if_sethwassistbits(ifp, CSUM_TSO, 0); 2918 else 2919 if_sethwassistbits(ifp, 0, CSUM_TSO); 2920 } 2921 if ((mask & IFCAP_WOL_MAGIC) != 0 && 2922 (if_getcapabilities(ifp) & IFCAP_WOL_MAGIC) != 0) 2923 if_togglecapenable(ifp, IFCAP_WOL_MAGIC); 2924 if ((mask & IFCAP_VLAN_MTU) != 0 && 2925 (if_getcapabilities(ifp) & IFCAP_VLAN_MTU) != 0) { 2926 if_togglecapenable(ifp, IFCAP_VLAN_MTU); 2927 if (sc->revision != FXP_REV_82557) 2928 flag = FXP_FLAG_LONG_PKT_EN; 2929 else /* a hack to get long frames on the old chip */ 2930 flag = FXP_FLAG_SAVE_BAD; 2931 sc->flags ^= flag; 2932 if (if_getflags(ifp) & IFF_UP) 2933 reinit++; 2934 } 2935 if ((mask & IFCAP_VLAN_HWCSUM) != 0 && 2936 (if_getcapabilities(ifp) & IFCAP_VLAN_HWCSUM) != 0) 2937 if_togglecapenable(ifp, IFCAP_VLAN_HWCSUM); 2938 if ((mask & IFCAP_VLAN_HWTSO) != 0 && 2939 (if_getcapabilities(ifp) & IFCAP_VLAN_HWTSO) != 0) 2940 if_togglecapenable(ifp, IFCAP_VLAN_HWTSO); 2941 if ((mask & IFCAP_VLAN_HWTAGGING) != 0 && 2942 (if_getcapabilities(ifp) & IFCAP_VLAN_HWTAGGING) != 0) { 2943 if_togglecapenable(ifp, IFCAP_VLAN_HWTAGGING); 2944 if ((if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING) == 0) 2945 if_setcapenablebit(ifp, 0, IFCAP_VLAN_HWTSO | 2946 IFCAP_VLAN_HWCSUM); 2947 reinit++; 2948 } 2949 if (reinit > 0 && 2950 (if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) { 2951 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 2952 fxp_init_body(sc, 0); 2953 } 2954 FXP_UNLOCK(sc); 2955 if_vlancap(ifp); 2956 break; 2957 2958 default: 2959 error = ether_ioctl(ifp, command, data); 2960 } 2961 return (error); 2962 } 2963 2964 static u_int 2965 fxp_setup_maddr(void *arg, struct sockaddr_dl *sdl, u_int cnt) 2966 { 2967 struct fxp_softc *sc = arg; 2968 struct fxp_cb_mcs *mcsp = sc->mcsp; 2969 2970 if (mcsp->mc_cnt < MAXMCADDR) 2971 bcopy(LLADDR(sdl), mcsp->mc_addr[mcsp->mc_cnt * ETHER_ADDR_LEN], 2972 ETHER_ADDR_LEN); 2973 mcsp->mc_cnt++; 2974 return (1); 2975 } 2976 2977 /* 2978 * Fill in the multicast address list and return number of entries. 2979 */ 2980 static void 2981 fxp_mc_addrs(struct fxp_softc *sc) 2982 { 2983 struct fxp_cb_mcs *mcsp = sc->mcsp; 2984 if_t ifp = sc->ifp; 2985 2986 if ((if_getflags(ifp) & IFF_ALLMULTI) == 0) { 2987 mcsp->mc_cnt = 0; 2988 if_foreach_llmaddr(sc->ifp, fxp_setup_maddr, sc); 2989 if (mcsp->mc_cnt >= MAXMCADDR) { 2990 if_setflagbits(ifp, IFF_ALLMULTI, 0); 2991 mcsp->mc_cnt = 0; 2992 } 2993 } 2994 mcsp->mc_cnt = htole16(mcsp->mc_cnt * ETHER_ADDR_LEN); 2995 } 2996 2997 /* 2998 * Program the multicast filter. 2999 * 3000 * We have an artificial restriction that the multicast setup command 3001 * must be the first command in the chain, so we take steps to ensure 3002 * this. By requiring this, it allows us to keep up the performance of 3003 * the pre-initialized command ring (esp. link pointers) by not actually 3004 * inserting the mcsetup command in the ring - i.e. its link pointer 3005 * points to the TxCB ring, but the mcsetup descriptor itself is not part 3006 * of it. We then can do 'CU_START' on the mcsetup descriptor and have it 3007 * lead into the regular TxCB ring when it completes. 3008 */ 3009 static void 3010 fxp_mc_setup(struct fxp_softc *sc) 3011 { 3012 struct fxp_cb_mcs *mcsp; 3013 int count; 3014 3015 FXP_LOCK_ASSERT(sc, MA_OWNED); 3016 3017 mcsp = sc->mcsp; 3018 mcsp->cb_status = 0; 3019 mcsp->cb_command = htole16(FXP_CB_COMMAND_MCAS | FXP_CB_COMMAND_EL); 3020 mcsp->link_addr = 0xffffffff; 3021 fxp_mc_addrs(sc); 3022 3023 /* 3024 * Wait until command unit is idle. This should never be the 3025 * case when nothing is queued, but make sure anyway. 3026 */ 3027 count = 100; 3028 while ((CSR_READ_1(sc, FXP_CSR_SCB_RUSCUS) >> 6) != 3029 FXP_SCB_CUS_IDLE && --count) 3030 DELAY(10); 3031 if (count == 0) { 3032 device_printf(sc->dev, "command queue timeout\n"); 3033 return; 3034 } 3035 3036 /* 3037 * Start the multicast setup command. 3038 */ 3039 fxp_scb_wait(sc); 3040 bus_dmamap_sync(sc->mcs_tag, sc->mcs_map, 3041 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3042 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->mcs_addr); 3043 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 3044 /* ...and wait for it to complete. */ 3045 fxp_dma_wait(sc, &mcsp->cb_status, sc->mcs_tag, sc->mcs_map); 3046 } 3047 3048 static uint32_t fxp_ucode_d101a[] = D101_A_RCVBUNDLE_UCODE; 3049 static uint32_t fxp_ucode_d101b0[] = D101_B0_RCVBUNDLE_UCODE; 3050 static uint32_t fxp_ucode_d101ma[] = D101M_B_RCVBUNDLE_UCODE; 3051 static uint32_t fxp_ucode_d101s[] = D101S_RCVBUNDLE_UCODE; 3052 static uint32_t fxp_ucode_d102[] = D102_B_RCVBUNDLE_UCODE; 3053 static uint32_t fxp_ucode_d102c[] = D102_C_RCVBUNDLE_UCODE; 3054 static uint32_t fxp_ucode_d102e[] = D102_E_RCVBUNDLE_UCODE; 3055 3056 #define UCODE(x) x, sizeof(x)/sizeof(uint32_t) 3057 3058 static const struct ucode { 3059 uint32_t revision; 3060 uint32_t *ucode; 3061 int length; 3062 u_short int_delay_offset; 3063 u_short bundle_max_offset; 3064 } ucode_table[] = { 3065 { FXP_REV_82558_A4, UCODE(fxp_ucode_d101a), D101_CPUSAVER_DWORD, 0 }, 3066 { FXP_REV_82558_B0, UCODE(fxp_ucode_d101b0), D101_CPUSAVER_DWORD, 0 }, 3067 { FXP_REV_82559_A0, UCODE(fxp_ucode_d101ma), 3068 D101M_CPUSAVER_DWORD, D101M_CPUSAVER_BUNDLE_MAX_DWORD }, 3069 { FXP_REV_82559S_A, UCODE(fxp_ucode_d101s), 3070 D101S_CPUSAVER_DWORD, D101S_CPUSAVER_BUNDLE_MAX_DWORD }, 3071 { FXP_REV_82550, UCODE(fxp_ucode_d102), 3072 D102_B_CPUSAVER_DWORD, D102_B_CPUSAVER_BUNDLE_MAX_DWORD }, 3073 { FXP_REV_82550_C, UCODE(fxp_ucode_d102c), 3074 D102_C_CPUSAVER_DWORD, D102_C_CPUSAVER_BUNDLE_MAX_DWORD }, 3075 { FXP_REV_82551_F, UCODE(fxp_ucode_d102e), 3076 D102_E_CPUSAVER_DWORD, D102_E_CPUSAVER_BUNDLE_MAX_DWORD }, 3077 { FXP_REV_82551_10, UCODE(fxp_ucode_d102e), 3078 D102_E_CPUSAVER_DWORD, D102_E_CPUSAVER_BUNDLE_MAX_DWORD }, 3079 { 0, NULL, 0, 0, 0 } 3080 }; 3081 3082 static void 3083 fxp_load_ucode(struct fxp_softc *sc) 3084 { 3085 const struct ucode *uc; 3086 struct fxp_cb_ucode *cbp; 3087 int i; 3088 3089 if (sc->flags & FXP_FLAG_NO_UCODE) 3090 return; 3091 3092 for (uc = ucode_table; uc->ucode != NULL; uc++) 3093 if (sc->revision == uc->revision) 3094 break; 3095 if (uc->ucode == NULL) 3096 return; 3097 cbp = (struct fxp_cb_ucode *)sc->fxp_desc.cbl_list; 3098 cbp->cb_status = 0; 3099 cbp->cb_command = htole16(FXP_CB_COMMAND_UCODE | FXP_CB_COMMAND_EL); 3100 cbp->link_addr = 0xffffffff; /* (no) next command */ 3101 for (i = 0; i < uc->length; i++) 3102 cbp->ucode[i] = htole32(uc->ucode[i]); 3103 if (uc->int_delay_offset) 3104 *(uint16_t *)&cbp->ucode[uc->int_delay_offset] = 3105 htole16(sc->tunable_int_delay + sc->tunable_int_delay / 2); 3106 if (uc->bundle_max_offset) 3107 *(uint16_t *)&cbp->ucode[uc->bundle_max_offset] = 3108 htole16(sc->tunable_bundle_max); 3109 /* 3110 * Download the ucode to the chip. 3111 */ 3112 fxp_scb_wait(sc); 3113 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, 3114 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3115 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->fxp_desc.cbl_addr); 3116 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 3117 /* ...and wait for it to complete. */ 3118 fxp_dma_wait(sc, &cbp->cb_status, sc->cbl_tag, sc->cbl_map); 3119 device_printf(sc->dev, 3120 "Microcode loaded, int_delay: %d usec bundle_max: %d\n", 3121 sc->tunable_int_delay, 3122 uc->bundle_max_offset == 0 ? 0 : sc->tunable_bundle_max); 3123 sc->flags |= FXP_FLAG_UCODE; 3124 bzero(cbp, FXP_TXCB_SZ); 3125 } 3126 3127 #define FXP_SYSCTL_STAT_ADD(c, h, n, p, d) \ 3128 SYSCTL_ADD_UINT(c, h, OID_AUTO, n, CTLFLAG_RD, p, 0, d) 3129 3130 static void 3131 fxp_sysctl_node(struct fxp_softc *sc) 3132 { 3133 struct sysctl_ctx_list *ctx; 3134 struct sysctl_oid_list *child, *parent; 3135 struct sysctl_oid *tree; 3136 struct fxp_hwstats *hsp; 3137 3138 ctx = device_get_sysctl_ctx(sc->dev); 3139 child = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)); 3140 3141 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "int_delay", 3142 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_MPSAFE, 3143 &sc->tunable_int_delay, 0, sysctl_hw_fxp_int_delay, "I", 3144 "FXP driver receive interrupt microcode bundling delay"); 3145 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "bundle_max", 3146 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_MPSAFE, 3147 &sc->tunable_bundle_max, 0, sysctl_hw_fxp_bundle_max, "I", 3148 "FXP driver receive interrupt microcode bundle size limit"); 3149 SYSCTL_ADD_INT(ctx, child,OID_AUTO, "rnr", CTLFLAG_RD, &sc->rnr, 0, 3150 "FXP RNR events"); 3151 3152 /* 3153 * Pull in device tunables. 3154 */ 3155 sc->tunable_int_delay = TUNABLE_INT_DELAY; 3156 sc->tunable_bundle_max = TUNABLE_BUNDLE_MAX; 3157 (void) resource_int_value(device_get_name(sc->dev), 3158 device_get_unit(sc->dev), "int_delay", &sc->tunable_int_delay); 3159 (void) resource_int_value(device_get_name(sc->dev), 3160 device_get_unit(sc->dev), "bundle_max", &sc->tunable_bundle_max); 3161 sc->rnr = 0; 3162 3163 hsp = &sc->fxp_hwstats; 3164 tree = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "stats", 3165 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "FXP statistics"); 3166 parent = SYSCTL_CHILDREN(tree); 3167 3168 /* Rx MAC statistics. */ 3169 tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "rx", 3170 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "Rx MAC statistics"); 3171 child = SYSCTL_CHILDREN(tree); 3172 FXP_SYSCTL_STAT_ADD(ctx, child, "good_frames", 3173 &hsp->rx_good, "Good frames"); 3174 FXP_SYSCTL_STAT_ADD(ctx, child, "crc_errors", 3175 &hsp->rx_crc_errors, "CRC errors"); 3176 FXP_SYSCTL_STAT_ADD(ctx, child, "alignment_errors", 3177 &hsp->rx_alignment_errors, "Alignment errors"); 3178 FXP_SYSCTL_STAT_ADD(ctx, child, "rnr_errors", 3179 &hsp->rx_rnr_errors, "RNR errors"); 3180 FXP_SYSCTL_STAT_ADD(ctx, child, "overrun_errors", 3181 &hsp->rx_overrun_errors, "Overrun errors"); 3182 FXP_SYSCTL_STAT_ADD(ctx, child, "cdt_errors", 3183 &hsp->rx_cdt_errors, "Collision detect errors"); 3184 FXP_SYSCTL_STAT_ADD(ctx, child, "shortframes", 3185 &hsp->rx_shortframes, "Short frame errors"); 3186 if (sc->revision >= FXP_REV_82558_A4) { 3187 FXP_SYSCTL_STAT_ADD(ctx, child, "pause", 3188 &hsp->rx_pause, "Pause frames"); 3189 FXP_SYSCTL_STAT_ADD(ctx, child, "controls", 3190 &hsp->rx_controls, "Unsupported control frames"); 3191 } 3192 if (sc->revision >= FXP_REV_82559_A0) 3193 FXP_SYSCTL_STAT_ADD(ctx, child, "tco", 3194 &hsp->rx_tco, "TCO frames"); 3195 3196 /* Tx MAC statistics. */ 3197 tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "tx", 3198 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "Tx MAC statistics"); 3199 child = SYSCTL_CHILDREN(tree); 3200 FXP_SYSCTL_STAT_ADD(ctx, child, "good_frames", 3201 &hsp->tx_good, "Good frames"); 3202 FXP_SYSCTL_STAT_ADD(ctx, child, "maxcols", 3203 &hsp->tx_maxcols, "Maximum collisions errors"); 3204 FXP_SYSCTL_STAT_ADD(ctx, child, "latecols", 3205 &hsp->tx_latecols, "Late collisions errors"); 3206 FXP_SYSCTL_STAT_ADD(ctx, child, "underruns", 3207 &hsp->tx_underruns, "Underrun errors"); 3208 FXP_SYSCTL_STAT_ADD(ctx, child, "lostcrs", 3209 &hsp->tx_lostcrs, "Lost carrier sense"); 3210 FXP_SYSCTL_STAT_ADD(ctx, child, "deffered", 3211 &hsp->tx_deffered, "Deferred"); 3212 FXP_SYSCTL_STAT_ADD(ctx, child, "single_collisions", 3213 &hsp->tx_single_collisions, "Single collisions"); 3214 FXP_SYSCTL_STAT_ADD(ctx, child, "multiple_collisions", 3215 &hsp->tx_multiple_collisions, "Multiple collisions"); 3216 FXP_SYSCTL_STAT_ADD(ctx, child, "total_collisions", 3217 &hsp->tx_total_collisions, "Total collisions"); 3218 if (sc->revision >= FXP_REV_82558_A4) 3219 FXP_SYSCTL_STAT_ADD(ctx, child, "pause", 3220 &hsp->tx_pause, "Pause frames"); 3221 if (sc->revision >= FXP_REV_82559_A0) 3222 FXP_SYSCTL_STAT_ADD(ctx, child, "tco", 3223 &hsp->tx_tco, "TCO frames"); 3224 } 3225 3226 #undef FXP_SYSCTL_STAT_ADD 3227 3228 static int 3229 sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high) 3230 { 3231 int error, value; 3232 3233 value = *(int *)arg1; 3234 error = sysctl_handle_int(oidp, &value, 0, req); 3235 if (error || !req->newptr) 3236 return (error); 3237 if (value < low || value > high) 3238 return (EINVAL); 3239 *(int *)arg1 = value; 3240 return (0); 3241 } 3242 3243 /* 3244 * Interrupt delay is expressed in microseconds, a multiplier is used 3245 * to convert this to the appropriate clock ticks before using. 3246 */ 3247 static int 3248 sysctl_hw_fxp_int_delay(SYSCTL_HANDLER_ARGS) 3249 { 3250 3251 return (sysctl_int_range(oidp, arg1, arg2, req, 300, 3000)); 3252 } 3253 3254 static int 3255 sysctl_hw_fxp_bundle_max(SYSCTL_HANDLER_ARGS) 3256 { 3257 3258 return (sysctl_int_range(oidp, arg1, arg2, req, 1, 0xffff)); 3259 } 3260