1 /*- 2 * Copyright (c) 1995, David Greenman 3 * Copyright (c) 2001 Jonathan Lemon <jlemon@freebsd.org> 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice unmodified, this list of conditions, and the following 11 * disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 * 28 */ 29 30 #include <sys/cdefs.h> 31 __FBSDID("$FreeBSD$"); 32 33 /* 34 * Intel EtherExpress Pro/100B PCI Fast Ethernet driver 35 */ 36 37 #include <sys/param.h> 38 #include <sys/systm.h> 39 #include <sys/endian.h> 40 #include <sys/mbuf.h> 41 /* #include <sys/mutex.h> */ 42 #include <sys/kernel.h> 43 #include <sys/module.h> 44 #include <sys/socket.h> 45 #include <sys/sysctl.h> 46 47 #include <net/if.h> 48 #include <net/if_dl.h> 49 #include <net/if_media.h> 50 51 #include <net/bpf.h> 52 #include <sys/sockio.h> 53 #include <sys/bus.h> 54 #include <machine/bus.h> 55 #include <sys/rman.h> 56 #include <machine/resource.h> 57 58 #include <net/ethernet.h> 59 #include <net/if_arp.h> 60 61 #include <machine/clock.h> /* for DELAY */ 62 63 #include <net/if_types.h> 64 #include <net/if_vlan_var.h> 65 66 #ifdef FXP_IP_CSUM_WAR 67 #include <netinet/in.h> 68 #include <netinet/in_systm.h> 69 #include <netinet/ip.h> 70 #include <machine/in_cksum.h> 71 #endif 72 73 #include <dev/pci/pcivar.h> 74 #include <dev/pci/pcireg.h> /* for PCIM_CMD_xxx */ 75 76 #include <dev/mii/mii.h> 77 #include <dev/mii/miivar.h> 78 79 #include <dev/fxp/if_fxpreg.h> 80 #include <dev/fxp/if_fxpvar.h> 81 #include <dev/fxp/rcvbundl.h> 82 83 MODULE_DEPEND(fxp, pci, 1, 1, 1); 84 MODULE_DEPEND(fxp, ether, 1, 1, 1); 85 MODULE_DEPEND(fxp, miibus, 1, 1, 1); 86 #include "miibus_if.h" 87 88 /* 89 * NOTE! On the Alpha, we have an alignment constraint. The 90 * card DMAs the packet immediately following the RFA. However, 91 * the first thing in the packet is a 14-byte Ethernet header. 92 * This means that the packet is misaligned. To compensate, 93 * we actually offset the RFA 2 bytes into the cluster. This 94 * alignes the packet after the Ethernet header at a 32-bit 95 * boundary. HOWEVER! This means that the RFA is misaligned! 96 */ 97 #define RFA_ALIGNMENT_FUDGE 2 98 99 /* 100 * Set initial transmit threshold at 64 (512 bytes). This is 101 * increased by 64 (512 bytes) at a time, to maximum of 192 102 * (1536 bytes), if an underrun occurs. 103 */ 104 static int tx_threshold = 64; 105 106 /* 107 * The configuration byte map has several undefined fields which 108 * must be one or must be zero. Set up a template for these bits 109 * only, (assuming a 82557 chip) leaving the actual configuration 110 * to fxp_init. 111 * 112 * See struct fxp_cb_config for the bit definitions. 113 */ 114 static u_char fxp_cb_config_template[] = { 115 0x0, 0x0, /* cb_status */ 116 0x0, 0x0, /* cb_command */ 117 0x0, 0x0, 0x0, 0x0, /* link_addr */ 118 0x0, /* 0 */ 119 0x0, /* 1 */ 120 0x0, /* 2 */ 121 0x0, /* 3 */ 122 0x0, /* 4 */ 123 0x0, /* 5 */ 124 0x32, /* 6 */ 125 0x0, /* 7 */ 126 0x0, /* 8 */ 127 0x0, /* 9 */ 128 0x6, /* 10 */ 129 0x0, /* 11 */ 130 0x0, /* 12 */ 131 0x0, /* 13 */ 132 0xf2, /* 14 */ 133 0x48, /* 15 */ 134 0x0, /* 16 */ 135 0x40, /* 17 */ 136 0xf0, /* 18 */ 137 0x0, /* 19 */ 138 0x3f, /* 20 */ 139 0x5 /* 21 */ 140 }; 141 142 struct fxp_ident { 143 u_int16_t devid; 144 int16_t revid; /* -1 matches anything */ 145 char *name; 146 }; 147 148 /* 149 * Claim various Intel PCI device identifiers for this driver. The 150 * sub-vendor and sub-device field are extensively used to identify 151 * particular variants, but we don't currently differentiate between 152 * them. 153 */ 154 static struct fxp_ident fxp_ident_table[] = { 155 { 0x1029, -1, "Intel 82559 PCI/CardBus Pro/100" }, 156 { 0x1030, -1, "Intel 82559 Pro/100 Ethernet" }, 157 { 0x1031, -1, "Intel 82801CAM (ICH3) Pro/100 VE Ethernet" }, 158 { 0x1032, -1, "Intel 82801CAM (ICH3) Pro/100 VE Ethernet" }, 159 { 0x1033, -1, "Intel 82801CAM (ICH3) Pro/100 VM Ethernet" }, 160 { 0x1034, -1, "Intel 82801CAM (ICH3) Pro/100 VM Ethernet" }, 161 { 0x1035, -1, "Intel 82801CAM (ICH3) Pro/100 Ethernet" }, 162 { 0x1036, -1, "Intel 82801CAM (ICH3) Pro/100 Ethernet" }, 163 { 0x1037, -1, "Intel 82801CAM (ICH3) Pro/100 Ethernet" }, 164 { 0x1038, -1, "Intel 82801CAM (ICH3) Pro/100 VM Ethernet" }, 165 { 0x1039, -1, "Intel 82801DB (ICH4) Pro/100 VE Ethernet" }, 166 { 0x103A, -1, "Intel 82801DB (ICH4) Pro/100 Ethernet" }, 167 { 0x103B, -1, "Intel 82801DB (ICH4) Pro/100 VM Ethernet" }, 168 { 0x103C, -1, "Intel 82801DB (ICH4) Pro/100 Ethernet" }, 169 { 0x103D, -1, "Intel 82801DB (ICH4) Pro/100 VE Ethernet" }, 170 { 0x103E, -1, "Intel 82801DB (ICH4) Pro/100 VM Ethernet" }, 171 { 0x1050, -1, "Intel 82801BA (D865) Pro/100 VE Ethernet" }, 172 { 0x1051, -1, "Intel 82562ET (ICH5/ICH5R) Pro/100 VE Ethernet" }, 173 { 0x1059, -1, "Intel 82551QM Pro/100 M Mobile Connection" }, 174 { 0x1209, -1, "Intel 82559ER Embedded 10/100 Ethernet" }, 175 { 0x1229, 0x01, "Intel 82557 Pro/100 Ethernet" }, 176 { 0x1229, 0x02, "Intel 82557 Pro/100 Ethernet" }, 177 { 0x1229, 0x03, "Intel 82557 Pro/100 Ethernet" }, 178 { 0x1229, 0x04, "Intel 82558 Pro/100 Ethernet" }, 179 { 0x1229, 0x05, "Intel 82558 Pro/100 Ethernet" }, 180 { 0x1229, 0x06, "Intel 82559 Pro/100 Ethernet" }, 181 { 0x1229, 0x07, "Intel 82559 Pro/100 Ethernet" }, 182 { 0x1229, 0x08, "Intel 82559 Pro/100 Ethernet" }, 183 { 0x1229, 0x09, "Intel 82559ER Pro/100 Ethernet" }, 184 { 0x1229, 0x0c, "Intel 82550 Pro/100 Ethernet" }, 185 { 0x1229, 0x0d, "Intel 82550 Pro/100 Ethernet" }, 186 { 0x1229, 0x0e, "Intel 82550 Pro/100 Ethernet" }, 187 { 0x1229, 0x0f, "Intel 82551 Pro/100 Ethernet" }, 188 { 0x1229, 0x10, "Intel 82551 Pro/100 Ethernet" }, 189 { 0x1229, -1, "Intel 82557/8/9 Pro/100 Ethernet" }, 190 { 0x2449, -1, "Intel 82801BA/CAM (ICH2/3) Pro/100 Ethernet" }, 191 { 0, -1, NULL }, 192 }; 193 194 #ifdef FXP_IP_CSUM_WAR 195 #define FXP_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 196 #else 197 #define FXP_CSUM_FEATURES (CSUM_TCP | CSUM_UDP) 198 #endif 199 200 static int fxp_probe(device_t dev); 201 static int fxp_attach(device_t dev); 202 static int fxp_detach(device_t dev); 203 static int fxp_shutdown(device_t dev); 204 static int fxp_suspend(device_t dev); 205 static int fxp_resume(device_t dev); 206 207 static void fxp_intr(void *xsc); 208 static void fxp_intr_body(struct fxp_softc *sc, struct ifnet *ifp, 209 u_int8_t statack, int count); 210 static void fxp_init(void *xsc); 211 static void fxp_init_body(struct fxp_softc *sc); 212 static void fxp_tick(void *xsc); 213 static void fxp_start(struct ifnet *ifp); 214 static void fxp_start_body(struct ifnet *ifp); 215 static void fxp_stop(struct fxp_softc *sc); 216 static void fxp_release(struct fxp_softc *sc); 217 static int fxp_ioctl(struct ifnet *ifp, u_long command, 218 caddr_t data); 219 static void fxp_watchdog(struct ifnet *ifp); 220 static int fxp_add_rfabuf(struct fxp_softc *sc, 221 struct fxp_rx *rxp); 222 static int fxp_mc_addrs(struct fxp_softc *sc); 223 static void fxp_mc_setup(struct fxp_softc *sc); 224 static u_int16_t fxp_eeprom_getword(struct fxp_softc *sc, int offset, 225 int autosize); 226 static void fxp_eeprom_putword(struct fxp_softc *sc, int offset, 227 u_int16_t data); 228 static void fxp_autosize_eeprom(struct fxp_softc *sc); 229 static void fxp_read_eeprom(struct fxp_softc *sc, u_short *data, 230 int offset, int words); 231 static void fxp_write_eeprom(struct fxp_softc *sc, u_short *data, 232 int offset, int words); 233 static int fxp_ifmedia_upd(struct ifnet *ifp); 234 static void fxp_ifmedia_sts(struct ifnet *ifp, 235 struct ifmediareq *ifmr); 236 static int fxp_serial_ifmedia_upd(struct ifnet *ifp); 237 static void fxp_serial_ifmedia_sts(struct ifnet *ifp, 238 struct ifmediareq *ifmr); 239 static volatile int fxp_miibus_readreg(device_t dev, int phy, int reg); 240 static void fxp_miibus_writereg(device_t dev, int phy, int reg, 241 int value); 242 static void fxp_load_ucode(struct fxp_softc *sc); 243 static int sysctl_int_range(SYSCTL_HANDLER_ARGS, 244 int low, int high); 245 static int sysctl_hw_fxp_bundle_max(SYSCTL_HANDLER_ARGS); 246 static int sysctl_hw_fxp_int_delay(SYSCTL_HANDLER_ARGS); 247 static void fxp_scb_wait(struct fxp_softc *sc); 248 static void fxp_scb_cmd(struct fxp_softc *sc, int cmd); 249 static void fxp_dma_wait(struct fxp_softc *sc, 250 volatile u_int16_t *status, bus_dma_tag_t dmat, 251 bus_dmamap_t map); 252 253 static device_method_t fxp_methods[] = { 254 /* Device interface */ 255 DEVMETHOD(device_probe, fxp_probe), 256 DEVMETHOD(device_attach, fxp_attach), 257 DEVMETHOD(device_detach, fxp_detach), 258 DEVMETHOD(device_shutdown, fxp_shutdown), 259 DEVMETHOD(device_suspend, fxp_suspend), 260 DEVMETHOD(device_resume, fxp_resume), 261 262 /* MII interface */ 263 DEVMETHOD(miibus_readreg, fxp_miibus_readreg), 264 DEVMETHOD(miibus_writereg, fxp_miibus_writereg), 265 266 { 0, 0 } 267 }; 268 269 static driver_t fxp_driver = { 270 "fxp", 271 fxp_methods, 272 sizeof(struct fxp_softc), 273 }; 274 275 static devclass_t fxp_devclass; 276 277 DRIVER_MODULE(fxp, pci, fxp_driver, fxp_devclass, 0, 0); 278 DRIVER_MODULE(fxp, cardbus, fxp_driver, fxp_devclass, 0, 0); 279 DRIVER_MODULE(miibus, fxp, miibus_driver, miibus_devclass, 0, 0); 280 281 /* 282 * Wait for the previous command to be accepted (but not necessarily 283 * completed). 284 */ 285 static void 286 fxp_scb_wait(struct fxp_softc *sc) 287 { 288 int i = 10000; 289 290 while (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) && --i) 291 DELAY(2); 292 if (i == 0) 293 device_printf(sc->dev, "SCB timeout: 0x%x 0x%x 0x%x 0x%x\n", 294 CSR_READ_1(sc, FXP_CSR_SCB_COMMAND), 295 CSR_READ_1(sc, FXP_CSR_SCB_STATACK), 296 CSR_READ_1(sc, FXP_CSR_SCB_RUSCUS), 297 CSR_READ_2(sc, FXP_CSR_FLOWCONTROL)); 298 } 299 300 static void 301 fxp_scb_cmd(struct fxp_softc *sc, int cmd) 302 { 303 304 if (cmd == FXP_SCB_COMMAND_CU_RESUME && sc->cu_resume_bug) { 305 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_CB_COMMAND_NOP); 306 fxp_scb_wait(sc); 307 } 308 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, cmd); 309 } 310 311 static void 312 fxp_dma_wait(struct fxp_softc *sc, volatile u_int16_t *status, 313 bus_dma_tag_t dmat, bus_dmamap_t map) 314 { 315 int i = 10000; 316 317 bus_dmamap_sync(dmat, map, BUS_DMASYNC_POSTREAD); 318 while (!(le16toh(*status) & FXP_CB_STATUS_C) && --i) { 319 DELAY(2); 320 bus_dmamap_sync(dmat, map, BUS_DMASYNC_POSTREAD); 321 } 322 if (i == 0) 323 device_printf(sc->dev, "DMA timeout\n"); 324 } 325 326 /* 327 * Return identification string if this device is ours. 328 */ 329 static int 330 fxp_probe(device_t dev) 331 { 332 u_int16_t devid; 333 u_int8_t revid; 334 struct fxp_ident *ident; 335 336 if (pci_get_vendor(dev) == FXP_VENDORID_INTEL) { 337 devid = pci_get_device(dev); 338 revid = pci_get_revid(dev); 339 for (ident = fxp_ident_table; ident->name != NULL; ident++) { 340 if (ident->devid == devid && 341 (ident->revid == revid || ident->revid == -1)) { 342 device_set_desc(dev, ident->name); 343 return (0); 344 } 345 } 346 } 347 return (ENXIO); 348 } 349 350 static void 351 fxp_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error) 352 { 353 u_int32_t *addr; 354 355 if (error) 356 return; 357 358 KASSERT(nseg == 1, ("too many DMA segments, %d should be 1", nseg)); 359 addr = arg; 360 *addr = segs->ds_addr; 361 } 362 363 static int 364 fxp_attach(device_t dev) 365 { 366 int error = 0; 367 struct fxp_softc *sc = device_get_softc(dev); 368 struct ifnet *ifp; 369 struct fxp_rx *rxp; 370 u_int32_t val; 371 u_int16_t data, myea[ETHER_ADDR_LEN / 2]; 372 int i, rid, m1, m2, prefer_iomap, maxtxseg; 373 int s, ipcbxmit_disable; 374 375 sc->dev = dev; 376 callout_init(&sc->stat_ch, CALLOUT_MPSAFE); 377 mtx_init(&sc->sc_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 378 MTX_DEF); 379 ifmedia_init(&sc->sc_media, 0, fxp_serial_ifmedia_upd, 380 fxp_serial_ifmedia_sts); 381 382 s = splimp(); 383 384 /* 385 * Enable bus mastering. 386 */ 387 pci_enable_busmaster(dev); 388 val = pci_read_config(dev, PCIR_COMMAND, 2); 389 390 /* 391 * Figure out which we should try first - memory mapping or i/o mapping? 392 * We default to memory mapping. Then we accept an override from the 393 * command line. Then we check to see which one is enabled. 394 */ 395 m1 = PCIM_CMD_MEMEN; 396 m2 = PCIM_CMD_PORTEN; 397 prefer_iomap = 0; 398 if (resource_int_value(device_get_name(dev), device_get_unit(dev), 399 "prefer_iomap", &prefer_iomap) == 0 && prefer_iomap != 0) { 400 m1 = PCIM_CMD_PORTEN; 401 m2 = PCIM_CMD_MEMEN; 402 } 403 404 sc->rtp = (m1 == PCIM_CMD_MEMEN)? SYS_RES_MEMORY : SYS_RES_IOPORT; 405 sc->rgd = (m1 == PCIM_CMD_MEMEN)? FXP_PCI_MMBA : FXP_PCI_IOBA; 406 sc->mem = bus_alloc_resource_any(dev, sc->rtp, &sc->rgd, RF_ACTIVE); 407 if (sc->mem == NULL) { 408 sc->rtp = 409 (m2 == PCIM_CMD_MEMEN)? SYS_RES_MEMORY : SYS_RES_IOPORT; 410 sc->rgd = (m2 == PCIM_CMD_MEMEN)? FXP_PCI_MMBA : FXP_PCI_IOBA; 411 sc->mem = bus_alloc_resource_any(dev, sc->rtp, &sc->rgd, 412 RF_ACTIVE); 413 } 414 415 if (!sc->mem) { 416 error = ENXIO; 417 goto fail; 418 } 419 if (bootverbose) { 420 device_printf(dev, "using %s space register mapping\n", 421 sc->rtp == SYS_RES_MEMORY? "memory" : "I/O"); 422 } 423 424 sc->sc_st = rman_get_bustag(sc->mem); 425 sc->sc_sh = rman_get_bushandle(sc->mem); 426 427 /* 428 * Allocate our interrupt. 429 */ 430 rid = 0; 431 sc->irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 432 RF_SHAREABLE | RF_ACTIVE); 433 if (sc->irq == NULL) { 434 device_printf(dev, "could not map interrupt\n"); 435 error = ENXIO; 436 goto fail; 437 } 438 439 /* 440 * Reset to a stable state. 441 */ 442 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET); 443 DELAY(10); 444 445 /* 446 * Find out how large of an SEEPROM we have. 447 */ 448 fxp_autosize_eeprom(sc); 449 450 /* 451 * Determine whether we must use the 503 serial interface. 452 */ 453 fxp_read_eeprom(sc, &data, 6, 1); 454 if ((data & FXP_PHY_DEVICE_MASK) != 0 && 455 (data & FXP_PHY_SERIAL_ONLY)) 456 sc->flags |= FXP_FLAG_SERIAL_MEDIA; 457 458 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 459 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 460 OID_AUTO, "int_delay", CTLTYPE_INT | CTLFLAG_RW, 461 &sc->tunable_int_delay, 0, sysctl_hw_fxp_int_delay, "I", 462 "FXP driver receive interrupt microcode bundling delay"); 463 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 464 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 465 OID_AUTO, "bundle_max", CTLTYPE_INT | CTLFLAG_RW, 466 &sc->tunable_bundle_max, 0, sysctl_hw_fxp_bundle_max, "I", 467 "FXP driver receive interrupt microcode bundle size limit"); 468 SYSCTL_ADD_INT(device_get_sysctl_ctx(dev), 469 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 470 OID_AUTO, "rnr", CTLFLAG_RD, &sc->rnr, 0, 471 "FXP RNR events"); 472 SYSCTL_ADD_INT(device_get_sysctl_ctx(dev), 473 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 474 OID_AUTO, "noflow", CTLFLAG_RW, &sc->tunable_noflow, 0, 475 "FXP flow control disabled"); 476 477 /* 478 * Pull in device tunables. 479 */ 480 sc->tunable_int_delay = TUNABLE_INT_DELAY; 481 sc->tunable_bundle_max = TUNABLE_BUNDLE_MAX; 482 sc->tunable_noflow = 0; 483 (void) resource_int_value(device_get_name(dev), device_get_unit(dev), 484 "int_delay", &sc->tunable_int_delay); 485 (void) resource_int_value(device_get_name(dev), device_get_unit(dev), 486 "bundle_max", &sc->tunable_bundle_max); 487 (void) resource_int_value(device_get_name(dev), device_get_unit(dev), 488 "noflow", &sc->tunable_noflow); 489 sc->rnr = 0; 490 491 /* 492 * Find out the chip revision; lump all 82557 revs together. 493 */ 494 fxp_read_eeprom(sc, &data, 5, 1); 495 if ((data >> 8) == 1) 496 sc->revision = FXP_REV_82557; 497 else 498 sc->revision = pci_get_revid(dev); 499 500 /* 501 * Enable workarounds for certain chip revision deficiencies. 502 * 503 * Systems based on the ICH2/ICH2-M chip from Intel, and possibly 504 * some systems based a normal 82559 design, have a defect where 505 * the chip can cause a PCI protocol violation if it receives 506 * a CU_RESUME command when it is entering the IDLE state. The 507 * workaround is to disable Dynamic Standby Mode, so the chip never 508 * deasserts CLKRUN#, and always remains in an active state. 509 * 510 * See Intel 82801BA/82801BAM Specification Update, Errata #30. 511 */ 512 i = pci_get_device(dev); 513 if (i == 0x2449 || (i > 0x1030 && i < 0x1039) || 514 sc->revision >= FXP_REV_82559_A0) { 515 fxp_read_eeprom(sc, &data, 10, 1); 516 if (data & 0x02) { /* STB enable */ 517 u_int16_t cksum; 518 int i; 519 520 device_printf(dev, 521 "Disabling dynamic standby mode in EEPROM\n"); 522 data &= ~0x02; 523 fxp_write_eeprom(sc, &data, 10, 1); 524 device_printf(dev, "New EEPROM ID: 0x%x\n", data); 525 cksum = 0; 526 for (i = 0; i < (1 << sc->eeprom_size) - 1; i++) { 527 fxp_read_eeprom(sc, &data, i, 1); 528 cksum += data; 529 } 530 i = (1 << sc->eeprom_size) - 1; 531 cksum = 0xBABA - cksum; 532 fxp_read_eeprom(sc, &data, i, 1); 533 fxp_write_eeprom(sc, &cksum, i, 1); 534 device_printf(dev, 535 "EEPROM checksum @ 0x%x: 0x%x -> 0x%x\n", 536 i, data, cksum); 537 #if 1 538 /* 539 * If the user elects to continue, try the software 540 * workaround, as it is better than nothing. 541 */ 542 sc->flags |= FXP_FLAG_CU_RESUME_BUG; 543 #endif 544 } 545 } 546 547 /* 548 * If we are not a 82557 chip, we can enable extended features. 549 */ 550 if (sc->revision != FXP_REV_82557) { 551 /* 552 * If MWI is enabled in the PCI configuration, and there 553 * is a valid cacheline size (8 or 16 dwords), then tell 554 * the board to turn on MWI. 555 */ 556 if (val & PCIM_CMD_MWRICEN && 557 pci_read_config(dev, PCIR_CACHELNSZ, 1) != 0) 558 sc->flags |= FXP_FLAG_MWI_ENABLE; 559 560 /* turn on the extended TxCB feature */ 561 sc->flags |= FXP_FLAG_EXT_TXCB; 562 563 /* enable reception of long frames for VLAN */ 564 sc->flags |= FXP_FLAG_LONG_PKT_EN; 565 } else { 566 /* a hack to get long VLAN frames on a 82557 */ 567 sc->flags |= FXP_FLAG_SAVE_BAD; 568 } 569 570 /* 571 * Enable use of extended RFDs and TCBs for 82550 572 * and later chips. Note: we need extended TXCB support 573 * too, but that's already enabled by the code above. 574 * Be careful to do this only on the right devices. 575 * 576 * At least some 82550 cards probed as "chip=0x12298086 rev=0x0d" 577 * truncate packets that end with an mbuf containing 1 to 3 bytes 578 * when used with this feature enabled in the previous version of the 579 * driver. This problem appears to be fixed now that the driver 580 * always sets the hardware parse bit in the IPCB structure, which 581 * the "Intel 8255x 10/100 Mbps Ethernet Controller Family Open 582 * Source Software Developer Manual" says is necessary in the 583 * cases where packet truncation was observed. 584 * 585 * The device hint "hint.fxp.UNIT_NUMBER.ipcbxmit_disable" 586 * allows this feature to be disabled at boot time. 587 * 588 * If fxp is not compiled into the kernel, this feature may also 589 * be disabled at run time: 590 * # kldunload fxp 591 * # kenv hint.fxp.0.ipcbxmit_disable=1 592 * # kldload fxp 593 */ 594 595 if (resource_int_value("fxp", device_get_unit(dev), "ipcbxmit_disable", 596 &ipcbxmit_disable) != 0) 597 ipcbxmit_disable = 0; 598 if (ipcbxmit_disable == 0 && (sc->revision == FXP_REV_82550 || 599 sc->revision == FXP_REV_82550_C)) { 600 sc->rfa_size = sizeof (struct fxp_rfa); 601 sc->tx_cmd = FXP_CB_COMMAND_IPCBXMIT; 602 sc->flags |= FXP_FLAG_EXT_RFA; 603 } else { 604 sc->rfa_size = sizeof (struct fxp_rfa) - FXP_RFAX_LEN; 605 sc->tx_cmd = FXP_CB_COMMAND_XMIT; 606 } 607 608 /* 609 * Allocate DMA tags and DMA safe memory. 610 */ 611 maxtxseg = sc->flags & FXP_FLAG_EXT_RFA ? FXP_NTXSEG - 1 : FXP_NTXSEG; 612 error = bus_dma_tag_create(NULL, 2, 0, BUS_SPACE_MAXADDR_32BIT, 613 BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES * maxtxseg, 614 maxtxseg, MCLBYTES, 0, busdma_lock_mutex, &Giant, &sc->fxp_mtag); 615 if (error) { 616 device_printf(dev, "could not allocate dma tag\n"); 617 goto fail; 618 } 619 620 error = bus_dma_tag_create(NULL, 4, 0, BUS_SPACE_MAXADDR_32BIT, 621 BUS_SPACE_MAXADDR, NULL, NULL, sizeof(struct fxp_stats), 1, 622 sizeof(struct fxp_stats), 0, busdma_lock_mutex, &Giant, 623 &sc->fxp_stag); 624 if (error) { 625 device_printf(dev, "could not allocate dma tag\n"); 626 goto fail; 627 } 628 629 error = bus_dmamem_alloc(sc->fxp_stag, (void **)&sc->fxp_stats, 630 BUS_DMA_NOWAIT | BUS_DMA_ZERO, &sc->fxp_smap); 631 if (error) 632 goto fail; 633 error = bus_dmamap_load(sc->fxp_stag, sc->fxp_smap, sc->fxp_stats, 634 sizeof(struct fxp_stats), fxp_dma_map_addr, &sc->stats_addr, 0); 635 if (error) { 636 device_printf(dev, "could not map the stats buffer\n"); 637 goto fail; 638 } 639 640 error = bus_dma_tag_create(NULL, 4, 0, BUS_SPACE_MAXADDR_32BIT, 641 BUS_SPACE_MAXADDR, NULL, NULL, FXP_TXCB_SZ, 1, 642 FXP_TXCB_SZ, 0, busdma_lock_mutex, &Giant, &sc->cbl_tag); 643 if (error) { 644 device_printf(dev, "could not allocate dma tag\n"); 645 goto fail; 646 } 647 648 error = bus_dmamem_alloc(sc->cbl_tag, (void **)&sc->fxp_desc.cbl_list, 649 BUS_DMA_NOWAIT | BUS_DMA_ZERO, &sc->cbl_map); 650 if (error) 651 goto fail; 652 653 error = bus_dmamap_load(sc->cbl_tag, sc->cbl_map, 654 sc->fxp_desc.cbl_list, FXP_TXCB_SZ, fxp_dma_map_addr, 655 &sc->fxp_desc.cbl_addr, 0); 656 if (error) { 657 device_printf(dev, "could not map DMA memory\n"); 658 goto fail; 659 } 660 661 error = bus_dma_tag_create(NULL, 4, 0, BUS_SPACE_MAXADDR_32BIT, 662 BUS_SPACE_MAXADDR, NULL, NULL, sizeof(struct fxp_cb_mcs), 1, 663 sizeof(struct fxp_cb_mcs), 0, busdma_lock_mutex, &Giant, 664 &sc->mcs_tag); 665 if (error) { 666 device_printf(dev, "could not allocate dma tag\n"); 667 goto fail; 668 } 669 670 error = bus_dmamem_alloc(sc->mcs_tag, (void **)&sc->mcsp, 671 BUS_DMA_NOWAIT, &sc->mcs_map); 672 if (error) 673 goto fail; 674 error = bus_dmamap_load(sc->mcs_tag, sc->mcs_map, sc->mcsp, 675 sizeof(struct fxp_cb_mcs), fxp_dma_map_addr, &sc->mcs_addr, 0); 676 if (error) { 677 device_printf(dev, "can't map the multicast setup command\n"); 678 goto fail; 679 } 680 681 /* 682 * Pre-allocate the TX DMA maps. 683 */ 684 for (i = 0; i < FXP_NTXCB; i++) { 685 error = bus_dmamap_create(sc->fxp_mtag, 0, 686 &sc->fxp_desc.tx_list[i].tx_map); 687 if (error) { 688 device_printf(dev, "can't create DMA map for TX\n"); 689 goto fail; 690 } 691 } 692 error = bus_dmamap_create(sc->fxp_mtag, 0, &sc->spare_map); 693 if (error) { 694 device_printf(dev, "can't create spare DMA map\n"); 695 goto fail; 696 } 697 698 /* 699 * Pre-allocate our receive buffers. 700 */ 701 sc->fxp_desc.rx_head = sc->fxp_desc.rx_tail = NULL; 702 for (i = 0; i < FXP_NRFABUFS; i++) { 703 rxp = &sc->fxp_desc.rx_list[i]; 704 error = bus_dmamap_create(sc->fxp_mtag, 0, &rxp->rx_map); 705 if (error) { 706 device_printf(dev, "can't create DMA map for RX\n"); 707 goto fail; 708 } 709 if (fxp_add_rfabuf(sc, rxp) != 0) { 710 error = ENOMEM; 711 goto fail; 712 } 713 } 714 715 /* 716 * Read MAC address. 717 */ 718 fxp_read_eeprom(sc, myea, 0, 3); 719 sc->arpcom.ac_enaddr[0] = myea[0] & 0xff; 720 sc->arpcom.ac_enaddr[1] = myea[0] >> 8; 721 sc->arpcom.ac_enaddr[2] = myea[1] & 0xff; 722 sc->arpcom.ac_enaddr[3] = myea[1] >> 8; 723 sc->arpcom.ac_enaddr[4] = myea[2] & 0xff; 724 sc->arpcom.ac_enaddr[5] = myea[2] >> 8; 725 if (bootverbose) { 726 device_printf(dev, "PCI IDs: %04x %04x %04x %04x %04x\n", 727 pci_get_vendor(dev), pci_get_device(dev), 728 pci_get_subvendor(dev), pci_get_subdevice(dev), 729 pci_get_revid(dev)); 730 fxp_read_eeprom(sc, &data, 10, 1); 731 device_printf(dev, "Dynamic Standby mode is %s\n", 732 data & 0x02 ? "enabled" : "disabled"); 733 } 734 735 /* 736 * If this is only a 10Mbps device, then there is no MII, and 737 * the PHY will use a serial interface instead. 738 * 739 * The Seeq 80c24 AutoDUPLEX(tm) Ethernet Interface Adapter 740 * doesn't have a programming interface of any sort. The 741 * media is sensed automatically based on how the link partner 742 * is configured. This is, in essence, manual configuration. 743 */ 744 if (sc->flags & FXP_FLAG_SERIAL_MEDIA) { 745 ifmedia_add(&sc->sc_media, IFM_ETHER|IFM_MANUAL, 0, NULL); 746 ifmedia_set(&sc->sc_media, IFM_ETHER|IFM_MANUAL); 747 } else { 748 if (mii_phy_probe(dev, &sc->miibus, fxp_ifmedia_upd, 749 fxp_ifmedia_sts)) { 750 device_printf(dev, "MII without any PHY!\n"); 751 error = ENXIO; 752 goto fail; 753 } 754 } 755 756 ifp = &sc->arpcom.ac_if; 757 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 758 ifp->if_baudrate = 100000000; 759 ifp->if_init = fxp_init; 760 ifp->if_softc = sc; 761 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 762 ifp->if_ioctl = fxp_ioctl; 763 ifp->if_start = fxp_start; 764 ifp->if_watchdog = fxp_watchdog; 765 766 ifp->if_capabilities = ifp->if_capenable = 0; 767 768 /* Enable checksum offload for 82550 or better chips */ 769 if (sc->flags & FXP_FLAG_EXT_RFA) { 770 ifp->if_hwassist = FXP_CSUM_FEATURES; 771 ifp->if_capabilities |= IFCAP_HWCSUM; 772 ifp->if_capenable |= IFCAP_HWCSUM; 773 } 774 775 #ifdef DEVICE_POLLING 776 /* Inform the world we support polling. */ 777 ifp->if_capabilities |= IFCAP_POLLING; 778 ifp->if_capenable |= IFCAP_POLLING; 779 #endif 780 781 /* 782 * Attach the interface. 783 */ 784 ether_ifattach(ifp, sc->arpcom.ac_enaddr); 785 786 /* 787 * Tell the upper layer(s) we support long frames. 788 * Must appear after the call to ether_ifattach() because 789 * ether_ifattach() sets ifi_hdrlen to the default value. 790 */ 791 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 792 ifp->if_capabilities |= IFCAP_VLAN_MTU; 793 ifp->if_capenable |= IFCAP_VLAN_MTU; /* the hw bits already set */ 794 795 /* 796 * Let the system queue as many packets as we have available 797 * TX descriptors. 798 */ 799 IFQ_SET_MAXLEN(&ifp->if_snd, FXP_NTXCB - 1); 800 ifp->if_snd.ifq_drv_maxlen = FXP_NTXCB - 1; 801 IFQ_SET_READY(&ifp->if_snd); 802 803 /* 804 * Hook our interrupt after all initialization is complete. 805 * XXX This driver has been tested with the INTR_MPSAFFE flag set 806 * however, ifp and its functions are not fully locked so MPSAFE 807 * should not be used unless you can handle potential data loss. 808 */ 809 error = bus_setup_intr(dev, sc->irq, INTR_TYPE_NET | INTR_MPSAFE, 810 fxp_intr, sc, &sc->ih); 811 if (error) { 812 device_printf(dev, "could not setup irq\n"); 813 ether_ifdetach(&sc->arpcom.ac_if); 814 goto fail; 815 } 816 817 fail: 818 splx(s); 819 if (error) 820 fxp_release(sc); 821 return (error); 822 } 823 824 /* 825 * Release all resources. The softc lock should not be held and the 826 * interrupt should already be torn down. 827 */ 828 static void 829 fxp_release(struct fxp_softc *sc) 830 { 831 struct fxp_rx *rxp; 832 struct fxp_tx *txp; 833 int i; 834 835 FXP_LOCK_ASSERT(sc, MA_NOTOWNED); 836 KASSERT(sc->ih == NULL, 837 ("fxp_release() called with intr handle still active")); 838 if (sc->miibus) 839 device_delete_child(sc->dev, sc->miibus); 840 bus_generic_detach(sc->dev); 841 ifmedia_removeall(&sc->sc_media); 842 if (sc->fxp_desc.cbl_list) { 843 bus_dmamap_unload(sc->cbl_tag, sc->cbl_map); 844 bus_dmamem_free(sc->cbl_tag, sc->fxp_desc.cbl_list, 845 sc->cbl_map); 846 } 847 if (sc->fxp_stats) { 848 bus_dmamap_unload(sc->fxp_stag, sc->fxp_smap); 849 bus_dmamem_free(sc->fxp_stag, sc->fxp_stats, sc->fxp_smap); 850 } 851 if (sc->mcsp) { 852 bus_dmamap_unload(sc->mcs_tag, sc->mcs_map); 853 bus_dmamem_free(sc->mcs_tag, sc->mcsp, sc->mcs_map); 854 } 855 if (sc->irq) 856 bus_release_resource(sc->dev, SYS_RES_IRQ, 0, sc->irq); 857 if (sc->mem) 858 bus_release_resource(sc->dev, sc->rtp, sc->rgd, sc->mem); 859 if (sc->fxp_mtag) { 860 for (i = 0; i < FXP_NRFABUFS; i++) { 861 rxp = &sc->fxp_desc.rx_list[i]; 862 if (rxp->rx_mbuf != NULL) { 863 bus_dmamap_sync(sc->fxp_mtag, rxp->rx_map, 864 BUS_DMASYNC_POSTREAD); 865 bus_dmamap_unload(sc->fxp_mtag, rxp->rx_map); 866 m_freem(rxp->rx_mbuf); 867 } 868 bus_dmamap_destroy(sc->fxp_mtag, rxp->rx_map); 869 } 870 bus_dmamap_destroy(sc->fxp_mtag, sc->spare_map); 871 bus_dma_tag_destroy(sc->fxp_mtag); 872 } 873 if (sc->fxp_stag) { 874 for (i = 0; i < FXP_NTXCB; i++) { 875 txp = &sc->fxp_desc.tx_list[i]; 876 if (txp->tx_mbuf != NULL) { 877 bus_dmamap_sync(sc->fxp_mtag, txp->tx_map, 878 BUS_DMASYNC_POSTWRITE); 879 bus_dmamap_unload(sc->fxp_mtag, txp->tx_map); 880 m_freem(txp->tx_mbuf); 881 } 882 bus_dmamap_destroy(sc->fxp_mtag, txp->tx_map); 883 } 884 bus_dma_tag_destroy(sc->fxp_stag); 885 } 886 if (sc->cbl_tag) 887 bus_dma_tag_destroy(sc->cbl_tag); 888 if (sc->mcs_tag) 889 bus_dma_tag_destroy(sc->mcs_tag); 890 891 mtx_destroy(&sc->sc_mtx); 892 } 893 894 /* 895 * Detach interface. 896 */ 897 static int 898 fxp_detach(device_t dev) 899 { 900 struct fxp_softc *sc = device_get_softc(dev); 901 int s; 902 903 FXP_LOCK(sc); 904 s = splimp(); 905 906 sc->suspended = 1; /* Do same thing as we do for suspend */ 907 /* 908 * Close down routes etc. 909 */ 910 ether_ifdetach(&sc->arpcom.ac_if); 911 912 /* 913 * Stop DMA and drop transmit queue, but disable interrupts first. 914 */ 915 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE); 916 fxp_stop(sc); 917 FXP_UNLOCK(sc); 918 919 /* 920 * Unhook interrupt before dropping lock. This is to prevent 921 * races with fxp_intr(). 922 */ 923 bus_teardown_intr(sc->dev, sc->irq, sc->ih); 924 sc->ih = NULL; 925 926 splx(s); 927 928 /* Release our allocated resources. */ 929 fxp_release(sc); 930 return (0); 931 } 932 933 /* 934 * Device shutdown routine. Called at system shutdown after sync. The 935 * main purpose of this routine is to shut off receiver DMA so that 936 * kernel memory doesn't get clobbered during warmboot. 937 */ 938 static int 939 fxp_shutdown(device_t dev) 940 { 941 /* 942 * Make sure that DMA is disabled prior to reboot. Not doing 943 * do could allow DMA to corrupt kernel memory during the 944 * reboot before the driver initializes. 945 */ 946 fxp_stop((struct fxp_softc *) device_get_softc(dev)); 947 return (0); 948 } 949 950 /* 951 * Device suspend routine. Stop the interface and save some PCI 952 * settings in case the BIOS doesn't restore them properly on 953 * resume. 954 */ 955 static int 956 fxp_suspend(device_t dev) 957 { 958 struct fxp_softc *sc = device_get_softc(dev); 959 int i, s; 960 961 FXP_LOCK(sc); 962 s = splimp(); 963 964 fxp_stop(sc); 965 966 for (i = 0; i < 5; i++) 967 sc->saved_maps[i] = pci_read_config(dev, PCIR_BAR(i), 4); 968 sc->saved_biosaddr = pci_read_config(dev, PCIR_BIOS, 4); 969 sc->saved_intline = pci_read_config(dev, PCIR_INTLINE, 1); 970 sc->saved_cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1); 971 sc->saved_lattimer = pci_read_config(dev, PCIR_LATTIMER, 1); 972 973 sc->suspended = 1; 974 975 FXP_UNLOCK(sc); 976 splx(s); 977 return (0); 978 } 979 980 /* 981 * Device resume routine. Restore some PCI settings in case the BIOS 982 * doesn't, re-enable busmastering, and restart the interface if 983 * appropriate. 984 */ 985 static int 986 fxp_resume(device_t dev) 987 { 988 struct fxp_softc *sc = device_get_softc(dev); 989 struct ifnet *ifp = &sc->sc_if; 990 u_int16_t pci_command; 991 int i, s; 992 993 FXP_LOCK(sc); 994 s = splimp(); 995 996 /* better way to do this? */ 997 for (i = 0; i < 5; i++) 998 pci_write_config(dev, PCIR_BAR(i), sc->saved_maps[i], 4); 999 pci_write_config(dev, PCIR_BIOS, sc->saved_biosaddr, 4); 1000 pci_write_config(dev, PCIR_INTLINE, sc->saved_intline, 1); 1001 pci_write_config(dev, PCIR_CACHELNSZ, sc->saved_cachelnsz, 1); 1002 pci_write_config(dev, PCIR_LATTIMER, sc->saved_lattimer, 1); 1003 1004 /* reenable busmastering */ 1005 pci_command = pci_read_config(dev, PCIR_COMMAND, 2); 1006 pci_command |= (PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN); 1007 pci_write_config(dev, PCIR_COMMAND, pci_command, 2); 1008 1009 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET); 1010 DELAY(10); 1011 1012 /* reinitialize interface if necessary */ 1013 if (ifp->if_flags & IFF_UP) 1014 fxp_init_body(sc); 1015 1016 sc->suspended = 0; 1017 1018 FXP_UNLOCK(sc); 1019 splx(s); 1020 return (0); 1021 } 1022 1023 static void 1024 fxp_eeprom_shiftin(struct fxp_softc *sc, int data, int length) 1025 { 1026 u_int16_t reg; 1027 int x; 1028 1029 /* 1030 * Shift in data. 1031 */ 1032 for (x = 1 << (length - 1); x; x >>= 1) { 1033 if (data & x) 1034 reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI; 1035 else 1036 reg = FXP_EEPROM_EECS; 1037 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 1038 DELAY(1); 1039 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK); 1040 DELAY(1); 1041 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 1042 DELAY(1); 1043 } 1044 } 1045 1046 /* 1047 * Read from the serial EEPROM. Basically, you manually shift in 1048 * the read opcode (one bit at a time) and then shift in the address, 1049 * and then you shift out the data (all of this one bit at a time). 1050 * The word size is 16 bits, so you have to provide the address for 1051 * every 16 bits of data. 1052 */ 1053 static u_int16_t 1054 fxp_eeprom_getword(struct fxp_softc *sc, int offset, int autosize) 1055 { 1056 u_int16_t reg, data; 1057 int x; 1058 1059 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 1060 /* 1061 * Shift in read opcode. 1062 */ 1063 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_READ, 3); 1064 /* 1065 * Shift in address. 1066 */ 1067 data = 0; 1068 for (x = 1 << (sc->eeprom_size - 1); x; x >>= 1) { 1069 if (offset & x) 1070 reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI; 1071 else 1072 reg = FXP_EEPROM_EECS; 1073 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 1074 DELAY(1); 1075 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK); 1076 DELAY(1); 1077 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 1078 DELAY(1); 1079 reg = CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO; 1080 data++; 1081 if (autosize && reg == 0) { 1082 sc->eeprom_size = data; 1083 break; 1084 } 1085 } 1086 /* 1087 * Shift out data. 1088 */ 1089 data = 0; 1090 reg = FXP_EEPROM_EECS; 1091 for (x = 1 << 15; x; x >>= 1) { 1092 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK); 1093 DELAY(1); 1094 if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO) 1095 data |= x; 1096 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 1097 DELAY(1); 1098 } 1099 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 1100 DELAY(1); 1101 1102 return (data); 1103 } 1104 1105 static void 1106 fxp_eeprom_putword(struct fxp_softc *sc, int offset, u_int16_t data) 1107 { 1108 int i; 1109 1110 /* 1111 * Erase/write enable. 1112 */ 1113 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 1114 fxp_eeprom_shiftin(sc, 0x4, 3); 1115 fxp_eeprom_shiftin(sc, 0x03 << (sc->eeprom_size - 2), sc->eeprom_size); 1116 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 1117 DELAY(1); 1118 /* 1119 * Shift in write opcode, address, data. 1120 */ 1121 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 1122 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_WRITE, 3); 1123 fxp_eeprom_shiftin(sc, offset, sc->eeprom_size); 1124 fxp_eeprom_shiftin(sc, data, 16); 1125 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 1126 DELAY(1); 1127 /* 1128 * Wait for EEPROM to finish up. 1129 */ 1130 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 1131 DELAY(1); 1132 for (i = 0; i < 1000; i++) { 1133 if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO) 1134 break; 1135 DELAY(50); 1136 } 1137 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 1138 DELAY(1); 1139 /* 1140 * Erase/write disable. 1141 */ 1142 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 1143 fxp_eeprom_shiftin(sc, 0x4, 3); 1144 fxp_eeprom_shiftin(sc, 0, sc->eeprom_size); 1145 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 1146 DELAY(1); 1147 } 1148 1149 /* 1150 * From NetBSD: 1151 * 1152 * Figure out EEPROM size. 1153 * 1154 * 559's can have either 64-word or 256-word EEPROMs, the 558 1155 * datasheet only talks about 64-word EEPROMs, and the 557 datasheet 1156 * talks about the existance of 16 to 256 word EEPROMs. 1157 * 1158 * The only known sizes are 64 and 256, where the 256 version is used 1159 * by CardBus cards to store CIS information. 1160 * 1161 * The address is shifted in msb-to-lsb, and after the last 1162 * address-bit the EEPROM is supposed to output a `dummy zero' bit, 1163 * after which follows the actual data. We try to detect this zero, by 1164 * probing the data-out bit in the EEPROM control register just after 1165 * having shifted in a bit. If the bit is zero, we assume we've 1166 * shifted enough address bits. The data-out should be tri-state, 1167 * before this, which should translate to a logical one. 1168 */ 1169 static void 1170 fxp_autosize_eeprom(struct fxp_softc *sc) 1171 { 1172 1173 /* guess maximum size of 256 words */ 1174 sc->eeprom_size = 8; 1175 1176 /* autosize */ 1177 (void) fxp_eeprom_getword(sc, 0, 1); 1178 } 1179 1180 static void 1181 fxp_read_eeprom(struct fxp_softc *sc, u_short *data, int offset, int words) 1182 { 1183 int i; 1184 1185 for (i = 0; i < words; i++) 1186 data[i] = fxp_eeprom_getword(sc, offset + i, 0); 1187 } 1188 1189 static void 1190 fxp_write_eeprom(struct fxp_softc *sc, u_short *data, int offset, int words) 1191 { 1192 int i; 1193 1194 for (i = 0; i < words; i++) 1195 fxp_eeprom_putword(sc, offset + i, data[i]); 1196 } 1197 1198 static void 1199 fxp_dma_map_txbuf(void *arg, bus_dma_segment_t *segs, int nseg, 1200 bus_size_t mapsize, int error) 1201 { 1202 struct fxp_softc *sc; 1203 struct fxp_cb_tx *txp; 1204 int i; 1205 1206 if (error) 1207 return; 1208 1209 KASSERT(nseg <= FXP_NTXSEG, ("too many DMA segments")); 1210 1211 sc = arg; 1212 txp = sc->fxp_desc.tx_last->tx_next->tx_cb; 1213 for (i = 0; i < nseg; i++) { 1214 KASSERT(segs[i].ds_len <= MCLBYTES, ("segment size too large")); 1215 /* 1216 * If this is an 82550/82551, then we're using extended 1217 * TxCBs _and_ we're using checksum offload. This means 1218 * that the TxCB is really an IPCB. One major difference 1219 * between the two is that with plain extended TxCBs, 1220 * the bottom half of the TxCB contains two entries from 1221 * the TBD array, whereas IPCBs contain just one entry: 1222 * one entry (8 bytes) has been sacrificed for the TCP/IP 1223 * checksum offload control bits. So to make things work 1224 * right, we have to start filling in the TBD array 1225 * starting from a different place depending on whether 1226 * the chip is an 82550/82551 or not. 1227 */ 1228 if (sc->flags & FXP_FLAG_EXT_RFA) { 1229 txp->tbd[i + 1].tb_addr = htole32(segs[i].ds_addr); 1230 txp->tbd[i + 1].tb_size = htole32(segs[i].ds_len); 1231 } else { 1232 txp->tbd[i].tb_addr = htole32(segs[i].ds_addr); 1233 txp->tbd[i].tb_size = htole32(segs[i].ds_len); 1234 } 1235 } 1236 txp->tbd_number = nseg; 1237 } 1238 1239 /* 1240 * Grab the softc lock and call the real fxp_start_body() routine 1241 */ 1242 static void 1243 fxp_start(struct ifnet *ifp) 1244 { 1245 struct fxp_softc *sc = ifp->if_softc; 1246 1247 FXP_LOCK(sc); 1248 fxp_start_body(ifp); 1249 FXP_UNLOCK(sc); 1250 } 1251 1252 /* 1253 * Start packet transmission on the interface. 1254 * This routine must be called with the softc lock held, and is an 1255 * internal entry point only. 1256 */ 1257 static void 1258 fxp_start_body(struct ifnet *ifp) 1259 { 1260 struct fxp_softc *sc = ifp->if_softc; 1261 struct fxp_tx *txp; 1262 struct mbuf *mb_head; 1263 int error; 1264 1265 FXP_LOCK_ASSERT(sc, MA_OWNED); 1266 /* 1267 * See if we need to suspend xmit until the multicast filter 1268 * has been reprogrammed (which can only be done at the head 1269 * of the command chain). 1270 */ 1271 if (sc->need_mcsetup) { 1272 return; 1273 } 1274 1275 txp = NULL; 1276 1277 /* 1278 * We're finished if there is nothing more to add to the list or if 1279 * we're all filled up with buffers to transmit. 1280 * NOTE: One TxCB is reserved to guarantee that fxp_mc_setup() can add 1281 * a NOP command when needed. 1282 */ 1283 while (!IFQ_DRV_IS_EMPTY(&ifp->if_snd) && 1284 sc->tx_queued < FXP_NTXCB - 1) { 1285 1286 /* 1287 * Grab a packet to transmit. 1288 */ 1289 IFQ_DRV_DEQUEUE(&ifp->if_snd, mb_head); 1290 if (mb_head == NULL) 1291 break; 1292 1293 /* 1294 * Get pointer to next available tx desc. 1295 */ 1296 txp = sc->fxp_desc.tx_last->tx_next; 1297 1298 /* 1299 * A note in Appendix B of the Intel 8255x 10/100 Mbps 1300 * Ethernet Controller Family Open Source Software 1301 * Developer Manual says: 1302 * Using software parsing is only allowed with legal 1303 * TCP/IP or UDP/IP packets. 1304 * ... 1305 * For all other datagrams, hardware parsing must 1306 * be used. 1307 * Software parsing appears to truncate ICMP and 1308 * fragmented UDP packets that contain one to three 1309 * bytes in the second (and final) mbuf of the packet. 1310 */ 1311 if (sc->flags & FXP_FLAG_EXT_RFA) 1312 txp->tx_cb->ipcb_ip_activation_high = 1313 FXP_IPCB_HARDWAREPARSING_ENABLE; 1314 1315 /* 1316 * Deal with TCP/IP checksum offload. Note that 1317 * in order for TCP checksum offload to work, 1318 * the pseudo header checksum must have already 1319 * been computed and stored in the checksum field 1320 * in the TCP header. The stack should have 1321 * already done this for us. 1322 */ 1323 1324 if (mb_head->m_pkthdr.csum_flags) { 1325 if (mb_head->m_pkthdr.csum_flags & CSUM_DELAY_DATA) { 1326 txp->tx_cb->ipcb_ip_schedule = 1327 FXP_IPCB_TCPUDP_CHECKSUM_ENABLE; 1328 if (mb_head->m_pkthdr.csum_flags & CSUM_TCP) 1329 txp->tx_cb->ipcb_ip_schedule |= 1330 FXP_IPCB_TCP_PACKET; 1331 } 1332 #ifdef FXP_IP_CSUM_WAR 1333 /* 1334 * XXX The 82550 chip appears to have trouble 1335 * dealing with IP header checksums in very small 1336 * datagrams, namely fragments from 1 to 3 bytes 1337 * in size. For example, say you want to transmit 1338 * a UDP packet of 1473 bytes. The packet will be 1339 * fragmented over two IP datagrams, the latter 1340 * containing only one byte of data. The 82550 will 1341 * botch the header checksum on the 1-byte fragment. 1342 * As long as the datagram contains 4 or more bytes 1343 * of data, you're ok. 1344 * 1345 * The following code attempts to work around this 1346 * problem: if the datagram is less than 38 bytes 1347 * in size (14 bytes ether header, 20 bytes IP header, 1348 * plus 4 bytes of data), we punt and compute the IP 1349 * header checksum by hand. This workaround doesn't 1350 * work very well, however, since it can be fooled 1351 * by things like VLAN tags and IP options that make 1352 * the header sizes/offsets vary. 1353 */ 1354 1355 if (mb_head->m_pkthdr.csum_flags & CSUM_IP) { 1356 if (mb_head->m_pkthdr.len < 38) { 1357 struct ip *ip; 1358 mb_head->m_data += ETHER_HDR_LEN; 1359 ip = mtod(mb_head, struct ip *); 1360 ip->ip_sum = in_cksum(mb_head, 1361 ip->ip_hl << 2); 1362 mb_head->m_data -= ETHER_HDR_LEN; 1363 } else { 1364 txp->tx_cb->ipcb_ip_activation_high = 1365 FXP_IPCB_HARDWAREPARSING_ENABLE; 1366 txp->tx_cb->ipcb_ip_schedule |= 1367 FXP_IPCB_IP_CHECKSUM_ENABLE; 1368 } 1369 } 1370 #endif 1371 } 1372 1373 /* 1374 * Go through each of the mbufs in the chain and initialize 1375 * the transmit buffer descriptors with the physical address 1376 * and size of the mbuf. 1377 */ 1378 error = bus_dmamap_load_mbuf(sc->fxp_mtag, txp->tx_map, 1379 mb_head, fxp_dma_map_txbuf, sc, 0); 1380 1381 if (error && error != EFBIG) { 1382 device_printf(sc->dev, "can't map mbuf (error %d)\n", 1383 error); 1384 m_freem(mb_head); 1385 break; 1386 } 1387 1388 if (error) { 1389 struct mbuf *mn; 1390 1391 /* 1392 * We ran out of segments. We have to recopy this 1393 * mbuf chain first. Bail out if we can't get the 1394 * new buffers. 1395 */ 1396 mn = m_defrag(mb_head, M_DONTWAIT); 1397 if (mn == NULL) { 1398 m_freem(mb_head); 1399 break; 1400 } else { 1401 mb_head = mn; 1402 } 1403 error = bus_dmamap_load_mbuf(sc->fxp_mtag, txp->tx_map, 1404 mb_head, fxp_dma_map_txbuf, sc, 0); 1405 if (error) { 1406 device_printf(sc->dev, 1407 "can't map mbuf (error %d)\n", error); 1408 m_freem(mb_head); 1409 break; 1410 } 1411 } 1412 1413 bus_dmamap_sync(sc->fxp_mtag, txp->tx_map, 1414 BUS_DMASYNC_PREWRITE); 1415 1416 txp->tx_mbuf = mb_head; 1417 txp->tx_cb->cb_status = 0; 1418 txp->tx_cb->byte_count = 0; 1419 if (sc->tx_queued != FXP_CXINT_THRESH - 1) { 1420 txp->tx_cb->cb_command = 1421 htole16(sc->tx_cmd | FXP_CB_COMMAND_SF | 1422 FXP_CB_COMMAND_S); 1423 } else { 1424 txp->tx_cb->cb_command = 1425 htole16(sc->tx_cmd | FXP_CB_COMMAND_SF | 1426 FXP_CB_COMMAND_S | FXP_CB_COMMAND_I); 1427 /* 1428 * Set a 5 second timer just in case we don't hear 1429 * from the card again. 1430 */ 1431 ifp->if_timer = 5; 1432 } 1433 txp->tx_cb->tx_threshold = tx_threshold; 1434 1435 /* 1436 * Advance the end of list forward. 1437 */ 1438 1439 #ifdef __alpha__ 1440 /* 1441 * On platforms which can't access memory in 16-bit 1442 * granularities, we must prevent the card from DMA'ing 1443 * up the status while we update the command field. 1444 * This could cause us to overwrite the completion status. 1445 * XXX This is probably bogus and we're _not_ looking 1446 * for atomicity here. 1447 */ 1448 atomic_clear_16(&sc->fxp_desc.tx_last->tx_cb->cb_command, 1449 htole16(FXP_CB_COMMAND_S)); 1450 #else 1451 sc->fxp_desc.tx_last->tx_cb->cb_command &= 1452 htole16(~FXP_CB_COMMAND_S); 1453 #endif /*__alpha__*/ 1454 sc->fxp_desc.tx_last = txp; 1455 1456 /* 1457 * Advance the beginning of the list forward if there are 1458 * no other packets queued (when nothing is queued, tx_first 1459 * sits on the last TxCB that was sent out). 1460 */ 1461 if (sc->tx_queued == 0) 1462 sc->fxp_desc.tx_first = txp; 1463 1464 sc->tx_queued++; 1465 1466 /* 1467 * Pass packet to bpf if there is a listener. 1468 */ 1469 BPF_MTAP(ifp, mb_head); 1470 } 1471 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE); 1472 1473 /* 1474 * We're finished. If we added to the list, issue a RESUME to get DMA 1475 * going again if suspended. 1476 */ 1477 if (txp != NULL) { 1478 fxp_scb_wait(sc); 1479 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_RESUME); 1480 } 1481 } 1482 1483 #ifdef DEVICE_POLLING 1484 static poll_handler_t fxp_poll; 1485 1486 static void 1487 fxp_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 1488 { 1489 struct fxp_softc *sc = ifp->if_softc; 1490 u_int8_t statack; 1491 1492 FXP_LOCK(sc); 1493 if (!(ifp->if_capenable & IFCAP_POLLING)) { 1494 ether_poll_deregister(ifp); 1495 cmd = POLL_DEREGISTER; 1496 } 1497 if (cmd == POLL_DEREGISTER) { /* final call, enable interrupts */ 1498 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, 0); 1499 FXP_UNLOCK(sc); 1500 return; 1501 } 1502 statack = FXP_SCB_STATACK_CXTNO | FXP_SCB_STATACK_CNA | 1503 FXP_SCB_STATACK_FR; 1504 if (cmd == POLL_AND_CHECK_STATUS) { 1505 u_int8_t tmp; 1506 1507 tmp = CSR_READ_1(sc, FXP_CSR_SCB_STATACK); 1508 if (tmp == 0xff || tmp == 0) { 1509 FXP_UNLOCK(sc); 1510 return; /* nothing to do */ 1511 } 1512 tmp &= ~statack; 1513 /* ack what we can */ 1514 if (tmp != 0) 1515 CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, tmp); 1516 statack |= tmp; 1517 } 1518 fxp_intr_body(sc, ifp, statack, count); 1519 FXP_UNLOCK(sc); 1520 } 1521 #endif /* DEVICE_POLLING */ 1522 1523 /* 1524 * Process interface interrupts. 1525 */ 1526 static void 1527 fxp_intr(void *xsc) 1528 { 1529 struct fxp_softc *sc = xsc; 1530 struct ifnet *ifp = &sc->sc_if; 1531 u_int8_t statack; 1532 1533 FXP_LOCK(sc); 1534 if (sc->suspended) { 1535 FXP_UNLOCK(sc); 1536 return; 1537 } 1538 1539 #ifdef DEVICE_POLLING 1540 if (ifp->if_flags & IFF_POLLING) { 1541 FXP_UNLOCK(sc); 1542 return; 1543 } 1544 if ((ifp->if_capenable & IFCAP_POLLING) && 1545 ether_poll_register(fxp_poll, ifp)) { 1546 /* disable interrupts */ 1547 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE); 1548 FXP_UNLOCK(sc); 1549 fxp_poll(ifp, 0, 1); 1550 return; 1551 } 1552 #endif 1553 while ((statack = CSR_READ_1(sc, FXP_CSR_SCB_STATACK)) != 0) { 1554 /* 1555 * It should not be possible to have all bits set; the 1556 * FXP_SCB_INTR_SWI bit always returns 0 on a read. If 1557 * all bits are set, this may indicate that the card has 1558 * been physically ejected, so ignore it. 1559 */ 1560 if (statack == 0xff) { 1561 FXP_UNLOCK(sc); 1562 return; 1563 } 1564 1565 /* 1566 * First ACK all the interrupts in this pass. 1567 */ 1568 CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, statack); 1569 fxp_intr_body(sc, ifp, statack, -1); 1570 } 1571 FXP_UNLOCK(sc); 1572 } 1573 1574 static void 1575 fxp_txeof(struct fxp_softc *sc) 1576 { 1577 struct fxp_tx *txp; 1578 1579 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREREAD); 1580 for (txp = sc->fxp_desc.tx_first; sc->tx_queued && 1581 (le16toh(txp->tx_cb->cb_status) & FXP_CB_STATUS_C) != 0; 1582 txp = txp->tx_next) { 1583 if (txp->tx_mbuf != NULL) { 1584 bus_dmamap_sync(sc->fxp_mtag, txp->tx_map, 1585 BUS_DMASYNC_POSTWRITE); 1586 bus_dmamap_unload(sc->fxp_mtag, txp->tx_map); 1587 m_freem(txp->tx_mbuf); 1588 txp->tx_mbuf = NULL; 1589 /* clear this to reset csum offload bits */ 1590 txp->tx_cb->tbd[0].tb_addr = 0; 1591 } 1592 sc->tx_queued--; 1593 } 1594 sc->fxp_desc.tx_first = txp; 1595 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE); 1596 } 1597 1598 static void 1599 fxp_intr_body(struct fxp_softc *sc, struct ifnet *ifp, u_int8_t statack, 1600 int count) 1601 { 1602 struct mbuf *m; 1603 struct fxp_rx *rxp; 1604 struct fxp_rfa *rfa; 1605 int rnr = (statack & FXP_SCB_STATACK_RNR) ? 1 : 0; 1606 1607 FXP_LOCK_ASSERT(sc, MA_OWNED); 1608 if (rnr) 1609 sc->rnr++; 1610 #ifdef DEVICE_POLLING 1611 /* Pick up a deferred RNR condition if `count' ran out last time. */ 1612 if (sc->flags & FXP_FLAG_DEFERRED_RNR) { 1613 sc->flags &= ~FXP_FLAG_DEFERRED_RNR; 1614 rnr = 1; 1615 } 1616 #endif 1617 1618 /* 1619 * Free any finished transmit mbuf chains. 1620 * 1621 * Handle the CNA event likt a CXTNO event. It used to 1622 * be that this event (control unit not ready) was not 1623 * encountered, but it is now with the SMPng modifications. 1624 * The exact sequence of events that occur when the interface 1625 * is brought up are different now, and if this event 1626 * goes unhandled, the configuration/rxfilter setup sequence 1627 * can stall for several seconds. The result is that no 1628 * packets go out onto the wire for about 5 to 10 seconds 1629 * after the interface is ifconfig'ed for the first time. 1630 */ 1631 if (statack & (FXP_SCB_STATACK_CXTNO | FXP_SCB_STATACK_CNA)) { 1632 fxp_txeof(sc); 1633 1634 ifp->if_timer = 0; 1635 if (sc->tx_queued == 0) { 1636 if (sc->need_mcsetup) 1637 fxp_mc_setup(sc); 1638 } 1639 /* 1640 * Try to start more packets transmitting. 1641 */ 1642 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1643 fxp_start_body(ifp); 1644 } 1645 1646 /* 1647 * Just return if nothing happened on the receive side. 1648 */ 1649 if (!rnr && (statack & FXP_SCB_STATACK_FR) == 0) 1650 return; 1651 1652 /* 1653 * Process receiver interrupts. If a no-resource (RNR) 1654 * condition exists, get whatever packets we can and 1655 * re-start the receiver. 1656 * 1657 * When using polling, we do not process the list to completion, 1658 * so when we get an RNR interrupt we must defer the restart 1659 * until we hit the last buffer with the C bit set. 1660 * If we run out of cycles and rfa_headm has the C bit set, 1661 * record the pending RNR in the FXP_FLAG_DEFERRED_RNR flag so 1662 * that the info will be used in the subsequent polling cycle. 1663 */ 1664 for (;;) { 1665 rxp = sc->fxp_desc.rx_head; 1666 m = rxp->rx_mbuf; 1667 rfa = (struct fxp_rfa *)(m->m_ext.ext_buf + 1668 RFA_ALIGNMENT_FUDGE); 1669 bus_dmamap_sync(sc->fxp_mtag, rxp->rx_map, 1670 BUS_DMASYNC_POSTREAD); 1671 1672 #ifdef DEVICE_POLLING /* loop at most count times if count >=0 */ 1673 if (count >= 0 && count-- == 0) { 1674 if (rnr) { 1675 /* Defer RNR processing until the next time. */ 1676 sc->flags |= FXP_FLAG_DEFERRED_RNR; 1677 rnr = 0; 1678 } 1679 break; 1680 } 1681 #endif /* DEVICE_POLLING */ 1682 1683 if ((le16toh(rfa->rfa_status) & FXP_RFA_STATUS_C) == 0) 1684 break; 1685 1686 /* 1687 * Advance head forward. 1688 */ 1689 sc->fxp_desc.rx_head = rxp->rx_next; 1690 1691 /* 1692 * Add a new buffer to the receive chain. 1693 * If this fails, the old buffer is recycled 1694 * instead. 1695 */ 1696 if (fxp_add_rfabuf(sc, rxp) == 0) { 1697 int total_len; 1698 1699 /* 1700 * Fetch packet length (the top 2 bits of 1701 * actual_size are flags set by the controller 1702 * upon completion), and drop the packet in case 1703 * of bogus length or CRC errors. 1704 */ 1705 total_len = le16toh(rfa->actual_size) & 0x3fff; 1706 if (total_len < sizeof(struct ether_header) || 1707 total_len > MCLBYTES - RFA_ALIGNMENT_FUDGE - 1708 sc->rfa_size || 1709 le16toh(rfa->rfa_status) & FXP_RFA_STATUS_CRC) { 1710 m_freem(m); 1711 continue; 1712 } 1713 1714 /* Do IP checksum checking. */ 1715 if (le16toh(rfa->rfa_status) & FXP_RFA_STATUS_PARSE) { 1716 if (rfa->rfax_csum_sts & 1717 FXP_RFDX_CS_IP_CSUM_BIT_VALID) 1718 m->m_pkthdr.csum_flags |= 1719 CSUM_IP_CHECKED; 1720 if (rfa->rfax_csum_sts & 1721 FXP_RFDX_CS_IP_CSUM_VALID) 1722 m->m_pkthdr.csum_flags |= 1723 CSUM_IP_VALID; 1724 if ((rfa->rfax_csum_sts & 1725 FXP_RFDX_CS_TCPUDP_CSUM_BIT_VALID) && 1726 (rfa->rfax_csum_sts & 1727 FXP_RFDX_CS_TCPUDP_CSUM_VALID)) { 1728 m->m_pkthdr.csum_flags |= 1729 CSUM_DATA_VALID|CSUM_PSEUDO_HDR; 1730 m->m_pkthdr.csum_data = 0xffff; 1731 } 1732 } 1733 1734 m->m_pkthdr.len = m->m_len = total_len; 1735 m->m_pkthdr.rcvif = ifp; 1736 1737 /* 1738 * Drop locks before calling if_input() since it 1739 * may re-enter fxp_start() in the netisr case. 1740 * This would result in a lock reversal. Better 1741 * performance might be obtained by chaining all 1742 * packets received, dropping the lock, and then 1743 * calling if_input() on each one. 1744 */ 1745 FXP_UNLOCK(sc); 1746 (*ifp->if_input)(ifp, m); 1747 FXP_LOCK(sc); 1748 } 1749 } 1750 if (rnr) { 1751 fxp_scb_wait(sc); 1752 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 1753 sc->fxp_desc.rx_head->rx_addr); 1754 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_START); 1755 } 1756 } 1757 1758 /* 1759 * Update packet in/out/collision statistics. The i82557 doesn't 1760 * allow you to access these counters without doing a fairly 1761 * expensive DMA to get _all_ of the statistics it maintains, so 1762 * we do this operation here only once per second. The statistics 1763 * counters in the kernel are updated from the previous dump-stats 1764 * DMA and then a new dump-stats DMA is started. The on-chip 1765 * counters are zeroed when the DMA completes. If we can't start 1766 * the DMA immediately, we don't wait - we just prepare to read 1767 * them again next time. 1768 */ 1769 static void 1770 fxp_tick(void *xsc) 1771 { 1772 struct fxp_softc *sc = xsc; 1773 struct ifnet *ifp = &sc->sc_if; 1774 struct fxp_stats *sp = sc->fxp_stats; 1775 int s; 1776 1777 FXP_LOCK(sc); 1778 s = splimp(); 1779 bus_dmamap_sync(sc->fxp_stag, sc->fxp_smap, BUS_DMASYNC_POSTREAD); 1780 ifp->if_opackets += le32toh(sp->tx_good); 1781 ifp->if_collisions += le32toh(sp->tx_total_collisions); 1782 if (sp->rx_good) { 1783 ifp->if_ipackets += le32toh(sp->rx_good); 1784 sc->rx_idle_secs = 0; 1785 } else { 1786 /* 1787 * Receiver's been idle for another second. 1788 */ 1789 sc->rx_idle_secs++; 1790 } 1791 ifp->if_ierrors += 1792 le32toh(sp->rx_crc_errors) + 1793 le32toh(sp->rx_alignment_errors) + 1794 le32toh(sp->rx_rnr_errors) + 1795 le32toh(sp->rx_overrun_errors); 1796 /* 1797 * If any transmit underruns occured, bump up the transmit 1798 * threshold by another 512 bytes (64 * 8). 1799 */ 1800 if (sp->tx_underruns) { 1801 ifp->if_oerrors += le32toh(sp->tx_underruns); 1802 if (tx_threshold < 192) 1803 tx_threshold += 64; 1804 } 1805 1806 /* 1807 * Release any xmit buffers that have completed DMA. This isn't 1808 * strictly necessary to do here, but it's advantagous for mbufs 1809 * with external storage to be released in a timely manner rather 1810 * than being defered for a potentially long time. This limits 1811 * the delay to a maximum of one second. 1812 */ 1813 fxp_txeof(sc); 1814 1815 /* 1816 * If we haven't received any packets in FXP_MAC_RX_IDLE seconds, 1817 * then assume the receiver has locked up and attempt to clear 1818 * the condition by reprogramming the multicast filter. This is 1819 * a work-around for a bug in the 82557 where the receiver locks 1820 * up if it gets certain types of garbage in the syncronization 1821 * bits prior to the packet header. This bug is supposed to only 1822 * occur in 10Mbps mode, but has been seen to occur in 100Mbps 1823 * mode as well (perhaps due to a 10/100 speed transition). 1824 */ 1825 if (sc->rx_idle_secs > FXP_MAX_RX_IDLE) { 1826 sc->rx_idle_secs = 0; 1827 fxp_mc_setup(sc); 1828 } 1829 /* 1830 * If there is no pending command, start another stats 1831 * dump. Otherwise punt for now. 1832 */ 1833 if (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) == 0) { 1834 /* 1835 * Start another stats dump. 1836 */ 1837 bus_dmamap_sync(sc->fxp_stag, sc->fxp_smap, 1838 BUS_DMASYNC_PREREAD); 1839 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_DUMPRESET); 1840 } else { 1841 /* 1842 * A previous command is still waiting to be accepted. 1843 * Just zero our copy of the stats and wait for the 1844 * next timer event to update them. 1845 */ 1846 sp->tx_good = 0; 1847 sp->tx_underruns = 0; 1848 sp->tx_total_collisions = 0; 1849 1850 sp->rx_good = 0; 1851 sp->rx_crc_errors = 0; 1852 sp->rx_alignment_errors = 0; 1853 sp->rx_rnr_errors = 0; 1854 sp->rx_overrun_errors = 0; 1855 } 1856 if (sc->miibus != NULL) 1857 mii_tick(device_get_softc(sc->miibus)); 1858 1859 /* 1860 * Schedule another timeout one second from now. 1861 */ 1862 callout_reset(&sc->stat_ch, hz, fxp_tick, sc); 1863 FXP_UNLOCK(sc); 1864 splx(s); 1865 } 1866 1867 /* 1868 * Stop the interface. Cancels the statistics updater and resets 1869 * the interface. 1870 */ 1871 static void 1872 fxp_stop(struct fxp_softc *sc) 1873 { 1874 struct ifnet *ifp = &sc->sc_if; 1875 struct fxp_tx *txp; 1876 int i; 1877 1878 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1879 ifp->if_timer = 0; 1880 1881 #ifdef DEVICE_POLLING 1882 ether_poll_deregister(ifp); 1883 #endif 1884 /* 1885 * Cancel stats updater. 1886 */ 1887 callout_stop(&sc->stat_ch); 1888 1889 /* 1890 * Issue software reset, which also unloads the microcode. 1891 */ 1892 sc->flags &= ~FXP_FLAG_UCODE; 1893 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SOFTWARE_RESET); 1894 DELAY(50); 1895 1896 /* 1897 * Release any xmit buffers. 1898 */ 1899 txp = sc->fxp_desc.tx_list; 1900 if (txp != NULL) { 1901 for (i = 0; i < FXP_NTXCB; i++) { 1902 if (txp[i].tx_mbuf != NULL) { 1903 bus_dmamap_sync(sc->fxp_mtag, txp[i].tx_map, 1904 BUS_DMASYNC_POSTWRITE); 1905 bus_dmamap_unload(sc->fxp_mtag, txp[i].tx_map); 1906 m_freem(txp[i].tx_mbuf); 1907 txp[i].tx_mbuf = NULL; 1908 /* clear this to reset csum offload bits */ 1909 txp[i].tx_cb->tbd[0].tb_addr = 0; 1910 } 1911 } 1912 } 1913 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE); 1914 sc->tx_queued = 0; 1915 } 1916 1917 /* 1918 * Watchdog/transmission transmit timeout handler. Called when a 1919 * transmission is started on the interface, but no interrupt is 1920 * received before the timeout. This usually indicates that the 1921 * card has wedged for some reason. 1922 */ 1923 static void 1924 fxp_watchdog(struct ifnet *ifp) 1925 { 1926 struct fxp_softc *sc = ifp->if_softc; 1927 1928 FXP_LOCK(sc); 1929 device_printf(sc->dev, "device timeout\n"); 1930 ifp->if_oerrors++; 1931 1932 fxp_init_body(sc); 1933 FXP_UNLOCK(sc); 1934 } 1935 1936 /* 1937 * Acquire locks and then call the real initialization function. This 1938 * is necessary because ether_ioctl() calls if_init() and this would 1939 * result in mutex recursion if the mutex was held. 1940 */ 1941 static void 1942 fxp_init(void *xsc) 1943 { 1944 struct fxp_softc *sc = xsc; 1945 1946 FXP_LOCK(sc); 1947 fxp_init_body(sc); 1948 FXP_UNLOCK(sc); 1949 } 1950 1951 /* 1952 * Perform device initialization. This routine must be called with the 1953 * softc lock held. 1954 */ 1955 static void 1956 fxp_init_body(struct fxp_softc *sc) 1957 { 1958 struct ifnet *ifp = &sc->sc_if; 1959 struct fxp_cb_config *cbp; 1960 struct fxp_cb_ias *cb_ias; 1961 struct fxp_cb_tx *tcbp; 1962 struct fxp_tx *txp; 1963 struct fxp_cb_mcs *mcsp; 1964 int i, prm, s; 1965 1966 FXP_LOCK_ASSERT(sc, MA_OWNED); 1967 s = splimp(); 1968 /* 1969 * Cancel any pending I/O 1970 */ 1971 fxp_stop(sc); 1972 1973 prm = (ifp->if_flags & IFF_PROMISC) ? 1 : 0; 1974 1975 /* 1976 * Initialize base of CBL and RFA memory. Loading with zero 1977 * sets it up for regular linear addressing. 1978 */ 1979 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 0); 1980 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_BASE); 1981 1982 fxp_scb_wait(sc); 1983 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_BASE); 1984 1985 /* 1986 * Initialize base of dump-stats buffer. 1987 */ 1988 fxp_scb_wait(sc); 1989 bus_dmamap_sync(sc->fxp_stag, sc->fxp_smap, BUS_DMASYNC_PREREAD); 1990 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->stats_addr); 1991 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_DUMP_ADR); 1992 1993 /* 1994 * Attempt to load microcode if requested. 1995 */ 1996 if (ifp->if_flags & IFF_LINK0 && (sc->flags & FXP_FLAG_UCODE) == 0) 1997 fxp_load_ucode(sc); 1998 1999 /* 2000 * Initialize the multicast address list. 2001 */ 2002 if (fxp_mc_addrs(sc)) { 2003 mcsp = sc->mcsp; 2004 mcsp->cb_status = 0; 2005 mcsp->cb_command = 2006 htole16(FXP_CB_COMMAND_MCAS | FXP_CB_COMMAND_EL); 2007 mcsp->link_addr = 0xffffffff; 2008 /* 2009 * Start the multicast setup command. 2010 */ 2011 fxp_scb_wait(sc); 2012 bus_dmamap_sync(sc->mcs_tag, sc->mcs_map, BUS_DMASYNC_PREWRITE); 2013 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->mcs_addr); 2014 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2015 /* ...and wait for it to complete. */ 2016 fxp_dma_wait(sc, &mcsp->cb_status, sc->mcs_tag, sc->mcs_map); 2017 bus_dmamap_sync(sc->mcs_tag, sc->mcs_map, 2018 BUS_DMASYNC_POSTWRITE); 2019 } 2020 2021 /* 2022 * We temporarily use memory that contains the TxCB list to 2023 * construct the config CB. The TxCB list memory is rebuilt 2024 * later. 2025 */ 2026 cbp = (struct fxp_cb_config *)sc->fxp_desc.cbl_list; 2027 2028 /* 2029 * This bcopy is kind of disgusting, but there are a bunch of must be 2030 * zero and must be one bits in this structure and this is the easiest 2031 * way to initialize them all to proper values. 2032 */ 2033 bcopy(fxp_cb_config_template, cbp, sizeof(fxp_cb_config_template)); 2034 2035 cbp->cb_status = 0; 2036 cbp->cb_command = htole16(FXP_CB_COMMAND_CONFIG | 2037 FXP_CB_COMMAND_EL); 2038 cbp->link_addr = 0xffffffff; /* (no) next command */ 2039 cbp->byte_count = sc->flags & FXP_FLAG_EXT_RFA ? 32 : 22; 2040 cbp->rx_fifo_limit = 8; /* rx fifo threshold (32 bytes) */ 2041 cbp->tx_fifo_limit = 0; /* tx fifo threshold (0 bytes) */ 2042 cbp->adaptive_ifs = 0; /* (no) adaptive interframe spacing */ 2043 cbp->mwi_enable = sc->flags & FXP_FLAG_MWI_ENABLE ? 1 : 0; 2044 cbp->type_enable = 0; /* actually reserved */ 2045 cbp->read_align_en = sc->flags & FXP_FLAG_READ_ALIGN ? 1 : 0; 2046 cbp->end_wr_on_cl = sc->flags & FXP_FLAG_WRITE_ALIGN ? 1 : 0; 2047 cbp->rx_dma_bytecount = 0; /* (no) rx DMA max */ 2048 cbp->tx_dma_bytecount = 0; /* (no) tx DMA max */ 2049 cbp->dma_mbce = 0; /* (disable) dma max counters */ 2050 cbp->late_scb = 0; /* (don't) defer SCB update */ 2051 cbp->direct_dma_dis = 1; /* disable direct rcv dma mode */ 2052 cbp->tno_int_or_tco_en =0; /* (disable) tx not okay interrupt */ 2053 cbp->ci_int = 1; /* interrupt on CU idle */ 2054 cbp->ext_txcb_dis = sc->flags & FXP_FLAG_EXT_TXCB ? 0 : 1; 2055 cbp->ext_stats_dis = 1; /* disable extended counters */ 2056 cbp->keep_overrun_rx = 0; /* don't pass overrun frames to host */ 2057 cbp->save_bf = sc->flags & FXP_FLAG_SAVE_BAD ? 1 : prm; 2058 cbp->disc_short_rx = !prm; /* discard short packets */ 2059 cbp->underrun_retry = 1; /* retry mode (once) on DMA underrun */ 2060 cbp->two_frames = 0; /* do not limit FIFO to 2 frames */ 2061 cbp->dyn_tbd = 0; /* (no) dynamic TBD mode */ 2062 cbp->ext_rfa = sc->flags & FXP_FLAG_EXT_RFA ? 1 : 0; 2063 cbp->mediatype = sc->flags & FXP_FLAG_SERIAL_MEDIA ? 0 : 1; 2064 cbp->csma_dis = 0; /* (don't) disable link */ 2065 cbp->tcp_udp_cksum = 0; /* (don't) enable checksum */ 2066 cbp->vlan_tco = 0; /* (don't) enable vlan wakeup */ 2067 cbp->link_wake_en = 0; /* (don't) assert PME# on link change */ 2068 cbp->arp_wake_en = 0; /* (don't) assert PME# on arp */ 2069 cbp->mc_wake_en = 0; /* (don't) enable PME# on mcmatch */ 2070 cbp->nsai = 1; /* (don't) disable source addr insert */ 2071 cbp->preamble_length = 2; /* (7 byte) preamble */ 2072 cbp->loopback = 0; /* (don't) loopback */ 2073 cbp->linear_priority = 0; /* (normal CSMA/CD operation) */ 2074 cbp->linear_pri_mode = 0; /* (wait after xmit only) */ 2075 cbp->interfrm_spacing = 6; /* (96 bits of) interframe spacing */ 2076 cbp->promiscuous = prm; /* promiscuous mode */ 2077 cbp->bcast_disable = 0; /* (don't) disable broadcasts */ 2078 cbp->wait_after_win = 0; /* (don't) enable modified backoff alg*/ 2079 cbp->ignore_ul = 0; /* consider U/L bit in IA matching */ 2080 cbp->crc16_en = 0; /* (don't) enable crc-16 algorithm */ 2081 cbp->crscdt = sc->flags & FXP_FLAG_SERIAL_MEDIA ? 1 : 0; 2082 2083 cbp->stripping = !prm; /* truncate rx packet to byte count */ 2084 cbp->padding = 1; /* (do) pad short tx packets */ 2085 cbp->rcv_crc_xfer = 0; /* (don't) xfer CRC to host */ 2086 cbp->long_rx_en = sc->flags & FXP_FLAG_LONG_PKT_EN ? 1 : 0; 2087 cbp->ia_wake_en = 0; /* (don't) wake up on address match */ 2088 cbp->magic_pkt_dis = 0; /* (don't) disable magic packet */ 2089 /* must set wake_en in PMCSR also */ 2090 cbp->force_fdx = 0; /* (don't) force full duplex */ 2091 cbp->fdx_pin_en = 1; /* (enable) FDX# pin */ 2092 cbp->multi_ia = 0; /* (don't) accept multiple IAs */ 2093 cbp->mc_all = sc->flags & FXP_FLAG_ALL_MCAST ? 1 : 0; 2094 cbp->gamla_rx = sc->flags & FXP_FLAG_EXT_RFA ? 1 : 0; 2095 2096 if (sc->tunable_noflow || sc->revision == FXP_REV_82557) { 2097 /* 2098 * The 82557 has no hardware flow control, the values 2099 * below are the defaults for the chip. 2100 */ 2101 cbp->fc_delay_lsb = 0; 2102 cbp->fc_delay_msb = 0x40; 2103 cbp->pri_fc_thresh = 3; 2104 cbp->tx_fc_dis = 0; 2105 cbp->rx_fc_restop = 0; 2106 cbp->rx_fc_restart = 0; 2107 cbp->fc_filter = 0; 2108 cbp->pri_fc_loc = 1; 2109 } else { 2110 cbp->fc_delay_lsb = 0x1f; 2111 cbp->fc_delay_msb = 0x01; 2112 cbp->pri_fc_thresh = 3; 2113 cbp->tx_fc_dis = 0; /* enable transmit FC */ 2114 cbp->rx_fc_restop = 1; /* enable FC restop frames */ 2115 cbp->rx_fc_restart = 1; /* enable FC restart frames */ 2116 cbp->fc_filter = !prm; /* drop FC frames to host */ 2117 cbp->pri_fc_loc = 1; /* FC pri location (byte31) */ 2118 } 2119 2120 /* 2121 * Start the config command/DMA. 2122 */ 2123 fxp_scb_wait(sc); 2124 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE); 2125 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->fxp_desc.cbl_addr); 2126 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2127 /* ...and wait for it to complete. */ 2128 fxp_dma_wait(sc, &cbp->cb_status, sc->cbl_tag, sc->cbl_map); 2129 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_POSTWRITE); 2130 2131 /* 2132 * Now initialize the station address. Temporarily use the TxCB 2133 * memory area like we did above for the config CB. 2134 */ 2135 cb_ias = (struct fxp_cb_ias *)sc->fxp_desc.cbl_list; 2136 cb_ias->cb_status = 0; 2137 cb_ias->cb_command = htole16(FXP_CB_COMMAND_IAS | FXP_CB_COMMAND_EL); 2138 cb_ias->link_addr = 0xffffffff; 2139 bcopy(sc->arpcom.ac_enaddr, cb_ias->macaddr, 2140 sizeof(sc->arpcom.ac_enaddr)); 2141 2142 /* 2143 * Start the IAS (Individual Address Setup) command/DMA. 2144 */ 2145 fxp_scb_wait(sc); 2146 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE); 2147 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2148 /* ...and wait for it to complete. */ 2149 fxp_dma_wait(sc, &cb_ias->cb_status, sc->cbl_tag, sc->cbl_map); 2150 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_POSTWRITE); 2151 2152 /* 2153 * Initialize transmit control block (TxCB) list. 2154 */ 2155 txp = sc->fxp_desc.tx_list; 2156 tcbp = sc->fxp_desc.cbl_list; 2157 bzero(tcbp, FXP_TXCB_SZ); 2158 for (i = 0; i < FXP_NTXCB; i++) { 2159 txp[i].tx_cb = tcbp + i; 2160 txp[i].tx_mbuf = NULL; 2161 tcbp[i].cb_status = htole16(FXP_CB_STATUS_C | FXP_CB_STATUS_OK); 2162 tcbp[i].cb_command = htole16(FXP_CB_COMMAND_NOP); 2163 tcbp[i].link_addr = htole32(sc->fxp_desc.cbl_addr + 2164 (((i + 1) & FXP_TXCB_MASK) * sizeof(struct fxp_cb_tx))); 2165 if (sc->flags & FXP_FLAG_EXT_TXCB) 2166 tcbp[i].tbd_array_addr = 2167 htole32(FXP_TXCB_DMA_ADDR(sc, &tcbp[i].tbd[2])); 2168 else 2169 tcbp[i].tbd_array_addr = 2170 htole32(FXP_TXCB_DMA_ADDR(sc, &tcbp[i].tbd[0])); 2171 txp[i].tx_next = &txp[(i + 1) & FXP_TXCB_MASK]; 2172 } 2173 /* 2174 * Set the suspend flag on the first TxCB and start the control 2175 * unit. It will execute the NOP and then suspend. 2176 */ 2177 tcbp->cb_command = htole16(FXP_CB_COMMAND_NOP | FXP_CB_COMMAND_S); 2178 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE); 2179 sc->fxp_desc.tx_first = sc->fxp_desc.tx_last = txp; 2180 sc->tx_queued = 1; 2181 2182 fxp_scb_wait(sc); 2183 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2184 2185 /* 2186 * Initialize receiver buffer area - RFA. 2187 */ 2188 fxp_scb_wait(sc); 2189 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->fxp_desc.rx_head->rx_addr); 2190 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_START); 2191 2192 /* 2193 * Set current media. 2194 */ 2195 if (sc->miibus != NULL) 2196 mii_mediachg(device_get_softc(sc->miibus)); 2197 2198 ifp->if_flags |= IFF_RUNNING; 2199 ifp->if_flags &= ~IFF_OACTIVE; 2200 2201 /* 2202 * Enable interrupts. 2203 */ 2204 #ifdef DEVICE_POLLING 2205 /* 2206 * ... but only do that if we are not polling. And because (presumably) 2207 * the default is interrupts on, we need to disable them explicitly! 2208 */ 2209 if ( ifp->if_flags & IFF_POLLING ) 2210 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE); 2211 else 2212 #endif /* DEVICE_POLLING */ 2213 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, 0); 2214 2215 /* 2216 * Start stats updater. 2217 */ 2218 callout_reset(&sc->stat_ch, hz, fxp_tick, sc); 2219 splx(s); 2220 } 2221 2222 static int 2223 fxp_serial_ifmedia_upd(struct ifnet *ifp) 2224 { 2225 2226 return (0); 2227 } 2228 2229 static void 2230 fxp_serial_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 2231 { 2232 2233 ifmr->ifm_active = IFM_ETHER|IFM_MANUAL; 2234 } 2235 2236 /* 2237 * Change media according to request. 2238 */ 2239 static int 2240 fxp_ifmedia_upd(struct ifnet *ifp) 2241 { 2242 struct fxp_softc *sc = ifp->if_softc; 2243 struct mii_data *mii; 2244 2245 mii = device_get_softc(sc->miibus); 2246 mii_mediachg(mii); 2247 return (0); 2248 } 2249 2250 /* 2251 * Notify the world which media we're using. 2252 */ 2253 static void 2254 fxp_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 2255 { 2256 struct fxp_softc *sc = ifp->if_softc; 2257 struct mii_data *mii; 2258 2259 mii = device_get_softc(sc->miibus); 2260 mii_pollstat(mii); 2261 ifmr->ifm_active = mii->mii_media_active; 2262 ifmr->ifm_status = mii->mii_media_status; 2263 2264 if (ifmr->ifm_status & IFM_10_T && sc->flags & FXP_FLAG_CU_RESUME_BUG) 2265 sc->cu_resume_bug = 1; 2266 else 2267 sc->cu_resume_bug = 0; 2268 } 2269 2270 /* 2271 * Add a buffer to the end of the RFA buffer list. 2272 * Return 0 if successful, 1 for failure. A failure results in 2273 * adding the 'oldm' (if non-NULL) on to the end of the list - 2274 * tossing out its old contents and recycling it. 2275 * The RFA struct is stuck at the beginning of mbuf cluster and the 2276 * data pointer is fixed up to point just past it. 2277 */ 2278 static int 2279 fxp_add_rfabuf(struct fxp_softc *sc, struct fxp_rx *rxp) 2280 { 2281 struct mbuf *m; 2282 struct fxp_rfa *rfa, *p_rfa; 2283 struct fxp_rx *p_rx; 2284 bus_dmamap_t tmp_map; 2285 int error; 2286 2287 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 2288 if (m == NULL) 2289 return (ENOBUFS); 2290 2291 /* 2292 * Move the data pointer up so that the incoming data packet 2293 * will be 32-bit aligned. 2294 */ 2295 m->m_data += RFA_ALIGNMENT_FUDGE; 2296 2297 /* 2298 * Get a pointer to the base of the mbuf cluster and move 2299 * data start past it. 2300 */ 2301 rfa = mtod(m, struct fxp_rfa *); 2302 m->m_data += sc->rfa_size; 2303 rfa->size = htole16(MCLBYTES - sc->rfa_size - RFA_ALIGNMENT_FUDGE); 2304 2305 rfa->rfa_status = 0; 2306 rfa->rfa_control = htole16(FXP_RFA_CONTROL_EL); 2307 rfa->actual_size = 0; 2308 2309 /* 2310 * Initialize the rest of the RFA. Note that since the RFA 2311 * is misaligned, we cannot store values directly. We're thus 2312 * using the le32enc() function which handles endianness and 2313 * is also alignment-safe. 2314 */ 2315 le32enc(&rfa->link_addr, 0xffffffff); 2316 le32enc(&rfa->rbd_addr, 0xffffffff); 2317 2318 /* Map the RFA into DMA memory. */ 2319 error = bus_dmamap_load(sc->fxp_mtag, sc->spare_map, rfa, 2320 MCLBYTES - RFA_ALIGNMENT_FUDGE, fxp_dma_map_addr, 2321 &rxp->rx_addr, 0); 2322 if (error) { 2323 m_freem(m); 2324 return (error); 2325 } 2326 2327 bus_dmamap_unload(sc->fxp_mtag, rxp->rx_map); 2328 tmp_map = sc->spare_map; 2329 sc->spare_map = rxp->rx_map; 2330 rxp->rx_map = tmp_map; 2331 rxp->rx_mbuf = m; 2332 2333 bus_dmamap_sync(sc->fxp_mtag, rxp->rx_map, 2334 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2335 2336 /* 2337 * If there are other buffers already on the list, attach this 2338 * one to the end by fixing up the tail to point to this one. 2339 */ 2340 if (sc->fxp_desc.rx_head != NULL) { 2341 p_rx = sc->fxp_desc.rx_tail; 2342 p_rfa = (struct fxp_rfa *) 2343 (p_rx->rx_mbuf->m_ext.ext_buf + RFA_ALIGNMENT_FUDGE); 2344 p_rx->rx_next = rxp; 2345 le32enc(&p_rfa->link_addr, rxp->rx_addr); 2346 p_rfa->rfa_control = 0; 2347 bus_dmamap_sync(sc->fxp_mtag, p_rx->rx_map, 2348 BUS_DMASYNC_PREWRITE); 2349 } else { 2350 rxp->rx_next = NULL; 2351 sc->fxp_desc.rx_head = rxp; 2352 } 2353 sc->fxp_desc.rx_tail = rxp; 2354 return (0); 2355 } 2356 2357 static volatile int 2358 fxp_miibus_readreg(device_t dev, int phy, int reg) 2359 { 2360 struct fxp_softc *sc = device_get_softc(dev); 2361 int count = 10000; 2362 int value; 2363 2364 CSR_WRITE_4(sc, FXP_CSR_MDICONTROL, 2365 (FXP_MDI_READ << 26) | (reg << 16) | (phy << 21)); 2366 2367 while (((value = CSR_READ_4(sc, FXP_CSR_MDICONTROL)) & 0x10000000) == 0 2368 && count--) 2369 DELAY(10); 2370 2371 if (count <= 0) 2372 device_printf(dev, "fxp_miibus_readreg: timed out\n"); 2373 2374 return (value & 0xffff); 2375 } 2376 2377 static void 2378 fxp_miibus_writereg(device_t dev, int phy, int reg, int value) 2379 { 2380 struct fxp_softc *sc = device_get_softc(dev); 2381 int count = 10000; 2382 2383 CSR_WRITE_4(sc, FXP_CSR_MDICONTROL, 2384 (FXP_MDI_WRITE << 26) | (reg << 16) | (phy << 21) | 2385 (value & 0xffff)); 2386 2387 while ((CSR_READ_4(sc, FXP_CSR_MDICONTROL) & 0x10000000) == 0 && 2388 count--) 2389 DELAY(10); 2390 2391 if (count <= 0) 2392 device_printf(dev, "fxp_miibus_writereg: timed out\n"); 2393 } 2394 2395 static int 2396 fxp_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 2397 { 2398 struct fxp_softc *sc = ifp->if_softc; 2399 struct ifreq *ifr = (struct ifreq *)data; 2400 struct mii_data *mii; 2401 int flag, mask, s, error = 0; 2402 2403 /* 2404 * Detaching causes us to call ioctl with the mutex owned. Preclude 2405 * that by saying we're busy if the lock is already held. 2406 */ 2407 if (FXP_LOCKED(sc)) 2408 return (EBUSY); 2409 2410 FXP_LOCK(sc); 2411 s = splimp(); 2412 2413 switch (command) { 2414 case SIOCSIFFLAGS: 2415 if (ifp->if_flags & IFF_ALLMULTI) 2416 sc->flags |= FXP_FLAG_ALL_MCAST; 2417 else 2418 sc->flags &= ~FXP_FLAG_ALL_MCAST; 2419 2420 /* 2421 * If interface is marked up and not running, then start it. 2422 * If it is marked down and running, stop it. 2423 * XXX If it's up then re-initialize it. This is so flags 2424 * such as IFF_PROMISC are handled. 2425 */ 2426 if (ifp->if_flags & IFF_UP) { 2427 fxp_init_body(sc); 2428 } else { 2429 if (ifp->if_flags & IFF_RUNNING) 2430 fxp_stop(sc); 2431 } 2432 break; 2433 2434 case SIOCADDMULTI: 2435 case SIOCDELMULTI: 2436 if (ifp->if_flags & IFF_ALLMULTI) 2437 sc->flags |= FXP_FLAG_ALL_MCAST; 2438 else 2439 sc->flags &= ~FXP_FLAG_ALL_MCAST; 2440 /* 2441 * Multicast list has changed; set the hardware filter 2442 * accordingly. 2443 */ 2444 if ((sc->flags & FXP_FLAG_ALL_MCAST) == 0) 2445 fxp_mc_setup(sc); 2446 /* 2447 * fxp_mc_setup() can set FXP_FLAG_ALL_MCAST, so check it 2448 * again rather than else {}. 2449 */ 2450 if (sc->flags & FXP_FLAG_ALL_MCAST) 2451 fxp_init_body(sc); 2452 error = 0; 2453 break; 2454 2455 case SIOCSIFMEDIA: 2456 case SIOCGIFMEDIA: 2457 if (sc->miibus != NULL) { 2458 mii = device_get_softc(sc->miibus); 2459 error = ifmedia_ioctl(ifp, ifr, 2460 &mii->mii_media, command); 2461 } else { 2462 error = ifmedia_ioctl(ifp, ifr, &sc->sc_media, command); 2463 } 2464 break; 2465 2466 case SIOCSIFCAP: 2467 mask = ifp->if_capenable ^ ifr->ifr_reqcap; 2468 if (mask & IFCAP_POLLING) 2469 ifp->if_capenable ^= IFCAP_POLLING; 2470 if (mask & IFCAP_VLAN_MTU) { 2471 ifp->if_capenable ^= IFCAP_VLAN_MTU; 2472 if (sc->revision != FXP_REV_82557) 2473 flag = FXP_FLAG_LONG_PKT_EN; 2474 else /* a hack to get long frames on the old chip */ 2475 flag = FXP_FLAG_SAVE_BAD; 2476 sc->flags ^= flag; 2477 if (ifp->if_flags & IFF_UP) 2478 fxp_init_body(sc); 2479 } 2480 break; 2481 2482 default: 2483 /* 2484 * ether_ioctl() will eventually call fxp_start() which 2485 * will result in mutex recursion so drop it first. 2486 */ 2487 FXP_UNLOCK(sc); 2488 error = ether_ioctl(ifp, command, data); 2489 } 2490 if (FXP_LOCKED(sc)) 2491 FXP_UNLOCK(sc); 2492 splx(s); 2493 return (error); 2494 } 2495 2496 /* 2497 * Fill in the multicast address list and return number of entries. 2498 */ 2499 static int 2500 fxp_mc_addrs(struct fxp_softc *sc) 2501 { 2502 struct fxp_cb_mcs *mcsp = sc->mcsp; 2503 struct ifnet *ifp = &sc->sc_if; 2504 struct ifmultiaddr *ifma; 2505 int nmcasts; 2506 2507 nmcasts = 0; 2508 if ((sc->flags & FXP_FLAG_ALL_MCAST) == 0) { 2509 #if __FreeBSD_version < 500000 2510 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 2511 #else 2512 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 2513 #endif 2514 if (ifma->ifma_addr->sa_family != AF_LINK) 2515 continue; 2516 if (nmcasts >= MAXMCADDR) { 2517 sc->flags |= FXP_FLAG_ALL_MCAST; 2518 nmcasts = 0; 2519 break; 2520 } 2521 bcopy(LLADDR((struct sockaddr_dl *)ifma->ifma_addr), 2522 &sc->mcsp->mc_addr[nmcasts][0], ETHER_ADDR_LEN); 2523 nmcasts++; 2524 } 2525 } 2526 mcsp->mc_cnt = htole16(nmcasts * ETHER_ADDR_LEN); 2527 return (nmcasts); 2528 } 2529 2530 /* 2531 * Program the multicast filter. 2532 * 2533 * We have an artificial restriction that the multicast setup command 2534 * must be the first command in the chain, so we take steps to ensure 2535 * this. By requiring this, it allows us to keep up the performance of 2536 * the pre-initialized command ring (esp. link pointers) by not actually 2537 * inserting the mcsetup command in the ring - i.e. its link pointer 2538 * points to the TxCB ring, but the mcsetup descriptor itself is not part 2539 * of it. We then can do 'CU_START' on the mcsetup descriptor and have it 2540 * lead into the regular TxCB ring when it completes. 2541 * 2542 * This function must be called at splimp. 2543 */ 2544 static void 2545 fxp_mc_setup(struct fxp_softc *sc) 2546 { 2547 struct fxp_cb_mcs *mcsp = sc->mcsp; 2548 struct ifnet *ifp = &sc->sc_if; 2549 struct fxp_tx *txp; 2550 int count; 2551 2552 FXP_LOCK_ASSERT(sc, MA_OWNED); 2553 /* 2554 * If there are queued commands, we must wait until they are all 2555 * completed. If we are already waiting, then add a NOP command 2556 * with interrupt option so that we're notified when all commands 2557 * have been completed - fxp_start() ensures that no additional 2558 * TX commands will be added when need_mcsetup is true. 2559 */ 2560 if (sc->tx_queued) { 2561 /* 2562 * need_mcsetup will be true if we are already waiting for the 2563 * NOP command to be completed (see below). In this case, bail. 2564 */ 2565 if (sc->need_mcsetup) 2566 return; 2567 sc->need_mcsetup = 1; 2568 2569 /* 2570 * Add a NOP command with interrupt so that we are notified 2571 * when all TX commands have been processed. 2572 */ 2573 txp = sc->fxp_desc.tx_last->tx_next; 2574 txp->tx_mbuf = NULL; 2575 txp->tx_cb->cb_status = 0; 2576 txp->tx_cb->cb_command = htole16(FXP_CB_COMMAND_NOP | 2577 FXP_CB_COMMAND_S | FXP_CB_COMMAND_I); 2578 /* 2579 * Advance the end of list forward. 2580 */ 2581 sc->fxp_desc.tx_last->tx_cb->cb_command &= 2582 htole16(~FXP_CB_COMMAND_S); 2583 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE); 2584 sc->fxp_desc.tx_last = txp; 2585 sc->tx_queued++; 2586 /* 2587 * Issue a resume in case the CU has just suspended. 2588 */ 2589 fxp_scb_wait(sc); 2590 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_RESUME); 2591 /* 2592 * Set a 5 second timer just in case we don't hear from the 2593 * card again. 2594 */ 2595 ifp->if_timer = 5; 2596 2597 return; 2598 } 2599 sc->need_mcsetup = 0; 2600 2601 /* 2602 * Initialize multicast setup descriptor. 2603 */ 2604 mcsp->cb_status = 0; 2605 mcsp->cb_command = htole16(FXP_CB_COMMAND_MCAS | 2606 FXP_CB_COMMAND_S | FXP_CB_COMMAND_I); 2607 mcsp->link_addr = htole32(sc->fxp_desc.cbl_addr); 2608 txp = &sc->fxp_desc.mcs_tx; 2609 txp->tx_mbuf = NULL; 2610 txp->tx_cb = (struct fxp_cb_tx *)sc->mcsp; 2611 txp->tx_next = sc->fxp_desc.tx_list; 2612 (void) fxp_mc_addrs(sc); 2613 sc->fxp_desc.tx_first = sc->fxp_desc.tx_last = txp; 2614 sc->tx_queued = 1; 2615 2616 /* 2617 * Wait until command unit is not active. This should never 2618 * be the case when nothing is queued, but make sure anyway. 2619 */ 2620 count = 100; 2621 while ((CSR_READ_1(sc, FXP_CSR_SCB_RUSCUS) >> 6) == 2622 FXP_SCB_CUS_ACTIVE && --count) 2623 DELAY(10); 2624 if (count == 0) { 2625 device_printf(sc->dev, "command queue timeout\n"); 2626 return; 2627 } 2628 2629 /* 2630 * Start the multicast setup command. 2631 */ 2632 fxp_scb_wait(sc); 2633 bus_dmamap_sync(sc->mcs_tag, sc->mcs_map, BUS_DMASYNC_PREWRITE); 2634 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->mcs_addr); 2635 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2636 2637 ifp->if_timer = 2; 2638 return; 2639 } 2640 2641 static u_int32_t fxp_ucode_d101a[] = D101_A_RCVBUNDLE_UCODE; 2642 static u_int32_t fxp_ucode_d101b0[] = D101_B0_RCVBUNDLE_UCODE; 2643 static u_int32_t fxp_ucode_d101ma[] = D101M_B_RCVBUNDLE_UCODE; 2644 static u_int32_t fxp_ucode_d101s[] = D101S_RCVBUNDLE_UCODE; 2645 static u_int32_t fxp_ucode_d102[] = D102_B_RCVBUNDLE_UCODE; 2646 static u_int32_t fxp_ucode_d102c[] = D102_C_RCVBUNDLE_UCODE; 2647 2648 #define UCODE(x) x, sizeof(x) 2649 2650 struct ucode { 2651 u_int32_t revision; 2652 u_int32_t *ucode; 2653 int length; 2654 u_short int_delay_offset; 2655 u_short bundle_max_offset; 2656 } ucode_table[] = { 2657 { FXP_REV_82558_A4, UCODE(fxp_ucode_d101a), D101_CPUSAVER_DWORD, 0 }, 2658 { FXP_REV_82558_B0, UCODE(fxp_ucode_d101b0), D101_CPUSAVER_DWORD, 0 }, 2659 { FXP_REV_82559_A0, UCODE(fxp_ucode_d101ma), 2660 D101M_CPUSAVER_DWORD, D101M_CPUSAVER_BUNDLE_MAX_DWORD }, 2661 { FXP_REV_82559S_A, UCODE(fxp_ucode_d101s), 2662 D101S_CPUSAVER_DWORD, D101S_CPUSAVER_BUNDLE_MAX_DWORD }, 2663 { FXP_REV_82550, UCODE(fxp_ucode_d102), 2664 D102_B_CPUSAVER_DWORD, D102_B_CPUSAVER_BUNDLE_MAX_DWORD }, 2665 { FXP_REV_82550_C, UCODE(fxp_ucode_d102c), 2666 D102_C_CPUSAVER_DWORD, D102_C_CPUSAVER_BUNDLE_MAX_DWORD }, 2667 { 0, NULL, 0, 0, 0 } 2668 }; 2669 2670 static void 2671 fxp_load_ucode(struct fxp_softc *sc) 2672 { 2673 struct ucode *uc; 2674 struct fxp_cb_ucode *cbp; 2675 2676 for (uc = ucode_table; uc->ucode != NULL; uc++) 2677 if (sc->revision == uc->revision) 2678 break; 2679 if (uc->ucode == NULL) 2680 return; 2681 cbp = (struct fxp_cb_ucode *)sc->fxp_desc.cbl_list; 2682 cbp->cb_status = 0; 2683 cbp->cb_command = htole16(FXP_CB_COMMAND_UCODE | FXP_CB_COMMAND_EL); 2684 cbp->link_addr = 0xffffffff; /* (no) next command */ 2685 memcpy(cbp->ucode, uc->ucode, uc->length); 2686 if (uc->int_delay_offset) 2687 *(u_int16_t *)&cbp->ucode[uc->int_delay_offset] = 2688 htole16(sc->tunable_int_delay + sc->tunable_int_delay / 2); 2689 if (uc->bundle_max_offset) 2690 *(u_int16_t *)&cbp->ucode[uc->bundle_max_offset] = 2691 htole16(sc->tunable_bundle_max); 2692 /* 2693 * Download the ucode to the chip. 2694 */ 2695 fxp_scb_wait(sc); 2696 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE); 2697 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->fxp_desc.cbl_addr); 2698 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2699 /* ...and wait for it to complete. */ 2700 fxp_dma_wait(sc, &cbp->cb_status, sc->cbl_tag, sc->cbl_map); 2701 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_POSTWRITE); 2702 device_printf(sc->dev, 2703 "Microcode loaded, int_delay: %d usec bundle_max: %d\n", 2704 sc->tunable_int_delay, 2705 uc->bundle_max_offset == 0 ? 0 : sc->tunable_bundle_max); 2706 sc->flags |= FXP_FLAG_UCODE; 2707 } 2708 2709 static int 2710 sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high) 2711 { 2712 int error, value; 2713 2714 value = *(int *)arg1; 2715 error = sysctl_handle_int(oidp, &value, 0, req); 2716 if (error || !req->newptr) 2717 return (error); 2718 if (value < low || value > high) 2719 return (EINVAL); 2720 *(int *)arg1 = value; 2721 return (0); 2722 } 2723 2724 /* 2725 * Interrupt delay is expressed in microseconds, a multiplier is used 2726 * to convert this to the appropriate clock ticks before using. 2727 */ 2728 static int 2729 sysctl_hw_fxp_int_delay(SYSCTL_HANDLER_ARGS) 2730 { 2731 return (sysctl_int_range(oidp, arg1, arg2, req, 300, 3000)); 2732 } 2733 2734 static int 2735 sysctl_hw_fxp_bundle_max(SYSCTL_HANDLER_ARGS) 2736 { 2737 return (sysctl_int_range(oidp, arg1, arg2, req, 1, 0xffff)); 2738 } 2739