1 /*- 2 * Copyright (c) 1995, David Greenman 3 * Copyright (c) 2001 Jonathan Lemon <jlemon@freebsd.org> 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice unmodified, this list of conditions, and the following 11 * disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 * 28 */ 29 30 #include <sys/cdefs.h> 31 __FBSDID("$FreeBSD$"); 32 33 /* 34 * Intel EtherExpress Pro/100B PCI Fast Ethernet driver 35 */ 36 37 #include <sys/param.h> 38 #include <sys/systm.h> 39 #include <sys/endian.h> 40 #include <sys/mbuf.h> 41 /* #include <sys/mutex.h> */ 42 #include <sys/kernel.h> 43 #include <sys/socket.h> 44 #include <sys/sysctl.h> 45 46 #include <net/if.h> 47 #include <net/if_dl.h> 48 #include <net/if_media.h> 49 50 #include <net/bpf.h> 51 #include <sys/sockio.h> 52 #include <sys/bus.h> 53 #include <machine/bus.h> 54 #include <sys/rman.h> 55 #include <machine/resource.h> 56 57 #include <net/ethernet.h> 58 #include <net/if_arp.h> 59 60 #include <machine/clock.h> /* for DELAY */ 61 62 #include <net/if_types.h> 63 #include <net/if_vlan_var.h> 64 65 #ifdef FXP_IP_CSUM_WAR 66 #include <netinet/in.h> 67 #include <netinet/in_systm.h> 68 #include <netinet/ip.h> 69 #include <machine/in_cksum.h> 70 #endif 71 72 #include <dev/pci/pcivar.h> 73 #include <dev/pci/pcireg.h> /* for PCIM_CMD_xxx */ 74 75 #include <dev/mii/mii.h> 76 #include <dev/mii/miivar.h> 77 78 #include <dev/fxp/if_fxpreg.h> 79 #include <dev/fxp/if_fxpvar.h> 80 #include <dev/fxp/rcvbundl.h> 81 82 MODULE_DEPEND(fxp, pci, 1, 1, 1); 83 MODULE_DEPEND(fxp, ether, 1, 1, 1); 84 MODULE_DEPEND(fxp, miibus, 1, 1, 1); 85 #include "miibus_if.h" 86 87 /* 88 * NOTE! On the Alpha, we have an alignment constraint. The 89 * card DMAs the packet immediately following the RFA. However, 90 * the first thing in the packet is a 14-byte Ethernet header. 91 * This means that the packet is misaligned. To compensate, 92 * we actually offset the RFA 2 bytes into the cluster. This 93 * alignes the packet after the Ethernet header at a 32-bit 94 * boundary. HOWEVER! This means that the RFA is misaligned! 95 */ 96 #define RFA_ALIGNMENT_FUDGE 2 97 98 /* 99 * Set initial transmit threshold at 64 (512 bytes). This is 100 * increased by 64 (512 bytes) at a time, to maximum of 192 101 * (1536 bytes), if an underrun occurs. 102 */ 103 static int tx_threshold = 64; 104 105 /* 106 * The configuration byte map has several undefined fields which 107 * must be one or must be zero. Set up a template for these bits 108 * only, (assuming a 82557 chip) leaving the actual configuration 109 * to fxp_init. 110 * 111 * See struct fxp_cb_config for the bit definitions. 112 */ 113 static u_char fxp_cb_config_template[] = { 114 0x0, 0x0, /* cb_status */ 115 0x0, 0x0, /* cb_command */ 116 0x0, 0x0, 0x0, 0x0, /* link_addr */ 117 0x0, /* 0 */ 118 0x0, /* 1 */ 119 0x0, /* 2 */ 120 0x0, /* 3 */ 121 0x0, /* 4 */ 122 0x0, /* 5 */ 123 0x32, /* 6 */ 124 0x0, /* 7 */ 125 0x0, /* 8 */ 126 0x0, /* 9 */ 127 0x6, /* 10 */ 128 0x0, /* 11 */ 129 0x0, /* 12 */ 130 0x0, /* 13 */ 131 0xf2, /* 14 */ 132 0x48, /* 15 */ 133 0x0, /* 16 */ 134 0x40, /* 17 */ 135 0xf0, /* 18 */ 136 0x0, /* 19 */ 137 0x3f, /* 20 */ 138 0x5 /* 21 */ 139 }; 140 141 struct fxp_ident { 142 u_int16_t devid; 143 int16_t revid; /* -1 matches anything */ 144 char *name; 145 }; 146 147 /* 148 * Claim various Intel PCI device identifiers for this driver. The 149 * sub-vendor and sub-device field are extensively used to identify 150 * particular variants, but we don't currently differentiate between 151 * them. 152 */ 153 static struct fxp_ident fxp_ident_table[] = { 154 { 0x1029, -1, "Intel 82559 PCI/CardBus Pro/100" }, 155 { 0x1030, -1, "Intel 82559 Pro/100 Ethernet" }, 156 { 0x1031, -1, "Intel 82801CAM (ICH3) Pro/100 VE Ethernet" }, 157 { 0x1032, -1, "Intel 82801CAM (ICH3) Pro/100 VE Ethernet" }, 158 { 0x1033, -1, "Intel 82801CAM (ICH3) Pro/100 VM Ethernet" }, 159 { 0x1034, -1, "Intel 82801CAM (ICH3) Pro/100 VM Ethernet" }, 160 { 0x1035, -1, "Intel 82801CAM (ICH3) Pro/100 Ethernet" }, 161 { 0x1036, -1, "Intel 82801CAM (ICH3) Pro/100 Ethernet" }, 162 { 0x1037, -1, "Intel 82801CAM (ICH3) Pro/100 Ethernet" }, 163 { 0x1038, -1, "Intel 82801CAM (ICH3) Pro/100 VM Ethernet" }, 164 { 0x1039, -1, "Intel 82801DB (ICH4) Pro/100 VE Ethernet" }, 165 { 0x103A, -1, "Intel 82801DB (ICH4) Pro/100 Ethernet" }, 166 { 0x103B, -1, "Intel 82801DB (ICH4) Pro/100 VM Ethernet" }, 167 { 0x103C, -1, "Intel 82801DB (ICH4) Pro/100 Ethernet" }, 168 { 0x103D, -1, "Intel 82801DB (ICH4) Pro/100 VE Ethernet" }, 169 { 0x103E, -1, "Intel 82801DB (ICH4) Pro/100 VM Ethernet" }, 170 { 0x1050, -1, "Intel 82801BA (D865) Pro/100 VE Ethernet" }, 171 { 0x1051, -1, "Intel 82562ET (ICH5/ICH5R) Pro/100 VE Ethernet" }, 172 { 0x1059, -1, "Intel 82551QM Pro/100 M Mobile Connection" }, 173 { 0x1209, -1, "Intel 82559ER Embedded 10/100 Ethernet" }, 174 { 0x1229, 0x01, "Intel 82557 Pro/100 Ethernet" }, 175 { 0x1229, 0x02, "Intel 82557 Pro/100 Ethernet" }, 176 { 0x1229, 0x03, "Intel 82557 Pro/100 Ethernet" }, 177 { 0x1229, 0x04, "Intel 82558 Pro/100 Ethernet" }, 178 { 0x1229, 0x05, "Intel 82558 Pro/100 Ethernet" }, 179 { 0x1229, 0x06, "Intel 82559 Pro/100 Ethernet" }, 180 { 0x1229, 0x07, "Intel 82559 Pro/100 Ethernet" }, 181 { 0x1229, 0x08, "Intel 82559 Pro/100 Ethernet" }, 182 { 0x1229, 0x09, "Intel 82559ER Pro/100 Ethernet" }, 183 { 0x1229, 0x0c, "Intel 82550 Pro/100 Ethernet" }, 184 { 0x1229, 0x0d, "Intel 82550 Pro/100 Ethernet" }, 185 { 0x1229, 0x0e, "Intel 82550 Pro/100 Ethernet" }, 186 { 0x1229, 0x0f, "Intel 82551 Pro/100 Ethernet" }, 187 { 0x1229, 0x10, "Intel 82551 Pro/100 Ethernet" }, 188 { 0x1229, -1, "Intel 82557/8/9 Pro/100 Ethernet" }, 189 { 0x2449, -1, "Intel 82801BA/CAM (ICH2/3) Pro/100 Ethernet" }, 190 { 0, -1, NULL }, 191 }; 192 193 #ifdef FXP_IP_CSUM_WAR 194 #define FXP_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 195 #else 196 #define FXP_CSUM_FEATURES (CSUM_TCP | CSUM_UDP) 197 #endif 198 199 static int fxp_probe(device_t dev); 200 static int fxp_attach(device_t dev); 201 static int fxp_detach(device_t dev); 202 static int fxp_shutdown(device_t dev); 203 static int fxp_suspend(device_t dev); 204 static int fxp_resume(device_t dev); 205 206 static void fxp_intr(void *xsc); 207 static void fxp_intr_body(struct fxp_softc *sc, struct ifnet *ifp, 208 u_int8_t statack, int count); 209 static void fxp_init(void *xsc); 210 static void fxp_init_body(struct fxp_softc *sc); 211 static void fxp_tick(void *xsc); 212 #ifndef BURN_BRIDGES 213 static void fxp_powerstate_d0(device_t dev); 214 #endif 215 static void fxp_start(struct ifnet *ifp); 216 static void fxp_start_body(struct ifnet *ifp); 217 static void fxp_stop(struct fxp_softc *sc); 218 static void fxp_release(struct fxp_softc *sc); 219 static int fxp_ioctl(struct ifnet *ifp, u_long command, 220 caddr_t data); 221 static void fxp_watchdog(struct ifnet *ifp); 222 static int fxp_add_rfabuf(struct fxp_softc *sc, 223 struct fxp_rx *rxp); 224 static int fxp_mc_addrs(struct fxp_softc *sc); 225 static void fxp_mc_setup(struct fxp_softc *sc); 226 static u_int16_t fxp_eeprom_getword(struct fxp_softc *sc, int offset, 227 int autosize); 228 static void fxp_eeprom_putword(struct fxp_softc *sc, int offset, 229 u_int16_t data); 230 static void fxp_autosize_eeprom(struct fxp_softc *sc); 231 static void fxp_read_eeprom(struct fxp_softc *sc, u_short *data, 232 int offset, int words); 233 static void fxp_write_eeprom(struct fxp_softc *sc, u_short *data, 234 int offset, int words); 235 static int fxp_ifmedia_upd(struct ifnet *ifp); 236 static void fxp_ifmedia_sts(struct ifnet *ifp, 237 struct ifmediareq *ifmr); 238 static int fxp_serial_ifmedia_upd(struct ifnet *ifp); 239 static void fxp_serial_ifmedia_sts(struct ifnet *ifp, 240 struct ifmediareq *ifmr); 241 static volatile int fxp_miibus_readreg(device_t dev, int phy, int reg); 242 static void fxp_miibus_writereg(device_t dev, int phy, int reg, 243 int value); 244 static void fxp_load_ucode(struct fxp_softc *sc); 245 static int sysctl_int_range(SYSCTL_HANDLER_ARGS, 246 int low, int high); 247 static int sysctl_hw_fxp_bundle_max(SYSCTL_HANDLER_ARGS); 248 static int sysctl_hw_fxp_int_delay(SYSCTL_HANDLER_ARGS); 249 static void fxp_scb_wait(struct fxp_softc *sc); 250 static void fxp_scb_cmd(struct fxp_softc *sc, int cmd); 251 static void fxp_dma_wait(struct fxp_softc *sc, 252 volatile u_int16_t *status, bus_dma_tag_t dmat, 253 bus_dmamap_t map); 254 255 static device_method_t fxp_methods[] = { 256 /* Device interface */ 257 DEVMETHOD(device_probe, fxp_probe), 258 DEVMETHOD(device_attach, fxp_attach), 259 DEVMETHOD(device_detach, fxp_detach), 260 DEVMETHOD(device_shutdown, fxp_shutdown), 261 DEVMETHOD(device_suspend, fxp_suspend), 262 DEVMETHOD(device_resume, fxp_resume), 263 264 /* MII interface */ 265 DEVMETHOD(miibus_readreg, fxp_miibus_readreg), 266 DEVMETHOD(miibus_writereg, fxp_miibus_writereg), 267 268 { 0, 0 } 269 }; 270 271 static driver_t fxp_driver = { 272 "fxp", 273 fxp_methods, 274 sizeof(struct fxp_softc), 275 }; 276 277 static devclass_t fxp_devclass; 278 279 DRIVER_MODULE(fxp, pci, fxp_driver, fxp_devclass, 0, 0); 280 DRIVER_MODULE(fxp, cardbus, fxp_driver, fxp_devclass, 0, 0); 281 DRIVER_MODULE(miibus, fxp, miibus_driver, miibus_devclass, 0, 0); 282 283 static int fxp_rnr; 284 SYSCTL_INT(_hw, OID_AUTO, fxp_rnr, CTLFLAG_RW, &fxp_rnr, 0, "fxp rnr events"); 285 286 static int fxp_noflow; 287 SYSCTL_INT(_hw, OID_AUTO, fxp_noflow, CTLFLAG_RW, &fxp_noflow, 0, "fxp flow control disabled"); 288 TUNABLE_INT("hw.fxp_noflow", &fxp_noflow); 289 290 /* 291 * Wait for the previous command to be accepted (but not necessarily 292 * completed). 293 */ 294 static void 295 fxp_scb_wait(struct fxp_softc *sc) 296 { 297 int i = 10000; 298 299 while (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) && --i) 300 DELAY(2); 301 if (i == 0) 302 device_printf(sc->dev, "SCB timeout: 0x%x 0x%x 0x%x 0x%x\n", 303 CSR_READ_1(sc, FXP_CSR_SCB_COMMAND), 304 CSR_READ_1(sc, FXP_CSR_SCB_STATACK), 305 CSR_READ_1(sc, FXP_CSR_SCB_RUSCUS), 306 CSR_READ_2(sc, FXP_CSR_FLOWCONTROL)); 307 } 308 309 static void 310 fxp_scb_cmd(struct fxp_softc *sc, int cmd) 311 { 312 313 if (cmd == FXP_SCB_COMMAND_CU_RESUME && sc->cu_resume_bug) { 314 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_CB_COMMAND_NOP); 315 fxp_scb_wait(sc); 316 } 317 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, cmd); 318 } 319 320 static void 321 fxp_dma_wait(struct fxp_softc *sc, volatile u_int16_t *status, 322 bus_dma_tag_t dmat, bus_dmamap_t map) 323 { 324 int i = 10000; 325 326 bus_dmamap_sync(dmat, map, BUS_DMASYNC_POSTREAD); 327 while (!(le16toh(*status) & FXP_CB_STATUS_C) && --i) { 328 DELAY(2); 329 bus_dmamap_sync(dmat, map, BUS_DMASYNC_POSTREAD); 330 } 331 if (i == 0) 332 device_printf(sc->dev, "DMA timeout\n"); 333 } 334 335 /* 336 * Return identification string if this device is ours. 337 */ 338 static int 339 fxp_probe(device_t dev) 340 { 341 u_int16_t devid; 342 u_int8_t revid; 343 struct fxp_ident *ident; 344 345 if (pci_get_vendor(dev) == FXP_VENDORID_INTEL) { 346 devid = pci_get_device(dev); 347 revid = pci_get_revid(dev); 348 for (ident = fxp_ident_table; ident->name != NULL; ident++) { 349 if (ident->devid == devid && 350 (ident->revid == revid || ident->revid == -1)) { 351 device_set_desc(dev, ident->name); 352 return (0); 353 } 354 } 355 } 356 return (ENXIO); 357 } 358 359 #ifndef BURN_BRIDGES 360 static void 361 fxp_powerstate_d0(device_t dev) 362 { 363 #if __FreeBSD_version >= 430002 364 u_int32_t iobase, membase, irq; 365 366 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 367 /* Save important PCI config data. */ 368 iobase = pci_read_config(dev, FXP_PCI_IOBA, 4); 369 membase = pci_read_config(dev, FXP_PCI_MMBA, 4); 370 irq = pci_read_config(dev, PCIR_INTLINE, 4); 371 372 /* Reset the power state. */ 373 device_printf(dev, "chip is in D%d power mode " 374 "-- setting to D0\n", pci_get_powerstate(dev)); 375 376 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 377 378 /* Restore PCI config data. */ 379 pci_write_config(dev, FXP_PCI_IOBA, iobase, 4); 380 pci_write_config(dev, FXP_PCI_MMBA, membase, 4); 381 pci_write_config(dev, PCIR_INTLINE, irq, 4); 382 } 383 #endif 384 } 385 #endif 386 387 static void 388 fxp_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error) 389 { 390 u_int32_t *addr; 391 392 if (error) 393 return; 394 395 KASSERT(nseg == 1, ("too many DMA segments, %d should be 1", nseg)); 396 addr = arg; 397 *addr = segs->ds_addr; 398 } 399 400 static int 401 fxp_attach(device_t dev) 402 { 403 int error = 0; 404 struct fxp_softc *sc = device_get_softc(dev); 405 struct ifnet *ifp; 406 struct fxp_rx *rxp; 407 u_int32_t val; 408 u_int16_t data, myea[ETHER_ADDR_LEN / 2]; 409 int i, rid, m1, m2, prefer_iomap, maxtxseg; 410 int s, ipcbxmit_disable; 411 412 sc->dev = dev; 413 callout_init(&sc->stat_ch, CALLOUT_MPSAFE); 414 sysctl_ctx_init(&sc->sysctl_ctx); 415 mtx_init(&sc->sc_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 416 MTX_DEF); 417 ifmedia_init(&sc->sc_media, 0, fxp_serial_ifmedia_upd, 418 fxp_serial_ifmedia_sts); 419 420 s = splimp(); 421 422 /* 423 * Enable bus mastering. 424 */ 425 pci_enable_busmaster(dev); 426 val = pci_read_config(dev, PCIR_COMMAND, 2); 427 #ifndef BURN_BRIDGES 428 fxp_powerstate_d0(dev); 429 #endif 430 /* 431 * Figure out which we should try first - memory mapping or i/o mapping? 432 * We default to memory mapping. Then we accept an override from the 433 * command line. Then we check to see which one is enabled. 434 */ 435 m1 = PCIM_CMD_MEMEN; 436 m2 = PCIM_CMD_PORTEN; 437 prefer_iomap = 0; 438 if (resource_int_value(device_get_name(dev), device_get_unit(dev), 439 "prefer_iomap", &prefer_iomap) == 0 && prefer_iomap != 0) { 440 m1 = PCIM_CMD_PORTEN; 441 m2 = PCIM_CMD_MEMEN; 442 } 443 444 sc->rtp = (m1 == PCIM_CMD_MEMEN)? SYS_RES_MEMORY : SYS_RES_IOPORT; 445 sc->rgd = (m1 == PCIM_CMD_MEMEN)? FXP_PCI_MMBA : FXP_PCI_IOBA; 446 sc->mem = bus_alloc_resource_any(dev, sc->rtp, &sc->rgd, RF_ACTIVE); 447 if (sc->mem == NULL) { 448 sc->rtp = 449 (m2 == PCIM_CMD_MEMEN)? SYS_RES_MEMORY : SYS_RES_IOPORT; 450 sc->rgd = (m2 == PCIM_CMD_MEMEN)? FXP_PCI_MMBA : FXP_PCI_IOBA; 451 sc->mem = bus_alloc_resource_any(dev, sc->rtp, &sc->rgd, 452 RF_ACTIVE); 453 } 454 455 if (!sc->mem) { 456 error = ENXIO; 457 goto fail; 458 } 459 if (bootverbose) { 460 device_printf(dev, "using %s space register mapping\n", 461 sc->rtp == SYS_RES_MEMORY? "memory" : "I/O"); 462 } 463 464 sc->sc_st = rman_get_bustag(sc->mem); 465 sc->sc_sh = rman_get_bushandle(sc->mem); 466 467 /* 468 * Allocate our interrupt. 469 */ 470 rid = 0; 471 sc->irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 472 RF_SHAREABLE | RF_ACTIVE); 473 if (sc->irq == NULL) { 474 device_printf(dev, "could not map interrupt\n"); 475 error = ENXIO; 476 goto fail; 477 } 478 479 /* 480 * Reset to a stable state. 481 */ 482 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET); 483 DELAY(10); 484 485 /* 486 * Find out how large of an SEEPROM we have. 487 */ 488 fxp_autosize_eeprom(sc); 489 490 /* 491 * Determine whether we must use the 503 serial interface. 492 */ 493 fxp_read_eeprom(sc, &data, 6, 1); 494 if ((data & FXP_PHY_DEVICE_MASK) != 0 && 495 (data & FXP_PHY_SERIAL_ONLY)) 496 sc->flags |= FXP_FLAG_SERIAL_MEDIA; 497 498 /* 499 * Create the sysctl tree 500 */ 501 sc->sysctl_tree = SYSCTL_ADD_NODE(&sc->sysctl_ctx, 502 SYSCTL_STATIC_CHILDREN(_hw), OID_AUTO, 503 device_get_nameunit(dev), CTLFLAG_RD, 0, ""); 504 if (sc->sysctl_tree == NULL) { 505 error = ENXIO; 506 goto fail; 507 } 508 SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree), 509 OID_AUTO, "int_delay", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_PRISON, 510 &sc->tunable_int_delay, 0, sysctl_hw_fxp_int_delay, "I", 511 "FXP driver receive interrupt microcode bundling delay"); 512 SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree), 513 OID_AUTO, "bundle_max", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_PRISON, 514 &sc->tunable_bundle_max, 0, sysctl_hw_fxp_bundle_max, "I", 515 "FXP driver receive interrupt microcode bundle size limit"); 516 517 /* 518 * Pull in device tunables. 519 */ 520 sc->tunable_int_delay = TUNABLE_INT_DELAY; 521 sc->tunable_bundle_max = TUNABLE_BUNDLE_MAX; 522 (void) resource_int_value(device_get_name(dev), device_get_unit(dev), 523 "int_delay", &sc->tunable_int_delay); 524 (void) resource_int_value(device_get_name(dev), device_get_unit(dev), 525 "bundle_max", &sc->tunable_bundle_max); 526 527 /* 528 * Find out the chip revision; lump all 82557 revs together. 529 */ 530 fxp_read_eeprom(sc, &data, 5, 1); 531 if ((data >> 8) == 1) 532 sc->revision = FXP_REV_82557; 533 else 534 sc->revision = pci_get_revid(dev); 535 536 /* 537 * Enable workarounds for certain chip revision deficiencies. 538 * 539 * Systems based on the ICH2/ICH2-M chip from Intel, and possibly 540 * some systems based a normal 82559 design, have a defect where 541 * the chip can cause a PCI protocol violation if it receives 542 * a CU_RESUME command when it is entering the IDLE state. The 543 * workaround is to disable Dynamic Standby Mode, so the chip never 544 * deasserts CLKRUN#, and always remains in an active state. 545 * 546 * See Intel 82801BA/82801BAM Specification Update, Errata #30. 547 */ 548 i = pci_get_device(dev); 549 if (i == 0x2449 || (i > 0x1030 && i < 0x1039) || 550 sc->revision >= FXP_REV_82559_A0) { 551 fxp_read_eeprom(sc, &data, 10, 1); 552 if (data & 0x02) { /* STB enable */ 553 u_int16_t cksum; 554 int i; 555 556 device_printf(dev, 557 "Disabling dynamic standby mode in EEPROM\n"); 558 data &= ~0x02; 559 fxp_write_eeprom(sc, &data, 10, 1); 560 device_printf(dev, "New EEPROM ID: 0x%x\n", data); 561 cksum = 0; 562 for (i = 0; i < (1 << sc->eeprom_size) - 1; i++) { 563 fxp_read_eeprom(sc, &data, i, 1); 564 cksum += data; 565 } 566 i = (1 << sc->eeprom_size) - 1; 567 cksum = 0xBABA - cksum; 568 fxp_read_eeprom(sc, &data, i, 1); 569 fxp_write_eeprom(sc, &cksum, i, 1); 570 device_printf(dev, 571 "EEPROM checksum @ 0x%x: 0x%x -> 0x%x\n", 572 i, data, cksum); 573 #if 1 574 /* 575 * If the user elects to continue, try the software 576 * workaround, as it is better than nothing. 577 */ 578 sc->flags |= FXP_FLAG_CU_RESUME_BUG; 579 #endif 580 } 581 } 582 583 /* 584 * If we are not a 82557 chip, we can enable extended features. 585 */ 586 if (sc->revision != FXP_REV_82557) { 587 /* 588 * If MWI is enabled in the PCI configuration, and there 589 * is a valid cacheline size (8 or 16 dwords), then tell 590 * the board to turn on MWI. 591 */ 592 if (val & PCIM_CMD_MWRICEN && 593 pci_read_config(dev, PCIR_CACHELNSZ, 1) != 0) 594 sc->flags |= FXP_FLAG_MWI_ENABLE; 595 596 /* turn on the extended TxCB feature */ 597 sc->flags |= FXP_FLAG_EXT_TXCB; 598 599 /* enable reception of long frames for VLAN */ 600 sc->flags |= FXP_FLAG_LONG_PKT_EN; 601 } 602 603 /* 604 * Enable use of extended RFDs and TCBs for 82550 605 * and later chips. Note: we need extended TXCB support 606 * too, but that's already enabled by the code above. 607 * Be careful to do this only on the right devices. 608 * 609 * At least some 82550 cards probed as "chip=0x12298086 rev=0x0d" 610 * truncate packets that end with an mbuf containing 1 to 3 bytes 611 * when used with this feature enabled in the previous version of the 612 * driver. This problem appears to be fixed now that the driver 613 * always sets the hardware parse bit in the IPCB structure, which 614 * the "Intel 8255x 10/100 Mbps Ethernet Controller Family Open 615 * Source Software Developer Manual" says is necessary in the 616 * cases where packet truncation was observed. 617 * 618 * The device hint "hint.fxp.UNIT_NUMBER.ipcbxmit_disable" 619 * allows this feature to be disabled at boot time. 620 * 621 * If fxp is not compiled into the kernel, this feature may also 622 * be disabled at run time: 623 * # kldunload fxp 624 * # kenv hint.fxp.0.ipcbxmit_disable=1 625 * # kldload fxp 626 */ 627 628 if (resource_int_value("fxp", device_get_unit(dev), "ipcbxmit_disable", 629 &ipcbxmit_disable) != 0) 630 ipcbxmit_disable = 0; 631 if (ipcbxmit_disable == 0 && (sc->revision == FXP_REV_82550 || 632 sc->revision == FXP_REV_82550_C)) { 633 sc->rfa_size = sizeof (struct fxp_rfa); 634 sc->tx_cmd = FXP_CB_COMMAND_IPCBXMIT; 635 sc->flags |= FXP_FLAG_EXT_RFA; 636 } else { 637 sc->rfa_size = sizeof (struct fxp_rfa) - FXP_RFAX_LEN; 638 sc->tx_cmd = FXP_CB_COMMAND_XMIT; 639 } 640 641 /* 642 * Allocate DMA tags and DMA safe memory. 643 */ 644 maxtxseg = sc->flags & FXP_FLAG_EXT_RFA ? FXP_NTXSEG - 1 : FXP_NTXSEG; 645 error = bus_dma_tag_create(NULL, 2, 0, BUS_SPACE_MAXADDR_32BIT, 646 BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES * maxtxseg, 647 maxtxseg, MCLBYTES, 0, busdma_lock_mutex, &Giant, &sc->fxp_mtag); 648 if (error) { 649 device_printf(dev, "could not allocate dma tag\n"); 650 goto fail; 651 } 652 653 error = bus_dma_tag_create(NULL, 4, 0, BUS_SPACE_MAXADDR_32BIT, 654 BUS_SPACE_MAXADDR, NULL, NULL, sizeof(struct fxp_stats), 1, 655 sizeof(struct fxp_stats), 0, busdma_lock_mutex, &Giant, 656 &sc->fxp_stag); 657 if (error) { 658 device_printf(dev, "could not allocate dma tag\n"); 659 goto fail; 660 } 661 662 error = bus_dmamem_alloc(sc->fxp_stag, (void **)&sc->fxp_stats, 663 BUS_DMA_NOWAIT | BUS_DMA_ZERO, &sc->fxp_smap); 664 if (error) 665 goto fail; 666 error = bus_dmamap_load(sc->fxp_stag, sc->fxp_smap, sc->fxp_stats, 667 sizeof(struct fxp_stats), fxp_dma_map_addr, &sc->stats_addr, 0); 668 if (error) { 669 device_printf(dev, "could not map the stats buffer\n"); 670 goto fail; 671 } 672 673 error = bus_dma_tag_create(NULL, 4, 0, BUS_SPACE_MAXADDR_32BIT, 674 BUS_SPACE_MAXADDR, NULL, NULL, FXP_TXCB_SZ, 1, 675 FXP_TXCB_SZ, 0, busdma_lock_mutex, &Giant, &sc->cbl_tag); 676 if (error) { 677 device_printf(dev, "could not allocate dma tag\n"); 678 goto fail; 679 } 680 681 error = bus_dmamem_alloc(sc->cbl_tag, (void **)&sc->fxp_desc.cbl_list, 682 BUS_DMA_NOWAIT | BUS_DMA_ZERO, &sc->cbl_map); 683 if (error) 684 goto fail; 685 686 error = bus_dmamap_load(sc->cbl_tag, sc->cbl_map, 687 sc->fxp_desc.cbl_list, FXP_TXCB_SZ, fxp_dma_map_addr, 688 &sc->fxp_desc.cbl_addr, 0); 689 if (error) { 690 device_printf(dev, "could not map DMA memory\n"); 691 goto fail; 692 } 693 694 error = bus_dma_tag_create(NULL, 4, 0, BUS_SPACE_MAXADDR_32BIT, 695 BUS_SPACE_MAXADDR, NULL, NULL, sizeof(struct fxp_cb_mcs), 1, 696 sizeof(struct fxp_cb_mcs), 0, busdma_lock_mutex, &Giant, 697 &sc->mcs_tag); 698 if (error) { 699 device_printf(dev, "could not allocate dma tag\n"); 700 goto fail; 701 } 702 703 error = bus_dmamem_alloc(sc->mcs_tag, (void **)&sc->mcsp, 704 BUS_DMA_NOWAIT, &sc->mcs_map); 705 if (error) 706 goto fail; 707 error = bus_dmamap_load(sc->mcs_tag, sc->mcs_map, sc->mcsp, 708 sizeof(struct fxp_cb_mcs), fxp_dma_map_addr, &sc->mcs_addr, 0); 709 if (error) { 710 device_printf(dev, "can't map the multicast setup command\n"); 711 goto fail; 712 } 713 714 /* 715 * Pre-allocate the TX DMA maps. 716 */ 717 for (i = 0; i < FXP_NTXCB; i++) { 718 error = bus_dmamap_create(sc->fxp_mtag, 0, 719 &sc->fxp_desc.tx_list[i].tx_map); 720 if (error) { 721 device_printf(dev, "can't create DMA map for TX\n"); 722 goto fail; 723 } 724 } 725 error = bus_dmamap_create(sc->fxp_mtag, 0, &sc->spare_map); 726 if (error) { 727 device_printf(dev, "can't create spare DMA map\n"); 728 goto fail; 729 } 730 731 /* 732 * Pre-allocate our receive buffers. 733 */ 734 sc->fxp_desc.rx_head = sc->fxp_desc.rx_tail = NULL; 735 for (i = 0; i < FXP_NRFABUFS; i++) { 736 rxp = &sc->fxp_desc.rx_list[i]; 737 error = bus_dmamap_create(sc->fxp_mtag, 0, &rxp->rx_map); 738 if (error) { 739 device_printf(dev, "can't create DMA map for RX\n"); 740 goto fail; 741 } 742 if (fxp_add_rfabuf(sc, rxp) != 0) { 743 error = ENOMEM; 744 goto fail; 745 } 746 } 747 748 /* 749 * Read MAC address. 750 */ 751 fxp_read_eeprom(sc, myea, 0, 3); 752 sc->arpcom.ac_enaddr[0] = myea[0] & 0xff; 753 sc->arpcom.ac_enaddr[1] = myea[0] >> 8; 754 sc->arpcom.ac_enaddr[2] = myea[1] & 0xff; 755 sc->arpcom.ac_enaddr[3] = myea[1] >> 8; 756 sc->arpcom.ac_enaddr[4] = myea[2] & 0xff; 757 sc->arpcom.ac_enaddr[5] = myea[2] >> 8; 758 if (bootverbose) { 759 device_printf(dev, "PCI IDs: %04x %04x %04x %04x %04x\n", 760 pci_get_vendor(dev), pci_get_device(dev), 761 pci_get_subvendor(dev), pci_get_subdevice(dev), 762 pci_get_revid(dev)); 763 fxp_read_eeprom(sc, &data, 10, 1); 764 device_printf(dev, "Dynamic Standby mode is %s\n", 765 data & 0x02 ? "enabled" : "disabled"); 766 } 767 768 /* 769 * If this is only a 10Mbps device, then there is no MII, and 770 * the PHY will use a serial interface instead. 771 * 772 * The Seeq 80c24 AutoDUPLEX(tm) Ethernet Interface Adapter 773 * doesn't have a programming interface of any sort. The 774 * media is sensed automatically based on how the link partner 775 * is configured. This is, in essence, manual configuration. 776 */ 777 if (sc->flags & FXP_FLAG_SERIAL_MEDIA) { 778 ifmedia_add(&sc->sc_media, IFM_ETHER|IFM_MANUAL, 0, NULL); 779 ifmedia_set(&sc->sc_media, IFM_ETHER|IFM_MANUAL); 780 } else { 781 if (mii_phy_probe(dev, &sc->miibus, fxp_ifmedia_upd, 782 fxp_ifmedia_sts)) { 783 device_printf(dev, "MII without any PHY!\n"); 784 error = ENXIO; 785 goto fail; 786 } 787 } 788 789 ifp = &sc->arpcom.ac_if; 790 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 791 ifp->if_output = ether_output; 792 ifp->if_baudrate = 100000000; 793 ifp->if_init = fxp_init; 794 ifp->if_softc = sc; 795 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 796 ifp->if_ioctl = fxp_ioctl; 797 ifp->if_start = fxp_start; 798 ifp->if_watchdog = fxp_watchdog; 799 800 /* Enable checksum offload for 82550 or better chips */ 801 if (sc->flags & FXP_FLAG_EXT_RFA) { 802 ifp->if_hwassist = FXP_CSUM_FEATURES; 803 ifp->if_capabilities = IFCAP_HWCSUM; 804 ifp->if_capenable = ifp->if_capabilities; 805 } 806 807 #ifdef DEVICE_POLLING 808 /* Inform the world we support polling. */ 809 ifp->if_capabilities |= IFCAP_POLLING; 810 ifp->if_capenable |= IFCAP_POLLING; 811 #endif 812 813 /* 814 * Attach the interface. 815 */ 816 ether_ifattach(ifp, sc->arpcom.ac_enaddr); 817 818 /* 819 * Tell the upper layer(s) we support long frames. 820 */ 821 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 822 ifp->if_capabilities |= IFCAP_VLAN_MTU; 823 824 /* 825 * Let the system queue as many packets as we have available 826 * TX descriptors. 827 */ 828 ifp->if_snd.ifq_maxlen = FXP_NTXCB - 1; 829 830 /* 831 * Hook our interrupt after all initialization is complete. 832 * XXX This driver has been tested with the INTR_MPSAFFE flag set 833 * however, ifp and its functions are not fully locked so MPSAFE 834 * should not be used unless you can handle potential data loss. 835 */ 836 error = bus_setup_intr(dev, sc->irq, INTR_TYPE_NET | INTR_MPSAFE, 837 fxp_intr, sc, &sc->ih); 838 if (error) { 839 device_printf(dev, "could not setup irq\n"); 840 ether_ifdetach(&sc->arpcom.ac_if); 841 goto fail; 842 } 843 844 fail: 845 splx(s); 846 if (error) 847 fxp_release(sc); 848 return (error); 849 } 850 851 /* 852 * Release all resources. The softc lock should not be held and the 853 * interrupt should already be torn down. 854 */ 855 static void 856 fxp_release(struct fxp_softc *sc) 857 { 858 struct fxp_rx *rxp; 859 struct fxp_tx *txp; 860 int i; 861 862 mtx_assert(&sc->sc_mtx, MA_NOTOWNED); 863 if (sc->ih) 864 panic("fxp_release() called with intr handle still active"); 865 if (sc->miibus) 866 device_delete_child(sc->dev, sc->miibus); 867 bus_generic_detach(sc->dev); 868 ifmedia_removeall(&sc->sc_media); 869 if (sc->fxp_desc.cbl_list) { 870 bus_dmamap_unload(sc->cbl_tag, sc->cbl_map); 871 bus_dmamem_free(sc->cbl_tag, sc->fxp_desc.cbl_list, 872 sc->cbl_map); 873 } 874 if (sc->fxp_stats) { 875 bus_dmamap_unload(sc->fxp_stag, sc->fxp_smap); 876 bus_dmamem_free(sc->fxp_stag, sc->fxp_stats, sc->fxp_smap); 877 } 878 if (sc->mcsp) { 879 bus_dmamap_unload(sc->mcs_tag, sc->mcs_map); 880 bus_dmamem_free(sc->mcs_tag, sc->mcsp, sc->mcs_map); 881 } 882 if (sc->irq) 883 bus_release_resource(sc->dev, SYS_RES_IRQ, 0, sc->irq); 884 if (sc->mem) 885 bus_release_resource(sc->dev, sc->rtp, sc->rgd, sc->mem); 886 if (sc->fxp_mtag) { 887 for (i = 0; i < FXP_NRFABUFS; i++) { 888 rxp = &sc->fxp_desc.rx_list[i]; 889 if (rxp->rx_mbuf != NULL) { 890 bus_dmamap_sync(sc->fxp_mtag, rxp->rx_map, 891 BUS_DMASYNC_POSTREAD); 892 bus_dmamap_unload(sc->fxp_mtag, rxp->rx_map); 893 m_freem(rxp->rx_mbuf); 894 } 895 bus_dmamap_destroy(sc->fxp_mtag, rxp->rx_map); 896 } 897 bus_dmamap_destroy(sc->fxp_mtag, sc->spare_map); 898 bus_dma_tag_destroy(sc->fxp_mtag); 899 } 900 if (sc->fxp_stag) { 901 for (i = 0; i < FXP_NTXCB; i++) { 902 txp = &sc->fxp_desc.tx_list[i]; 903 if (txp->tx_mbuf != NULL) { 904 bus_dmamap_sync(sc->fxp_mtag, txp->tx_map, 905 BUS_DMASYNC_POSTWRITE); 906 bus_dmamap_unload(sc->fxp_mtag, txp->tx_map); 907 m_freem(txp->tx_mbuf); 908 } 909 bus_dmamap_destroy(sc->fxp_mtag, txp->tx_map); 910 } 911 bus_dma_tag_destroy(sc->fxp_stag); 912 } 913 if (sc->cbl_tag) 914 bus_dma_tag_destroy(sc->cbl_tag); 915 if (sc->mcs_tag) 916 bus_dma_tag_destroy(sc->mcs_tag); 917 918 sysctl_ctx_free(&sc->sysctl_ctx); 919 920 mtx_destroy(&sc->sc_mtx); 921 } 922 923 /* 924 * Detach interface. 925 */ 926 static int 927 fxp_detach(device_t dev) 928 { 929 struct fxp_softc *sc = device_get_softc(dev); 930 int s; 931 932 FXP_LOCK(sc); 933 s = splimp(); 934 935 sc->suspended = 1; /* Do same thing as we do for suspend */ 936 /* 937 * Close down routes etc. 938 */ 939 ether_ifdetach(&sc->arpcom.ac_if); 940 941 /* 942 * Stop DMA and drop transmit queue, but disable interrupts first. 943 */ 944 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE); 945 fxp_stop(sc); 946 FXP_UNLOCK(sc); 947 948 /* 949 * Unhook interrupt before dropping lock. This is to prevent 950 * races with fxp_intr(). 951 */ 952 bus_teardown_intr(sc->dev, sc->irq, sc->ih); 953 sc->ih = NULL; 954 955 splx(s); 956 957 /* Release our allocated resources. */ 958 fxp_release(sc); 959 return (0); 960 } 961 962 /* 963 * Device shutdown routine. Called at system shutdown after sync. The 964 * main purpose of this routine is to shut off receiver DMA so that 965 * kernel memory doesn't get clobbered during warmboot. 966 */ 967 static int 968 fxp_shutdown(device_t dev) 969 { 970 /* 971 * Make sure that DMA is disabled prior to reboot. Not doing 972 * do could allow DMA to corrupt kernel memory during the 973 * reboot before the driver initializes. 974 */ 975 fxp_stop((struct fxp_softc *) device_get_softc(dev)); 976 return (0); 977 } 978 979 /* 980 * Device suspend routine. Stop the interface and save some PCI 981 * settings in case the BIOS doesn't restore them properly on 982 * resume. 983 */ 984 static int 985 fxp_suspend(device_t dev) 986 { 987 struct fxp_softc *sc = device_get_softc(dev); 988 int i, s; 989 990 FXP_LOCK(sc); 991 s = splimp(); 992 993 fxp_stop(sc); 994 995 for (i = 0; i < 5; i++) 996 sc->saved_maps[i] = pci_read_config(dev, PCIR_BAR(i), 4); 997 sc->saved_biosaddr = pci_read_config(dev, PCIR_BIOS, 4); 998 sc->saved_intline = pci_read_config(dev, PCIR_INTLINE, 1); 999 sc->saved_cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1); 1000 sc->saved_lattimer = pci_read_config(dev, PCIR_LATTIMER, 1); 1001 1002 sc->suspended = 1; 1003 1004 FXP_UNLOCK(sc); 1005 splx(s); 1006 return (0); 1007 } 1008 1009 /* 1010 * Device resume routine. Restore some PCI settings in case the BIOS 1011 * doesn't, re-enable busmastering, and restart the interface if 1012 * appropriate. 1013 */ 1014 static int 1015 fxp_resume(device_t dev) 1016 { 1017 struct fxp_softc *sc = device_get_softc(dev); 1018 struct ifnet *ifp = &sc->sc_if; 1019 u_int16_t pci_command; 1020 int i, s; 1021 1022 FXP_LOCK(sc); 1023 s = splimp(); 1024 #ifndef BURN_BRIDGES 1025 fxp_powerstate_d0(dev); 1026 #endif 1027 /* better way to do this? */ 1028 for (i = 0; i < 5; i++) 1029 pci_write_config(dev, PCIR_BAR(i), sc->saved_maps[i], 4); 1030 pci_write_config(dev, PCIR_BIOS, sc->saved_biosaddr, 4); 1031 pci_write_config(dev, PCIR_INTLINE, sc->saved_intline, 1); 1032 pci_write_config(dev, PCIR_CACHELNSZ, sc->saved_cachelnsz, 1); 1033 pci_write_config(dev, PCIR_LATTIMER, sc->saved_lattimer, 1); 1034 1035 /* reenable busmastering */ 1036 pci_command = pci_read_config(dev, PCIR_COMMAND, 2); 1037 pci_command |= (PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN); 1038 pci_write_config(dev, PCIR_COMMAND, pci_command, 2); 1039 1040 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET); 1041 DELAY(10); 1042 1043 /* reinitialize interface if necessary */ 1044 if (ifp->if_flags & IFF_UP) 1045 fxp_init_body(sc); 1046 1047 sc->suspended = 0; 1048 1049 FXP_UNLOCK(sc); 1050 splx(s); 1051 return (0); 1052 } 1053 1054 static void 1055 fxp_eeprom_shiftin(struct fxp_softc *sc, int data, int length) 1056 { 1057 u_int16_t reg; 1058 int x; 1059 1060 /* 1061 * Shift in data. 1062 */ 1063 for (x = 1 << (length - 1); x; x >>= 1) { 1064 if (data & x) 1065 reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI; 1066 else 1067 reg = FXP_EEPROM_EECS; 1068 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 1069 DELAY(1); 1070 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK); 1071 DELAY(1); 1072 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 1073 DELAY(1); 1074 } 1075 } 1076 1077 /* 1078 * Read from the serial EEPROM. Basically, you manually shift in 1079 * the read opcode (one bit at a time) and then shift in the address, 1080 * and then you shift out the data (all of this one bit at a time). 1081 * The word size is 16 bits, so you have to provide the address for 1082 * every 16 bits of data. 1083 */ 1084 static u_int16_t 1085 fxp_eeprom_getword(struct fxp_softc *sc, int offset, int autosize) 1086 { 1087 u_int16_t reg, data; 1088 int x; 1089 1090 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 1091 /* 1092 * Shift in read opcode. 1093 */ 1094 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_READ, 3); 1095 /* 1096 * Shift in address. 1097 */ 1098 data = 0; 1099 for (x = 1 << (sc->eeprom_size - 1); x; x >>= 1) { 1100 if (offset & x) 1101 reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI; 1102 else 1103 reg = FXP_EEPROM_EECS; 1104 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 1105 DELAY(1); 1106 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK); 1107 DELAY(1); 1108 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 1109 DELAY(1); 1110 reg = CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO; 1111 data++; 1112 if (autosize && reg == 0) { 1113 sc->eeprom_size = data; 1114 break; 1115 } 1116 } 1117 /* 1118 * Shift out data. 1119 */ 1120 data = 0; 1121 reg = FXP_EEPROM_EECS; 1122 for (x = 1 << 15; x; x >>= 1) { 1123 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK); 1124 DELAY(1); 1125 if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO) 1126 data |= x; 1127 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 1128 DELAY(1); 1129 } 1130 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 1131 DELAY(1); 1132 1133 return (data); 1134 } 1135 1136 static void 1137 fxp_eeprom_putword(struct fxp_softc *sc, int offset, u_int16_t data) 1138 { 1139 int i; 1140 1141 /* 1142 * Erase/write enable. 1143 */ 1144 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 1145 fxp_eeprom_shiftin(sc, 0x4, 3); 1146 fxp_eeprom_shiftin(sc, 0x03 << (sc->eeprom_size - 2), sc->eeprom_size); 1147 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 1148 DELAY(1); 1149 /* 1150 * Shift in write opcode, address, data. 1151 */ 1152 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 1153 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_WRITE, 3); 1154 fxp_eeprom_shiftin(sc, offset, sc->eeprom_size); 1155 fxp_eeprom_shiftin(sc, data, 16); 1156 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 1157 DELAY(1); 1158 /* 1159 * Wait for EEPROM to finish up. 1160 */ 1161 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 1162 DELAY(1); 1163 for (i = 0; i < 1000; i++) { 1164 if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO) 1165 break; 1166 DELAY(50); 1167 } 1168 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 1169 DELAY(1); 1170 /* 1171 * Erase/write disable. 1172 */ 1173 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 1174 fxp_eeprom_shiftin(sc, 0x4, 3); 1175 fxp_eeprom_shiftin(sc, 0, sc->eeprom_size); 1176 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 1177 DELAY(1); 1178 } 1179 1180 /* 1181 * From NetBSD: 1182 * 1183 * Figure out EEPROM size. 1184 * 1185 * 559's can have either 64-word or 256-word EEPROMs, the 558 1186 * datasheet only talks about 64-word EEPROMs, and the 557 datasheet 1187 * talks about the existance of 16 to 256 word EEPROMs. 1188 * 1189 * The only known sizes are 64 and 256, where the 256 version is used 1190 * by CardBus cards to store CIS information. 1191 * 1192 * The address is shifted in msb-to-lsb, and after the last 1193 * address-bit the EEPROM is supposed to output a `dummy zero' bit, 1194 * after which follows the actual data. We try to detect this zero, by 1195 * probing the data-out bit in the EEPROM control register just after 1196 * having shifted in a bit. If the bit is zero, we assume we've 1197 * shifted enough address bits. The data-out should be tri-state, 1198 * before this, which should translate to a logical one. 1199 */ 1200 static void 1201 fxp_autosize_eeprom(struct fxp_softc *sc) 1202 { 1203 1204 /* guess maximum size of 256 words */ 1205 sc->eeprom_size = 8; 1206 1207 /* autosize */ 1208 (void) fxp_eeprom_getword(sc, 0, 1); 1209 } 1210 1211 static void 1212 fxp_read_eeprom(struct fxp_softc *sc, u_short *data, int offset, int words) 1213 { 1214 int i; 1215 1216 for (i = 0; i < words; i++) 1217 data[i] = fxp_eeprom_getword(sc, offset + i, 0); 1218 } 1219 1220 static void 1221 fxp_write_eeprom(struct fxp_softc *sc, u_short *data, int offset, int words) 1222 { 1223 int i; 1224 1225 for (i = 0; i < words; i++) 1226 fxp_eeprom_putword(sc, offset + i, data[i]); 1227 } 1228 1229 static void 1230 fxp_dma_map_txbuf(void *arg, bus_dma_segment_t *segs, int nseg, 1231 bus_size_t mapsize, int error) 1232 { 1233 struct fxp_softc *sc; 1234 struct fxp_cb_tx *txp; 1235 int i; 1236 1237 if (error) 1238 return; 1239 1240 KASSERT(nseg <= FXP_NTXSEG, ("too many DMA segments")); 1241 1242 sc = arg; 1243 txp = sc->fxp_desc.tx_last->tx_next->tx_cb; 1244 for (i = 0; i < nseg; i++) { 1245 KASSERT(segs[i].ds_len <= MCLBYTES, ("segment size too large")); 1246 /* 1247 * If this is an 82550/82551, then we're using extended 1248 * TxCBs _and_ we're using checksum offload. This means 1249 * that the TxCB is really an IPCB. One major difference 1250 * between the two is that with plain extended TxCBs, 1251 * the bottom half of the TxCB contains two entries from 1252 * the TBD array, whereas IPCBs contain just one entry: 1253 * one entry (8 bytes) has been sacrificed for the TCP/IP 1254 * checksum offload control bits. So to make things work 1255 * right, we have to start filling in the TBD array 1256 * starting from a different place depending on whether 1257 * the chip is an 82550/82551 or not. 1258 */ 1259 if (sc->flags & FXP_FLAG_EXT_RFA) { 1260 txp->tbd[i + 1].tb_addr = htole32(segs[i].ds_addr); 1261 txp->tbd[i + 1].tb_size = htole32(segs[i].ds_len); 1262 } else { 1263 txp->tbd[i].tb_addr = htole32(segs[i].ds_addr); 1264 txp->tbd[i].tb_size = htole32(segs[i].ds_len); 1265 } 1266 } 1267 txp->tbd_number = nseg; 1268 } 1269 1270 /* 1271 * Grab the softc lock and call the real fxp_start_body() routine 1272 */ 1273 static void 1274 fxp_start(struct ifnet *ifp) 1275 { 1276 struct fxp_softc *sc = ifp->if_softc; 1277 1278 FXP_LOCK(sc); 1279 fxp_start_body(ifp); 1280 FXP_UNLOCK(sc); 1281 } 1282 1283 /* 1284 * Start packet transmission on the interface. 1285 * This routine must be called with the softc lock held, and is an 1286 * internal entry point only. 1287 */ 1288 static void 1289 fxp_start_body(struct ifnet *ifp) 1290 { 1291 struct fxp_softc *sc = ifp->if_softc; 1292 struct fxp_tx *txp; 1293 struct mbuf *mb_head; 1294 int error; 1295 1296 mtx_assert(&sc->sc_mtx, MA_OWNED); 1297 /* 1298 * See if we need to suspend xmit until the multicast filter 1299 * has been reprogrammed (which can only be done at the head 1300 * of the command chain). 1301 */ 1302 if (sc->need_mcsetup) { 1303 return; 1304 } 1305 1306 txp = NULL; 1307 1308 /* 1309 * We're finished if there is nothing more to add to the list or if 1310 * we're all filled up with buffers to transmit. 1311 * NOTE: One TxCB is reserved to guarantee that fxp_mc_setup() can add 1312 * a NOP command when needed. 1313 */ 1314 while (ifp->if_snd.ifq_head != NULL && sc->tx_queued < FXP_NTXCB - 1) { 1315 1316 /* 1317 * Grab a packet to transmit. 1318 */ 1319 IF_DEQUEUE(&ifp->if_snd, mb_head); 1320 1321 /* 1322 * Get pointer to next available tx desc. 1323 */ 1324 txp = sc->fxp_desc.tx_last->tx_next; 1325 1326 /* 1327 * A note in Appendix B of the Intel 8255x 10/100 Mbps 1328 * Ethernet Controller Family Open Source Software 1329 * Developer Manual says: 1330 * Using software parsing is only allowed with legal 1331 * TCP/IP or UDP/IP packets. 1332 * ... 1333 * For all other datagrams, hardware parsing must 1334 * be used. 1335 * Software parsing appears to truncate ICMP and 1336 * fragmented UDP packets that contain one to three 1337 * bytes in the second (and final) mbuf of the packet. 1338 */ 1339 if (sc->flags & FXP_FLAG_EXT_RFA) 1340 txp->tx_cb->ipcb_ip_activation_high = 1341 FXP_IPCB_HARDWAREPARSING_ENABLE; 1342 1343 /* 1344 * Deal with TCP/IP checksum offload. Note that 1345 * in order for TCP checksum offload to work, 1346 * the pseudo header checksum must have already 1347 * been computed and stored in the checksum field 1348 * in the TCP header. The stack should have 1349 * already done this for us. 1350 */ 1351 1352 if (mb_head->m_pkthdr.csum_flags) { 1353 if (mb_head->m_pkthdr.csum_flags & CSUM_DELAY_DATA) { 1354 txp->tx_cb->ipcb_ip_schedule = 1355 FXP_IPCB_TCPUDP_CHECKSUM_ENABLE; 1356 if (mb_head->m_pkthdr.csum_flags & CSUM_TCP) 1357 txp->tx_cb->ipcb_ip_schedule |= 1358 FXP_IPCB_TCP_PACKET; 1359 } 1360 #ifdef FXP_IP_CSUM_WAR 1361 /* 1362 * XXX The 82550 chip appears to have trouble 1363 * dealing with IP header checksums in very small 1364 * datagrams, namely fragments from 1 to 3 bytes 1365 * in size. For example, say you want to transmit 1366 * a UDP packet of 1473 bytes. The packet will be 1367 * fragmented over two IP datagrams, the latter 1368 * containing only one byte of data. The 82550 will 1369 * botch the header checksum on the 1-byte fragment. 1370 * As long as the datagram contains 4 or more bytes 1371 * of data, you're ok. 1372 * 1373 * The following code attempts to work around this 1374 * problem: if the datagram is less than 38 bytes 1375 * in size (14 bytes ether header, 20 bytes IP header, 1376 * plus 4 bytes of data), we punt and compute the IP 1377 * header checksum by hand. This workaround doesn't 1378 * work very well, however, since it can be fooled 1379 * by things like VLAN tags and IP options that make 1380 * the header sizes/offsets vary. 1381 */ 1382 1383 if (mb_head->m_pkthdr.csum_flags & CSUM_IP) { 1384 if (mb_head->m_pkthdr.len < 38) { 1385 struct ip *ip; 1386 mb_head->m_data += ETHER_HDR_LEN; 1387 ip = mtod(mb_head, struct ip *); 1388 ip->ip_sum = in_cksum(mb_head, 1389 ip->ip_hl << 2); 1390 mb_head->m_data -= ETHER_HDR_LEN; 1391 } else { 1392 txp->tx_cb->ipcb_ip_activation_high = 1393 FXP_IPCB_HARDWAREPARSING_ENABLE; 1394 txp->tx_cb->ipcb_ip_schedule |= 1395 FXP_IPCB_IP_CHECKSUM_ENABLE; 1396 } 1397 } 1398 #endif 1399 } 1400 1401 /* 1402 * Go through each of the mbufs in the chain and initialize 1403 * the transmit buffer descriptors with the physical address 1404 * and size of the mbuf. 1405 */ 1406 error = bus_dmamap_load_mbuf(sc->fxp_mtag, txp->tx_map, 1407 mb_head, fxp_dma_map_txbuf, sc, 0); 1408 1409 if (error && error != EFBIG) { 1410 device_printf(sc->dev, "can't map mbuf (error %d)\n", 1411 error); 1412 m_freem(mb_head); 1413 break; 1414 } 1415 1416 if (error) { 1417 struct mbuf *mn; 1418 1419 /* 1420 * We ran out of segments. We have to recopy this 1421 * mbuf chain first. Bail out if we can't get the 1422 * new buffers. 1423 */ 1424 mn = m_defrag(mb_head, M_DONTWAIT); 1425 if (mn == NULL) { 1426 m_freem(mb_head); 1427 break; 1428 } else { 1429 mb_head = mn; 1430 } 1431 error = bus_dmamap_load_mbuf(sc->fxp_mtag, txp->tx_map, 1432 mb_head, fxp_dma_map_txbuf, sc, 0); 1433 if (error) { 1434 device_printf(sc->dev, 1435 "can't map mbuf (error %d)\n", error); 1436 m_freem(mb_head); 1437 break; 1438 } 1439 } 1440 1441 bus_dmamap_sync(sc->fxp_mtag, txp->tx_map, 1442 BUS_DMASYNC_PREWRITE); 1443 1444 txp->tx_mbuf = mb_head; 1445 txp->tx_cb->cb_status = 0; 1446 txp->tx_cb->byte_count = 0; 1447 if (sc->tx_queued != FXP_CXINT_THRESH - 1) { 1448 txp->tx_cb->cb_command = 1449 htole16(sc->tx_cmd | FXP_CB_COMMAND_SF | 1450 FXP_CB_COMMAND_S); 1451 } else { 1452 txp->tx_cb->cb_command = 1453 htole16(sc->tx_cmd | FXP_CB_COMMAND_SF | 1454 FXP_CB_COMMAND_S | FXP_CB_COMMAND_I); 1455 /* 1456 * Set a 5 second timer just in case we don't hear 1457 * from the card again. 1458 */ 1459 ifp->if_timer = 5; 1460 } 1461 txp->tx_cb->tx_threshold = tx_threshold; 1462 1463 /* 1464 * Advance the end of list forward. 1465 */ 1466 1467 #ifdef __alpha__ 1468 /* 1469 * On platforms which can't access memory in 16-bit 1470 * granularities, we must prevent the card from DMA'ing 1471 * up the status while we update the command field. 1472 * This could cause us to overwrite the completion status. 1473 * XXX This is probably bogus and we're _not_ looking 1474 * for atomicity here. 1475 */ 1476 atomic_clear_16(&sc->fxp_desc.tx_last->tx_cb->cb_command, 1477 htole16(FXP_CB_COMMAND_S)); 1478 #else 1479 sc->fxp_desc.tx_last->tx_cb->cb_command &= 1480 htole16(~FXP_CB_COMMAND_S); 1481 #endif /*__alpha__*/ 1482 sc->fxp_desc.tx_last = txp; 1483 1484 /* 1485 * Advance the beginning of the list forward if there are 1486 * no other packets queued (when nothing is queued, tx_first 1487 * sits on the last TxCB that was sent out). 1488 */ 1489 if (sc->tx_queued == 0) 1490 sc->fxp_desc.tx_first = txp; 1491 1492 sc->tx_queued++; 1493 1494 /* 1495 * Pass packet to bpf if there is a listener. 1496 */ 1497 BPF_MTAP(ifp, mb_head); 1498 } 1499 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE); 1500 1501 /* 1502 * We're finished. If we added to the list, issue a RESUME to get DMA 1503 * going again if suspended. 1504 */ 1505 if (txp != NULL) { 1506 fxp_scb_wait(sc); 1507 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_RESUME); 1508 } 1509 } 1510 1511 #ifdef DEVICE_POLLING 1512 static poll_handler_t fxp_poll; 1513 1514 static void 1515 fxp_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 1516 { 1517 struct fxp_softc *sc = ifp->if_softc; 1518 u_int8_t statack; 1519 1520 FXP_LOCK(sc); 1521 if (!(ifp->if_capenable & IFCAP_POLLING)) { 1522 ether_poll_deregister(ifp); 1523 cmd = POLL_DEREGISTER; 1524 } 1525 if (cmd == POLL_DEREGISTER) { /* final call, enable interrupts */ 1526 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, 0); 1527 FXP_UNLOCK(sc); 1528 return; 1529 } 1530 statack = FXP_SCB_STATACK_CXTNO | FXP_SCB_STATACK_CNA | 1531 FXP_SCB_STATACK_FR; 1532 if (cmd == POLL_AND_CHECK_STATUS) { 1533 u_int8_t tmp; 1534 1535 tmp = CSR_READ_1(sc, FXP_CSR_SCB_STATACK); 1536 if (tmp == 0xff || tmp == 0) { 1537 FXP_UNLOCK(sc); 1538 return; /* nothing to do */ 1539 } 1540 tmp &= ~statack; 1541 /* ack what we can */ 1542 if (tmp != 0) 1543 CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, tmp); 1544 statack |= tmp; 1545 } 1546 fxp_intr_body(sc, ifp, statack, count); 1547 FXP_UNLOCK(sc); 1548 } 1549 #endif /* DEVICE_POLLING */ 1550 1551 /* 1552 * Process interface interrupts. 1553 */ 1554 static void 1555 fxp_intr(void *xsc) 1556 { 1557 struct fxp_softc *sc = xsc; 1558 struct ifnet *ifp = &sc->sc_if; 1559 u_int8_t statack; 1560 1561 FXP_LOCK(sc); 1562 if (sc->suspended) { 1563 FXP_UNLOCK(sc); 1564 return; 1565 } 1566 1567 #ifdef DEVICE_POLLING 1568 if (ifp->if_flags & IFF_POLLING) { 1569 FXP_UNLOCK(sc); 1570 return; 1571 } 1572 if ((ifp->if_capenable & IFCAP_POLLING) && 1573 ether_poll_register(fxp_poll, ifp)) { 1574 /* disable interrupts */ 1575 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE); 1576 FXP_UNLOCK(sc); 1577 fxp_poll(ifp, 0, 1); 1578 return; 1579 } 1580 #endif 1581 while ((statack = CSR_READ_1(sc, FXP_CSR_SCB_STATACK)) != 0) { 1582 /* 1583 * It should not be possible to have all bits set; the 1584 * FXP_SCB_INTR_SWI bit always returns 0 on a read. If 1585 * all bits are set, this may indicate that the card has 1586 * been physically ejected, so ignore it. 1587 */ 1588 if (statack == 0xff) { 1589 FXP_UNLOCK(sc); 1590 return; 1591 } 1592 1593 /* 1594 * First ACK all the interrupts in this pass. 1595 */ 1596 CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, statack); 1597 fxp_intr_body(sc, ifp, statack, -1); 1598 } 1599 FXP_UNLOCK(sc); 1600 } 1601 1602 static void 1603 fxp_txeof(struct fxp_softc *sc) 1604 { 1605 struct fxp_tx *txp; 1606 1607 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREREAD); 1608 for (txp = sc->fxp_desc.tx_first; sc->tx_queued && 1609 (le16toh(txp->tx_cb->cb_status) & FXP_CB_STATUS_C) != 0; 1610 txp = txp->tx_next) { 1611 if (txp->tx_mbuf != NULL) { 1612 bus_dmamap_sync(sc->fxp_mtag, txp->tx_map, 1613 BUS_DMASYNC_POSTWRITE); 1614 bus_dmamap_unload(sc->fxp_mtag, txp->tx_map); 1615 m_freem(txp->tx_mbuf); 1616 txp->tx_mbuf = NULL; 1617 /* clear this to reset csum offload bits */ 1618 txp->tx_cb->tbd[0].tb_addr = 0; 1619 } 1620 sc->tx_queued--; 1621 } 1622 sc->fxp_desc.tx_first = txp; 1623 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE); 1624 } 1625 1626 static void 1627 fxp_intr_body(struct fxp_softc *sc, struct ifnet *ifp, u_int8_t statack, 1628 int count) 1629 { 1630 struct mbuf *m; 1631 struct fxp_rx *rxp; 1632 struct fxp_rfa *rfa; 1633 int rnr = (statack & FXP_SCB_STATACK_RNR) ? 1 : 0; 1634 1635 mtx_assert(&sc->sc_mtx, MA_OWNED); 1636 if (rnr) 1637 fxp_rnr++; 1638 #ifdef DEVICE_POLLING 1639 /* Pick up a deferred RNR condition if `count' ran out last time. */ 1640 if (sc->flags & FXP_FLAG_DEFERRED_RNR) { 1641 sc->flags &= ~FXP_FLAG_DEFERRED_RNR; 1642 rnr = 1; 1643 } 1644 #endif 1645 1646 /* 1647 * Free any finished transmit mbuf chains. 1648 * 1649 * Handle the CNA event likt a CXTNO event. It used to 1650 * be that this event (control unit not ready) was not 1651 * encountered, but it is now with the SMPng modifications. 1652 * The exact sequence of events that occur when the interface 1653 * is brought up are different now, and if this event 1654 * goes unhandled, the configuration/rxfilter setup sequence 1655 * can stall for several seconds. The result is that no 1656 * packets go out onto the wire for about 5 to 10 seconds 1657 * after the interface is ifconfig'ed for the first time. 1658 */ 1659 if (statack & (FXP_SCB_STATACK_CXTNO | FXP_SCB_STATACK_CNA)) { 1660 fxp_txeof(sc); 1661 1662 ifp->if_timer = 0; 1663 if (sc->tx_queued == 0) { 1664 if (sc->need_mcsetup) 1665 fxp_mc_setup(sc); 1666 } 1667 /* 1668 * Try to start more packets transmitting. 1669 */ 1670 if (ifp->if_snd.ifq_head != NULL) 1671 fxp_start_body(ifp); 1672 } 1673 1674 /* 1675 * Just return if nothing happened on the receive side. 1676 */ 1677 if (!rnr && (statack & FXP_SCB_STATACK_FR) == 0) 1678 return; 1679 1680 /* 1681 * Process receiver interrupts. If a no-resource (RNR) 1682 * condition exists, get whatever packets we can and 1683 * re-start the receiver. 1684 * 1685 * When using polling, we do not process the list to completion, 1686 * so when we get an RNR interrupt we must defer the restart 1687 * until we hit the last buffer with the C bit set. 1688 * If we run out of cycles and rfa_headm has the C bit set, 1689 * record the pending RNR in the FXP_FLAG_DEFERRED_RNR flag so 1690 * that the info will be used in the subsequent polling cycle. 1691 */ 1692 for (;;) { 1693 rxp = sc->fxp_desc.rx_head; 1694 m = rxp->rx_mbuf; 1695 rfa = (struct fxp_rfa *)(m->m_ext.ext_buf + 1696 RFA_ALIGNMENT_FUDGE); 1697 bus_dmamap_sync(sc->fxp_mtag, rxp->rx_map, 1698 BUS_DMASYNC_POSTREAD); 1699 1700 #ifdef DEVICE_POLLING /* loop at most count times if count >=0 */ 1701 if (count >= 0 && count-- == 0) { 1702 if (rnr) { 1703 /* Defer RNR processing until the next time. */ 1704 sc->flags |= FXP_FLAG_DEFERRED_RNR; 1705 rnr = 0; 1706 } 1707 break; 1708 } 1709 #endif /* DEVICE_POLLING */ 1710 1711 if ((le16toh(rfa->rfa_status) & FXP_RFA_STATUS_C) == 0) 1712 break; 1713 1714 /* 1715 * Advance head forward. 1716 */ 1717 sc->fxp_desc.rx_head = rxp->rx_next; 1718 1719 /* 1720 * Add a new buffer to the receive chain. 1721 * If this fails, the old buffer is recycled 1722 * instead. 1723 */ 1724 if (fxp_add_rfabuf(sc, rxp) == 0) { 1725 int total_len; 1726 1727 /* 1728 * Fetch packet length (the top 2 bits of 1729 * actual_size are flags set by the controller 1730 * upon completion), and drop the packet in case 1731 * of bogus length or CRC errors. 1732 */ 1733 total_len = le16toh(rfa->actual_size) & 0x3fff; 1734 if (total_len < sizeof(struct ether_header) || 1735 total_len > MCLBYTES - RFA_ALIGNMENT_FUDGE - 1736 sc->rfa_size || 1737 le16toh(rfa->rfa_status) & FXP_RFA_STATUS_CRC) { 1738 m_freem(m); 1739 continue; 1740 } 1741 1742 /* Do IP checksum checking. */ 1743 if (le16toh(rfa->rfa_status) & FXP_RFA_STATUS_PARSE) { 1744 if (rfa->rfax_csum_sts & 1745 FXP_RFDX_CS_IP_CSUM_BIT_VALID) 1746 m->m_pkthdr.csum_flags |= 1747 CSUM_IP_CHECKED; 1748 if (rfa->rfax_csum_sts & 1749 FXP_RFDX_CS_IP_CSUM_VALID) 1750 m->m_pkthdr.csum_flags |= 1751 CSUM_IP_VALID; 1752 if ((rfa->rfax_csum_sts & 1753 FXP_RFDX_CS_TCPUDP_CSUM_BIT_VALID) && 1754 (rfa->rfax_csum_sts & 1755 FXP_RFDX_CS_TCPUDP_CSUM_VALID)) { 1756 m->m_pkthdr.csum_flags |= 1757 CSUM_DATA_VALID|CSUM_PSEUDO_HDR; 1758 m->m_pkthdr.csum_data = 0xffff; 1759 } 1760 } 1761 1762 m->m_pkthdr.len = m->m_len = total_len; 1763 m->m_pkthdr.rcvif = ifp; 1764 1765 /* 1766 * Drop locks before calling if_input() since it 1767 * may re-enter fxp_start() in the netisr case. 1768 * This would result in a lock reversal. Better 1769 * performance might be obtained by chaining all 1770 * packets received, dropping the lock, and then 1771 * calling if_input() on each one. 1772 */ 1773 FXP_UNLOCK(sc); 1774 (*ifp->if_input)(ifp, m); 1775 FXP_LOCK(sc); 1776 } 1777 } 1778 if (rnr) { 1779 fxp_scb_wait(sc); 1780 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 1781 sc->fxp_desc.rx_head->rx_addr); 1782 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_START); 1783 } 1784 } 1785 1786 /* 1787 * Update packet in/out/collision statistics. The i82557 doesn't 1788 * allow you to access these counters without doing a fairly 1789 * expensive DMA to get _all_ of the statistics it maintains, so 1790 * we do this operation here only once per second. The statistics 1791 * counters in the kernel are updated from the previous dump-stats 1792 * DMA and then a new dump-stats DMA is started. The on-chip 1793 * counters are zeroed when the DMA completes. If we can't start 1794 * the DMA immediately, we don't wait - we just prepare to read 1795 * them again next time. 1796 */ 1797 static void 1798 fxp_tick(void *xsc) 1799 { 1800 struct fxp_softc *sc = xsc; 1801 struct ifnet *ifp = &sc->sc_if; 1802 struct fxp_stats *sp = sc->fxp_stats; 1803 int s; 1804 1805 FXP_LOCK(sc); 1806 s = splimp(); 1807 bus_dmamap_sync(sc->fxp_stag, sc->fxp_smap, BUS_DMASYNC_POSTREAD); 1808 ifp->if_opackets += le32toh(sp->tx_good); 1809 ifp->if_collisions += le32toh(sp->tx_total_collisions); 1810 if (sp->rx_good) { 1811 ifp->if_ipackets += le32toh(sp->rx_good); 1812 sc->rx_idle_secs = 0; 1813 } else { 1814 /* 1815 * Receiver's been idle for another second. 1816 */ 1817 sc->rx_idle_secs++; 1818 } 1819 ifp->if_ierrors += 1820 le32toh(sp->rx_crc_errors) + 1821 le32toh(sp->rx_alignment_errors) + 1822 le32toh(sp->rx_rnr_errors) + 1823 le32toh(sp->rx_overrun_errors); 1824 /* 1825 * If any transmit underruns occured, bump up the transmit 1826 * threshold by another 512 bytes (64 * 8). 1827 */ 1828 if (sp->tx_underruns) { 1829 ifp->if_oerrors += le32toh(sp->tx_underruns); 1830 if (tx_threshold < 192) 1831 tx_threshold += 64; 1832 } 1833 1834 /* 1835 * Release any xmit buffers that have completed DMA. This isn't 1836 * strictly necessary to do here, but it's advantagous for mbufs 1837 * with external storage to be released in a timely manner rather 1838 * than being defered for a potentially long time. This limits 1839 * the delay to a maximum of one second. 1840 */ 1841 fxp_txeof(sc); 1842 1843 /* 1844 * If we haven't received any packets in FXP_MAC_RX_IDLE seconds, 1845 * then assume the receiver has locked up and attempt to clear 1846 * the condition by reprogramming the multicast filter. This is 1847 * a work-around for a bug in the 82557 where the receiver locks 1848 * up if it gets certain types of garbage in the syncronization 1849 * bits prior to the packet header. This bug is supposed to only 1850 * occur in 10Mbps mode, but has been seen to occur in 100Mbps 1851 * mode as well (perhaps due to a 10/100 speed transition). 1852 */ 1853 if (sc->rx_idle_secs > FXP_MAX_RX_IDLE) { 1854 sc->rx_idle_secs = 0; 1855 fxp_mc_setup(sc); 1856 } 1857 /* 1858 * If there is no pending command, start another stats 1859 * dump. Otherwise punt for now. 1860 */ 1861 if (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) == 0) { 1862 /* 1863 * Start another stats dump. 1864 */ 1865 bus_dmamap_sync(sc->fxp_stag, sc->fxp_smap, 1866 BUS_DMASYNC_PREREAD); 1867 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_DUMPRESET); 1868 } else { 1869 /* 1870 * A previous command is still waiting to be accepted. 1871 * Just zero our copy of the stats and wait for the 1872 * next timer event to update them. 1873 */ 1874 sp->tx_good = 0; 1875 sp->tx_underruns = 0; 1876 sp->tx_total_collisions = 0; 1877 1878 sp->rx_good = 0; 1879 sp->rx_crc_errors = 0; 1880 sp->rx_alignment_errors = 0; 1881 sp->rx_rnr_errors = 0; 1882 sp->rx_overrun_errors = 0; 1883 } 1884 if (sc->miibus != NULL) 1885 mii_tick(device_get_softc(sc->miibus)); 1886 1887 /* 1888 * Schedule another timeout one second from now. 1889 */ 1890 callout_reset(&sc->stat_ch, hz, fxp_tick, sc); 1891 FXP_UNLOCK(sc); 1892 splx(s); 1893 } 1894 1895 /* 1896 * Stop the interface. Cancels the statistics updater and resets 1897 * the interface. 1898 */ 1899 static void 1900 fxp_stop(struct fxp_softc *sc) 1901 { 1902 struct ifnet *ifp = &sc->sc_if; 1903 struct fxp_tx *txp; 1904 int i; 1905 1906 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1907 ifp->if_timer = 0; 1908 1909 #ifdef DEVICE_POLLING 1910 ether_poll_deregister(ifp); 1911 #endif 1912 /* 1913 * Cancel stats updater. 1914 */ 1915 callout_stop(&sc->stat_ch); 1916 1917 /* 1918 * Issue software reset, which also unloads the microcode. 1919 */ 1920 sc->flags &= ~FXP_FLAG_UCODE; 1921 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SOFTWARE_RESET); 1922 DELAY(50); 1923 1924 /* 1925 * Release any xmit buffers. 1926 */ 1927 txp = sc->fxp_desc.tx_list; 1928 if (txp != NULL) { 1929 for (i = 0; i < FXP_NTXCB; i++) { 1930 if (txp[i].tx_mbuf != NULL) { 1931 bus_dmamap_sync(sc->fxp_mtag, txp[i].tx_map, 1932 BUS_DMASYNC_POSTWRITE); 1933 bus_dmamap_unload(sc->fxp_mtag, txp[i].tx_map); 1934 m_freem(txp[i].tx_mbuf); 1935 txp[i].tx_mbuf = NULL; 1936 /* clear this to reset csum offload bits */ 1937 txp[i].tx_cb->tbd[0].tb_addr = 0; 1938 } 1939 } 1940 } 1941 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE); 1942 sc->tx_queued = 0; 1943 } 1944 1945 /* 1946 * Watchdog/transmission transmit timeout handler. Called when a 1947 * transmission is started on the interface, but no interrupt is 1948 * received before the timeout. This usually indicates that the 1949 * card has wedged for some reason. 1950 */ 1951 static void 1952 fxp_watchdog(struct ifnet *ifp) 1953 { 1954 struct fxp_softc *sc = ifp->if_softc; 1955 1956 FXP_LOCK(sc); 1957 device_printf(sc->dev, "device timeout\n"); 1958 ifp->if_oerrors++; 1959 1960 fxp_init_body(sc); 1961 FXP_UNLOCK(sc); 1962 } 1963 1964 /* 1965 * Acquire locks and then call the real initialization function. This 1966 * is necessary because ether_ioctl() calls if_init() and this would 1967 * result in mutex recursion if the mutex was held. 1968 */ 1969 static void 1970 fxp_init(void *xsc) 1971 { 1972 struct fxp_softc *sc = xsc; 1973 1974 FXP_LOCK(sc); 1975 fxp_init_body(sc); 1976 FXP_UNLOCK(sc); 1977 } 1978 1979 /* 1980 * Perform device initialization. This routine must be called with the 1981 * softc lock held. 1982 */ 1983 static void 1984 fxp_init_body(struct fxp_softc *sc) 1985 { 1986 struct ifnet *ifp = &sc->sc_if; 1987 struct fxp_cb_config *cbp; 1988 struct fxp_cb_ias *cb_ias; 1989 struct fxp_cb_tx *tcbp; 1990 struct fxp_tx *txp; 1991 struct fxp_cb_mcs *mcsp; 1992 int i, prm, s; 1993 1994 mtx_assert(&sc->sc_mtx, MA_OWNED); 1995 s = splimp(); 1996 /* 1997 * Cancel any pending I/O 1998 */ 1999 fxp_stop(sc); 2000 2001 prm = (ifp->if_flags & IFF_PROMISC) ? 1 : 0; 2002 2003 /* 2004 * Initialize base of CBL and RFA memory. Loading with zero 2005 * sets it up for regular linear addressing. 2006 */ 2007 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 0); 2008 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_BASE); 2009 2010 fxp_scb_wait(sc); 2011 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_BASE); 2012 2013 /* 2014 * Initialize base of dump-stats buffer. 2015 */ 2016 fxp_scb_wait(sc); 2017 bus_dmamap_sync(sc->fxp_stag, sc->fxp_smap, BUS_DMASYNC_PREREAD); 2018 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->stats_addr); 2019 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_DUMP_ADR); 2020 2021 /* 2022 * Attempt to load microcode if requested. 2023 */ 2024 if (ifp->if_flags & IFF_LINK0 && (sc->flags & FXP_FLAG_UCODE) == 0) 2025 fxp_load_ucode(sc); 2026 2027 /* 2028 * Initialize the multicast address list. 2029 */ 2030 if (fxp_mc_addrs(sc)) { 2031 mcsp = sc->mcsp; 2032 mcsp->cb_status = 0; 2033 mcsp->cb_command = 2034 htole16(FXP_CB_COMMAND_MCAS | FXP_CB_COMMAND_EL); 2035 mcsp->link_addr = 0xffffffff; 2036 /* 2037 * Start the multicast setup command. 2038 */ 2039 fxp_scb_wait(sc); 2040 bus_dmamap_sync(sc->mcs_tag, sc->mcs_map, BUS_DMASYNC_PREWRITE); 2041 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->mcs_addr); 2042 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2043 /* ...and wait for it to complete. */ 2044 fxp_dma_wait(sc, &mcsp->cb_status, sc->mcs_tag, sc->mcs_map); 2045 bus_dmamap_sync(sc->mcs_tag, sc->mcs_map, 2046 BUS_DMASYNC_POSTWRITE); 2047 } 2048 2049 /* 2050 * We temporarily use memory that contains the TxCB list to 2051 * construct the config CB. The TxCB list memory is rebuilt 2052 * later. 2053 */ 2054 cbp = (struct fxp_cb_config *)sc->fxp_desc.cbl_list; 2055 2056 /* 2057 * This bcopy is kind of disgusting, but there are a bunch of must be 2058 * zero and must be one bits in this structure and this is the easiest 2059 * way to initialize them all to proper values. 2060 */ 2061 bcopy(fxp_cb_config_template, cbp, sizeof(fxp_cb_config_template)); 2062 2063 cbp->cb_status = 0; 2064 cbp->cb_command = htole16(FXP_CB_COMMAND_CONFIG | 2065 FXP_CB_COMMAND_EL); 2066 cbp->link_addr = 0xffffffff; /* (no) next command */ 2067 cbp->byte_count = sc->flags & FXP_FLAG_EXT_RFA ? 32 : 22; 2068 cbp->rx_fifo_limit = 8; /* rx fifo threshold (32 bytes) */ 2069 cbp->tx_fifo_limit = 0; /* tx fifo threshold (0 bytes) */ 2070 cbp->adaptive_ifs = 0; /* (no) adaptive interframe spacing */ 2071 cbp->mwi_enable = sc->flags & FXP_FLAG_MWI_ENABLE ? 1 : 0; 2072 cbp->type_enable = 0; /* actually reserved */ 2073 cbp->read_align_en = sc->flags & FXP_FLAG_READ_ALIGN ? 1 : 0; 2074 cbp->end_wr_on_cl = sc->flags & FXP_FLAG_WRITE_ALIGN ? 1 : 0; 2075 cbp->rx_dma_bytecount = 0; /* (no) rx DMA max */ 2076 cbp->tx_dma_bytecount = 0; /* (no) tx DMA max */ 2077 cbp->dma_mbce = 0; /* (disable) dma max counters */ 2078 cbp->late_scb = 0; /* (don't) defer SCB update */ 2079 cbp->direct_dma_dis = 1; /* disable direct rcv dma mode */ 2080 cbp->tno_int_or_tco_en =0; /* (disable) tx not okay interrupt */ 2081 cbp->ci_int = 1; /* interrupt on CU idle */ 2082 cbp->ext_txcb_dis = sc->flags & FXP_FLAG_EXT_TXCB ? 0 : 1; 2083 cbp->ext_stats_dis = 1; /* disable extended counters */ 2084 cbp->keep_overrun_rx = 0; /* don't pass overrun frames to host */ 2085 cbp->save_bf = sc->revision == FXP_REV_82557 ? 1 : prm; 2086 cbp->disc_short_rx = !prm; /* discard short packets */ 2087 cbp->underrun_retry = 1; /* retry mode (once) on DMA underrun */ 2088 cbp->two_frames = 0; /* do not limit FIFO to 2 frames */ 2089 cbp->dyn_tbd = 0; /* (no) dynamic TBD mode */ 2090 cbp->ext_rfa = sc->flags & FXP_FLAG_EXT_RFA ? 1 : 0; 2091 cbp->mediatype = sc->flags & FXP_FLAG_SERIAL_MEDIA ? 0 : 1; 2092 cbp->csma_dis = 0; /* (don't) disable link */ 2093 cbp->tcp_udp_cksum = 0; /* (don't) enable checksum */ 2094 cbp->vlan_tco = 0; /* (don't) enable vlan wakeup */ 2095 cbp->link_wake_en = 0; /* (don't) assert PME# on link change */ 2096 cbp->arp_wake_en = 0; /* (don't) assert PME# on arp */ 2097 cbp->mc_wake_en = 0; /* (don't) enable PME# on mcmatch */ 2098 cbp->nsai = 1; /* (don't) disable source addr insert */ 2099 cbp->preamble_length = 2; /* (7 byte) preamble */ 2100 cbp->loopback = 0; /* (don't) loopback */ 2101 cbp->linear_priority = 0; /* (normal CSMA/CD operation) */ 2102 cbp->linear_pri_mode = 0; /* (wait after xmit only) */ 2103 cbp->interfrm_spacing = 6; /* (96 bits of) interframe spacing */ 2104 cbp->promiscuous = prm; /* promiscuous mode */ 2105 cbp->bcast_disable = 0; /* (don't) disable broadcasts */ 2106 cbp->wait_after_win = 0; /* (don't) enable modified backoff alg*/ 2107 cbp->ignore_ul = 0; /* consider U/L bit in IA matching */ 2108 cbp->crc16_en = 0; /* (don't) enable crc-16 algorithm */ 2109 cbp->crscdt = sc->flags & FXP_FLAG_SERIAL_MEDIA ? 1 : 0; 2110 2111 cbp->stripping = !prm; /* truncate rx packet to byte count */ 2112 cbp->padding = 1; /* (do) pad short tx packets */ 2113 cbp->rcv_crc_xfer = 0; /* (don't) xfer CRC to host */ 2114 cbp->long_rx_en = sc->flags & FXP_FLAG_LONG_PKT_EN ? 1 : 0; 2115 cbp->ia_wake_en = 0; /* (don't) wake up on address match */ 2116 cbp->magic_pkt_dis = 0; /* (don't) disable magic packet */ 2117 /* must set wake_en in PMCSR also */ 2118 cbp->force_fdx = 0; /* (don't) force full duplex */ 2119 cbp->fdx_pin_en = 1; /* (enable) FDX# pin */ 2120 cbp->multi_ia = 0; /* (don't) accept multiple IAs */ 2121 cbp->mc_all = sc->flags & FXP_FLAG_ALL_MCAST ? 1 : 0; 2122 cbp->gamla_rx = sc->flags & FXP_FLAG_EXT_RFA ? 1 : 0; 2123 2124 if (fxp_noflow || sc->revision == FXP_REV_82557) { 2125 /* 2126 * The 82557 has no hardware flow control, the values 2127 * below are the defaults for the chip. 2128 */ 2129 cbp->fc_delay_lsb = 0; 2130 cbp->fc_delay_msb = 0x40; 2131 cbp->pri_fc_thresh = 3; 2132 cbp->tx_fc_dis = 0; 2133 cbp->rx_fc_restop = 0; 2134 cbp->rx_fc_restart = 0; 2135 cbp->fc_filter = 0; 2136 cbp->pri_fc_loc = 1; 2137 } else { 2138 cbp->fc_delay_lsb = 0x1f; 2139 cbp->fc_delay_msb = 0x01; 2140 cbp->pri_fc_thresh = 3; 2141 cbp->tx_fc_dis = 0; /* enable transmit FC */ 2142 cbp->rx_fc_restop = 1; /* enable FC restop frames */ 2143 cbp->rx_fc_restart = 1; /* enable FC restart frames */ 2144 cbp->fc_filter = !prm; /* drop FC frames to host */ 2145 cbp->pri_fc_loc = 1; /* FC pri location (byte31) */ 2146 } 2147 2148 /* 2149 * Start the config command/DMA. 2150 */ 2151 fxp_scb_wait(sc); 2152 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE); 2153 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->fxp_desc.cbl_addr); 2154 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2155 /* ...and wait for it to complete. */ 2156 fxp_dma_wait(sc, &cbp->cb_status, sc->cbl_tag, sc->cbl_map); 2157 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_POSTWRITE); 2158 2159 /* 2160 * Now initialize the station address. Temporarily use the TxCB 2161 * memory area like we did above for the config CB. 2162 */ 2163 cb_ias = (struct fxp_cb_ias *)sc->fxp_desc.cbl_list; 2164 cb_ias->cb_status = 0; 2165 cb_ias->cb_command = htole16(FXP_CB_COMMAND_IAS | FXP_CB_COMMAND_EL); 2166 cb_ias->link_addr = 0xffffffff; 2167 bcopy(sc->arpcom.ac_enaddr, cb_ias->macaddr, 2168 sizeof(sc->arpcom.ac_enaddr)); 2169 2170 /* 2171 * Start the IAS (Individual Address Setup) command/DMA. 2172 */ 2173 fxp_scb_wait(sc); 2174 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE); 2175 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2176 /* ...and wait for it to complete. */ 2177 fxp_dma_wait(sc, &cb_ias->cb_status, sc->cbl_tag, sc->cbl_map); 2178 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_POSTWRITE); 2179 2180 /* 2181 * Initialize transmit control block (TxCB) list. 2182 */ 2183 txp = sc->fxp_desc.tx_list; 2184 tcbp = sc->fxp_desc.cbl_list; 2185 bzero(tcbp, FXP_TXCB_SZ); 2186 for (i = 0; i < FXP_NTXCB; i++) { 2187 txp[i].tx_cb = tcbp + i; 2188 txp[i].tx_mbuf = NULL; 2189 tcbp[i].cb_status = htole16(FXP_CB_STATUS_C | FXP_CB_STATUS_OK); 2190 tcbp[i].cb_command = htole16(FXP_CB_COMMAND_NOP); 2191 tcbp[i].link_addr = htole32(sc->fxp_desc.cbl_addr + 2192 (((i + 1) & FXP_TXCB_MASK) * sizeof(struct fxp_cb_tx))); 2193 if (sc->flags & FXP_FLAG_EXT_TXCB) 2194 tcbp[i].tbd_array_addr = 2195 htole32(FXP_TXCB_DMA_ADDR(sc, &tcbp[i].tbd[2])); 2196 else 2197 tcbp[i].tbd_array_addr = 2198 htole32(FXP_TXCB_DMA_ADDR(sc, &tcbp[i].tbd[0])); 2199 txp[i].tx_next = &txp[(i + 1) & FXP_TXCB_MASK]; 2200 } 2201 /* 2202 * Set the suspend flag on the first TxCB and start the control 2203 * unit. It will execute the NOP and then suspend. 2204 */ 2205 tcbp->cb_command = htole16(FXP_CB_COMMAND_NOP | FXP_CB_COMMAND_S); 2206 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE); 2207 sc->fxp_desc.tx_first = sc->fxp_desc.tx_last = txp; 2208 sc->tx_queued = 1; 2209 2210 fxp_scb_wait(sc); 2211 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2212 2213 /* 2214 * Initialize receiver buffer area - RFA. 2215 */ 2216 fxp_scb_wait(sc); 2217 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->fxp_desc.rx_head->rx_addr); 2218 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_START); 2219 2220 /* 2221 * Set current media. 2222 */ 2223 if (sc->miibus != NULL) 2224 mii_mediachg(device_get_softc(sc->miibus)); 2225 2226 ifp->if_flags |= IFF_RUNNING; 2227 ifp->if_flags &= ~IFF_OACTIVE; 2228 2229 /* 2230 * Enable interrupts. 2231 */ 2232 #ifdef DEVICE_POLLING 2233 /* 2234 * ... but only do that if we are not polling. And because (presumably) 2235 * the default is interrupts on, we need to disable them explicitly! 2236 */ 2237 if ( ifp->if_flags & IFF_POLLING ) 2238 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE); 2239 else 2240 #endif /* DEVICE_POLLING */ 2241 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, 0); 2242 2243 /* 2244 * Start stats updater. 2245 */ 2246 callout_reset(&sc->stat_ch, hz, fxp_tick, sc); 2247 splx(s); 2248 } 2249 2250 static int 2251 fxp_serial_ifmedia_upd(struct ifnet *ifp) 2252 { 2253 2254 return (0); 2255 } 2256 2257 static void 2258 fxp_serial_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 2259 { 2260 2261 ifmr->ifm_active = IFM_ETHER|IFM_MANUAL; 2262 } 2263 2264 /* 2265 * Change media according to request. 2266 */ 2267 static int 2268 fxp_ifmedia_upd(struct ifnet *ifp) 2269 { 2270 struct fxp_softc *sc = ifp->if_softc; 2271 struct mii_data *mii; 2272 2273 mii = device_get_softc(sc->miibus); 2274 mii_mediachg(mii); 2275 return (0); 2276 } 2277 2278 /* 2279 * Notify the world which media we're using. 2280 */ 2281 static void 2282 fxp_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 2283 { 2284 struct fxp_softc *sc = ifp->if_softc; 2285 struct mii_data *mii; 2286 2287 mii = device_get_softc(sc->miibus); 2288 mii_pollstat(mii); 2289 ifmr->ifm_active = mii->mii_media_active; 2290 ifmr->ifm_status = mii->mii_media_status; 2291 2292 if (ifmr->ifm_status & IFM_10_T && sc->flags & FXP_FLAG_CU_RESUME_BUG) 2293 sc->cu_resume_bug = 1; 2294 else 2295 sc->cu_resume_bug = 0; 2296 } 2297 2298 /* 2299 * Add a buffer to the end of the RFA buffer list. 2300 * Return 0 if successful, 1 for failure. A failure results in 2301 * adding the 'oldm' (if non-NULL) on to the end of the list - 2302 * tossing out its old contents and recycling it. 2303 * The RFA struct is stuck at the beginning of mbuf cluster and the 2304 * data pointer is fixed up to point just past it. 2305 */ 2306 static int 2307 fxp_add_rfabuf(struct fxp_softc *sc, struct fxp_rx *rxp) 2308 { 2309 struct mbuf *m; 2310 struct fxp_rfa *rfa, *p_rfa; 2311 struct fxp_rx *p_rx; 2312 bus_dmamap_t tmp_map; 2313 int error; 2314 2315 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 2316 if (m == NULL) 2317 return (ENOBUFS); 2318 2319 /* 2320 * Move the data pointer up so that the incoming data packet 2321 * will be 32-bit aligned. 2322 */ 2323 m->m_data += RFA_ALIGNMENT_FUDGE; 2324 2325 /* 2326 * Get a pointer to the base of the mbuf cluster and move 2327 * data start past it. 2328 */ 2329 rfa = mtod(m, struct fxp_rfa *); 2330 m->m_data += sc->rfa_size; 2331 rfa->size = htole16(MCLBYTES - sc->rfa_size - RFA_ALIGNMENT_FUDGE); 2332 2333 rfa->rfa_status = 0; 2334 rfa->rfa_control = htole16(FXP_RFA_CONTROL_EL); 2335 rfa->actual_size = 0; 2336 2337 /* 2338 * Initialize the rest of the RFA. Note that since the RFA 2339 * is misaligned, we cannot store values directly. We're thus 2340 * using the le32enc() function which handles endianness and 2341 * is also alignment-safe. 2342 */ 2343 le32enc(&rfa->link_addr, 0xffffffff); 2344 le32enc(&rfa->rbd_addr, 0xffffffff); 2345 2346 /* Map the RFA into DMA memory. */ 2347 error = bus_dmamap_load(sc->fxp_mtag, sc->spare_map, rfa, 2348 MCLBYTES - RFA_ALIGNMENT_FUDGE, fxp_dma_map_addr, 2349 &rxp->rx_addr, 0); 2350 if (error) { 2351 m_freem(m); 2352 return (error); 2353 } 2354 2355 bus_dmamap_unload(sc->fxp_mtag, rxp->rx_map); 2356 tmp_map = sc->spare_map; 2357 sc->spare_map = rxp->rx_map; 2358 rxp->rx_map = tmp_map; 2359 rxp->rx_mbuf = m; 2360 2361 bus_dmamap_sync(sc->fxp_mtag, rxp->rx_map, 2362 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2363 2364 /* 2365 * If there are other buffers already on the list, attach this 2366 * one to the end by fixing up the tail to point to this one. 2367 */ 2368 if (sc->fxp_desc.rx_head != NULL) { 2369 p_rx = sc->fxp_desc.rx_tail; 2370 p_rfa = (struct fxp_rfa *) 2371 (p_rx->rx_mbuf->m_ext.ext_buf + RFA_ALIGNMENT_FUDGE); 2372 p_rx->rx_next = rxp; 2373 le32enc(&p_rfa->link_addr, rxp->rx_addr); 2374 p_rfa->rfa_control = 0; 2375 bus_dmamap_sync(sc->fxp_mtag, p_rx->rx_map, 2376 BUS_DMASYNC_PREWRITE); 2377 } else { 2378 rxp->rx_next = NULL; 2379 sc->fxp_desc.rx_head = rxp; 2380 } 2381 sc->fxp_desc.rx_tail = rxp; 2382 return (0); 2383 } 2384 2385 static volatile int 2386 fxp_miibus_readreg(device_t dev, int phy, int reg) 2387 { 2388 struct fxp_softc *sc = device_get_softc(dev); 2389 int count = 10000; 2390 int value; 2391 2392 CSR_WRITE_4(sc, FXP_CSR_MDICONTROL, 2393 (FXP_MDI_READ << 26) | (reg << 16) | (phy << 21)); 2394 2395 while (((value = CSR_READ_4(sc, FXP_CSR_MDICONTROL)) & 0x10000000) == 0 2396 && count--) 2397 DELAY(10); 2398 2399 if (count <= 0) 2400 device_printf(dev, "fxp_miibus_readreg: timed out\n"); 2401 2402 return (value & 0xffff); 2403 } 2404 2405 static void 2406 fxp_miibus_writereg(device_t dev, int phy, int reg, int value) 2407 { 2408 struct fxp_softc *sc = device_get_softc(dev); 2409 int count = 10000; 2410 2411 CSR_WRITE_4(sc, FXP_CSR_MDICONTROL, 2412 (FXP_MDI_WRITE << 26) | (reg << 16) | (phy << 21) | 2413 (value & 0xffff)); 2414 2415 while ((CSR_READ_4(sc, FXP_CSR_MDICONTROL) & 0x10000000) == 0 && 2416 count--) 2417 DELAY(10); 2418 2419 if (count <= 0) 2420 device_printf(dev, "fxp_miibus_writereg: timed out\n"); 2421 } 2422 2423 static int 2424 fxp_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 2425 { 2426 struct fxp_softc *sc = ifp->if_softc; 2427 struct ifreq *ifr = (struct ifreq *)data; 2428 struct mii_data *mii; 2429 int s, error = 0; 2430 2431 /* 2432 * Detaching causes us to call ioctl with the mutex owned. Preclude 2433 * that by saying we're busy if the lock is already held. 2434 */ 2435 if (mtx_owned(&sc->sc_mtx)) 2436 return (EBUSY); 2437 2438 FXP_LOCK(sc); 2439 s = splimp(); 2440 2441 switch (command) { 2442 case SIOCSIFFLAGS: 2443 if (ifp->if_flags & IFF_ALLMULTI) 2444 sc->flags |= FXP_FLAG_ALL_MCAST; 2445 else 2446 sc->flags &= ~FXP_FLAG_ALL_MCAST; 2447 2448 /* 2449 * If interface is marked up and not running, then start it. 2450 * If it is marked down and running, stop it. 2451 * XXX If it's up then re-initialize it. This is so flags 2452 * such as IFF_PROMISC are handled. 2453 */ 2454 if (ifp->if_flags & IFF_UP) { 2455 fxp_init_body(sc); 2456 } else { 2457 if (ifp->if_flags & IFF_RUNNING) 2458 fxp_stop(sc); 2459 } 2460 break; 2461 2462 case SIOCADDMULTI: 2463 case SIOCDELMULTI: 2464 if (ifp->if_flags & IFF_ALLMULTI) 2465 sc->flags |= FXP_FLAG_ALL_MCAST; 2466 else 2467 sc->flags &= ~FXP_FLAG_ALL_MCAST; 2468 /* 2469 * Multicast list has changed; set the hardware filter 2470 * accordingly. 2471 */ 2472 if ((sc->flags & FXP_FLAG_ALL_MCAST) == 0) 2473 fxp_mc_setup(sc); 2474 /* 2475 * fxp_mc_setup() can set FXP_FLAG_ALL_MCAST, so check it 2476 * again rather than else {}. 2477 */ 2478 if (sc->flags & FXP_FLAG_ALL_MCAST) 2479 fxp_init_body(sc); 2480 error = 0; 2481 break; 2482 2483 case SIOCSIFMEDIA: 2484 case SIOCGIFMEDIA: 2485 if (sc->miibus != NULL) { 2486 mii = device_get_softc(sc->miibus); 2487 error = ifmedia_ioctl(ifp, ifr, 2488 &mii->mii_media, command); 2489 } else { 2490 error = ifmedia_ioctl(ifp, ifr, &sc->sc_media, command); 2491 } 2492 break; 2493 2494 case SIOCSIFCAP: 2495 ifp->if_capenable = ifr->ifr_reqcap; 2496 break; 2497 2498 default: 2499 /* 2500 * ether_ioctl() will eventually call fxp_start() which 2501 * will result in mutex recursion so drop it first. 2502 */ 2503 FXP_UNLOCK(sc); 2504 error = ether_ioctl(ifp, command, data); 2505 } 2506 if (mtx_owned(&sc->sc_mtx)) 2507 FXP_UNLOCK(sc); 2508 splx(s); 2509 return (error); 2510 } 2511 2512 /* 2513 * Fill in the multicast address list and return number of entries. 2514 */ 2515 static int 2516 fxp_mc_addrs(struct fxp_softc *sc) 2517 { 2518 struct fxp_cb_mcs *mcsp = sc->mcsp; 2519 struct ifnet *ifp = &sc->sc_if; 2520 struct ifmultiaddr *ifma; 2521 int nmcasts; 2522 2523 nmcasts = 0; 2524 if ((sc->flags & FXP_FLAG_ALL_MCAST) == 0) { 2525 #if __FreeBSD_version < 500000 2526 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 2527 #else 2528 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 2529 #endif 2530 if (ifma->ifma_addr->sa_family != AF_LINK) 2531 continue; 2532 if (nmcasts >= MAXMCADDR) { 2533 sc->flags |= FXP_FLAG_ALL_MCAST; 2534 nmcasts = 0; 2535 break; 2536 } 2537 bcopy(LLADDR((struct sockaddr_dl *)ifma->ifma_addr), 2538 &sc->mcsp->mc_addr[nmcasts][0], ETHER_ADDR_LEN); 2539 nmcasts++; 2540 } 2541 } 2542 mcsp->mc_cnt = htole16(nmcasts * ETHER_ADDR_LEN); 2543 return (nmcasts); 2544 } 2545 2546 /* 2547 * Program the multicast filter. 2548 * 2549 * We have an artificial restriction that the multicast setup command 2550 * must be the first command in the chain, so we take steps to ensure 2551 * this. By requiring this, it allows us to keep up the performance of 2552 * the pre-initialized command ring (esp. link pointers) by not actually 2553 * inserting the mcsetup command in the ring - i.e. its link pointer 2554 * points to the TxCB ring, but the mcsetup descriptor itself is not part 2555 * of it. We then can do 'CU_START' on the mcsetup descriptor and have it 2556 * lead into the regular TxCB ring when it completes. 2557 * 2558 * This function must be called at splimp. 2559 */ 2560 static void 2561 fxp_mc_setup(struct fxp_softc *sc) 2562 { 2563 struct fxp_cb_mcs *mcsp = sc->mcsp; 2564 struct ifnet *ifp = &sc->sc_if; 2565 struct fxp_tx *txp; 2566 int count; 2567 2568 /* 2569 * If there are queued commands, we must wait until they are all 2570 * completed. If we are already waiting, then add a NOP command 2571 * with interrupt option so that we're notified when all commands 2572 * have been completed - fxp_start() ensures that no additional 2573 * TX commands will be added when need_mcsetup is true. 2574 */ 2575 if (sc->tx_queued) { 2576 /* 2577 * need_mcsetup will be true if we are already waiting for the 2578 * NOP command to be completed (see below). In this case, bail. 2579 */ 2580 if (sc->need_mcsetup) 2581 return; 2582 sc->need_mcsetup = 1; 2583 2584 /* 2585 * Add a NOP command with interrupt so that we are notified 2586 * when all TX commands have been processed. 2587 */ 2588 txp = sc->fxp_desc.tx_last->tx_next; 2589 txp->tx_mbuf = NULL; 2590 txp->tx_cb->cb_status = 0; 2591 txp->tx_cb->cb_command = htole16(FXP_CB_COMMAND_NOP | 2592 FXP_CB_COMMAND_S | FXP_CB_COMMAND_I); 2593 /* 2594 * Advance the end of list forward. 2595 */ 2596 sc->fxp_desc.tx_last->tx_cb->cb_command &= 2597 htole16(~FXP_CB_COMMAND_S); 2598 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE); 2599 sc->fxp_desc.tx_last = txp; 2600 sc->tx_queued++; 2601 /* 2602 * Issue a resume in case the CU has just suspended. 2603 */ 2604 fxp_scb_wait(sc); 2605 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_RESUME); 2606 /* 2607 * Set a 5 second timer just in case we don't hear from the 2608 * card again. 2609 */ 2610 ifp->if_timer = 5; 2611 2612 return; 2613 } 2614 sc->need_mcsetup = 0; 2615 2616 /* 2617 * Initialize multicast setup descriptor. 2618 */ 2619 mcsp->cb_status = 0; 2620 mcsp->cb_command = htole16(FXP_CB_COMMAND_MCAS | 2621 FXP_CB_COMMAND_S | FXP_CB_COMMAND_I); 2622 mcsp->link_addr = htole32(sc->fxp_desc.cbl_addr); 2623 txp = &sc->fxp_desc.mcs_tx; 2624 txp->tx_mbuf = NULL; 2625 txp->tx_cb = (struct fxp_cb_tx *)sc->mcsp; 2626 txp->tx_next = sc->fxp_desc.tx_list; 2627 (void) fxp_mc_addrs(sc); 2628 sc->fxp_desc.tx_first = sc->fxp_desc.tx_last = txp; 2629 sc->tx_queued = 1; 2630 2631 /* 2632 * Wait until command unit is not active. This should never 2633 * be the case when nothing is queued, but make sure anyway. 2634 */ 2635 count = 100; 2636 while ((CSR_READ_1(sc, FXP_CSR_SCB_RUSCUS) >> 6) == 2637 FXP_SCB_CUS_ACTIVE && --count) 2638 DELAY(10); 2639 if (count == 0) { 2640 device_printf(sc->dev, "command queue timeout\n"); 2641 return; 2642 } 2643 2644 /* 2645 * Start the multicast setup command. 2646 */ 2647 fxp_scb_wait(sc); 2648 bus_dmamap_sync(sc->mcs_tag, sc->mcs_map, BUS_DMASYNC_PREWRITE); 2649 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->mcs_addr); 2650 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2651 2652 ifp->if_timer = 2; 2653 return; 2654 } 2655 2656 static u_int32_t fxp_ucode_d101a[] = D101_A_RCVBUNDLE_UCODE; 2657 static u_int32_t fxp_ucode_d101b0[] = D101_B0_RCVBUNDLE_UCODE; 2658 static u_int32_t fxp_ucode_d101ma[] = D101M_B_RCVBUNDLE_UCODE; 2659 static u_int32_t fxp_ucode_d101s[] = D101S_RCVBUNDLE_UCODE; 2660 static u_int32_t fxp_ucode_d102[] = D102_B_RCVBUNDLE_UCODE; 2661 static u_int32_t fxp_ucode_d102c[] = D102_C_RCVBUNDLE_UCODE; 2662 2663 #define UCODE(x) x, sizeof(x) 2664 2665 struct ucode { 2666 u_int32_t revision; 2667 u_int32_t *ucode; 2668 int length; 2669 u_short int_delay_offset; 2670 u_short bundle_max_offset; 2671 } ucode_table[] = { 2672 { FXP_REV_82558_A4, UCODE(fxp_ucode_d101a), D101_CPUSAVER_DWORD, 0 }, 2673 { FXP_REV_82558_B0, UCODE(fxp_ucode_d101b0), D101_CPUSAVER_DWORD, 0 }, 2674 { FXP_REV_82559_A0, UCODE(fxp_ucode_d101ma), 2675 D101M_CPUSAVER_DWORD, D101M_CPUSAVER_BUNDLE_MAX_DWORD }, 2676 { FXP_REV_82559S_A, UCODE(fxp_ucode_d101s), 2677 D101S_CPUSAVER_DWORD, D101S_CPUSAVER_BUNDLE_MAX_DWORD }, 2678 { FXP_REV_82550, UCODE(fxp_ucode_d102), 2679 D102_B_CPUSAVER_DWORD, D102_B_CPUSAVER_BUNDLE_MAX_DWORD }, 2680 { FXP_REV_82550_C, UCODE(fxp_ucode_d102c), 2681 D102_C_CPUSAVER_DWORD, D102_C_CPUSAVER_BUNDLE_MAX_DWORD }, 2682 { 0, NULL, 0, 0, 0 } 2683 }; 2684 2685 static void 2686 fxp_load_ucode(struct fxp_softc *sc) 2687 { 2688 struct ucode *uc; 2689 struct fxp_cb_ucode *cbp; 2690 2691 for (uc = ucode_table; uc->ucode != NULL; uc++) 2692 if (sc->revision == uc->revision) 2693 break; 2694 if (uc->ucode == NULL) 2695 return; 2696 cbp = (struct fxp_cb_ucode *)sc->fxp_desc.cbl_list; 2697 cbp->cb_status = 0; 2698 cbp->cb_command = htole16(FXP_CB_COMMAND_UCODE | FXP_CB_COMMAND_EL); 2699 cbp->link_addr = 0xffffffff; /* (no) next command */ 2700 memcpy(cbp->ucode, uc->ucode, uc->length); 2701 if (uc->int_delay_offset) 2702 *(u_int16_t *)&cbp->ucode[uc->int_delay_offset] = 2703 htole16(sc->tunable_int_delay + sc->tunable_int_delay / 2); 2704 if (uc->bundle_max_offset) 2705 *(u_int16_t *)&cbp->ucode[uc->bundle_max_offset] = 2706 htole16(sc->tunable_bundle_max); 2707 /* 2708 * Download the ucode to the chip. 2709 */ 2710 fxp_scb_wait(sc); 2711 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE); 2712 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->fxp_desc.cbl_addr); 2713 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2714 /* ...and wait for it to complete. */ 2715 fxp_dma_wait(sc, &cbp->cb_status, sc->cbl_tag, sc->cbl_map); 2716 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_POSTWRITE); 2717 device_printf(sc->dev, 2718 "Microcode loaded, int_delay: %d usec bundle_max: %d\n", 2719 sc->tunable_int_delay, 2720 uc->bundle_max_offset == 0 ? 0 : sc->tunable_bundle_max); 2721 sc->flags |= FXP_FLAG_UCODE; 2722 } 2723 2724 static int 2725 sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high) 2726 { 2727 int error, value; 2728 2729 value = *(int *)arg1; 2730 error = sysctl_handle_int(oidp, &value, 0, req); 2731 if (error || !req->newptr) 2732 return (error); 2733 if (value < low || value > high) 2734 return (EINVAL); 2735 *(int *)arg1 = value; 2736 return (0); 2737 } 2738 2739 /* 2740 * Interrupt delay is expressed in microseconds, a multiplier is used 2741 * to convert this to the appropriate clock ticks before using. 2742 */ 2743 static int 2744 sysctl_hw_fxp_int_delay(SYSCTL_HANDLER_ARGS) 2745 { 2746 return (sysctl_int_range(oidp, arg1, arg2, req, 300, 3000)); 2747 } 2748 2749 static int 2750 sysctl_hw_fxp_bundle_max(SYSCTL_HANDLER_ARGS) 2751 { 2752 return (sysctl_int_range(oidp, arg1, arg2, req, 1, 0xffff)); 2753 } 2754