xref: /freebsd/sys/dev/fxp/if_fxp.c (revision 1e413cf93298b5b97441a21d9a50fdcd0ee9945e)
1 /*-
2  * Copyright (c) 1995, David Greenman
3  * Copyright (c) 2001 Jonathan Lemon <jlemon@freebsd.org>
4  * All rights reserved.
5  *
6  * Redistribution and use in source and binary forms, with or without
7  * modification, are permitted provided that the following conditions
8  * are met:
9  * 1. Redistributions of source code must retain the above copyright
10  *    notice unmodified, this list of conditions, and the following
11  *    disclaimer.
12  * 2. Redistributions in binary form must reproduce the above copyright
13  *    notice, this list of conditions and the following disclaimer in the
14  *    documentation and/or other materials provided with the distribution.
15  *
16  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26  * SUCH DAMAGE.
27  *
28  */
29 
30 #include <sys/cdefs.h>
31 __FBSDID("$FreeBSD$");
32 
33 /*
34  * Intel EtherExpress Pro/100B PCI Fast Ethernet driver
35  */
36 
37 #ifdef HAVE_KERNEL_OPTION_HEADERS
38 #include "opt_device_polling.h"
39 #endif
40 
41 #include <sys/param.h>
42 #include <sys/systm.h>
43 #include <sys/endian.h>
44 #include <sys/mbuf.h>
45 		/* #include <sys/mutex.h> */
46 #include <sys/kernel.h>
47 #include <sys/module.h>
48 #include <sys/socket.h>
49 #include <sys/sysctl.h>
50 
51 #include <net/if.h>
52 #include <net/if_dl.h>
53 #include <net/if_media.h>
54 
55 #include <net/bpf.h>
56 #include <sys/sockio.h>
57 #include <sys/bus.h>
58 #include <machine/bus.h>
59 #include <sys/rman.h>
60 #include <machine/resource.h>
61 
62 #include <net/ethernet.h>
63 #include <net/if_arp.h>
64 
65 
66 #include <net/if_types.h>
67 #include <net/if_vlan_var.h>
68 
69 #ifdef FXP_IP_CSUM_WAR
70 #include <netinet/in.h>
71 #include <netinet/in_systm.h>
72 #include <netinet/ip.h>
73 #include <machine/in_cksum.h>
74 #endif
75 
76 #include <dev/pci/pcivar.h>
77 #include <dev/pci/pcireg.h>		/* for PCIM_CMD_xxx */
78 
79 #include <dev/mii/mii.h>
80 #include <dev/mii/miivar.h>
81 
82 #include <dev/fxp/if_fxpreg.h>
83 #include <dev/fxp/if_fxpvar.h>
84 #include <dev/fxp/rcvbundl.h>
85 
86 MODULE_DEPEND(fxp, pci, 1, 1, 1);
87 MODULE_DEPEND(fxp, ether, 1, 1, 1);
88 MODULE_DEPEND(fxp, miibus, 1, 1, 1);
89 #include "miibus_if.h"
90 
91 /*
92  * NOTE!  On the Alpha, we have an alignment constraint.  The
93  * card DMAs the packet immediately following the RFA.  However,
94  * the first thing in the packet is a 14-byte Ethernet header.
95  * This means that the packet is misaligned.  To compensate,
96  * we actually offset the RFA 2 bytes into the cluster.  This
97  * alignes the packet after the Ethernet header at a 32-bit
98  * boundary.  HOWEVER!  This means that the RFA is misaligned!
99  */
100 #define	RFA_ALIGNMENT_FUDGE	2
101 
102 /*
103  * Set initial transmit threshold at 64 (512 bytes). This is
104  * increased by 64 (512 bytes) at a time, to maximum of 192
105  * (1536 bytes), if an underrun occurs.
106  */
107 static int tx_threshold = 64;
108 
109 /*
110  * The configuration byte map has several undefined fields which
111  * must be one or must be zero.  Set up a template for these bits
112  * only, (assuming a 82557 chip) leaving the actual configuration
113  * to fxp_init.
114  *
115  * See struct fxp_cb_config for the bit definitions.
116  */
117 static u_char fxp_cb_config_template[] = {
118 	0x0, 0x0,		/* cb_status */
119 	0x0, 0x0,		/* cb_command */
120 	0x0, 0x0, 0x0, 0x0,	/* link_addr */
121 	0x0,	/*  0 */
122 	0x0,	/*  1 */
123 	0x0,	/*  2 */
124 	0x0,	/*  3 */
125 	0x0,	/*  4 */
126 	0x0,	/*  5 */
127 	0x32,	/*  6 */
128 	0x0,	/*  7 */
129 	0x0,	/*  8 */
130 	0x0,	/*  9 */
131 	0x6,	/* 10 */
132 	0x0,	/* 11 */
133 	0x0,	/* 12 */
134 	0x0,	/* 13 */
135 	0xf2,	/* 14 */
136 	0x48,	/* 15 */
137 	0x0,	/* 16 */
138 	0x40,	/* 17 */
139 	0xf0,	/* 18 */
140 	0x0,	/* 19 */
141 	0x3f,	/* 20 */
142 	0x5	/* 21 */
143 };
144 
145 struct fxp_ident {
146 	uint16_t	devid;
147 	int16_t		revid;		/* -1 matches anything */
148 	char 		*name;
149 };
150 
151 /*
152  * Claim various Intel PCI device identifiers for this driver.  The
153  * sub-vendor and sub-device field are extensively used to identify
154  * particular variants, but we don't currently differentiate between
155  * them.
156  */
157 static struct fxp_ident fxp_ident_table[] = {
158     { 0x1029,	-1,	"Intel 82559 PCI/CardBus Pro/100" },
159     { 0x1030,	-1,	"Intel 82559 Pro/100 Ethernet" },
160     { 0x1031,	-1,	"Intel 82801CAM (ICH3) Pro/100 VE Ethernet" },
161     { 0x1032,	-1,	"Intel 82801CAM (ICH3) Pro/100 VE Ethernet" },
162     { 0x1033,	-1,	"Intel 82801CAM (ICH3) Pro/100 VM Ethernet" },
163     { 0x1034,	-1,	"Intel 82801CAM (ICH3) Pro/100 VM Ethernet" },
164     { 0x1035,	-1,	"Intel 82801CAM (ICH3) Pro/100 Ethernet" },
165     { 0x1036,	-1,	"Intel 82801CAM (ICH3) Pro/100 Ethernet" },
166     { 0x1037,	-1,	"Intel 82801CAM (ICH3) Pro/100 Ethernet" },
167     { 0x1038,	-1,	"Intel 82801CAM (ICH3) Pro/100 VM Ethernet" },
168     { 0x1039,	-1,	"Intel 82801DB (ICH4) Pro/100 VE Ethernet" },
169     { 0x103A,	-1,	"Intel 82801DB (ICH4) Pro/100 Ethernet" },
170     { 0x103B,	-1,	"Intel 82801DB (ICH4) Pro/100 VM Ethernet" },
171     { 0x103C,	-1,	"Intel 82801DB (ICH4) Pro/100 Ethernet" },
172     { 0x103D,	-1,	"Intel 82801DB (ICH4) Pro/100 VE Ethernet" },
173     { 0x103E,	-1,	"Intel 82801DB (ICH4) Pro/100 VM Ethernet" },
174     { 0x1050,	-1,	"Intel 82801BA (D865) Pro/100 VE Ethernet" },
175     { 0x1051,	-1,	"Intel 82562ET (ICH5/ICH5R) Pro/100 VE Ethernet" },
176     { 0x1059,	-1,	"Intel 82551QM Pro/100 M Mobile Connection" },
177     { 0x1064,	-1,	"Intel 82562EZ (ICH6)" },
178     { 0x1065,	-1,	"Intel 82562ET/EZ/GT/GZ PRO/100 VE Ethernet" },
179     { 0x1068,	-1,	"Intel 82801FBM (ICH6-M) Pro/100 VE Ethernet" },
180     { 0x1069,	-1,	"Intel 82562EM/EX/GX Pro/100 Ethernet" },
181     { 0x1091,	-1,	"Intel 82562GX Pro/100 Ethernet" },
182     { 0x1092,	-1,	"Intel Pro/100 VE Network Connection" },
183     { 0x1093,	-1,	"Intel Pro/100 VM Network Connection" },
184     { 0x1094,	-1,	"Intel Pro/100 946GZ (ICH7) Network Connection" },
185     { 0x1209,	-1,	"Intel 82559ER Embedded 10/100 Ethernet" },
186     { 0x1229,	0x01,	"Intel 82557 Pro/100 Ethernet" },
187     { 0x1229,	0x02,	"Intel 82557 Pro/100 Ethernet" },
188     { 0x1229,	0x03,	"Intel 82557 Pro/100 Ethernet" },
189     { 0x1229,	0x04,	"Intel 82558 Pro/100 Ethernet" },
190     { 0x1229,	0x05,	"Intel 82558 Pro/100 Ethernet" },
191     { 0x1229,	0x06,	"Intel 82559 Pro/100 Ethernet" },
192     { 0x1229,	0x07,	"Intel 82559 Pro/100 Ethernet" },
193     { 0x1229,	0x08,	"Intel 82559 Pro/100 Ethernet" },
194     { 0x1229,	0x09,	"Intel 82559ER Pro/100 Ethernet" },
195     { 0x1229,	0x0c,	"Intel 82550 Pro/100 Ethernet" },
196     { 0x1229,	0x0d,	"Intel 82550 Pro/100 Ethernet" },
197     { 0x1229,	0x0e,	"Intel 82550 Pro/100 Ethernet" },
198     { 0x1229,	0x0f,	"Intel 82551 Pro/100 Ethernet" },
199     { 0x1229,	0x10,	"Intel 82551 Pro/100 Ethernet" },
200     { 0x1229,	-1,	"Intel 82557/8/9 Pro/100 Ethernet" },
201     { 0x2449,	-1,	"Intel 82801BA/CAM (ICH2/3) Pro/100 Ethernet" },
202     { 0x27dc,	-1,	"Intel 82801GB (ICH7) 10/100 Ethernet" },
203     { 0,	-1,	NULL },
204 };
205 
206 #ifdef FXP_IP_CSUM_WAR
207 #define FXP_CSUM_FEATURES    (CSUM_IP | CSUM_TCP | CSUM_UDP)
208 #else
209 #define FXP_CSUM_FEATURES    (CSUM_TCP | CSUM_UDP)
210 #endif
211 
212 static int		fxp_probe(device_t dev);
213 static int		fxp_attach(device_t dev);
214 static int		fxp_detach(device_t dev);
215 static int		fxp_shutdown(device_t dev);
216 static int		fxp_suspend(device_t dev);
217 static int		fxp_resume(device_t dev);
218 
219 static void		fxp_intr(void *xsc);
220 static void		fxp_intr_body(struct fxp_softc *sc, struct ifnet *ifp,
221 			    uint8_t statack, int count);
222 static void 		fxp_init(void *xsc);
223 static void 		fxp_init_body(struct fxp_softc *sc);
224 static void 		fxp_tick(void *xsc);
225 static void 		fxp_start(struct ifnet *ifp);
226 static void 		fxp_start_body(struct ifnet *ifp);
227 static int		fxp_encap(struct fxp_softc *sc, struct mbuf *m_head);
228 static void		fxp_stop(struct fxp_softc *sc);
229 static void 		fxp_release(struct fxp_softc *sc);
230 static int		fxp_ioctl(struct ifnet *ifp, u_long command,
231 			    caddr_t data);
232 static void 		fxp_watchdog(struct fxp_softc *sc);
233 static int		fxp_add_rfabuf(struct fxp_softc *sc,
234     			    struct fxp_rx *rxp);
235 static int		fxp_mc_addrs(struct fxp_softc *sc);
236 static void		fxp_mc_setup(struct fxp_softc *sc);
237 static uint16_t		fxp_eeprom_getword(struct fxp_softc *sc, int offset,
238 			    int autosize);
239 static void 		fxp_eeprom_putword(struct fxp_softc *sc, int offset,
240 			    uint16_t data);
241 static void		fxp_autosize_eeprom(struct fxp_softc *sc);
242 static void		fxp_read_eeprom(struct fxp_softc *sc, u_short *data,
243 			    int offset, int words);
244 static void		fxp_write_eeprom(struct fxp_softc *sc, u_short *data,
245 			    int offset, int words);
246 static int		fxp_ifmedia_upd(struct ifnet *ifp);
247 static void		fxp_ifmedia_sts(struct ifnet *ifp,
248 			    struct ifmediareq *ifmr);
249 static int		fxp_serial_ifmedia_upd(struct ifnet *ifp);
250 static void		fxp_serial_ifmedia_sts(struct ifnet *ifp,
251 			    struct ifmediareq *ifmr);
252 static int		fxp_miibus_readreg(device_t dev, int phy, int reg);
253 static void		fxp_miibus_writereg(device_t dev, int phy, int reg,
254 			    int value);
255 static void		fxp_load_ucode(struct fxp_softc *sc);
256 static int		sysctl_int_range(SYSCTL_HANDLER_ARGS,
257 			    int low, int high);
258 static int		sysctl_hw_fxp_bundle_max(SYSCTL_HANDLER_ARGS);
259 static int		sysctl_hw_fxp_int_delay(SYSCTL_HANDLER_ARGS);
260 static void 		fxp_scb_wait(struct fxp_softc *sc);
261 static void		fxp_scb_cmd(struct fxp_softc *sc, int cmd);
262 static void		fxp_dma_wait(struct fxp_softc *sc,
263     			    volatile uint16_t *status, bus_dma_tag_t dmat,
264 			    bus_dmamap_t map);
265 
266 static device_method_t fxp_methods[] = {
267 	/* Device interface */
268 	DEVMETHOD(device_probe,		fxp_probe),
269 	DEVMETHOD(device_attach,	fxp_attach),
270 	DEVMETHOD(device_detach,	fxp_detach),
271 	DEVMETHOD(device_shutdown,	fxp_shutdown),
272 	DEVMETHOD(device_suspend,	fxp_suspend),
273 	DEVMETHOD(device_resume,	fxp_resume),
274 
275 	/* MII interface */
276 	DEVMETHOD(miibus_readreg,	fxp_miibus_readreg),
277 	DEVMETHOD(miibus_writereg,	fxp_miibus_writereg),
278 
279 	{ 0, 0 }
280 };
281 
282 static driver_t fxp_driver = {
283 	"fxp",
284 	fxp_methods,
285 	sizeof(struct fxp_softc),
286 };
287 
288 static devclass_t fxp_devclass;
289 
290 DRIVER_MODULE(fxp, pci, fxp_driver, fxp_devclass, 0, 0);
291 DRIVER_MODULE(fxp, cardbus, fxp_driver, fxp_devclass, 0, 0);
292 DRIVER_MODULE(miibus, fxp, miibus_driver, miibus_devclass, 0, 0);
293 
294 static struct resource_spec fxp_res_spec_mem[] = {
295 	{ SYS_RES_MEMORY,	FXP_PCI_MMBA,	RF_ACTIVE },
296 	{ SYS_RES_IRQ,		0,		RF_ACTIVE | RF_SHAREABLE },
297 	{ -1, 0 }
298 };
299 
300 static struct resource_spec fxp_res_spec_io[] = {
301 	{ SYS_RES_IOPORT,	FXP_PCI_IOBA,	RF_ACTIVE },
302 	{ SYS_RES_IRQ,		0,		RF_ACTIVE | RF_SHAREABLE },
303 	{ -1, 0 }
304 };
305 
306 /*
307  * Wait for the previous command to be accepted (but not necessarily
308  * completed).
309  */
310 static void
311 fxp_scb_wait(struct fxp_softc *sc)
312 {
313 	union {
314 		uint16_t w;
315 		uint8_t b[2];
316 	} flowctl;
317 	int i = 10000;
318 
319 	while (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) && --i)
320 		DELAY(2);
321 	if (i == 0) {
322 		flowctl.b[0] = CSR_READ_1(sc, FXP_CSR_FLOWCONTROL);
323 		flowctl.b[1] = CSR_READ_1(sc, FXP_CSR_FLOWCONTROL + 1);
324 		device_printf(sc->dev, "SCB timeout: 0x%x 0x%x 0x%x 0x%x\n",
325 		    CSR_READ_1(sc, FXP_CSR_SCB_COMMAND),
326 		    CSR_READ_1(sc, FXP_CSR_SCB_STATACK),
327 		    CSR_READ_1(sc, FXP_CSR_SCB_RUSCUS), flowctl.w);
328 	}
329 }
330 
331 static void
332 fxp_scb_cmd(struct fxp_softc *sc, int cmd)
333 {
334 
335 	if (cmd == FXP_SCB_COMMAND_CU_RESUME && sc->cu_resume_bug) {
336 		CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_CB_COMMAND_NOP);
337 		fxp_scb_wait(sc);
338 	}
339 	CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, cmd);
340 }
341 
342 static void
343 fxp_dma_wait(struct fxp_softc *sc, volatile uint16_t *status,
344     bus_dma_tag_t dmat, bus_dmamap_t map)
345 {
346 	int i = 10000;
347 
348 	bus_dmamap_sync(dmat, map, BUS_DMASYNC_POSTREAD);
349 	while (!(le16toh(*status) & FXP_CB_STATUS_C) && --i) {
350 		DELAY(2);
351 		bus_dmamap_sync(dmat, map, BUS_DMASYNC_POSTREAD);
352 	}
353 	if (i == 0)
354 		device_printf(sc->dev, "DMA timeout\n");
355 }
356 
357 /*
358  * Return identification string if this device is ours.
359  */
360 static int
361 fxp_probe(device_t dev)
362 {
363 	uint16_t devid;
364 	uint8_t revid;
365 	struct fxp_ident *ident;
366 
367 	if (pci_get_vendor(dev) == FXP_VENDORID_INTEL) {
368 		devid = pci_get_device(dev);
369 		revid = pci_get_revid(dev);
370 		for (ident = fxp_ident_table; ident->name != NULL; ident++) {
371 			if (ident->devid == devid &&
372 			    (ident->revid == revid || ident->revid == -1)) {
373 				device_set_desc(dev, ident->name);
374 				return (BUS_PROBE_DEFAULT);
375 			}
376 		}
377 	}
378 	return (ENXIO);
379 }
380 
381 static void
382 fxp_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error)
383 {
384 	uint32_t *addr;
385 
386 	if (error)
387 		return;
388 
389 	KASSERT(nseg == 1, ("too many DMA segments, %d should be 1", nseg));
390 	addr = arg;
391 	*addr = segs->ds_addr;
392 }
393 
394 static int
395 fxp_attach(device_t dev)
396 {
397 	struct fxp_softc *sc;
398 	struct fxp_cb_tx *tcbp;
399 	struct fxp_tx *txp;
400 	struct fxp_rx *rxp;
401 	struct ifnet *ifp;
402 	uint32_t val;
403 	uint16_t data, myea[ETHER_ADDR_LEN / 2];
404 	u_char eaddr[ETHER_ADDR_LEN];
405 	int i, prefer_iomap;
406 	int error;
407 
408 	error = 0;
409 	sc = device_get_softc(dev);
410 	sc->dev = dev;
411 	mtx_init(&sc->sc_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
412 	    MTX_DEF);
413 	callout_init_mtx(&sc->stat_ch, &sc->sc_mtx, 0);
414 	ifmedia_init(&sc->sc_media, 0, fxp_serial_ifmedia_upd,
415 	    fxp_serial_ifmedia_sts);
416 
417 	ifp = sc->ifp = if_alloc(IFT_ETHER);
418 	if (ifp == NULL) {
419 		device_printf(dev, "can not if_alloc()\n");
420 		error = ENOSPC;
421 		goto fail;
422 	}
423 
424 	/*
425 	 * Enable bus mastering.
426 	 */
427 	pci_enable_busmaster(dev);
428 	val = pci_read_config(dev, PCIR_COMMAND, 2);
429 
430 	/*
431 	 * Figure out which we should try first - memory mapping or i/o mapping?
432 	 * We default to memory mapping. Then we accept an override from the
433 	 * command line. Then we check to see which one is enabled.
434 	 */
435 	prefer_iomap = 0;
436 	resource_int_value(device_get_name(dev), device_get_unit(dev),
437 	    "prefer_iomap", &prefer_iomap);
438 	if (prefer_iomap)
439 		sc->fxp_spec = fxp_res_spec_io;
440 	else
441 		sc->fxp_spec = fxp_res_spec_mem;
442 
443 	error = bus_alloc_resources(dev, sc->fxp_spec, sc->fxp_res);
444 	if (error) {
445 		if (sc->fxp_spec == fxp_res_spec_mem)
446 			sc->fxp_spec = fxp_res_spec_io;
447 		else
448 			sc->fxp_spec = fxp_res_spec_mem;
449 		error = bus_alloc_resources(dev, sc->fxp_spec, sc->fxp_res);
450 	}
451 	if (error) {
452 		device_printf(dev, "could not allocate resources\n");
453 		error = ENXIO;
454 		goto fail;
455 	}
456 
457 	if (bootverbose) {
458 		device_printf(dev, "using %s space register mapping\n",
459 		   sc->fxp_spec == fxp_res_spec_mem ? "memory" : "I/O");
460 	}
461 
462 	/*
463 	 * Reset to a stable state.
464 	 */
465 	CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET);
466 	DELAY(10);
467 
468 	/*
469 	 * Find out how large of an SEEPROM we have.
470 	 */
471 	fxp_autosize_eeprom(sc);
472 
473 	/*
474 	 * Find out the chip revision; lump all 82557 revs together.
475 	 */
476 	fxp_read_eeprom(sc, &data, 5, 1);
477 	if ((data >> 8) == 1)
478 		sc->revision = FXP_REV_82557;
479 	else
480 		sc->revision = pci_get_revid(dev);
481 
482 	/*
483 	 * Determine whether we must use the 503 serial interface.
484 	 */
485 	fxp_read_eeprom(sc, &data, 6, 1);
486 	if (sc->revision == FXP_REV_82557 && (data & FXP_PHY_DEVICE_MASK) != 0
487 	    && (data & FXP_PHY_SERIAL_ONLY))
488 		sc->flags |= FXP_FLAG_SERIAL_MEDIA;
489 
490 	SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
491 	    SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
492 	    OID_AUTO, "int_delay", CTLTYPE_INT | CTLFLAG_RW,
493 	    &sc->tunable_int_delay, 0, sysctl_hw_fxp_int_delay, "I",
494 	    "FXP driver receive interrupt microcode bundling delay");
495 	SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
496 	    SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
497 	    OID_AUTO, "bundle_max", CTLTYPE_INT | CTLFLAG_RW,
498 	    &sc->tunable_bundle_max, 0, sysctl_hw_fxp_bundle_max, "I",
499 	    "FXP driver receive interrupt microcode bundle size limit");
500 	SYSCTL_ADD_INT(device_get_sysctl_ctx(dev),
501 	    SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
502 	    OID_AUTO, "rnr", CTLFLAG_RD, &sc->rnr, 0,
503 	    "FXP RNR events");
504 	SYSCTL_ADD_INT(device_get_sysctl_ctx(dev),
505 	    SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
506 	    OID_AUTO, "noflow", CTLFLAG_RW, &sc->tunable_noflow, 0,
507 	    "FXP flow control disabled");
508 
509 	/*
510 	 * Pull in device tunables.
511 	 */
512 	sc->tunable_int_delay = TUNABLE_INT_DELAY;
513 	sc->tunable_bundle_max = TUNABLE_BUNDLE_MAX;
514 	sc->tunable_noflow = 1;
515 	(void) resource_int_value(device_get_name(dev), device_get_unit(dev),
516 	    "int_delay", &sc->tunable_int_delay);
517 	(void) resource_int_value(device_get_name(dev), device_get_unit(dev),
518 	    "bundle_max", &sc->tunable_bundle_max);
519 	(void) resource_int_value(device_get_name(dev), device_get_unit(dev),
520 	    "noflow", &sc->tunable_noflow);
521 	sc->rnr = 0;
522 
523 	/*
524 	 * Enable workarounds for certain chip revision deficiencies.
525 	 *
526 	 * Systems based on the ICH2/ICH2-M chip from Intel, and possibly
527 	 * some systems based a normal 82559 design, have a defect where
528 	 * the chip can cause a PCI protocol violation if it receives
529 	 * a CU_RESUME command when it is entering the IDLE state.  The
530 	 * workaround is to disable Dynamic Standby Mode, so the chip never
531 	 * deasserts CLKRUN#, and always remains in an active state.
532 	 *
533 	 * See Intel 82801BA/82801BAM Specification Update, Errata #30.
534 	 */
535 	i = pci_get_device(dev);
536 	if (i == 0x2449 || (i > 0x1030 && i < 0x1039) ||
537 	    sc->revision >= FXP_REV_82559_A0) {
538 		fxp_read_eeprom(sc, &data, 10, 1);
539 		if (data & 0x02) {			/* STB enable */
540 			uint16_t cksum;
541 			int i;
542 
543 			device_printf(dev,
544 			    "Disabling dynamic standby mode in EEPROM\n");
545 			data &= ~0x02;
546 			fxp_write_eeprom(sc, &data, 10, 1);
547 			device_printf(dev, "New EEPROM ID: 0x%x\n", data);
548 			cksum = 0;
549 			for (i = 0; i < (1 << sc->eeprom_size) - 1; i++) {
550 				fxp_read_eeprom(sc, &data, i, 1);
551 				cksum += data;
552 			}
553 			i = (1 << sc->eeprom_size) - 1;
554 			cksum = 0xBABA - cksum;
555 			fxp_read_eeprom(sc, &data, i, 1);
556 			fxp_write_eeprom(sc, &cksum, i, 1);
557 			device_printf(dev,
558 			    "EEPROM checksum @ 0x%x: 0x%x -> 0x%x\n",
559 			    i, data, cksum);
560 #if 1
561 			/*
562 			 * If the user elects to continue, try the software
563 			 * workaround, as it is better than nothing.
564 			 */
565 			sc->flags |= FXP_FLAG_CU_RESUME_BUG;
566 #endif
567 		}
568 	}
569 
570 	/*
571 	 * If we are not a 82557 chip, we can enable extended features.
572 	 */
573 	if (sc->revision != FXP_REV_82557) {
574 		/*
575 		 * If MWI is enabled in the PCI configuration, and there
576 		 * is a valid cacheline size (8 or 16 dwords), then tell
577 		 * the board to turn on MWI.
578 		 */
579 		if (val & PCIM_CMD_MWRICEN &&
580 		    pci_read_config(dev, PCIR_CACHELNSZ, 1) != 0)
581 			sc->flags |= FXP_FLAG_MWI_ENABLE;
582 
583 		/* turn on the extended TxCB feature */
584 		sc->flags |= FXP_FLAG_EXT_TXCB;
585 
586 		/* enable reception of long frames for VLAN */
587 		sc->flags |= FXP_FLAG_LONG_PKT_EN;
588 	} else {
589 		/* a hack to get long VLAN frames on a 82557 */
590 		sc->flags |= FXP_FLAG_SAVE_BAD;
591 	}
592 
593 	/*
594 	 * Enable use of extended RFDs and TCBs for 82550
595 	 * and later chips. Note: we need extended TXCB support
596 	 * too, but that's already enabled by the code above.
597 	 * Be careful to do this only on the right devices.
598 	 */
599 	if (sc->revision == FXP_REV_82550 || sc->revision == FXP_REV_82550_C ||
600 	    sc->revision == FXP_REV_82551_E || sc->revision == FXP_REV_82551_F
601 	    || sc->revision == FXP_REV_82551_10) {
602 		sc->rfa_size = sizeof (struct fxp_rfa);
603 		sc->tx_cmd = FXP_CB_COMMAND_IPCBXMIT;
604 		sc->flags |= FXP_FLAG_EXT_RFA;
605 	} else {
606 		sc->rfa_size = sizeof (struct fxp_rfa) - FXP_RFAX_LEN;
607 		sc->tx_cmd = FXP_CB_COMMAND_XMIT;
608 	}
609 
610 	/*
611 	 * Allocate DMA tags and DMA safe memory.
612 	 */
613 	sc->maxtxseg = FXP_NTXSEG;
614 	if (sc->flags & FXP_FLAG_EXT_RFA)
615 		sc->maxtxseg--;
616 	error = bus_dma_tag_create(bus_get_dma_tag(dev), 2, 0,
617 	    BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
618 	    MCLBYTES * sc->maxtxseg, sc->maxtxseg, MCLBYTES, 0,
619 	    busdma_lock_mutex, &Giant, &sc->fxp_mtag);
620 	if (error) {
621 		device_printf(dev, "could not allocate dma tag\n");
622 		goto fail;
623 	}
624 
625 	error = bus_dma_tag_create(bus_get_dma_tag(dev), 4, 0,
626 	    BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
627 	    sizeof(struct fxp_stats), 1, sizeof(struct fxp_stats), 0,
628 	    busdma_lock_mutex, &Giant, &sc->fxp_stag);
629 	if (error) {
630 		device_printf(dev, "could not allocate dma tag\n");
631 		goto fail;
632 	}
633 
634 	error = bus_dmamem_alloc(sc->fxp_stag, (void **)&sc->fxp_stats,
635 	    BUS_DMA_NOWAIT | BUS_DMA_ZERO, &sc->fxp_smap);
636 	if (error)
637 		goto fail;
638 	error = bus_dmamap_load(sc->fxp_stag, sc->fxp_smap, sc->fxp_stats,
639 	    sizeof(struct fxp_stats), fxp_dma_map_addr, &sc->stats_addr, 0);
640 	if (error) {
641 		device_printf(dev, "could not map the stats buffer\n");
642 		goto fail;
643 	}
644 
645 	error = bus_dma_tag_create(bus_get_dma_tag(dev), 4, 0,
646 	    BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
647 	    FXP_TXCB_SZ, 1, FXP_TXCB_SZ, 0,
648 	    busdma_lock_mutex, &Giant, &sc->cbl_tag);
649 	if (error) {
650 		device_printf(dev, "could not allocate dma tag\n");
651 		goto fail;
652 	}
653 
654 	error = bus_dmamem_alloc(sc->cbl_tag, (void **)&sc->fxp_desc.cbl_list,
655 	    BUS_DMA_NOWAIT | BUS_DMA_ZERO, &sc->cbl_map);
656 	if (error)
657 		goto fail;
658 
659 	error = bus_dmamap_load(sc->cbl_tag, sc->cbl_map,
660 	    sc->fxp_desc.cbl_list, FXP_TXCB_SZ, fxp_dma_map_addr,
661 	    &sc->fxp_desc.cbl_addr, 0);
662 	if (error) {
663 		device_printf(dev, "could not map DMA memory\n");
664 		goto fail;
665 	}
666 
667 	error = bus_dma_tag_create(bus_get_dma_tag(dev), 4, 0,
668 	    BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
669 	    sizeof(struct fxp_cb_mcs), 1, sizeof(struct fxp_cb_mcs), 0,
670 	    busdma_lock_mutex, &Giant, &sc->mcs_tag);
671 	if (error) {
672 		device_printf(dev, "could not allocate dma tag\n");
673 		goto fail;
674 	}
675 
676 	error = bus_dmamem_alloc(sc->mcs_tag, (void **)&sc->mcsp,
677 	    BUS_DMA_NOWAIT, &sc->mcs_map);
678 	if (error)
679 		goto fail;
680 	error = bus_dmamap_load(sc->mcs_tag, sc->mcs_map, sc->mcsp,
681 	    sizeof(struct fxp_cb_mcs), fxp_dma_map_addr, &sc->mcs_addr, 0);
682 	if (error) {
683 		device_printf(dev, "can't map the multicast setup command\n");
684 		goto fail;
685 	}
686 
687 	/*
688 	 * Pre-allocate the TX DMA maps and setup the pointers to
689 	 * the TX command blocks.
690 	 */
691 	txp = sc->fxp_desc.tx_list;
692 	tcbp = sc->fxp_desc.cbl_list;
693 	for (i = 0; i < FXP_NTXCB; i++) {
694 		txp[i].tx_cb = tcbp + i;
695 		error = bus_dmamap_create(sc->fxp_mtag, 0, &txp[i].tx_map);
696 		if (error) {
697 			device_printf(dev, "can't create DMA map for TX\n");
698 			goto fail;
699 		}
700 	}
701 	error = bus_dmamap_create(sc->fxp_mtag, 0, &sc->spare_map);
702 	if (error) {
703 		device_printf(dev, "can't create spare DMA map\n");
704 		goto fail;
705 	}
706 
707 	/*
708 	 * Pre-allocate our receive buffers.
709 	 */
710 	sc->fxp_desc.rx_head = sc->fxp_desc.rx_tail = NULL;
711 	for (i = 0; i < FXP_NRFABUFS; i++) {
712 		rxp = &sc->fxp_desc.rx_list[i];
713 		error = bus_dmamap_create(sc->fxp_mtag, 0, &rxp->rx_map);
714 		if (error) {
715 			device_printf(dev, "can't create DMA map for RX\n");
716 			goto fail;
717 		}
718 		if (fxp_add_rfabuf(sc, rxp) != 0) {
719 			error = ENOMEM;
720 			goto fail;
721 		}
722 	}
723 
724 	/*
725 	 * Read MAC address.
726 	 */
727 	fxp_read_eeprom(sc, myea, 0, 3);
728 	eaddr[0] = myea[0] & 0xff;
729 	eaddr[1] = myea[0] >> 8;
730 	eaddr[2] = myea[1] & 0xff;
731 	eaddr[3] = myea[1] >> 8;
732 	eaddr[4] = myea[2] & 0xff;
733 	eaddr[5] = myea[2] >> 8;
734 	if (bootverbose) {
735 		device_printf(dev, "PCI IDs: %04x %04x %04x %04x %04x\n",
736 		    pci_get_vendor(dev), pci_get_device(dev),
737 		    pci_get_subvendor(dev), pci_get_subdevice(dev),
738 		    pci_get_revid(dev));
739 		fxp_read_eeprom(sc, &data, 10, 1);
740 		device_printf(dev, "Dynamic Standby mode is %s\n",
741 		    data & 0x02 ? "enabled" : "disabled");
742 	}
743 
744 	/*
745 	 * If this is only a 10Mbps device, then there is no MII, and
746 	 * the PHY will use a serial interface instead.
747 	 *
748 	 * The Seeq 80c24 AutoDUPLEX(tm) Ethernet Interface Adapter
749 	 * doesn't have a programming interface of any sort.  The
750 	 * media is sensed automatically based on how the link partner
751 	 * is configured.  This is, in essence, manual configuration.
752 	 */
753 	if (sc->flags & FXP_FLAG_SERIAL_MEDIA) {
754 		ifmedia_add(&sc->sc_media, IFM_ETHER|IFM_MANUAL, 0, NULL);
755 		ifmedia_set(&sc->sc_media, IFM_ETHER|IFM_MANUAL);
756 	} else {
757 		if (mii_phy_probe(dev, &sc->miibus, fxp_ifmedia_upd,
758 		    fxp_ifmedia_sts)) {
759 	                device_printf(dev, "MII without any PHY!\n");
760 			error = ENXIO;
761 			goto fail;
762 		}
763 	}
764 
765 	if_initname(ifp, device_get_name(dev), device_get_unit(dev));
766 	ifp->if_init = fxp_init;
767 	ifp->if_softc = sc;
768 	ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
769 	ifp->if_ioctl = fxp_ioctl;
770 	ifp->if_start = fxp_start;
771 
772 	ifp->if_capabilities = ifp->if_capenable = 0;
773 
774 	/* Enable checksum offload for 82550 or better chips */
775 	if (sc->flags & FXP_FLAG_EXT_RFA) {
776 		ifp->if_hwassist = FXP_CSUM_FEATURES;
777 		ifp->if_capabilities |= IFCAP_HWCSUM;
778 		ifp->if_capenable |= IFCAP_HWCSUM;
779 	}
780 
781 #ifdef DEVICE_POLLING
782 	/* Inform the world we support polling. */
783 	ifp->if_capabilities |= IFCAP_POLLING;
784 #endif
785 
786 	/*
787 	 * Attach the interface.
788 	 */
789 	ether_ifattach(ifp, eaddr);
790 
791 	/*
792 	 * Tell the upper layer(s) we support long frames.
793 	 * Must appear after the call to ether_ifattach() because
794 	 * ether_ifattach() sets ifi_hdrlen to the default value.
795 	 */
796 	ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
797 	ifp->if_capabilities |= IFCAP_VLAN_MTU;
798 	ifp->if_capenable |= IFCAP_VLAN_MTU; /* the hw bits already set */
799 
800 	/*
801 	 * Let the system queue as many packets as we have available
802 	 * TX descriptors.
803 	 */
804 	IFQ_SET_MAXLEN(&ifp->if_snd, FXP_NTXCB - 1);
805 	ifp->if_snd.ifq_drv_maxlen = FXP_NTXCB - 1;
806 	IFQ_SET_READY(&ifp->if_snd);
807 
808 	/*
809 	 * Hook our interrupt after all initialization is complete.
810 	 */
811 	error = bus_setup_intr(dev, sc->fxp_res[1], INTR_TYPE_NET | INTR_MPSAFE,
812 			       NULL, fxp_intr, sc, &sc->ih);
813 	if (error) {
814 		device_printf(dev, "could not setup irq\n");
815 		ether_ifdetach(sc->ifp);
816 		goto fail;
817 	}
818 
819 fail:
820 	if (error)
821 		fxp_release(sc);
822 	return (error);
823 }
824 
825 /*
826  * Release all resources.  The softc lock should not be held and the
827  * interrupt should already be torn down.
828  */
829 static void
830 fxp_release(struct fxp_softc *sc)
831 {
832 	struct fxp_rx *rxp;
833 	struct fxp_tx *txp;
834 	int i;
835 
836 	FXP_LOCK_ASSERT(sc, MA_NOTOWNED);
837 	KASSERT(sc->ih == NULL,
838 	    ("fxp_release() called with intr handle still active"));
839 	if (sc->miibus)
840 		device_delete_child(sc->dev, sc->miibus);
841 	bus_generic_detach(sc->dev);
842 	ifmedia_removeall(&sc->sc_media);
843 	if (sc->fxp_desc.cbl_list) {
844 		bus_dmamap_unload(sc->cbl_tag, sc->cbl_map);
845 		bus_dmamem_free(sc->cbl_tag, sc->fxp_desc.cbl_list,
846 		    sc->cbl_map);
847 	}
848 	if (sc->fxp_stats) {
849 		bus_dmamap_unload(sc->fxp_stag, sc->fxp_smap);
850 		bus_dmamem_free(sc->fxp_stag, sc->fxp_stats, sc->fxp_smap);
851 	}
852 	if (sc->mcsp) {
853 		bus_dmamap_unload(sc->mcs_tag, sc->mcs_map);
854 		bus_dmamem_free(sc->mcs_tag, sc->mcsp, sc->mcs_map);
855 	}
856 	bus_release_resources(sc->dev, sc->fxp_spec, sc->fxp_res);
857 	if (sc->fxp_mtag) {
858 		for (i = 0; i < FXP_NRFABUFS; i++) {
859 			rxp = &sc->fxp_desc.rx_list[i];
860 			if (rxp->rx_mbuf != NULL) {
861 				bus_dmamap_sync(sc->fxp_mtag, rxp->rx_map,
862 				    BUS_DMASYNC_POSTREAD);
863 				bus_dmamap_unload(sc->fxp_mtag, rxp->rx_map);
864 				m_freem(rxp->rx_mbuf);
865 			}
866 			bus_dmamap_destroy(sc->fxp_mtag, rxp->rx_map);
867 		}
868 		bus_dmamap_destroy(sc->fxp_mtag, sc->spare_map);
869 		for (i = 0; i < FXP_NTXCB; i++) {
870 			txp = &sc->fxp_desc.tx_list[i];
871 			if (txp->tx_mbuf != NULL) {
872 				bus_dmamap_sync(sc->fxp_mtag, txp->tx_map,
873 				    BUS_DMASYNC_POSTWRITE);
874 				bus_dmamap_unload(sc->fxp_mtag, txp->tx_map);
875 				m_freem(txp->tx_mbuf);
876 			}
877 			bus_dmamap_destroy(sc->fxp_mtag, txp->tx_map);
878 		}
879 		bus_dma_tag_destroy(sc->fxp_mtag);
880 	}
881 	if (sc->fxp_stag)
882 		bus_dma_tag_destroy(sc->fxp_stag);
883 	if (sc->cbl_tag)
884 		bus_dma_tag_destroy(sc->cbl_tag);
885 	if (sc->mcs_tag)
886 		bus_dma_tag_destroy(sc->mcs_tag);
887 	if (sc->ifp)
888 		if_free(sc->ifp);
889 
890 	mtx_destroy(&sc->sc_mtx);
891 }
892 
893 /*
894  * Detach interface.
895  */
896 static int
897 fxp_detach(device_t dev)
898 {
899 	struct fxp_softc *sc = device_get_softc(dev);
900 
901 #ifdef DEVICE_POLLING
902 	if (sc->ifp->if_capenable & IFCAP_POLLING)
903 		ether_poll_deregister(sc->ifp);
904 #endif
905 
906 	FXP_LOCK(sc);
907 	sc->suspended = 1;	/* Do same thing as we do for suspend */
908 	/*
909 	 * Stop DMA and drop transmit queue, but disable interrupts first.
910 	 */
911 	CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE);
912 	fxp_stop(sc);
913 	FXP_UNLOCK(sc);
914 	callout_drain(&sc->stat_ch);
915 
916 	/*
917 	 * Close down routes etc.
918 	 */
919 	ether_ifdetach(sc->ifp);
920 
921 	/*
922 	 * Unhook interrupt before dropping lock. This is to prevent
923 	 * races with fxp_intr().
924 	 */
925 	bus_teardown_intr(sc->dev, sc->fxp_res[1], sc->ih);
926 	sc->ih = NULL;
927 
928 	/* Release our allocated resources. */
929 	fxp_release(sc);
930 	return (0);
931 }
932 
933 /*
934  * Device shutdown routine. Called at system shutdown after sync. The
935  * main purpose of this routine is to shut off receiver DMA so that
936  * kernel memory doesn't get clobbered during warmboot.
937  */
938 static int
939 fxp_shutdown(device_t dev)
940 {
941 	struct fxp_softc *sc = device_get_softc(dev);
942 
943 	/*
944 	 * Make sure that DMA is disabled prior to reboot. Not doing
945 	 * do could allow DMA to corrupt kernel memory during the
946 	 * reboot before the driver initializes.
947 	 */
948 	FXP_LOCK(sc);
949 	fxp_stop(sc);
950 	FXP_UNLOCK(sc);
951 	return (0);
952 }
953 
954 /*
955  * Device suspend routine.  Stop the interface and save some PCI
956  * settings in case the BIOS doesn't restore them properly on
957  * resume.
958  */
959 static int
960 fxp_suspend(device_t dev)
961 {
962 	struct fxp_softc *sc = device_get_softc(dev);
963 
964 	FXP_LOCK(sc);
965 
966 	fxp_stop(sc);
967 
968 	sc->suspended = 1;
969 
970 	FXP_UNLOCK(sc);
971 	return (0);
972 }
973 
974 /*
975  * Device resume routine. re-enable busmastering, and restart the interface if
976  * appropriate.
977  */
978 static int
979 fxp_resume(device_t dev)
980 {
981 	struct fxp_softc *sc = device_get_softc(dev);
982 	struct ifnet *ifp = sc->ifp;
983 
984 	FXP_LOCK(sc);
985 
986 	CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET);
987 	DELAY(10);
988 
989 	/* reinitialize interface if necessary */
990 	if (ifp->if_flags & IFF_UP)
991 		fxp_init_body(sc);
992 
993 	sc->suspended = 0;
994 
995 	FXP_UNLOCK(sc);
996 	return (0);
997 }
998 
999 static void
1000 fxp_eeprom_shiftin(struct fxp_softc *sc, int data, int length)
1001 {
1002 	uint16_t reg;
1003 	int x;
1004 
1005 	/*
1006 	 * Shift in data.
1007 	 */
1008 	for (x = 1 << (length - 1); x; x >>= 1) {
1009 		if (data & x)
1010 			reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI;
1011 		else
1012 			reg = FXP_EEPROM_EECS;
1013 		CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg);
1014 		DELAY(1);
1015 		CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK);
1016 		DELAY(1);
1017 		CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg);
1018 		DELAY(1);
1019 	}
1020 }
1021 
1022 /*
1023  * Read from the serial EEPROM. Basically, you manually shift in
1024  * the read opcode (one bit at a time) and then shift in the address,
1025  * and then you shift out the data (all of this one bit at a time).
1026  * The word size is 16 bits, so you have to provide the address for
1027  * every 16 bits of data.
1028  */
1029 static uint16_t
1030 fxp_eeprom_getword(struct fxp_softc *sc, int offset, int autosize)
1031 {
1032 	uint16_t reg, data;
1033 	int x;
1034 
1035 	CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS);
1036 	/*
1037 	 * Shift in read opcode.
1038 	 */
1039 	fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_READ, 3);
1040 	/*
1041 	 * Shift in address.
1042 	 */
1043 	data = 0;
1044 	for (x = 1 << (sc->eeprom_size - 1); x; x >>= 1) {
1045 		if (offset & x)
1046 			reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI;
1047 		else
1048 			reg = FXP_EEPROM_EECS;
1049 		CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg);
1050 		DELAY(1);
1051 		CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK);
1052 		DELAY(1);
1053 		CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg);
1054 		DELAY(1);
1055 		reg = CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO;
1056 		data++;
1057 		if (autosize && reg == 0) {
1058 			sc->eeprom_size = data;
1059 			break;
1060 		}
1061 	}
1062 	/*
1063 	 * Shift out data.
1064 	 */
1065 	data = 0;
1066 	reg = FXP_EEPROM_EECS;
1067 	for (x = 1 << 15; x; x >>= 1) {
1068 		CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK);
1069 		DELAY(1);
1070 		if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO)
1071 			data |= x;
1072 		CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg);
1073 		DELAY(1);
1074 	}
1075 	CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0);
1076 	DELAY(1);
1077 
1078 	return (data);
1079 }
1080 
1081 static void
1082 fxp_eeprom_putword(struct fxp_softc *sc, int offset, uint16_t data)
1083 {
1084 	int i;
1085 
1086 	/*
1087 	 * Erase/write enable.
1088 	 */
1089 	CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS);
1090 	fxp_eeprom_shiftin(sc, 0x4, 3);
1091 	fxp_eeprom_shiftin(sc, 0x03 << (sc->eeprom_size - 2), sc->eeprom_size);
1092 	CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0);
1093 	DELAY(1);
1094 	/*
1095 	 * Shift in write opcode, address, data.
1096 	 */
1097 	CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS);
1098 	fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_WRITE, 3);
1099 	fxp_eeprom_shiftin(sc, offset, sc->eeprom_size);
1100 	fxp_eeprom_shiftin(sc, data, 16);
1101 	CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0);
1102 	DELAY(1);
1103 	/*
1104 	 * Wait for EEPROM to finish up.
1105 	 */
1106 	CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS);
1107 	DELAY(1);
1108 	for (i = 0; i < 1000; i++) {
1109 		if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO)
1110 			break;
1111 		DELAY(50);
1112 	}
1113 	CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0);
1114 	DELAY(1);
1115 	/*
1116 	 * Erase/write disable.
1117 	 */
1118 	CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS);
1119 	fxp_eeprom_shiftin(sc, 0x4, 3);
1120 	fxp_eeprom_shiftin(sc, 0, sc->eeprom_size);
1121 	CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0);
1122 	DELAY(1);
1123 }
1124 
1125 /*
1126  * From NetBSD:
1127  *
1128  * Figure out EEPROM size.
1129  *
1130  * 559's can have either 64-word or 256-word EEPROMs, the 558
1131  * datasheet only talks about 64-word EEPROMs, and the 557 datasheet
1132  * talks about the existance of 16 to 256 word EEPROMs.
1133  *
1134  * The only known sizes are 64 and 256, where the 256 version is used
1135  * by CardBus cards to store CIS information.
1136  *
1137  * The address is shifted in msb-to-lsb, and after the last
1138  * address-bit the EEPROM is supposed to output a `dummy zero' bit,
1139  * after which follows the actual data. We try to detect this zero, by
1140  * probing the data-out bit in the EEPROM control register just after
1141  * having shifted in a bit. If the bit is zero, we assume we've
1142  * shifted enough address bits. The data-out should be tri-state,
1143  * before this, which should translate to a logical one.
1144  */
1145 static void
1146 fxp_autosize_eeprom(struct fxp_softc *sc)
1147 {
1148 
1149 	/* guess maximum size of 256 words */
1150 	sc->eeprom_size = 8;
1151 
1152 	/* autosize */
1153 	(void) fxp_eeprom_getword(sc, 0, 1);
1154 }
1155 
1156 static void
1157 fxp_read_eeprom(struct fxp_softc *sc, u_short *data, int offset, int words)
1158 {
1159 	int i;
1160 
1161 	for (i = 0; i < words; i++)
1162 		data[i] = fxp_eeprom_getword(sc, offset + i, 0);
1163 }
1164 
1165 static void
1166 fxp_write_eeprom(struct fxp_softc *sc, u_short *data, int offset, int words)
1167 {
1168 	int i;
1169 
1170 	for (i = 0; i < words; i++)
1171 		fxp_eeprom_putword(sc, offset + i, data[i]);
1172 }
1173 
1174 /*
1175  * Grab the softc lock and call the real fxp_start_body() routine
1176  */
1177 static void
1178 fxp_start(struct ifnet *ifp)
1179 {
1180 	struct fxp_softc *sc = ifp->if_softc;
1181 
1182 	FXP_LOCK(sc);
1183 	fxp_start_body(ifp);
1184 	FXP_UNLOCK(sc);
1185 }
1186 
1187 /*
1188  * Start packet transmission on the interface.
1189  * This routine must be called with the softc lock held, and is an
1190  * internal entry point only.
1191  */
1192 static void
1193 fxp_start_body(struct ifnet *ifp)
1194 {
1195 	struct fxp_softc *sc = ifp->if_softc;
1196 	struct mbuf *mb_head;
1197 	int error, txqueued;
1198 
1199 	FXP_LOCK_ASSERT(sc, MA_OWNED);
1200 
1201 	/*
1202 	 * See if we need to suspend xmit until the multicast filter
1203 	 * has been reprogrammed (which can only be done at the head
1204 	 * of the command chain).
1205 	 */
1206 	if (sc->need_mcsetup)
1207 		return;
1208 
1209 	/*
1210 	 * We're finished if there is nothing more to add to the list or if
1211 	 * we're all filled up with buffers to transmit.
1212 	 * NOTE: One TxCB is reserved to guarantee that fxp_mc_setup() can add
1213 	 *       a NOP command when needed.
1214 	 */
1215 	txqueued = 0;
1216 	while (!IFQ_DRV_IS_EMPTY(&ifp->if_snd) &&
1217 	    sc->tx_queued < FXP_NTXCB - 1) {
1218 
1219 		/*
1220 		 * Grab a packet to transmit.
1221 		 */
1222 		IFQ_DRV_DEQUEUE(&ifp->if_snd, mb_head);
1223 		if (mb_head == NULL)
1224 			break;
1225 
1226 		error = fxp_encap(sc, mb_head);
1227 		if (error)
1228 			break;
1229 		txqueued = 1;
1230 	}
1231 	bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE);
1232 
1233 	/*
1234 	 * We're finished. If we added to the list, issue a RESUME to get DMA
1235 	 * going again if suspended.
1236 	 */
1237 	if (txqueued) {
1238 		fxp_scb_wait(sc);
1239 		fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_RESUME);
1240 	}
1241 }
1242 
1243 static int
1244 fxp_encap(struct fxp_softc *sc, struct mbuf *m_head)
1245 {
1246 	struct ifnet *ifp;
1247 	struct mbuf *m;
1248 	struct fxp_tx *txp;
1249 	struct fxp_cb_tx *cbp;
1250 	bus_dma_segment_t segs[FXP_NTXSEG];
1251 	int chainlen, error, i, nseg;
1252 
1253 	FXP_LOCK_ASSERT(sc, MA_OWNED);
1254 	ifp = sc->ifp;
1255 
1256 	/*
1257 	 * Get pointer to next available tx desc.
1258 	 */
1259 	txp = sc->fxp_desc.tx_last->tx_next;
1260 
1261 	/*
1262 	 * A note in Appendix B of the Intel 8255x 10/100 Mbps
1263 	 * Ethernet Controller Family Open Source Software
1264 	 * Developer Manual says:
1265 	 *   Using software parsing is only allowed with legal
1266 	 *   TCP/IP or UDP/IP packets.
1267 	 *   ...
1268 	 *   For all other datagrams, hardware parsing must
1269 	 *   be used.
1270 	 * Software parsing appears to truncate ICMP and
1271 	 * fragmented UDP packets that contain one to three
1272 	 * bytes in the second (and final) mbuf of the packet.
1273 	 */
1274 	if (sc->flags & FXP_FLAG_EXT_RFA)
1275 		txp->tx_cb->ipcb_ip_activation_high =
1276 		    FXP_IPCB_HARDWAREPARSING_ENABLE;
1277 
1278 	/*
1279 	 * Deal with TCP/IP checksum offload. Note that
1280 	 * in order for TCP checksum offload to work,
1281 	 * the pseudo header checksum must have already
1282 	 * been computed and stored in the checksum field
1283 	 * in the TCP header. The stack should have
1284 	 * already done this for us.
1285 	 */
1286 	if (m_head->m_pkthdr.csum_flags) {
1287 		if (m_head->m_pkthdr.csum_flags & CSUM_DELAY_DATA) {
1288 			txp->tx_cb->ipcb_ip_schedule =
1289 			    FXP_IPCB_TCPUDP_CHECKSUM_ENABLE;
1290 			if (m_head->m_pkthdr.csum_flags & CSUM_TCP)
1291 				txp->tx_cb->ipcb_ip_schedule |=
1292 				    FXP_IPCB_TCP_PACKET;
1293 		}
1294 
1295 #ifdef FXP_IP_CSUM_WAR
1296 		/*
1297 		 * XXX The 82550 chip appears to have trouble
1298 		 * dealing with IP header checksums in very small
1299 		 * datagrams, namely fragments from 1 to 3 bytes
1300 		 * in size. For example, say you want to transmit
1301 		 * a UDP packet of 1473 bytes. The packet will be
1302 		 * fragmented over two IP datagrams, the latter
1303 		 * containing only one byte of data. The 82550 will
1304 		 * botch the header checksum on the 1-byte fragment.
1305 		 * As long as the datagram contains 4 or more bytes
1306 		 * of data, you're ok.
1307 		 *
1308                  * The following code attempts to work around this
1309 		 * problem: if the datagram is less than 38 bytes
1310 		 * in size (14 bytes ether header, 20 bytes IP header,
1311 		 * plus 4 bytes of data), we punt and compute the IP
1312 		 * header checksum by hand. This workaround doesn't
1313 		 * work very well, however, since it can be fooled
1314 		 * by things like VLAN tags and IP options that make
1315 		 * the header sizes/offsets vary.
1316 		 */
1317 
1318 		if (m_head->m_pkthdr.csum_flags & CSUM_IP) {
1319 			if (m_head->m_pkthdr.len < 38) {
1320 				struct ip *ip;
1321 				m_head->m_data += ETHER_HDR_LEN;
1322 				ip = mtod(mb_head, struct ip *);
1323 				ip->ip_sum = in_cksum(mb_head, ip->ip_hl << 2);
1324 				m_head->m_data -= ETHER_HDR_LEN;
1325 			} else {
1326 				txp->tx_cb->ipcb_ip_activation_high =
1327 				    FXP_IPCB_HARDWAREPARSING_ENABLE;
1328 				txp->tx_cb->ipcb_ip_schedule |=
1329 				    FXP_IPCB_IP_CHECKSUM_ENABLE;
1330 			}
1331 		}
1332 #endif
1333 	}
1334 
1335 	chainlen = 0;
1336 	for (m = m_head; m != NULL && chainlen <= sc->maxtxseg; m = m->m_next)
1337 		chainlen++;
1338 	if (chainlen > sc->maxtxseg) {
1339 		struct mbuf *mn;
1340 
1341 		/*
1342 		 * We ran out of segments. We have to recopy this
1343 		 * mbuf chain first. Bail out if we can't get the
1344 		 * new buffers.
1345 		 */
1346 		mn = m_defrag(m_head, M_DONTWAIT);
1347 		if (mn == NULL) {
1348 			m_freem(m_head);
1349 			return (-1);
1350 		} else {
1351 			m_head = mn;
1352 		}
1353 	}
1354 
1355 	/*
1356 	 * Go through each of the mbufs in the chain and initialize
1357 	 * the transmit buffer descriptors with the physical address
1358 	 * and size of the mbuf.
1359 	 */
1360 	error = bus_dmamap_load_mbuf_sg(sc->fxp_mtag, txp->tx_map,
1361 	    m_head, segs, &nseg, 0);
1362 	if (error) {
1363 		device_printf(sc->dev, "can't map mbuf (error %d)\n", error);
1364 		m_freem(m_head);
1365 		return (-1);
1366 	}
1367 
1368 	KASSERT(nseg <= sc->maxtxseg, ("too many DMA segments"));
1369 
1370 	cbp = txp->tx_cb;
1371 	for (i = 0; i < nseg; i++) {
1372 		KASSERT(segs[i].ds_len <= MCLBYTES, ("segment size too large"));
1373 		/*
1374 		 * If this is an 82550/82551, then we're using extended
1375 		 * TxCBs _and_ we're using checksum offload. This means
1376 		 * that the TxCB is really an IPCB. One major difference
1377 		 * between the two is that with plain extended TxCBs,
1378 		 * the bottom half of the TxCB contains two entries from
1379 		 * the TBD array, whereas IPCBs contain just one entry:
1380 		 * one entry (8 bytes) has been sacrificed for the TCP/IP
1381 		 * checksum offload control bits. So to make things work
1382 		 * right, we have to start filling in the TBD array
1383 		 * starting from a different place depending on whether
1384 		 * the chip is an 82550/82551 or not.
1385 		 */
1386 		if (sc->flags & FXP_FLAG_EXT_RFA) {
1387 			cbp->tbd[i + 1].tb_addr = htole32(segs[i].ds_addr);
1388 			cbp->tbd[i + 1].tb_size = htole32(segs[i].ds_len);
1389 		} else {
1390 			cbp->tbd[i].tb_addr = htole32(segs[i].ds_addr);
1391 			cbp->tbd[i].tb_size = htole32(segs[i].ds_len);
1392 		}
1393 	}
1394 	cbp->tbd_number = nseg;
1395 
1396 	bus_dmamap_sync(sc->fxp_mtag, txp->tx_map, BUS_DMASYNC_PREWRITE);
1397 	txp->tx_mbuf = m_head;
1398 	txp->tx_cb->cb_status = 0;
1399 	txp->tx_cb->byte_count = 0;
1400 	if (sc->tx_queued != FXP_CXINT_THRESH - 1) {
1401 		txp->tx_cb->cb_command =
1402 		    htole16(sc->tx_cmd | FXP_CB_COMMAND_SF |
1403 		    FXP_CB_COMMAND_S);
1404 	} else {
1405 		txp->tx_cb->cb_command =
1406 		    htole16(sc->tx_cmd | FXP_CB_COMMAND_SF |
1407 		    FXP_CB_COMMAND_S | FXP_CB_COMMAND_I);
1408 		/*
1409 		 * Set a 5 second timer just in case we don't hear
1410 		 * from the card again.
1411 		 */
1412 		sc->watchdog_timer = 5;
1413 	}
1414 	txp->tx_cb->tx_threshold = tx_threshold;
1415 
1416 	/*
1417 	 * Advance the end of list forward.
1418 	 */
1419 
1420 #ifdef __alpha__
1421 	/*
1422 	 * On platforms which can't access memory in 16-bit
1423 	 * granularities, we must prevent the card from DMA'ing
1424 	 * up the status while we update the command field.
1425 	 * This could cause us to overwrite the completion status.
1426 	 * XXX This is probably bogus and we're _not_ looking
1427 	 * for atomicity here.
1428 	 */
1429 	atomic_clear_16(&sc->fxp_desc.tx_last->tx_cb->cb_command,
1430 	    htole16(FXP_CB_COMMAND_S));
1431 #else
1432 	sc->fxp_desc.tx_last->tx_cb->cb_command &= htole16(~FXP_CB_COMMAND_S);
1433 #endif /*__alpha__*/
1434 	sc->fxp_desc.tx_last = txp;
1435 
1436 	/*
1437 	 * Advance the beginning of the list forward if there are
1438 	 * no other packets queued (when nothing is queued, tx_first
1439 	 * sits on the last TxCB that was sent out).
1440 	 */
1441 	if (sc->tx_queued == 0)
1442 		sc->fxp_desc.tx_first = txp;
1443 
1444 	sc->tx_queued++;
1445 
1446 	/*
1447 	 * Pass packet to bpf if there is a listener.
1448 	 */
1449 	BPF_MTAP(ifp, m_head);
1450 	return (0);
1451 }
1452 
1453 #ifdef DEVICE_POLLING
1454 static poll_handler_t fxp_poll;
1455 
1456 static void
1457 fxp_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
1458 {
1459 	struct fxp_softc *sc = ifp->if_softc;
1460 	uint8_t statack;
1461 
1462 	FXP_LOCK(sc);
1463 	if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) {
1464 		FXP_UNLOCK(sc);
1465 		return;
1466 	}
1467 
1468 	statack = FXP_SCB_STATACK_CXTNO | FXP_SCB_STATACK_CNA |
1469 	    FXP_SCB_STATACK_FR;
1470 	if (cmd == POLL_AND_CHECK_STATUS) {
1471 		uint8_t tmp;
1472 
1473 		tmp = CSR_READ_1(sc, FXP_CSR_SCB_STATACK);
1474 		if (tmp == 0xff || tmp == 0) {
1475 			FXP_UNLOCK(sc);
1476 			return; /* nothing to do */
1477 		}
1478 		tmp &= ~statack;
1479 		/* ack what we can */
1480 		if (tmp != 0)
1481 			CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, tmp);
1482 		statack |= tmp;
1483 	}
1484 	fxp_intr_body(sc, ifp, statack, count);
1485 	FXP_UNLOCK(sc);
1486 }
1487 #endif /* DEVICE_POLLING */
1488 
1489 /*
1490  * Process interface interrupts.
1491  */
1492 static void
1493 fxp_intr(void *xsc)
1494 {
1495 	struct fxp_softc *sc = xsc;
1496 	struct ifnet *ifp = sc->ifp;
1497 	uint8_t statack;
1498 
1499 	FXP_LOCK(sc);
1500 	if (sc->suspended) {
1501 		FXP_UNLOCK(sc);
1502 		return;
1503 	}
1504 
1505 #ifdef DEVICE_POLLING
1506 	if (ifp->if_capenable & IFCAP_POLLING) {
1507 		FXP_UNLOCK(sc);
1508 		return;
1509 	}
1510 #endif
1511 	while ((statack = CSR_READ_1(sc, FXP_CSR_SCB_STATACK)) != 0) {
1512 		/*
1513 		 * It should not be possible to have all bits set; the
1514 		 * FXP_SCB_INTR_SWI bit always returns 0 on a read.  If
1515 		 * all bits are set, this may indicate that the card has
1516 		 * been physically ejected, so ignore it.
1517 		 */
1518 		if (statack == 0xff) {
1519 			FXP_UNLOCK(sc);
1520 			return;
1521 		}
1522 
1523 		/*
1524 		 * First ACK all the interrupts in this pass.
1525 		 */
1526 		CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, statack);
1527 		fxp_intr_body(sc, ifp, statack, -1);
1528 	}
1529 	FXP_UNLOCK(sc);
1530 }
1531 
1532 static void
1533 fxp_txeof(struct fxp_softc *sc)
1534 {
1535 	struct fxp_tx *txp;
1536 
1537 	bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREREAD);
1538 	for (txp = sc->fxp_desc.tx_first; sc->tx_queued &&
1539 	    (le16toh(txp->tx_cb->cb_status) & FXP_CB_STATUS_C) != 0;
1540 	    txp = txp->tx_next) {
1541 		if (txp->tx_mbuf != NULL) {
1542 			bus_dmamap_sync(sc->fxp_mtag, txp->tx_map,
1543 			    BUS_DMASYNC_POSTWRITE);
1544 			bus_dmamap_unload(sc->fxp_mtag, txp->tx_map);
1545 			m_freem(txp->tx_mbuf);
1546 			txp->tx_mbuf = NULL;
1547 			/* clear this to reset csum offload bits */
1548 			txp->tx_cb->tbd[0].tb_addr = 0;
1549 		}
1550 		sc->tx_queued--;
1551 	}
1552 	sc->fxp_desc.tx_first = txp;
1553 	bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE);
1554 }
1555 
1556 static void
1557 fxp_intr_body(struct fxp_softc *sc, struct ifnet *ifp, uint8_t statack,
1558     int count)
1559 {
1560 	struct mbuf *m;
1561 	struct fxp_rx *rxp;
1562 	struct fxp_rfa *rfa;
1563 	int rnr = (statack & FXP_SCB_STATACK_RNR) ? 1 : 0;
1564 	int fxp_rc = 0;
1565 
1566 	FXP_LOCK_ASSERT(sc, MA_OWNED);
1567 	if (rnr)
1568 		sc->rnr++;
1569 #ifdef DEVICE_POLLING
1570 	/* Pick up a deferred RNR condition if `count' ran out last time. */
1571 	if (sc->flags & FXP_FLAG_DEFERRED_RNR) {
1572 		sc->flags &= ~FXP_FLAG_DEFERRED_RNR;
1573 		rnr = 1;
1574 	}
1575 #endif
1576 
1577 	/*
1578 	 * Free any finished transmit mbuf chains.
1579 	 *
1580 	 * Handle the CNA event likt a CXTNO event. It used to
1581 	 * be that this event (control unit not ready) was not
1582 	 * encountered, but it is now with the SMPng modifications.
1583 	 * The exact sequence of events that occur when the interface
1584 	 * is brought up are different now, and if this event
1585 	 * goes unhandled, the configuration/rxfilter setup sequence
1586 	 * can stall for several seconds. The result is that no
1587 	 * packets go out onto the wire for about 5 to 10 seconds
1588 	 * after the interface is ifconfig'ed for the first time.
1589 	 */
1590 	if (statack & (FXP_SCB_STATACK_CXTNO | FXP_SCB_STATACK_CNA)) {
1591 		fxp_txeof(sc);
1592 
1593 		sc->watchdog_timer = 0;
1594 		if (sc->tx_queued == 0) {
1595 			if (sc->need_mcsetup)
1596 				fxp_mc_setup(sc);
1597 		}
1598 		/*
1599 		 * Try to start more packets transmitting.
1600 		 */
1601 		if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
1602 			fxp_start_body(ifp);
1603 	}
1604 
1605 	/*
1606 	 * Just return if nothing happened on the receive side.
1607 	 */
1608 	if (!rnr && (statack & FXP_SCB_STATACK_FR) == 0)
1609 		return;
1610 
1611 	/*
1612 	 * Process receiver interrupts. If a no-resource (RNR)
1613 	 * condition exists, get whatever packets we can and
1614 	 * re-start the receiver.
1615 	 *
1616 	 * When using polling, we do not process the list to completion,
1617 	 * so when we get an RNR interrupt we must defer the restart
1618 	 * until we hit the last buffer with the C bit set.
1619 	 * If we run out of cycles and rfa_headm has the C bit set,
1620 	 * record the pending RNR in the FXP_FLAG_DEFERRED_RNR flag so
1621 	 * that the info will be used in the subsequent polling cycle.
1622 	 */
1623 	for (;;) {
1624 		rxp = sc->fxp_desc.rx_head;
1625 		m = rxp->rx_mbuf;
1626 		rfa = (struct fxp_rfa *)(m->m_ext.ext_buf +
1627 		    RFA_ALIGNMENT_FUDGE);
1628 		bus_dmamap_sync(sc->fxp_mtag, rxp->rx_map,
1629 		    BUS_DMASYNC_POSTREAD);
1630 
1631 #ifdef DEVICE_POLLING /* loop at most count times if count >=0 */
1632 		if (count >= 0 && count-- == 0) {
1633 			if (rnr) {
1634 				/* Defer RNR processing until the next time. */
1635 				sc->flags |= FXP_FLAG_DEFERRED_RNR;
1636 				rnr = 0;
1637 			}
1638 			break;
1639 		}
1640 #endif /* DEVICE_POLLING */
1641 
1642 		if ((le16toh(rfa->rfa_status) & FXP_RFA_STATUS_C) == 0)
1643 			break;
1644 
1645 		/*
1646 		 * Advance head forward.
1647 		 */
1648 		sc->fxp_desc.rx_head = rxp->rx_next;
1649 
1650 		/*
1651 		 * Add a new buffer to the receive chain.
1652 		 * If this fails, the old buffer is recycled
1653 		 * instead.
1654 		 */
1655 		fxp_rc = fxp_add_rfabuf(sc, rxp);
1656 		if (fxp_rc == 0) {
1657 			int total_len;
1658 
1659 			/*
1660 			 * Fetch packet length (the top 2 bits of
1661 			 * actual_size are flags set by the controller
1662 			 * upon completion), and drop the packet in case
1663 			 * of bogus length or CRC errors.
1664 			 */
1665 			total_len = le16toh(rfa->actual_size) & 0x3fff;
1666 			if (total_len < sizeof(struct ether_header) ||
1667 			    total_len > MCLBYTES - RFA_ALIGNMENT_FUDGE -
1668 				sc->rfa_size ||
1669 			    le16toh(rfa->rfa_status) & FXP_RFA_STATUS_CRC) {
1670 				m_freem(m);
1671 				continue;
1672 			}
1673 
1674                         /* Do IP checksum checking. */
1675 			if (le16toh(rfa->rfa_status) & FXP_RFA_STATUS_PARSE) {
1676 				if (rfa->rfax_csum_sts &
1677 				    FXP_RFDX_CS_IP_CSUM_BIT_VALID)
1678 					m->m_pkthdr.csum_flags |=
1679 					    CSUM_IP_CHECKED;
1680 				if (rfa->rfax_csum_sts &
1681 				    FXP_RFDX_CS_IP_CSUM_VALID)
1682 					m->m_pkthdr.csum_flags |=
1683 					    CSUM_IP_VALID;
1684 				if ((rfa->rfax_csum_sts &
1685 				    FXP_RFDX_CS_TCPUDP_CSUM_BIT_VALID) &&
1686 				    (rfa->rfax_csum_sts &
1687 				    FXP_RFDX_CS_TCPUDP_CSUM_VALID)) {
1688 					m->m_pkthdr.csum_flags |=
1689 					    CSUM_DATA_VALID|CSUM_PSEUDO_HDR;
1690 					m->m_pkthdr.csum_data = 0xffff;
1691 				}
1692 			}
1693 
1694 			m->m_pkthdr.len = m->m_len = total_len;
1695 			m->m_pkthdr.rcvif = ifp;
1696 
1697 			/*
1698 			 * Drop locks before calling if_input() since it
1699 			 * may re-enter fxp_start() in the netisr case.
1700 			 * This would result in a lock reversal.  Better
1701 			 * performance might be obtained by chaining all
1702 			 * packets received, dropping the lock, and then
1703 			 * calling if_input() on each one.
1704 			 */
1705 			FXP_UNLOCK(sc);
1706 			(*ifp->if_input)(ifp, m);
1707 			FXP_LOCK(sc);
1708 		} else if (fxp_rc == ENOBUFS) {
1709 			rnr = 0;
1710 			break;
1711 		}
1712 	}
1713 	if (rnr) {
1714 		fxp_scb_wait(sc);
1715 		CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL,
1716 		    sc->fxp_desc.rx_head->rx_addr);
1717 		fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_START);
1718 	}
1719 }
1720 
1721 /*
1722  * Update packet in/out/collision statistics. The i82557 doesn't
1723  * allow you to access these counters without doing a fairly
1724  * expensive DMA to get _all_ of the statistics it maintains, so
1725  * we do this operation here only once per second. The statistics
1726  * counters in the kernel are updated from the previous dump-stats
1727  * DMA and then a new dump-stats DMA is started. The on-chip
1728  * counters are zeroed when the DMA completes. If we can't start
1729  * the DMA immediately, we don't wait - we just prepare to read
1730  * them again next time.
1731  */
1732 static void
1733 fxp_tick(void *xsc)
1734 {
1735 	struct fxp_softc *sc = xsc;
1736 	struct ifnet *ifp = sc->ifp;
1737 	struct fxp_stats *sp = sc->fxp_stats;
1738 
1739 	FXP_LOCK_ASSERT(sc, MA_OWNED);
1740 	bus_dmamap_sync(sc->fxp_stag, sc->fxp_smap, BUS_DMASYNC_POSTREAD);
1741 	ifp->if_opackets += le32toh(sp->tx_good);
1742 	ifp->if_collisions += le32toh(sp->tx_total_collisions);
1743 	if (sp->rx_good) {
1744 		ifp->if_ipackets += le32toh(sp->rx_good);
1745 		sc->rx_idle_secs = 0;
1746 	} else {
1747 		/*
1748 		 * Receiver's been idle for another second.
1749 		 */
1750 		sc->rx_idle_secs++;
1751 	}
1752 	ifp->if_ierrors +=
1753 	    le32toh(sp->rx_crc_errors) +
1754 	    le32toh(sp->rx_alignment_errors) +
1755 	    le32toh(sp->rx_rnr_errors) +
1756 	    le32toh(sp->rx_overrun_errors);
1757 	/*
1758 	 * If any transmit underruns occured, bump up the transmit
1759 	 * threshold by another 512 bytes (64 * 8).
1760 	 */
1761 	if (sp->tx_underruns) {
1762 		ifp->if_oerrors += le32toh(sp->tx_underruns);
1763 		if (tx_threshold < 192)
1764 			tx_threshold += 64;
1765 	}
1766 
1767 	/*
1768 	 * Release any xmit buffers that have completed DMA. This isn't
1769 	 * strictly necessary to do here, but it's advantagous for mbufs
1770 	 * with external storage to be released in a timely manner rather
1771 	 * than being defered for a potentially long time. This limits
1772 	 * the delay to a maximum of one second.
1773 	 */
1774 	fxp_txeof(sc);
1775 
1776 	/*
1777 	 * If we haven't received any packets in FXP_MAC_RX_IDLE seconds,
1778 	 * then assume the receiver has locked up and attempt to clear
1779 	 * the condition by reprogramming the multicast filter. This is
1780 	 * a work-around for a bug in the 82557 where the receiver locks
1781 	 * up if it gets certain types of garbage in the syncronization
1782 	 * bits prior to the packet header. This bug is supposed to only
1783 	 * occur in 10Mbps mode, but has been seen to occur in 100Mbps
1784 	 * mode as well (perhaps due to a 10/100 speed transition).
1785 	 */
1786 	if (sc->rx_idle_secs > FXP_MAX_RX_IDLE) {
1787 		sc->rx_idle_secs = 0;
1788 		fxp_mc_setup(sc);
1789 	}
1790 	/*
1791 	 * If there is no pending command, start another stats
1792 	 * dump. Otherwise punt for now.
1793 	 */
1794 	if (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) == 0) {
1795 		/*
1796 		 * Start another stats dump.
1797 		 */
1798 		bus_dmamap_sync(sc->fxp_stag, sc->fxp_smap,
1799 		    BUS_DMASYNC_PREREAD);
1800 		fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_DUMPRESET);
1801 	} else {
1802 		/*
1803 		 * A previous command is still waiting to be accepted.
1804 		 * Just zero our copy of the stats and wait for the
1805 		 * next timer event to update them.
1806 		 */
1807 		sp->tx_good = 0;
1808 		sp->tx_underruns = 0;
1809 		sp->tx_total_collisions = 0;
1810 
1811 		sp->rx_good = 0;
1812 		sp->rx_crc_errors = 0;
1813 		sp->rx_alignment_errors = 0;
1814 		sp->rx_rnr_errors = 0;
1815 		sp->rx_overrun_errors = 0;
1816 	}
1817 	if (sc->miibus != NULL)
1818 		mii_tick(device_get_softc(sc->miibus));
1819 
1820 	/*
1821 	 * Check that chip hasn't hung.
1822 	 */
1823 	fxp_watchdog(sc);
1824 
1825 	/*
1826 	 * Schedule another timeout one second from now.
1827 	 */
1828 	callout_reset(&sc->stat_ch, hz, fxp_tick, sc);
1829 }
1830 
1831 /*
1832  * Stop the interface. Cancels the statistics updater and resets
1833  * the interface.
1834  */
1835 static void
1836 fxp_stop(struct fxp_softc *sc)
1837 {
1838 	struct ifnet *ifp = sc->ifp;
1839 	struct fxp_tx *txp;
1840 	int i;
1841 
1842 	ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
1843 	sc->watchdog_timer = 0;
1844 
1845 	/*
1846 	 * Cancel stats updater.
1847 	 */
1848 	callout_stop(&sc->stat_ch);
1849 
1850 	/*
1851 	 * Issue software reset, which also unloads the microcode.
1852 	 */
1853 	sc->flags &= ~FXP_FLAG_UCODE;
1854 	CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SOFTWARE_RESET);
1855 	DELAY(50);
1856 
1857 	/*
1858 	 * Release any xmit buffers.
1859 	 */
1860 	txp = sc->fxp_desc.tx_list;
1861 	if (txp != NULL) {
1862 		for (i = 0; i < FXP_NTXCB; i++) {
1863  			if (txp[i].tx_mbuf != NULL) {
1864 				bus_dmamap_sync(sc->fxp_mtag, txp[i].tx_map,
1865 				    BUS_DMASYNC_POSTWRITE);
1866 				bus_dmamap_unload(sc->fxp_mtag, txp[i].tx_map);
1867 				m_freem(txp[i].tx_mbuf);
1868 				txp[i].tx_mbuf = NULL;
1869 				/* clear this to reset csum offload bits */
1870 				txp[i].tx_cb->tbd[0].tb_addr = 0;
1871 			}
1872 		}
1873 	}
1874 	bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE);
1875 	sc->tx_queued = 0;
1876 }
1877 
1878 /*
1879  * Watchdog/transmission transmit timeout handler. Called when a
1880  * transmission is started on the interface, but no interrupt is
1881  * received before the timeout. This usually indicates that the
1882  * card has wedged for some reason.
1883  */
1884 static void
1885 fxp_watchdog(struct fxp_softc *sc)
1886 {
1887 
1888 	FXP_LOCK_ASSERT(sc, MA_OWNED);
1889 
1890 	if (sc->watchdog_timer == 0 || --sc->watchdog_timer)
1891 		return;
1892 
1893 	device_printf(sc->dev, "device timeout\n");
1894 	sc->ifp->if_oerrors++;
1895 
1896 	fxp_init_body(sc);
1897 }
1898 
1899 /*
1900  * Acquire locks and then call the real initialization function.  This
1901  * is necessary because ether_ioctl() calls if_init() and this would
1902  * result in mutex recursion if the mutex was held.
1903  */
1904 static void
1905 fxp_init(void *xsc)
1906 {
1907 	struct fxp_softc *sc = xsc;
1908 
1909 	FXP_LOCK(sc);
1910 	fxp_init_body(sc);
1911 	FXP_UNLOCK(sc);
1912 }
1913 
1914 /*
1915  * Perform device initialization. This routine must be called with the
1916  * softc lock held.
1917  */
1918 static void
1919 fxp_init_body(struct fxp_softc *sc)
1920 {
1921 	struct ifnet *ifp = sc->ifp;
1922 	struct fxp_cb_config *cbp;
1923 	struct fxp_cb_ias *cb_ias;
1924 	struct fxp_cb_tx *tcbp;
1925 	struct fxp_tx *txp;
1926 	struct fxp_cb_mcs *mcsp;
1927 	int i, prm;
1928 
1929 	FXP_LOCK_ASSERT(sc, MA_OWNED);
1930 	/*
1931 	 * Cancel any pending I/O
1932 	 */
1933 	fxp_stop(sc);
1934 
1935 	prm = (ifp->if_flags & IFF_PROMISC) ? 1 : 0;
1936 
1937 	/*
1938 	 * Initialize base of CBL and RFA memory. Loading with zero
1939 	 * sets it up for regular linear addressing.
1940 	 */
1941 	CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 0);
1942 	fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_BASE);
1943 
1944 	fxp_scb_wait(sc);
1945 	fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_BASE);
1946 
1947 	/*
1948 	 * Initialize base of dump-stats buffer.
1949 	 */
1950 	fxp_scb_wait(sc);
1951 	bus_dmamap_sync(sc->fxp_stag, sc->fxp_smap, BUS_DMASYNC_PREREAD);
1952 	CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->stats_addr);
1953 	fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_DUMP_ADR);
1954 
1955 	/*
1956 	 * Attempt to load microcode if requested.
1957 	 */
1958 	if (ifp->if_flags & IFF_LINK0 && (sc->flags & FXP_FLAG_UCODE) == 0)
1959 		fxp_load_ucode(sc);
1960 
1961 	/*
1962 	 * Initialize the multicast address list.
1963 	 */
1964 	if (fxp_mc_addrs(sc)) {
1965 		mcsp = sc->mcsp;
1966 		mcsp->cb_status = 0;
1967 		mcsp->cb_command =
1968 		    htole16(FXP_CB_COMMAND_MCAS | FXP_CB_COMMAND_EL);
1969 		mcsp->link_addr = 0xffffffff;
1970 		/*
1971 	 	 * Start the multicast setup command.
1972 		 */
1973 		fxp_scb_wait(sc);
1974 		bus_dmamap_sync(sc->mcs_tag, sc->mcs_map, BUS_DMASYNC_PREWRITE);
1975 		CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->mcs_addr);
1976 		fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START);
1977 		/* ...and wait for it to complete. */
1978 		fxp_dma_wait(sc, &mcsp->cb_status, sc->mcs_tag, sc->mcs_map);
1979 		bus_dmamap_sync(sc->mcs_tag, sc->mcs_map,
1980 		    BUS_DMASYNC_POSTWRITE);
1981 	}
1982 
1983 	/*
1984 	 * We temporarily use memory that contains the TxCB list to
1985 	 * construct the config CB. The TxCB list memory is rebuilt
1986 	 * later.
1987 	 */
1988 	cbp = (struct fxp_cb_config *)sc->fxp_desc.cbl_list;
1989 
1990 	/*
1991 	 * This bcopy is kind of disgusting, but there are a bunch of must be
1992 	 * zero and must be one bits in this structure and this is the easiest
1993 	 * way to initialize them all to proper values.
1994 	 */
1995 	bcopy(fxp_cb_config_template, cbp, sizeof(fxp_cb_config_template));
1996 
1997 	cbp->cb_status =	0;
1998 	cbp->cb_command =	htole16(FXP_CB_COMMAND_CONFIG |
1999 	    FXP_CB_COMMAND_EL);
2000 	cbp->link_addr =	0xffffffff;	/* (no) next command */
2001 	cbp->byte_count =	sc->flags & FXP_FLAG_EXT_RFA ? 32 : 22;
2002 	cbp->rx_fifo_limit =	8;	/* rx fifo threshold (32 bytes) */
2003 	cbp->tx_fifo_limit =	0;	/* tx fifo threshold (0 bytes) */
2004 	cbp->adaptive_ifs =	0;	/* (no) adaptive interframe spacing */
2005 	cbp->mwi_enable =	sc->flags & FXP_FLAG_MWI_ENABLE ? 1 : 0;
2006 	cbp->type_enable =	0;	/* actually reserved */
2007 	cbp->read_align_en =	sc->flags & FXP_FLAG_READ_ALIGN ? 1 : 0;
2008 	cbp->end_wr_on_cl =	sc->flags & FXP_FLAG_WRITE_ALIGN ? 1 : 0;
2009 	cbp->rx_dma_bytecount =	0;	/* (no) rx DMA max */
2010 	cbp->tx_dma_bytecount =	0;	/* (no) tx DMA max */
2011 	cbp->dma_mbce =		0;	/* (disable) dma max counters */
2012 	cbp->late_scb =		0;	/* (don't) defer SCB update */
2013 	cbp->direct_dma_dis =	1;	/* disable direct rcv dma mode */
2014 	cbp->tno_int_or_tco_en =0;	/* (disable) tx not okay interrupt */
2015 	cbp->ci_int =		1;	/* interrupt on CU idle */
2016 	cbp->ext_txcb_dis = 	sc->flags & FXP_FLAG_EXT_TXCB ? 0 : 1;
2017 	cbp->ext_stats_dis = 	1;	/* disable extended counters */
2018 	cbp->keep_overrun_rx = 	0;	/* don't pass overrun frames to host */
2019 	cbp->save_bf =		sc->flags & FXP_FLAG_SAVE_BAD ? 1 : prm;
2020 	cbp->disc_short_rx =	!prm;	/* discard short packets */
2021 	cbp->underrun_retry =	1;	/* retry mode (once) on DMA underrun */
2022 	cbp->two_frames =	0;	/* do not limit FIFO to 2 frames */
2023 	cbp->dyn_tbd =		0;	/* (no) dynamic TBD mode */
2024 	cbp->ext_rfa =		sc->flags & FXP_FLAG_EXT_RFA ? 1 : 0;
2025 	cbp->mediatype =	sc->flags & FXP_FLAG_SERIAL_MEDIA ? 0 : 1;
2026 	cbp->csma_dis =		0;	/* (don't) disable link */
2027 	cbp->tcp_udp_cksum =	0;	/* (don't) enable checksum */
2028 	cbp->vlan_tco =		0;	/* (don't) enable vlan wakeup */
2029 	cbp->link_wake_en =	0;	/* (don't) assert PME# on link change */
2030 	cbp->arp_wake_en =	0;	/* (don't) assert PME# on arp */
2031 	cbp->mc_wake_en =	0;	/* (don't) enable PME# on mcmatch */
2032 	cbp->nsai =		1;	/* (don't) disable source addr insert */
2033 	cbp->preamble_length =	2;	/* (7 byte) preamble */
2034 	cbp->loopback =		0;	/* (don't) loopback */
2035 	cbp->linear_priority =	0;	/* (normal CSMA/CD operation) */
2036 	cbp->linear_pri_mode =	0;	/* (wait after xmit only) */
2037 	cbp->interfrm_spacing =	6;	/* (96 bits of) interframe spacing */
2038 	cbp->promiscuous =	prm;	/* promiscuous mode */
2039 	cbp->bcast_disable =	0;	/* (don't) disable broadcasts */
2040 	cbp->wait_after_win =	0;	/* (don't) enable modified backoff alg*/
2041 	cbp->ignore_ul =	0;	/* consider U/L bit in IA matching */
2042 	cbp->crc16_en =		0;	/* (don't) enable crc-16 algorithm */
2043 	cbp->crscdt =		sc->flags & FXP_FLAG_SERIAL_MEDIA ? 1 : 0;
2044 
2045 	cbp->stripping =	!prm;	/* truncate rx packet to byte count */
2046 	cbp->padding =		1;	/* (do) pad short tx packets */
2047 	cbp->rcv_crc_xfer =	0;	/* (don't) xfer CRC to host */
2048 	cbp->long_rx_en =	sc->flags & FXP_FLAG_LONG_PKT_EN ? 1 : 0;
2049 	cbp->ia_wake_en =	0;	/* (don't) wake up on address match */
2050 	cbp->magic_pkt_dis =	0;	/* (don't) disable magic packet */
2051 					/* must set wake_en in PMCSR also */
2052 	cbp->force_fdx =	0;	/* (don't) force full duplex */
2053 	cbp->fdx_pin_en =	1;	/* (enable) FDX# pin */
2054 	cbp->multi_ia =		0;	/* (don't) accept multiple IAs */
2055 	cbp->mc_all =		sc->flags & FXP_FLAG_ALL_MCAST ? 1 : 0;
2056 	cbp->gamla_rx =		sc->flags & FXP_FLAG_EXT_RFA ? 1 : 0;
2057 
2058 	if (sc->tunable_noflow || sc->revision == FXP_REV_82557) {
2059 		/*
2060 		 * The 82557 has no hardware flow control, the values
2061 		 * below are the defaults for the chip.
2062 		 */
2063 		cbp->fc_delay_lsb =	0;
2064 		cbp->fc_delay_msb =	0x40;
2065 		cbp->pri_fc_thresh =	3;
2066 		cbp->tx_fc_dis =	0;
2067 		cbp->rx_fc_restop =	0;
2068 		cbp->rx_fc_restart =	0;
2069 		cbp->fc_filter =	0;
2070 		cbp->pri_fc_loc =	1;
2071 	} else {
2072 		cbp->fc_delay_lsb =	0x1f;
2073 		cbp->fc_delay_msb =	0x01;
2074 		cbp->pri_fc_thresh =	3;
2075 		cbp->tx_fc_dis =	0;	/* enable transmit FC */
2076 		cbp->rx_fc_restop =	1;	/* enable FC restop frames */
2077 		cbp->rx_fc_restart =	1;	/* enable FC restart frames */
2078 		cbp->fc_filter =	!prm;	/* drop FC frames to host */
2079 		cbp->pri_fc_loc =	1;	/* FC pri location (byte31) */
2080 	}
2081 
2082 	/*
2083 	 * Start the config command/DMA.
2084 	 */
2085 	fxp_scb_wait(sc);
2086 	bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE);
2087 	CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->fxp_desc.cbl_addr);
2088 	fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START);
2089 	/* ...and wait for it to complete. */
2090 	fxp_dma_wait(sc, &cbp->cb_status, sc->cbl_tag, sc->cbl_map);
2091 	bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_POSTWRITE);
2092 
2093 	/*
2094 	 * Now initialize the station address. Temporarily use the TxCB
2095 	 * memory area like we did above for the config CB.
2096 	 */
2097 	cb_ias = (struct fxp_cb_ias *)sc->fxp_desc.cbl_list;
2098 	cb_ias->cb_status = 0;
2099 	cb_ias->cb_command = htole16(FXP_CB_COMMAND_IAS | FXP_CB_COMMAND_EL);
2100 	cb_ias->link_addr = 0xffffffff;
2101 	bcopy(IF_LLADDR(sc->ifp), cb_ias->macaddr, ETHER_ADDR_LEN);
2102 
2103 	/*
2104 	 * Start the IAS (Individual Address Setup) command/DMA.
2105 	 */
2106 	fxp_scb_wait(sc);
2107 	bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE);
2108 	fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START);
2109 	/* ...and wait for it to complete. */
2110 	fxp_dma_wait(sc, &cb_ias->cb_status, sc->cbl_tag, sc->cbl_map);
2111 	bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_POSTWRITE);
2112 
2113 	/*
2114 	 * Initialize transmit control block (TxCB) list.
2115 	 */
2116 	txp = sc->fxp_desc.tx_list;
2117 	tcbp = sc->fxp_desc.cbl_list;
2118 	bzero(tcbp, FXP_TXCB_SZ);
2119 	for (i = 0; i < FXP_NTXCB; i++) {
2120 		txp[i].tx_mbuf = NULL;
2121 		tcbp[i].cb_status = htole16(FXP_CB_STATUS_C | FXP_CB_STATUS_OK);
2122 		tcbp[i].cb_command = htole16(FXP_CB_COMMAND_NOP);
2123 		tcbp[i].link_addr = htole32(sc->fxp_desc.cbl_addr +
2124 		    (((i + 1) & FXP_TXCB_MASK) * sizeof(struct fxp_cb_tx)));
2125 		if (sc->flags & FXP_FLAG_EXT_TXCB)
2126 			tcbp[i].tbd_array_addr =
2127 			    htole32(FXP_TXCB_DMA_ADDR(sc, &tcbp[i].tbd[2]));
2128 		else
2129 			tcbp[i].tbd_array_addr =
2130 			    htole32(FXP_TXCB_DMA_ADDR(sc, &tcbp[i].tbd[0]));
2131 		txp[i].tx_next = &txp[(i + 1) & FXP_TXCB_MASK];
2132 	}
2133 	/*
2134 	 * Set the suspend flag on the first TxCB and start the control
2135 	 * unit. It will execute the NOP and then suspend.
2136 	 */
2137 	tcbp->cb_command = htole16(FXP_CB_COMMAND_NOP | FXP_CB_COMMAND_S);
2138 	bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE);
2139 	sc->fxp_desc.tx_first = sc->fxp_desc.tx_last = txp;
2140 	sc->tx_queued = 1;
2141 
2142 	fxp_scb_wait(sc);
2143 	fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START);
2144 
2145 	/*
2146 	 * Initialize receiver buffer area - RFA.
2147 	 */
2148 	fxp_scb_wait(sc);
2149 	CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->fxp_desc.rx_head->rx_addr);
2150 	fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_START);
2151 
2152 	/*
2153 	 * Set current media.
2154 	 */
2155 	if (sc->miibus != NULL)
2156 		mii_mediachg(device_get_softc(sc->miibus));
2157 
2158 	ifp->if_drv_flags |= IFF_DRV_RUNNING;
2159 	ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
2160 
2161 	/*
2162 	 * Enable interrupts.
2163 	 */
2164 #ifdef DEVICE_POLLING
2165 	/*
2166 	 * ... but only do that if we are not polling. And because (presumably)
2167 	 * the default is interrupts on, we need to disable them explicitly!
2168 	 */
2169 	if (ifp->if_capenable & IFCAP_POLLING )
2170 		CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE);
2171 	else
2172 #endif /* DEVICE_POLLING */
2173 	CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, 0);
2174 
2175 	/*
2176 	 * Start stats updater.
2177 	 */
2178 	callout_reset(&sc->stat_ch, hz, fxp_tick, sc);
2179 }
2180 
2181 static int
2182 fxp_serial_ifmedia_upd(struct ifnet *ifp)
2183 {
2184 
2185 	return (0);
2186 }
2187 
2188 static void
2189 fxp_serial_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
2190 {
2191 
2192 	ifmr->ifm_active = IFM_ETHER|IFM_MANUAL;
2193 }
2194 
2195 /*
2196  * Change media according to request.
2197  */
2198 static int
2199 fxp_ifmedia_upd(struct ifnet *ifp)
2200 {
2201 	struct fxp_softc *sc = ifp->if_softc;
2202 	struct mii_data *mii;
2203 
2204 	mii = device_get_softc(sc->miibus);
2205 	FXP_LOCK(sc);
2206 	if (mii->mii_instance) {
2207 		struct mii_softc	*miisc;
2208 		LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
2209 			mii_phy_reset(miisc);
2210 	}
2211 	mii_mediachg(mii);
2212 	FXP_UNLOCK(sc);
2213 	return (0);
2214 }
2215 
2216 /*
2217  * Notify the world which media we're using.
2218  */
2219 static void
2220 fxp_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
2221 {
2222 	struct fxp_softc *sc = ifp->if_softc;
2223 	struct mii_data *mii;
2224 
2225 	mii = device_get_softc(sc->miibus);
2226 	FXP_LOCK(sc);
2227 	mii_pollstat(mii);
2228 	ifmr->ifm_active = mii->mii_media_active;
2229 	ifmr->ifm_status = mii->mii_media_status;
2230 
2231 	if (IFM_SUBTYPE(ifmr->ifm_active) == IFM_10_T &&
2232 	    sc->flags & FXP_FLAG_CU_RESUME_BUG)
2233 		sc->cu_resume_bug = 1;
2234 	else
2235 		sc->cu_resume_bug = 0;
2236 	FXP_UNLOCK(sc);
2237 }
2238 
2239 /*
2240  * Add a buffer to the end of the RFA buffer list.
2241  * Return 0 if successful, 1 for failure. A failure results in
2242  * adding the 'oldm' (if non-NULL) on to the end of the list -
2243  * tossing out its old contents and recycling it.
2244  * The RFA struct is stuck at the beginning of mbuf cluster and the
2245  * data pointer is fixed up to point just past it.
2246  */
2247 static int
2248 fxp_add_rfabuf(struct fxp_softc *sc, struct fxp_rx *rxp)
2249 {
2250 	struct mbuf *m;
2251 	struct fxp_rfa *rfa, *p_rfa;
2252 	struct fxp_rx *p_rx;
2253 	bus_dmamap_t tmp_map;
2254 	int error;
2255 
2256 	m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR);
2257 	if (m == NULL)
2258 		return (ENOBUFS);
2259 
2260 	/*
2261 	 * Move the data pointer up so that the incoming data packet
2262 	 * will be 32-bit aligned.
2263 	 */
2264 	m->m_data += RFA_ALIGNMENT_FUDGE;
2265 
2266 	/*
2267 	 * Get a pointer to the base of the mbuf cluster and move
2268 	 * data start past it.
2269 	 */
2270 	rfa = mtod(m, struct fxp_rfa *);
2271 	m->m_data += sc->rfa_size;
2272 	rfa->size = htole16(MCLBYTES - sc->rfa_size - RFA_ALIGNMENT_FUDGE);
2273 
2274 	rfa->rfa_status = 0;
2275 	rfa->rfa_control = htole16(FXP_RFA_CONTROL_EL);
2276 	rfa->actual_size = 0;
2277 
2278 	/*
2279 	 * Initialize the rest of the RFA.  Note that since the RFA
2280 	 * is misaligned, we cannot store values directly.  We're thus
2281 	 * using the le32enc() function which handles endianness and
2282 	 * is also alignment-safe.
2283 	 */
2284 	le32enc(&rfa->link_addr, 0xffffffff);
2285 	le32enc(&rfa->rbd_addr, 0xffffffff);
2286 
2287 	/* Map the RFA into DMA memory. */
2288 	error = bus_dmamap_load(sc->fxp_mtag, sc->spare_map, rfa,
2289 	    MCLBYTES - RFA_ALIGNMENT_FUDGE, fxp_dma_map_addr,
2290 	    &rxp->rx_addr, 0);
2291 	if (error) {
2292 		m_freem(m);
2293 		return (error);
2294 	}
2295 
2296 	bus_dmamap_unload(sc->fxp_mtag, rxp->rx_map);
2297 	tmp_map = sc->spare_map;
2298 	sc->spare_map = rxp->rx_map;
2299 	rxp->rx_map = tmp_map;
2300 	rxp->rx_mbuf = m;
2301 
2302 	bus_dmamap_sync(sc->fxp_mtag, rxp->rx_map,
2303 	    BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2304 
2305 	/*
2306 	 * If there are other buffers already on the list, attach this
2307 	 * one to the end by fixing up the tail to point to this one.
2308 	 */
2309 	if (sc->fxp_desc.rx_head != NULL) {
2310 		p_rx = sc->fxp_desc.rx_tail;
2311 		p_rfa = (struct fxp_rfa *)
2312 		    (p_rx->rx_mbuf->m_ext.ext_buf + RFA_ALIGNMENT_FUDGE);
2313 		p_rx->rx_next = rxp;
2314 		le32enc(&p_rfa->link_addr, rxp->rx_addr);
2315 		p_rfa->rfa_control = 0;
2316 		bus_dmamap_sync(sc->fxp_mtag, p_rx->rx_map,
2317 		    BUS_DMASYNC_PREWRITE);
2318 	} else {
2319 		rxp->rx_next = NULL;
2320 		sc->fxp_desc.rx_head = rxp;
2321 	}
2322 	sc->fxp_desc.rx_tail = rxp;
2323 	return (0);
2324 }
2325 
2326 static int
2327 fxp_miibus_readreg(device_t dev, int phy, int reg)
2328 {
2329 	struct fxp_softc *sc = device_get_softc(dev);
2330 	int count = 10000;
2331 	int value;
2332 
2333 	CSR_WRITE_4(sc, FXP_CSR_MDICONTROL,
2334 	    (FXP_MDI_READ << 26) | (reg << 16) | (phy << 21));
2335 
2336 	while (((value = CSR_READ_4(sc, FXP_CSR_MDICONTROL)) & 0x10000000) == 0
2337 	    && count--)
2338 		DELAY(10);
2339 
2340 	if (count <= 0)
2341 		device_printf(dev, "fxp_miibus_readreg: timed out\n");
2342 
2343 	return (value & 0xffff);
2344 }
2345 
2346 static void
2347 fxp_miibus_writereg(device_t dev, int phy, int reg, int value)
2348 {
2349 	struct fxp_softc *sc = device_get_softc(dev);
2350 	int count = 10000;
2351 
2352 	CSR_WRITE_4(sc, FXP_CSR_MDICONTROL,
2353 	    (FXP_MDI_WRITE << 26) | (reg << 16) | (phy << 21) |
2354 	    (value & 0xffff));
2355 
2356 	while ((CSR_READ_4(sc, FXP_CSR_MDICONTROL) & 0x10000000) == 0 &&
2357 	    count--)
2358 		DELAY(10);
2359 
2360 	if (count <= 0)
2361 		device_printf(dev, "fxp_miibus_writereg: timed out\n");
2362 }
2363 
2364 static int
2365 fxp_ioctl(struct ifnet *ifp, u_long command, caddr_t data)
2366 {
2367 	struct fxp_softc *sc = ifp->if_softc;
2368 	struct ifreq *ifr = (struct ifreq *)data;
2369 	struct mii_data *mii;
2370 	int flag, mask, error = 0;
2371 
2372 	switch (command) {
2373 	case SIOCSIFFLAGS:
2374 		FXP_LOCK(sc);
2375 		if (ifp->if_flags & IFF_ALLMULTI)
2376 			sc->flags |= FXP_FLAG_ALL_MCAST;
2377 		else
2378 			sc->flags &= ~FXP_FLAG_ALL_MCAST;
2379 
2380 		/*
2381 		 * If interface is marked up and not running, then start it.
2382 		 * If it is marked down and running, stop it.
2383 		 * XXX If it's up then re-initialize it. This is so flags
2384 		 * such as IFF_PROMISC are handled.
2385 		 */
2386 		if (ifp->if_flags & IFF_UP) {
2387 			fxp_init_body(sc);
2388 		} else {
2389 			if (ifp->if_drv_flags & IFF_DRV_RUNNING)
2390 				fxp_stop(sc);
2391 		}
2392 		FXP_UNLOCK(sc);
2393 		break;
2394 
2395 	case SIOCADDMULTI:
2396 	case SIOCDELMULTI:
2397 		FXP_LOCK(sc);
2398 		if (ifp->if_flags & IFF_ALLMULTI)
2399 			sc->flags |= FXP_FLAG_ALL_MCAST;
2400 		else
2401 			sc->flags &= ~FXP_FLAG_ALL_MCAST;
2402 		/*
2403 		 * Multicast list has changed; set the hardware filter
2404 		 * accordingly.
2405 		 */
2406 		if ((sc->flags & FXP_FLAG_ALL_MCAST) == 0)
2407 			fxp_mc_setup(sc);
2408 		/*
2409 		 * fxp_mc_setup() can set FXP_FLAG_ALL_MCAST, so check it
2410 		 * again rather than else {}.
2411 		 */
2412 		if (sc->flags & FXP_FLAG_ALL_MCAST)
2413 			fxp_init_body(sc);
2414 		FXP_UNLOCK(sc);
2415 		error = 0;
2416 		break;
2417 
2418 	case SIOCSIFMEDIA:
2419 	case SIOCGIFMEDIA:
2420 		if (sc->miibus != NULL) {
2421 			mii = device_get_softc(sc->miibus);
2422                         error = ifmedia_ioctl(ifp, ifr,
2423                             &mii->mii_media, command);
2424 		} else {
2425                         error = ifmedia_ioctl(ifp, ifr, &sc->sc_media, command);
2426 		}
2427 		break;
2428 
2429 	case SIOCSIFCAP:
2430 		mask = ifp->if_capenable ^ ifr->ifr_reqcap;
2431 #ifdef DEVICE_POLLING
2432 		if (mask & IFCAP_POLLING) {
2433 			if (ifr->ifr_reqcap & IFCAP_POLLING) {
2434 				error = ether_poll_register(fxp_poll, ifp);
2435 				if (error)
2436 					return(error);
2437 				FXP_LOCK(sc);
2438 				CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL,
2439 				    FXP_SCB_INTR_DISABLE);
2440 				ifp->if_capenable |= IFCAP_POLLING;
2441 				FXP_UNLOCK(sc);
2442 			} else {
2443 				error = ether_poll_deregister(ifp);
2444 				/* Enable interrupts in any case */
2445 				FXP_LOCK(sc);
2446 				CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, 0);
2447 				ifp->if_capenable &= ~IFCAP_POLLING;
2448 				FXP_UNLOCK(sc);
2449 			}
2450 		}
2451 #endif
2452 		if (mask & IFCAP_VLAN_MTU) {
2453 			FXP_LOCK(sc);
2454 			ifp->if_capenable ^= IFCAP_VLAN_MTU;
2455 			if (sc->revision != FXP_REV_82557)
2456 				flag = FXP_FLAG_LONG_PKT_EN;
2457 			else /* a hack to get long frames on the old chip */
2458 				flag = FXP_FLAG_SAVE_BAD;
2459 			sc->flags ^= flag;
2460 			if (ifp->if_flags & IFF_UP)
2461 				fxp_init_body(sc);
2462 			FXP_UNLOCK(sc);
2463 		}
2464 		break;
2465 
2466 	default:
2467 		error = ether_ioctl(ifp, command, data);
2468 	}
2469 	return (error);
2470 }
2471 
2472 /*
2473  * Fill in the multicast address list and return number of entries.
2474  */
2475 static int
2476 fxp_mc_addrs(struct fxp_softc *sc)
2477 {
2478 	struct fxp_cb_mcs *mcsp = sc->mcsp;
2479 	struct ifnet *ifp = sc->ifp;
2480 	struct ifmultiaddr *ifma;
2481 	int nmcasts;
2482 
2483 	nmcasts = 0;
2484 	if ((sc->flags & FXP_FLAG_ALL_MCAST) == 0) {
2485 		IF_ADDR_LOCK(ifp);
2486 		TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
2487 			if (ifma->ifma_addr->sa_family != AF_LINK)
2488 				continue;
2489 			if (nmcasts >= MAXMCADDR) {
2490 				sc->flags |= FXP_FLAG_ALL_MCAST;
2491 				nmcasts = 0;
2492 				break;
2493 			}
2494 			bcopy(LLADDR((struct sockaddr_dl *)ifma->ifma_addr),
2495 			    &sc->mcsp->mc_addr[nmcasts][0], ETHER_ADDR_LEN);
2496 			nmcasts++;
2497 		}
2498 		IF_ADDR_UNLOCK(ifp);
2499 	}
2500 	mcsp->mc_cnt = htole16(nmcasts * ETHER_ADDR_LEN);
2501 	return (nmcasts);
2502 }
2503 
2504 /*
2505  * Program the multicast filter.
2506  *
2507  * We have an artificial restriction that the multicast setup command
2508  * must be the first command in the chain, so we take steps to ensure
2509  * this. By requiring this, it allows us to keep up the performance of
2510  * the pre-initialized command ring (esp. link pointers) by not actually
2511  * inserting the mcsetup command in the ring - i.e. its link pointer
2512  * points to the TxCB ring, but the mcsetup descriptor itself is not part
2513  * of it. We then can do 'CU_START' on the mcsetup descriptor and have it
2514  * lead into the regular TxCB ring when it completes.
2515  *
2516  * This function must be called at splimp.
2517  */
2518 static void
2519 fxp_mc_setup(struct fxp_softc *sc)
2520 {
2521 	struct fxp_cb_mcs *mcsp = sc->mcsp;
2522 	struct fxp_tx *txp;
2523 	int count;
2524 
2525 	FXP_LOCK_ASSERT(sc, MA_OWNED);
2526 	/*
2527 	 * If there are queued commands, we must wait until they are all
2528 	 * completed. If we are already waiting, then add a NOP command
2529 	 * with interrupt option so that we're notified when all commands
2530 	 * have been completed - fxp_start() ensures that no additional
2531 	 * TX commands will be added when need_mcsetup is true.
2532 	 */
2533 	if (sc->tx_queued) {
2534 		/*
2535 		 * need_mcsetup will be true if we are already waiting for the
2536 		 * NOP command to be completed (see below). In this case, bail.
2537 		 */
2538 		if (sc->need_mcsetup)
2539 			return;
2540 		sc->need_mcsetup = 1;
2541 
2542 		/*
2543 		 * Add a NOP command with interrupt so that we are notified
2544 		 * when all TX commands have been processed.
2545 		 */
2546 		txp = sc->fxp_desc.tx_last->tx_next;
2547 		txp->tx_mbuf = NULL;
2548 		txp->tx_cb->cb_status = 0;
2549 		txp->tx_cb->cb_command = htole16(FXP_CB_COMMAND_NOP |
2550 		    FXP_CB_COMMAND_S | FXP_CB_COMMAND_I);
2551 		/*
2552 		 * Advance the end of list forward.
2553 		 */
2554 		sc->fxp_desc.tx_last->tx_cb->cb_command &=
2555 		    htole16(~FXP_CB_COMMAND_S);
2556 		bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE);
2557 		sc->fxp_desc.tx_last = txp;
2558 		sc->tx_queued++;
2559 		/*
2560 		 * Issue a resume in case the CU has just suspended.
2561 		 */
2562 		fxp_scb_wait(sc);
2563 		fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_RESUME);
2564 		/*
2565 		 * Set a 5 second timer just in case we don't hear from the
2566 		 * card again.
2567 		 */
2568 		sc->watchdog_timer = 5;
2569 
2570 		return;
2571 	}
2572 	sc->need_mcsetup = 0;
2573 
2574 	/*
2575 	 * Initialize multicast setup descriptor.
2576 	 */
2577 	mcsp->cb_status = 0;
2578 	mcsp->cb_command = htole16(FXP_CB_COMMAND_MCAS |
2579 	    FXP_CB_COMMAND_S | FXP_CB_COMMAND_I);
2580 	mcsp->link_addr = htole32(sc->fxp_desc.cbl_addr);
2581 	txp = &sc->fxp_desc.mcs_tx;
2582 	txp->tx_mbuf = NULL;
2583 	txp->tx_cb = (struct fxp_cb_tx *)sc->mcsp;
2584 	txp->tx_next = sc->fxp_desc.tx_list;
2585 	(void) fxp_mc_addrs(sc);
2586 	sc->fxp_desc.tx_first = sc->fxp_desc.tx_last = txp;
2587 	sc->tx_queued = 1;
2588 
2589 	/*
2590 	 * Wait until command unit is not active. This should never
2591 	 * be the case when nothing is queued, but make sure anyway.
2592 	 */
2593 	count = 100;
2594 	while ((CSR_READ_1(sc, FXP_CSR_SCB_RUSCUS) >> 6) ==
2595 	    FXP_SCB_CUS_ACTIVE && --count)
2596 		DELAY(10);
2597 	if (count == 0) {
2598 		device_printf(sc->dev, "command queue timeout\n");
2599 		return;
2600 	}
2601 
2602 	/*
2603 	 * Start the multicast setup command.
2604 	 */
2605 	fxp_scb_wait(sc);
2606 	bus_dmamap_sync(sc->mcs_tag, sc->mcs_map, BUS_DMASYNC_PREWRITE);
2607 	CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->mcs_addr);
2608 	fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START);
2609 
2610 	sc->watchdog_timer = 2;
2611 	return;
2612 }
2613 
2614 static uint32_t fxp_ucode_d101a[] = D101_A_RCVBUNDLE_UCODE;
2615 static uint32_t fxp_ucode_d101b0[] = D101_B0_RCVBUNDLE_UCODE;
2616 static uint32_t fxp_ucode_d101ma[] = D101M_B_RCVBUNDLE_UCODE;
2617 static uint32_t fxp_ucode_d101s[] = D101S_RCVBUNDLE_UCODE;
2618 static uint32_t fxp_ucode_d102[] = D102_B_RCVBUNDLE_UCODE;
2619 static uint32_t fxp_ucode_d102c[] = D102_C_RCVBUNDLE_UCODE;
2620 static uint32_t fxp_ucode_d102e[] = D102_E_RCVBUNDLE_UCODE;
2621 
2622 #define UCODE(x)	x, sizeof(x)/sizeof(uint32_t)
2623 
2624 struct ucode {
2625 	uint32_t	revision;
2626 	uint32_t	*ucode;
2627 	int		length;
2628 	u_short		int_delay_offset;
2629 	u_short		bundle_max_offset;
2630 } ucode_table[] = {
2631 	{ FXP_REV_82558_A4, UCODE(fxp_ucode_d101a), D101_CPUSAVER_DWORD, 0 },
2632 	{ FXP_REV_82558_B0, UCODE(fxp_ucode_d101b0), D101_CPUSAVER_DWORD, 0 },
2633 	{ FXP_REV_82559_A0, UCODE(fxp_ucode_d101ma),
2634 	    D101M_CPUSAVER_DWORD, D101M_CPUSAVER_BUNDLE_MAX_DWORD },
2635 	{ FXP_REV_82559S_A, UCODE(fxp_ucode_d101s),
2636 	    D101S_CPUSAVER_DWORD, D101S_CPUSAVER_BUNDLE_MAX_DWORD },
2637 	{ FXP_REV_82550, UCODE(fxp_ucode_d102),
2638 	    D102_B_CPUSAVER_DWORD, D102_B_CPUSAVER_BUNDLE_MAX_DWORD },
2639 	{ FXP_REV_82550_C, UCODE(fxp_ucode_d102c),
2640 	    D102_C_CPUSAVER_DWORD, D102_C_CPUSAVER_BUNDLE_MAX_DWORD },
2641 	{ FXP_REV_82551_F, UCODE(fxp_ucode_d102e),
2642 	    D102_E_CPUSAVER_DWORD, D102_E_CPUSAVER_BUNDLE_MAX_DWORD },
2643 	{ 0, NULL, 0, 0, 0 }
2644 };
2645 
2646 static void
2647 fxp_load_ucode(struct fxp_softc *sc)
2648 {
2649 	struct ucode *uc;
2650 	struct fxp_cb_ucode *cbp;
2651 	int i;
2652 
2653 	for (uc = ucode_table; uc->ucode != NULL; uc++)
2654 		if (sc->revision == uc->revision)
2655 			break;
2656 	if (uc->ucode == NULL)
2657 		return;
2658 	cbp = (struct fxp_cb_ucode *)sc->fxp_desc.cbl_list;
2659 	cbp->cb_status = 0;
2660 	cbp->cb_command = htole16(FXP_CB_COMMAND_UCODE | FXP_CB_COMMAND_EL);
2661 	cbp->link_addr = 0xffffffff;    	/* (no) next command */
2662 	for (i = 0; i < uc->length; i++)
2663 		cbp->ucode[i] = htole32(uc->ucode[i]);
2664 	if (uc->int_delay_offset)
2665 		*(uint16_t *)&cbp->ucode[uc->int_delay_offset] =
2666 		    htole16(sc->tunable_int_delay + sc->tunable_int_delay / 2);
2667 	if (uc->bundle_max_offset)
2668 		*(uint16_t *)&cbp->ucode[uc->bundle_max_offset] =
2669 		    htole16(sc->tunable_bundle_max);
2670 	/*
2671 	 * Download the ucode to the chip.
2672 	 */
2673 	fxp_scb_wait(sc);
2674 	bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE);
2675 	CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->fxp_desc.cbl_addr);
2676 	fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START);
2677 	/* ...and wait for it to complete. */
2678 	fxp_dma_wait(sc, &cbp->cb_status, sc->cbl_tag, sc->cbl_map);
2679 	bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_POSTWRITE);
2680 	device_printf(sc->dev,
2681 	    "Microcode loaded, int_delay: %d usec  bundle_max: %d\n",
2682 	    sc->tunable_int_delay,
2683 	    uc->bundle_max_offset == 0 ? 0 : sc->tunable_bundle_max);
2684 	sc->flags |= FXP_FLAG_UCODE;
2685 }
2686 
2687 static int
2688 sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high)
2689 {
2690 	int error, value;
2691 
2692 	value = *(int *)arg1;
2693 	error = sysctl_handle_int(oidp, &value, 0, req);
2694 	if (error || !req->newptr)
2695 		return (error);
2696 	if (value < low || value > high)
2697 		return (EINVAL);
2698 	*(int *)arg1 = value;
2699 	return (0);
2700 }
2701 
2702 /*
2703  * Interrupt delay is expressed in microseconds, a multiplier is used
2704  * to convert this to the appropriate clock ticks before using.
2705  */
2706 static int
2707 sysctl_hw_fxp_int_delay(SYSCTL_HANDLER_ARGS)
2708 {
2709 	return (sysctl_int_range(oidp, arg1, arg2, req, 300, 3000));
2710 }
2711 
2712 static int
2713 sysctl_hw_fxp_bundle_max(SYSCTL_HANDLER_ARGS)
2714 {
2715 	return (sysctl_int_range(oidp, arg1, arg2, req, 1, 0xffff));
2716 }
2717