1 /*- 2 * Copyright (c) 1995, David Greenman 3 * Copyright (c) 2001 Jonathan Lemon <jlemon@freebsd.org> 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice unmodified, this list of conditions, and the following 11 * disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 * 28 */ 29 30 #include <sys/cdefs.h> 31 __FBSDID("$FreeBSD$"); 32 33 /* 34 * Intel EtherExpress Pro/100B PCI Fast Ethernet driver 35 */ 36 37 #include <sys/cdefs.h> 38 __FBSDID("$FreeBSD$"); 39 40 #include <sys/param.h> 41 #include <sys/systm.h> 42 #include <sys/endian.h> 43 #include <sys/mbuf.h> 44 /* #include <sys/mutex.h> */ 45 #include <sys/kernel.h> 46 #include <sys/socket.h> 47 #include <sys/sysctl.h> 48 49 #include <net/if.h> 50 #include <net/if_dl.h> 51 #include <net/if_media.h> 52 53 #include <net/bpf.h> 54 #include <sys/sockio.h> 55 #include <sys/bus.h> 56 #include <machine/bus.h> 57 #include <sys/rman.h> 58 #include <machine/resource.h> 59 60 #include <net/ethernet.h> 61 #include <net/if_arp.h> 62 63 #include <machine/clock.h> /* for DELAY */ 64 65 #include <net/if_types.h> 66 #include <net/if_vlan_var.h> 67 68 #ifdef FXP_IP_CSUM_WAR 69 #include <netinet/in.h> 70 #include <netinet/in_systm.h> 71 #include <netinet/ip.h> 72 #include <machine/in_cksum.h> 73 #endif 74 75 #include <dev/pci/pcivar.h> 76 #include <dev/pci/pcireg.h> /* for PCIM_CMD_xxx */ 77 78 #include <dev/mii/mii.h> 79 #include <dev/mii/miivar.h> 80 81 #include <dev/fxp/if_fxpreg.h> 82 #include <dev/fxp/if_fxpvar.h> 83 #include <dev/fxp/rcvbundl.h> 84 85 MODULE_DEPEND(fxp, pci, 1, 1, 1); 86 MODULE_DEPEND(fxp, ether, 1, 1, 1); 87 MODULE_DEPEND(fxp, miibus, 1, 1, 1); 88 #include "miibus_if.h" 89 90 /* 91 * NOTE! On the Alpha, we have an alignment constraint. The 92 * card DMAs the packet immediately following the RFA. However, 93 * the first thing in the packet is a 14-byte Ethernet header. 94 * This means that the packet is misaligned. To compensate, 95 * we actually offset the RFA 2 bytes into the cluster. This 96 * alignes the packet after the Ethernet header at a 32-bit 97 * boundary. HOWEVER! This means that the RFA is misaligned! 98 */ 99 #define RFA_ALIGNMENT_FUDGE 2 100 101 /* 102 * Set initial transmit threshold at 64 (512 bytes). This is 103 * increased by 64 (512 bytes) at a time, to maximum of 192 104 * (1536 bytes), if an underrun occurs. 105 */ 106 static int tx_threshold = 64; 107 108 /* 109 * The configuration byte map has several undefined fields which 110 * must be one or must be zero. Set up a template for these bits 111 * only, (assuming a 82557 chip) leaving the actual configuration 112 * to fxp_init. 113 * 114 * See struct fxp_cb_config for the bit definitions. 115 */ 116 static u_char fxp_cb_config_template[] = { 117 0x0, 0x0, /* cb_status */ 118 0x0, 0x0, /* cb_command */ 119 0x0, 0x0, 0x0, 0x0, /* link_addr */ 120 0x0, /* 0 */ 121 0x0, /* 1 */ 122 0x0, /* 2 */ 123 0x0, /* 3 */ 124 0x0, /* 4 */ 125 0x0, /* 5 */ 126 0x32, /* 6 */ 127 0x0, /* 7 */ 128 0x0, /* 8 */ 129 0x0, /* 9 */ 130 0x6, /* 10 */ 131 0x0, /* 11 */ 132 0x0, /* 12 */ 133 0x0, /* 13 */ 134 0xf2, /* 14 */ 135 0x48, /* 15 */ 136 0x0, /* 16 */ 137 0x40, /* 17 */ 138 0xf0, /* 18 */ 139 0x0, /* 19 */ 140 0x3f, /* 20 */ 141 0x5 /* 21 */ 142 }; 143 144 struct fxp_ident { 145 u_int16_t devid; 146 int16_t revid; /* -1 matches anything */ 147 char *name; 148 }; 149 150 /* 151 * Claim various Intel PCI device identifiers for this driver. The 152 * sub-vendor and sub-device field are extensively used to identify 153 * particular variants, but we don't currently differentiate between 154 * them. 155 */ 156 static struct fxp_ident fxp_ident_table[] = { 157 { 0x1029, -1, "Intel 82559 PCI/CardBus Pro/100" }, 158 { 0x1030, -1, "Intel 82559 Pro/100 Ethernet" }, 159 { 0x1031, -1, "Intel 82801CAM (ICH3) Pro/100 VE Ethernet" }, 160 { 0x1032, -1, "Intel 82801CAM (ICH3) Pro/100 VE Ethernet" }, 161 { 0x1033, -1, "Intel 82801CAM (ICH3) Pro/100 VM Ethernet" }, 162 { 0x1034, -1, "Intel 82801CAM (ICH3) Pro/100 VM Ethernet" }, 163 { 0x1035, -1, "Intel 82801CAM (ICH3) Pro/100 Ethernet" }, 164 { 0x1036, -1, "Intel 82801CAM (ICH3) Pro/100 Ethernet" }, 165 { 0x1037, -1, "Intel 82801CAM (ICH3) Pro/100 Ethernet" }, 166 { 0x1038, -1, "Intel 82801CAM (ICH3) Pro/100 VM Ethernet" }, 167 { 0x1039, -1, "Intel 82801DB (ICH4) Pro/100 VE Ethernet" }, 168 { 0x103A, -1, "Intel 82801DB (ICH4) Pro/100 Ethernet" }, 169 { 0x103B, -1, "Intel 82801DB (ICH4) Pro/100 VM Ethernet" }, 170 { 0x103C, -1, "Intel 82801DB (ICH4) Pro/100 Ethernet" }, 171 { 0x103D, -1, "Intel 82801DB (ICH4) Pro/100 VE Ethernet" }, 172 { 0x103E, -1, "Intel 82801DB (ICH4) Pro/100 VM Ethernet" }, 173 { 0x1050, -1, "Intel 82801BA (D865) Pro/100 VE Ethernet" }, 174 { 0x1059, -1, "Intel 82551QM Pro/100 M Mobile Connection" }, 175 { 0x1209, -1, "Intel 82559ER Embedded 10/100 Ethernet" }, 176 { 0x1229, 0x01, "Intel 82557 Pro/100 Ethernet" }, 177 { 0x1229, 0x02, "Intel 82557 Pro/100 Ethernet" }, 178 { 0x1229, 0x03, "Intel 82557 Pro/100 Ethernet" }, 179 { 0x1229, 0x04, "Intel 82558 Pro/100 Ethernet" }, 180 { 0x1229, 0x05, "Intel 82558 Pro/100 Ethernet" }, 181 { 0x1229, 0x06, "Intel 82559 Pro/100 Ethernet" }, 182 { 0x1229, 0x07, "Intel 82559 Pro/100 Ethernet" }, 183 { 0x1229, 0x08, "Intel 82559 Pro/100 Ethernet" }, 184 { 0x1229, 0x09, "Intel 82559ER Pro/100 Ethernet" }, 185 { 0x1229, 0x0c, "Intel 82550 Pro/100 Ethernet" }, 186 { 0x1229, 0x0d, "Intel 82550 Pro/100 Ethernet" }, 187 { 0x1229, 0x0e, "Intel 82550 Pro/100 Ethernet" }, 188 { 0x1229, 0x0f, "Intel 82551 Pro/100 Ethernet" }, 189 { 0x1229, 0x10, "Intel 82551 Pro/100 Ethernet" }, 190 { 0x1229, -1, "Intel 82557/8/9 Pro/100 Ethernet" }, 191 { 0x2449, -1, "Intel 82801BA/CAM (ICH2/3) Pro/100 Ethernet" }, 192 { 0, -1, NULL }, 193 }; 194 195 #ifdef FXP_IP_CSUM_WAR 196 #define FXP_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 197 #else 198 #define FXP_CSUM_FEATURES (CSUM_TCP | CSUM_UDP) 199 #endif 200 201 static int fxp_probe(device_t dev); 202 static int fxp_attach(device_t dev); 203 static int fxp_detach(device_t dev); 204 static int fxp_shutdown(device_t dev); 205 static int fxp_suspend(device_t dev); 206 static int fxp_resume(device_t dev); 207 208 static void fxp_intr(void *xsc); 209 static void fxp_intr_body(struct fxp_softc *sc, struct ifnet *ifp, 210 u_int8_t statack, int count); 211 static void fxp_init(void *xsc); 212 static void fxp_init_body(struct fxp_softc *sc); 213 static void fxp_tick(void *xsc); 214 #ifndef BURN_BRIDGES 215 static void fxp_powerstate_d0(device_t dev); 216 #endif 217 static void fxp_start(struct ifnet *ifp); 218 static void fxp_start_body(struct ifnet *ifp); 219 static void fxp_stop(struct fxp_softc *sc); 220 static void fxp_release(struct fxp_softc *sc); 221 static int fxp_ioctl(struct ifnet *ifp, u_long command, 222 caddr_t data); 223 static void fxp_watchdog(struct ifnet *ifp); 224 static int fxp_add_rfabuf(struct fxp_softc *sc, 225 struct fxp_rx *rxp); 226 static int fxp_mc_addrs(struct fxp_softc *sc); 227 static void fxp_mc_setup(struct fxp_softc *sc); 228 static u_int16_t fxp_eeprom_getword(struct fxp_softc *sc, int offset, 229 int autosize); 230 static void fxp_eeprom_putword(struct fxp_softc *sc, int offset, 231 u_int16_t data); 232 static void fxp_autosize_eeprom(struct fxp_softc *sc); 233 static void fxp_read_eeprom(struct fxp_softc *sc, u_short *data, 234 int offset, int words); 235 static void fxp_write_eeprom(struct fxp_softc *sc, u_short *data, 236 int offset, int words); 237 static int fxp_ifmedia_upd(struct ifnet *ifp); 238 static void fxp_ifmedia_sts(struct ifnet *ifp, 239 struct ifmediareq *ifmr); 240 static int fxp_serial_ifmedia_upd(struct ifnet *ifp); 241 static void fxp_serial_ifmedia_sts(struct ifnet *ifp, 242 struct ifmediareq *ifmr); 243 static volatile int fxp_miibus_readreg(device_t dev, int phy, int reg); 244 static void fxp_miibus_writereg(device_t dev, int phy, int reg, 245 int value); 246 static void fxp_load_ucode(struct fxp_softc *sc); 247 static int sysctl_int_range(SYSCTL_HANDLER_ARGS, 248 int low, int high); 249 static int sysctl_hw_fxp_bundle_max(SYSCTL_HANDLER_ARGS); 250 static int sysctl_hw_fxp_int_delay(SYSCTL_HANDLER_ARGS); 251 static void fxp_scb_wait(struct fxp_softc *sc); 252 static void fxp_scb_cmd(struct fxp_softc *sc, int cmd); 253 static void fxp_dma_wait(struct fxp_softc *sc, 254 volatile u_int16_t *status, bus_dma_tag_t dmat, 255 bus_dmamap_t map); 256 257 static device_method_t fxp_methods[] = { 258 /* Device interface */ 259 DEVMETHOD(device_probe, fxp_probe), 260 DEVMETHOD(device_attach, fxp_attach), 261 DEVMETHOD(device_detach, fxp_detach), 262 DEVMETHOD(device_shutdown, fxp_shutdown), 263 DEVMETHOD(device_suspend, fxp_suspend), 264 DEVMETHOD(device_resume, fxp_resume), 265 266 /* MII interface */ 267 DEVMETHOD(miibus_readreg, fxp_miibus_readreg), 268 DEVMETHOD(miibus_writereg, fxp_miibus_writereg), 269 270 { 0, 0 } 271 }; 272 273 static driver_t fxp_driver = { 274 "fxp", 275 fxp_methods, 276 sizeof(struct fxp_softc), 277 }; 278 279 static devclass_t fxp_devclass; 280 281 DRIVER_MODULE(fxp, pci, fxp_driver, fxp_devclass, 0, 0); 282 DRIVER_MODULE(fxp, cardbus, fxp_driver, fxp_devclass, 0, 0); 283 DRIVER_MODULE(miibus, fxp, miibus_driver, miibus_devclass, 0, 0); 284 285 static int fxp_rnr; 286 SYSCTL_INT(_hw, OID_AUTO, fxp_rnr, CTLFLAG_RW, &fxp_rnr, 0, "fxp rnr events"); 287 288 static int fxp_noflow; 289 SYSCTL_INT(_hw, OID_AUTO, fxp_noflow, CTLFLAG_RW, &fxp_noflow, 0, "fxp flow control disabled"); 290 TUNABLE_INT("hw.fxp_noflow", &fxp_noflow); 291 292 /* 293 * Wait for the previous command to be accepted (but not necessarily 294 * completed). 295 */ 296 static void 297 fxp_scb_wait(struct fxp_softc *sc) 298 { 299 int i = 10000; 300 301 while (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) && --i) 302 DELAY(2); 303 if (i == 0) 304 device_printf(sc->dev, "SCB timeout: 0x%x 0x%x 0x%x 0x%x\n", 305 CSR_READ_1(sc, FXP_CSR_SCB_COMMAND), 306 CSR_READ_1(sc, FXP_CSR_SCB_STATACK), 307 CSR_READ_1(sc, FXP_CSR_SCB_RUSCUS), 308 CSR_READ_2(sc, FXP_CSR_FLOWCONTROL)); 309 } 310 311 static void 312 fxp_scb_cmd(struct fxp_softc *sc, int cmd) 313 { 314 315 if (cmd == FXP_SCB_COMMAND_CU_RESUME && sc->cu_resume_bug) { 316 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_CB_COMMAND_NOP); 317 fxp_scb_wait(sc); 318 } 319 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, cmd); 320 } 321 322 static void 323 fxp_dma_wait(struct fxp_softc *sc, volatile u_int16_t *status, 324 bus_dma_tag_t dmat, bus_dmamap_t map) 325 { 326 int i = 10000; 327 328 bus_dmamap_sync(dmat, map, BUS_DMASYNC_POSTREAD); 329 while (!(le16toh(*status) & FXP_CB_STATUS_C) && --i) { 330 DELAY(2); 331 bus_dmamap_sync(dmat, map, BUS_DMASYNC_POSTREAD); 332 } 333 if (i == 0) 334 device_printf(sc->dev, "DMA timeout\n"); 335 } 336 337 /* 338 * Return identification string if this device is ours. 339 */ 340 static int 341 fxp_probe(device_t dev) 342 { 343 u_int16_t devid; 344 u_int8_t revid; 345 struct fxp_ident *ident; 346 347 if (pci_get_vendor(dev) == FXP_VENDORID_INTEL) { 348 devid = pci_get_device(dev); 349 revid = pci_get_revid(dev); 350 for (ident = fxp_ident_table; ident->name != NULL; ident++) { 351 if (ident->devid == devid && 352 (ident->revid == revid || ident->revid == -1)) { 353 device_set_desc(dev, ident->name); 354 return (0); 355 } 356 } 357 } 358 return (ENXIO); 359 } 360 361 #ifndef BURN_BRIDGES 362 static void 363 fxp_powerstate_d0(device_t dev) 364 { 365 #if __FreeBSD_version >= 430002 366 u_int32_t iobase, membase, irq; 367 368 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 369 /* Save important PCI config data. */ 370 iobase = pci_read_config(dev, FXP_PCI_IOBA, 4); 371 membase = pci_read_config(dev, FXP_PCI_MMBA, 4); 372 irq = pci_read_config(dev, PCIR_INTLINE, 4); 373 374 /* Reset the power state. */ 375 device_printf(dev, "chip is in D%d power mode " 376 "-- setting to D0\n", pci_get_powerstate(dev)); 377 378 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 379 380 /* Restore PCI config data. */ 381 pci_write_config(dev, FXP_PCI_IOBA, iobase, 4); 382 pci_write_config(dev, FXP_PCI_MMBA, membase, 4); 383 pci_write_config(dev, PCIR_INTLINE, irq, 4); 384 } 385 #endif 386 } 387 #endif 388 389 static void 390 fxp_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error) 391 { 392 u_int32_t *addr; 393 394 if (error) 395 return; 396 397 KASSERT(nseg == 1, ("too many DMA segments, %d should be 1", nseg)); 398 addr = arg; 399 *addr = segs->ds_addr; 400 } 401 402 static int 403 fxp_attach(device_t dev) 404 { 405 int error = 0; 406 struct fxp_softc *sc = device_get_softc(dev); 407 struct ifnet *ifp; 408 struct fxp_rx *rxp; 409 u_int32_t val; 410 u_int16_t data, myea[ETHER_ADDR_LEN / 2]; 411 int i, rid, m1, m2, prefer_iomap, maxtxseg; 412 int s, ipcbxmit_disable; 413 414 sc->dev = dev; 415 callout_init(&sc->stat_ch, CALLOUT_MPSAFE); 416 sysctl_ctx_init(&sc->sysctl_ctx); 417 mtx_init(&sc->sc_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 418 MTX_DEF); 419 ifmedia_init(&sc->sc_media, 0, fxp_serial_ifmedia_upd, 420 fxp_serial_ifmedia_sts); 421 422 s = splimp(); 423 424 /* 425 * Enable bus mastering. 426 */ 427 pci_enable_busmaster(dev); 428 val = pci_read_config(dev, PCIR_COMMAND, 2); 429 #ifndef BURN_BRIDGES 430 fxp_powerstate_d0(dev); 431 #endif 432 /* 433 * Figure out which we should try first - memory mapping or i/o mapping? 434 * We default to memory mapping. Then we accept an override from the 435 * command line. Then we check to see which one is enabled. 436 */ 437 m1 = PCIM_CMD_MEMEN; 438 m2 = PCIM_CMD_PORTEN; 439 prefer_iomap = 0; 440 if (resource_int_value(device_get_name(dev), device_get_unit(dev), 441 "prefer_iomap", &prefer_iomap) == 0 && prefer_iomap != 0) { 442 m1 = PCIM_CMD_PORTEN; 443 m2 = PCIM_CMD_MEMEN; 444 } 445 446 sc->rtp = (m1 == PCIM_CMD_MEMEN)? SYS_RES_MEMORY : SYS_RES_IOPORT; 447 sc->rgd = (m1 == PCIM_CMD_MEMEN)? FXP_PCI_MMBA : FXP_PCI_IOBA; 448 sc->mem = bus_alloc_resource(dev, sc->rtp, &sc->rgd, 449 0, ~0, 1, RF_ACTIVE); 450 if (sc->mem == NULL) { 451 sc->rtp = 452 (m2 == PCIM_CMD_MEMEN)? SYS_RES_MEMORY : SYS_RES_IOPORT; 453 sc->rgd = (m2 == PCIM_CMD_MEMEN)? FXP_PCI_MMBA : FXP_PCI_IOBA; 454 sc->mem = bus_alloc_resource(dev, sc->rtp, &sc->rgd, 455 0, ~0, 1, RF_ACTIVE); 456 } 457 458 if (!sc->mem) { 459 error = ENXIO; 460 goto fail; 461 } 462 if (bootverbose) { 463 device_printf(dev, "using %s space register mapping\n", 464 sc->rtp == SYS_RES_MEMORY? "memory" : "I/O"); 465 } 466 467 sc->sc_st = rman_get_bustag(sc->mem); 468 sc->sc_sh = rman_get_bushandle(sc->mem); 469 470 /* 471 * Allocate our interrupt. 472 */ 473 rid = 0; 474 sc->irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 475 RF_SHAREABLE | RF_ACTIVE); 476 if (sc->irq == NULL) { 477 device_printf(dev, "could not map interrupt\n"); 478 error = ENXIO; 479 goto fail; 480 } 481 482 /* 483 * Reset to a stable state. 484 */ 485 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET); 486 DELAY(10); 487 488 /* 489 * Find out how large of an SEEPROM we have. 490 */ 491 fxp_autosize_eeprom(sc); 492 493 /* 494 * Determine whether we must use the 503 serial interface. 495 */ 496 fxp_read_eeprom(sc, &data, 6, 1); 497 if ((data & FXP_PHY_DEVICE_MASK) != 0 && 498 (data & FXP_PHY_SERIAL_ONLY)) 499 sc->flags |= FXP_FLAG_SERIAL_MEDIA; 500 501 /* 502 * Create the sysctl tree 503 */ 504 sc->sysctl_tree = SYSCTL_ADD_NODE(&sc->sysctl_ctx, 505 SYSCTL_STATIC_CHILDREN(_hw), OID_AUTO, 506 device_get_nameunit(dev), CTLFLAG_RD, 0, ""); 507 if (sc->sysctl_tree == NULL) { 508 error = ENXIO; 509 goto fail; 510 } 511 SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree), 512 OID_AUTO, "int_delay", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_PRISON, 513 &sc->tunable_int_delay, 0, sysctl_hw_fxp_int_delay, "I", 514 "FXP driver receive interrupt microcode bundling delay"); 515 SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree), 516 OID_AUTO, "bundle_max", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_PRISON, 517 &sc->tunable_bundle_max, 0, sysctl_hw_fxp_bundle_max, "I", 518 "FXP driver receive interrupt microcode bundle size limit"); 519 520 /* 521 * Pull in device tunables. 522 */ 523 sc->tunable_int_delay = TUNABLE_INT_DELAY; 524 sc->tunable_bundle_max = TUNABLE_BUNDLE_MAX; 525 (void) resource_int_value(device_get_name(dev), device_get_unit(dev), 526 "int_delay", &sc->tunable_int_delay); 527 (void) resource_int_value(device_get_name(dev), device_get_unit(dev), 528 "bundle_max", &sc->tunable_bundle_max); 529 530 /* 531 * Find out the chip revision; lump all 82557 revs together. 532 */ 533 fxp_read_eeprom(sc, &data, 5, 1); 534 if ((data >> 8) == 1) 535 sc->revision = FXP_REV_82557; 536 else 537 sc->revision = pci_get_revid(dev); 538 539 /* 540 * Enable workarounds for certain chip revision deficiencies. 541 * 542 * Systems based on the ICH2/ICH2-M chip from Intel, and possibly 543 * some systems based a normal 82559 design, have a defect where 544 * the chip can cause a PCI protocol violation if it receives 545 * a CU_RESUME command when it is entering the IDLE state. The 546 * workaround is to disable Dynamic Standby Mode, so the chip never 547 * deasserts CLKRUN#, and always remains in an active state. 548 * 549 * See Intel 82801BA/82801BAM Specification Update, Errata #30. 550 */ 551 i = pci_get_device(dev); 552 if (i == 0x2449 || (i > 0x1030 && i < 0x1039) || 553 sc->revision >= FXP_REV_82559_A0) { 554 fxp_read_eeprom(sc, &data, 10, 1); 555 if (data & 0x02) { /* STB enable */ 556 u_int16_t cksum; 557 int i; 558 559 device_printf(dev, 560 "Disabling dynamic standby mode in EEPROM\n"); 561 data &= ~0x02; 562 fxp_write_eeprom(sc, &data, 10, 1); 563 device_printf(dev, "New EEPROM ID: 0x%x\n", data); 564 cksum = 0; 565 for (i = 0; i < (1 << sc->eeprom_size) - 1; i++) { 566 fxp_read_eeprom(sc, &data, i, 1); 567 cksum += data; 568 } 569 i = (1 << sc->eeprom_size) - 1; 570 cksum = 0xBABA - cksum; 571 fxp_read_eeprom(sc, &data, i, 1); 572 fxp_write_eeprom(sc, &cksum, i, 1); 573 device_printf(dev, 574 "EEPROM checksum @ 0x%x: 0x%x -> 0x%x\n", 575 i, data, cksum); 576 #if 1 577 /* 578 * If the user elects to continue, try the software 579 * workaround, as it is better than nothing. 580 */ 581 sc->flags |= FXP_FLAG_CU_RESUME_BUG; 582 #endif 583 } 584 } 585 586 /* 587 * If we are not a 82557 chip, we can enable extended features. 588 */ 589 if (sc->revision != FXP_REV_82557) { 590 /* 591 * If MWI is enabled in the PCI configuration, and there 592 * is a valid cacheline size (8 or 16 dwords), then tell 593 * the board to turn on MWI. 594 */ 595 if (val & PCIM_CMD_MWRICEN && 596 pci_read_config(dev, PCIR_CACHELNSZ, 1) != 0) 597 sc->flags |= FXP_FLAG_MWI_ENABLE; 598 599 /* turn on the extended TxCB feature */ 600 sc->flags |= FXP_FLAG_EXT_TXCB; 601 602 /* enable reception of long frames for VLAN */ 603 sc->flags |= FXP_FLAG_LONG_PKT_EN; 604 } 605 606 /* 607 * Enable use of extended RFDs and TCBs for 82550 608 * and later chips. Note: we need extended TXCB support 609 * too, but that's already enabled by the code above. 610 * Be careful to do this only on the right devices. 611 * 612 * At least some 82550 cards probed as "chip=0x12298086 rev=0x0d" 613 * truncate packets that end with an mbuf containing 1 to 3 bytes 614 * when used with this feature enabled in the previous version of the 615 * driver. This problem appears to be fixed now that the driver 616 * always sets the hardware parse bit in the IPCB structure, which 617 * the "Intel 8255x 10/100 Mbps Ethernet Controller Family Open 618 * Source Software Developer Manual" says is necessary in the 619 * cases where packet truncation was observed. 620 * 621 * The device hint "hint.fxp.UNIT_NUMBER.ipcbxmit_disable" 622 * allows this feature to be disabled at boot time. 623 * 624 * If fxp is not compiled into the kernel, this feature may also 625 * be disabled at run time: 626 * # kldunload fxp 627 * # kenv hint.fxp.0.ipcbxmit_disable=1 628 * # kldload fxp 629 */ 630 631 if (resource_int_value("fxp", device_get_unit(dev), "ipcbxmit_disable", 632 &ipcbxmit_disable) != 0) 633 ipcbxmit_disable = 0; 634 if (ipcbxmit_disable == 0 && (sc->revision == FXP_REV_82550 || 635 sc->revision == FXP_REV_82550_C)) { 636 sc->rfa_size = sizeof (struct fxp_rfa); 637 sc->tx_cmd = FXP_CB_COMMAND_IPCBXMIT; 638 sc->flags |= FXP_FLAG_EXT_RFA; 639 } else { 640 sc->rfa_size = sizeof (struct fxp_rfa) - FXP_RFAX_LEN; 641 sc->tx_cmd = FXP_CB_COMMAND_XMIT; 642 } 643 644 /* 645 * Allocate DMA tags and DMA safe memory. 646 */ 647 maxtxseg = sc->flags & FXP_FLAG_EXT_RFA ? FXP_NTXSEG - 1 : FXP_NTXSEG; 648 error = bus_dma_tag_create(NULL, 2, 0, BUS_SPACE_MAXADDR_32BIT, 649 BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES * maxtxseg, 650 maxtxseg, MCLBYTES, 0, busdma_lock_mutex, &Giant, &sc->fxp_mtag); 651 if (error) { 652 device_printf(dev, "could not allocate dma tag\n"); 653 goto fail; 654 } 655 656 error = bus_dma_tag_create(NULL, 4, 0, BUS_SPACE_MAXADDR_32BIT, 657 BUS_SPACE_MAXADDR, NULL, NULL, sizeof(struct fxp_stats), 1, 658 sizeof(struct fxp_stats), 0, busdma_lock_mutex, &Giant, 659 &sc->fxp_stag); 660 if (error) { 661 device_printf(dev, "could not allocate dma tag\n"); 662 goto fail; 663 } 664 665 error = bus_dmamem_alloc(sc->fxp_stag, (void **)&sc->fxp_stats, 666 BUS_DMA_NOWAIT | BUS_DMA_ZERO, &sc->fxp_smap); 667 if (error) 668 goto fail; 669 error = bus_dmamap_load(sc->fxp_stag, sc->fxp_smap, sc->fxp_stats, 670 sizeof(struct fxp_stats), fxp_dma_map_addr, &sc->stats_addr, 0); 671 if (error) { 672 device_printf(dev, "could not map the stats buffer\n"); 673 goto fail; 674 } 675 676 error = bus_dma_tag_create(NULL, 4, 0, BUS_SPACE_MAXADDR_32BIT, 677 BUS_SPACE_MAXADDR, NULL, NULL, FXP_TXCB_SZ, 1, 678 FXP_TXCB_SZ, 0, busdma_lock_mutex, &Giant, &sc->cbl_tag); 679 if (error) { 680 device_printf(dev, "could not allocate dma tag\n"); 681 goto fail; 682 } 683 684 error = bus_dmamem_alloc(sc->cbl_tag, (void **)&sc->fxp_desc.cbl_list, 685 BUS_DMA_NOWAIT | BUS_DMA_ZERO, &sc->cbl_map); 686 if (error) 687 goto fail; 688 689 error = bus_dmamap_load(sc->cbl_tag, sc->cbl_map, 690 sc->fxp_desc.cbl_list, FXP_TXCB_SZ, fxp_dma_map_addr, 691 &sc->fxp_desc.cbl_addr, 0); 692 if (error) { 693 device_printf(dev, "could not map DMA memory\n"); 694 goto fail; 695 } 696 697 error = bus_dma_tag_create(NULL, 4, 0, BUS_SPACE_MAXADDR_32BIT, 698 BUS_SPACE_MAXADDR, NULL, NULL, sizeof(struct fxp_cb_mcs), 1, 699 sizeof(struct fxp_cb_mcs), 0, busdma_lock_mutex, &Giant, 700 &sc->mcs_tag); 701 if (error) { 702 device_printf(dev, "could not allocate dma tag\n"); 703 goto fail; 704 } 705 706 error = bus_dmamem_alloc(sc->mcs_tag, (void **)&sc->mcsp, 707 BUS_DMA_NOWAIT, &sc->mcs_map); 708 if (error) 709 goto fail; 710 error = bus_dmamap_load(sc->mcs_tag, sc->mcs_map, sc->mcsp, 711 sizeof(struct fxp_cb_mcs), fxp_dma_map_addr, &sc->mcs_addr, 0); 712 if (error) { 713 device_printf(dev, "can't map the multicast setup command\n"); 714 goto fail; 715 } 716 717 /* 718 * Pre-allocate the TX DMA maps. 719 */ 720 for (i = 0; i < FXP_NTXCB; i++) { 721 error = bus_dmamap_create(sc->fxp_mtag, 0, 722 &sc->fxp_desc.tx_list[i].tx_map); 723 if (error) { 724 device_printf(dev, "can't create DMA map for TX\n"); 725 goto fail; 726 } 727 } 728 error = bus_dmamap_create(sc->fxp_mtag, 0, &sc->spare_map); 729 if (error) { 730 device_printf(dev, "can't create spare DMA map\n"); 731 goto fail; 732 } 733 734 /* 735 * Pre-allocate our receive buffers. 736 */ 737 sc->fxp_desc.rx_head = sc->fxp_desc.rx_tail = NULL; 738 for (i = 0; i < FXP_NRFABUFS; i++) { 739 rxp = &sc->fxp_desc.rx_list[i]; 740 error = bus_dmamap_create(sc->fxp_mtag, 0, &rxp->rx_map); 741 if (error) { 742 device_printf(dev, "can't create DMA map for RX\n"); 743 goto fail; 744 } 745 if (fxp_add_rfabuf(sc, rxp) != 0) { 746 error = ENOMEM; 747 goto fail; 748 } 749 } 750 751 /* 752 * Read MAC address. 753 */ 754 fxp_read_eeprom(sc, myea, 0, 3); 755 sc->arpcom.ac_enaddr[0] = myea[0] & 0xff; 756 sc->arpcom.ac_enaddr[1] = myea[0] >> 8; 757 sc->arpcom.ac_enaddr[2] = myea[1] & 0xff; 758 sc->arpcom.ac_enaddr[3] = myea[1] >> 8; 759 sc->arpcom.ac_enaddr[4] = myea[2] & 0xff; 760 sc->arpcom.ac_enaddr[5] = myea[2] >> 8; 761 device_printf(dev, "Ethernet address %6D%s\n", 762 sc->arpcom.ac_enaddr, ":", 763 sc->flags & FXP_FLAG_SERIAL_MEDIA ? ", 10Mbps" : ""); 764 if (bootverbose) { 765 device_printf(dev, "PCI IDs: %04x %04x %04x %04x %04x\n", 766 pci_get_vendor(dev), pci_get_device(dev), 767 pci_get_subvendor(dev), pci_get_subdevice(dev), 768 pci_get_revid(dev)); 769 fxp_read_eeprom(sc, &data, 10, 1); 770 device_printf(dev, "Dynamic Standby mode is %s\n", 771 data & 0x02 ? "enabled" : "disabled"); 772 } 773 774 /* 775 * If this is only a 10Mbps device, then there is no MII, and 776 * the PHY will use a serial interface instead. 777 * 778 * The Seeq 80c24 AutoDUPLEX(tm) Ethernet Interface Adapter 779 * doesn't have a programming interface of any sort. The 780 * media is sensed automatically based on how the link partner 781 * is configured. This is, in essence, manual configuration. 782 */ 783 if (sc->flags & FXP_FLAG_SERIAL_MEDIA) { 784 ifmedia_add(&sc->sc_media, IFM_ETHER|IFM_MANUAL, 0, NULL); 785 ifmedia_set(&sc->sc_media, IFM_ETHER|IFM_MANUAL); 786 } else { 787 if (mii_phy_probe(dev, &sc->miibus, fxp_ifmedia_upd, 788 fxp_ifmedia_sts)) { 789 device_printf(dev, "MII without any PHY!\n"); 790 error = ENXIO; 791 goto fail; 792 } 793 } 794 795 ifp = &sc->arpcom.ac_if; 796 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 797 ifp->if_output = ether_output; 798 ifp->if_baudrate = 100000000; 799 ifp->if_init = fxp_init; 800 ifp->if_softc = sc; 801 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 802 ifp->if_ioctl = fxp_ioctl; 803 ifp->if_start = fxp_start; 804 ifp->if_watchdog = fxp_watchdog; 805 806 /* Enable checksum offload for 82550 or better chips */ 807 if (sc->flags & FXP_FLAG_EXT_RFA) { 808 ifp->if_hwassist = FXP_CSUM_FEATURES; 809 ifp->if_capabilities = IFCAP_HWCSUM; 810 ifp->if_capenable = ifp->if_capabilities; 811 } 812 813 /* 814 * Attach the interface. 815 */ 816 ether_ifattach(ifp, sc->arpcom.ac_enaddr); 817 818 /* 819 * Tell the upper layer(s) we support long frames. 820 */ 821 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 822 ifp->if_capabilities |= IFCAP_VLAN_MTU; 823 824 /* 825 * Let the system queue as many packets as we have available 826 * TX descriptors. 827 */ 828 ifp->if_snd.ifq_maxlen = FXP_NTXCB - 1; 829 830 /* 831 * Hook our interrupt after all initialization is complete. 832 * XXX This driver has been tested with the INTR_MPSAFFE flag set 833 * however, ifp and its functions are not fully locked so MPSAFE 834 * should not be used unless you can handle potential data loss. 835 */ 836 error = bus_setup_intr(dev, sc->irq, INTR_TYPE_NET | INTR_MPSAFE, 837 fxp_intr, sc, &sc->ih); 838 if (error) { 839 device_printf(dev, "could not setup irq\n"); 840 ether_ifdetach(&sc->arpcom.ac_if); 841 goto fail; 842 } 843 844 fail: 845 splx(s); 846 if (error) 847 fxp_release(sc); 848 return (error); 849 } 850 851 /* 852 * Release all resources. The softc lock should not be held and the 853 * interrupt should already be torn down. 854 */ 855 static void 856 fxp_release(struct fxp_softc *sc) 857 { 858 struct fxp_rx *rxp; 859 struct fxp_tx *txp; 860 int i; 861 862 mtx_assert(&sc->sc_mtx, MA_NOTOWNED); 863 if (sc->ih) 864 panic("fxp_release() called with intr handle still active"); 865 if (sc->miibus) 866 device_delete_child(sc->dev, sc->miibus); 867 bus_generic_detach(sc->dev); 868 ifmedia_removeall(&sc->sc_media); 869 if (sc->fxp_desc.cbl_list) { 870 bus_dmamap_unload(sc->cbl_tag, sc->cbl_map); 871 bus_dmamem_free(sc->cbl_tag, sc->fxp_desc.cbl_list, 872 sc->cbl_map); 873 } 874 if (sc->fxp_stats) { 875 bus_dmamap_unload(sc->fxp_stag, sc->fxp_smap); 876 bus_dmamem_free(sc->fxp_stag, sc->fxp_stats, sc->fxp_smap); 877 } 878 if (sc->mcsp) { 879 bus_dmamap_unload(sc->mcs_tag, sc->mcs_map); 880 bus_dmamem_free(sc->mcs_tag, sc->mcsp, sc->mcs_map); 881 } 882 if (sc->irq) 883 bus_release_resource(sc->dev, SYS_RES_IRQ, 0, sc->irq); 884 if (sc->mem) 885 bus_release_resource(sc->dev, sc->rtp, sc->rgd, sc->mem); 886 if (sc->fxp_mtag) { 887 for (i = 0; i < FXP_NRFABUFS; i++) { 888 rxp = &sc->fxp_desc.rx_list[i]; 889 if (rxp->rx_mbuf != NULL) { 890 bus_dmamap_sync(sc->fxp_mtag, rxp->rx_map, 891 BUS_DMASYNC_POSTREAD); 892 bus_dmamap_unload(sc->fxp_mtag, rxp->rx_map); 893 m_freem(rxp->rx_mbuf); 894 } 895 bus_dmamap_destroy(sc->fxp_mtag, rxp->rx_map); 896 } 897 bus_dmamap_destroy(sc->fxp_mtag, sc->spare_map); 898 bus_dma_tag_destroy(sc->fxp_mtag); 899 } 900 if (sc->fxp_stag) { 901 for (i = 0; i < FXP_NTXCB; i++) { 902 txp = &sc->fxp_desc.tx_list[i]; 903 if (txp->tx_mbuf != NULL) { 904 bus_dmamap_sync(sc->fxp_mtag, txp->tx_map, 905 BUS_DMASYNC_POSTWRITE); 906 bus_dmamap_unload(sc->fxp_mtag, txp->tx_map); 907 m_freem(txp->tx_mbuf); 908 } 909 bus_dmamap_destroy(sc->fxp_mtag, txp->tx_map); 910 } 911 bus_dma_tag_destroy(sc->fxp_stag); 912 } 913 if (sc->cbl_tag) 914 bus_dma_tag_destroy(sc->cbl_tag); 915 if (sc->mcs_tag) 916 bus_dma_tag_destroy(sc->mcs_tag); 917 918 sysctl_ctx_free(&sc->sysctl_ctx); 919 920 mtx_destroy(&sc->sc_mtx); 921 } 922 923 /* 924 * Detach interface. 925 */ 926 static int 927 fxp_detach(device_t dev) 928 { 929 struct fxp_softc *sc = device_get_softc(dev); 930 int s; 931 932 FXP_LOCK(sc); 933 s = splimp(); 934 935 sc->suspended = 1; /* Do same thing as we do for suspend */ 936 /* 937 * Close down routes etc. 938 */ 939 ether_ifdetach(&sc->arpcom.ac_if); 940 941 /* 942 * Stop DMA and drop transmit queue, but disable interrupts first. 943 */ 944 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE); 945 fxp_stop(sc); 946 FXP_UNLOCK(sc); 947 948 /* 949 * Unhook interrupt before dropping lock. This is to prevent 950 * races with fxp_intr(). 951 */ 952 bus_teardown_intr(sc->dev, sc->irq, sc->ih); 953 sc->ih = NULL; 954 955 splx(s); 956 957 /* Release our allocated resources. */ 958 fxp_release(sc); 959 return (0); 960 } 961 962 /* 963 * Device shutdown routine. Called at system shutdown after sync. The 964 * main purpose of this routine is to shut off receiver DMA so that 965 * kernel memory doesn't get clobbered during warmboot. 966 */ 967 static int 968 fxp_shutdown(device_t dev) 969 { 970 /* 971 * Make sure that DMA is disabled prior to reboot. Not doing 972 * do could allow DMA to corrupt kernel memory during the 973 * reboot before the driver initializes. 974 */ 975 fxp_stop((struct fxp_softc *) device_get_softc(dev)); 976 return (0); 977 } 978 979 /* 980 * Device suspend routine. Stop the interface and save some PCI 981 * settings in case the BIOS doesn't restore them properly on 982 * resume. 983 */ 984 static int 985 fxp_suspend(device_t dev) 986 { 987 struct fxp_softc *sc = device_get_softc(dev); 988 int i, s; 989 990 FXP_LOCK(sc); 991 s = splimp(); 992 993 fxp_stop(sc); 994 995 for (i = 0; i < 5; i++) 996 sc->saved_maps[i] = pci_read_config(dev, PCIR_BAR(i), 4); 997 sc->saved_biosaddr = pci_read_config(dev, PCIR_BIOS, 4); 998 sc->saved_intline = pci_read_config(dev, PCIR_INTLINE, 1); 999 sc->saved_cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1); 1000 sc->saved_lattimer = pci_read_config(dev, PCIR_LATTIMER, 1); 1001 1002 sc->suspended = 1; 1003 1004 FXP_UNLOCK(sc); 1005 splx(s); 1006 return (0); 1007 } 1008 1009 /* 1010 * Device resume routine. Restore some PCI settings in case the BIOS 1011 * doesn't, re-enable busmastering, and restart the interface if 1012 * appropriate. 1013 */ 1014 static int 1015 fxp_resume(device_t dev) 1016 { 1017 struct fxp_softc *sc = device_get_softc(dev); 1018 struct ifnet *ifp = &sc->sc_if; 1019 u_int16_t pci_command; 1020 int i, s; 1021 1022 FXP_LOCK(sc); 1023 s = splimp(); 1024 #ifndef BURN_BRIDGES 1025 fxp_powerstate_d0(dev); 1026 #endif 1027 /* better way to do this? */ 1028 for (i = 0; i < 5; i++) 1029 pci_write_config(dev, PCIR_BAR(i), sc->saved_maps[i], 4); 1030 pci_write_config(dev, PCIR_BIOS, sc->saved_biosaddr, 4); 1031 pci_write_config(dev, PCIR_INTLINE, sc->saved_intline, 1); 1032 pci_write_config(dev, PCIR_CACHELNSZ, sc->saved_cachelnsz, 1); 1033 pci_write_config(dev, PCIR_LATTIMER, sc->saved_lattimer, 1); 1034 1035 /* reenable busmastering */ 1036 pci_command = pci_read_config(dev, PCIR_COMMAND, 2); 1037 pci_command |= (PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN); 1038 pci_write_config(dev, PCIR_COMMAND, pci_command, 2); 1039 1040 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET); 1041 DELAY(10); 1042 1043 /* reinitialize interface if necessary */ 1044 if (ifp->if_flags & IFF_UP) 1045 fxp_init_body(sc); 1046 1047 sc->suspended = 0; 1048 1049 FXP_UNLOCK(sc); 1050 splx(s); 1051 return (0); 1052 } 1053 1054 static void 1055 fxp_eeprom_shiftin(struct fxp_softc *sc, int data, int length) 1056 { 1057 u_int16_t reg; 1058 int x; 1059 1060 /* 1061 * Shift in data. 1062 */ 1063 for (x = 1 << (length - 1); x; x >>= 1) { 1064 if (data & x) 1065 reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI; 1066 else 1067 reg = FXP_EEPROM_EECS; 1068 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 1069 DELAY(1); 1070 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK); 1071 DELAY(1); 1072 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 1073 DELAY(1); 1074 } 1075 } 1076 1077 /* 1078 * Read from the serial EEPROM. Basically, you manually shift in 1079 * the read opcode (one bit at a time) and then shift in the address, 1080 * and then you shift out the data (all of this one bit at a time). 1081 * The word size is 16 bits, so you have to provide the address for 1082 * every 16 bits of data. 1083 */ 1084 static u_int16_t 1085 fxp_eeprom_getword(struct fxp_softc *sc, int offset, int autosize) 1086 { 1087 u_int16_t reg, data; 1088 int x; 1089 1090 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 1091 /* 1092 * Shift in read opcode. 1093 */ 1094 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_READ, 3); 1095 /* 1096 * Shift in address. 1097 */ 1098 data = 0; 1099 for (x = 1 << (sc->eeprom_size - 1); x; x >>= 1) { 1100 if (offset & x) 1101 reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI; 1102 else 1103 reg = FXP_EEPROM_EECS; 1104 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 1105 DELAY(1); 1106 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK); 1107 DELAY(1); 1108 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 1109 DELAY(1); 1110 reg = CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO; 1111 data++; 1112 if (autosize && reg == 0) { 1113 sc->eeprom_size = data; 1114 break; 1115 } 1116 } 1117 /* 1118 * Shift out data. 1119 */ 1120 data = 0; 1121 reg = FXP_EEPROM_EECS; 1122 for (x = 1 << 15; x; x >>= 1) { 1123 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK); 1124 DELAY(1); 1125 if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO) 1126 data |= x; 1127 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 1128 DELAY(1); 1129 } 1130 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 1131 DELAY(1); 1132 1133 return (data); 1134 } 1135 1136 static void 1137 fxp_eeprom_putword(struct fxp_softc *sc, int offset, u_int16_t data) 1138 { 1139 int i; 1140 1141 /* 1142 * Erase/write enable. 1143 */ 1144 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 1145 fxp_eeprom_shiftin(sc, 0x4, 3); 1146 fxp_eeprom_shiftin(sc, 0x03 << (sc->eeprom_size - 2), sc->eeprom_size); 1147 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 1148 DELAY(1); 1149 /* 1150 * Shift in write opcode, address, data. 1151 */ 1152 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 1153 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_WRITE, 3); 1154 fxp_eeprom_shiftin(sc, offset, sc->eeprom_size); 1155 fxp_eeprom_shiftin(sc, data, 16); 1156 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 1157 DELAY(1); 1158 /* 1159 * Wait for EEPROM to finish up. 1160 */ 1161 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 1162 DELAY(1); 1163 for (i = 0; i < 1000; i++) { 1164 if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO) 1165 break; 1166 DELAY(50); 1167 } 1168 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 1169 DELAY(1); 1170 /* 1171 * Erase/write disable. 1172 */ 1173 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 1174 fxp_eeprom_shiftin(sc, 0x4, 3); 1175 fxp_eeprom_shiftin(sc, 0, sc->eeprom_size); 1176 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 1177 DELAY(1); 1178 } 1179 1180 /* 1181 * From NetBSD: 1182 * 1183 * Figure out EEPROM size. 1184 * 1185 * 559's can have either 64-word or 256-word EEPROMs, the 558 1186 * datasheet only talks about 64-word EEPROMs, and the 557 datasheet 1187 * talks about the existance of 16 to 256 word EEPROMs. 1188 * 1189 * The only known sizes are 64 and 256, where the 256 version is used 1190 * by CardBus cards to store CIS information. 1191 * 1192 * The address is shifted in msb-to-lsb, and after the last 1193 * address-bit the EEPROM is supposed to output a `dummy zero' bit, 1194 * after which follows the actual data. We try to detect this zero, by 1195 * probing the data-out bit in the EEPROM control register just after 1196 * having shifted in a bit. If the bit is zero, we assume we've 1197 * shifted enough address bits. The data-out should be tri-state, 1198 * before this, which should translate to a logical one. 1199 */ 1200 static void 1201 fxp_autosize_eeprom(struct fxp_softc *sc) 1202 { 1203 1204 /* guess maximum size of 256 words */ 1205 sc->eeprom_size = 8; 1206 1207 /* autosize */ 1208 (void) fxp_eeprom_getword(sc, 0, 1); 1209 } 1210 1211 static void 1212 fxp_read_eeprom(struct fxp_softc *sc, u_short *data, int offset, int words) 1213 { 1214 int i; 1215 1216 for (i = 0; i < words; i++) 1217 data[i] = fxp_eeprom_getword(sc, offset + i, 0); 1218 } 1219 1220 static void 1221 fxp_write_eeprom(struct fxp_softc *sc, u_short *data, int offset, int words) 1222 { 1223 int i; 1224 1225 for (i = 0; i < words; i++) 1226 fxp_eeprom_putword(sc, offset + i, data[i]); 1227 } 1228 1229 static void 1230 fxp_dma_map_txbuf(void *arg, bus_dma_segment_t *segs, int nseg, 1231 bus_size_t mapsize, int error) 1232 { 1233 struct fxp_softc *sc; 1234 struct fxp_cb_tx *txp; 1235 int i; 1236 1237 if (error) 1238 return; 1239 1240 KASSERT(nseg <= FXP_NTXSEG, ("too many DMA segments")); 1241 1242 sc = arg; 1243 txp = sc->fxp_desc.tx_last->tx_next->tx_cb; 1244 for (i = 0; i < nseg; i++) { 1245 KASSERT(segs[i].ds_len <= MCLBYTES, ("segment size too large")); 1246 /* 1247 * If this is an 82550/82551, then we're using extended 1248 * TxCBs _and_ we're using checksum offload. This means 1249 * that the TxCB is really an IPCB. One major difference 1250 * between the two is that with plain extended TxCBs, 1251 * the bottom half of the TxCB contains two entries from 1252 * the TBD array, whereas IPCBs contain just one entry: 1253 * one entry (8 bytes) has been sacrificed for the TCP/IP 1254 * checksum offload control bits. So to make things work 1255 * right, we have to start filling in the TBD array 1256 * starting from a different place depending on whether 1257 * the chip is an 82550/82551 or not. 1258 */ 1259 if (sc->flags & FXP_FLAG_EXT_RFA) { 1260 txp->tbd[i + 1].tb_addr = htole32(segs[i].ds_addr); 1261 txp->tbd[i + 1].tb_size = htole32(segs[i].ds_len); 1262 } else { 1263 txp->tbd[i].tb_addr = htole32(segs[i].ds_addr); 1264 txp->tbd[i].tb_size = htole32(segs[i].ds_len); 1265 } 1266 } 1267 txp->tbd_number = nseg; 1268 } 1269 1270 /* 1271 * Grab the softc lock and call the real fxp_start_body() routine 1272 */ 1273 static void 1274 fxp_start(struct ifnet *ifp) 1275 { 1276 struct fxp_softc *sc = ifp->if_softc; 1277 1278 FXP_LOCK(sc); 1279 fxp_start_body(ifp); 1280 FXP_UNLOCK(sc); 1281 } 1282 1283 /* 1284 * Start packet transmission on the interface. 1285 * This routine must be called with the softc lock held, and is an 1286 * internal entry point only. 1287 */ 1288 static void 1289 fxp_start_body(struct ifnet *ifp) 1290 { 1291 struct fxp_softc *sc = ifp->if_softc; 1292 struct fxp_tx *txp; 1293 struct mbuf *mb_head; 1294 int error; 1295 1296 mtx_assert(&sc->sc_mtx, MA_OWNED); 1297 /* 1298 * See if we need to suspend xmit until the multicast filter 1299 * has been reprogrammed (which can only be done at the head 1300 * of the command chain). 1301 */ 1302 if (sc->need_mcsetup) { 1303 return; 1304 } 1305 1306 txp = NULL; 1307 1308 /* 1309 * We're finished if there is nothing more to add to the list or if 1310 * we're all filled up with buffers to transmit. 1311 * NOTE: One TxCB is reserved to guarantee that fxp_mc_setup() can add 1312 * a NOP command when needed. 1313 */ 1314 while (ifp->if_snd.ifq_head != NULL && sc->tx_queued < FXP_NTXCB - 1) { 1315 1316 /* 1317 * Grab a packet to transmit. 1318 */ 1319 IF_DEQUEUE(&ifp->if_snd, mb_head); 1320 1321 /* 1322 * Get pointer to next available tx desc. 1323 */ 1324 txp = sc->fxp_desc.tx_last->tx_next; 1325 1326 /* 1327 * A note in Appendix B of the Intel 8255x 10/100 Mbps 1328 * Ethernet Controller Family Open Source Software 1329 * Developer Manual says: 1330 * Using software parsing is only allowed with legal 1331 * TCP/IP or UDP/IP packets. 1332 * ... 1333 * For all other datagrams, hardware parsing must 1334 * be used. 1335 * Software parsing appears to truncate ICMP and 1336 * fragmented UDP packets that contain one to three 1337 * bytes in the second (and final) mbuf of the packet. 1338 */ 1339 if (sc->flags & FXP_FLAG_EXT_RFA) 1340 txp->tx_cb->ipcb_ip_activation_high = 1341 FXP_IPCB_HARDWAREPARSING_ENABLE; 1342 1343 /* 1344 * Deal with TCP/IP checksum offload. Note that 1345 * in order for TCP checksum offload to work, 1346 * the pseudo header checksum must have already 1347 * been computed and stored in the checksum field 1348 * in the TCP header. The stack should have 1349 * already done this for us. 1350 */ 1351 1352 if (mb_head->m_pkthdr.csum_flags) { 1353 if (mb_head->m_pkthdr.csum_flags & CSUM_DELAY_DATA) { 1354 txp->tx_cb->ipcb_ip_schedule = 1355 FXP_IPCB_TCPUDP_CHECKSUM_ENABLE; 1356 if (mb_head->m_pkthdr.csum_flags & CSUM_TCP) 1357 txp->tx_cb->ipcb_ip_schedule |= 1358 FXP_IPCB_TCP_PACKET; 1359 } 1360 #ifdef FXP_IP_CSUM_WAR 1361 /* 1362 * XXX The 82550 chip appears to have trouble 1363 * dealing with IP header checksums in very small 1364 * datagrams, namely fragments from 1 to 3 bytes 1365 * in size. For example, say you want to transmit 1366 * a UDP packet of 1473 bytes. The packet will be 1367 * fragmented over two IP datagrams, the latter 1368 * containing only one byte of data. The 82550 will 1369 * botch the header checksum on the 1-byte fragment. 1370 * As long as the datagram contains 4 or more bytes 1371 * of data, you're ok. 1372 * 1373 * The following code attempts to work around this 1374 * problem: if the datagram is less than 38 bytes 1375 * in size (14 bytes ether header, 20 bytes IP header, 1376 * plus 4 bytes of data), we punt and compute the IP 1377 * header checksum by hand. This workaround doesn't 1378 * work very well, however, since it can be fooled 1379 * by things like VLAN tags and IP options that make 1380 * the header sizes/offsets vary. 1381 */ 1382 1383 if (mb_head->m_pkthdr.csum_flags & CSUM_IP) { 1384 if (mb_head->m_pkthdr.len < 38) { 1385 struct ip *ip; 1386 mb_head->m_data += ETHER_HDR_LEN; 1387 ip = mtod(mb_head, struct ip *); 1388 ip->ip_sum = in_cksum(mb_head, 1389 ip->ip_hl << 2); 1390 mb_head->m_data -= ETHER_HDR_LEN; 1391 } else { 1392 txp->tx_cb->ipcb_ip_activation_high = 1393 FXP_IPCB_HARDWAREPARSING_ENABLE; 1394 txp->tx_cb->ipcb_ip_schedule |= 1395 FXP_IPCB_IP_CHECKSUM_ENABLE; 1396 } 1397 } 1398 #endif 1399 } 1400 1401 /* 1402 * Go through each of the mbufs in the chain and initialize 1403 * the transmit buffer descriptors with the physical address 1404 * and size of the mbuf. 1405 */ 1406 error = bus_dmamap_load_mbuf(sc->fxp_mtag, txp->tx_map, 1407 mb_head, fxp_dma_map_txbuf, sc, 0); 1408 1409 if (error && error != EFBIG) { 1410 device_printf(sc->dev, "can't map mbuf (error %d)\n", 1411 error); 1412 m_freem(mb_head); 1413 break; 1414 } 1415 1416 if (error) { 1417 struct mbuf *mn; 1418 1419 /* 1420 * We ran out of segments. We have to recopy this 1421 * mbuf chain first. Bail out if we can't get the 1422 * new buffers. 1423 */ 1424 mn = m_defrag(mb_head, M_DONTWAIT); 1425 if (mn == NULL) { 1426 m_freem(mb_head); 1427 break; 1428 } else { 1429 mb_head = mn; 1430 } 1431 error = bus_dmamap_load_mbuf(sc->fxp_mtag, txp->tx_map, 1432 mb_head, fxp_dma_map_txbuf, sc, 0); 1433 if (error) { 1434 device_printf(sc->dev, 1435 "can't map mbuf (error %d)\n", error); 1436 m_freem(mb_head); 1437 break; 1438 } 1439 } 1440 1441 bus_dmamap_sync(sc->fxp_mtag, txp->tx_map, 1442 BUS_DMASYNC_PREWRITE); 1443 1444 txp->tx_mbuf = mb_head; 1445 txp->tx_cb->cb_status = 0; 1446 txp->tx_cb->byte_count = 0; 1447 if (sc->tx_queued != FXP_CXINT_THRESH - 1) { 1448 txp->tx_cb->cb_command = 1449 htole16(sc->tx_cmd | FXP_CB_COMMAND_SF | 1450 FXP_CB_COMMAND_S); 1451 } else { 1452 txp->tx_cb->cb_command = 1453 htole16(sc->tx_cmd | FXP_CB_COMMAND_SF | 1454 FXP_CB_COMMAND_S | FXP_CB_COMMAND_I); 1455 /* 1456 * Set a 5 second timer just in case we don't hear 1457 * from the card again. 1458 */ 1459 ifp->if_timer = 5; 1460 } 1461 txp->tx_cb->tx_threshold = tx_threshold; 1462 1463 /* 1464 * Advance the end of list forward. 1465 */ 1466 1467 #ifdef __alpha__ 1468 /* 1469 * On platforms which can't access memory in 16-bit 1470 * granularities, we must prevent the card from DMA'ing 1471 * up the status while we update the command field. 1472 * This could cause us to overwrite the completion status. 1473 * XXX This is probably bogus and we're _not_ looking 1474 * for atomicity here. 1475 */ 1476 atomic_clear_16(&sc->fxp_desc.tx_last->tx_cb->cb_command, 1477 htole16(FXP_CB_COMMAND_S)); 1478 #else 1479 sc->fxp_desc.tx_last->tx_cb->cb_command &= 1480 htole16(~FXP_CB_COMMAND_S); 1481 #endif /*__alpha__*/ 1482 sc->fxp_desc.tx_last = txp; 1483 1484 /* 1485 * Advance the beginning of the list forward if there are 1486 * no other packets queued (when nothing is queued, tx_first 1487 * sits on the last TxCB that was sent out). 1488 */ 1489 if (sc->tx_queued == 0) 1490 sc->fxp_desc.tx_first = txp; 1491 1492 sc->tx_queued++; 1493 1494 /* 1495 * Pass packet to bpf if there is a listener. 1496 */ 1497 BPF_MTAP(ifp, mb_head); 1498 } 1499 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE); 1500 1501 /* 1502 * We're finished. If we added to the list, issue a RESUME to get DMA 1503 * going again if suspended. 1504 */ 1505 if (txp != NULL) { 1506 fxp_scb_wait(sc); 1507 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_RESUME); 1508 } 1509 } 1510 1511 #ifdef DEVICE_POLLING 1512 static poll_handler_t fxp_poll; 1513 1514 static void 1515 fxp_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 1516 { 1517 struct fxp_softc *sc = ifp->if_softc; 1518 u_int8_t statack; 1519 1520 FXP_LOCK(sc); 1521 if (cmd == POLL_DEREGISTER) { /* final call, enable interrupts */ 1522 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, 0); 1523 FXP_UNLOCK(sc); 1524 return; 1525 } 1526 statack = FXP_SCB_STATACK_CXTNO | FXP_SCB_STATACK_CNA | 1527 FXP_SCB_STATACK_FR; 1528 if (cmd == POLL_AND_CHECK_STATUS) { 1529 u_int8_t tmp; 1530 1531 tmp = CSR_READ_1(sc, FXP_CSR_SCB_STATACK); 1532 if (tmp == 0xff || tmp == 0) { 1533 FXP_UNLOCK(sc); 1534 return; /* nothing to do */ 1535 } 1536 tmp &= ~statack; 1537 /* ack what we can */ 1538 if (tmp != 0) 1539 CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, tmp); 1540 statack |= tmp; 1541 } 1542 fxp_intr_body(sc, ifp, statack, count); 1543 FXP_UNLOCK(sc); 1544 } 1545 #endif /* DEVICE_POLLING */ 1546 1547 /* 1548 * Process interface interrupts. 1549 */ 1550 static void 1551 fxp_intr(void *xsc) 1552 { 1553 struct fxp_softc *sc = xsc; 1554 struct ifnet *ifp = &sc->sc_if; 1555 u_int8_t statack; 1556 1557 FXP_LOCK(sc); 1558 if (sc->suspended) { 1559 FXP_UNLOCK(sc); 1560 return; 1561 } 1562 1563 #ifdef DEVICE_POLLING 1564 if (ifp->if_flags & IFF_POLLING) { 1565 FXP_UNLOCK(sc); 1566 return; 1567 } 1568 if (ether_poll_register(fxp_poll, ifp)) { 1569 /* disable interrupts */ 1570 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE); 1571 FXP_UNLOCK(sc); 1572 fxp_poll(ifp, 0, 1); 1573 return; 1574 } 1575 #endif 1576 while ((statack = CSR_READ_1(sc, FXP_CSR_SCB_STATACK)) != 0) { 1577 /* 1578 * It should not be possible to have all bits set; the 1579 * FXP_SCB_INTR_SWI bit always returns 0 on a read. If 1580 * all bits are set, this may indicate that the card has 1581 * been physically ejected, so ignore it. 1582 */ 1583 if (statack == 0xff) { 1584 FXP_UNLOCK(sc); 1585 return; 1586 } 1587 1588 /* 1589 * First ACK all the interrupts in this pass. 1590 */ 1591 CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, statack); 1592 fxp_intr_body(sc, ifp, statack, -1); 1593 } 1594 FXP_UNLOCK(sc); 1595 } 1596 1597 static void 1598 fxp_txeof(struct fxp_softc *sc) 1599 { 1600 struct fxp_tx *txp; 1601 1602 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREREAD); 1603 for (txp = sc->fxp_desc.tx_first; sc->tx_queued && 1604 (le16toh(txp->tx_cb->cb_status) & FXP_CB_STATUS_C) != 0; 1605 txp = txp->tx_next) { 1606 if (txp->tx_mbuf != NULL) { 1607 bus_dmamap_sync(sc->fxp_mtag, txp->tx_map, 1608 BUS_DMASYNC_POSTWRITE); 1609 bus_dmamap_unload(sc->fxp_mtag, txp->tx_map); 1610 m_freem(txp->tx_mbuf); 1611 txp->tx_mbuf = NULL; 1612 /* clear this to reset csum offload bits */ 1613 txp->tx_cb->tbd[0].tb_addr = 0; 1614 } 1615 sc->tx_queued--; 1616 } 1617 sc->fxp_desc.tx_first = txp; 1618 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE); 1619 } 1620 1621 static void 1622 fxp_intr_body(struct fxp_softc *sc, struct ifnet *ifp, u_int8_t statack, 1623 int count) 1624 { 1625 struct mbuf *m; 1626 struct fxp_rx *rxp; 1627 struct fxp_rfa *rfa; 1628 int rnr = (statack & FXP_SCB_STATACK_RNR) ? 1 : 0; 1629 1630 mtx_assert(&sc->sc_mtx, MA_OWNED); 1631 if (rnr) 1632 fxp_rnr++; 1633 #ifdef DEVICE_POLLING 1634 /* Pick up a deferred RNR condition if `count' ran out last time. */ 1635 if (sc->flags & FXP_FLAG_DEFERRED_RNR) { 1636 sc->flags &= ~FXP_FLAG_DEFERRED_RNR; 1637 rnr = 1; 1638 } 1639 #endif 1640 1641 /* 1642 * Free any finished transmit mbuf chains. 1643 * 1644 * Handle the CNA event likt a CXTNO event. It used to 1645 * be that this event (control unit not ready) was not 1646 * encountered, but it is now with the SMPng modifications. 1647 * The exact sequence of events that occur when the interface 1648 * is brought up are different now, and if this event 1649 * goes unhandled, the configuration/rxfilter setup sequence 1650 * can stall for several seconds. The result is that no 1651 * packets go out onto the wire for about 5 to 10 seconds 1652 * after the interface is ifconfig'ed for the first time. 1653 */ 1654 if (statack & (FXP_SCB_STATACK_CXTNO | FXP_SCB_STATACK_CNA)) { 1655 fxp_txeof(sc); 1656 1657 ifp->if_timer = 0; 1658 if (sc->tx_queued == 0) { 1659 if (sc->need_mcsetup) 1660 fxp_mc_setup(sc); 1661 } 1662 /* 1663 * Try to start more packets transmitting. 1664 */ 1665 if (ifp->if_snd.ifq_head != NULL) 1666 fxp_start_body(ifp); 1667 } 1668 1669 /* 1670 * Just return if nothing happened on the receive side. 1671 */ 1672 if (!rnr && (statack & FXP_SCB_STATACK_FR) == 0) 1673 return; 1674 1675 /* 1676 * Process receiver interrupts. If a no-resource (RNR) 1677 * condition exists, get whatever packets we can and 1678 * re-start the receiver. 1679 * 1680 * When using polling, we do not process the list to completion, 1681 * so when we get an RNR interrupt we must defer the restart 1682 * until we hit the last buffer with the C bit set. 1683 * If we run out of cycles and rfa_headm has the C bit set, 1684 * record the pending RNR in the FXP_FLAG_DEFERRED_RNR flag so 1685 * that the info will be used in the subsequent polling cycle. 1686 */ 1687 for (;;) { 1688 rxp = sc->fxp_desc.rx_head; 1689 m = rxp->rx_mbuf; 1690 rfa = (struct fxp_rfa *)(m->m_ext.ext_buf + 1691 RFA_ALIGNMENT_FUDGE); 1692 bus_dmamap_sync(sc->fxp_mtag, rxp->rx_map, 1693 BUS_DMASYNC_POSTREAD); 1694 1695 #ifdef DEVICE_POLLING /* loop at most count times if count >=0 */ 1696 if (count >= 0 && count-- == 0) { 1697 if (rnr) { 1698 /* Defer RNR processing until the next time. */ 1699 sc->flags |= FXP_FLAG_DEFERRED_RNR; 1700 rnr = 0; 1701 } 1702 break; 1703 } 1704 #endif /* DEVICE_POLLING */ 1705 1706 if ((le16toh(rfa->rfa_status) & FXP_RFA_STATUS_C) == 0) 1707 break; 1708 1709 /* 1710 * Advance head forward. 1711 */ 1712 sc->fxp_desc.rx_head = rxp->rx_next; 1713 1714 /* 1715 * Add a new buffer to the receive chain. 1716 * If this fails, the old buffer is recycled 1717 * instead. 1718 */ 1719 if (fxp_add_rfabuf(sc, rxp) == 0) { 1720 int total_len; 1721 1722 /* 1723 * Fetch packet length (the top 2 bits of 1724 * actual_size are flags set by the controller 1725 * upon completion), and drop the packet in case 1726 * of bogus length or CRC errors. 1727 */ 1728 total_len = le16toh(rfa->actual_size) & 0x3fff; 1729 if (total_len < sizeof(struct ether_header) || 1730 total_len > MCLBYTES - RFA_ALIGNMENT_FUDGE - 1731 sc->rfa_size || 1732 le16toh(rfa->rfa_status) & FXP_RFA_STATUS_CRC) { 1733 m_freem(m); 1734 continue; 1735 } 1736 1737 /* Do IP checksum checking. */ 1738 if (le16toh(rfa->rfa_status) & FXP_RFA_STATUS_PARSE) { 1739 if (rfa->rfax_csum_sts & 1740 FXP_RFDX_CS_IP_CSUM_BIT_VALID) 1741 m->m_pkthdr.csum_flags |= 1742 CSUM_IP_CHECKED; 1743 if (rfa->rfax_csum_sts & 1744 FXP_RFDX_CS_IP_CSUM_VALID) 1745 m->m_pkthdr.csum_flags |= 1746 CSUM_IP_VALID; 1747 if ((rfa->rfax_csum_sts & 1748 FXP_RFDX_CS_TCPUDP_CSUM_BIT_VALID) && 1749 (rfa->rfax_csum_sts & 1750 FXP_RFDX_CS_TCPUDP_CSUM_VALID)) { 1751 m->m_pkthdr.csum_flags |= 1752 CSUM_DATA_VALID|CSUM_PSEUDO_HDR; 1753 m->m_pkthdr.csum_data = 0xffff; 1754 } 1755 } 1756 1757 m->m_pkthdr.len = m->m_len = total_len; 1758 m->m_pkthdr.rcvif = ifp; 1759 1760 /* 1761 * Drop locks before calling if_input() since it 1762 * may re-enter fxp_start() in the netisr case. 1763 * This would result in a lock reversal. Better 1764 * performance might be obtained by chaining all 1765 * packets received, dropping the lock, and then 1766 * calling if_input() on each one. 1767 */ 1768 FXP_UNLOCK(sc); 1769 (*ifp->if_input)(ifp, m); 1770 FXP_LOCK(sc); 1771 } 1772 } 1773 if (rnr) { 1774 fxp_scb_wait(sc); 1775 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 1776 sc->fxp_desc.rx_head->rx_addr); 1777 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_START); 1778 } 1779 } 1780 1781 /* 1782 * Update packet in/out/collision statistics. The i82557 doesn't 1783 * allow you to access these counters without doing a fairly 1784 * expensive DMA to get _all_ of the statistics it maintains, so 1785 * we do this operation here only once per second. The statistics 1786 * counters in the kernel are updated from the previous dump-stats 1787 * DMA and then a new dump-stats DMA is started. The on-chip 1788 * counters are zeroed when the DMA completes. If we can't start 1789 * the DMA immediately, we don't wait - we just prepare to read 1790 * them again next time. 1791 */ 1792 static void 1793 fxp_tick(void *xsc) 1794 { 1795 struct fxp_softc *sc = xsc; 1796 struct ifnet *ifp = &sc->sc_if; 1797 struct fxp_stats *sp = sc->fxp_stats; 1798 int s; 1799 1800 FXP_LOCK(sc); 1801 s = splimp(); 1802 bus_dmamap_sync(sc->fxp_stag, sc->fxp_smap, BUS_DMASYNC_POSTREAD); 1803 ifp->if_opackets += le32toh(sp->tx_good); 1804 ifp->if_collisions += le32toh(sp->tx_total_collisions); 1805 if (sp->rx_good) { 1806 ifp->if_ipackets += le32toh(sp->rx_good); 1807 sc->rx_idle_secs = 0; 1808 } else { 1809 /* 1810 * Receiver's been idle for another second. 1811 */ 1812 sc->rx_idle_secs++; 1813 } 1814 ifp->if_ierrors += 1815 le32toh(sp->rx_crc_errors) + 1816 le32toh(sp->rx_alignment_errors) + 1817 le32toh(sp->rx_rnr_errors) + 1818 le32toh(sp->rx_overrun_errors); 1819 /* 1820 * If any transmit underruns occured, bump up the transmit 1821 * threshold by another 512 bytes (64 * 8). 1822 */ 1823 if (sp->tx_underruns) { 1824 ifp->if_oerrors += le32toh(sp->tx_underruns); 1825 if (tx_threshold < 192) 1826 tx_threshold += 64; 1827 } 1828 1829 /* 1830 * Release any xmit buffers that have completed DMA. This isn't 1831 * strictly necessary to do here, but it's advantagous for mbufs 1832 * with external storage to be released in a timely manner rather 1833 * than being defered for a potentially long time. This limits 1834 * the delay to a maximum of one second. 1835 */ 1836 fxp_txeof(sc); 1837 1838 /* 1839 * If we haven't received any packets in FXP_MAC_RX_IDLE seconds, 1840 * then assume the receiver has locked up and attempt to clear 1841 * the condition by reprogramming the multicast filter. This is 1842 * a work-around for a bug in the 82557 where the receiver locks 1843 * up if it gets certain types of garbage in the syncronization 1844 * bits prior to the packet header. This bug is supposed to only 1845 * occur in 10Mbps mode, but has been seen to occur in 100Mbps 1846 * mode as well (perhaps due to a 10/100 speed transition). 1847 */ 1848 if (sc->rx_idle_secs > FXP_MAX_RX_IDLE) { 1849 sc->rx_idle_secs = 0; 1850 fxp_mc_setup(sc); 1851 } 1852 /* 1853 * If there is no pending command, start another stats 1854 * dump. Otherwise punt for now. 1855 */ 1856 if (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) == 0) { 1857 /* 1858 * Start another stats dump. 1859 */ 1860 bus_dmamap_sync(sc->fxp_stag, sc->fxp_smap, 1861 BUS_DMASYNC_PREREAD); 1862 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_DUMPRESET); 1863 } else { 1864 /* 1865 * A previous command is still waiting to be accepted. 1866 * Just zero our copy of the stats and wait for the 1867 * next timer event to update them. 1868 */ 1869 sp->tx_good = 0; 1870 sp->tx_underruns = 0; 1871 sp->tx_total_collisions = 0; 1872 1873 sp->rx_good = 0; 1874 sp->rx_crc_errors = 0; 1875 sp->rx_alignment_errors = 0; 1876 sp->rx_rnr_errors = 0; 1877 sp->rx_overrun_errors = 0; 1878 } 1879 if (sc->miibus != NULL) 1880 mii_tick(device_get_softc(sc->miibus)); 1881 1882 /* 1883 * Schedule another timeout one second from now. 1884 */ 1885 callout_reset(&sc->stat_ch, hz, fxp_tick, sc); 1886 FXP_UNLOCK(sc); 1887 splx(s); 1888 } 1889 1890 /* 1891 * Stop the interface. Cancels the statistics updater and resets 1892 * the interface. 1893 */ 1894 static void 1895 fxp_stop(struct fxp_softc *sc) 1896 { 1897 struct ifnet *ifp = &sc->sc_if; 1898 struct fxp_tx *txp; 1899 int i; 1900 1901 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1902 ifp->if_timer = 0; 1903 1904 #ifdef DEVICE_POLLING 1905 ether_poll_deregister(ifp); 1906 #endif 1907 /* 1908 * Cancel stats updater. 1909 */ 1910 callout_stop(&sc->stat_ch); 1911 1912 /* 1913 * Issue software reset, which also unloads the microcode. 1914 */ 1915 sc->flags &= ~FXP_FLAG_UCODE; 1916 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SOFTWARE_RESET); 1917 DELAY(50); 1918 1919 /* 1920 * Release any xmit buffers. 1921 */ 1922 txp = sc->fxp_desc.tx_list; 1923 if (txp != NULL) { 1924 for (i = 0; i < FXP_NTXCB; i++) { 1925 if (txp[i].tx_mbuf != NULL) { 1926 bus_dmamap_sync(sc->fxp_mtag, txp[i].tx_map, 1927 BUS_DMASYNC_POSTWRITE); 1928 bus_dmamap_unload(sc->fxp_mtag, txp[i].tx_map); 1929 m_freem(txp[i].tx_mbuf); 1930 txp[i].tx_mbuf = NULL; 1931 /* clear this to reset csum offload bits */ 1932 txp[i].tx_cb->tbd[0].tb_addr = 0; 1933 } 1934 } 1935 } 1936 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE); 1937 sc->tx_queued = 0; 1938 } 1939 1940 /* 1941 * Watchdog/transmission transmit timeout handler. Called when a 1942 * transmission is started on the interface, but no interrupt is 1943 * received before the timeout. This usually indicates that the 1944 * card has wedged for some reason. 1945 */ 1946 static void 1947 fxp_watchdog(struct ifnet *ifp) 1948 { 1949 struct fxp_softc *sc = ifp->if_softc; 1950 1951 FXP_LOCK(sc); 1952 device_printf(sc->dev, "device timeout\n"); 1953 ifp->if_oerrors++; 1954 1955 fxp_init_body(sc); 1956 FXP_UNLOCK(sc); 1957 } 1958 1959 /* 1960 * Acquire locks and then call the real initialization function. This 1961 * is necessary because ether_ioctl() calls if_init() and this would 1962 * result in mutex recursion if the mutex was held. 1963 */ 1964 static void 1965 fxp_init(void *xsc) 1966 { 1967 struct fxp_softc *sc = xsc; 1968 1969 FXP_LOCK(sc); 1970 fxp_init_body(sc); 1971 FXP_UNLOCK(sc); 1972 } 1973 1974 /* 1975 * Perform device initialization. This routine must be called with the 1976 * softc lock held. 1977 */ 1978 static void 1979 fxp_init_body(struct fxp_softc *sc) 1980 { 1981 struct ifnet *ifp = &sc->sc_if; 1982 struct fxp_cb_config *cbp; 1983 struct fxp_cb_ias *cb_ias; 1984 struct fxp_cb_tx *tcbp; 1985 struct fxp_tx *txp; 1986 struct fxp_cb_mcs *mcsp; 1987 int i, prm, s; 1988 1989 mtx_assert(&sc->sc_mtx, MA_OWNED); 1990 s = splimp(); 1991 /* 1992 * Cancel any pending I/O 1993 */ 1994 fxp_stop(sc); 1995 1996 prm = (ifp->if_flags & IFF_PROMISC) ? 1 : 0; 1997 1998 /* 1999 * Initialize base of CBL and RFA memory. Loading with zero 2000 * sets it up for regular linear addressing. 2001 */ 2002 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 0); 2003 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_BASE); 2004 2005 fxp_scb_wait(sc); 2006 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_BASE); 2007 2008 /* 2009 * Initialize base of dump-stats buffer. 2010 */ 2011 fxp_scb_wait(sc); 2012 bus_dmamap_sync(sc->fxp_stag, sc->fxp_smap, BUS_DMASYNC_PREREAD); 2013 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->stats_addr); 2014 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_DUMP_ADR); 2015 2016 /* 2017 * Attempt to load microcode if requested. 2018 */ 2019 if (ifp->if_flags & IFF_LINK0 && (sc->flags & FXP_FLAG_UCODE) == 0) 2020 fxp_load_ucode(sc); 2021 2022 /* 2023 * Initialize the multicast address list. 2024 */ 2025 if (fxp_mc_addrs(sc)) { 2026 mcsp = sc->mcsp; 2027 mcsp->cb_status = 0; 2028 mcsp->cb_command = 2029 htole16(FXP_CB_COMMAND_MCAS | FXP_CB_COMMAND_EL); 2030 mcsp->link_addr = 0xffffffff; 2031 /* 2032 * Start the multicast setup command. 2033 */ 2034 fxp_scb_wait(sc); 2035 bus_dmamap_sync(sc->mcs_tag, sc->mcs_map, BUS_DMASYNC_PREWRITE); 2036 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->mcs_addr); 2037 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2038 /* ...and wait for it to complete. */ 2039 fxp_dma_wait(sc, &mcsp->cb_status, sc->mcs_tag, sc->mcs_map); 2040 bus_dmamap_sync(sc->mcs_tag, sc->mcs_map, 2041 BUS_DMASYNC_POSTWRITE); 2042 } 2043 2044 /* 2045 * We temporarily use memory that contains the TxCB list to 2046 * construct the config CB. The TxCB list memory is rebuilt 2047 * later. 2048 */ 2049 cbp = (struct fxp_cb_config *)sc->fxp_desc.cbl_list; 2050 2051 /* 2052 * This bcopy is kind of disgusting, but there are a bunch of must be 2053 * zero and must be one bits in this structure and this is the easiest 2054 * way to initialize them all to proper values. 2055 */ 2056 bcopy(fxp_cb_config_template, cbp, sizeof(fxp_cb_config_template)); 2057 2058 cbp->cb_status = 0; 2059 cbp->cb_command = htole16(FXP_CB_COMMAND_CONFIG | 2060 FXP_CB_COMMAND_EL); 2061 cbp->link_addr = 0xffffffff; /* (no) next command */ 2062 cbp->byte_count = sc->flags & FXP_FLAG_EXT_RFA ? 32 : 22; 2063 cbp->rx_fifo_limit = 8; /* rx fifo threshold (32 bytes) */ 2064 cbp->tx_fifo_limit = 0; /* tx fifo threshold (0 bytes) */ 2065 cbp->adaptive_ifs = 0; /* (no) adaptive interframe spacing */ 2066 cbp->mwi_enable = sc->flags & FXP_FLAG_MWI_ENABLE ? 1 : 0; 2067 cbp->type_enable = 0; /* actually reserved */ 2068 cbp->read_align_en = sc->flags & FXP_FLAG_READ_ALIGN ? 1 : 0; 2069 cbp->end_wr_on_cl = sc->flags & FXP_FLAG_WRITE_ALIGN ? 1 : 0; 2070 cbp->rx_dma_bytecount = 0; /* (no) rx DMA max */ 2071 cbp->tx_dma_bytecount = 0; /* (no) tx DMA max */ 2072 cbp->dma_mbce = 0; /* (disable) dma max counters */ 2073 cbp->late_scb = 0; /* (don't) defer SCB update */ 2074 cbp->direct_dma_dis = 1; /* disable direct rcv dma mode */ 2075 cbp->tno_int_or_tco_en =0; /* (disable) tx not okay interrupt */ 2076 cbp->ci_int = 1; /* interrupt on CU idle */ 2077 cbp->ext_txcb_dis = sc->flags & FXP_FLAG_EXT_TXCB ? 0 : 1; 2078 cbp->ext_stats_dis = 1; /* disable extended counters */ 2079 cbp->keep_overrun_rx = 0; /* don't pass overrun frames to host */ 2080 cbp->save_bf = sc->revision == FXP_REV_82557 ? 1 : prm; 2081 cbp->disc_short_rx = !prm; /* discard short packets */ 2082 cbp->underrun_retry = 1; /* retry mode (once) on DMA underrun */ 2083 cbp->two_frames = 0; /* do not limit FIFO to 2 frames */ 2084 cbp->dyn_tbd = 0; /* (no) dynamic TBD mode */ 2085 cbp->ext_rfa = sc->flags & FXP_FLAG_EXT_RFA ? 1 : 0; 2086 cbp->mediatype = sc->flags & FXP_FLAG_SERIAL_MEDIA ? 0 : 1; 2087 cbp->csma_dis = 0; /* (don't) disable link */ 2088 cbp->tcp_udp_cksum = 0; /* (don't) enable checksum */ 2089 cbp->vlan_tco = 0; /* (don't) enable vlan wakeup */ 2090 cbp->link_wake_en = 0; /* (don't) assert PME# on link change */ 2091 cbp->arp_wake_en = 0; /* (don't) assert PME# on arp */ 2092 cbp->mc_wake_en = 0; /* (don't) enable PME# on mcmatch */ 2093 cbp->nsai = 1; /* (don't) disable source addr insert */ 2094 cbp->preamble_length = 2; /* (7 byte) preamble */ 2095 cbp->loopback = 0; /* (don't) loopback */ 2096 cbp->linear_priority = 0; /* (normal CSMA/CD operation) */ 2097 cbp->linear_pri_mode = 0; /* (wait after xmit only) */ 2098 cbp->interfrm_spacing = 6; /* (96 bits of) interframe spacing */ 2099 cbp->promiscuous = prm; /* promiscuous mode */ 2100 cbp->bcast_disable = 0; /* (don't) disable broadcasts */ 2101 cbp->wait_after_win = 0; /* (don't) enable modified backoff alg*/ 2102 cbp->ignore_ul = 0; /* consider U/L bit in IA matching */ 2103 cbp->crc16_en = 0; /* (don't) enable crc-16 algorithm */ 2104 cbp->crscdt = sc->flags & FXP_FLAG_SERIAL_MEDIA ? 1 : 0; 2105 2106 cbp->stripping = !prm; /* truncate rx packet to byte count */ 2107 cbp->padding = 1; /* (do) pad short tx packets */ 2108 cbp->rcv_crc_xfer = 0; /* (don't) xfer CRC to host */ 2109 cbp->long_rx_en = sc->flags & FXP_FLAG_LONG_PKT_EN ? 1 : 0; 2110 cbp->ia_wake_en = 0; /* (don't) wake up on address match */ 2111 cbp->magic_pkt_dis = 0; /* (don't) disable magic packet */ 2112 /* must set wake_en in PMCSR also */ 2113 cbp->force_fdx = 0; /* (don't) force full duplex */ 2114 cbp->fdx_pin_en = 1; /* (enable) FDX# pin */ 2115 cbp->multi_ia = 0; /* (don't) accept multiple IAs */ 2116 cbp->mc_all = sc->flags & FXP_FLAG_ALL_MCAST ? 1 : 0; 2117 cbp->gamla_rx = sc->flags & FXP_FLAG_EXT_RFA ? 1 : 0; 2118 2119 if (fxp_noflow || sc->revision == FXP_REV_82557) { 2120 /* 2121 * The 82557 has no hardware flow control, the values 2122 * below are the defaults for the chip. 2123 */ 2124 cbp->fc_delay_lsb = 0; 2125 cbp->fc_delay_msb = 0x40; 2126 cbp->pri_fc_thresh = 3; 2127 cbp->tx_fc_dis = 0; 2128 cbp->rx_fc_restop = 0; 2129 cbp->rx_fc_restart = 0; 2130 cbp->fc_filter = 0; 2131 cbp->pri_fc_loc = 1; 2132 } else { 2133 cbp->fc_delay_lsb = 0x1f; 2134 cbp->fc_delay_msb = 0x01; 2135 cbp->pri_fc_thresh = 3; 2136 cbp->tx_fc_dis = 0; /* enable transmit FC */ 2137 cbp->rx_fc_restop = 1; /* enable FC restop frames */ 2138 cbp->rx_fc_restart = 1; /* enable FC restart frames */ 2139 cbp->fc_filter = !prm; /* drop FC frames to host */ 2140 cbp->pri_fc_loc = 1; /* FC pri location (byte31) */ 2141 } 2142 2143 /* 2144 * Start the config command/DMA. 2145 */ 2146 fxp_scb_wait(sc); 2147 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE); 2148 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->fxp_desc.cbl_addr); 2149 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2150 /* ...and wait for it to complete. */ 2151 fxp_dma_wait(sc, &cbp->cb_status, sc->cbl_tag, sc->cbl_map); 2152 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_POSTWRITE); 2153 2154 /* 2155 * Now initialize the station address. Temporarily use the TxCB 2156 * memory area like we did above for the config CB. 2157 */ 2158 cb_ias = (struct fxp_cb_ias *)sc->fxp_desc.cbl_list; 2159 cb_ias->cb_status = 0; 2160 cb_ias->cb_command = htole16(FXP_CB_COMMAND_IAS | FXP_CB_COMMAND_EL); 2161 cb_ias->link_addr = 0xffffffff; 2162 bcopy(sc->arpcom.ac_enaddr, cb_ias->macaddr, 2163 sizeof(sc->arpcom.ac_enaddr)); 2164 2165 /* 2166 * Start the IAS (Individual Address Setup) command/DMA. 2167 */ 2168 fxp_scb_wait(sc); 2169 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE); 2170 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2171 /* ...and wait for it to complete. */ 2172 fxp_dma_wait(sc, &cb_ias->cb_status, sc->cbl_tag, sc->cbl_map); 2173 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_POSTWRITE); 2174 2175 /* 2176 * Initialize transmit control block (TxCB) list. 2177 */ 2178 txp = sc->fxp_desc.tx_list; 2179 tcbp = sc->fxp_desc.cbl_list; 2180 bzero(tcbp, FXP_TXCB_SZ); 2181 for (i = 0; i < FXP_NTXCB; i++) { 2182 txp[i].tx_cb = tcbp + i; 2183 txp[i].tx_mbuf = NULL; 2184 tcbp[i].cb_status = htole16(FXP_CB_STATUS_C | FXP_CB_STATUS_OK); 2185 tcbp[i].cb_command = htole16(FXP_CB_COMMAND_NOP); 2186 tcbp[i].link_addr = htole32(sc->fxp_desc.cbl_addr + 2187 (((i + 1) & FXP_TXCB_MASK) * sizeof(struct fxp_cb_tx))); 2188 if (sc->flags & FXP_FLAG_EXT_TXCB) 2189 tcbp[i].tbd_array_addr = 2190 htole32(FXP_TXCB_DMA_ADDR(sc, &tcbp[i].tbd[2])); 2191 else 2192 tcbp[i].tbd_array_addr = 2193 htole32(FXP_TXCB_DMA_ADDR(sc, &tcbp[i].tbd[0])); 2194 txp[i].tx_next = &txp[(i + 1) & FXP_TXCB_MASK]; 2195 } 2196 /* 2197 * Set the suspend flag on the first TxCB and start the control 2198 * unit. It will execute the NOP and then suspend. 2199 */ 2200 tcbp->cb_command = htole16(FXP_CB_COMMAND_NOP | FXP_CB_COMMAND_S); 2201 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE); 2202 sc->fxp_desc.tx_first = sc->fxp_desc.tx_last = txp; 2203 sc->tx_queued = 1; 2204 2205 fxp_scb_wait(sc); 2206 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2207 2208 /* 2209 * Initialize receiver buffer area - RFA. 2210 */ 2211 fxp_scb_wait(sc); 2212 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->fxp_desc.rx_head->rx_addr); 2213 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_START); 2214 2215 /* 2216 * Set current media. 2217 */ 2218 if (sc->miibus != NULL) 2219 mii_mediachg(device_get_softc(sc->miibus)); 2220 2221 ifp->if_flags |= IFF_RUNNING; 2222 ifp->if_flags &= ~IFF_OACTIVE; 2223 2224 /* 2225 * Enable interrupts. 2226 */ 2227 #ifdef DEVICE_POLLING 2228 /* 2229 * ... but only do that if we are not polling. And because (presumably) 2230 * the default is interrupts on, we need to disable them explicitly! 2231 */ 2232 if ( ifp->if_flags & IFF_POLLING ) 2233 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE); 2234 else 2235 #endif /* DEVICE_POLLING */ 2236 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, 0); 2237 2238 /* 2239 * Start stats updater. 2240 */ 2241 callout_reset(&sc->stat_ch, hz, fxp_tick, sc); 2242 splx(s); 2243 } 2244 2245 static int 2246 fxp_serial_ifmedia_upd(struct ifnet *ifp) 2247 { 2248 2249 return (0); 2250 } 2251 2252 static void 2253 fxp_serial_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 2254 { 2255 2256 ifmr->ifm_active = IFM_ETHER|IFM_MANUAL; 2257 } 2258 2259 /* 2260 * Change media according to request. 2261 */ 2262 static int 2263 fxp_ifmedia_upd(struct ifnet *ifp) 2264 { 2265 struct fxp_softc *sc = ifp->if_softc; 2266 struct mii_data *mii; 2267 2268 mii = device_get_softc(sc->miibus); 2269 mii_mediachg(mii); 2270 return (0); 2271 } 2272 2273 /* 2274 * Notify the world which media we're using. 2275 */ 2276 static void 2277 fxp_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 2278 { 2279 struct fxp_softc *sc = ifp->if_softc; 2280 struct mii_data *mii; 2281 2282 mii = device_get_softc(sc->miibus); 2283 mii_pollstat(mii); 2284 ifmr->ifm_active = mii->mii_media_active; 2285 ifmr->ifm_status = mii->mii_media_status; 2286 2287 if (ifmr->ifm_status & IFM_10_T && sc->flags & FXP_FLAG_CU_RESUME_BUG) 2288 sc->cu_resume_bug = 1; 2289 else 2290 sc->cu_resume_bug = 0; 2291 } 2292 2293 /* 2294 * Add a buffer to the end of the RFA buffer list. 2295 * Return 0 if successful, 1 for failure. A failure results in 2296 * adding the 'oldm' (if non-NULL) on to the end of the list - 2297 * tossing out its old contents and recycling it. 2298 * The RFA struct is stuck at the beginning of mbuf cluster and the 2299 * data pointer is fixed up to point just past it. 2300 */ 2301 static int 2302 fxp_add_rfabuf(struct fxp_softc *sc, struct fxp_rx *rxp) 2303 { 2304 struct mbuf *m; 2305 struct fxp_rfa *rfa, *p_rfa; 2306 struct fxp_rx *p_rx; 2307 bus_dmamap_t tmp_map; 2308 int error; 2309 2310 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 2311 if (m == NULL) 2312 return (ENOBUFS); 2313 2314 /* 2315 * Move the data pointer up so that the incoming data packet 2316 * will be 32-bit aligned. 2317 */ 2318 m->m_data += RFA_ALIGNMENT_FUDGE; 2319 2320 /* 2321 * Get a pointer to the base of the mbuf cluster and move 2322 * data start past it. 2323 */ 2324 rfa = mtod(m, struct fxp_rfa *); 2325 m->m_data += sc->rfa_size; 2326 rfa->size = htole16(MCLBYTES - sc->rfa_size - RFA_ALIGNMENT_FUDGE); 2327 2328 rfa->rfa_status = 0; 2329 rfa->rfa_control = htole16(FXP_RFA_CONTROL_EL); 2330 rfa->actual_size = 0; 2331 2332 /* 2333 * Initialize the rest of the RFA. Note that since the RFA 2334 * is misaligned, we cannot store values directly. We're thus 2335 * using the le32enc() function which handles endianness and 2336 * is also alignment-safe. 2337 */ 2338 le32enc(&rfa->link_addr, 0xffffffff); 2339 le32enc(&rfa->rbd_addr, 0xffffffff); 2340 2341 /* Map the RFA into DMA memory. */ 2342 error = bus_dmamap_load(sc->fxp_mtag, sc->spare_map, rfa, 2343 MCLBYTES - RFA_ALIGNMENT_FUDGE, fxp_dma_map_addr, 2344 &rxp->rx_addr, 0); 2345 if (error) { 2346 m_freem(m); 2347 return (error); 2348 } 2349 2350 bus_dmamap_unload(sc->fxp_mtag, rxp->rx_map); 2351 tmp_map = sc->spare_map; 2352 sc->spare_map = rxp->rx_map; 2353 rxp->rx_map = tmp_map; 2354 rxp->rx_mbuf = m; 2355 2356 bus_dmamap_sync(sc->fxp_mtag, rxp->rx_map, 2357 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2358 2359 /* 2360 * If there are other buffers already on the list, attach this 2361 * one to the end by fixing up the tail to point to this one. 2362 */ 2363 if (sc->fxp_desc.rx_head != NULL) { 2364 p_rx = sc->fxp_desc.rx_tail; 2365 p_rfa = (struct fxp_rfa *) 2366 (p_rx->rx_mbuf->m_ext.ext_buf + RFA_ALIGNMENT_FUDGE); 2367 p_rx->rx_next = rxp; 2368 le32enc(&p_rfa->link_addr, rxp->rx_addr); 2369 p_rfa->rfa_control = 0; 2370 bus_dmamap_sync(sc->fxp_mtag, p_rx->rx_map, 2371 BUS_DMASYNC_PREWRITE); 2372 } else { 2373 rxp->rx_next = NULL; 2374 sc->fxp_desc.rx_head = rxp; 2375 } 2376 sc->fxp_desc.rx_tail = rxp; 2377 return (0); 2378 } 2379 2380 static volatile int 2381 fxp_miibus_readreg(device_t dev, int phy, int reg) 2382 { 2383 struct fxp_softc *sc = device_get_softc(dev); 2384 int count = 10000; 2385 int value; 2386 2387 CSR_WRITE_4(sc, FXP_CSR_MDICONTROL, 2388 (FXP_MDI_READ << 26) | (reg << 16) | (phy << 21)); 2389 2390 while (((value = CSR_READ_4(sc, FXP_CSR_MDICONTROL)) & 0x10000000) == 0 2391 && count--) 2392 DELAY(10); 2393 2394 if (count <= 0) 2395 device_printf(dev, "fxp_miibus_readreg: timed out\n"); 2396 2397 return (value & 0xffff); 2398 } 2399 2400 static void 2401 fxp_miibus_writereg(device_t dev, int phy, int reg, int value) 2402 { 2403 struct fxp_softc *sc = device_get_softc(dev); 2404 int count = 10000; 2405 2406 CSR_WRITE_4(sc, FXP_CSR_MDICONTROL, 2407 (FXP_MDI_WRITE << 26) | (reg << 16) | (phy << 21) | 2408 (value & 0xffff)); 2409 2410 while ((CSR_READ_4(sc, FXP_CSR_MDICONTROL) & 0x10000000) == 0 && 2411 count--) 2412 DELAY(10); 2413 2414 if (count <= 0) 2415 device_printf(dev, "fxp_miibus_writereg: timed out\n"); 2416 } 2417 2418 static int 2419 fxp_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 2420 { 2421 struct fxp_softc *sc = ifp->if_softc; 2422 struct ifreq *ifr = (struct ifreq *)data; 2423 struct mii_data *mii; 2424 int s, error = 0; 2425 2426 /* 2427 * Detaching causes us to call ioctl with the mutex owned. Preclude 2428 * that by saying we're busy if the lock is already held. 2429 */ 2430 if (mtx_owned(&sc->sc_mtx)) 2431 return (EBUSY); 2432 2433 FXP_LOCK(sc); 2434 s = splimp(); 2435 2436 switch (command) { 2437 case SIOCSIFFLAGS: 2438 if (ifp->if_flags & IFF_ALLMULTI) 2439 sc->flags |= FXP_FLAG_ALL_MCAST; 2440 else 2441 sc->flags &= ~FXP_FLAG_ALL_MCAST; 2442 2443 /* 2444 * If interface is marked up and not running, then start it. 2445 * If it is marked down and running, stop it. 2446 * XXX If it's up then re-initialize it. This is so flags 2447 * such as IFF_PROMISC are handled. 2448 */ 2449 if (ifp->if_flags & IFF_UP) { 2450 fxp_init_body(sc); 2451 } else { 2452 if (ifp->if_flags & IFF_RUNNING) 2453 fxp_stop(sc); 2454 } 2455 break; 2456 2457 case SIOCADDMULTI: 2458 case SIOCDELMULTI: 2459 if (ifp->if_flags & IFF_ALLMULTI) 2460 sc->flags |= FXP_FLAG_ALL_MCAST; 2461 else 2462 sc->flags &= ~FXP_FLAG_ALL_MCAST; 2463 /* 2464 * Multicast list has changed; set the hardware filter 2465 * accordingly. 2466 */ 2467 if ((sc->flags & FXP_FLAG_ALL_MCAST) == 0) 2468 fxp_mc_setup(sc); 2469 /* 2470 * fxp_mc_setup() can set FXP_FLAG_ALL_MCAST, so check it 2471 * again rather than else {}. 2472 */ 2473 if (sc->flags & FXP_FLAG_ALL_MCAST) 2474 fxp_init_body(sc); 2475 error = 0; 2476 break; 2477 2478 case SIOCSIFMEDIA: 2479 case SIOCGIFMEDIA: 2480 if (sc->miibus != NULL) { 2481 mii = device_get_softc(sc->miibus); 2482 error = ifmedia_ioctl(ifp, ifr, 2483 &mii->mii_media, command); 2484 } else { 2485 error = ifmedia_ioctl(ifp, ifr, &sc->sc_media, command); 2486 } 2487 break; 2488 2489 default: 2490 /* 2491 * ether_ioctl() will eventually call fxp_start() which 2492 * will result in mutex recursion so drop it first. 2493 */ 2494 FXP_UNLOCK(sc); 2495 error = ether_ioctl(ifp, command, data); 2496 } 2497 if (mtx_owned(&sc->sc_mtx)) 2498 FXP_UNLOCK(sc); 2499 splx(s); 2500 return (error); 2501 } 2502 2503 /* 2504 * Fill in the multicast address list and return number of entries. 2505 */ 2506 static int 2507 fxp_mc_addrs(struct fxp_softc *sc) 2508 { 2509 struct fxp_cb_mcs *mcsp = sc->mcsp; 2510 struct ifnet *ifp = &sc->sc_if; 2511 struct ifmultiaddr *ifma; 2512 int nmcasts; 2513 2514 nmcasts = 0; 2515 if ((sc->flags & FXP_FLAG_ALL_MCAST) == 0) { 2516 #if __FreeBSD_version < 500000 2517 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 2518 #else 2519 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 2520 #endif 2521 if (ifma->ifma_addr->sa_family != AF_LINK) 2522 continue; 2523 if (nmcasts >= MAXMCADDR) { 2524 sc->flags |= FXP_FLAG_ALL_MCAST; 2525 nmcasts = 0; 2526 break; 2527 } 2528 bcopy(LLADDR((struct sockaddr_dl *)ifma->ifma_addr), 2529 &sc->mcsp->mc_addr[nmcasts][0], ETHER_ADDR_LEN); 2530 nmcasts++; 2531 } 2532 } 2533 mcsp->mc_cnt = htole16(nmcasts * ETHER_ADDR_LEN); 2534 return (nmcasts); 2535 } 2536 2537 /* 2538 * Program the multicast filter. 2539 * 2540 * We have an artificial restriction that the multicast setup command 2541 * must be the first command in the chain, so we take steps to ensure 2542 * this. By requiring this, it allows us to keep up the performance of 2543 * the pre-initialized command ring (esp. link pointers) by not actually 2544 * inserting the mcsetup command in the ring - i.e. its link pointer 2545 * points to the TxCB ring, but the mcsetup descriptor itself is not part 2546 * of it. We then can do 'CU_START' on the mcsetup descriptor and have it 2547 * lead into the regular TxCB ring when it completes. 2548 * 2549 * This function must be called at splimp. 2550 */ 2551 static void 2552 fxp_mc_setup(struct fxp_softc *sc) 2553 { 2554 struct fxp_cb_mcs *mcsp = sc->mcsp; 2555 struct ifnet *ifp = &sc->sc_if; 2556 struct fxp_tx *txp; 2557 int count; 2558 2559 /* 2560 * If there are queued commands, we must wait until they are all 2561 * completed. If we are already waiting, then add a NOP command 2562 * with interrupt option so that we're notified when all commands 2563 * have been completed - fxp_start() ensures that no additional 2564 * TX commands will be added when need_mcsetup is true. 2565 */ 2566 if (sc->tx_queued) { 2567 /* 2568 * need_mcsetup will be true if we are already waiting for the 2569 * NOP command to be completed (see below). In this case, bail. 2570 */ 2571 if (sc->need_mcsetup) 2572 return; 2573 sc->need_mcsetup = 1; 2574 2575 /* 2576 * Add a NOP command with interrupt so that we are notified 2577 * when all TX commands have been processed. 2578 */ 2579 txp = sc->fxp_desc.tx_last->tx_next; 2580 txp->tx_mbuf = NULL; 2581 txp->tx_cb->cb_status = 0; 2582 txp->tx_cb->cb_command = htole16(FXP_CB_COMMAND_NOP | 2583 FXP_CB_COMMAND_S | FXP_CB_COMMAND_I); 2584 /* 2585 * Advance the end of list forward. 2586 */ 2587 sc->fxp_desc.tx_last->tx_cb->cb_command &= 2588 htole16(~FXP_CB_COMMAND_S); 2589 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE); 2590 sc->fxp_desc.tx_last = txp; 2591 sc->tx_queued++; 2592 /* 2593 * Issue a resume in case the CU has just suspended. 2594 */ 2595 fxp_scb_wait(sc); 2596 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_RESUME); 2597 /* 2598 * Set a 5 second timer just in case we don't hear from the 2599 * card again. 2600 */ 2601 ifp->if_timer = 5; 2602 2603 return; 2604 } 2605 sc->need_mcsetup = 0; 2606 2607 /* 2608 * Initialize multicast setup descriptor. 2609 */ 2610 mcsp->cb_status = 0; 2611 mcsp->cb_command = htole16(FXP_CB_COMMAND_MCAS | 2612 FXP_CB_COMMAND_S | FXP_CB_COMMAND_I); 2613 mcsp->link_addr = htole32(sc->fxp_desc.cbl_addr); 2614 txp = &sc->fxp_desc.mcs_tx; 2615 txp->tx_mbuf = NULL; 2616 txp->tx_cb = (struct fxp_cb_tx *)sc->mcsp; 2617 txp->tx_next = sc->fxp_desc.tx_list; 2618 (void) fxp_mc_addrs(sc); 2619 sc->fxp_desc.tx_first = sc->fxp_desc.tx_last = txp; 2620 sc->tx_queued = 1; 2621 2622 /* 2623 * Wait until command unit is not active. This should never 2624 * be the case when nothing is queued, but make sure anyway. 2625 */ 2626 count = 100; 2627 while ((CSR_READ_1(sc, FXP_CSR_SCB_RUSCUS) >> 6) == 2628 FXP_SCB_CUS_ACTIVE && --count) 2629 DELAY(10); 2630 if (count == 0) { 2631 device_printf(sc->dev, "command queue timeout\n"); 2632 return; 2633 } 2634 2635 /* 2636 * Start the multicast setup command. 2637 */ 2638 fxp_scb_wait(sc); 2639 bus_dmamap_sync(sc->mcs_tag, sc->mcs_map, BUS_DMASYNC_PREWRITE); 2640 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->mcs_addr); 2641 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2642 2643 ifp->if_timer = 2; 2644 return; 2645 } 2646 2647 static u_int32_t fxp_ucode_d101a[] = D101_A_RCVBUNDLE_UCODE; 2648 static u_int32_t fxp_ucode_d101b0[] = D101_B0_RCVBUNDLE_UCODE; 2649 static u_int32_t fxp_ucode_d101ma[] = D101M_B_RCVBUNDLE_UCODE; 2650 static u_int32_t fxp_ucode_d101s[] = D101S_RCVBUNDLE_UCODE; 2651 static u_int32_t fxp_ucode_d102[] = D102_B_RCVBUNDLE_UCODE; 2652 static u_int32_t fxp_ucode_d102c[] = D102_C_RCVBUNDLE_UCODE; 2653 2654 #define UCODE(x) x, sizeof(x) 2655 2656 struct ucode { 2657 u_int32_t revision; 2658 u_int32_t *ucode; 2659 int length; 2660 u_short int_delay_offset; 2661 u_short bundle_max_offset; 2662 } ucode_table[] = { 2663 { FXP_REV_82558_A4, UCODE(fxp_ucode_d101a), D101_CPUSAVER_DWORD, 0 }, 2664 { FXP_REV_82558_B0, UCODE(fxp_ucode_d101b0), D101_CPUSAVER_DWORD, 0 }, 2665 { FXP_REV_82559_A0, UCODE(fxp_ucode_d101ma), 2666 D101M_CPUSAVER_DWORD, D101M_CPUSAVER_BUNDLE_MAX_DWORD }, 2667 { FXP_REV_82559S_A, UCODE(fxp_ucode_d101s), 2668 D101S_CPUSAVER_DWORD, D101S_CPUSAVER_BUNDLE_MAX_DWORD }, 2669 { FXP_REV_82550, UCODE(fxp_ucode_d102), 2670 D102_B_CPUSAVER_DWORD, D102_B_CPUSAVER_BUNDLE_MAX_DWORD }, 2671 { FXP_REV_82550_C, UCODE(fxp_ucode_d102c), 2672 D102_C_CPUSAVER_DWORD, D102_C_CPUSAVER_BUNDLE_MAX_DWORD }, 2673 { 0, NULL, 0, 0, 0 } 2674 }; 2675 2676 static void 2677 fxp_load_ucode(struct fxp_softc *sc) 2678 { 2679 struct ucode *uc; 2680 struct fxp_cb_ucode *cbp; 2681 2682 for (uc = ucode_table; uc->ucode != NULL; uc++) 2683 if (sc->revision == uc->revision) 2684 break; 2685 if (uc->ucode == NULL) 2686 return; 2687 cbp = (struct fxp_cb_ucode *)sc->fxp_desc.cbl_list; 2688 cbp->cb_status = 0; 2689 cbp->cb_command = htole16(FXP_CB_COMMAND_UCODE | FXP_CB_COMMAND_EL); 2690 cbp->link_addr = 0xffffffff; /* (no) next command */ 2691 memcpy(cbp->ucode, uc->ucode, uc->length); 2692 if (uc->int_delay_offset) 2693 *(u_int16_t *)&cbp->ucode[uc->int_delay_offset] = 2694 htole16(sc->tunable_int_delay + sc->tunable_int_delay / 2); 2695 if (uc->bundle_max_offset) 2696 *(u_int16_t *)&cbp->ucode[uc->bundle_max_offset] = 2697 htole16(sc->tunable_bundle_max); 2698 /* 2699 * Download the ucode to the chip. 2700 */ 2701 fxp_scb_wait(sc); 2702 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE); 2703 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->fxp_desc.cbl_addr); 2704 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2705 /* ...and wait for it to complete. */ 2706 fxp_dma_wait(sc, &cbp->cb_status, sc->cbl_tag, sc->cbl_map); 2707 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_POSTWRITE); 2708 device_printf(sc->dev, 2709 "Microcode loaded, int_delay: %d usec bundle_max: %d\n", 2710 sc->tunable_int_delay, 2711 uc->bundle_max_offset == 0 ? 0 : sc->tunable_bundle_max); 2712 sc->flags |= FXP_FLAG_UCODE; 2713 } 2714 2715 static int 2716 sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high) 2717 { 2718 int error, value; 2719 2720 value = *(int *)arg1; 2721 error = sysctl_handle_int(oidp, &value, 0, req); 2722 if (error || !req->newptr) 2723 return (error); 2724 if (value < low || value > high) 2725 return (EINVAL); 2726 *(int *)arg1 = value; 2727 return (0); 2728 } 2729 2730 /* 2731 * Interrupt delay is expressed in microseconds, a multiplier is used 2732 * to convert this to the appropriate clock ticks before using. 2733 */ 2734 static int 2735 sysctl_hw_fxp_int_delay(SYSCTL_HANDLER_ARGS) 2736 { 2737 return (sysctl_int_range(oidp, arg1, arg2, req, 300, 3000)); 2738 } 2739 2740 static int 2741 sysctl_hw_fxp_bundle_max(SYSCTL_HANDLER_ARGS) 2742 { 2743 return (sysctl_int_range(oidp, arg1, arg2, req, 1, 0xffff)); 2744 } 2745