xref: /freebsd/sys/dev/flash/w25nreg.h (revision 89e3c2d27ab426e1edf326d470318d75d8be5e37)
1*89e3c2d2SAdrian Chadd /*-
2*89e3c2d2SAdrian Chadd  * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
3*89e3c2d2SAdrian Chadd  *
4*89e3c2d2SAdrian Chadd  * Copyright (c) 2022 Adrian Chadd <adrian@FreeBSD.org>.
5*89e3c2d2SAdrian Chadd  * All rights reserved.
6*89e3c2d2SAdrian Chadd  *
7*89e3c2d2SAdrian Chadd  * Redistribution and use in source and binary forms, with or without
8*89e3c2d2SAdrian Chadd  * modification, are permitted provided that the following conditions
9*89e3c2d2SAdrian Chadd  * are met:
10*89e3c2d2SAdrian Chadd  * 1. Redistributions of source code must retain the above copyright
11*89e3c2d2SAdrian Chadd  *    notice unmodified, this list of conditions, and the following
12*89e3c2d2SAdrian Chadd  *    disclaimer.
13*89e3c2d2SAdrian Chadd  * 2. Redistributions in binary form must reproduce the above copyright
14*89e3c2d2SAdrian Chadd  *    notice, this list of conditions and the following disclaimer in the
15*89e3c2d2SAdrian Chadd  *    documentation and/or other materials provided with the distribution.
16*89e3c2d2SAdrian Chadd  *
17*89e3c2d2SAdrian Chadd  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
18*89e3c2d2SAdrian Chadd  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19*89e3c2d2SAdrian Chadd  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20*89e3c2d2SAdrian Chadd  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
21*89e3c2d2SAdrian Chadd  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22*89e3c2d2SAdrian Chadd  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23*89e3c2d2SAdrian Chadd  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24*89e3c2d2SAdrian Chadd  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25*89e3c2d2SAdrian Chadd  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26*89e3c2d2SAdrian Chadd  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27*89e3c2d2SAdrian Chadd  * SUCH DAMAGE.
28*89e3c2d2SAdrian Chadd  */
29*89e3c2d2SAdrian Chadd 
30*89e3c2d2SAdrian Chadd #ifndef	__W25NREG_H__
31*89e3c2d2SAdrian Chadd #define	__W25NREG_H__
32*89e3c2d2SAdrian Chadd 
33*89e3c2d2SAdrian Chadd /*
34*89e3c2d2SAdrian Chadd  * Commands
35*89e3c2d2SAdrian Chadd  */
36*89e3c2d2SAdrian Chadd #define	CMD_READ_STATUS		0x05
37*89e3c2d2SAdrian Chadd #define	CMD_FAST_READ		0x0B
38*89e3c2d2SAdrian Chadd #define	CMD_PAGE_DATA_READ	0x13
39*89e3c2d2SAdrian Chadd #define	CMD_READ_IDENT		0x9F
40*89e3c2d2SAdrian Chadd #define	CMD_LAST_ECC_FAILURE	0xA9
41*89e3c2d2SAdrian Chadd #define	CMD_BLOCK_ERAS		0xD8
42*89e3c2d2SAdrian Chadd 
43*89e3c2d2SAdrian Chadd /*
44*89e3c2d2SAdrian Chadd  * Three status registers - 0xAx, 0xBx, 0xCx.
45*89e3c2d2SAdrian Chadd  *
46*89e3c2d2SAdrian Chadd  * status register 1 (0xA0) is for protection config/status
47*89e3c2d2SAdrian Chadd  * status register 2 (0xB0) is for configuration config/status
48*89e3c2d2SAdrian Chadd  * status register 3 (0xC0) is for general status
49*89e3c2d2SAdrian Chadd  */
50*89e3c2d2SAdrian Chadd 
51*89e3c2d2SAdrian Chadd #define	STATUS_REG_1		0xA0
52*89e3c2d2SAdrian Chadd #define		STATUS_REG_1_SRP1	0x10
53*89e3c2d2SAdrian Chadd #define		STATUS_REG_1_WP_EN	0x20
54*89e3c2d2SAdrian Chadd #define		STATUS_REG_1_TOP_BOTTOM_PROT	0x40
55*89e3c2d2SAdrian Chadd #define		STATUS_REG_1_BP0	0x80
56*89e3c2d2SAdrian Chadd #define		STATUS_REG_1_BP1	0x10
57*89e3c2d2SAdrian Chadd #define		STATUS_REG_1_BP2	0x20
58*89e3c2d2SAdrian Chadd #define		STATUS_REG_1_BP3	0x40
59*89e3c2d2SAdrian Chadd #define		STATUS_REG_1_SRP0	0x80
60*89e3c2d2SAdrian Chadd 
61*89e3c2d2SAdrian Chadd #define	STATUS_REG_2			0xB0
62*89e3c2d2SAdrian Chadd #define		STATUS_REG_2_BUF_EN	0x08
63*89e3c2d2SAdrian Chadd #define		STATUS_REG_2_ECC_EN	0x10
64*89e3c2d2SAdrian Chadd #define		STATUS_REG_2_SR1_LOCK	0x20
65*89e3c2d2SAdrian Chadd #define		STATUS_REG_2_OTP_EN	0x40
66*89e3c2d2SAdrian Chadd #define		STATUS_REG_2_OTP_L	0x80
67*89e3c2d2SAdrian Chadd 
68*89e3c2d2SAdrian Chadd #define	STATUS_REG_3			0xC0
69*89e3c2d2SAdrian Chadd #define		STATUS_REG_3_BUSY		0x01
70*89e3c2d2SAdrian Chadd #define		STATUS_REG_3_WRITE_EN_LATCH	0x02
71*89e3c2d2SAdrian Chadd #define		STATUS_REG_3_ERASE_FAIL		0x04
72*89e3c2d2SAdrian Chadd #define		STATUS_REG_3_PROGRAM_FAIL	0x08
73*89e3c2d2SAdrian Chadd #define		STATUS_REG_3_ECC_STATUS_0	0x10
74*89e3c2d2SAdrian Chadd #define		STATUS_REG_3_ECC_STATUS_1	0x20
75*89e3c2d2SAdrian Chadd #define		STATUS_REG_3_ECC_STATUS_SHIFT	4
76*89e3c2d2SAdrian Chadd #define		STATUS_REG_3_ECC_STATUS_MASK	0x03
77*89e3c2d2SAdrian Chadd #define		STATUS_REG_3_BBM_LUT_FULL	0x40
78*89e3c2d2SAdrian Chadd 
79*89e3c2d2SAdrian Chadd /* ECC status */
80*89e3c2d2SAdrian Chadd #define		STATUS_ECC_OK			0
81*89e3c2d2SAdrian Chadd #define		STATUS_ECC_1BIT_OK		1
82*89e3c2d2SAdrian Chadd #define		STATUS_ECC_2BIT_ERR		2
83*89e3c2d2SAdrian Chadd #define		STATUS_ECC_2BIT_ERR_MULTIPAGE	3
84*89e3c2d2SAdrian Chadd 
85*89e3c2d2SAdrian Chadd #endif	/* __W25NREG_H__ */
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