1 /*- 2 * Copyright (c) 2021 Alstom Group. 3 * Copyright (c) 2021 Semihalf. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 15 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 16 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 17 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 18 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 19 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 20 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 21 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 22 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 23 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 24 */ 25 26 #ifndef DEV_FLASH_FLEX_SPI_H_ 27 #define DEV_FLASH_FLEX_SPI_H_ 28 29 #define BIT(x) (1 << (x)) 30 31 /* Registers used by the driver */ 32 #define FSPI_MCR0 0x00 33 #define FSPI_MCR0_AHB_TIMEOUT(x) ((x) << 24) 34 #define FSPI_MCR0_IP_TIMEOUT(x) ((x) << 16) 35 #define FSPI_MCR0_LEARN_EN BIT(15) 36 #define FSPI_MCR0_SCRFRUN_EN BIT(14) 37 #define FSPI_MCR0_OCTCOMB_EN BIT(13) 38 #define FSPI_MCR0_DOZE_EN BIT(12) 39 #define FSPI_MCR0_HSEN BIT(11) 40 #define FSPI_MCR0_SERCLKDIV BIT(8) 41 #define FSPI_MCR0_ATDF_EN BIT(7) 42 #define FSPI_MCR0_ARDF_EN BIT(6) 43 #define FSPI_MCR0_RXCLKSRC(x) ((x) << 4) 44 #define FSPI_MCR0_END_CFG(x) ((x) << 2) 45 #define FSPI_MCR0_MDIS BIT(1) 46 #define FSPI_MCR0_SWRST BIT(0) 47 48 #define FSPI_MCR1 0x04 49 #define FSPI_MCR1_SEQ_TIMEOUT(x) ((x) << 16) 50 #define FSPI_MCR1_AHB_TIMEOUT(x) (x) 51 52 #define FSPI_MCR2 0x08 53 #define FSPI_MCR2_IDLE_WAIT(x) ((x) << 24) 54 #define FSPI_MCR2_SAMEDEVICEEN BIT(15) 55 #define FSPI_MCR2_CLRLRPHS BIT(14) 56 #define FSPI_MCR2_ABRDATSZ BIT(8) 57 #define FSPI_MCR2_ABRLEARN BIT(7) 58 #define FSPI_MCR2_ABR_READ BIT(6) 59 #define FSPI_MCR2_ABRWRITE BIT(5) 60 #define FSPI_MCR2_ABRDUMMY BIT(4) 61 #define FSPI_MCR2_ABR_MODE BIT(3) 62 #define FSPI_MCR2_ABRCADDR BIT(2) 63 #define FSPI_MCR2_ABRRADDR BIT(1) 64 #define FSPI_MCR2_ABR_CMD BIT(0) 65 66 #define FSPI_AHBCR 0x0c 67 #define FSPI_AHBCR_RDADDROPT BIT(6) 68 #define FSPI_AHBCR_PREF_EN BIT(5) 69 #define FSPI_AHBCR_BUFF_EN BIT(4) 70 #define FSPI_AHBCR_CACH_EN BIT(3) 71 #define FSPI_AHBCR_CLRTXBUF BIT(2) 72 #define FSPI_AHBCR_CLRRXBUF BIT(1) 73 #define FSPI_AHBCR_PAR_EN BIT(0) 74 75 #define FSPI_INTEN 0x10 76 #define FSPI_INTEN_SCLKSBWR BIT(9) 77 #define FSPI_INTEN_SCLKSBRD BIT(8) 78 #define FSPI_INTEN_DATALRNFL BIT(7) 79 #define FSPI_INTEN_IPTXWE BIT(6) 80 #define FSPI_INTEN_IPRXWA BIT(5) 81 #define FSPI_INTEN_AHBCMDERR BIT(4) 82 #define FSPI_INTEN_IPCMDERR BIT(3) 83 #define FSPI_INTEN_AHBCMDGE BIT(2) 84 #define FSPI_INTEN_IPCMDGE BIT(1) 85 #define FSPI_INTEN_IPCMDDONE BIT(0) 86 87 #define FSPI_INTR 0x14 88 #define FSPI_INTR_SCLKSBWR BIT(9) 89 #define FSPI_INTR_SCLKSBRD BIT(8) 90 #define FSPI_INTR_DATALRNFL BIT(7) 91 #define FSPI_INTR_IPTXWE BIT(6) 92 #define FSPI_INTR_IPRXWA BIT(5) 93 #define FSPI_INTR_AHBCMDERR BIT(4) 94 #define FSPI_INTR_IPCMDERR BIT(3) 95 #define FSPI_INTR_AHBCMDGE BIT(2) 96 #define FSPI_INTR_IPCMDGE BIT(1) 97 #define FSPI_INTR_IPCMDDONE BIT(0) 98 99 #define FSPI_LUTKEY 0x18 100 #define FSPI_LUTKEY_VALUE 0x5AF05AF0 101 102 #define FSPI_LCKCR 0x1C 103 104 #define FSPI_LCKER_LOCK 0x1 105 #define FSPI_LCKER_UNLOCK 0x2 106 107 #define FSPI_BUFXCR_INVALID_MSTRID 0xE 108 #define FSPI_AHBRX_BUF0CR0 0x20 109 #define FSPI_AHBRX_BUF1CR0 0x24 110 #define FSPI_AHBRX_BUF2CR0 0x28 111 #define FSPI_AHBRX_BUF3CR0 0x2C 112 #define FSPI_AHBRX_BUF4CR0 0x30 113 #define FSPI_AHBRX_BUF5CR0 0x34 114 #define FSPI_AHBRX_BUF6CR0 0x38 115 #define FSPI_AHBRX_BUF7CR0 0x3C 116 #define FSPI_AHBRXBUF0CR7_PREF BIT(31) 117 118 #define FSPI_AHBRX_BUF0CR1 0x40 119 #define FSPI_AHBRX_BUF1CR1 0x44 120 #define FSPI_AHBRX_BUF2CR1 0x48 121 #define FSPI_AHBRX_BUF3CR1 0x4C 122 #define FSPI_AHBRX_BUF4CR1 0x50 123 #define FSPI_AHBRX_BUF5CR1 0x54 124 #define FSPI_AHBRX_BUF6CR1 0x58 125 #define FSPI_AHBRX_BUF7CR1 0x5C 126 127 #define FSPI_FLSHA1CR0 0x60 128 #define FSPI_FLSHA2CR0 0x64 129 #define FSPI_FLSHB1CR0 0x68 130 #define FSPI_FLSHB2CR0 0x6C 131 #define FSPI_FLSHXCR0_SZ_KB 10 132 #define FSPI_FLSHXCR0_SZ(x) ((x) >> FSPI_FLSHXCR0_SZ_KB) 133 134 #define FSPI_FLSHA1CR1 0x70 135 #define FSPI_FLSHA2CR1 0x74 136 #define FSPI_FLSHB1CR1 0x78 137 #define FSPI_FLSHB2CR1 0x7C 138 #define FSPI_FLSHXCR1_CSINTR(x) ((x) << 16) 139 #define FSPI_FLSHXCR1_CAS(x) ((x) << 11) 140 #define FSPI_FLSHXCR1_WA BIT(10) 141 #define FSPI_FLSHXCR1_TCSH(x) ((x) << 5) 142 #define FSPI_FLSHXCR1_TCSS(x) (x) 143 144 #define FSPI_FLSHA1CR2 0x80 145 #define FSPI_FLSHA2CR2 0x84 146 #define FSPI_FLSHB1CR2 0x88 147 #define FSPI_FLSHB2CR2 0x8C 148 #define FSPI_FLSHXCR2_CLRINSP BIT(24) 149 #define FSPI_FLSHXCR2_AWRWAIT BIT(16) 150 #define FSPI_FLSHXCR2_AWRSEQN_SHIFT 13 151 #define FSPI_FLSHXCR2_AWRSEQI_SHIFT 8 152 #define FSPI_FLSHXCR2_ARDSEQN_SHIFT 5 153 #define FSPI_FLSHXCR2_ARDSEQI_SHIFT 0 154 155 #define FSPI_IPCR0 0xA0 156 157 #define FSPI_IPCR1 0xA4 158 #define FSPI_IPCR1_IPAREN BIT(31) 159 #define FSPI_IPCR1_SEQNUM_SHIFT 24 160 #define FSPI_IPCR1_SEQID_SHIFT 16 161 #define FSPI_IPCR1_IDATSZ(x) (x) 162 163 #define FSPI_IPCMD 0xB0 164 #define FSPI_IPCMD_TRG BIT(0) 165 166 #define FSPI_DLPR 0xB4 167 168 #define FSPI_IPRXFCR 0xB8 169 #define FSPI_IPRXFCR_CLR BIT(0) 170 #define FSPI_IPRXFCR_DMA_EN BIT(1) 171 #define FSPI_IPRXFCR_WMRK(x) ((x) << 2) 172 173 #define FSPI_IPTXFCR 0xBC 174 #define FSPI_IPTXFCR_CLR BIT(0) 175 #define FSPI_IPTXFCR_DMA_EN BIT(1) 176 #define FSPI_IPTXFCR_WMRK(x) ((x) << 2) 177 178 #define FSPI_DLLACR 0xC0 179 #define FSPI_DLLACR_OVRDEN BIT(8) 180 181 #define FSPI_DLLBCR 0xC4 182 #define FSPI_DLLBCR_OVRDEN BIT(8) 183 184 #define FSPI_STS0 0xE0 185 #define FSPI_STS0_DLPHB(x) ((x) << 8) 186 #define FSPI_STS0_DLPHA(x) ((x) << 4) 187 #define FSPI_STS0_CMD_SRC(x) ((x) << 2) 188 #define FSPI_STS0_ARB_IDLE BIT(1) 189 #define FSPI_STS0_SEQ_IDLE BIT(0) 190 191 #define FSPI_STS1 0xE4 192 #define FSPI_STS1_IP_ERRCD(x) ((x) << 24) 193 #define FSPI_STS1_IP_ERRID(x) ((x) << 16) 194 #define FSPI_STS1_AHB_ERRCD(x) ((x) << 8) 195 #define FSPI_STS1_AHB_ERRID(x) (x) 196 197 #define FSPI_AHBSPNST 0xEC 198 #define FSPI_AHBSPNST_DATLFT(x) ((x) << 16) 199 #define FSPI_AHBSPNST_BUFID(x) ((x) << 1) 200 #define FSPI_AHBSPNST_ACTIVE BIT(0) 201 202 #define FSPI_IPRXFSTS 0xF0 203 #define FSPI_IPRXFSTS_RDCNTR(x) ((x) << 16) 204 #define FSPI_IPRXFSTS_FILL(x) (x) 205 206 #define FSPI_IPTXFSTS 0xF4 207 #define FSPI_IPTXFSTS_WRCNTR(x) ((x) << 16) 208 #define FSPI_IPTXFSTS_FILL(x) (x) 209 210 #define FSPI_RFDR 0x100 211 #define FSPI_TFDR 0x180 212 213 #define FSPI_LUT_BASE 0x200 214 #define FSPI_LUT_REG(idx) \ 215 (FSPI_LUT_BASE + (idx) * 0x10) 216 217 /* 218 * Commands 219 */ 220 #define FSPI_CMD_WRITE_ENABLE 0x06 221 #define FSPI_CMD_WRITE_DISABLE 0x04 222 #define FSPI_CMD_READ_IDENT 0x9F 223 #define FSPI_CMD_READ_STATUS 0x05 224 #define FSPI_CMD_WRITE_STATUS 0x01 225 #define FSPI_CMD_READ 0x03 226 #define FSPI_CMD_FAST_READ 0x0B 227 #define FSPI_CMD_PAGE_PROGRAM 0x02 228 #define FSPI_CMD_SECTOR_ERASE 0xD8 229 #define FSPI_CMD_BULK_ERASE 0xC7 230 #define FSPI_CMD_BLOCK_4K_ERASE 0x20 231 #define FSPI_CMD_BLOCK_32K_ERASE 0x52 232 #define FSPI_CMD_ENTER_4B_MODE 0xB7 233 #define FSPI_CMD_EXIT_4B_MODE 0xE9 234 #define FSPI_CMD_READ_CTRL_REG 0x35 235 #define FSPI_CMD_BANK_REG_WRITE 0x17 /* (spansion) */ 236 #define FSPI_CMD_SECTOR_ERASE_4B 0xDC 237 #define FSPI_CMD_BLOCK_4K_ERASE_4B 0x21 238 #define FSPI_CMD_BLOCK_32K_ERASE_4B 0x5C 239 #define FSPI_CMD_PAGE_PROGRAM_4B 0x12 240 #define FSPI_CMD_FAST_READ_4B 0x0C 241 242 243 244 /* register map end */ 245 246 /* Instruction set for the LUT register. */ 247 #define LUT_STOP 0x00 248 #define LUT_CMD 0x01 249 #define LUT_ADDR 0x02 250 #define LUT_CADDR_SDR 0x03 251 #define LUT_MODE 0x04 252 #define LUT_MODE2 0x05 253 #define LUT_MODE4 0x06 254 #define LUT_MODE8 0x07 255 #define LUT_NXP_WRITE 0x08 256 #define LUT_NXP_READ 0x09 257 #define LUT_LEARN_SDR 0x0A 258 #define LUT_DATSZ_SDR 0x0B 259 #define LUT_DUMMY 0x0C 260 #define LUT_DUMMY_RWDS_SDR 0x0D 261 #define LUT_JMP_ON_CS 0x1F 262 #define LUT_CMD_DDR 0x21 263 #define LUT_ADDR_DDR 0x22 264 #define LUT_CADDR_DDR 0x23 265 #define LUT_MODE_DDR 0x24 266 #define LUT_MODE2_DDR 0x25 267 #define LUT_MODE4_DDR 0x26 268 #define LUT_MODE8_DDR 0x27 269 #define LUT_WRITE_DDR 0x28 270 #define LUT_READ_DDR 0x29 271 #define LUT_LEARN_DDR 0x2A 272 #define LUT_DATSZ_DDR 0x2B 273 #define LUT_DUMMY_DDR 0x2C 274 #define LUT_DUMMY_RWDS_DDR 0x2D 275 276 /* LUT to operation mapping */ 277 #define LUT_FLASH_CMD_READ 0 278 #define LUT_FLASH_CMD_JEDECID 1 279 #define LUT_FLASH_CMD_STATUS_READ 2 280 #define LUT_FLASH_CMD_PAGE_PROGRAM 3 281 #define LUT_FLASH_CMD_WRITE_ENABLE 4 282 #define LUT_FLASH_CMD_WRITE_DISABLE 5 283 #define LUT_FLASH_CMD_SECTOR_ERASE 6 284 285 286 /* 287 * Calculate number of required PAD bits for LUT register. 288 * 289 * The pad stands for the number of IO lines [0:7]. 290 * For example, the octal read needs eight IO lines, 291 * so you should use LUT_PAD(8). This macro 292 * returns 3 i.e. use eight (2^3) IP lines for read. 293 */ 294 #define LUT_PAD(x) (fls(x) - 1) 295 296 /* 297 * Macro for constructing the LUT entries with the following 298 * register layout: 299 * 300 * --------------------------------------------------- 301 * | INSTR1 | PAD1 | OPRND1 | INSTR0 | PAD0 | OPRND0 | 302 * --------------------------------------------------- 303 */ 304 #define PAD_SHIFT 8 305 #define INSTR_SHIFT 10 306 #define OPRND_SHIFT 16 307 308 /* Macros for constructing the LUT register. */ 309 #define LUT_DEF(idx, ins, pad, opr) \ 310 ((((ins) << INSTR_SHIFT) | ((pad) << PAD_SHIFT) | \ 311 (opr)) << (((idx) % 2) * OPRND_SHIFT)) 312 313 #define POLL_TOUT 5000 314 #define NXP_FSPI_MAX_CHIPSELECT 4 315 #define NXP_FSPI_MIN_IOMAP SZ_4M 316 317 #define DCFG_RCWSR1 0x100 318 319 /* Access flash memory using IP bus only */ 320 #define FSPI_QUIRK_USE_IP_ONLY BIT(0) 321 322 #define FLASH_SECTORSIZE 512 323 324 #define TSTATE_STOPPED 0 325 #define TSTATE_STOPPING 1 326 #define TSTATE_RUNNING 2 327 328 #define STATUS_SRWD BIT(7) 329 #define STATUS_BP2 BIT(4) 330 #define STATUS_BP1 BIT(3) 331 #define STATUS_BP0 BIT(2) 332 #define STATUS_WEL BIT(1) 333 #define STATUS_WIP BIT(0) 334 335 336 #endif /* DEV_FLASH_FLEX_SPI_H_ */ 337