1 /*- 2 * Copyright (c) 2017-2018 Ruslan Bukin <br@bsdpad.com> 3 * All rights reserved. 4 * 5 * This software was developed by SRI International and the University of 6 * Cambridge Computer Laboratory under DARPA/AFRL contract FA8750-10-C-0237 7 * ("CTSRD"), as part of the DARPA CRASH research programme. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 */ 30 31 #ifndef _CQSPI_H_ 32 #define _CQSPI_H_ 33 34 #define CQSPI_CFG 0x00 /* QSPI Configuration */ 35 #define CFG_IDLE (1 << 31) 36 #define CFG_ENDMA (1 << 15) 37 #define CFG_IDLE (1 << 31) 38 #define CFG_BAUD_S 19 39 #define CFG_BAUD_M (0xf << CFG_BAUD_S) 40 #define CFG_BAUD2 (0 << CFG_BAUD_S) 41 #define CFG_BAUD4 (1 << CFG_BAUD_S) 42 #define CFG_BAUD6 (2 << CFG_BAUD_S) 43 #define CFG_BAUD8 (3 << CFG_BAUD_S) 44 #define CFG_BAUD10 (4 << CFG_BAUD_S) 45 #define CFG_BAUD12 (5 << CFG_BAUD_S) 46 #define CFG_BAUD14 (6 << CFG_BAUD_S) 47 #define CFG_BAUD16 (7 << CFG_BAUD_S) 48 #define CFG_BAUD18 (8 << CFG_BAUD_S) 49 #define CFG_BAUD20 (9 << CFG_BAUD_S) 50 #define CFG_BAUD22 (10 << CFG_BAUD_S) 51 #define CFG_BAUD24 (11 << CFG_BAUD_S) 52 #define CFG_BAUD26 (12 << CFG_BAUD_S) 53 #define CFG_BAUD28 (13 << CFG_BAUD_S) 54 #define CFG_BAUD30 (14 << CFG_BAUD_S) 55 #define CFG_BAUD32 (0xf << CFG_BAUD_S) 56 #define CFG_EN (1 << 0) 57 #define CQSPI_DEVRD 0x04 /* Device Read Instruction Configuration */ 58 #define DEVRD_DUMMYRDCLKS_S 24 59 #define DEVRD_ENMODEBITS (1 << 20) 60 #define DEVRD_DATA_WIDTH_S 16 61 #define DEVRD_DATA_WIDTH_QUAD (2 << DEVRD_DATA_WIDTH_S) 62 #define DEVRD_ADDR_WIDTH_S 12 63 #define DEVRD_ADDR_WIDTH_SINGLE (0 << DEVRD_ADDR_WIDTH_S) 64 #define DEVRD_INST_WIDTH_S 8 65 #define DEVRD_INST_WIDTH_SINGLE (0 << DEVRD_INST_WIDTH_S) 66 #define DEVRD_RDOPCODE_S 0 67 #define CQSPI_DEVWR 0x08 /* Device Write Instruction Configuration */ 68 #define DEVWR_DUMMYWRCLKS_S 24 69 #define DEVWR_WROPCODE_S 0 70 #define DEVWR_DATA_WIDTH_S 16 71 #define DEVWR_DATA_WIDTH_QUAD (2 << DEVWR_DATA_WIDTH_S) 72 #define DEVWR_ADDR_WIDTH_S 12 73 #define DEVWR_ADDR_WIDTH_SINGLE (0 << DEVWR_ADDR_WIDTH_S) 74 #define CQSPI_DELAY 0x0C /* QSPI Device Delay Register */ 75 #define DELAY_NSS_S 24 76 #define DELAY_BTWN_S 16 77 #define DELAY_AFTER_S 8 78 #define DELAY_INIT_S 0 79 #define CQSPI_RDDATACAP 0x10 /* Read Data Capture Register */ 80 #define RDDATACAP_DELAY_S 1 81 #define RDDATACAP_DELAY_M (0xf << RDDATACAP_DELAY_S) 82 #define CQSPI_DEVSZ 0x14 /* Device Size Configuration Register */ 83 #define DEVSZ_NUMADDRBYTES_S 0 84 #define DEVSZ_NUMADDRBYTES_M (0xf << DEVSZ_NUMADDRBYTES_S) 85 #define CQSPI_SRAMPART 0x18 /* SRAM Partition Configuration Register */ 86 #define CQSPI_INDADDRTRIG 0x1C /* Indirect AHB Address Trigger Register */ 87 #define CQSPI_DMAPER 0x20 /* DMA Peripheral Configuration Register */ 88 #define DMAPER_NUMSGLREQBYTES_S 0 89 #define DMAPER_NUMBURSTREQBYTES_S 8 90 #define DMAPER_NUMSGLREQBYTES_4 (2 << DMAPER_NUMSGLREQBYTES_S); 91 #define DMAPER_NUMBURSTREQBYTES_4 (2 << DMAPER_NUMBURSTREQBYTES_S); 92 #define CQSPI_REMAPADDR 0x24 /* Remap Address Register */ 93 #define CQSPI_MODEBIT 0x28 /* Mode Bit Configuration */ 94 #define CQSPI_SRAMFILL 0x2C /* SRAM Fill Register */ 95 #define CQSPI_TXTHRESH 0x30 /* TX Threshold Register */ 96 #define CQSPI_RXTHRESH 0x34 /* RX Threshold Register */ 97 #define CQSPI_IRQSTAT 0x40 /* Interrupt Status Register */ 98 #define CQSPI_IRQMASK 0x44 /* Interrupt Mask */ 99 #define IRQMASK_INDSRAMFULL (1 << 12) 100 #define IRQMASK_INDXFRLVL (1 << 6) 101 #define IRQMASK_INDOPDONE (1 << 2) 102 #define CQSPI_LOWWRPROT 0x50 /* Lower Write Protection */ 103 #define CQSPI_UPPWRPROT 0x54 /* Upper Write Protection */ 104 #define CQSPI_WRPROT 0x58 /* Write Protection Control Register */ 105 #define CQSPI_INDRD 0x60 /* Indirect Read Transfer Control Register */ 106 #define INDRD_IND_OPS_DONE_STATUS (1 << 5) 107 #define INDRD_START (1 << 0) 108 #define CQSPI_INDRDWATER 0x64 /* Indirect Read Transfer Watermark Register */ 109 #define CQSPI_INDRDSTADDR 0x68 /* Indirect Read Transfer Start Address Register */ 110 #define CQSPI_INDRDCNT 0x6C /* Indirect Read Transfer Number Bytes Register */ 111 #define CQSPI_INDWR 0x70 /* Indirect Write Transfer Control Register */ 112 #define CQSPI_INDWRWATER 0x74 /* Indirect Write Transfer Watermark Register */ 113 #define CQSPI_INDWRSTADDR 0x78 /* Indirect Write Transfer Start Address Register */ 114 #define CQSPI_INDWRCNT 0x7C /* Indirect Write Transfer Number Bytes Register */ 115 #define CQSPI_FLASHCMD 0x90 /* Flash Command Control Register */ 116 #define FLASHCMD_NUMADDRBYTES_S 16 117 #define FLASHCMD_NUMRDDATABYTES_S 20 118 #define FLASHCMD_NUMRDDATABYTES_M (0x7 << FLASHCMD_NUMRDDATABYTES_S) 119 #define FLASHCMD_ENCMDADDR (1 << 19) 120 #define FLASHCMD_ENRDDATA (1 << 23) 121 #define FLASHCMD_CMDOPCODE_S 24 122 #define FLASHCMD_CMDOPCODE_M (0xff << FLASHCMD_CMDOPCODE_S) 123 #define FLASHCMD_CMDEXECSTAT (1 << 1) /* Command execution in progress. */ 124 #define FLASHCMD_EXECCMD (1 << 0) /* Execute the command. */ 125 #define CQSPI_FLASHCMDADDR 0x94 /* Flash Command Address Registers */ 126 #define CQSPI_FLASHCMDRDDATALO 0xA0 /* Flash Command Read Data Register (Lower) */ 127 #define CQSPI_FLASHCMDRDDATAUP 0xA4 /* Flash Command Read Data Register (Upper) */ 128 #define CQSPI_FLASHCMDWRDATALO 0xA8 /* Flash Command Write Data Register (Lower) */ 129 #define CQSPI_FLASHCMDWRDATAUP 0xAC /* Flash Command Write Data Register (Upper) */ 130 #define CQSPI_MODULEID 0xFC /* Module ID Register */ 131 132 #endif /* !_CQSPI_H_ */ 133