1 /*- 2 * SPDX-License-Identifier: BSD-4-Clause 3 * 4 * Copyright (C) 2003 5 * Hidetoshi Shimokawa. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * 18 * This product includes software developed by Hidetoshi Shimokawa. 19 * 20 * 4. Neither the name of the author nor the names of its contributors 21 * may be used to endorse or promote products derived from this software 22 * without specific prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 25 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 27 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 30 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 31 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 32 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 33 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 34 * SUCH DAMAGE. 35 * 36 */ 37 38 /* 39 * IEEE 1394a 40 * Figure 5B - 1 41 */ 42 struct phyreg_base { 43 #if BYTE_ORDER == BIG_ENDIAN 44 uint8_t phy_id:6, 45 r:1, 46 cps:1; 47 uint8_t rhb:1, 48 ibr:1, 49 gap_count:6; 50 uint8_t extended:3, 51 num_ports:5; 52 uint8_t phy_speed:3, 53 :1, 54 delay:4; 55 uint8_t lctrl:1, 56 c:1, 57 jitter:3, 58 pwr_class:3; 59 uint8_t wdie:1, 60 isbr:1, 61 ctoi:1, 62 cpsi:1, 63 stoi:1, 64 pei:1, 65 eaa:1, 66 emc:1; 67 uint8_t legacy_spd:3, 68 blink:1, 69 bridge:2, 70 :2; 71 uint8_t page_select:3, 72 :1, 73 port_select:4; 74 #else 75 uint8_t cps:1, 76 r:1, 77 phy_id:6; 78 uint8_t gap_count:6, 79 ibr:1, 80 rhb:1; 81 uint8_t num_ports:5, 82 extended:3; 83 uint8_t delay:4, 84 :1, 85 phy_speed:3; 86 uint8_t pwr_class:3, 87 jitter:3, 88 c:1, 89 lctrl:1; 90 uint8_t emc:1, 91 eaa:1, 92 pei:1, 93 stoi:1, 94 cpsi:1, 95 ctoi:1, 96 isbr:1, 97 wdie:1; 98 uint8_t :2, 99 bridge:2, 100 blink:1, 101 legacy_spd:3; 102 uint8_t port_select:4, 103 :1, 104 page_select:3; 105 #endif 106 }; 107 108 /* 109 * IEEE 1394a 110 * Figure 5B - 2 111 */ 112 struct phyreg_page0 { 113 #if BYTE_ORDER == BIG_ENDIAN 114 uint8_t astat:2, 115 bstat:2, 116 ch:1, 117 con:1, 118 rxok:1, 119 dis:1; 120 uint8_t negotiated_speed:3, 121 pie:1, 122 fault:1, 123 stanby_fault:1, 124 disscrm:1, 125 b_only:1; 126 uint8_t dc_connected:1, 127 max_port_speed:3, 128 lpp:1, 129 cable_speed:3; 130 uint8_t connection_unreliable:1, 131 :3, 132 beta_mode:1, 133 :3; 134 uint8_t port_error; 135 uint8_t :5, 136 loop_disable:1, 137 in_standby:1, 138 hard_disable:1; 139 uint8_t :8; 140 uint8_t :8; 141 #else 142 uint8_t dis:1, 143 rxok:1, 144 con:1, 145 ch:1, 146 bstat:2, 147 astat:2; 148 uint8_t b_only:1, 149 disscrm:1, 150 stanby_fault:1, 151 fault:1, 152 pie:1, 153 negotiated_speed:3; 154 uint8_t cable_speed:3, 155 lpp:1, 156 max_port_speed:3, 157 dc_connected:1; 158 uint8_t :3, 159 beta_mode:1, 160 :3, 161 connection_unreliable:1; 162 uint8_t port_error; 163 uint8_t hard_disable:1, 164 in_standby:1, 165 loop_disable:1, 166 :5; 167 uint8_t :8; 168 uint8_t :8; 169 #endif 170 }; 171 172 /* 173 * IEEE 1394a 174 * Figure 5B - 3 175 */ 176 struct phyreg_page1 { 177 uint8_t compliance; 178 uint8_t :8; 179 uint8_t vendor_id[3]; 180 uint8_t product_id[3]; 181 }; 182