1 /* 2 * Copyright (c) 1998-2001 Katsushi Kobayashi and Hidetoshi Shimokawa 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the acknowledgement as bellow: 15 * 16 * This product includes software developed by K. Kobayashi and H. Shimokawa 17 * 18 * 4. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 23 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 24 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 25 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 26 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 27 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 28 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 29 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 30 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 * POSSIBILITY OF SUCH DAMAGE. 32 * 33 * $FreeBSD$ 34 * 35 */ 36 #define PCI_CBMEM 0x10 37 38 #define FW_VENDORID_NEC 0x1033 39 #define FW_VENDORID_TI 0x104c 40 #define FW_VENDORID_SONY 0x104d 41 #define FW_VENDORID_VIA 0x1106 42 #define FW_VENDORID_RICOH 0x1180 43 #define FW_VENDORID_APPLE 0x106b 44 #define FW_VENDORID_LUCENT 0x11c1 45 46 #define FW_DEVICE_UPD861 (0x0063 << 16) 47 #define FW_DEVICE_UPD871 (0x00ce << 16) 48 #define FW_DEVICE_TITSB22 (0x8009 << 16) 49 #define FW_DEVICE_TITSB23 (0x8019 << 16) 50 #define FW_DEVICE_TITSB26 (0x8020 << 16) 51 #define FW_DEVICE_TITSB43 (0x8021 << 16) 52 #define FW_DEVICE_TITSB43A (0x8023 << 16) 53 #define FW_DEVICE_TIPCI4450 (0x8011 << 16) 54 #define FW_DEVICE_TIPCI4410A (0x8017 << 16) 55 #define FW_DEVICE_CX3022 (0x8039 << 16) 56 #define FW_DEVICE_VT6306 (0x3044 << 16) 57 #define FW_DEVICE_R5C552 (0x0552 << 16) 58 #define FW_DEVICE_PANGEA (0x0030 << 16) 59 #define FW_DEVICE_UNINORTH (0x0031 << 16) 60 #define FW_DEVICE_FW322 (0x5811 << 16) 61 62 #define PCI_INTERFACE_OHCI 0x10 63 64 #define FW_OHCI_BASE_REG 0x10 65 66 #define OHCI_DMA_ITCH 0x20 67 #define OHCI_DMA_IRCH 0x20 68 69 #define OHCI_MAX_DMA_CH (0x4 + OHCI_DMA_ITCH + OHCI_DMA_IRCH) 70 71 72 typedef volatile u_int32_t fwohcireg_t; 73 74 struct fwohcidb { 75 union { 76 struct { 77 volatile u_int32_t reqcount:16, 78 control:16; 79 volatile u_int32_t addr; 80 volatile u_int32_t depend; 81 volatile u_int32_t count:16, 82 status:16; 83 } desc; 84 volatile u_int32_t immed[4]; 85 } db; 86 #define OHCI_OUTPUT_MORE (0 << 12) 87 #define OHCI_OUTPUT_LAST (1 << 12) 88 #define OHCI_INPUT_MORE (2 << 12) 89 #define OHCI_INPUT_LAST (3 << 12) 90 #define OHCI_STORE_QUAD (4 << 12) 91 #define OHCI_LOAD_QUAD (5 << 12) 92 #define OHCI_NOP (6 << 12) 93 #define OHCI_STOP (7 << 12) 94 #define OHCI_STORE (8 << 12) 95 #define OHCI_CMD_MASK (0xf << 12) 96 97 #define OHCI_UPDATE (1 << 11) 98 99 #define OHCI_KEY_ST0 (0 << 8) 100 #define OHCI_KEY_ST1 (1 << 8) 101 #define OHCI_KEY_ST2 (2 << 8) 102 #define OHCI_KEY_ST3 (3 << 8) 103 #define OHCI_KEY_REGS (5 << 8) 104 #define OHCI_KEY_SYS (6 << 8) 105 #define OHCI_KEY_DEVICE (7 << 8) 106 #define OHCI_KEY_MASK (7 << 8) 107 108 #define OHCI_INTERRUPT_NEVER (0 << 4) 109 #define OHCI_INTERRUPT_TRUE (1 << 4) 110 #define OHCI_INTERRUPT_FALSE (2 << 4) 111 #define OHCI_INTERRUPT_ALWAYS (3 << 4) 112 113 #define OHCI_BRANCH_NEVER (0 << 2) 114 #define OHCI_BRANCH_TRUE (1 << 2) 115 #define OHCI_BRANCH_FALSE (2 << 2) 116 #define OHCI_BRANCH_ALWAYS (3 << 2) 117 #define OHCI_BRANCH_MASK (3 << 2) 118 119 #define OHCI_WAIT_NEVER (0) 120 #define OHCI_WAIT_TRUE (1) 121 #define OHCI_WAIT_FALSE (2) 122 #define OHCI_WAIT_ALWAYS (3) 123 }; 124 125 #define OHCI_SPD_S100 0x4 126 #define OHCI_SPD_S200 0x1 127 #define OHCI_SPD_S400 0x2 128 129 130 #define FWOHCIEV_NOSTAT 0 131 #define FWOHCIEV_LONGP 2 132 #define FWOHCIEV_MISSACK 3 133 #define FWOHCIEV_UNDRRUN 4 134 #define FWOHCIEV_OVRRUN 5 135 #define FWOHCIEV_DESCERR 6 136 #define FWOHCIEV_DTRDERR 7 137 #define FWOHCIEV_DTWRERR 8 138 #define FWOHCIEV_BUSRST 9 139 #define FWOHCIEV_TIMEOUT 0xa 140 #define FWOHCIEV_TCODERR 0xb 141 #define FWOHCIEV_UNKNOWN 0xe 142 #define FWOHCIEV_FLUSHED 0xf 143 #define FWOHCIEV_ACKCOMPL 0x11 144 #define FWOHCIEV_ACKPEND 0x12 145 #define FWOHCIEV_ACKBSX 0x14 146 #define FWOHCIEV_ACKBSA 0x15 147 #define FWOHCIEV_ACKBSB 0x16 148 #define FWOHCIEV_ACKTARD 0x1b 149 #define FWOHCIEV_ACKDERR 0x1d 150 #define FWOHCIEV_ACKTERR 0x1e 151 152 #define FWOHCIEV_MASK 0x1f 153 154 struct ohci_registers { 155 fwohcireg_t ver; /* Version No. 0x0 */ 156 fwohcireg_t guid; /* GUID_ROM No. 0x4 */ 157 fwohcireg_t retry; /* AT retries 0x8 */ 158 #define FWOHCI_RETRY 0x8 159 fwohcireg_t csr_data; /* CSR data 0xc */ 160 fwohcireg_t csr_cmp; /* CSR compare 0x10 */ 161 fwohcireg_t csr_cntl; /* CSR compare 0x14 */ 162 fwohcireg_t rom_hdr; /* config ROM ptr. 0x18 */ 163 fwohcireg_t bus_id; /* BUS_ID 0x1c */ 164 fwohcireg_t bus_opt; /* BUS option 0x20 */ 165 #define FWOHCIGUID_H 0x24 166 #define FWOHCIGUID_L 0x28 167 fwohcireg_t guid_hi; /* GUID hi 0x24 */ 168 fwohcireg_t guid_lo; /* GUID lo 0x28 */ 169 fwohcireg_t dummy0[2]; /* dummy 0x2c-0x30 */ 170 fwohcireg_t config_rom; /* config ROM map 0x34 */ 171 fwohcireg_t post_wr_lo; /* post write addr lo 0x38 */ 172 fwohcireg_t post_wr_hi; /* post write addr hi 0x3c */ 173 fwohcireg_t vender; /* vender ID 0x40 */ 174 fwohcireg_t dummy1[3]; /* dummy 0x44-0x4c */ 175 fwohcireg_t hcc_cntl_set; /* HCC control set 0x50 */ 176 fwohcireg_t hcc_cntl_clr; /* HCC control clr 0x54 */ 177 #define OHCI_HCC_BIBIV (1 << 31) /* BIBimage Valid */ 178 #define OHCI_HCC_BIGEND (1 << 30) /* noByteSwapData */ 179 #define OHCI_HCC_PRPHY (1 << 23) /* programPhyEnable */ 180 #define OHCI_HCC_PHYEN (1 << 22) /* aPhyEnhanceEnable */ 181 #define OHCI_HCC_LPS (1 << 19) /* LPS */ 182 #define OHCI_HCC_POSTWR (1 << 18) /* postedWriteEnable */ 183 #define OHCI_HCC_LINKEN (1 << 17) /* linkEnable */ 184 #define OHCI_HCC_RESET (1 << 16) /* softReset */ 185 fwohcireg_t dummy2[2]; /* dummy 0x58-0x5c */ 186 fwohcireg_t dummy3[1]; /* dummy 0x60 */ 187 fwohcireg_t sid_buf; /* self id buffer 0x64 */ 188 fwohcireg_t sid_cnt; /* self id count 0x68 */ 189 fwohcireg_t dummy4[1]; /* dummy 0x6c */ 190 fwohcireg_t ir_mask_hi_set; /* ir mask hi set 0x70 */ 191 fwohcireg_t ir_mask_hi_clr; /* ir mask hi set 0x74 */ 192 fwohcireg_t ir_mask_lo_set; /* ir mask hi set 0x78 */ 193 fwohcireg_t ir_mask_lo_clr; /* ir mask hi set 0x7c */ 194 #define FWOHCI_INTSTAT 0x80 195 #define FWOHCI_INTSTATCLR 0x84 196 #define FWOHCI_INTMASK 0x88 197 #define FWOHCI_INTMASKCLR 0x8c 198 fwohcireg_t int_stat; /* 0x80 */ 199 fwohcireg_t int_clear; /* 0x84 */ 200 fwohcireg_t int_mask; /* 0x88 */ 201 fwohcireg_t int_mask_clear; /* 0x8c */ 202 fwohcireg_t it_int_stat; /* 0x90 */ 203 fwohcireg_t it_int_clear; /* 0x94 */ 204 fwohcireg_t it_int_mask; /* 0x98 */ 205 fwohcireg_t it_mask_clear; /* 0x9c */ 206 fwohcireg_t ir_int_stat; /* 0xa0 */ 207 fwohcireg_t ir_int_clear; /* 0xa4 */ 208 fwohcireg_t ir_int_mask; /* 0xa8 */ 209 fwohcireg_t ir_mask_clear; /* 0xac */ 210 fwohcireg_t dummy5[11]; /* dummy 0xb0-d8 */ 211 fwohcireg_t fairness; /* fairness control 0xdc */ 212 fwohcireg_t link_cntl; /* Chip control 0xe0*/ 213 fwohcireg_t link_cntl_clr; /* Chip control clear 0xe4*/ 214 #define FWOHCI_NODEID 0xe8 215 fwohcireg_t node; /* Node ID 0xe8 */ 216 #define OHCI_NODE_VALID (1 << 31) 217 #define OHCI_NODE_ROOT (1 << 30) 218 219 #define OHCI_ASYSRCBUS 1 220 221 fwohcireg_t phy_access; /* PHY cntl 0xec */ 222 #define PHYDEV_RDDONE (1<<31) 223 #define PHYDEV_RDCMD (1<<15) 224 #define PHYDEV_WRCMD (1<<14) 225 #define PHYDEV_REGADDR 8 226 #define PHYDEV_WRDATA 0 227 #define PHYDEV_RDADDR 24 228 #define PHYDEV_RDDATA 16 229 230 fwohcireg_t cycle_timer; /* Cycle Timer 0xf0 */ 231 fwohcireg_t dummy6[3]; /* dummy 0xf4-fc */ 232 fwohcireg_t areq_hi; /* Async req. filter hi 0x100 */ 233 fwohcireg_t areq_hi_clr; /* Async req. filter hi 0x104 */ 234 fwohcireg_t areq_lo; /* Async req. filter lo 0x108 */ 235 fwohcireg_t areq_lo_clr; /* Async req. filter lo 0x10c */ 236 fwohcireg_t preq_hi; /* Async req. filter hi 0x110 */ 237 fwohcireg_t preq_hi_clr; /* Async req. filter hi 0x114 */ 238 fwohcireg_t preq_lo; /* Async req. filter lo 0x118 */ 239 fwohcireg_t preq_lo_clr; /* Async req. filter lo 0x11c */ 240 241 fwohcireg_t pys_upper; /* Physical Upper bound 0x120 */ 242 243 fwohcireg_t dummy7[23]; /* dummy 0x124-0x17c */ 244 245 struct ohci_dma{ 246 fwohcireg_t cntl; 247 248 #define OHCI_CNTL_CYCMATCH_S (0x1 << 31) 249 250 #define OHCI_CNTL_BUFFIL (0x1 << 31) 251 #define OHCI_CNTL_ISOHDR (0x1 << 30) 252 #define OHCI_CNTL_CYCMATCH_R (0x1 << 29) 253 #define OHCI_CNTL_MULTICH (0x1 << 28) 254 255 #define OHCI_CNTL_DMA_RUN (0x1 << 15) 256 #define OHCI_CNTL_DMA_WAKE (0x1 << 12) 257 #define OHCI_CNTL_DMA_DEAD (0x1 << 11) 258 #define OHCI_CNTL_DMA_ACTIVE (0x1 << 10) 259 #define OHCI_CNTL_DMA_BT (0x1 << 8) 260 #define OHCI_CNTL_DMA_BAD (0x1 << 7) 261 #define OHCI_CNTL_DMA_STAT (0xff) 262 263 fwohcireg_t cntl_clr; 264 fwohcireg_t dummy0; 265 fwohcireg_t cmd; 266 fwohcireg_t match; 267 fwohcireg_t dummy1; 268 fwohcireg_t dummy2; 269 fwohcireg_t dummy3; 270 }; 271 /* 0x180, 0x184, 0x188, 0x18c */ 272 /* 0x190, 0x194, 0x198, 0x19c */ 273 /* 0x1a0, 0x1a4, 0x1a8, 0x1ac */ 274 /* 0x1b0, 0x1b4, 0x1b8, 0x1bc */ 275 /* 0x1c0, 0x1c4, 0x1c8, 0x1cc */ 276 /* 0x1d0, 0x1d4, 0x1d8, 0x1dc */ 277 /* 0x1e0, 0x1e4, 0x1e8, 0x1ec */ 278 /* 0x1f0, 0x1f4, 0x1f8, 0x1fc */ 279 struct ohci_dma dma_ch[0x4]; 280 281 /* 0x200, 0x204, 0x208, 0x20c */ 282 /* 0x210, 0x204, 0x208, 0x20c */ 283 struct ohci_itdma{ 284 fwohcireg_t cntl; 285 fwohcireg_t cntl_clr; 286 fwohcireg_t dummy0; 287 fwohcireg_t cmd; 288 }; 289 struct ohci_itdma dma_itch[0x20]; 290 291 /* 0x400, 0x404, 0x408, 0x40c */ 292 /* 0x410, 0x404, 0x408, 0x40c */ 293 294 struct ohci_dma dma_irch[0x20]; 295 }; 296 297 struct fwohcidb_tr{ 298 STAILQ_ENTRY(fwohcidb_tr) link; 299 struct fw_xfer *xfer; 300 volatile struct fwohcidb *db; 301 caddr_t buf; 302 caddr_t dummy; 303 int dbcnt; 304 }; 305 306 /* 307 * OHCI info structure. 308 */ 309 struct fwohci_txpkthdr{ 310 union{ 311 u_int32_t ld[4]; 312 struct { 313 u_int32_t res3:4, 314 tcode:4, 315 res2:8, 316 spd:3, 317 res1:13; 318 }common; 319 struct { 320 u_int32_t res3:4, 321 tcode:4, 322 tlrt:8, 323 spd:3, 324 res2:4, 325 srcbus:1, 326 res1:8; 327 u_int32_t res4:16, 328 dst:16; 329 }asycomm; 330 struct { 331 u_int32_t sy:4, 332 tcode:4, 333 chtag:8, 334 spd:3, 335 res1:13; 336 u_int32_t res2:16, 337 len:16; 338 }stream; 339 }mode; 340 }; 341 struct fwohci_trailer{ 342 u_int32_t time:16, 343 stat:16; 344 }; 345 346 #define OHCI_CNTL_CYCSRC (0x1 << 22) 347 #define OHCI_CNTL_CYCMTR (0x1 << 21) 348 #define OHCI_CNTL_CYCTIMER (0x1 << 20) 349 #define OHCI_CNTL_PHYPKT (0x1 << 10) 350 #define OHCI_CNTL_SID (0x1 << 9) 351 352 #define OHCI_INT_DMA_ATRQ (0x1 << 0) 353 #define OHCI_INT_DMA_ATRS (0x1 << 1) 354 #define OHCI_INT_DMA_ARRQ (0x1 << 2) 355 #define OHCI_INT_DMA_ARRS (0x1 << 3) 356 #define OHCI_INT_DMA_PRRQ (0x1 << 4) 357 #define OHCI_INT_DMA_PRRS (0x1 << 5) 358 #define OHCI_INT_DMA_IT (0x1 << 6) 359 #define OHCI_INT_DMA_IR (0x1 << 7) 360 #define OHCI_INT_PW_ERR (0x1 << 8) 361 #define OHCI_INT_LR_ERR (0x1 << 9) 362 363 #define OHCI_INT_PHY_SID (0x1 << 16) 364 #define OHCI_INT_PHY_BUS_R (0x1 << 17) 365 366 #define OHCI_INT_REG_FAIL (0x1 << 18) 367 368 #define OHCI_INT_PHY_INT (0x1 << 19) 369 #define OHCI_INT_CYC_START (0x1 << 20) 370 #define OHCI_INT_CYC_64SECOND (0x1 << 21) 371 #define OHCI_INT_CYC_LOST (0x1 << 22) 372 #define OHCI_INT_CYC_ERR (0x1 << 23) 373 374 #define OHCI_INT_ERR (0x1 << 24) 375 #define OHCI_INT_CYC_LONG (0x1 << 25) 376 #define OHCI_INT_PHY_REG (0x1 << 26) 377 378 #define OHCI_INT_EN (0x1 << 31) 379 380 #define IP_CHANNELS 0x0234 381 #define FWOHCI_MAXREC 2048 382 383 #define OHCI_ISORA 0x02 384 #define OHCI_ISORB 0x04 385 386 #define FWOHCITCODE_PHY 0xe 387