1 /* 2 * Copyright (c) 2003 Hidetoshi Shimokawa 3 * Copyright (c) 1998-2002 Katsushi Kobayashi and Hidetoshi Shimokawa 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the acknowledgement as bellow: 16 * 17 * This product includes software developed by K. Kobayashi and H. Shimokawa 18 * 19 * 4. The name of the author may not be used to endorse or promote products 20 * derived from this software without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 24 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 25 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 26 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 27 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 28 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 29 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 30 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 31 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 32 * POSSIBILITY OF SUCH DAMAGE. 33 * 34 * $FreeBSD$ 35 * 36 */ 37 #define PCI_CBMEM PCIR_BAR(0) 38 39 #define FW_VENDORID_NATSEMI 0x100B 40 #define FW_VENDORID_NEC 0x1033 41 #define FW_VENDORID_SIS 0x1039 42 #define FW_VENDORID_TI 0x104c 43 #define FW_VENDORID_SONY 0x104d 44 #define FW_VENDORID_VIA 0x1106 45 #define FW_VENDORID_RICOH 0x1180 46 #define FW_VENDORID_APPLE 0x106b 47 #define FW_VENDORID_LUCENT 0x11c1 48 #define FW_VENDORID_INTEL 0x8086 49 #define FW_VENDORID_ADAPTEC 0x9004 50 51 #define FW_DEVICE_CS4210 (0x000f << 16) 52 #define FW_DEVICE_UPD861 (0x0063 << 16) 53 #define FW_DEVICE_UPD871 (0x00ce << 16) 54 #define FW_DEVICE_UPD72870 (0x00cd << 16) 55 #define FW_DEVICE_UPD72873 (0x00e7 << 16) 56 #define FW_DEVICE_UPD72874 (0x00f2 << 16) 57 #define FW_DEVICE_TITSB22 (0x8009 << 16) 58 #define FW_DEVICE_TITSB23 (0x8019 << 16) 59 #define FW_DEVICE_TITSB26 (0x8020 << 16) 60 #define FW_DEVICE_TITSB43 (0x8021 << 16) 61 #define FW_DEVICE_TITSB43A (0x8023 << 16) 62 #define FW_DEVICE_TITSB43AB23 (0x8024 << 16) 63 #define FW_DEVICE_TITSB82AA2 (0x8025 << 16) 64 #define FW_DEVICE_TITSB43AB21 (0x8026 << 16) 65 #define FW_DEVICE_TIPCI4410A (0x8017 << 16) 66 #define FW_DEVICE_TIPCI4450 (0x8011 << 16) 67 #define FW_DEVICE_TIPCI4451 (0x8027 << 16) 68 #define FW_DEVICE_CX3022 (0x8039 << 16) 69 #define FW_DEVICE_VT6306 (0x3044 << 16) 70 #define FW_DEVICE_R5C551 (0x0551 << 16) 71 #define FW_DEVICE_R5C552 (0x0552 << 16) 72 #define FW_DEVICE_PANGEA (0x0030 << 16) 73 #define FW_DEVICE_UNINORTH (0x0031 << 16) 74 #define FW_DEVICE_AIC5800 (0x5800 << 16) 75 #define FW_DEVICE_FW322 (0x5811 << 16) 76 #define FW_DEVICE_7007 (0x7007 << 16) 77 #define FW_DEVICE_82372FB (0x7605 << 16) 78 79 #define PCI_INTERFACE_OHCI 0x10 80 81 #define FW_OHCI_BASE_REG 0x10 82 83 #define OHCI_DMA_ITCH 0x20 84 #define OHCI_DMA_IRCH 0x20 85 86 #define OHCI_MAX_DMA_CH (0x4 + OHCI_DMA_ITCH + OHCI_DMA_IRCH) 87 88 89 typedef uint32_t fwohcireg_t; 90 91 /* for PCI */ 92 #if BYTE_ORDER == BIG_ENDIAN 93 #define FWOHCI_DMA_WRITE(x, y) ((x) = htole32(y)) 94 #define FWOHCI_DMA_READ(x) le32toh(x) 95 #define FWOHCI_DMA_SET(x, y) ((x) |= htole32(y)) 96 #define FWOHCI_DMA_CLEAR(x, y) ((x) &= htole32(~(y))) 97 #else 98 #define FWOHCI_DMA_WRITE(x, y) ((x) = (y)) 99 #define FWOHCI_DMA_READ(x) (x) 100 #define FWOHCI_DMA_SET(x, y) ((x) |= (y)) 101 #define FWOHCI_DMA_CLEAR(x, y) ((x) &= ~(y)) 102 #endif 103 104 struct fwohcidb { 105 union { 106 struct { 107 uint32_t cmd; 108 uint32_t addr; 109 uint32_t depend; 110 uint32_t res; 111 } desc; 112 uint32_t immed[4]; 113 } db; 114 #define OHCI_STATUS_SHIFT 16 115 #define OHCI_COUNT_MASK 0xffff 116 #define OHCI_OUTPUT_MORE (0 << 28) 117 #define OHCI_OUTPUT_LAST (1 << 28) 118 #define OHCI_INPUT_MORE (2 << 28) 119 #define OHCI_INPUT_LAST (3 << 28) 120 #define OHCI_STORE_QUAD (4 << 28) 121 #define OHCI_LOAD_QUAD (5 << 28) 122 #define OHCI_NOP (6 << 28) 123 #define OHCI_STOP (7 << 28) 124 #define OHCI_STORE (8 << 28) 125 #define OHCI_CMD_MASK (0xf << 28) 126 127 #define OHCI_UPDATE (1 << 27) 128 129 #define OHCI_KEY_ST0 (0 << 24) 130 #define OHCI_KEY_ST1 (1 << 24) 131 #define OHCI_KEY_ST2 (2 << 24) 132 #define OHCI_KEY_ST3 (3 << 24) 133 #define OHCI_KEY_REGS (5 << 24) 134 #define OHCI_KEY_SYS (6 << 24) 135 #define OHCI_KEY_DEVICE (7 << 24) 136 #define OHCI_KEY_MASK (7 << 24) 137 138 #define OHCI_INTERRUPT_NEVER (0 << 20) 139 #define OHCI_INTERRUPT_TRUE (1 << 20) 140 #define OHCI_INTERRUPT_FALSE (2 << 20) 141 #define OHCI_INTERRUPT_ALWAYS (3 << 20) 142 143 #define OHCI_BRANCH_NEVER (0 << 18) 144 #define OHCI_BRANCH_TRUE (1 << 18) 145 #define OHCI_BRANCH_FALSE (2 << 18) 146 #define OHCI_BRANCH_ALWAYS (3 << 18) 147 #define OHCI_BRANCH_MASK (3 << 18) 148 149 #define OHCI_WAIT_NEVER (0 << 16) 150 #define OHCI_WAIT_TRUE (1 << 16) 151 #define OHCI_WAIT_FALSE (2 << 16) 152 #define OHCI_WAIT_ALWAYS (3 << 16) 153 }; 154 155 #define OHCI_SPD_S100 0x4 156 #define OHCI_SPD_S200 0x1 157 #define OHCI_SPD_S400 0x2 158 159 160 #define FWOHCIEV_NOSTAT 0 161 #define FWOHCIEV_LONGP 2 162 #define FWOHCIEV_MISSACK 3 163 #define FWOHCIEV_UNDRRUN 4 164 #define FWOHCIEV_OVRRUN 5 165 #define FWOHCIEV_DESCERR 6 166 #define FWOHCIEV_DTRDERR 7 167 #define FWOHCIEV_DTWRERR 8 168 #define FWOHCIEV_BUSRST 9 169 #define FWOHCIEV_TIMEOUT 0xa 170 #define FWOHCIEV_TCODERR 0xb 171 #define FWOHCIEV_UNKNOWN 0xe 172 #define FWOHCIEV_FLUSHED 0xf 173 #define FWOHCIEV_ACKCOMPL 0x11 174 #define FWOHCIEV_ACKPEND 0x12 175 #define FWOHCIEV_ACKBSX 0x14 176 #define FWOHCIEV_ACKBSA 0x15 177 #define FWOHCIEV_ACKBSB 0x16 178 #define FWOHCIEV_ACKTARD 0x1b 179 #define FWOHCIEV_ACKDERR 0x1d 180 #define FWOHCIEV_ACKTERR 0x1e 181 182 #define FWOHCIEV_MASK 0x1f 183 184 struct ohci_dma{ 185 fwohcireg_t cntl; 186 187 #define OHCI_CNTL_CYCMATCH_S (0x1 << 31) 188 189 #define OHCI_CNTL_BUFFIL (0x1 << 31) 190 #define OHCI_CNTL_ISOHDR (0x1 << 30) 191 #define OHCI_CNTL_CYCMATCH_R (0x1 << 29) 192 #define OHCI_CNTL_MULTICH (0x1 << 28) 193 194 #define OHCI_CNTL_DMA_RUN (0x1 << 15) 195 #define OHCI_CNTL_DMA_WAKE (0x1 << 12) 196 #define OHCI_CNTL_DMA_DEAD (0x1 << 11) 197 #define OHCI_CNTL_DMA_ACTIVE (0x1 << 10) 198 #define OHCI_CNTL_DMA_BT (0x1 << 8) 199 #define OHCI_CNTL_DMA_BAD (0x1 << 7) 200 #define OHCI_CNTL_DMA_STAT (0xff) 201 202 fwohcireg_t cntl_clr; 203 fwohcireg_t dummy0; 204 fwohcireg_t cmd; 205 fwohcireg_t match; 206 fwohcireg_t dummy1; 207 fwohcireg_t dummy2; 208 fwohcireg_t dummy3; 209 }; 210 211 struct ohci_itdma{ 212 fwohcireg_t cntl; 213 fwohcireg_t cntl_clr; 214 fwohcireg_t dummy0; 215 fwohcireg_t cmd; 216 }; 217 218 struct ohci_registers { 219 fwohcireg_t ver; /* Version No. 0x0 */ 220 fwohcireg_t guid; /* GUID_ROM No. 0x4 */ 221 fwohcireg_t retry; /* AT retries 0x8 */ 222 #define FWOHCI_RETRY 0x8 223 fwohcireg_t csr_data; /* CSR data 0xc */ 224 fwohcireg_t csr_cmp; /* CSR compare 0x10 */ 225 fwohcireg_t csr_cntl; /* CSR compare 0x14 */ 226 fwohcireg_t rom_hdr; /* config ROM ptr. 0x18 */ 227 fwohcireg_t bus_id; /* BUS_ID 0x1c */ 228 fwohcireg_t bus_opt; /* BUS option 0x20 */ 229 #define FWOHCIGUID_H 0x24 230 #define FWOHCIGUID_L 0x28 231 fwohcireg_t guid_hi; /* GUID hi 0x24 */ 232 fwohcireg_t guid_lo; /* GUID lo 0x28 */ 233 fwohcireg_t dummy0[2]; /* dummy 0x2c-0x30 */ 234 fwohcireg_t config_rom; /* config ROM map 0x34 */ 235 fwohcireg_t post_wr_lo; /* post write addr lo 0x38 */ 236 fwohcireg_t post_wr_hi; /* post write addr hi 0x3c */ 237 fwohcireg_t vender; /* vender ID 0x40 */ 238 fwohcireg_t dummy1[3]; /* dummy 0x44-0x4c */ 239 fwohcireg_t hcc_cntl_set; /* HCC control set 0x50 */ 240 fwohcireg_t hcc_cntl_clr; /* HCC control clr 0x54 */ 241 #define OHCI_HCC_BIBIV (1 << 31) /* BIBimage Valid */ 242 #define OHCI_HCC_BIGEND (1 << 30) /* noByteSwapData */ 243 #define OHCI_HCC_PRPHY (1 << 23) /* programPhyEnable */ 244 #define OHCI_HCC_PHYEN (1 << 22) /* aPhyEnhanceEnable */ 245 #define OHCI_HCC_LPS (1 << 19) /* LPS */ 246 #define OHCI_HCC_POSTWR (1 << 18) /* postedWriteEnable */ 247 #define OHCI_HCC_LINKEN (1 << 17) /* linkEnable */ 248 #define OHCI_HCC_RESET (1 << 16) /* softReset */ 249 fwohcireg_t dummy2[2]; /* dummy 0x58-0x5c */ 250 fwohcireg_t dummy3[1]; /* dummy 0x60 */ 251 fwohcireg_t sid_buf; /* self id buffer 0x64 */ 252 fwohcireg_t sid_cnt; /* self id count 0x68 */ 253 fwohcireg_t dummy4[1]; /* dummy 0x6c */ 254 fwohcireg_t ir_mask_hi_set; /* ir mask hi set 0x70 */ 255 fwohcireg_t ir_mask_hi_clr; /* ir mask hi set 0x74 */ 256 fwohcireg_t ir_mask_lo_set; /* ir mask hi set 0x78 */ 257 fwohcireg_t ir_mask_lo_clr; /* ir mask hi set 0x7c */ 258 #define FWOHCI_INTSTAT 0x80 259 #define FWOHCI_INTSTATCLR 0x84 260 #define FWOHCI_INTMASK 0x88 261 #define FWOHCI_INTMASKCLR 0x8c 262 fwohcireg_t int_stat; /* 0x80 */ 263 fwohcireg_t int_clear; /* 0x84 */ 264 fwohcireg_t int_mask; /* 0x88 */ 265 fwohcireg_t int_mask_clear; /* 0x8c */ 266 fwohcireg_t it_int_stat; /* 0x90 */ 267 fwohcireg_t it_int_clear; /* 0x94 */ 268 fwohcireg_t it_int_mask; /* 0x98 */ 269 fwohcireg_t it_mask_clear; /* 0x9c */ 270 fwohcireg_t ir_int_stat; /* 0xa0 */ 271 fwohcireg_t ir_int_clear; /* 0xa4 */ 272 fwohcireg_t ir_int_mask; /* 0xa8 */ 273 fwohcireg_t ir_mask_clear; /* 0xac */ 274 fwohcireg_t dummy5[11]; /* dummy 0xb0-d8 */ 275 fwohcireg_t fairness; /* fairness control 0xdc */ 276 fwohcireg_t link_cntl; /* Chip control 0xe0*/ 277 fwohcireg_t link_cntl_clr; /* Chip control clear 0xe4*/ 278 #define FWOHCI_NODEID 0xe8 279 fwohcireg_t node; /* Node ID 0xe8 */ 280 #define OHCI_NODE_VALID (1 << 31) 281 #define OHCI_NODE_ROOT (1 << 30) 282 283 #define OHCI_ASYSRCBUS 1 284 285 fwohcireg_t phy_access; /* PHY cntl 0xec */ 286 #define PHYDEV_RDDONE (1<<31) 287 #define PHYDEV_RDCMD (1<<15) 288 #define PHYDEV_WRCMD (1<<14) 289 #define PHYDEV_REGADDR 8 290 #define PHYDEV_WRDATA 0 291 #define PHYDEV_RDADDR 24 292 #define PHYDEV_RDDATA 16 293 294 fwohcireg_t cycle_timer; /* Cycle Timer 0xf0 */ 295 fwohcireg_t dummy6[3]; /* dummy 0xf4-fc */ 296 fwohcireg_t areq_hi; /* Async req. filter hi 0x100 */ 297 fwohcireg_t areq_hi_clr; /* Async req. filter hi 0x104 */ 298 fwohcireg_t areq_lo; /* Async req. filter lo 0x108 */ 299 fwohcireg_t areq_lo_clr; /* Async req. filter lo 0x10c */ 300 fwohcireg_t preq_hi; /* Async req. filter hi 0x110 */ 301 fwohcireg_t preq_hi_clr; /* Async req. filter hi 0x114 */ 302 fwohcireg_t preq_lo; /* Async req. filter lo 0x118 */ 303 fwohcireg_t preq_lo_clr; /* Async req. filter lo 0x11c */ 304 305 fwohcireg_t pys_upper; /* Physical Upper bound 0x120 */ 306 307 fwohcireg_t dummy7[23]; /* dummy 0x124-0x17c */ 308 309 /* 0x180, 0x184, 0x188, 0x18c */ 310 /* 0x190, 0x194, 0x198, 0x19c */ 311 /* 0x1a0, 0x1a4, 0x1a8, 0x1ac */ 312 /* 0x1b0, 0x1b4, 0x1b8, 0x1bc */ 313 /* 0x1c0, 0x1c4, 0x1c8, 0x1cc */ 314 /* 0x1d0, 0x1d4, 0x1d8, 0x1dc */ 315 /* 0x1e0, 0x1e4, 0x1e8, 0x1ec */ 316 /* 0x1f0, 0x1f4, 0x1f8, 0x1fc */ 317 struct ohci_dma dma_ch[0x4]; 318 319 /* 0x200, 0x204, 0x208, 0x20c */ 320 /* 0x210, 0x204, 0x208, 0x20c */ 321 struct ohci_itdma dma_itch[0x20]; 322 323 /* 0x400, 0x404, 0x408, 0x40c */ 324 /* 0x410, 0x404, 0x408, 0x40c */ 325 struct ohci_dma dma_irch[0x20]; 326 }; 327 328 struct fwohcidb_tr{ 329 STAILQ_ENTRY(fwohcidb_tr) link; 330 struct fw_xfer *xfer; 331 struct fwohcidb *db; 332 bus_dmamap_t dma_map; 333 caddr_t buf; 334 bus_addr_t bus_addr; 335 int dbcnt; 336 }; 337 338 /* 339 * OHCI info structure. 340 */ 341 struct fwohci_txpkthdr{ 342 union{ 343 uint32_t ld[4]; 344 struct { 345 #if BYTE_ORDER == BIG_ENDIAN 346 uint32_t spd:16, /* XXX include reserved field */ 347 :8, 348 tcode:4, 349 :4; 350 #else 351 uint32_t :4, 352 tcode:4, 353 :8, 354 spd:16; /* XXX include reserved fields */ 355 #endif 356 }common; 357 struct { 358 #if BYTE_ORDER == BIG_ENDIAN 359 uint32_t :8, 360 srcbus:1, 361 :4, 362 spd:3, 363 tlrt:8, 364 tcode:4, 365 :4; 366 #else 367 uint32_t :4, 368 tcode:4, 369 tlrt:8, 370 spd:3, 371 :4, 372 srcbus:1, 373 :8; 374 #endif 375 BIT16x2(dst, ); 376 }asycomm; 377 struct { 378 #if BYTE_ORDER == BIG_ENDIAN 379 uint32_t :13, 380 spd:3, 381 chtag:8, 382 tcode:4, 383 sy:4; 384 #else 385 uint32_t sy:4, 386 tcode:4, 387 chtag:8, 388 spd:3, 389 :13; 390 #endif 391 BIT16x2(len, ); 392 }stream; 393 }mode; 394 }; 395 struct fwohci_trailer{ 396 uint32_t time:16, 397 stat:16; 398 }; 399 400 #define OHCI_CNTL_CYCSRC (0x1 << 22) 401 #define OHCI_CNTL_CYCMTR (0x1 << 21) 402 #define OHCI_CNTL_CYCTIMER (0x1 << 20) 403 #define OHCI_CNTL_PHYPKT (0x1 << 10) 404 #define OHCI_CNTL_SID (0x1 << 9) 405 406 #define OHCI_INT_DMA_ATRQ (0x1 << 0) 407 #define OHCI_INT_DMA_ATRS (0x1 << 1) 408 #define OHCI_INT_DMA_ARRQ (0x1 << 2) 409 #define OHCI_INT_DMA_ARRS (0x1 << 3) 410 #define OHCI_INT_DMA_PRRQ (0x1 << 4) 411 #define OHCI_INT_DMA_PRRS (0x1 << 5) 412 #define OHCI_INT_DMA_IT (0x1 << 6) 413 #define OHCI_INT_DMA_IR (0x1 << 7) 414 #define OHCI_INT_PW_ERR (0x1 << 8) 415 #define OHCI_INT_LR_ERR (0x1 << 9) 416 417 #define OHCI_INT_PHY_SID (0x1 << 16) 418 #define OHCI_INT_PHY_BUS_R (0x1 << 17) 419 420 #define OHCI_INT_REG_FAIL (0x1 << 18) 421 422 #define OHCI_INT_PHY_INT (0x1 << 19) 423 #define OHCI_INT_CYC_START (0x1 << 20) 424 #define OHCI_INT_CYC_64SECOND (0x1 << 21) 425 #define OHCI_INT_CYC_LOST (0x1 << 22) 426 #define OHCI_INT_CYC_ERR (0x1 << 23) 427 428 #define OHCI_INT_ERR (0x1 << 24) 429 #define OHCI_INT_CYC_LONG (0x1 << 25) 430 #define OHCI_INT_PHY_REG (0x1 << 26) 431 432 #define OHCI_INT_EN (0x1 << 31) 433 434 #define IP_CHANNELS 0x0234 435 #define FWOHCI_MAXREC 2048 436 437 #define OHCI_ISORA 0x02 438 #define OHCI_ISORB 0x04 439 440 #define FWOHCITCODE_PHY 0xe 441