1 /* 2 * Copyright (c) 1998-2001 Katsushi Kobayashi and Hidetoshi Shimokawa 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the acknowledgement as bellow: 15 * 16 * This product includes software developed by K. Kobayashi and H. Shimokawa 17 * 18 * 4. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 23 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 24 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 25 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 26 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 27 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 28 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 29 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 30 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 * POSSIBILITY OF SUCH DAMAGE. 32 * 33 * $FreeBSD$ 34 * 35 */ 36 #define PCI_CBMEM 0x10 37 38 #define FW_VENDORID_NEC (0x1033 << 16) 39 #define FW_VENDORID_TI (0x104c << 16) 40 #define FW_VENDORID_SONY (0x104d << 16) 41 #define FW_VENDORID_VIA (0x1106 << 16) 42 #define FW_VENDORID_RICOH (0x1180 << 16) 43 #define FW_VENDORID_APPLE (0x106b << 16) 44 #define FW_VENDORID_LUCENT (0x11c1 << 16) 45 46 #define FW_DEVICE_UPD861 0x0063 47 #define FW_DEVICE_TITSB22 0x8009 48 #define FW_DEVICE_TITSB23 0x8019 49 #define FW_DEVICE_TITSB26 0x8020 50 #define FW_DEVICE_TITSB43 0x8021 51 #define FW_DEVICE_TITSB43A 0x8023 52 #define FW_DEVICE_TIPCI4450 0x8011 53 #define FW_DEVICE_TIPCI4410A 0x8017 54 #define FW_DEVICE_CX3022 0x8039 55 #define FW_DEVICE_VT6306 0x3044 56 #define FW_DEVICE_R5C552 0x0552 57 #define FW_DEVICE_PANGEA 0x0030 58 #define FW_DEVICE_UNINORTH 0x0031 59 #define FW_DEVICE_FW322 0x5811 60 61 #define PCI_INTERFACE_OHCI 0x10 62 63 #define FW_OHCI_BASE_REG 0x10 64 65 #define OHCI_DMA_ITCH 0x20 66 #define OHCI_DMA_IRCH 0x20 67 68 #define OHCI_MAX_DMA_CH (0x4 + OHCI_DMA_ITCH + OHCI_DMA_IRCH) 69 70 71 typedef volatile u_int32_t fwohcireg_t; 72 73 struct fwohcidb { 74 union { 75 struct { 76 volatile u_int32_t reqcount:16, 77 control:16; 78 volatile u_int32_t addr; 79 volatile u_int32_t depend; 80 volatile u_int32_t count:16, 81 status:16; 82 } desc; 83 volatile u_int32_t immed[4]; 84 } db; 85 #define OHCI_OUTPUT_MORE (0 << 12) 86 #define OHCI_OUTPUT_LAST (1 << 12) 87 #define OHCI_INPUT_MORE (2 << 12) 88 #define OHCI_INPUT_LAST (3 << 12) 89 #define OHCI_STORE_QUAD (4 << 12) 90 #define OHCI_LOAD_QUAD (5 << 12) 91 #define OHCI_NOP (6 << 12) 92 #define OHCI_STOP (7 << 12) 93 #define OHCI_STORE (8 << 12) 94 #define OHCI_CMD_MASK (0xf << 12) 95 96 #define OHCI_UPDATE (1 << 11) 97 98 #define OHCI_KEY_ST0 (0 << 8) 99 #define OHCI_KEY_ST1 (1 << 8) 100 #define OHCI_KEY_ST2 (2 << 8) 101 #define OHCI_KEY_ST3 (3 << 8) 102 #define OHCI_KEY_REGS (5 << 8) 103 #define OHCI_KEY_SYS (6 << 8) 104 #define OHCI_KEY_DEVICE (7 << 8) 105 #define OHCI_KEY_MASK (7 << 8) 106 107 #define OHCI_INTERRUPT_NEVER (0 << 4) 108 #define OHCI_INTERRUPT_TRUE (1 << 4) 109 #define OHCI_INTERRUPT_FALSE (2 << 4) 110 #define OHCI_INTERRUPT_ALWAYS (3 << 4) 111 112 #define OHCI_BRANCH_NEVER (0 << 2) 113 #define OHCI_BRANCH_TRUE (1 << 2) 114 #define OHCI_BRANCH_FALSE (2 << 2) 115 #define OHCI_BRANCH_ALWAYS (3 << 2) 116 #define OHCI_BRANCH_MASK (3 << 2) 117 118 #define OHCI_WAIT_NEVER (0) 119 #define OHCI_WAIT_TRUE (1) 120 #define OHCI_WAIT_FALSE (2) 121 #define OHCI_WAIT_ALWAYS (3) 122 }; 123 124 #define OHCI_SPD_S100 0x4 125 #define OHCI_SPD_S200 0x1 126 #define OHCI_SPD_S400 0x2 127 128 129 #define FWOHCIEV_NOSTAT 0 130 #define FWOHCIEV_LONGP 2 131 #define FWOHCIEV_MISSACK 3 132 #define FWOHCIEV_UNDRRUN 4 133 #define FWOHCIEV_OVRRUN 5 134 #define FWOHCIEV_DESCERR 6 135 #define FWOHCIEV_DTRDERR 7 136 #define FWOHCIEV_DTWRERR 8 137 #define FWOHCIEV_BUSRST 9 138 #define FWOHCIEV_TIMEOUT 0xa 139 #define FWOHCIEV_TCODERR 0xb 140 #define FWOHCIEV_UNKNOWN 0xe 141 #define FWOHCIEV_FLUSHED 0xf 142 #define FWOHCIEV_ACKCOMPL 0x11 143 #define FWOHCIEV_ACKPEND 0x12 144 #define FWOHCIEV_ACKBSX 0x14 145 #define FWOHCIEV_ACKBSA 0x15 146 #define FWOHCIEV_ACKBSB 0x16 147 #define FWOHCIEV_ACKTARD 0x1b 148 #define FWOHCIEV_ACKDERR 0x1d 149 #define FWOHCIEV_ACKTERR 0x1e 150 151 #define FWOHCIEV_MASK 0x1f 152 153 struct ohci_registers { 154 fwohcireg_t ver; /* Version No. 0x0 */ 155 fwohcireg_t guid; /* GUID_ROM No. 0x4 */ 156 fwohcireg_t retry; /* AT retries 0x8 */ 157 #define FWOHCI_RETRY 0x8 158 fwohcireg_t csr_data; /* CSR data 0xc */ 159 fwohcireg_t csr_cmp; /* CSR compare 0x10 */ 160 fwohcireg_t csr_cntl; /* CSR compare 0x14 */ 161 fwohcireg_t rom_hdr; /* config ROM ptr. 0x18 */ 162 fwohcireg_t bus_id; /* BUS_ID 0x1c */ 163 fwohcireg_t bus_opt; /* BUS option 0x20 */ 164 #define FWOHCIGUID_H 0x24 165 #define FWOHCIGUID_L 0x28 166 fwohcireg_t guid_hi; /* GUID hi 0x24 */ 167 fwohcireg_t guid_lo; /* GUID lo 0x28 */ 168 fwohcireg_t dummy0[2]; /* dummy 0x2c-0x30 */ 169 fwohcireg_t config_rom; /* config ROM map 0x34 */ 170 fwohcireg_t post_wr_lo; /* post write addr lo 0x38 */ 171 fwohcireg_t post_wr_hi; /* post write addr hi 0x3c */ 172 fwohcireg_t vender; /* vender ID 0x40 */ 173 fwohcireg_t dummy1[3]; /* dummy 0x44-0x4c */ 174 fwohcireg_t hcc_cntl_set; /* HCC control set 0x50 */ 175 fwohcireg_t hcc_cntl_clr; /* HCC control clr 0x54 */ 176 #define OHCI_HCC_BIBIV (1 << 31) /* BIBimage Valid */ 177 #define OHCI_HCC_BIGEND (1 << 30) /* noByteSwapData */ 178 #define OHCI_HCC_PRPHY (1 << 23) /* programPhyEnable */ 179 #define OHCI_HCC_PHYEN (1 << 22) /* aPhyEnhanceEnable */ 180 #define OHCI_HCC_LPS (1 << 19) /* LPS */ 181 #define OHCI_HCC_POSTWR (1 << 18) /* postedWriteEnable */ 182 #define OHCI_HCC_LINKEN (1 << 17) /* linkEnable */ 183 #define OHCI_HCC_RESET (1 << 16) /* softReset */ 184 fwohcireg_t dummy2[2]; /* dummy 0x58-0x5c */ 185 fwohcireg_t dummy3[1]; /* dummy 0x60 */ 186 fwohcireg_t sid_buf; /* self id buffer 0x64 */ 187 fwohcireg_t sid_cnt; /* self id count 0x68 */ 188 fwohcireg_t dummy4[1]; /* dummy 0x6c */ 189 fwohcireg_t ir_mask_hi_set; /* ir mask hi set 0x70 */ 190 fwohcireg_t ir_mask_hi_clr; /* ir mask hi set 0x74 */ 191 fwohcireg_t ir_mask_lo_set; /* ir mask hi set 0x78 */ 192 fwohcireg_t ir_mask_lo_clr; /* ir mask hi set 0x7c */ 193 #define FWOHCI_INTSTAT 0x80 194 #define FWOHCI_INTSTATCLR 0x84 195 #define FWOHCI_INTMASK 0x88 196 #define FWOHCI_INTMASKCLR 0x8c 197 fwohcireg_t int_stat; /* 0x80 */ 198 fwohcireg_t int_clear; /* 0x84 */ 199 fwohcireg_t int_mask; /* 0x88 */ 200 fwohcireg_t int_mask_clear; /* 0x8c */ 201 fwohcireg_t it_int_stat; /* 0x90 */ 202 fwohcireg_t it_int_clear; /* 0x94 */ 203 fwohcireg_t it_int_mask; /* 0x98 */ 204 fwohcireg_t it_mask_clear; /* 0x9c */ 205 fwohcireg_t ir_int_stat; /* 0xa0 */ 206 fwohcireg_t ir_int_clear; /* 0xa4 */ 207 fwohcireg_t ir_int_mask; /* 0xa8 */ 208 fwohcireg_t ir_mask_clear; /* 0xac */ 209 fwohcireg_t dummy5[11]; /* dummy 0xb0-d8 */ 210 fwohcireg_t fairness; /* fairness control 0xdc */ 211 fwohcireg_t link_cntl; /* Chip control 0xe0*/ 212 fwohcireg_t link_cntl_clr; /* Chip control clear 0xe4*/ 213 #define FWOHCI_NODEID 0xe8 214 fwohcireg_t node; /* Node ID 0xe8 */ 215 #define OHCI_NODE_VALID (1 << 31) 216 #define OHCI_NODE_ROOT (1 << 30) 217 218 #define OHCI_ASYSRCBUS 1 219 220 fwohcireg_t phy_access; /* PHY cntl 0xec */ 221 #define PHYDEV_RDDONE (1<<31) 222 #define PHYDEV_RDCMD (1<<15) 223 #define PHYDEV_WRCMD (1<<14) 224 #define PHYDEV_REGADDR 8 225 #define PHYDEV_WRDATA 0 226 #define PHYDEV_RDADDR 24 227 #define PHYDEV_RDDATA 16 228 229 fwohcireg_t cycle_timer; /* Cycle Timer 0xf0 */ 230 fwohcireg_t dummy6[3]; /* dummy 0xf4-fc */ 231 fwohcireg_t areq_hi; /* Async req. filter hi 0x100 */ 232 fwohcireg_t areq_hi_clr; /* Async req. filter hi 0x104 */ 233 fwohcireg_t areq_lo; /* Async req. filter lo 0x108 */ 234 fwohcireg_t areq_lo_clr; /* Async req. filter lo 0x10c */ 235 fwohcireg_t preq_hi; /* Async req. filter hi 0x110 */ 236 fwohcireg_t preq_hi_clr; /* Async req. filter hi 0x114 */ 237 fwohcireg_t preq_lo; /* Async req. filter lo 0x118 */ 238 fwohcireg_t preq_lo_clr; /* Async req. filter lo 0x11c */ 239 240 fwohcireg_t pys_upper; /* Physical Upper bound 0x120 */ 241 242 fwohcireg_t dummy7[23]; /* dummy 0x124-0x17c */ 243 244 struct ohci_dma{ 245 fwohcireg_t cntl; 246 247 #define OHCI_CNTL_CYCMATCH_S (0x1 << 31) 248 249 #define OHCI_CNTL_BUFFIL (0x1 << 31) 250 #define OHCI_CNTL_ISOHDR (0x1 << 30) 251 #define OHCI_CNTL_CYCMATCH_R (0x1 << 29) 252 #define OHCI_CNTL_MULTICH (0x1 << 28) 253 254 #define OHCI_CNTL_DMA_RUN (0x1 << 15) 255 #define OHCI_CNTL_DMA_WAKE (0x1 << 12) 256 #define OHCI_CNTL_DMA_DEAD (0x1 << 11) 257 #define OHCI_CNTL_DMA_ACTIVE (0x1 << 10) 258 #define OHCI_CNTL_DMA_BT (0x1 << 8) 259 #define OHCI_CNTL_DMA_BAD (0x1 << 7) 260 #define OHCI_CNTL_DMA_STAT (0xff) 261 262 fwohcireg_t cntl_clr; 263 fwohcireg_t dummy0; 264 fwohcireg_t cmd; 265 fwohcireg_t match; 266 fwohcireg_t dummy1; 267 fwohcireg_t dummy2; 268 fwohcireg_t dummy3; 269 }; 270 /* 0x180, 0x184, 0x188, 0x18c */ 271 /* 0x190, 0x194, 0x198, 0x19c */ 272 /* 0x1a0, 0x1a4, 0x1a8, 0x1ac */ 273 /* 0x1b0, 0x1b4, 0x1b8, 0x1bc */ 274 /* 0x1c0, 0x1c4, 0x1c8, 0x1cc */ 275 /* 0x1d0, 0x1d4, 0x1d8, 0x1dc */ 276 /* 0x1e0, 0x1e4, 0x1e8, 0x1ec */ 277 /* 0x1f0, 0x1f4, 0x1f8, 0x1fc */ 278 struct ohci_dma dma_ch[0x4]; 279 280 /* 0x200, 0x204, 0x208, 0x20c */ 281 /* 0x210, 0x204, 0x208, 0x20c */ 282 struct ohci_itdma{ 283 fwohcireg_t cntl; 284 fwohcireg_t cntl_clr; 285 fwohcireg_t dummy0; 286 fwohcireg_t cmd; 287 }; 288 struct ohci_itdma dma_itch[0x20]; 289 290 /* 0x400, 0x404, 0x408, 0x40c */ 291 /* 0x410, 0x404, 0x408, 0x40c */ 292 293 struct ohci_dma dma_irch[0x20]; 294 }; 295 296 struct fwohcidb_tr{ 297 STAILQ_ENTRY(fwohcidb_tr) link; 298 struct fw_xfer *xfer; 299 volatile struct fwohcidb *db; 300 caddr_t buf; 301 caddr_t dummy; 302 int dbcnt; 303 }; 304 305 /* 306 * OHCI info structure. 307 */ 308 struct fwohci_txpkthdr{ 309 union{ 310 u_int32_t ld[4]; 311 struct { 312 u_int32_t res3:4, 313 tcode:4, 314 res2:8, 315 spd:3, 316 res1:13; 317 }common; 318 struct { 319 u_int32_t res3:4, 320 tcode:4, 321 tlrt:8, 322 spd:3, 323 res2:4, 324 srcbus:1, 325 res1:8; 326 u_int32_t res4:16, 327 dst:16; 328 }asycomm; 329 struct { 330 u_int32_t sy:4, 331 tcode:4, 332 chtag:8, 333 spd:3, 334 res1:13; 335 u_int32_t res2:16, 336 len:16; 337 }stream; 338 }mode; 339 }; 340 struct fwohci_trailer{ 341 u_int32_t time:16, 342 stat:16; 343 }; 344 345 #define OHCI_CNTL_CYCSRC (0x1 << 22) 346 #define OHCI_CNTL_CYCMTR (0x1 << 21) 347 #define OHCI_CNTL_CYCTIMER (0x1 << 20) 348 #define OHCI_CNTL_PHYPKT (0x1 << 10) 349 #define OHCI_CNTL_SID (0x1 << 9) 350 351 #define OHCI_INT_DMA_ATRQ (0x1 << 0) 352 #define OHCI_INT_DMA_ATRS (0x1 << 1) 353 #define OHCI_INT_DMA_ARRQ (0x1 << 2) 354 #define OHCI_INT_DMA_ARRS (0x1 << 3) 355 #define OHCI_INT_DMA_PRRQ (0x1 << 4) 356 #define OHCI_INT_DMA_PRRS (0x1 << 5) 357 #define OHCI_INT_DMA_IT (0x1 << 6) 358 #define OHCI_INT_DMA_IR (0x1 << 7) 359 #define OHCI_INT_PW_ERR (0x1 << 8) 360 #define OHCI_INT_LR_ERR (0x1 << 9) 361 362 #define OHCI_INT_PHY_SID (0x1 << 16) 363 #define OHCI_INT_PHY_BUS_R (0x1 << 17) 364 365 #define OHCI_INT_REG_FAIL (0x1 << 18) 366 367 #define OHCI_INT_PHY_INT (0x1 << 19) 368 #define OHCI_INT_CYC_START (0x1 << 20) 369 #define OHCI_INT_CYC_64SECOND (0x1 << 21) 370 #define OHCI_INT_CYC_LOST (0x1 << 22) 371 #define OHCI_INT_CYC_ERR (0x1 << 23) 372 373 #define OHCI_INT_ERR (0x1 << 24) 374 #define OHCI_INT_CYC_LONG (0x1 << 25) 375 #define OHCI_INT_PHY_REG (0x1 << 26) 376 377 #define OHCI_INT_EN (0x1 << 31) 378 379 #define IP_CHANNELS 0x0234 380 #define FWOHCI_MAXREC 2048 381 382 #define OHCI_ISORA 0x02 383 #define OHCI_ISORB 0x04 384 385 #define FWOHCITCODE_PHY 0xe 386