1 /*- 2 * Copyright (c) 2003 Hidetoshi Shimokawa 3 * Copyright (c) 1998-2002 Katsushi Kobayashi and Hidetoshi Shimokawa 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the acknowledgement as bellow: 16 * 17 * This product includes software developed by K. Kobayashi and H. Shimokawa 18 * 19 * 4. The name of the author may not be used to endorse or promote products 20 * derived from this software without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 24 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 25 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 26 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 27 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 28 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 29 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 30 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 31 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 32 * POSSIBILITY OF SUCH DAMAGE. 33 * 34 * $FreeBSD$ 35 * 36 */ 37 38 #define ATRQ_CH 0 39 #define ATRS_CH 1 40 #define ARRQ_CH 2 41 #define ARRS_CH 3 42 #define ITX_CH 4 43 #define IRX_CH 0x24 44 45 #include <sys/param.h> 46 #include <sys/systm.h> 47 #include <sys/mbuf.h> 48 #include <sys/malloc.h> 49 #include <sys/sockio.h> 50 #include <sys/sysctl.h> 51 #include <sys/bus.h> 52 #include <sys/kernel.h> 53 #include <sys/conf.h> 54 #include <sys/endian.h> 55 #include <sys/kdb.h> 56 57 #include <machine/bus.h> 58 59 #include <dev/firewire/firewire.h> 60 #include <dev/firewire/firewirereg.h> 61 #include <dev/firewire/fwdma.h> 62 #include <dev/firewire/fwohcireg.h> 63 #include <dev/firewire/fwohcivar.h> 64 #include <dev/firewire/firewire_phy.h> 65 66 #undef OHCI_DEBUG 67 68 static int nocyclemaster; 69 int firewire_phydma_enable = 1; 70 SYSCTL_DECL(_hw_firewire); 71 SYSCTL_INT(_hw_firewire, OID_AUTO, nocyclemaster, CTLFLAG_RWTUN, 72 &nocyclemaster, 0, "Do not send cycle start packets"); 73 SYSCTL_INT(_hw_firewire, OID_AUTO, phydma_enable, CTLFLAG_RWTUN, 74 &firewire_phydma_enable, 0, "Allow physical request DMA from firewire"); 75 76 static char dbcode[16][0x10]={"OUTM", "OUTL","INPM","INPL", 77 "STOR","LOAD","NOP ","STOP",}; 78 79 static char dbkey[8][0x10]={"ST0", "ST1","ST2","ST3", 80 "UNDEF","REG","SYS","DEV"}; 81 static char dbcond[4][0x10]={"NEV","C=1", "C=0", "ALL"}; 82 char fwohcicode[32][0x20]={ 83 "No stat","Undef","long","miss Ack err", 84 "FIFO underrun","FIFO overrun","desc err", "data read err", 85 "data write err","bus reset","timeout","tcode err", 86 "Undef","Undef","unknown event","flushed", 87 "Undef","ack complete","ack pend","Undef", 88 "ack busy_X","ack busy_A","ack busy_B","Undef", 89 "Undef","Undef","Undef","ack tardy", 90 "Undef","ack data_err","ack type_err",""}; 91 92 #define MAX_SPEED 3 93 extern char *linkspeed[]; 94 uint32_t tagbit[4] = { 1 << 28, 1 << 29, 1 << 30, 1 << 31}; 95 96 static struct tcode_info tinfo[] = { 97 /* hdr_len block flag valid_response */ 98 /* 0 WREQQ */ {16, FWTI_REQ | FWTI_TLABEL, FWTCODE_WRES}, 99 /* 1 WREQB */ {16, FWTI_REQ | FWTI_TLABEL | FWTI_BLOCK_ASY, FWTCODE_WRES}, 100 /* 2 WRES */ {12, FWTI_RES, 0xff}, 101 /* 3 XXX */ { 0, 0, 0xff}, 102 /* 4 RREQQ */ {12, FWTI_REQ | FWTI_TLABEL, FWTCODE_RRESQ}, 103 /* 5 RREQB */ {16, FWTI_REQ | FWTI_TLABEL, FWTCODE_RRESB}, 104 /* 6 RRESQ */ {16, FWTI_RES, 0xff}, 105 /* 7 RRESB */ {16, FWTI_RES | FWTI_BLOCK_ASY, 0xff}, 106 /* 8 CYCS */ { 0, 0, 0xff}, 107 /* 9 LREQ */ {16, FWTI_REQ | FWTI_TLABEL | FWTI_BLOCK_ASY, FWTCODE_LRES}, 108 /* a STREAM */ { 4, FWTI_REQ | FWTI_BLOCK_STR, 0xff}, 109 /* b LRES */ {16, FWTI_RES | FWTI_BLOCK_ASY, 0xff}, 110 /* c XXX */ { 0, 0, 0xff}, 111 /* d XXX */ { 0, 0, 0xff}, 112 /* e PHY */ {12, FWTI_REQ, 0xff}, 113 /* f XXX */ { 0, 0, 0xff} 114 }; 115 116 #define OHCI_WRITE_SIGMASK 0xffff0000 117 #define OHCI_READ_SIGMASK 0xffff0000 118 119 #define OWRITE(sc, r, x) bus_space_write_4((sc)->bst, (sc)->bsh, (r), (x)) 120 #define OREAD(sc, r) bus_space_read_4((sc)->bst, (sc)->bsh, (r)) 121 122 static void fwohci_ibr (struct firewire_comm *); 123 static void fwohci_db_init (struct fwohci_softc *, struct fwohci_dbch *); 124 static void fwohci_db_free (struct fwohci_dbch *); 125 static void fwohci_arcv (struct fwohci_softc *, struct fwohci_dbch *, int); 126 static void fwohci_txd (struct fwohci_softc *, struct fwohci_dbch *); 127 static void fwohci_start_atq (struct firewire_comm *); 128 static void fwohci_start_ats (struct firewire_comm *); 129 static void fwohci_start (struct fwohci_softc *, struct fwohci_dbch *); 130 static uint32_t fwphy_wrdata ( struct fwohci_softc *, uint32_t, uint32_t); 131 static uint32_t fwphy_rddata ( struct fwohci_softc *, uint32_t); 132 static int fwohci_rx_enable (struct fwohci_softc *, struct fwohci_dbch *); 133 static int fwohci_tx_enable (struct fwohci_softc *, struct fwohci_dbch *); 134 static int fwohci_irx_enable (struct firewire_comm *, int); 135 static int fwohci_irx_disable (struct firewire_comm *, int); 136 #if BYTE_ORDER == BIG_ENDIAN 137 static void fwohci_irx_post (struct firewire_comm *, uint32_t *); 138 #endif 139 static int fwohci_itxbuf_enable (struct firewire_comm *, int); 140 static int fwohci_itx_disable (struct firewire_comm *, int); 141 static void fwohci_timeout (void *); 142 static void fwohci_set_intr (struct firewire_comm *, int); 143 144 static int fwohci_add_rx_buf (struct fwohci_dbch *, struct fwohcidb_tr *, int, struct fwdma_alloc *); 145 static int fwohci_add_tx_buf (struct fwohci_dbch *, struct fwohcidb_tr *, int); 146 static void dump_db (struct fwohci_softc *, uint32_t); 147 static void print_db (struct fwohcidb_tr *, struct fwohcidb *, uint32_t , uint32_t); 148 static void dump_dma (struct fwohci_softc *, uint32_t); 149 static uint32_t fwohci_cyctimer (struct firewire_comm *); 150 static void fwohci_rbuf_update (struct fwohci_softc *, int); 151 static void fwohci_tbuf_update (struct fwohci_softc *, int); 152 void fwohci_txbufdb (struct fwohci_softc *, int , struct fw_bulkxfer *); 153 static void fwohci_task_busreset(void *, int); 154 static void fwohci_task_sid(void *, int); 155 static void fwohci_task_dma(void *, int); 156 157 /* 158 * memory allocated for DMA programs 159 */ 160 #define DMA_PROG_ALLOC (8 * PAGE_SIZE) 161 162 #define NDB FWMAXQUEUE 163 164 #define OHCI_VERSION 0x00 165 #define OHCI_ATRETRY 0x08 166 #define OHCI_CROMHDR 0x18 167 #define OHCI_BUS_OPT 0x20 168 #define OHCI_BUSIRMC (1U << 31) 169 #define OHCI_BUSCMC (1 << 30) 170 #define OHCI_BUSISC (1 << 29) 171 #define OHCI_BUSBMC (1 << 28) 172 #define OHCI_BUSPMC (1 << 27) 173 #define OHCI_BUSFNC OHCI_BUSIRMC | OHCI_BUSCMC | OHCI_BUSISC |\ 174 OHCI_BUSBMC | OHCI_BUSPMC 175 176 #define OHCI_EUID_HI 0x24 177 #define OHCI_EUID_LO 0x28 178 179 #define OHCI_CROMPTR 0x34 180 #define OHCI_HCCCTL 0x50 181 #define OHCI_HCCCTLCLR 0x54 182 #define OHCI_AREQHI 0x100 183 #define OHCI_AREQHICLR 0x104 184 #define OHCI_AREQLO 0x108 185 #define OHCI_AREQLOCLR 0x10c 186 #define OHCI_PREQHI 0x110 187 #define OHCI_PREQHICLR 0x114 188 #define OHCI_PREQLO 0x118 189 #define OHCI_PREQLOCLR 0x11c 190 #define OHCI_PREQUPPER 0x120 191 192 #define OHCI_SID_BUF 0x64 193 #define OHCI_SID_CNT 0x68 194 #define OHCI_SID_ERR (1U << 31) 195 #define OHCI_SID_CNT_MASK 0xffc 196 197 #define OHCI_IT_STAT 0x90 198 #define OHCI_IT_STATCLR 0x94 199 #define OHCI_IT_MASK 0x98 200 #define OHCI_IT_MASKCLR 0x9c 201 202 #define OHCI_IR_STAT 0xa0 203 #define OHCI_IR_STATCLR 0xa4 204 #define OHCI_IR_MASK 0xa8 205 #define OHCI_IR_MASKCLR 0xac 206 207 #define OHCI_LNKCTL 0xe0 208 #define OHCI_LNKCTLCLR 0xe4 209 210 #define OHCI_PHYACCESS 0xec 211 #define OHCI_CYCLETIMER 0xf0 212 213 #define OHCI_DMACTL(off) (off) 214 #define OHCI_DMACTLCLR(off) (off + 4) 215 #define OHCI_DMACMD(off) (off + 0xc) 216 #define OHCI_DMAMATCH(off) (off + 0x10) 217 218 #define OHCI_ATQOFF 0x180 219 #define OHCI_ATQCTL OHCI_ATQOFF 220 #define OHCI_ATQCTLCLR (OHCI_ATQOFF + 4) 221 #define OHCI_ATQCMD (OHCI_ATQOFF + 0xc) 222 #define OHCI_ATQMATCH (OHCI_ATQOFF + 0x10) 223 224 #define OHCI_ATSOFF 0x1a0 225 #define OHCI_ATSCTL OHCI_ATSOFF 226 #define OHCI_ATSCTLCLR (OHCI_ATSOFF + 4) 227 #define OHCI_ATSCMD (OHCI_ATSOFF + 0xc) 228 #define OHCI_ATSMATCH (OHCI_ATSOFF + 0x10) 229 230 #define OHCI_ARQOFF 0x1c0 231 #define OHCI_ARQCTL OHCI_ARQOFF 232 #define OHCI_ARQCTLCLR (OHCI_ARQOFF + 4) 233 #define OHCI_ARQCMD (OHCI_ARQOFF + 0xc) 234 #define OHCI_ARQMATCH (OHCI_ARQOFF + 0x10) 235 236 #define OHCI_ARSOFF 0x1e0 237 #define OHCI_ARSCTL OHCI_ARSOFF 238 #define OHCI_ARSCTLCLR (OHCI_ARSOFF + 4) 239 #define OHCI_ARSCMD (OHCI_ARSOFF + 0xc) 240 #define OHCI_ARSMATCH (OHCI_ARSOFF + 0x10) 241 242 #define OHCI_ITOFF(CH) (0x200 + 0x10 * (CH)) 243 #define OHCI_ITCTL(CH) (OHCI_ITOFF(CH)) 244 #define OHCI_ITCTLCLR(CH) (OHCI_ITOFF(CH) + 4) 245 #define OHCI_ITCMD(CH) (OHCI_ITOFF(CH) + 0xc) 246 247 #define OHCI_IROFF(CH) (0x400 + 0x20 * (CH)) 248 #define OHCI_IRCTL(CH) (OHCI_IROFF(CH)) 249 #define OHCI_IRCTLCLR(CH) (OHCI_IROFF(CH) + 4) 250 #define OHCI_IRCMD(CH) (OHCI_IROFF(CH) + 0xc) 251 #define OHCI_IRMATCH(CH) (OHCI_IROFF(CH) + 0x10) 252 253 d_ioctl_t fwohci_ioctl; 254 255 /* 256 * Communication with PHY device 257 */ 258 /* XXX need lock for phy access */ 259 static uint32_t 260 fwphy_wrdata( struct fwohci_softc *sc, uint32_t addr, uint32_t data) 261 { 262 uint32_t fun; 263 264 addr &= 0xf; 265 data &= 0xff; 266 267 fun = (PHYDEV_WRCMD | (addr << PHYDEV_REGADDR) | (data << PHYDEV_WRDATA)); 268 OWRITE(sc, OHCI_PHYACCESS, fun); 269 DELAY(100); 270 271 return(fwphy_rddata( sc, addr)); 272 } 273 274 static uint32_t 275 fwohci_set_bus_manager(struct firewire_comm *fc, u_int node) 276 { 277 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 278 int i; 279 uint32_t bm; 280 281 #define OHCI_CSR_DATA 0x0c 282 #define OHCI_CSR_COMP 0x10 283 #define OHCI_CSR_CONT 0x14 284 #define OHCI_BUS_MANAGER_ID 0 285 286 OWRITE(sc, OHCI_CSR_DATA, node); 287 OWRITE(sc, OHCI_CSR_COMP, 0x3f); 288 OWRITE(sc, OHCI_CSR_CONT, OHCI_BUS_MANAGER_ID); 289 for (i = 0; !(OREAD(sc, OHCI_CSR_CONT) & (1<<31)) && (i < 1000); i++) 290 DELAY(10); 291 bm = OREAD(sc, OHCI_CSR_DATA); 292 if((bm & 0x3f) == 0x3f) 293 bm = node; 294 if (firewire_debug) 295 device_printf(sc->fc.dev, "%s: %d->%d (loop=%d)\n", 296 __func__, bm, node, i); 297 298 return(bm); 299 } 300 301 static uint32_t 302 fwphy_rddata(struct fwohci_softc *sc, u_int addr) 303 { 304 uint32_t fun, stat; 305 u_int i, retry = 0; 306 307 addr &= 0xf; 308 #define MAX_RETRY 100 309 again: 310 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_REG_FAIL); 311 fun = PHYDEV_RDCMD | (addr << PHYDEV_REGADDR); 312 OWRITE(sc, OHCI_PHYACCESS, fun); 313 for ( i = 0 ; i < MAX_RETRY ; i ++ ){ 314 fun = OREAD(sc, OHCI_PHYACCESS); 315 if ((fun & PHYDEV_RDCMD) == 0 && (fun & PHYDEV_RDDONE) != 0) 316 break; 317 DELAY(100); 318 } 319 if(i >= MAX_RETRY) { 320 if (firewire_debug) 321 device_printf(sc->fc.dev, "%s: failed(1).\n", __func__); 322 if (++retry < MAX_RETRY) { 323 DELAY(100); 324 goto again; 325 } 326 } 327 /* Make sure that SCLK is started */ 328 stat = OREAD(sc, FWOHCI_INTSTAT); 329 if ((stat & OHCI_INT_REG_FAIL) != 0 || 330 ((fun >> PHYDEV_REGADDR) & 0xf) != addr) { 331 if (firewire_debug) 332 device_printf(sc->fc.dev, "%s: failed(2).\n", __func__); 333 if (++retry < MAX_RETRY) { 334 DELAY(100); 335 goto again; 336 } 337 } 338 if (firewire_debug > 1 || retry >= MAX_RETRY) 339 device_printf(sc->fc.dev, 340 "%s:: 0x%x loop=%d, retry=%d\n", 341 __func__, addr, i, retry); 342 #undef MAX_RETRY 343 return((fun >> PHYDEV_RDDATA )& 0xff); 344 } 345 /* Device specific ioctl. */ 346 int 347 fwohci_ioctl (struct cdev *dev, u_long cmd, caddr_t data, int flag, fw_proc *td) 348 { 349 struct firewire_softc *sc; 350 struct fwohci_softc *fc; 351 int unit = DEV2UNIT(dev); 352 int err = 0; 353 struct fw_reg_req_t *reg = (struct fw_reg_req_t *) data; 354 uint32_t *dmach = (uint32_t *) data; 355 356 sc = devclass_get_softc(firewire_devclass, unit); 357 if(sc == NULL){ 358 return(EINVAL); 359 } 360 fc = (struct fwohci_softc *)sc->fc; 361 362 if (!data) 363 return(EINVAL); 364 365 switch (cmd) { 366 case FWOHCI_WRREG: 367 #define OHCI_MAX_REG 0x800 368 if(reg->addr <= OHCI_MAX_REG){ 369 OWRITE(fc, reg->addr, reg->data); 370 reg->data = OREAD(fc, reg->addr); 371 }else{ 372 err = EINVAL; 373 } 374 break; 375 case FWOHCI_RDREG: 376 if(reg->addr <= OHCI_MAX_REG){ 377 reg->data = OREAD(fc, reg->addr); 378 }else{ 379 err = EINVAL; 380 } 381 break; 382 /* Read DMA descriptors for debug */ 383 case DUMPDMA: 384 if(*dmach <= OHCI_MAX_DMA_CH ){ 385 dump_dma(fc, *dmach); 386 dump_db(fc, *dmach); 387 }else{ 388 err = EINVAL; 389 } 390 break; 391 /* Read/Write Phy registers */ 392 #define OHCI_MAX_PHY_REG 0xf 393 case FWOHCI_RDPHYREG: 394 if (reg->addr <= OHCI_MAX_PHY_REG) 395 reg->data = fwphy_rddata(fc, reg->addr); 396 else 397 err = EINVAL; 398 break; 399 case FWOHCI_WRPHYREG: 400 if (reg->addr <= OHCI_MAX_PHY_REG) 401 reg->data = fwphy_wrdata(fc, reg->addr, reg->data); 402 else 403 err = EINVAL; 404 break; 405 default: 406 err = EINVAL; 407 break; 408 } 409 return err; 410 } 411 412 static int 413 fwohci_probe_phy(struct fwohci_softc *sc, device_t dev) 414 { 415 uint32_t reg, reg2; 416 int e1394a = 1; 417 /* 418 * probe PHY parameters 419 * 0. to prove PHY version, whether compliance of 1394a. 420 * 1. to probe maximum speed supported by the PHY and 421 * number of port supported by core-logic. 422 * It is not actually available port on your PC . 423 */ 424 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_LPS); 425 DELAY(500); 426 427 reg = fwphy_rddata(sc, FW_PHY_SPD_REG); 428 429 if((reg >> 5) != 7 ){ 430 sc->fc.mode &= ~FWPHYASYST; 431 sc->fc.nport = reg & FW_PHY_NP; 432 sc->fc.speed = reg & FW_PHY_SPD >> 6; 433 if (sc->fc.speed > MAX_SPEED) { 434 device_printf(dev, "invalid speed %d (fixed to %d).\n", 435 sc->fc.speed, MAX_SPEED); 436 sc->fc.speed = MAX_SPEED; 437 } 438 device_printf(dev, 439 "Phy 1394 only %s, %d ports.\n", 440 linkspeed[sc->fc.speed], sc->fc.nport); 441 }else{ 442 reg2 = fwphy_rddata(sc, FW_PHY_ESPD_REG); 443 sc->fc.mode |= FWPHYASYST; 444 sc->fc.nport = reg & FW_PHY_NP; 445 sc->fc.speed = (reg2 & FW_PHY_ESPD) >> 5; 446 if (sc->fc.speed > MAX_SPEED) { 447 device_printf(dev, "invalid speed %d (fixed to %d).\n", 448 sc->fc.speed, MAX_SPEED); 449 sc->fc.speed = MAX_SPEED; 450 } 451 device_printf(dev, 452 "Phy 1394a available %s, %d ports.\n", 453 linkspeed[sc->fc.speed], sc->fc.nport); 454 455 /* check programPhyEnable */ 456 reg2 = fwphy_rddata(sc, 5); 457 #if 0 458 if (e1394a && (OREAD(sc, OHCI_HCCCTL) & OHCI_HCC_PRPHY)) { 459 #else /* XXX force to enable 1394a */ 460 if (e1394a) { 461 #endif 462 if (firewire_debug) 463 device_printf(dev, 464 "Enable 1394a Enhancements\n"); 465 /* enable EAA EMC */ 466 reg2 |= 0x03; 467 /* set aPhyEnhanceEnable */ 468 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_PHYEN); 469 OWRITE(sc, OHCI_HCCCTLCLR, OHCI_HCC_PRPHY); 470 } else { 471 /* for safe */ 472 reg2 &= ~0x83; 473 } 474 reg2 = fwphy_wrdata(sc, 5, reg2); 475 } 476 477 reg = fwphy_rddata(sc, FW_PHY_SPD_REG); 478 if((reg >> 5) == 7 ){ 479 reg = fwphy_rddata(sc, 4); 480 reg |= 1 << 6; 481 fwphy_wrdata(sc, 4, reg); 482 reg = fwphy_rddata(sc, 4); 483 } 484 return 0; 485 } 486 487 488 void 489 fwohci_reset(struct fwohci_softc *sc, device_t dev) 490 { 491 int i, max_rec, speed; 492 uint32_t reg, reg2; 493 struct fwohcidb_tr *db_tr; 494 495 /* Disable interrupts */ 496 OWRITE(sc, FWOHCI_INTMASKCLR, ~0); 497 498 /* Now stopping all DMA channels */ 499 OWRITE(sc, OHCI_ARQCTLCLR, OHCI_CNTL_DMA_RUN); 500 OWRITE(sc, OHCI_ARSCTLCLR, OHCI_CNTL_DMA_RUN); 501 OWRITE(sc, OHCI_ATQCTLCLR, OHCI_CNTL_DMA_RUN); 502 OWRITE(sc, OHCI_ATSCTLCLR, OHCI_CNTL_DMA_RUN); 503 504 OWRITE(sc, OHCI_IR_MASKCLR, ~0); 505 for( i = 0 ; i < sc->fc.nisodma ; i ++ ){ 506 OWRITE(sc, OHCI_IRCTLCLR(i), OHCI_CNTL_DMA_RUN); 507 OWRITE(sc, OHCI_ITCTLCLR(i), OHCI_CNTL_DMA_RUN); 508 } 509 510 /* FLUSH FIFO and reset Transmitter/Reciever */ 511 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_RESET); 512 if (firewire_debug) 513 device_printf(dev, "resetting OHCI..."); 514 i = 0; 515 while(OREAD(sc, OHCI_HCCCTL) & OHCI_HCC_RESET) { 516 if (i++ > 100) break; 517 DELAY(1000); 518 } 519 if (firewire_debug) 520 printf("done (loop=%d)\n", i); 521 522 /* Probe phy */ 523 fwohci_probe_phy(sc, dev); 524 525 /* Probe link */ 526 reg = OREAD(sc, OHCI_BUS_OPT); 527 reg2 = reg | OHCI_BUSFNC; 528 max_rec = (reg & 0x0000f000) >> 12; 529 speed = (reg & 0x00000007); 530 device_printf(dev, "Link %s, max_rec %d bytes.\n", 531 linkspeed[speed], MAXREC(max_rec)); 532 /* XXX fix max_rec */ 533 sc->fc.maxrec = sc->fc.speed + 8; 534 if (max_rec != sc->fc.maxrec) { 535 reg2 = (reg2 & 0xffff0fff) | (sc->fc.maxrec << 12); 536 device_printf(dev, "max_rec %d -> %d\n", 537 MAXREC(max_rec), MAXREC(sc->fc.maxrec)); 538 } 539 if (firewire_debug) 540 device_printf(dev, "BUS_OPT 0x%x -> 0x%x\n", reg, reg2); 541 OWRITE(sc, OHCI_BUS_OPT, reg2); 542 543 /* Initialize registers */ 544 OWRITE(sc, OHCI_CROMHDR, sc->fc.config_rom[0]); 545 OWRITE(sc, OHCI_CROMPTR, sc->crom_dma.bus_addr); 546 OWRITE(sc, OHCI_HCCCTLCLR, OHCI_HCC_BIGEND); 547 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_POSTWR); 548 OWRITE(sc, OHCI_SID_BUF, sc->sid_dma.bus_addr); 549 OWRITE(sc, OHCI_LNKCTL, OHCI_CNTL_SID); 550 551 /* Enable link */ 552 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_LINKEN); 553 554 /* Force to start async RX DMA */ 555 sc->arrq.xferq.flag &= ~FWXFERQ_RUNNING; 556 sc->arrs.xferq.flag &= ~FWXFERQ_RUNNING; 557 fwohci_rx_enable(sc, &sc->arrq); 558 fwohci_rx_enable(sc, &sc->arrs); 559 560 /* Initialize async TX */ 561 OWRITE(sc, OHCI_ATQCTLCLR, OHCI_CNTL_DMA_RUN | OHCI_CNTL_DMA_DEAD); 562 OWRITE(sc, OHCI_ATSCTLCLR, OHCI_CNTL_DMA_RUN | OHCI_CNTL_DMA_DEAD); 563 564 /* AT Retries */ 565 OWRITE(sc, FWOHCI_RETRY, 566 /* CycleLimit PhyRespRetries ATRespRetries ATReqRetries */ 567 (0xffff << 16 ) | (0x0f << 8) | (0x0f << 4) | 0x0f) ; 568 569 sc->atrq.top = STAILQ_FIRST(&sc->atrq.db_trq); 570 sc->atrs.top = STAILQ_FIRST(&sc->atrs.db_trq); 571 sc->atrq.bottom = sc->atrq.top; 572 sc->atrs.bottom = sc->atrs.top; 573 574 for( i = 0, db_tr = sc->atrq.top; i < sc->atrq.ndb ; 575 i ++, db_tr = STAILQ_NEXT(db_tr, link)){ 576 db_tr->xfer = NULL; 577 } 578 for( i = 0, db_tr = sc->atrs.top; i < sc->atrs.ndb ; 579 i ++, db_tr = STAILQ_NEXT(db_tr, link)){ 580 db_tr->xfer = NULL; 581 } 582 583 584 /* Enable interrupts */ 585 sc->intmask = (OHCI_INT_ERR | OHCI_INT_PHY_SID 586 | OHCI_INT_DMA_ATRQ | OHCI_INT_DMA_ATRS 587 | OHCI_INT_DMA_PRRQ | OHCI_INT_DMA_PRRS 588 | OHCI_INT_PHY_BUS_R | OHCI_INT_PW_ERR); 589 sc->intmask |= OHCI_INT_DMA_IR | OHCI_INT_DMA_IT; 590 sc->intmask |= OHCI_INT_CYC_LOST | OHCI_INT_PHY_INT; 591 OWRITE(sc, FWOHCI_INTMASK, sc->intmask); 592 fwohci_set_intr(&sc->fc, 1); 593 594 } 595 596 int 597 fwohci_init(struct fwohci_softc *sc, device_t dev) 598 { 599 int i, mver; 600 uint32_t reg; 601 uint8_t ui[8]; 602 603 /* OHCI version */ 604 reg = OREAD(sc, OHCI_VERSION); 605 mver = (reg >> 16) & 0xff; 606 device_printf(dev, "OHCI version %x.%x (ROM=%d)\n", 607 mver, reg & 0xff, (reg>>24) & 1); 608 if (mver < 1 || mver > 9) { 609 device_printf(dev, "invalid OHCI version\n"); 610 return (ENXIO); 611 } 612 613 /* Available Isochronous DMA channel probe */ 614 OWRITE(sc, OHCI_IT_MASK, 0xffffffff); 615 OWRITE(sc, OHCI_IR_MASK, 0xffffffff); 616 reg = OREAD(sc, OHCI_IT_MASK) & OREAD(sc, OHCI_IR_MASK); 617 OWRITE(sc, OHCI_IT_MASKCLR, 0xffffffff); 618 OWRITE(sc, OHCI_IR_MASKCLR, 0xffffffff); 619 for (i = 0; i < 0x20; i++) 620 if ((reg & (1 << i)) == 0) 621 break; 622 sc->fc.nisodma = i; 623 device_printf(dev, "No. of Isochronous channels is %d.\n", i); 624 if (i == 0) 625 return (ENXIO); 626 627 sc->fc.arq = &sc->arrq.xferq; 628 sc->fc.ars = &sc->arrs.xferq; 629 sc->fc.atq = &sc->atrq.xferq; 630 sc->fc.ats = &sc->atrs.xferq; 631 632 sc->arrq.xferq.psize = roundup2(FWPMAX_S400, PAGE_SIZE); 633 sc->arrs.xferq.psize = roundup2(FWPMAX_S400, PAGE_SIZE); 634 sc->atrq.xferq.psize = roundup2(FWPMAX_S400, PAGE_SIZE); 635 sc->atrs.xferq.psize = roundup2(FWPMAX_S400, PAGE_SIZE); 636 637 sc->arrq.xferq.start = NULL; 638 sc->arrs.xferq.start = NULL; 639 sc->atrq.xferq.start = fwohci_start_atq; 640 sc->atrs.xferq.start = fwohci_start_ats; 641 642 sc->arrq.xferq.buf = NULL; 643 sc->arrs.xferq.buf = NULL; 644 sc->atrq.xferq.buf = NULL; 645 sc->atrs.xferq.buf = NULL; 646 647 sc->arrq.xferq.dmach = -1; 648 sc->arrs.xferq.dmach = -1; 649 sc->atrq.xferq.dmach = -1; 650 sc->atrs.xferq.dmach = -1; 651 652 sc->arrq.ndesc = 1; 653 sc->arrs.ndesc = 1; 654 sc->atrq.ndesc = 8; /* equal to maximum of mbuf chains */ 655 sc->atrs.ndesc = 2; 656 657 sc->arrq.ndb = NDB; 658 sc->arrs.ndb = NDB / 2; 659 sc->atrq.ndb = NDB; 660 sc->atrs.ndb = NDB / 2; 661 662 for( i = 0 ; i < sc->fc.nisodma ; i ++ ){ 663 sc->fc.it[i] = &sc->it[i].xferq; 664 sc->fc.ir[i] = &sc->ir[i].xferq; 665 sc->it[i].xferq.dmach = i; 666 sc->ir[i].xferq.dmach = i; 667 sc->it[i].ndb = 0; 668 sc->ir[i].ndb = 0; 669 } 670 671 sc->fc.tcode = tinfo; 672 sc->fc.dev = dev; 673 674 sc->fc.config_rom = fwdma_malloc(&sc->fc, CROMSIZE, CROMSIZE, 675 &sc->crom_dma, BUS_DMA_WAITOK | BUS_DMA_COHERENT); 676 if(sc->fc.config_rom == NULL){ 677 device_printf(dev, "config_rom alloc failed."); 678 return ENOMEM; 679 } 680 681 #if 0 682 bzero(&sc->fc.config_rom[0], CROMSIZE); 683 sc->fc.config_rom[1] = 0x31333934; 684 sc->fc.config_rom[2] = 0xf000a002; 685 sc->fc.config_rom[3] = OREAD(sc, OHCI_EUID_HI); 686 sc->fc.config_rom[4] = OREAD(sc, OHCI_EUID_LO); 687 sc->fc.config_rom[5] = 0; 688 sc->fc.config_rom[0] = (4 << 24) | (5 << 16); 689 690 sc->fc.config_rom[0] |= fw_crc16(&sc->fc.config_rom[1], 5*4); 691 #endif 692 693 694 /* SID recieve buffer must align 2^11 */ 695 #define OHCI_SIDSIZE (1 << 11) 696 sc->sid_buf = fwdma_malloc(&sc->fc, OHCI_SIDSIZE, OHCI_SIDSIZE, 697 &sc->sid_dma, BUS_DMA_WAITOK | BUS_DMA_COHERENT); 698 if (sc->sid_buf == NULL) { 699 device_printf(dev, "sid_buf alloc failed."); 700 return ENOMEM; 701 } 702 703 fwdma_malloc(&sc->fc, sizeof(uint32_t), sizeof(uint32_t), 704 &sc->dummy_dma, BUS_DMA_WAITOK); 705 706 if (sc->dummy_dma.v_addr == NULL) { 707 device_printf(dev, "dummy_dma alloc failed."); 708 return ENOMEM; 709 } 710 711 fwohci_db_init(sc, &sc->arrq); 712 if ((sc->arrq.flags & FWOHCI_DBCH_INIT) == 0) 713 return ENOMEM; 714 715 fwohci_db_init(sc, &sc->arrs); 716 if ((sc->arrs.flags & FWOHCI_DBCH_INIT) == 0) 717 return ENOMEM; 718 719 fwohci_db_init(sc, &sc->atrq); 720 if ((sc->atrq.flags & FWOHCI_DBCH_INIT) == 0) 721 return ENOMEM; 722 723 fwohci_db_init(sc, &sc->atrs); 724 if ((sc->atrs.flags & FWOHCI_DBCH_INIT) == 0) 725 return ENOMEM; 726 727 sc->fc.eui.hi = OREAD(sc, FWOHCIGUID_H); 728 sc->fc.eui.lo = OREAD(sc, FWOHCIGUID_L); 729 for( i = 0 ; i < 8 ; i ++) 730 ui[i] = FW_EUI64_BYTE(&sc->fc.eui,i); 731 device_printf(dev, "EUI64 %02x:%02x:%02x:%02x:%02x:%02x:%02x:%02x\n", 732 ui[0], ui[1], ui[2], ui[3], ui[4], ui[5], ui[6], ui[7]); 733 734 sc->fc.ioctl = fwohci_ioctl; 735 sc->fc.cyctimer = fwohci_cyctimer; 736 sc->fc.set_bmr = fwohci_set_bus_manager; 737 sc->fc.ibr = fwohci_ibr; 738 sc->fc.irx_enable = fwohci_irx_enable; 739 sc->fc.irx_disable = fwohci_irx_disable; 740 741 sc->fc.itx_enable = fwohci_itxbuf_enable; 742 sc->fc.itx_disable = fwohci_itx_disable; 743 #if BYTE_ORDER == BIG_ENDIAN 744 sc->fc.irx_post = fwohci_irx_post; 745 #else 746 sc->fc.irx_post = NULL; 747 #endif 748 sc->fc.itx_post = NULL; 749 sc->fc.timeout = fwohci_timeout; 750 sc->fc.poll = fwohci_poll; 751 sc->fc.set_intr = fwohci_set_intr; 752 753 sc->intmask = sc->irstat = sc->itstat = 0; 754 755 /* Init task queue */ 756 sc->fc.taskqueue = taskqueue_create_fast("fw_taskq", M_WAITOK, 757 taskqueue_thread_enqueue, &sc->fc.taskqueue); 758 taskqueue_start_threads(&sc->fc.taskqueue, 1, PI_NET, "fw%d_taskq", 759 device_get_unit(dev)); 760 TASK_INIT(&sc->fwohci_task_busreset, 2, fwohci_task_busreset, sc); 761 TASK_INIT(&sc->fwohci_task_sid, 1, fwohci_task_sid, sc); 762 TASK_INIT(&sc->fwohci_task_dma, 0, fwohci_task_dma, sc); 763 764 fw_init(&sc->fc); 765 fwohci_reset(sc, dev); 766 767 return 0; 768 } 769 770 void 771 fwohci_timeout(void *arg) 772 { 773 struct fwohci_softc *sc; 774 775 sc = (struct fwohci_softc *)arg; 776 } 777 778 uint32_t 779 fwohci_cyctimer(struct firewire_comm *fc) 780 { 781 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 782 return(OREAD(sc, OHCI_CYCLETIMER)); 783 } 784 785 int 786 fwohci_detach(struct fwohci_softc *sc, device_t dev) 787 { 788 int i; 789 790 if (sc->sid_buf != NULL) 791 fwdma_free(&sc->fc, &sc->sid_dma); 792 if (sc->fc.config_rom != NULL) 793 fwdma_free(&sc->fc, &sc->crom_dma); 794 795 fwohci_db_free(&sc->arrq); 796 fwohci_db_free(&sc->arrs); 797 798 fwohci_db_free(&sc->atrq); 799 fwohci_db_free(&sc->atrs); 800 801 for( i = 0 ; i < sc->fc.nisodma ; i ++ ){ 802 fwohci_db_free(&sc->it[i]); 803 fwohci_db_free(&sc->ir[i]); 804 } 805 if (sc->fc.taskqueue != NULL) { 806 taskqueue_drain(sc->fc.taskqueue, &sc->fwohci_task_busreset); 807 taskqueue_drain(sc->fc.taskqueue, &sc->fwohci_task_sid); 808 taskqueue_drain(sc->fc.taskqueue, &sc->fwohci_task_dma); 809 taskqueue_drain(sc->fc.taskqueue, &sc->fc.task_timeout); 810 taskqueue_free(sc->fc.taskqueue); 811 sc->fc.taskqueue = NULL; 812 } 813 814 return 0; 815 } 816 817 #define LAST_DB(dbtr, db) do { \ 818 struct fwohcidb_tr *_dbtr = (dbtr); \ 819 int _cnt = _dbtr->dbcnt; \ 820 db = &_dbtr->db[ (_cnt > 2) ? (_cnt -1) : 0]; \ 821 } while (0) 822 823 static void 824 fwohci_execute_db(void *arg, bus_dma_segment_t *segs, int nseg, int error) 825 { 826 struct fwohcidb_tr *db_tr; 827 struct fwohcidb *db; 828 bus_dma_segment_t *s; 829 int i; 830 831 db_tr = (struct fwohcidb_tr *)arg; 832 db = &db_tr->db[db_tr->dbcnt]; 833 if (error) { 834 if (firewire_debug || error != EFBIG) 835 printf("fwohci_execute_db: error=%d\n", error); 836 return; 837 } 838 for (i = 0; i < nseg; i++) { 839 s = &segs[i]; 840 FWOHCI_DMA_WRITE(db->db.desc.addr, s->ds_addr); 841 FWOHCI_DMA_WRITE(db->db.desc.cmd, s->ds_len); 842 FWOHCI_DMA_WRITE(db->db.desc.res, 0); 843 db++; 844 db_tr->dbcnt++; 845 } 846 } 847 848 static void 849 fwohci_execute_db2(void *arg, bus_dma_segment_t *segs, int nseg, 850 bus_size_t size, int error) 851 { 852 fwohci_execute_db(arg, segs, nseg, error); 853 } 854 855 static void 856 fwohci_start(struct fwohci_softc *sc, struct fwohci_dbch *dbch) 857 { 858 int i, s; 859 int tcode, hdr_len, pl_off; 860 int fsegment = -1; 861 uint32_t off; 862 struct fw_xfer *xfer; 863 struct fw_pkt *fp; 864 struct fwohci_txpkthdr *ohcifp; 865 struct fwohcidb_tr *db_tr; 866 struct fwohcidb *db; 867 uint32_t *ld; 868 struct tcode_info *info; 869 static int maxdesc=0; 870 871 FW_GLOCK_ASSERT(&sc->fc); 872 873 if(&sc->atrq == dbch){ 874 off = OHCI_ATQOFF; 875 }else if(&sc->atrs == dbch){ 876 off = OHCI_ATSOFF; 877 }else{ 878 return; 879 } 880 881 if (dbch->flags & FWOHCI_DBCH_FULL) 882 return; 883 884 s = splfw(); 885 db_tr = dbch->top; 886 txloop: 887 xfer = STAILQ_FIRST(&dbch->xferq.q); 888 if(xfer == NULL){ 889 goto kick; 890 } 891 #if 0 892 if(dbch->xferq.queued == 0 ){ 893 device_printf(sc->fc.dev, "TX queue empty\n"); 894 } 895 #endif 896 STAILQ_REMOVE_HEAD(&dbch->xferq.q, link); 897 db_tr->xfer = xfer; 898 xfer->flag = FWXF_START; 899 900 fp = &xfer->send.hdr; 901 tcode = fp->mode.common.tcode; 902 903 ohcifp = (struct fwohci_txpkthdr *) db_tr->db[1].db.immed; 904 info = &tinfo[tcode]; 905 hdr_len = pl_off = info->hdr_len; 906 907 ld = &ohcifp->mode.ld[0]; 908 ld[0] = ld[1] = ld[2] = ld[3] = 0; 909 for( i = 0 ; i < pl_off ; i+= 4) 910 ld[i/4] = fp->mode.ld[i/4]; 911 912 ohcifp->mode.common.spd = xfer->send.spd & 0x7; 913 if (tcode == FWTCODE_STREAM ){ 914 hdr_len = 8; 915 ohcifp->mode.stream.len = fp->mode.stream.len; 916 } else if (tcode == FWTCODE_PHY) { 917 hdr_len = 12; 918 ld[1] = fp->mode.ld[1]; 919 ld[2] = fp->mode.ld[2]; 920 ohcifp->mode.common.spd = 0; 921 ohcifp->mode.common.tcode = FWOHCITCODE_PHY; 922 } else { 923 ohcifp->mode.asycomm.dst = fp->mode.hdr.dst; 924 ohcifp->mode.asycomm.srcbus = OHCI_ASYSRCBUS; 925 ohcifp->mode.asycomm.tlrt |= FWRETRY_X; 926 } 927 db = &db_tr->db[0]; 928 FWOHCI_DMA_WRITE(db->db.desc.cmd, 929 OHCI_OUTPUT_MORE | OHCI_KEY_ST2 | hdr_len); 930 FWOHCI_DMA_WRITE(db->db.desc.addr, 0); 931 FWOHCI_DMA_WRITE(db->db.desc.res, 0); 932 /* Specify bound timer of asy. responce */ 933 if(&sc->atrs == dbch){ 934 FWOHCI_DMA_WRITE(db->db.desc.res, 935 (OREAD(sc, OHCI_CYCLETIMER) >> 12) + (1 << 13)); 936 } 937 #if BYTE_ORDER == BIG_ENDIAN 938 if (tcode == FWTCODE_WREQQ || tcode == FWTCODE_RRESQ) 939 hdr_len = 12; 940 for (i = 0; i < hdr_len/4; i ++) 941 FWOHCI_DMA_WRITE(ld[i], ld[i]); 942 #endif 943 944 again: 945 db_tr->dbcnt = 2; 946 db = &db_tr->db[db_tr->dbcnt]; 947 if (xfer->send.pay_len > 0) { 948 int err; 949 /* handle payload */ 950 if (xfer->mbuf == NULL) { 951 err = bus_dmamap_load(dbch->dmat, db_tr->dma_map, 952 &xfer->send.payload[0], xfer->send.pay_len, 953 fwohci_execute_db, db_tr, 954 /*flags*/0); 955 } else { 956 /* XXX we can handle only 6 (=8-2) mbuf chains */ 957 err = bus_dmamap_load_mbuf(dbch->dmat, db_tr->dma_map, 958 xfer->mbuf, 959 fwohci_execute_db2, db_tr, 960 /* flags */0); 961 if (err == EFBIG) { 962 struct mbuf *m0; 963 964 if (firewire_debug) 965 device_printf(sc->fc.dev, "EFBIG.\n"); 966 m0 = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 967 if (m0 != NULL) { 968 m_copydata(xfer->mbuf, 0, 969 xfer->mbuf->m_pkthdr.len, 970 mtod(m0, caddr_t)); 971 m0->m_len = m0->m_pkthdr.len = 972 xfer->mbuf->m_pkthdr.len; 973 m_freem(xfer->mbuf); 974 xfer->mbuf = m0; 975 goto again; 976 } 977 device_printf(sc->fc.dev, "m_getcl failed.\n"); 978 } 979 } 980 if (err) 981 printf("dmamap_load: err=%d\n", err); 982 bus_dmamap_sync(dbch->dmat, db_tr->dma_map, 983 BUS_DMASYNC_PREWRITE); 984 #if 0 /* OHCI_OUTPUT_MODE == 0 */ 985 for (i = 2; i < db_tr->dbcnt; i++) 986 FWOHCI_DMA_SET(db_tr->db[i].db.desc.cmd, 987 OHCI_OUTPUT_MORE); 988 #endif 989 } 990 if (maxdesc < db_tr->dbcnt) { 991 maxdesc = db_tr->dbcnt; 992 if (firewire_debug) 993 device_printf(sc->fc.dev, "%s: maxdesc %d\n", __func__, maxdesc); 994 } 995 /* last db */ 996 LAST_DB(db_tr, db); 997 FWOHCI_DMA_SET(db->db.desc.cmd, 998 OHCI_OUTPUT_LAST | OHCI_INTERRUPT_ALWAYS | OHCI_BRANCH_ALWAYS); 999 FWOHCI_DMA_WRITE(db->db.desc.depend, 1000 STAILQ_NEXT(db_tr, link)->bus_addr); 1001 1002 if(fsegment == -1 ) 1003 fsegment = db_tr->dbcnt; 1004 if (dbch->pdb_tr != NULL) { 1005 LAST_DB(dbch->pdb_tr, db); 1006 FWOHCI_DMA_SET(db->db.desc.depend, db_tr->dbcnt); 1007 } 1008 dbch->xferq.queued ++; 1009 dbch->pdb_tr = db_tr; 1010 db_tr = STAILQ_NEXT(db_tr, link); 1011 if(db_tr != dbch->bottom){ 1012 goto txloop; 1013 } else { 1014 device_printf(sc->fc.dev, "fwohci_start: lack of db_trq\n"); 1015 dbch->flags |= FWOHCI_DBCH_FULL; 1016 } 1017 kick: 1018 /* kick asy q */ 1019 fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREREAD); 1020 fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREWRITE); 1021 1022 if(dbch->xferq.flag & FWXFERQ_RUNNING) { 1023 OWRITE(sc, OHCI_DMACTL(off), OHCI_CNTL_DMA_WAKE); 1024 } else { 1025 if (firewire_debug) 1026 device_printf(sc->fc.dev, "start AT DMA status=%x\n", 1027 OREAD(sc, OHCI_DMACTL(off))); 1028 OWRITE(sc, OHCI_DMACMD(off), dbch->top->bus_addr | fsegment); 1029 OWRITE(sc, OHCI_DMACTL(off), OHCI_CNTL_DMA_RUN); 1030 dbch->xferq.flag |= FWXFERQ_RUNNING; 1031 } 1032 1033 dbch->top = db_tr; 1034 splx(s); 1035 return; 1036 } 1037 1038 static void 1039 fwohci_start_atq(struct firewire_comm *fc) 1040 { 1041 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 1042 FW_GLOCK(&sc->fc); 1043 fwohci_start( sc, &(sc->atrq)); 1044 FW_GUNLOCK(&sc->fc); 1045 return; 1046 } 1047 1048 static void 1049 fwohci_start_ats(struct firewire_comm *fc) 1050 { 1051 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 1052 FW_GLOCK(&sc->fc); 1053 fwohci_start( sc, &(sc->atrs)); 1054 FW_GUNLOCK(&sc->fc); 1055 return; 1056 } 1057 1058 void 1059 fwohci_txd(struct fwohci_softc *sc, struct fwohci_dbch *dbch) 1060 { 1061 int s, ch, err = 0; 1062 struct fwohcidb_tr *tr; 1063 struct fwohcidb *db; 1064 struct fw_xfer *xfer; 1065 uint32_t off; 1066 u_int stat, status; 1067 int packets; 1068 struct firewire_comm *fc = (struct firewire_comm *)sc; 1069 1070 if(&sc->atrq == dbch){ 1071 off = OHCI_ATQOFF; 1072 ch = ATRQ_CH; 1073 }else if(&sc->atrs == dbch){ 1074 off = OHCI_ATSOFF; 1075 ch = ATRS_CH; 1076 }else{ 1077 return; 1078 } 1079 s = splfw(); 1080 tr = dbch->bottom; 1081 packets = 0; 1082 fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_POSTREAD); 1083 fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_POSTWRITE); 1084 while(dbch->xferq.queued > 0){ 1085 LAST_DB(tr, db); 1086 status = FWOHCI_DMA_READ(db->db.desc.res) >> OHCI_STATUS_SHIFT; 1087 if(!(status & OHCI_CNTL_DMA_ACTIVE)){ 1088 if (fc->status != FWBUSINIT) 1089 /* maybe out of order?? */ 1090 goto out; 1091 } 1092 bus_dmamap_sync(dbch->dmat, tr->dma_map, 1093 BUS_DMASYNC_POSTWRITE); 1094 bus_dmamap_unload(dbch->dmat, tr->dma_map); 1095 #if 1 1096 if (firewire_debug > 1) 1097 dump_db(sc, ch); 1098 #endif 1099 if(status & OHCI_CNTL_DMA_DEAD) { 1100 /* Stop DMA */ 1101 OWRITE(sc, OHCI_DMACTLCLR(off), OHCI_CNTL_DMA_RUN); 1102 device_printf(sc->fc.dev, "force reset AT FIFO\n"); 1103 OWRITE(sc, OHCI_HCCCTLCLR, OHCI_HCC_LINKEN); 1104 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_LPS | OHCI_HCC_LINKEN); 1105 OWRITE(sc, OHCI_DMACTLCLR(off), OHCI_CNTL_DMA_RUN); 1106 } 1107 stat = status & FWOHCIEV_MASK; 1108 switch(stat){ 1109 case FWOHCIEV_ACKPEND: 1110 case FWOHCIEV_ACKCOMPL: 1111 err = 0; 1112 break; 1113 case FWOHCIEV_ACKBSA: 1114 case FWOHCIEV_ACKBSB: 1115 case FWOHCIEV_ACKBSX: 1116 err = EBUSY; 1117 break; 1118 case FWOHCIEV_FLUSHED: 1119 case FWOHCIEV_ACKTARD: 1120 err = EAGAIN; 1121 break; 1122 case FWOHCIEV_MISSACK: 1123 case FWOHCIEV_UNDRRUN: 1124 case FWOHCIEV_OVRRUN: 1125 case FWOHCIEV_DESCERR: 1126 case FWOHCIEV_DTRDERR: 1127 case FWOHCIEV_TIMEOUT: 1128 case FWOHCIEV_TCODERR: 1129 case FWOHCIEV_UNKNOWN: 1130 case FWOHCIEV_ACKDERR: 1131 case FWOHCIEV_ACKTERR: 1132 default: 1133 err = EINVAL; 1134 break; 1135 } 1136 if (tr->xfer != NULL) { 1137 xfer = tr->xfer; 1138 if (xfer->flag & FWXF_RCVD) { 1139 #if 0 1140 if (firewire_debug) 1141 printf("already rcvd\n"); 1142 #endif 1143 fw_xfer_done(xfer); 1144 } else { 1145 microtime(&xfer->tv); 1146 xfer->flag = FWXF_SENT; 1147 if (err == EBUSY) { 1148 xfer->flag = FWXF_BUSY; 1149 xfer->resp = err; 1150 xfer->recv.pay_len = 0; 1151 fw_xfer_done(xfer); 1152 } else if (stat != FWOHCIEV_ACKPEND) { 1153 if (stat != FWOHCIEV_ACKCOMPL) 1154 xfer->flag = FWXF_SENTERR; 1155 xfer->resp = err; 1156 xfer->recv.pay_len = 0; 1157 fw_xfer_done(xfer); 1158 } 1159 } 1160 /* 1161 * The watchdog timer takes care of split 1162 * transcation timeout for ACKPEND case. 1163 */ 1164 } else { 1165 printf("this shouldn't happen\n"); 1166 } 1167 FW_GLOCK(fc); 1168 dbch->xferq.queued --; 1169 FW_GUNLOCK(fc); 1170 tr->xfer = NULL; 1171 1172 packets ++; 1173 tr = STAILQ_NEXT(tr, link); 1174 dbch->bottom = tr; 1175 if (dbch->bottom == dbch->top) { 1176 /* we reaches the end of context program */ 1177 if (firewire_debug && dbch->xferq.queued > 0) 1178 printf("queued > 0\n"); 1179 break; 1180 } 1181 } 1182 out: 1183 if ((dbch->flags & FWOHCI_DBCH_FULL) && packets > 0) { 1184 printf("make free slot\n"); 1185 dbch->flags &= ~FWOHCI_DBCH_FULL; 1186 FW_GLOCK(fc); 1187 fwohci_start(sc, dbch); 1188 FW_GUNLOCK(fc); 1189 } 1190 splx(s); 1191 } 1192 1193 static void 1194 fwohci_db_free(struct fwohci_dbch *dbch) 1195 { 1196 struct fwohcidb_tr *db_tr; 1197 int idb; 1198 1199 if ((dbch->flags & FWOHCI_DBCH_INIT) == 0) 1200 return; 1201 1202 for(db_tr = STAILQ_FIRST(&dbch->db_trq), idb = 0; idb < dbch->ndb; 1203 db_tr = STAILQ_NEXT(db_tr, link), idb++){ 1204 if ((dbch->xferq.flag & FWXFERQ_EXTBUF) == 0 && 1205 db_tr->buf != NULL) { 1206 fwdma_free_size(dbch->dmat, db_tr->dma_map, 1207 db_tr->buf, dbch->xferq.psize); 1208 db_tr->buf = NULL; 1209 } else if (db_tr->dma_map != NULL) 1210 bus_dmamap_destroy(dbch->dmat, db_tr->dma_map); 1211 } 1212 dbch->ndb = 0; 1213 db_tr = STAILQ_FIRST(&dbch->db_trq); 1214 fwdma_free_multiseg(dbch->am); 1215 free(db_tr, M_FW); 1216 STAILQ_INIT(&dbch->db_trq); 1217 dbch->flags &= ~FWOHCI_DBCH_INIT; 1218 } 1219 1220 static void 1221 fwohci_db_init(struct fwohci_softc *sc, struct fwohci_dbch *dbch) 1222 { 1223 int idb; 1224 struct fwohcidb_tr *db_tr; 1225 1226 if ((dbch->flags & FWOHCI_DBCH_INIT) != 0) 1227 goto out; 1228 1229 /* create dma_tag for buffers */ 1230 #define MAX_REQCOUNT 0xffff 1231 if (bus_dma_tag_create(/*parent*/ sc->fc.dmat, 1232 /*alignment*/ 1, /*boundary*/ 0, 1233 /*lowaddr*/ BUS_SPACE_MAXADDR_32BIT, 1234 /*highaddr*/ BUS_SPACE_MAXADDR, 1235 /*filter*/NULL, /*filterarg*/NULL, 1236 /*maxsize*/ dbch->xferq.psize, 1237 /*nsegments*/ dbch->ndesc > 3 ? dbch->ndesc - 2 : 1, 1238 /*maxsegsz*/ MAX_REQCOUNT, 1239 /*flags*/ 0, 1240 #if defined(__FreeBSD__) && __FreeBSD_version >= 501102 1241 /*lockfunc*/busdma_lock_mutex, 1242 /*lockarg*/FW_GMTX(&sc->fc), 1243 #endif 1244 &dbch->dmat)) 1245 return; 1246 1247 /* allocate DB entries and attach one to each DMA channels */ 1248 /* DB entry must start at 16 bytes bounary. */ 1249 STAILQ_INIT(&dbch->db_trq); 1250 db_tr = (struct fwohcidb_tr *) 1251 malloc(sizeof(struct fwohcidb_tr) * dbch->ndb, 1252 M_FW, M_WAITOK | M_ZERO); 1253 if(db_tr == NULL){ 1254 printf("fwohci_db_init: malloc(1) failed\n"); 1255 return; 1256 } 1257 1258 #define DB_SIZE(x) (sizeof(struct fwohcidb) * (x)->ndesc) 1259 dbch->am = fwdma_malloc_multiseg(&sc->fc, DB_SIZE(dbch), 1260 DB_SIZE(dbch), dbch->ndb, BUS_DMA_WAITOK); 1261 if (dbch->am == NULL) { 1262 printf("fwohci_db_init: fwdma_malloc_multiseg failed\n"); 1263 free(db_tr, M_FW); 1264 return; 1265 } 1266 /* Attach DB to DMA ch. */ 1267 for(idb = 0 ; idb < dbch->ndb ; idb++){ 1268 db_tr->dbcnt = 0; 1269 db_tr->db = (struct fwohcidb *)fwdma_v_addr(dbch->am, idb); 1270 db_tr->bus_addr = fwdma_bus_addr(dbch->am, idb); 1271 /* create dmamap for buffers */ 1272 /* XXX do we need 4bytes alignment tag? */ 1273 /* XXX don't alloc dma_map for AR */ 1274 if (bus_dmamap_create(dbch->dmat, 0, &db_tr->dma_map) != 0) { 1275 printf("bus_dmamap_create failed\n"); 1276 dbch->flags = FWOHCI_DBCH_INIT; /* XXX fake */ 1277 fwohci_db_free(dbch); 1278 return; 1279 } 1280 STAILQ_INSERT_TAIL(&dbch->db_trq, db_tr, link); 1281 if (dbch->xferq.flag & FWXFERQ_EXTBUF) { 1282 if (idb % dbch->xferq.bnpacket == 0) 1283 dbch->xferq.bulkxfer[idb / dbch->xferq.bnpacket 1284 ].start = (caddr_t)db_tr; 1285 if ((idb + 1) % dbch->xferq.bnpacket == 0) 1286 dbch->xferq.bulkxfer[idb / dbch->xferq.bnpacket 1287 ].end = (caddr_t)db_tr; 1288 } 1289 db_tr++; 1290 } 1291 STAILQ_LAST(&dbch->db_trq, fwohcidb_tr,link)->link.stqe_next 1292 = STAILQ_FIRST(&dbch->db_trq); 1293 out: 1294 dbch->xferq.queued = 0; 1295 dbch->pdb_tr = NULL; 1296 dbch->top = STAILQ_FIRST(&dbch->db_trq); 1297 dbch->bottom = dbch->top; 1298 dbch->flags = FWOHCI_DBCH_INIT; 1299 } 1300 1301 static int 1302 fwohci_itx_disable(struct firewire_comm *fc, int dmach) 1303 { 1304 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 1305 1306 OWRITE(sc, OHCI_ITCTLCLR(dmach), 1307 OHCI_CNTL_DMA_RUN | OHCI_CNTL_CYCMATCH_S); 1308 OWRITE(sc, OHCI_IT_MASKCLR, 1 << dmach); 1309 OWRITE(sc, OHCI_IT_STATCLR, 1 << dmach); 1310 /* XXX we cannot free buffers until the DMA really stops */ 1311 pause("fwitxd", hz); 1312 fwohci_db_free(&sc->it[dmach]); 1313 sc->it[dmach].xferq.flag &= ~FWXFERQ_RUNNING; 1314 return 0; 1315 } 1316 1317 static int 1318 fwohci_irx_disable(struct firewire_comm *fc, int dmach) 1319 { 1320 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 1321 1322 OWRITE(sc, OHCI_IRCTLCLR(dmach), OHCI_CNTL_DMA_RUN); 1323 OWRITE(sc, OHCI_IR_MASKCLR, 1 << dmach); 1324 OWRITE(sc, OHCI_IR_STATCLR, 1 << dmach); 1325 /* XXX we cannot free buffers until the DMA really stops */ 1326 pause("fwirxd", hz); 1327 fwohci_db_free(&sc->ir[dmach]); 1328 sc->ir[dmach].xferq.flag &= ~FWXFERQ_RUNNING; 1329 return 0; 1330 } 1331 1332 #if BYTE_ORDER == BIG_ENDIAN 1333 static void 1334 fwohci_irx_post (struct firewire_comm *fc , uint32_t *qld) 1335 { 1336 qld[0] = FWOHCI_DMA_READ(qld[0]); 1337 return; 1338 } 1339 #endif 1340 1341 static int 1342 fwohci_tx_enable(struct fwohci_softc *sc, struct fwohci_dbch *dbch) 1343 { 1344 int err = 0; 1345 int idb, z, i, dmach = 0, ldesc; 1346 uint32_t off = 0; 1347 struct fwohcidb_tr *db_tr; 1348 struct fwohcidb *db; 1349 1350 if(!(dbch->xferq.flag & FWXFERQ_EXTBUF)){ 1351 err = EINVAL; 1352 return err; 1353 } 1354 z = dbch->ndesc; 1355 for(dmach = 0 ; dmach < sc->fc.nisodma ; dmach++){ 1356 if( &sc->it[dmach] == dbch){ 1357 off = OHCI_ITOFF(dmach); 1358 break; 1359 } 1360 } 1361 if(off == 0){ 1362 err = EINVAL; 1363 return err; 1364 } 1365 if(dbch->xferq.flag & FWXFERQ_RUNNING) 1366 return err; 1367 dbch->xferq.flag |= FWXFERQ_RUNNING; 1368 for( i = 0, dbch->bottom = dbch->top; i < (dbch->ndb - 1); i++){ 1369 dbch->bottom = STAILQ_NEXT(dbch->bottom, link); 1370 } 1371 db_tr = dbch->top; 1372 for (idb = 0; idb < dbch->ndb; idb ++) { 1373 fwohci_add_tx_buf(dbch, db_tr, idb); 1374 if(STAILQ_NEXT(db_tr, link) == NULL){ 1375 break; 1376 } 1377 db = db_tr->db; 1378 ldesc = db_tr->dbcnt - 1; 1379 FWOHCI_DMA_WRITE(db[0].db.desc.depend, 1380 STAILQ_NEXT(db_tr, link)->bus_addr | z); 1381 db[ldesc].db.desc.depend = db[0].db.desc.depend; 1382 if(dbch->xferq.flag & FWXFERQ_EXTBUF){ 1383 if(((idb + 1 ) % dbch->xferq.bnpacket) == 0){ 1384 FWOHCI_DMA_SET( 1385 db[ldesc].db.desc.cmd, 1386 OHCI_INTERRUPT_ALWAYS); 1387 /* OHCI 1.1 and above */ 1388 FWOHCI_DMA_SET( 1389 db[0].db.desc.cmd, 1390 OHCI_INTERRUPT_ALWAYS); 1391 } 1392 } 1393 db_tr = STAILQ_NEXT(db_tr, link); 1394 } 1395 FWOHCI_DMA_CLEAR( 1396 dbch->bottom->db[dbch->bottom->dbcnt - 1].db.desc.depend, 0xf); 1397 return err; 1398 } 1399 1400 static int 1401 fwohci_rx_enable(struct fwohci_softc *sc, struct fwohci_dbch *dbch) 1402 { 1403 int err = 0; 1404 int idb, z, i, dmach = 0, ldesc; 1405 uint32_t off = 0; 1406 struct fwohcidb_tr *db_tr; 1407 struct fwohcidb *db; 1408 1409 z = dbch->ndesc; 1410 if(&sc->arrq == dbch){ 1411 off = OHCI_ARQOFF; 1412 }else if(&sc->arrs == dbch){ 1413 off = OHCI_ARSOFF; 1414 }else{ 1415 for(dmach = 0 ; dmach < sc->fc.nisodma ; dmach++){ 1416 if( &sc->ir[dmach] == dbch){ 1417 off = OHCI_IROFF(dmach); 1418 break; 1419 } 1420 } 1421 } 1422 if(off == 0){ 1423 err = EINVAL; 1424 return err; 1425 } 1426 if(dbch->xferq.flag & FWXFERQ_STREAM){ 1427 if(dbch->xferq.flag & FWXFERQ_RUNNING) 1428 return err; 1429 }else{ 1430 if(dbch->xferq.flag & FWXFERQ_RUNNING){ 1431 err = EBUSY; 1432 return err; 1433 } 1434 } 1435 dbch->xferq.flag |= FWXFERQ_RUNNING; 1436 dbch->top = STAILQ_FIRST(&dbch->db_trq); 1437 for( i = 0, dbch->bottom = dbch->top; i < (dbch->ndb - 1); i++){ 1438 dbch->bottom = STAILQ_NEXT(dbch->bottom, link); 1439 } 1440 db_tr = dbch->top; 1441 for (idb = 0; idb < dbch->ndb; idb ++) { 1442 fwohci_add_rx_buf(dbch, db_tr, idb, &sc->dummy_dma); 1443 if (STAILQ_NEXT(db_tr, link) == NULL) 1444 break; 1445 db = db_tr->db; 1446 ldesc = db_tr->dbcnt - 1; 1447 FWOHCI_DMA_WRITE(db[ldesc].db.desc.depend, 1448 STAILQ_NEXT(db_tr, link)->bus_addr | z); 1449 if(dbch->xferq.flag & FWXFERQ_EXTBUF){ 1450 if(((idb + 1 ) % dbch->xferq.bnpacket) == 0){ 1451 FWOHCI_DMA_SET( 1452 db[ldesc].db.desc.cmd, 1453 OHCI_INTERRUPT_ALWAYS); 1454 FWOHCI_DMA_CLEAR( 1455 db[ldesc].db.desc.depend, 1456 0xf); 1457 } 1458 } 1459 db_tr = STAILQ_NEXT(db_tr, link); 1460 } 1461 FWOHCI_DMA_CLEAR( 1462 dbch->bottom->db[db_tr->dbcnt - 1].db.desc.depend, 0xf); 1463 dbch->buf_offset = 0; 1464 fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREREAD); 1465 fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREWRITE); 1466 if(dbch->xferq.flag & FWXFERQ_STREAM){ 1467 return err; 1468 }else{ 1469 OWRITE(sc, OHCI_DMACMD(off), dbch->top->bus_addr | z); 1470 } 1471 OWRITE(sc, OHCI_DMACTL(off), OHCI_CNTL_DMA_RUN); 1472 return err; 1473 } 1474 1475 static int 1476 fwohci_next_cycle(struct firewire_comm *fc, int cycle_now) 1477 { 1478 int sec, cycle, cycle_match; 1479 1480 cycle = cycle_now & 0x1fff; 1481 sec = cycle_now >> 13; 1482 #define CYCLE_MOD 0x10 1483 #if 1 1484 #define CYCLE_DELAY 8 /* min delay to start DMA */ 1485 #else 1486 #define CYCLE_DELAY 7000 /* min delay to start DMA */ 1487 #endif 1488 cycle = cycle + CYCLE_DELAY; 1489 if (cycle >= 8000) { 1490 sec ++; 1491 cycle -= 8000; 1492 } 1493 cycle = roundup2(cycle, CYCLE_MOD); 1494 if (cycle >= 8000) { 1495 sec ++; 1496 if (cycle == 8000) 1497 cycle = 0; 1498 else 1499 cycle = CYCLE_MOD; 1500 } 1501 cycle_match = ((sec << 13) | cycle) & 0x7ffff; 1502 1503 return(cycle_match); 1504 } 1505 1506 static int 1507 fwohci_itxbuf_enable(struct firewire_comm *fc, int dmach) 1508 { 1509 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 1510 int err = 0; 1511 unsigned short tag, ich; 1512 struct fwohci_dbch *dbch; 1513 int cycle_match, cycle_now, s, ldesc; 1514 uint32_t stat; 1515 struct fw_bulkxfer *first, *chunk, *prev; 1516 struct fw_xferq *it; 1517 1518 dbch = &sc->it[dmach]; 1519 it = &dbch->xferq; 1520 1521 tag = (it->flag >> 6) & 3; 1522 ich = it->flag & 0x3f; 1523 if ((dbch->flags & FWOHCI_DBCH_INIT) == 0) { 1524 dbch->ndb = it->bnpacket * it->bnchunk; 1525 dbch->ndesc = 3; 1526 fwohci_db_init(sc, dbch); 1527 if ((dbch->flags & FWOHCI_DBCH_INIT) == 0) 1528 return ENOMEM; 1529 1530 err = fwohci_tx_enable(sc, dbch); 1531 } 1532 if(err) 1533 return err; 1534 1535 ldesc = dbch->ndesc - 1; 1536 s = splfw(); 1537 FW_GLOCK(fc); 1538 prev = STAILQ_LAST(&it->stdma, fw_bulkxfer, link); 1539 while ((chunk = STAILQ_FIRST(&it->stvalid)) != NULL) { 1540 struct fwohcidb *db; 1541 1542 fwdma_sync_multiseg(it->buf, chunk->poffset, it->bnpacket, 1543 BUS_DMASYNC_PREWRITE); 1544 fwohci_txbufdb(sc, dmach, chunk); 1545 if (prev != NULL) { 1546 db = ((struct fwohcidb_tr *)(prev->end))->db; 1547 #if 0 /* XXX necessary? */ 1548 FWOHCI_DMA_SET(db[ldesc].db.desc.cmd, 1549 OHCI_BRANCH_ALWAYS); 1550 #endif 1551 #if 0 /* if bulkxfer->npacket changes */ 1552 db[ldesc].db.desc.depend = db[0].db.desc.depend = 1553 ((struct fwohcidb_tr *) 1554 (chunk->start))->bus_addr | dbch->ndesc; 1555 #else 1556 FWOHCI_DMA_SET(db[0].db.desc.depend, dbch->ndesc); 1557 FWOHCI_DMA_SET(db[ldesc].db.desc.depend, dbch->ndesc); 1558 #endif 1559 } 1560 STAILQ_REMOVE_HEAD(&it->stvalid, link); 1561 STAILQ_INSERT_TAIL(&it->stdma, chunk, link); 1562 prev = chunk; 1563 } 1564 FW_GUNLOCK(fc); 1565 fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREWRITE); 1566 fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREREAD); 1567 splx(s); 1568 stat = OREAD(sc, OHCI_ITCTL(dmach)); 1569 if (firewire_debug && (stat & OHCI_CNTL_CYCMATCH_S)) 1570 printf("stat 0x%x\n", stat); 1571 1572 if (stat & (OHCI_CNTL_DMA_ACTIVE | OHCI_CNTL_CYCMATCH_S)) 1573 return 0; 1574 1575 #if 0 1576 OWRITE(sc, OHCI_ITCTLCLR(dmach), OHCI_CNTL_DMA_RUN); 1577 #endif 1578 OWRITE(sc, OHCI_IT_MASKCLR, 1 << dmach); 1579 OWRITE(sc, OHCI_IT_STATCLR, 1 << dmach); 1580 OWRITE(sc, OHCI_IT_MASK, 1 << dmach); 1581 OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_DMA_IT); 1582 1583 first = STAILQ_FIRST(&it->stdma); 1584 OWRITE(sc, OHCI_ITCMD(dmach), 1585 ((struct fwohcidb_tr *)(first->start))->bus_addr | dbch->ndesc); 1586 if (firewire_debug > 1) { 1587 printf("fwohci_itxbuf_enable: kick 0x%08x\n", stat); 1588 #if 1 1589 dump_dma(sc, ITX_CH + dmach); 1590 #endif 1591 } 1592 if ((stat & OHCI_CNTL_DMA_RUN) == 0) { 1593 #if 1 1594 /* Don't start until all chunks are buffered */ 1595 if (STAILQ_FIRST(&it->stfree) != NULL) 1596 goto out; 1597 #endif 1598 #if 1 1599 /* Clear cycle match counter bits */ 1600 OWRITE(sc, OHCI_ITCTLCLR(dmach), 0xffff0000); 1601 1602 /* 2bit second + 13bit cycle */ 1603 cycle_now = (fc->cyctimer(fc) >> 12) & 0x7fff; 1604 cycle_match = fwohci_next_cycle(fc, cycle_now); 1605 1606 OWRITE(sc, OHCI_ITCTL(dmach), 1607 OHCI_CNTL_CYCMATCH_S | (cycle_match << 16) 1608 | OHCI_CNTL_DMA_RUN); 1609 #else 1610 OWRITE(sc, OHCI_ITCTL(dmach), OHCI_CNTL_DMA_RUN); 1611 #endif 1612 if (firewire_debug > 1) { 1613 printf("cycle_match: 0x%04x->0x%04x\n", 1614 cycle_now, cycle_match); 1615 dump_dma(sc, ITX_CH + dmach); 1616 dump_db(sc, ITX_CH + dmach); 1617 } 1618 } else if ((stat & OHCI_CNTL_CYCMATCH_S) == 0) { 1619 device_printf(sc->fc.dev, 1620 "IT DMA underrun (0x%08x)\n", stat); 1621 OWRITE(sc, OHCI_ITCTL(dmach), OHCI_CNTL_DMA_WAKE); 1622 } 1623 out: 1624 return err; 1625 } 1626 1627 static int 1628 fwohci_irx_enable(struct firewire_comm *fc, int dmach) 1629 { 1630 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 1631 int err = 0, s, ldesc; 1632 unsigned short tag, ich; 1633 uint32_t stat; 1634 struct fwohci_dbch *dbch; 1635 struct fwohcidb_tr *db_tr; 1636 struct fw_bulkxfer *first, *prev, *chunk; 1637 struct fw_xferq *ir; 1638 1639 dbch = &sc->ir[dmach]; 1640 ir = &dbch->xferq; 1641 1642 if ((ir->flag & FWXFERQ_RUNNING) == 0) { 1643 tag = (ir->flag >> 6) & 3; 1644 ich = ir->flag & 0x3f; 1645 OWRITE(sc, OHCI_IRMATCH(dmach), tagbit[tag] | ich); 1646 1647 ir->queued = 0; 1648 dbch->ndb = ir->bnpacket * ir->bnchunk; 1649 dbch->ndesc = 2; 1650 fwohci_db_init(sc, dbch); 1651 if ((dbch->flags & FWOHCI_DBCH_INIT) == 0) 1652 return ENOMEM; 1653 err = fwohci_rx_enable(sc, dbch); 1654 } 1655 if(err) 1656 return err; 1657 1658 first = STAILQ_FIRST(&ir->stfree); 1659 if (first == NULL) { 1660 device_printf(fc->dev, "IR DMA no free chunk\n"); 1661 return 0; 1662 } 1663 1664 ldesc = dbch->ndesc - 1; 1665 s = splfw(); 1666 if ((ir->flag & FWXFERQ_HANDLER) == 0) 1667 FW_GLOCK(fc); 1668 prev = STAILQ_LAST(&ir->stdma, fw_bulkxfer, link); 1669 while ((chunk = STAILQ_FIRST(&ir->stfree)) != NULL) { 1670 struct fwohcidb *db; 1671 1672 #if 1 /* XXX for if_fwe */ 1673 if (chunk->mbuf != NULL) { 1674 db_tr = (struct fwohcidb_tr *)(chunk->start); 1675 db_tr->dbcnt = 1; 1676 err = bus_dmamap_load_mbuf(dbch->dmat, db_tr->dma_map, 1677 chunk->mbuf, fwohci_execute_db2, db_tr, 1678 /* flags */0); 1679 FWOHCI_DMA_SET(db_tr->db[1].db.desc.cmd, 1680 OHCI_UPDATE | OHCI_INPUT_LAST | 1681 OHCI_INTERRUPT_ALWAYS | OHCI_BRANCH_ALWAYS); 1682 } 1683 #endif 1684 db = ((struct fwohcidb_tr *)(chunk->end))->db; 1685 FWOHCI_DMA_WRITE(db[ldesc].db.desc.res, 0); 1686 FWOHCI_DMA_CLEAR(db[ldesc].db.desc.depend, 0xf); 1687 if (prev != NULL) { 1688 db = ((struct fwohcidb_tr *)(prev->end))->db; 1689 FWOHCI_DMA_SET(db[ldesc].db.desc.depend, dbch->ndesc); 1690 } 1691 STAILQ_REMOVE_HEAD(&ir->stfree, link); 1692 STAILQ_INSERT_TAIL(&ir->stdma, chunk, link); 1693 prev = chunk; 1694 } 1695 if ((ir->flag & FWXFERQ_HANDLER) == 0) 1696 FW_GUNLOCK(fc); 1697 fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREWRITE); 1698 fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREREAD); 1699 splx(s); 1700 stat = OREAD(sc, OHCI_IRCTL(dmach)); 1701 if (stat & OHCI_CNTL_DMA_ACTIVE) 1702 return 0; 1703 if (stat & OHCI_CNTL_DMA_RUN) { 1704 OWRITE(sc, OHCI_IRCTLCLR(dmach), OHCI_CNTL_DMA_RUN); 1705 device_printf(sc->fc.dev, "IR DMA overrun (0x%08x)\n", stat); 1706 } 1707 1708 if (firewire_debug) 1709 printf("start IR DMA 0x%x\n", stat); 1710 OWRITE(sc, OHCI_IR_MASKCLR, 1 << dmach); 1711 OWRITE(sc, OHCI_IR_STATCLR, 1 << dmach); 1712 OWRITE(sc, OHCI_IR_MASK, 1 << dmach); 1713 OWRITE(sc, OHCI_IRCTLCLR(dmach), 0xf0000000); 1714 OWRITE(sc, OHCI_IRCTL(dmach), OHCI_CNTL_ISOHDR); 1715 OWRITE(sc, OHCI_IRCMD(dmach), 1716 ((struct fwohcidb_tr *)(first->start))->bus_addr 1717 | dbch->ndesc); 1718 OWRITE(sc, OHCI_IRCTL(dmach), OHCI_CNTL_DMA_RUN); 1719 OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_DMA_IR); 1720 #if 0 1721 dump_db(sc, IRX_CH + dmach); 1722 #endif 1723 return err; 1724 } 1725 1726 int 1727 fwohci_stop(struct fwohci_softc *sc, device_t dev) 1728 { 1729 u_int i; 1730 1731 fwohci_set_intr(&sc->fc, 0); 1732 1733 /* Now stopping all DMA channel */ 1734 OWRITE(sc, OHCI_ARQCTLCLR, OHCI_CNTL_DMA_RUN); 1735 OWRITE(sc, OHCI_ARSCTLCLR, OHCI_CNTL_DMA_RUN); 1736 OWRITE(sc, OHCI_ATQCTLCLR, OHCI_CNTL_DMA_RUN); 1737 OWRITE(sc, OHCI_ATSCTLCLR, OHCI_CNTL_DMA_RUN); 1738 1739 for( i = 0 ; i < sc->fc.nisodma ; i ++ ){ 1740 OWRITE(sc, OHCI_IRCTLCLR(i), OHCI_CNTL_DMA_RUN); 1741 OWRITE(sc, OHCI_ITCTLCLR(i), OHCI_CNTL_DMA_RUN); 1742 } 1743 1744 #if 0 /* Let dcons(4) be accessed */ 1745 /* Stop interrupt */ 1746 OWRITE(sc, FWOHCI_INTMASKCLR, 1747 OHCI_INT_EN | OHCI_INT_ERR | OHCI_INT_PHY_SID 1748 | OHCI_INT_PHY_INT 1749 | OHCI_INT_DMA_ATRQ | OHCI_INT_DMA_ATRS 1750 | OHCI_INT_DMA_PRRQ | OHCI_INT_DMA_PRRS 1751 | OHCI_INT_DMA_ARRQ | OHCI_INT_DMA_ARRS 1752 | OHCI_INT_PHY_BUS_R); 1753 1754 /* FLUSH FIFO and reset Transmitter/Reciever */ 1755 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_RESET); 1756 #endif 1757 1758 /* XXX Link down? Bus reset? */ 1759 return 0; 1760 } 1761 1762 int 1763 fwohci_resume(struct fwohci_softc *sc, device_t dev) 1764 { 1765 int i; 1766 struct fw_xferq *ir; 1767 struct fw_bulkxfer *chunk; 1768 1769 fwohci_reset(sc, dev); 1770 /* XXX resume isochronous receive automatically. (how about TX?) */ 1771 for(i = 0; i < sc->fc.nisodma; i ++) { 1772 ir = &sc->ir[i].xferq; 1773 if((ir->flag & FWXFERQ_RUNNING) != 0) { 1774 device_printf(sc->fc.dev, 1775 "resume iso receive ch: %d\n", i); 1776 ir->flag &= ~FWXFERQ_RUNNING; 1777 /* requeue stdma to stfree */ 1778 while((chunk = STAILQ_FIRST(&ir->stdma)) != NULL) { 1779 STAILQ_REMOVE_HEAD(&ir->stdma, link); 1780 STAILQ_INSERT_TAIL(&ir->stfree, chunk, link); 1781 } 1782 sc->fc.irx_enable(&sc->fc, i); 1783 } 1784 } 1785 1786 bus_generic_resume(dev); 1787 sc->fc.ibr(&sc->fc); 1788 return 0; 1789 } 1790 1791 #ifdef OHCI_DEBUG 1792 static void 1793 fwohci_dump_intr(struct fwohci_softc *sc, uint32_t stat) 1794 { 1795 if(stat & OREAD(sc, FWOHCI_INTMASK)) 1796 device_printf(fc->dev, "INTERRUPT < %s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s> 0x%08x, 0x%08x\n", 1797 stat & OHCI_INT_EN ? "DMA_EN ":"", 1798 stat & OHCI_INT_PHY_REG ? "PHY_REG ":"", 1799 stat & OHCI_INT_CYC_LONG ? "CYC_LONG ":"", 1800 stat & OHCI_INT_ERR ? "INT_ERR ":"", 1801 stat & OHCI_INT_CYC_ERR ? "CYC_ERR ":"", 1802 stat & OHCI_INT_CYC_LOST ? "CYC_LOST ":"", 1803 stat & OHCI_INT_CYC_64SECOND ? "CYC_64SECOND ":"", 1804 stat & OHCI_INT_CYC_START ? "CYC_START ":"", 1805 stat & OHCI_INT_PHY_INT ? "PHY_INT ":"", 1806 stat & OHCI_INT_PHY_BUS_R ? "BUS_RESET ":"", 1807 stat & OHCI_INT_PHY_SID ? "SID ":"", 1808 stat & OHCI_INT_LR_ERR ? "DMA_LR_ERR ":"", 1809 stat & OHCI_INT_PW_ERR ? "DMA_PW_ERR ":"", 1810 stat & OHCI_INT_DMA_IR ? "DMA_IR ":"", 1811 stat & OHCI_INT_DMA_IT ? "DMA_IT " :"", 1812 stat & OHCI_INT_DMA_PRRS ? "DMA_PRRS " :"", 1813 stat & OHCI_INT_DMA_PRRQ ? "DMA_PRRQ " :"", 1814 stat & OHCI_INT_DMA_ARRS ? "DMA_ARRS " :"", 1815 stat & OHCI_INT_DMA_ARRQ ? "DMA_ARRQ " :"", 1816 stat & OHCI_INT_DMA_ATRS ? "DMA_ATRS " :"", 1817 stat & OHCI_INT_DMA_ATRQ ? "DMA_ATRQ " :"", 1818 stat, OREAD(sc, FWOHCI_INTMASK) 1819 ); 1820 } 1821 #endif 1822 static void 1823 fwohci_intr_core(struct fwohci_softc *sc, uint32_t stat, int count) 1824 { 1825 struct firewire_comm *fc = (struct firewire_comm *)sc; 1826 uint32_t node_id, plen; 1827 1828 FW_GLOCK_ASSERT(fc); 1829 if ((stat & OHCI_INT_PHY_BUS_R) && (fc->status != FWBUSRESET)) { 1830 fc->status = FWBUSRESET; 1831 /* Disable bus reset interrupt until sid recv. */ 1832 OWRITE(sc, FWOHCI_INTMASKCLR, OHCI_INT_PHY_BUS_R); 1833 1834 device_printf(fc->dev, "%s: BUS reset\n", __func__); 1835 OWRITE(sc, FWOHCI_INTMASKCLR, OHCI_INT_CYC_LOST); 1836 OWRITE(sc, OHCI_LNKCTLCLR, OHCI_CNTL_CYCSRC); 1837 1838 OWRITE(sc, OHCI_ATQCTLCLR, OHCI_CNTL_DMA_RUN); 1839 sc->atrq.xferq.flag &= ~FWXFERQ_RUNNING; 1840 OWRITE(sc, OHCI_ATSCTLCLR, OHCI_CNTL_DMA_RUN); 1841 sc->atrs.xferq.flag &= ~FWXFERQ_RUNNING; 1842 1843 if (!kdb_active) 1844 taskqueue_enqueue(sc->fc.taskqueue, &sc->fwohci_task_busreset); 1845 } 1846 if (stat & OHCI_INT_PHY_SID) { 1847 /* Enable bus reset interrupt */ 1848 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_PHY_BUS_R); 1849 OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_PHY_BUS_R); 1850 1851 /* Allow async. request to us */ 1852 OWRITE(sc, OHCI_AREQHI, 1 << 31); 1853 if (firewire_phydma_enable) { 1854 /* allow from all nodes */ 1855 OWRITE(sc, OHCI_PREQHI, 0x7fffffff); 1856 OWRITE(sc, OHCI_PREQLO, 0xffffffff); 1857 /* 0 to 4GB region */ 1858 OWRITE(sc, OHCI_PREQUPPER, 0x10000); 1859 } 1860 /* Set ATRetries register */ 1861 OWRITE(sc, OHCI_ATRETRY, 1<<(13+16) | 0xfff); 1862 1863 /* 1864 * Checking whether the node is root or not. If root, turn on 1865 * cycle master. 1866 */ 1867 node_id = OREAD(sc, FWOHCI_NODEID); 1868 plen = OREAD(sc, OHCI_SID_CNT); 1869 1870 fc->nodeid = node_id & 0x3f; 1871 device_printf(fc->dev, "%s: node_id=0x%08x, SelfID Count=%d, ", 1872 __func__, fc->nodeid, (plen >> 16) & 0xff); 1873 if (!(node_id & OHCI_NODE_VALID)) { 1874 device_printf(fc->dev, "%s: Bus reset failure\n", 1875 __func__); 1876 goto sidout; 1877 } 1878 1879 /* cycle timer */ 1880 sc->cycle_lost = 0; 1881 OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_CYC_LOST); 1882 if ((node_id & OHCI_NODE_ROOT) && !nocyclemaster) { 1883 printf("CYCLEMASTER mode\n"); 1884 OWRITE(sc, OHCI_LNKCTL, 1885 OHCI_CNTL_CYCMTR | OHCI_CNTL_CYCTIMER); 1886 } else { 1887 printf("non CYCLEMASTER mode\n"); 1888 OWRITE(sc, OHCI_LNKCTLCLR, OHCI_CNTL_CYCMTR); 1889 OWRITE(sc, OHCI_LNKCTL, OHCI_CNTL_CYCTIMER); 1890 } 1891 1892 fc->status = FWBUSINIT; 1893 1894 if (!kdb_active) 1895 taskqueue_enqueue(sc->fc.taskqueue, &sc->fwohci_task_sid); 1896 } 1897 sidout: 1898 if ((stat & ~(OHCI_INT_PHY_BUS_R | OHCI_INT_PHY_SID)) && (!kdb_active)) 1899 taskqueue_enqueue(sc->fc.taskqueue, &sc->fwohci_task_dma); 1900 } 1901 1902 static void 1903 fwohci_intr_dma(struct fwohci_softc *sc, uint32_t stat, int count) 1904 { 1905 uint32_t irstat, itstat; 1906 u_int i; 1907 struct firewire_comm *fc = (struct firewire_comm *)sc; 1908 1909 if (stat & OHCI_INT_DMA_IR) { 1910 irstat = atomic_readandclear_int(&sc->irstat); 1911 for(i = 0; i < fc->nisodma ; i++){ 1912 struct fwohci_dbch *dbch; 1913 1914 if((irstat & (1 << i)) != 0){ 1915 dbch = &sc->ir[i]; 1916 if ((dbch->xferq.flag & FWXFERQ_OPEN) == 0) { 1917 device_printf(sc->fc.dev, 1918 "dma(%d) not active\n", i); 1919 continue; 1920 } 1921 fwohci_rbuf_update(sc, i); 1922 } 1923 } 1924 } 1925 if (stat & OHCI_INT_DMA_IT) { 1926 itstat = atomic_readandclear_int(&sc->itstat); 1927 for(i = 0; i < fc->nisodma ; i++){ 1928 if((itstat & (1 << i)) != 0){ 1929 fwohci_tbuf_update(sc, i); 1930 } 1931 } 1932 } 1933 if (stat & OHCI_INT_DMA_PRRS) { 1934 #if 0 1935 dump_dma(sc, ARRS_CH); 1936 dump_db(sc, ARRS_CH); 1937 #endif 1938 fwohci_arcv(sc, &sc->arrs, count); 1939 } 1940 if (stat & OHCI_INT_DMA_PRRQ) { 1941 #if 0 1942 dump_dma(sc, ARRQ_CH); 1943 dump_db(sc, ARRQ_CH); 1944 #endif 1945 fwohci_arcv(sc, &sc->arrq, count); 1946 } 1947 if (stat & OHCI_INT_CYC_LOST) { 1948 if (sc->cycle_lost >= 0) 1949 sc->cycle_lost ++; 1950 if (sc->cycle_lost > 10) { 1951 sc->cycle_lost = -1; 1952 #if 0 1953 OWRITE(sc, OHCI_LNKCTLCLR, OHCI_CNTL_CYCTIMER); 1954 #endif 1955 OWRITE(sc, FWOHCI_INTMASKCLR, OHCI_INT_CYC_LOST); 1956 device_printf(fc->dev, "too many cycles lost, " 1957 "no cycle master present?\n"); 1958 } 1959 } 1960 if (stat & OHCI_INT_DMA_ATRQ) { 1961 fwohci_txd(sc, &(sc->atrq)); 1962 } 1963 if (stat & OHCI_INT_DMA_ATRS) { 1964 fwohci_txd(sc, &(sc->atrs)); 1965 } 1966 if (stat & OHCI_INT_PW_ERR) { 1967 device_printf(fc->dev, "posted write error\n"); 1968 } 1969 if (stat & OHCI_INT_ERR) { 1970 device_printf(fc->dev, "unrecoverable error\n"); 1971 } 1972 if (stat & OHCI_INT_PHY_INT) { 1973 device_printf(fc->dev, "phy int\n"); 1974 } 1975 1976 return; 1977 } 1978 1979 static void 1980 fwohci_task_busreset(void *arg, int pending) 1981 { 1982 struct fwohci_softc *sc = (struct fwohci_softc *)arg; 1983 1984 FW_GLOCK(&sc->fc); 1985 fw_busreset(&sc->fc, FWBUSRESET); 1986 OWRITE(sc, OHCI_CROMHDR, ntohl(sc->fc.config_rom[0])); 1987 OWRITE(sc, OHCI_BUS_OPT, ntohl(sc->fc.config_rom[2])); 1988 FW_GUNLOCK(&sc->fc); 1989 } 1990 1991 static void 1992 fwohci_task_sid(void *arg, int pending) 1993 { 1994 struct fwohci_softc *sc = (struct fwohci_softc *)arg; 1995 struct firewire_comm *fc = &sc->fc; 1996 uint32_t *buf; 1997 int i, plen; 1998 1999 2000 /* 2001 * We really should have locking 2002 * here. Not sure why it's not 2003 */ 2004 plen = OREAD(sc, OHCI_SID_CNT); 2005 2006 if (plen & OHCI_SID_ERR) { 2007 device_printf(fc->dev, "SID Error\n"); 2008 return; 2009 } 2010 plen &= OHCI_SID_CNT_MASK; 2011 if (plen < 4 || plen > OHCI_SIDSIZE) { 2012 device_printf(fc->dev, "invalid SID len = %d\n", plen); 2013 return; 2014 } 2015 plen -= 4; /* chop control info */ 2016 buf = (uint32_t *)malloc(OHCI_SIDSIZE, M_FW, M_NOWAIT); 2017 if (buf == NULL) { 2018 device_printf(fc->dev, "malloc failed\n"); 2019 return; 2020 } 2021 for (i = 0; i < plen / 4; i ++) 2022 buf[i] = FWOHCI_DMA_READ(sc->sid_buf[i+1]); 2023 2024 /* pending all pre-bus_reset packets */ 2025 fwohci_txd(sc, &sc->atrq); 2026 fwohci_txd(sc, &sc->atrs); 2027 fwohci_arcv(sc, &sc->arrs, -1); 2028 fwohci_arcv(sc, &sc->arrq, -1); 2029 fw_drain_txq(fc); 2030 fw_sidrcv(fc, buf, plen); 2031 free(buf, M_FW); 2032 } 2033 2034 static void 2035 fwohci_task_dma(void *arg, int pending) 2036 { 2037 struct fwohci_softc *sc = (struct fwohci_softc *)arg; 2038 uint32_t stat; 2039 2040 again: 2041 stat = atomic_readandclear_int(&sc->intstat); 2042 if (stat) 2043 fwohci_intr_dma(sc, stat, -1); 2044 else 2045 return; 2046 goto again; 2047 } 2048 2049 static int 2050 fwohci_check_stat(struct fwohci_softc *sc) 2051 { 2052 uint32_t stat, irstat, itstat; 2053 2054 FW_GLOCK_ASSERT(&sc->fc); 2055 stat = OREAD(sc, FWOHCI_INTSTAT); 2056 if (stat == 0xffffffff) { 2057 if (!bus_child_present(sc->fc.dev)) 2058 return (FILTER_HANDLED); 2059 device_printf(sc->fc.dev, "device physically ejected?\n"); 2060 return (FILTER_STRAY); 2061 } 2062 if (stat) 2063 OWRITE(sc, FWOHCI_INTSTATCLR, stat & ~OHCI_INT_PHY_BUS_R); 2064 2065 stat &= sc->intmask; 2066 if (stat == 0) 2067 return (FILTER_STRAY); 2068 2069 atomic_set_int(&sc->intstat, stat); 2070 if (stat & OHCI_INT_DMA_IR) { 2071 irstat = OREAD(sc, OHCI_IR_STAT); 2072 OWRITE(sc, OHCI_IR_STATCLR, irstat); 2073 atomic_set_int(&sc->irstat, irstat); 2074 } 2075 if (stat & OHCI_INT_DMA_IT) { 2076 itstat = OREAD(sc, OHCI_IT_STAT); 2077 OWRITE(sc, OHCI_IT_STATCLR, itstat); 2078 atomic_set_int(&sc->itstat, itstat); 2079 } 2080 2081 fwohci_intr_core(sc, stat, -1); 2082 return (FILTER_HANDLED); 2083 } 2084 2085 void 2086 fwohci_intr(void *arg) 2087 { 2088 struct fwohci_softc *sc = (struct fwohci_softc *)arg; 2089 2090 FW_GLOCK(&sc->fc); 2091 fwohci_check_stat(sc); 2092 FW_GUNLOCK(&sc->fc); 2093 } 2094 2095 void 2096 fwohci_poll(struct firewire_comm *fc, int quick, int count) 2097 { 2098 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 2099 2100 FW_GLOCK(fc); 2101 fwohci_check_stat(sc); 2102 FW_GUNLOCK(fc); 2103 } 2104 2105 static void 2106 fwohci_set_intr(struct firewire_comm *fc, int enable) 2107 { 2108 struct fwohci_softc *sc; 2109 2110 sc = (struct fwohci_softc *)fc; 2111 if (firewire_debug) 2112 device_printf(sc->fc.dev, "fwohci_set_intr: %d\n", enable); 2113 if (enable) { 2114 sc->intmask |= OHCI_INT_EN; 2115 OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_EN); 2116 } else { 2117 sc->intmask &= ~OHCI_INT_EN; 2118 OWRITE(sc, FWOHCI_INTMASKCLR, OHCI_INT_EN); 2119 } 2120 } 2121 2122 static void 2123 fwohci_tbuf_update(struct fwohci_softc *sc, int dmach) 2124 { 2125 struct firewire_comm *fc = &sc->fc; 2126 struct fwohcidb *db; 2127 struct fw_bulkxfer *chunk; 2128 struct fw_xferq *it; 2129 uint32_t stat, count; 2130 int s, w=0, ldesc; 2131 2132 it = fc->it[dmach]; 2133 ldesc = sc->it[dmach].ndesc - 1; 2134 s = splfw(); /* unnecessary ? */ 2135 FW_GLOCK(fc); 2136 fwdma_sync_multiseg_all(sc->it[dmach].am, BUS_DMASYNC_POSTREAD); 2137 if (firewire_debug) 2138 dump_db(sc, ITX_CH + dmach); 2139 while ((chunk = STAILQ_FIRST(&it->stdma)) != NULL) { 2140 db = ((struct fwohcidb_tr *)(chunk->end))->db; 2141 stat = FWOHCI_DMA_READ(db[ldesc].db.desc.res) 2142 >> OHCI_STATUS_SHIFT; 2143 db = ((struct fwohcidb_tr *)(chunk->start))->db; 2144 /* timestamp */ 2145 count = FWOHCI_DMA_READ(db[ldesc].db.desc.res) 2146 & OHCI_COUNT_MASK; 2147 if (stat == 0) 2148 break; 2149 STAILQ_REMOVE_HEAD(&it->stdma, link); 2150 switch (stat & FWOHCIEV_MASK){ 2151 case FWOHCIEV_ACKCOMPL: 2152 #if 0 2153 device_printf(fc->dev, "0x%08x\n", count); 2154 #endif 2155 break; 2156 default: 2157 device_printf(fc->dev, 2158 "Isochronous transmit err %02x(%s)\n", 2159 stat, fwohcicode[stat & 0x1f]); 2160 } 2161 STAILQ_INSERT_TAIL(&it->stfree, chunk, link); 2162 w++; 2163 } 2164 FW_GUNLOCK(fc); 2165 splx(s); 2166 if (w) 2167 wakeup(it); 2168 } 2169 2170 static void 2171 fwohci_rbuf_update(struct fwohci_softc *sc, int dmach) 2172 { 2173 struct firewire_comm *fc = &sc->fc; 2174 struct fwohcidb_tr *db_tr; 2175 struct fw_bulkxfer *chunk; 2176 struct fw_xferq *ir; 2177 uint32_t stat; 2178 int s, w = 0, ldesc; 2179 2180 ir = fc->ir[dmach]; 2181 ldesc = sc->ir[dmach].ndesc - 1; 2182 2183 #if 0 2184 dump_db(sc, dmach); 2185 #endif 2186 s = splfw(); 2187 if ((ir->flag & FWXFERQ_HANDLER) == 0) 2188 FW_GLOCK(fc); 2189 fwdma_sync_multiseg_all(sc->ir[dmach].am, BUS_DMASYNC_POSTREAD); 2190 while ((chunk = STAILQ_FIRST(&ir->stdma)) != NULL) { 2191 db_tr = (struct fwohcidb_tr *)chunk->end; 2192 stat = FWOHCI_DMA_READ(db_tr->db[ldesc].db.desc.res) 2193 >> OHCI_STATUS_SHIFT; 2194 if (stat == 0) 2195 break; 2196 2197 if (chunk->mbuf != NULL) { 2198 bus_dmamap_sync(sc->ir[dmach].dmat, db_tr->dma_map, 2199 BUS_DMASYNC_POSTREAD); 2200 bus_dmamap_unload(sc->ir[dmach].dmat, db_tr->dma_map); 2201 } else if (ir->buf != NULL) { 2202 fwdma_sync_multiseg(ir->buf, chunk->poffset, 2203 ir->bnpacket, BUS_DMASYNC_POSTREAD); 2204 } else { 2205 /* XXX */ 2206 printf("fwohci_rbuf_update: this shouldn't happend\n"); 2207 } 2208 2209 STAILQ_REMOVE_HEAD(&ir->stdma, link); 2210 STAILQ_INSERT_TAIL(&ir->stvalid, chunk, link); 2211 switch (stat & FWOHCIEV_MASK) { 2212 case FWOHCIEV_ACKCOMPL: 2213 chunk->resp = 0; 2214 break; 2215 default: 2216 chunk->resp = EINVAL; 2217 device_printf(fc->dev, 2218 "Isochronous receive err %02x(%s)\n", 2219 stat, fwohcicode[stat & 0x1f]); 2220 } 2221 w++; 2222 } 2223 if ((ir->flag & FWXFERQ_HANDLER) == 0) 2224 FW_GUNLOCK(fc); 2225 splx(s); 2226 if (w == 0) 2227 return; 2228 2229 if (ir->flag & FWXFERQ_HANDLER) 2230 ir->hand(ir); 2231 else 2232 wakeup(ir); 2233 } 2234 2235 void 2236 dump_dma(struct fwohci_softc *sc, uint32_t ch) 2237 { 2238 uint32_t off, cntl, stat, cmd, match; 2239 2240 if(ch == 0){ 2241 off = OHCI_ATQOFF; 2242 }else if(ch == 1){ 2243 off = OHCI_ATSOFF; 2244 }else if(ch == 2){ 2245 off = OHCI_ARQOFF; 2246 }else if(ch == 3){ 2247 off = OHCI_ARSOFF; 2248 }else if(ch < IRX_CH){ 2249 off = OHCI_ITCTL(ch - ITX_CH); 2250 }else{ 2251 off = OHCI_IRCTL(ch - IRX_CH); 2252 } 2253 cntl = stat = OREAD(sc, off); 2254 cmd = OREAD(sc, off + 0xc); 2255 match = OREAD(sc, off + 0x10); 2256 2257 device_printf(sc->fc.dev, "ch %1x cntl:0x%08x cmd:0x%08x match:0x%08x\n", 2258 ch, 2259 cntl, 2260 cmd, 2261 match); 2262 stat &= 0xffff ; 2263 if (stat) { 2264 device_printf(sc->fc.dev, "dma %d ch:%s%s%s%s%s%s %s(%x)\n", 2265 ch, 2266 stat & OHCI_CNTL_DMA_RUN ? "RUN," : "", 2267 stat & OHCI_CNTL_DMA_WAKE ? "WAKE," : "", 2268 stat & OHCI_CNTL_DMA_DEAD ? "DEAD," : "", 2269 stat & OHCI_CNTL_DMA_ACTIVE ? "ACTIVE," : "", 2270 stat & OHCI_CNTL_DMA_BT ? "BRANCH," : "", 2271 stat & OHCI_CNTL_DMA_BAD ? "BADDMA," : "", 2272 fwohcicode[stat & 0x1f], 2273 stat & 0x1f 2274 ); 2275 }else{ 2276 device_printf(sc->fc.dev, "dma %d ch: Nostat\n", ch); 2277 } 2278 } 2279 2280 void 2281 dump_db(struct fwohci_softc *sc, uint32_t ch) 2282 { 2283 struct fwohci_dbch *dbch; 2284 struct fwohcidb_tr *cp = NULL, *pp, *np = NULL; 2285 struct fwohcidb *curr = NULL, *prev, *next = NULL; 2286 int idb, jdb; 2287 uint32_t cmd, off; 2288 if(ch == 0){ 2289 off = OHCI_ATQOFF; 2290 dbch = &sc->atrq; 2291 }else if(ch == 1){ 2292 off = OHCI_ATSOFF; 2293 dbch = &sc->atrs; 2294 }else if(ch == 2){ 2295 off = OHCI_ARQOFF; 2296 dbch = &sc->arrq; 2297 }else if(ch == 3){ 2298 off = OHCI_ARSOFF; 2299 dbch = &sc->arrs; 2300 }else if(ch < IRX_CH){ 2301 off = OHCI_ITCTL(ch - ITX_CH); 2302 dbch = &sc->it[ch - ITX_CH]; 2303 }else { 2304 off = OHCI_IRCTL(ch - IRX_CH); 2305 dbch = &sc->ir[ch - IRX_CH]; 2306 } 2307 cmd = OREAD(sc, off + 0xc); 2308 2309 if( dbch->ndb == 0 ){ 2310 device_printf(sc->fc.dev, "No DB is attached ch=%d\n", ch); 2311 return; 2312 } 2313 pp = dbch->top; 2314 prev = pp->db; 2315 for(idb = 0 ; idb < dbch->ndb ; idb ++ ){ 2316 cp = STAILQ_NEXT(pp, link); 2317 if(cp == NULL){ 2318 curr = NULL; 2319 goto outdb; 2320 } 2321 np = STAILQ_NEXT(cp, link); 2322 for(jdb = 0 ; jdb < dbch->ndesc ; jdb ++ ){ 2323 if ((cmd & 0xfffffff0) == cp->bus_addr) { 2324 curr = cp->db; 2325 if(np != NULL){ 2326 next = np->db; 2327 }else{ 2328 next = NULL; 2329 } 2330 goto outdb; 2331 } 2332 } 2333 pp = STAILQ_NEXT(pp, link); 2334 if(pp == NULL){ 2335 curr = NULL; 2336 goto outdb; 2337 } 2338 prev = pp->db; 2339 } 2340 outdb: 2341 if( curr != NULL){ 2342 #if 0 2343 printf("Prev DB %d\n", ch); 2344 print_db(pp, prev, ch, dbch->ndesc); 2345 #endif 2346 printf("Current DB %d\n", ch); 2347 print_db(cp, curr, ch, dbch->ndesc); 2348 #if 0 2349 printf("Next DB %d\n", ch); 2350 print_db(np, next, ch, dbch->ndesc); 2351 #endif 2352 }else{ 2353 printf("dbdump err ch = %d cmd = 0x%08x\n", ch, cmd); 2354 } 2355 return; 2356 } 2357 2358 void 2359 print_db(struct fwohcidb_tr *db_tr, struct fwohcidb *db, 2360 uint32_t ch, uint32_t max) 2361 { 2362 fwohcireg_t stat; 2363 int i, key; 2364 uint32_t cmd, res; 2365 2366 if(db == NULL){ 2367 printf("No Descriptor is found\n"); 2368 return; 2369 } 2370 2371 printf("ch = %d\n%8s %s %s %s %s %4s %8s %8s %4s:%4s\n", 2372 ch, 2373 "Current", 2374 "OP ", 2375 "KEY", 2376 "INT", 2377 "BR ", 2378 "len", 2379 "Addr", 2380 "Depend", 2381 "Stat", 2382 "Cnt"); 2383 for( i = 0 ; i <= max ; i ++){ 2384 cmd = FWOHCI_DMA_READ(db[i].db.desc.cmd); 2385 res = FWOHCI_DMA_READ(db[i].db.desc.res); 2386 key = cmd & OHCI_KEY_MASK; 2387 stat = res >> OHCI_STATUS_SHIFT; 2388 #if defined(__DragonFly__) || __FreeBSD_version < 500000 2389 printf("%08x %s %s %s %s %5d %08x %08x %04x:%04x", 2390 db_tr->bus_addr, 2391 #else 2392 printf("%08jx %s %s %s %s %5d %08x %08x %04x:%04x", 2393 (uintmax_t)db_tr->bus_addr, 2394 #endif 2395 dbcode[(cmd >> 28) & 0xf], 2396 dbkey[(cmd >> 24) & 0x7], 2397 dbcond[(cmd >> 20) & 0x3], 2398 dbcond[(cmd >> 18) & 0x3], 2399 cmd & OHCI_COUNT_MASK, 2400 FWOHCI_DMA_READ(db[i].db.desc.addr), 2401 FWOHCI_DMA_READ(db[i].db.desc.depend), 2402 stat, 2403 res & OHCI_COUNT_MASK); 2404 if(stat & 0xff00){ 2405 printf(" %s%s%s%s%s%s %s(%x)\n", 2406 stat & OHCI_CNTL_DMA_RUN ? "RUN," : "", 2407 stat & OHCI_CNTL_DMA_WAKE ? "WAKE," : "", 2408 stat & OHCI_CNTL_DMA_DEAD ? "DEAD," : "", 2409 stat & OHCI_CNTL_DMA_ACTIVE ? "ACTIVE," : "", 2410 stat & OHCI_CNTL_DMA_BT ? "BRANCH," : "", 2411 stat & OHCI_CNTL_DMA_BAD ? "BADDMA," : "", 2412 fwohcicode[stat & 0x1f], 2413 stat & 0x1f 2414 ); 2415 }else{ 2416 printf(" Nostat\n"); 2417 } 2418 if(key == OHCI_KEY_ST2 ){ 2419 printf("0x%08x 0x%08x 0x%08x 0x%08x\n", 2420 FWOHCI_DMA_READ(db[i+1].db.immed[0]), 2421 FWOHCI_DMA_READ(db[i+1].db.immed[1]), 2422 FWOHCI_DMA_READ(db[i+1].db.immed[2]), 2423 FWOHCI_DMA_READ(db[i+1].db.immed[3])); 2424 } 2425 if(key == OHCI_KEY_DEVICE){ 2426 return; 2427 } 2428 if((cmd & OHCI_BRANCH_MASK) 2429 == OHCI_BRANCH_ALWAYS){ 2430 return; 2431 } 2432 if((cmd & OHCI_CMD_MASK) 2433 == OHCI_OUTPUT_LAST){ 2434 return; 2435 } 2436 if((cmd & OHCI_CMD_MASK) 2437 == OHCI_INPUT_LAST){ 2438 return; 2439 } 2440 if(key == OHCI_KEY_ST2 ){ 2441 i++; 2442 } 2443 } 2444 return; 2445 } 2446 2447 void 2448 fwohci_ibr(struct firewire_comm *fc) 2449 { 2450 struct fwohci_softc *sc; 2451 uint32_t fun; 2452 2453 device_printf(fc->dev, "Initiate bus reset\n"); 2454 sc = (struct fwohci_softc *)fc; 2455 2456 FW_GLOCK(fc); 2457 /* 2458 * Make sure our cached values from the config rom are 2459 * initialised. 2460 */ 2461 OWRITE(sc, OHCI_CROMHDR, ntohl(sc->fc.config_rom[0])); 2462 OWRITE(sc, OHCI_BUS_OPT, ntohl(sc->fc.config_rom[2])); 2463 2464 /* 2465 * Set root hold-off bit so that non cyclemaster capable node 2466 * shouldn't became the root node. 2467 */ 2468 #if 1 2469 fun = fwphy_rddata(sc, FW_PHY_IBR_REG); 2470 fun |= FW_PHY_IBR | FW_PHY_RHB; 2471 fun = fwphy_wrdata(sc, FW_PHY_IBR_REG, fun); 2472 #else /* Short bus reset */ 2473 fun = fwphy_rddata(sc, FW_PHY_ISBR_REG); 2474 fun |= FW_PHY_ISBR | FW_PHY_RHB; 2475 fun = fwphy_wrdata(sc, FW_PHY_ISBR_REG, fun); 2476 #endif 2477 FW_GUNLOCK(fc); 2478 } 2479 2480 void 2481 fwohci_txbufdb(struct fwohci_softc *sc, int dmach, struct fw_bulkxfer *bulkxfer) 2482 { 2483 struct fwohcidb_tr *db_tr, *fdb_tr; 2484 struct fwohci_dbch *dbch; 2485 struct fwohcidb *db; 2486 struct fw_pkt *fp; 2487 struct fwohci_txpkthdr *ohcifp; 2488 unsigned short chtag; 2489 int idb; 2490 2491 FW_GLOCK_ASSERT(&sc->fc); 2492 2493 dbch = &sc->it[dmach]; 2494 chtag = sc->it[dmach].xferq.flag & 0xff; 2495 2496 db_tr = (struct fwohcidb_tr *)(bulkxfer->start); 2497 fdb_tr = (struct fwohcidb_tr *)(bulkxfer->end); 2498 /* 2499 device_printf(sc->fc.dev, "DB %08x %08x %08x\n", bulkxfer, db_tr->bus_addr, fdb_tr->bus_addr); 2500 */ 2501 for (idb = 0; idb < dbch->xferq.bnpacket; idb ++) { 2502 db = db_tr->db; 2503 fp = (struct fw_pkt *)db_tr->buf; 2504 ohcifp = (struct fwohci_txpkthdr *) db[1].db.immed; 2505 ohcifp->mode.ld[0] = fp->mode.ld[0]; 2506 ohcifp->mode.common.spd = 0 & 0x7; 2507 ohcifp->mode.stream.len = fp->mode.stream.len; 2508 ohcifp->mode.stream.chtag = chtag; 2509 ohcifp->mode.stream.tcode = 0xa; 2510 #if BYTE_ORDER == BIG_ENDIAN 2511 FWOHCI_DMA_WRITE(db[1].db.immed[0], db[1].db.immed[0]); 2512 FWOHCI_DMA_WRITE(db[1].db.immed[1], db[1].db.immed[1]); 2513 #endif 2514 2515 FWOHCI_DMA_CLEAR(db[2].db.desc.cmd, OHCI_COUNT_MASK); 2516 FWOHCI_DMA_SET(db[2].db.desc.cmd, fp->mode.stream.len); 2517 FWOHCI_DMA_WRITE(db[2].db.desc.res, 0); 2518 #if 0 /* if bulkxfer->npackets changes */ 2519 db[2].db.desc.cmd = OHCI_OUTPUT_LAST 2520 | OHCI_UPDATE 2521 | OHCI_BRANCH_ALWAYS; 2522 db[0].db.desc.depend = 2523 = db[dbch->ndesc - 1].db.desc.depend 2524 = STAILQ_NEXT(db_tr, link)->bus_addr | dbch->ndesc; 2525 #else 2526 FWOHCI_DMA_SET(db[0].db.desc.depend, dbch->ndesc); 2527 FWOHCI_DMA_SET(db[dbch->ndesc - 1].db.desc.depend, dbch->ndesc); 2528 #endif 2529 bulkxfer->end = (caddr_t)db_tr; 2530 db_tr = STAILQ_NEXT(db_tr, link); 2531 } 2532 db = ((struct fwohcidb_tr *)bulkxfer->end)->db; 2533 FWOHCI_DMA_CLEAR(db[0].db.desc.depend, 0xf); 2534 FWOHCI_DMA_CLEAR(db[dbch->ndesc - 1].db.desc.depend, 0xf); 2535 #if 0 /* if bulkxfer->npackets changes */ 2536 db[dbch->ndesc - 1].db.desc.control |= OHCI_INTERRUPT_ALWAYS; 2537 /* OHCI 1.1 and above */ 2538 db[0].db.desc.control |= OHCI_INTERRUPT_ALWAYS; 2539 #endif 2540 /* 2541 db_tr = (struct fwohcidb_tr *)bulkxfer->start; 2542 fdb_tr = (struct fwohcidb_tr *)bulkxfer->end; 2543 device_printf(sc->fc.dev, "DB %08x %3d %08x %08x\n", bulkxfer, bulkxfer->npacket, db_tr->bus_addr, fdb_tr->bus_addr); 2544 */ 2545 return; 2546 } 2547 2548 static int 2549 fwohci_add_tx_buf(struct fwohci_dbch *dbch, struct fwohcidb_tr *db_tr, 2550 int poffset) 2551 { 2552 struct fwohcidb *db = db_tr->db; 2553 struct fw_xferq *it; 2554 int err = 0; 2555 2556 it = &dbch->xferq; 2557 if(it->buf == 0){ 2558 err = EINVAL; 2559 return err; 2560 } 2561 db_tr->buf = fwdma_v_addr(it->buf, poffset); 2562 db_tr->dbcnt = 3; 2563 2564 FWOHCI_DMA_WRITE(db[0].db.desc.cmd, 2565 OHCI_OUTPUT_MORE | OHCI_KEY_ST2 | 8); 2566 FWOHCI_DMA_WRITE(db[0].db.desc.addr, 0); 2567 bzero((void *)&db[1].db.immed[0], sizeof(db[1].db.immed)); 2568 FWOHCI_DMA_WRITE(db[2].db.desc.addr, 2569 fwdma_bus_addr(it->buf, poffset) + sizeof(uint32_t)); 2570 2571 FWOHCI_DMA_WRITE(db[2].db.desc.cmd, 2572 OHCI_OUTPUT_LAST | OHCI_UPDATE | OHCI_BRANCH_ALWAYS); 2573 #if 1 2574 FWOHCI_DMA_WRITE(db[0].db.desc.res, 0); 2575 FWOHCI_DMA_WRITE(db[2].db.desc.res, 0); 2576 #endif 2577 return 0; 2578 } 2579 2580 int 2581 fwohci_add_rx_buf(struct fwohci_dbch *dbch, struct fwohcidb_tr *db_tr, 2582 int poffset, struct fwdma_alloc *dummy_dma) 2583 { 2584 struct fwohcidb *db = db_tr->db; 2585 struct fw_xferq *ir; 2586 int i, ldesc; 2587 bus_addr_t dbuf[2]; 2588 int dsiz[2]; 2589 2590 ir = &dbch->xferq; 2591 if (ir->buf == NULL && (dbch->xferq.flag & FWXFERQ_EXTBUF) == 0) { 2592 if (db_tr->buf == NULL) { 2593 db_tr->buf = fwdma_malloc_size(dbch->dmat, 2594 &db_tr->dma_map, ir->psize, &dbuf[0], 2595 BUS_DMA_NOWAIT); 2596 if (db_tr->buf == NULL) 2597 return(ENOMEM); 2598 } 2599 db_tr->dbcnt = 1; 2600 dsiz[0] = ir->psize; 2601 bus_dmamap_sync(dbch->dmat, db_tr->dma_map, 2602 BUS_DMASYNC_PREREAD); 2603 } else { 2604 db_tr->dbcnt = 0; 2605 if (dummy_dma != NULL) { 2606 dsiz[db_tr->dbcnt] = sizeof(uint32_t); 2607 dbuf[db_tr->dbcnt++] = dummy_dma->bus_addr; 2608 } 2609 dsiz[db_tr->dbcnt] = ir->psize; 2610 if (ir->buf != NULL) { 2611 db_tr->buf = fwdma_v_addr(ir->buf, poffset); 2612 dbuf[db_tr->dbcnt] = fwdma_bus_addr( ir->buf, poffset); 2613 } 2614 db_tr->dbcnt++; 2615 } 2616 for(i = 0 ; i < db_tr->dbcnt ; i++){ 2617 FWOHCI_DMA_WRITE(db[i].db.desc.addr, dbuf[i]); 2618 FWOHCI_DMA_WRITE(db[i].db.desc.cmd, OHCI_INPUT_MORE | dsiz[i]); 2619 if (ir->flag & FWXFERQ_STREAM) { 2620 FWOHCI_DMA_SET(db[i].db.desc.cmd, OHCI_UPDATE); 2621 } 2622 FWOHCI_DMA_WRITE(db[i].db.desc.res, dsiz[i]); 2623 } 2624 ldesc = db_tr->dbcnt - 1; 2625 if (ir->flag & FWXFERQ_STREAM) { 2626 FWOHCI_DMA_SET(db[ldesc].db.desc.cmd, OHCI_INPUT_LAST); 2627 } 2628 FWOHCI_DMA_SET(db[ldesc].db.desc.cmd, OHCI_BRANCH_ALWAYS); 2629 return 0; 2630 } 2631 2632 2633 static int 2634 fwohci_arcv_swap(struct fw_pkt *fp, int len) 2635 { 2636 struct fw_pkt *fp0; 2637 uint32_t ld0; 2638 int slen, hlen; 2639 #if BYTE_ORDER == BIG_ENDIAN 2640 int i; 2641 #endif 2642 2643 ld0 = FWOHCI_DMA_READ(fp->mode.ld[0]); 2644 #if 0 2645 printf("ld0: x%08x\n", ld0); 2646 #endif 2647 fp0 = (struct fw_pkt *)&ld0; 2648 /* determine length to swap */ 2649 switch (fp0->mode.common.tcode) { 2650 case FWTCODE_RREQQ: 2651 case FWTCODE_WRES: 2652 case FWTCODE_WREQQ: 2653 case FWTCODE_RRESQ: 2654 case FWOHCITCODE_PHY: 2655 slen = 12; 2656 break; 2657 case FWTCODE_RREQB: 2658 case FWTCODE_WREQB: 2659 case FWTCODE_LREQ: 2660 case FWTCODE_RRESB: 2661 case FWTCODE_LRES: 2662 slen = 16; 2663 break; 2664 default: 2665 printf("Unknown tcode %d\n", fp0->mode.common.tcode); 2666 return(0); 2667 } 2668 hlen = tinfo[fp0->mode.common.tcode].hdr_len; 2669 if (hlen > len) { 2670 if (firewire_debug) 2671 printf("splitted header\n"); 2672 return(-hlen); 2673 } 2674 #if BYTE_ORDER == BIG_ENDIAN 2675 for(i = 0; i < slen/4; i ++) 2676 fp->mode.ld[i] = FWOHCI_DMA_READ(fp->mode.ld[i]); 2677 #endif 2678 return(hlen); 2679 } 2680 2681 static int 2682 fwohci_get_plen(struct fwohci_softc *sc, struct fwohci_dbch *dbch, struct fw_pkt *fp) 2683 { 2684 struct tcode_info *info; 2685 int r; 2686 2687 info = &tinfo[fp->mode.common.tcode]; 2688 r = info->hdr_len + sizeof(uint32_t); 2689 if ((info->flag & FWTI_BLOCK_ASY) != 0) 2690 r += roundup2(fp->mode.wreqb.len, sizeof(uint32_t)); 2691 2692 if (r == sizeof(uint32_t)) { 2693 /* XXX */ 2694 device_printf(sc->fc.dev, "Unknown tcode %d\n", 2695 fp->mode.common.tcode); 2696 return (-1); 2697 } 2698 2699 if (r > dbch->xferq.psize) { 2700 device_printf(sc->fc.dev, "Invalid packet length %d\n", r); 2701 return (-1); 2702 /* panic ? */ 2703 } 2704 2705 return r; 2706 } 2707 2708 static void 2709 fwohci_arcv_free_buf(struct fwohci_softc *sc, struct fwohci_dbch *dbch, 2710 struct fwohcidb_tr *db_tr, uint32_t off, int wake) 2711 { 2712 struct fwohcidb *db = &db_tr->db[0]; 2713 2714 FWOHCI_DMA_CLEAR(db->db.desc.depend, 0xf); 2715 FWOHCI_DMA_WRITE(db->db.desc.res, dbch->xferq.psize); 2716 FWOHCI_DMA_SET(dbch->bottom->db[0].db.desc.depend, 1); 2717 fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREWRITE); 2718 dbch->bottom = db_tr; 2719 2720 if (wake) 2721 OWRITE(sc, OHCI_DMACTL(off), OHCI_CNTL_DMA_WAKE); 2722 } 2723 2724 static void 2725 fwohci_arcv(struct fwohci_softc *sc, struct fwohci_dbch *dbch, int count) 2726 { 2727 struct fwohcidb_tr *db_tr; 2728 struct iovec vec[2]; 2729 struct fw_pkt pktbuf; 2730 int nvec; 2731 struct fw_pkt *fp; 2732 uint8_t *ld; 2733 uint32_t stat, off, status, event; 2734 u_int spd; 2735 int len, plen, hlen, pcnt, offset; 2736 int s; 2737 caddr_t buf; 2738 int resCount; 2739 2740 if(&sc->arrq == dbch){ 2741 off = OHCI_ARQOFF; 2742 }else if(&sc->arrs == dbch){ 2743 off = OHCI_ARSOFF; 2744 }else{ 2745 return; 2746 } 2747 2748 s = splfw(); 2749 db_tr = dbch->top; 2750 pcnt = 0; 2751 /* XXX we cannot handle a packet which lies in more than two buf */ 2752 fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_POSTREAD); 2753 fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_POSTWRITE); 2754 status = FWOHCI_DMA_READ(db_tr->db[0].db.desc.res) >> OHCI_STATUS_SHIFT; 2755 resCount = FWOHCI_DMA_READ(db_tr->db[0].db.desc.res) & OHCI_COUNT_MASK; 2756 while (status & OHCI_CNTL_DMA_ACTIVE) { 2757 #if 0 2758 2759 if (off == OHCI_ARQOFF) 2760 printf("buf 0x%08x, status 0x%04x, resCount 0x%04x\n", 2761 db_tr->bus_addr, status, resCount); 2762 #endif 2763 len = dbch->xferq.psize - resCount; 2764 ld = (uint8_t *)db_tr->buf; 2765 if (dbch->pdb_tr == NULL) { 2766 len -= dbch->buf_offset; 2767 ld += dbch->buf_offset; 2768 } 2769 if (len > 0) 2770 bus_dmamap_sync(dbch->dmat, db_tr->dma_map, 2771 BUS_DMASYNC_POSTREAD); 2772 while (len > 0 ) { 2773 if (count >= 0 && count-- == 0) 2774 goto out; 2775 if(dbch->pdb_tr != NULL){ 2776 /* we have a fragment in previous buffer */ 2777 int rlen; 2778 2779 offset = dbch->buf_offset; 2780 if (offset < 0) 2781 offset = - offset; 2782 buf = dbch->pdb_tr->buf + offset; 2783 rlen = dbch->xferq.psize - offset; 2784 if (firewire_debug) 2785 printf("rlen=%d, offset=%d\n", 2786 rlen, dbch->buf_offset); 2787 if (dbch->buf_offset < 0) { 2788 /* splitted in header, pull up */ 2789 char *p; 2790 2791 p = (char *)&pktbuf; 2792 bcopy(buf, p, rlen); 2793 p += rlen; 2794 /* this must be too long but harmless */ 2795 rlen = sizeof(pktbuf) - rlen; 2796 if (rlen < 0) 2797 printf("why rlen < 0\n"); 2798 bcopy(db_tr->buf, p, rlen); 2799 ld += rlen; 2800 len -= rlen; 2801 hlen = fwohci_arcv_swap(&pktbuf, sizeof(pktbuf)); 2802 if (hlen <= 0) { 2803 printf("hlen should be positive."); 2804 goto err; 2805 } 2806 offset = sizeof(pktbuf); 2807 vec[0].iov_base = (char *)&pktbuf; 2808 vec[0].iov_len = offset; 2809 } else { 2810 /* splitted in payload */ 2811 offset = rlen; 2812 vec[0].iov_base = buf; 2813 vec[0].iov_len = rlen; 2814 } 2815 fp=(struct fw_pkt *)vec[0].iov_base; 2816 nvec = 1; 2817 } else { 2818 /* no fragment in previous buffer */ 2819 fp=(struct fw_pkt *)ld; 2820 hlen = fwohci_arcv_swap(fp, len); 2821 if (hlen == 0) 2822 goto err; 2823 if (hlen < 0) { 2824 dbch->pdb_tr = db_tr; 2825 dbch->buf_offset = - dbch->buf_offset; 2826 /* sanity check */ 2827 if (resCount != 0) { 2828 printf("resCount=%d hlen=%d\n", 2829 resCount, hlen); 2830 goto err; 2831 } 2832 goto out; 2833 } 2834 offset = 0; 2835 nvec = 0; 2836 } 2837 plen = fwohci_get_plen(sc, dbch, fp) - offset; 2838 if (plen < 0) { 2839 /* minimum header size + trailer 2840 = sizeof(fw_pkt) so this shouldn't happens */ 2841 printf("plen(%d) is negative! offset=%d\n", 2842 plen, offset); 2843 goto err; 2844 } 2845 if (plen > 0) { 2846 len -= plen; 2847 if (len < 0) { 2848 dbch->pdb_tr = db_tr; 2849 if (firewire_debug) 2850 printf("splitted payload\n"); 2851 /* sanity check */ 2852 if (resCount != 0) { 2853 printf("resCount=%d plen=%d" 2854 " len=%d\n", 2855 resCount, plen, len); 2856 goto err; 2857 } 2858 goto out; 2859 } 2860 vec[nvec].iov_base = ld; 2861 vec[nvec].iov_len = plen; 2862 nvec ++; 2863 ld += plen; 2864 } 2865 dbch->buf_offset = ld - (uint8_t *)db_tr->buf; 2866 if (nvec == 0) 2867 printf("nvec == 0\n"); 2868 2869 /* DMA result-code will be written at the tail of packet */ 2870 stat = FWOHCI_DMA_READ(*(uint32_t *)(ld - sizeof(struct fwohci_trailer))); 2871 #if 0 2872 printf("plen: %d, stat %x\n", 2873 plen ,stat); 2874 #endif 2875 spd = (stat >> 21) & 0x3; 2876 event = (stat >> 16) & 0x1f; 2877 switch (event) { 2878 case FWOHCIEV_ACKPEND: 2879 #if 0 2880 printf("fwohci_arcv: ack pending tcode=0x%x..\n", fp->mode.common.tcode); 2881 #endif 2882 /* fall through */ 2883 case FWOHCIEV_ACKCOMPL: 2884 { 2885 struct fw_rcv_buf rb; 2886 2887 if ((vec[nvec-1].iov_len -= 2888 sizeof(struct fwohci_trailer)) == 0) 2889 nvec--; 2890 rb.fc = &sc->fc; 2891 rb.vec = vec; 2892 rb.nvec = nvec; 2893 rb.spd = spd; 2894 fw_rcv(&rb); 2895 break; 2896 } 2897 case FWOHCIEV_BUSRST: 2898 if ((sc->fc.status != FWBUSRESET) && 2899 (sc->fc.status != FWBUSINIT)) 2900 printf("got BUSRST packet!?\n"); 2901 break; 2902 default: 2903 device_printf(sc->fc.dev, 2904 "Async DMA Receive error err=%02x %s" 2905 " plen=%d offset=%d len=%d status=0x%08x" 2906 " tcode=0x%x, stat=0x%08x\n", 2907 event, fwohcicode[event], plen, 2908 dbch->buf_offset, len, 2909 OREAD(sc, OHCI_DMACTL(off)), 2910 fp->mode.common.tcode, stat); 2911 #if 1 /* XXX */ 2912 goto err; 2913 #endif 2914 break; 2915 } 2916 pcnt ++; 2917 if (dbch->pdb_tr != NULL) { 2918 fwohci_arcv_free_buf(sc, dbch, dbch->pdb_tr, 2919 off, 1); 2920 dbch->pdb_tr = NULL; 2921 } 2922 2923 } 2924 out: 2925 if (resCount == 0) { 2926 /* done on this buffer */ 2927 if (dbch->pdb_tr == NULL) { 2928 fwohci_arcv_free_buf(sc, dbch, db_tr, off, 1); 2929 dbch->buf_offset = 0; 2930 } else 2931 if (dbch->pdb_tr != db_tr) 2932 printf("pdb_tr != db_tr\n"); 2933 db_tr = STAILQ_NEXT(db_tr, link); 2934 status = FWOHCI_DMA_READ(db_tr->db[0].db.desc.res) 2935 >> OHCI_STATUS_SHIFT; 2936 resCount = FWOHCI_DMA_READ(db_tr->db[0].db.desc.res) 2937 & OHCI_COUNT_MASK; 2938 /* XXX check buffer overrun */ 2939 dbch->top = db_tr; 2940 } else { 2941 dbch->buf_offset = dbch->xferq.psize - resCount; 2942 break; 2943 } 2944 /* XXX make sure DMA is not dead */ 2945 } 2946 #if 0 2947 if (pcnt < 1) 2948 printf("fwohci_arcv: no packets\n"); 2949 #endif 2950 splx(s); 2951 return; 2952 2953 err: 2954 device_printf(sc->fc.dev, "AR DMA status=%x, ", 2955 OREAD(sc, OHCI_DMACTL(off))); 2956 dbch->pdb_tr = NULL; 2957 /* skip until resCount != 0 */ 2958 printf(" skip buffer"); 2959 while (resCount == 0) { 2960 printf(" #"); 2961 fwohci_arcv_free_buf(sc, dbch, db_tr, off, 0); 2962 db_tr = STAILQ_NEXT(db_tr, link); 2963 resCount = FWOHCI_DMA_READ(db_tr->db[0].db.desc.res) 2964 & OHCI_COUNT_MASK; 2965 } 2966 printf(" done\n"); 2967 dbch->top = db_tr; 2968 dbch->buf_offset = dbch->xferq.psize - resCount; 2969 OWRITE(sc, OHCI_DMACTL(off), OHCI_CNTL_DMA_WAKE); 2970 splx(s); 2971 } 2972