1 /* 2 * Copyright (c) 2003 Hidetoshi Shimokawa 3 * Copyright (c) 1998-2002 Katsushi Kobayashi and Hidetoshi Shimokawa 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the acknowledgement as bellow: 16 * 17 * This product includes software developed by K. Kobayashi and H. Shimokawa 18 * 19 * 4. The name of the author may not be used to endorse or promote products 20 * derived from this software without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 24 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 25 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 26 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 27 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 28 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 29 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 30 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 31 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 32 * POSSIBILITY OF SUCH DAMAGE. 33 * 34 * $FreeBSD$ 35 * 36 */ 37 38 #define ATRQ_CH 0 39 #define ATRS_CH 1 40 #define ARRQ_CH 2 41 #define ARRS_CH 3 42 #define ITX_CH 4 43 #define IRX_CH 0x24 44 45 #include <sys/param.h> 46 #include <sys/systm.h> 47 #include <sys/mbuf.h> 48 #include <sys/malloc.h> 49 #include <sys/sockio.h> 50 #include <sys/bus.h> 51 #include <sys/kernel.h> 52 #include <sys/conf.h> 53 #include <sys/endian.h> 54 55 #include <machine/bus.h> 56 57 #if __FreeBSD_version < 500000 58 #include <machine/clock.h> /* for DELAY() */ 59 #endif 60 61 #include <dev/firewire/firewire.h> 62 #include <dev/firewire/firewirereg.h> 63 #include <dev/firewire/fwdma.h> 64 #include <dev/firewire/fwohcireg.h> 65 #include <dev/firewire/fwohcivar.h> 66 #include <dev/firewire/firewire_phy.h> 67 68 #undef OHCI_DEBUG 69 70 static char dbcode[16][0x10]={"OUTM", "OUTL","INPM","INPL", 71 "STOR","LOAD","NOP ","STOP",}; 72 73 static char dbkey[8][0x10]={"ST0", "ST1","ST2","ST3", 74 "UNDEF","REG","SYS","DEV"}; 75 static char dbcond[4][0x10]={"NEV","C=1", "C=0", "ALL"}; 76 char fwohcicode[32][0x20]={ 77 "No stat","Undef","long","miss Ack err", 78 "underrun","overrun","desc err", "data read err", 79 "data write err","bus reset","timeout","tcode err", 80 "Undef","Undef","unknown event","flushed", 81 "Undef","ack complete","ack pend","Undef", 82 "ack busy_X","ack busy_A","ack busy_B","Undef", 83 "Undef","Undef","Undef","ack tardy", 84 "Undef","ack data_err","ack type_err",""}; 85 86 #define MAX_SPEED 3 87 extern char linkspeed[][0x10]; 88 u_int32_t tagbit[4] = { 1 << 28, 1 << 29, 1 << 30, 1 << 31}; 89 90 static struct tcode_info tinfo[] = { 91 /* hdr_len block flag*/ 92 /* 0 WREQQ */ {16, FWTI_REQ | FWTI_TLABEL}, 93 /* 1 WREQB */ {16, FWTI_REQ | FWTI_TLABEL | FWTI_BLOCK_ASY}, 94 /* 2 WRES */ {12, FWTI_RES}, 95 /* 3 XXX */ { 0, 0}, 96 /* 4 RREQQ */ {12, FWTI_REQ | FWTI_TLABEL}, 97 /* 5 RREQB */ {16, FWTI_REQ | FWTI_TLABEL}, 98 /* 6 RRESQ */ {16, FWTI_RES}, 99 /* 7 RRESB */ {16, FWTI_RES | FWTI_BLOCK_ASY}, 100 /* 8 CYCS */ { 0, 0}, 101 /* 9 LREQ */ {16, FWTI_REQ | FWTI_TLABEL | FWTI_BLOCK_ASY}, 102 /* a STREAM */ { 4, FWTI_REQ | FWTI_BLOCK_STR}, 103 /* b LRES */ {16, FWTI_RES | FWTI_BLOCK_ASY}, 104 /* c XXX */ { 0, 0}, 105 /* d XXX */ { 0, 0}, 106 /* e PHY */ {12, FWTI_REQ}, 107 /* f XXX */ { 0, 0} 108 }; 109 110 #define OHCI_WRITE_SIGMASK 0xffff0000 111 #define OHCI_READ_SIGMASK 0xffff0000 112 113 #define OWRITE(sc, r, x) bus_space_write_4((sc)->bst, (sc)->bsh, (r), (x)) 114 #define OREAD(sc, r) bus_space_read_4((sc)->bst, (sc)->bsh, (r)) 115 116 static void fwohci_ibr __P((struct firewire_comm *)); 117 static void fwohci_db_init __P((struct fwohci_softc *, struct fwohci_dbch *)); 118 static void fwohci_db_free __P((struct fwohci_dbch *)); 119 static void fwohci_arcv __P((struct fwohci_softc *, struct fwohci_dbch *, int)); 120 static void fwohci_txd __P((struct fwohci_softc *, struct fwohci_dbch *)); 121 static void fwohci_start_atq __P((struct firewire_comm *)); 122 static void fwohci_start_ats __P((struct firewire_comm *)); 123 static void fwohci_start __P((struct fwohci_softc *, struct fwohci_dbch *)); 124 static u_int32_t fwphy_wrdata __P(( struct fwohci_softc *, u_int32_t, u_int32_t)); 125 static u_int32_t fwphy_rddata __P(( struct fwohci_softc *, u_int32_t)); 126 static int fwohci_rx_enable __P((struct fwohci_softc *, struct fwohci_dbch *)); 127 static int fwohci_tx_enable __P((struct fwohci_softc *, struct fwohci_dbch *)); 128 static int fwohci_irx_enable __P((struct firewire_comm *, int)); 129 static int fwohci_irx_disable __P((struct firewire_comm *, int)); 130 #if BYTE_ORDER == BIG_ENDIAN 131 static void fwohci_irx_post __P((struct firewire_comm *, u_int32_t *)); 132 #endif 133 static int fwohci_itxbuf_enable __P((struct firewire_comm *, int)); 134 static int fwohci_itx_disable __P((struct firewire_comm *, int)); 135 static void fwohci_timeout __P((void *)); 136 static void fwohci_set_intr __P((struct firewire_comm *, int)); 137 138 static int fwohci_add_rx_buf __P((struct fwohci_dbch *, struct fwohcidb_tr *, int, struct fwdma_alloc *)); 139 static int fwohci_add_tx_buf __P((struct fwohci_dbch *, struct fwohcidb_tr *, int)); 140 static void dump_db __P((struct fwohci_softc *, u_int32_t)); 141 static void print_db __P((struct fwohcidb_tr *, volatile struct fwohcidb *, u_int32_t , u_int32_t)); 142 static void dump_dma __P((struct fwohci_softc *, u_int32_t)); 143 static u_int32_t fwohci_cyctimer __P((struct firewire_comm *)); 144 static void fwohci_rbuf_update __P((struct fwohci_softc *, int)); 145 static void fwohci_tbuf_update __P((struct fwohci_softc *, int)); 146 void fwohci_txbufdb __P((struct fwohci_softc *, int , struct fw_bulkxfer *)); 147 #if FWOHCI_TASKQUEUE 148 static void fwohci_complete(void *, int); 149 #endif 150 151 /* 152 * memory allocated for DMA programs 153 */ 154 #define DMA_PROG_ALLOC (8 * PAGE_SIZE) 155 156 /* #define NDB 1024 */ 157 #define NDB FWMAXQUEUE 158 #define NDVDB (DVBUF * NDB) 159 160 #define OHCI_VERSION 0x00 161 #define OHCI_ATRETRY 0x08 162 #define OHCI_CROMHDR 0x18 163 #define OHCI_BUS_OPT 0x20 164 #define OHCI_BUSIRMC (1 << 31) 165 #define OHCI_BUSCMC (1 << 30) 166 #define OHCI_BUSISC (1 << 29) 167 #define OHCI_BUSBMC (1 << 28) 168 #define OHCI_BUSPMC (1 << 27) 169 #define OHCI_BUSFNC OHCI_BUSIRMC | OHCI_BUSCMC | OHCI_BUSISC |\ 170 OHCI_BUSBMC | OHCI_BUSPMC 171 172 #define OHCI_EUID_HI 0x24 173 #define OHCI_EUID_LO 0x28 174 175 #define OHCI_CROMPTR 0x34 176 #define OHCI_HCCCTL 0x50 177 #define OHCI_HCCCTLCLR 0x54 178 #define OHCI_AREQHI 0x100 179 #define OHCI_AREQHICLR 0x104 180 #define OHCI_AREQLO 0x108 181 #define OHCI_AREQLOCLR 0x10c 182 #define OHCI_PREQHI 0x110 183 #define OHCI_PREQHICLR 0x114 184 #define OHCI_PREQLO 0x118 185 #define OHCI_PREQLOCLR 0x11c 186 #define OHCI_PREQUPPER 0x120 187 188 #define OHCI_SID_BUF 0x64 189 #define OHCI_SID_CNT 0x68 190 #define OHCI_SID_ERR (1 << 31) 191 #define OHCI_SID_CNT_MASK 0xffc 192 193 #define OHCI_IT_STAT 0x90 194 #define OHCI_IT_STATCLR 0x94 195 #define OHCI_IT_MASK 0x98 196 #define OHCI_IT_MASKCLR 0x9c 197 198 #define OHCI_IR_STAT 0xa0 199 #define OHCI_IR_STATCLR 0xa4 200 #define OHCI_IR_MASK 0xa8 201 #define OHCI_IR_MASKCLR 0xac 202 203 #define OHCI_LNKCTL 0xe0 204 #define OHCI_LNKCTLCLR 0xe4 205 206 #define OHCI_PHYACCESS 0xec 207 #define OHCI_CYCLETIMER 0xf0 208 209 #define OHCI_DMACTL(off) (off) 210 #define OHCI_DMACTLCLR(off) (off + 4) 211 #define OHCI_DMACMD(off) (off + 0xc) 212 #define OHCI_DMAMATCH(off) (off + 0x10) 213 214 #define OHCI_ATQOFF 0x180 215 #define OHCI_ATQCTL OHCI_ATQOFF 216 #define OHCI_ATQCTLCLR (OHCI_ATQOFF + 4) 217 #define OHCI_ATQCMD (OHCI_ATQOFF + 0xc) 218 #define OHCI_ATQMATCH (OHCI_ATQOFF + 0x10) 219 220 #define OHCI_ATSOFF 0x1a0 221 #define OHCI_ATSCTL OHCI_ATSOFF 222 #define OHCI_ATSCTLCLR (OHCI_ATSOFF + 4) 223 #define OHCI_ATSCMD (OHCI_ATSOFF + 0xc) 224 #define OHCI_ATSMATCH (OHCI_ATSOFF + 0x10) 225 226 #define OHCI_ARQOFF 0x1c0 227 #define OHCI_ARQCTL OHCI_ARQOFF 228 #define OHCI_ARQCTLCLR (OHCI_ARQOFF + 4) 229 #define OHCI_ARQCMD (OHCI_ARQOFF + 0xc) 230 #define OHCI_ARQMATCH (OHCI_ARQOFF + 0x10) 231 232 #define OHCI_ARSOFF 0x1e0 233 #define OHCI_ARSCTL OHCI_ARSOFF 234 #define OHCI_ARSCTLCLR (OHCI_ARSOFF + 4) 235 #define OHCI_ARSCMD (OHCI_ARSOFF + 0xc) 236 #define OHCI_ARSMATCH (OHCI_ARSOFF + 0x10) 237 238 #define OHCI_ITOFF(CH) (0x200 + 0x10 * (CH)) 239 #define OHCI_ITCTL(CH) (OHCI_ITOFF(CH)) 240 #define OHCI_ITCTLCLR(CH) (OHCI_ITOFF(CH) + 4) 241 #define OHCI_ITCMD(CH) (OHCI_ITOFF(CH) + 0xc) 242 243 #define OHCI_IROFF(CH) (0x400 + 0x20 * (CH)) 244 #define OHCI_IRCTL(CH) (OHCI_IROFF(CH)) 245 #define OHCI_IRCTLCLR(CH) (OHCI_IROFF(CH) + 4) 246 #define OHCI_IRCMD(CH) (OHCI_IROFF(CH) + 0xc) 247 #define OHCI_IRMATCH(CH) (OHCI_IROFF(CH) + 0x10) 248 249 d_ioctl_t fwohci_ioctl; 250 251 /* 252 * Communication with PHY device 253 */ 254 static u_int32_t 255 fwphy_wrdata( struct fwohci_softc *sc, u_int32_t addr, u_int32_t data) 256 { 257 u_int32_t fun; 258 259 addr &= 0xf; 260 data &= 0xff; 261 262 fun = (PHYDEV_WRCMD | (addr << PHYDEV_REGADDR) | (data << PHYDEV_WRDATA)); 263 OWRITE(sc, OHCI_PHYACCESS, fun); 264 DELAY(100); 265 266 return(fwphy_rddata( sc, addr)); 267 } 268 269 static u_int32_t 270 fwohci_set_bus_manager(struct firewire_comm *fc, u_int node) 271 { 272 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 273 int i; 274 u_int32_t bm; 275 276 #define OHCI_CSR_DATA 0x0c 277 #define OHCI_CSR_COMP 0x10 278 #define OHCI_CSR_CONT 0x14 279 #define OHCI_BUS_MANAGER_ID 0 280 281 OWRITE(sc, OHCI_CSR_DATA, node); 282 OWRITE(sc, OHCI_CSR_COMP, 0x3f); 283 OWRITE(sc, OHCI_CSR_CONT, OHCI_BUS_MANAGER_ID); 284 for (i = 0; !(OREAD(sc, OHCI_CSR_CONT) & (1<<31)) && (i < 1000); i++) 285 DELAY(10); 286 bm = OREAD(sc, OHCI_CSR_DATA); 287 if((bm & 0x3f) == 0x3f) 288 bm = node; 289 if (bootverbose) 290 device_printf(sc->fc.dev, 291 "fw_set_bus_manager: %d->%d (loop=%d)\n", bm, node, i); 292 293 return(bm); 294 } 295 296 static u_int32_t 297 fwphy_rddata(struct fwohci_softc *sc, u_int addr) 298 { 299 u_int32_t fun, stat; 300 u_int i, retry = 0; 301 302 addr &= 0xf; 303 #define MAX_RETRY 100 304 again: 305 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_REG_FAIL); 306 fun = PHYDEV_RDCMD | (addr << PHYDEV_REGADDR); 307 OWRITE(sc, OHCI_PHYACCESS, fun); 308 for ( i = 0 ; i < MAX_RETRY ; i ++ ){ 309 fun = OREAD(sc, OHCI_PHYACCESS); 310 if ((fun & PHYDEV_RDCMD) == 0 && (fun & PHYDEV_RDDONE) != 0) 311 break; 312 DELAY(100); 313 } 314 if(i >= MAX_RETRY) { 315 if (bootverbose) 316 device_printf(sc->fc.dev, "phy read failed(1).\n"); 317 if (++retry < MAX_RETRY) { 318 DELAY(100); 319 goto again; 320 } 321 } 322 /* Make sure that SCLK is started */ 323 stat = OREAD(sc, FWOHCI_INTSTAT); 324 if ((stat & OHCI_INT_REG_FAIL) != 0 || 325 ((fun >> PHYDEV_REGADDR) & 0xf) != addr) { 326 if (bootverbose) 327 device_printf(sc->fc.dev, "phy read failed(2).\n"); 328 if (++retry < MAX_RETRY) { 329 DELAY(100); 330 goto again; 331 } 332 } 333 if (bootverbose || retry >= MAX_RETRY) 334 device_printf(sc->fc.dev, 335 "fwphy_rddata: loop=%d, retry=%d\n", i, retry); 336 #undef MAX_RETRY 337 return((fun >> PHYDEV_RDDATA )& 0xff); 338 } 339 /* Device specific ioctl. */ 340 int 341 fwohci_ioctl (dev_t dev, u_long cmd, caddr_t data, int flag, fw_proc *td) 342 { 343 struct firewire_softc *sc; 344 struct fwohci_softc *fc; 345 int unit = DEV2UNIT(dev); 346 int err = 0; 347 struct fw_reg_req_t *reg = (struct fw_reg_req_t *) data; 348 u_int32_t *dmach = (u_int32_t *) data; 349 350 sc = devclass_get_softc(firewire_devclass, unit); 351 if(sc == NULL){ 352 return(EINVAL); 353 } 354 fc = (struct fwohci_softc *)sc->fc; 355 356 if (!data) 357 return(EINVAL); 358 359 switch (cmd) { 360 case FWOHCI_WRREG: 361 #define OHCI_MAX_REG 0x800 362 if(reg->addr <= OHCI_MAX_REG){ 363 OWRITE(fc, reg->addr, reg->data); 364 reg->data = OREAD(fc, reg->addr); 365 }else{ 366 err = EINVAL; 367 } 368 break; 369 case FWOHCI_RDREG: 370 if(reg->addr <= OHCI_MAX_REG){ 371 reg->data = OREAD(fc, reg->addr); 372 }else{ 373 err = EINVAL; 374 } 375 break; 376 /* Read DMA descriptors for debug */ 377 case DUMPDMA: 378 if(*dmach <= OHCI_MAX_DMA_CH ){ 379 dump_dma(fc, *dmach); 380 dump_db(fc, *dmach); 381 }else{ 382 err = EINVAL; 383 } 384 break; 385 default: 386 break; 387 } 388 return err; 389 } 390 391 static int 392 fwohci_probe_phy(struct fwohci_softc *sc, device_t dev) 393 { 394 u_int32_t reg, reg2; 395 int e1394a = 1; 396 /* 397 * probe PHY parameters 398 * 0. to prove PHY version, whether compliance of 1394a. 399 * 1. to probe maximum speed supported by the PHY and 400 * number of port supported by core-logic. 401 * It is not actually available port on your PC . 402 */ 403 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_LPS); 404 reg = fwphy_rddata(sc, FW_PHY_SPD_REG); 405 406 if((reg >> 5) != 7 ){ 407 sc->fc.mode &= ~FWPHYASYST; 408 sc->fc.nport = reg & FW_PHY_NP; 409 sc->fc.speed = reg & FW_PHY_SPD >> 6; 410 if (sc->fc.speed > MAX_SPEED) { 411 device_printf(dev, "invalid speed %d (fixed to %d).\n", 412 sc->fc.speed, MAX_SPEED); 413 sc->fc.speed = MAX_SPEED; 414 } 415 device_printf(dev, 416 "Phy 1394 only %s, %d ports.\n", 417 linkspeed[sc->fc.speed], sc->fc.nport); 418 }else{ 419 reg2 = fwphy_rddata(sc, FW_PHY_ESPD_REG); 420 sc->fc.mode |= FWPHYASYST; 421 sc->fc.nport = reg & FW_PHY_NP; 422 sc->fc.speed = (reg2 & FW_PHY_ESPD) >> 5; 423 if (sc->fc.speed > MAX_SPEED) { 424 device_printf(dev, "invalid speed %d (fixed to %d).\n", 425 sc->fc.speed, MAX_SPEED); 426 sc->fc.speed = MAX_SPEED; 427 } 428 device_printf(dev, 429 "Phy 1394a available %s, %d ports.\n", 430 linkspeed[sc->fc.speed], sc->fc.nport); 431 432 /* check programPhyEnable */ 433 reg2 = fwphy_rddata(sc, 5); 434 #if 0 435 if (e1394a && (OREAD(sc, OHCI_HCCCTL) & OHCI_HCC_PRPHY)) { 436 #else /* XXX force to enable 1394a */ 437 if (e1394a) { 438 #endif 439 if (bootverbose) 440 device_printf(dev, 441 "Enable 1394a Enhancements\n"); 442 /* enable EAA EMC */ 443 reg2 |= 0x03; 444 /* set aPhyEnhanceEnable */ 445 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_PHYEN); 446 OWRITE(sc, OHCI_HCCCTLCLR, OHCI_HCC_PRPHY); 447 } else { 448 /* for safe */ 449 reg2 &= ~0x83; 450 } 451 reg2 = fwphy_wrdata(sc, 5, reg2); 452 } 453 454 reg = fwphy_rddata(sc, FW_PHY_SPD_REG); 455 if((reg >> 5) == 7 ){ 456 reg = fwphy_rddata(sc, 4); 457 reg |= 1 << 6; 458 fwphy_wrdata(sc, 4, reg); 459 reg = fwphy_rddata(sc, 4); 460 } 461 return 0; 462 } 463 464 465 void 466 fwohci_reset(struct fwohci_softc *sc, device_t dev) 467 { 468 int i, max_rec, speed; 469 u_int32_t reg, reg2; 470 struct fwohcidb_tr *db_tr; 471 472 /* Disable interrupt */ 473 OWRITE(sc, FWOHCI_INTMASKCLR, ~0); 474 475 /* Now stopping all DMA channel */ 476 OWRITE(sc, OHCI_ARQCTLCLR, OHCI_CNTL_DMA_RUN); 477 OWRITE(sc, OHCI_ARSCTLCLR, OHCI_CNTL_DMA_RUN); 478 OWRITE(sc, OHCI_ATQCTLCLR, OHCI_CNTL_DMA_RUN); 479 OWRITE(sc, OHCI_ATSCTLCLR, OHCI_CNTL_DMA_RUN); 480 481 OWRITE(sc, OHCI_IR_MASKCLR, ~0); 482 for( i = 0 ; i < sc->fc.nisodma ; i ++ ){ 483 OWRITE(sc, OHCI_IRCTLCLR(i), OHCI_CNTL_DMA_RUN); 484 OWRITE(sc, OHCI_ITCTLCLR(i), OHCI_CNTL_DMA_RUN); 485 } 486 487 /* FLUSH FIFO and reset Transmitter/Reciever */ 488 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_RESET); 489 if (bootverbose) 490 device_printf(dev, "resetting OHCI..."); 491 i = 0; 492 while(OREAD(sc, OHCI_HCCCTL) & OHCI_HCC_RESET) { 493 if (i++ > 100) break; 494 DELAY(1000); 495 } 496 if (bootverbose) 497 printf("done (loop=%d)\n", i); 498 499 /* Probe phy */ 500 fwohci_probe_phy(sc, dev); 501 502 /* Probe link */ 503 reg = OREAD(sc, OHCI_BUS_OPT); 504 reg2 = reg | OHCI_BUSFNC; 505 max_rec = (reg & 0x0000f000) >> 12; 506 speed = (reg & 0x00000007); 507 device_printf(dev, "Link %s, max_rec %d bytes.\n", 508 linkspeed[speed], MAXREC(max_rec)); 509 /* XXX fix max_rec */ 510 sc->fc.maxrec = sc->fc.speed + 8; 511 if (max_rec != sc->fc.maxrec) { 512 reg2 = (reg2 & 0xffff0fff) | (sc->fc.maxrec << 12); 513 device_printf(dev, "max_rec %d -> %d\n", 514 MAXREC(max_rec), MAXREC(sc->fc.maxrec)); 515 } 516 if (bootverbose) 517 device_printf(dev, "BUS_OPT 0x%x -> 0x%x\n", reg, reg2); 518 OWRITE(sc, OHCI_BUS_OPT, reg2); 519 520 /* Initialize registers */ 521 OWRITE(sc, OHCI_CROMHDR, sc->fc.config_rom[0]); 522 OWRITE(sc, OHCI_CROMPTR, sc->crom_dma.bus_addr); 523 OWRITE(sc, OHCI_HCCCTLCLR, OHCI_HCC_BIGEND); 524 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_POSTWR); 525 OWRITE(sc, OHCI_SID_BUF, sc->sid_dma.bus_addr); 526 OWRITE(sc, OHCI_LNKCTL, OHCI_CNTL_SID); 527 fw_busreset(&sc->fc); 528 529 /* Enable link */ 530 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_LINKEN); 531 532 /* Force to start async RX DMA */ 533 sc->arrq.xferq.flag &= ~FWXFERQ_RUNNING; 534 sc->arrs.xferq.flag &= ~FWXFERQ_RUNNING; 535 fwohci_rx_enable(sc, &sc->arrq); 536 fwohci_rx_enable(sc, &sc->arrs); 537 538 /* Initialize async TX */ 539 OWRITE(sc, OHCI_ATQCTLCLR, OHCI_CNTL_DMA_RUN | OHCI_CNTL_DMA_DEAD); 540 OWRITE(sc, OHCI_ATSCTLCLR, OHCI_CNTL_DMA_RUN | OHCI_CNTL_DMA_DEAD); 541 542 /* AT Retries */ 543 OWRITE(sc, FWOHCI_RETRY, 544 /* CycleLimit PhyRespRetries ATRespRetries ATReqRetries */ 545 (0xffff << 16 ) | (0x0f << 8) | (0x0f << 4) | 0x0f) ; 546 547 sc->atrq.top = STAILQ_FIRST(&sc->atrq.db_trq); 548 sc->atrs.top = STAILQ_FIRST(&sc->atrs.db_trq); 549 sc->atrq.bottom = sc->atrq.top; 550 sc->atrs.bottom = sc->atrs.top; 551 552 for( i = 0, db_tr = sc->atrq.top; i < sc->atrq.ndb ; 553 i ++, db_tr = STAILQ_NEXT(db_tr, link)){ 554 db_tr->xfer = NULL; 555 } 556 for( i = 0, db_tr = sc->atrs.top; i < sc->atrs.ndb ; 557 i ++, db_tr = STAILQ_NEXT(db_tr, link)){ 558 db_tr->xfer = NULL; 559 } 560 561 562 /* Enable interrupt */ 563 OWRITE(sc, FWOHCI_INTMASK, 564 OHCI_INT_ERR | OHCI_INT_PHY_SID 565 | OHCI_INT_DMA_ATRQ | OHCI_INT_DMA_ATRS 566 | OHCI_INT_DMA_PRRQ | OHCI_INT_DMA_PRRS 567 | OHCI_INT_PHY_BUS_R | OHCI_INT_PW_ERR); 568 fwohci_set_intr(&sc->fc, 1); 569 570 } 571 572 int 573 fwohci_init(struct fwohci_softc *sc, device_t dev) 574 { 575 int i; 576 u_int32_t reg; 577 u_int8_t ui[8]; 578 579 #if FWOHCI_TASKQUEUE 580 TASK_INIT(&sc->fwohci_task_complete, 0, fwohci_complete, sc); 581 #endif 582 583 reg = OREAD(sc, OHCI_VERSION); 584 device_printf(dev, "OHCI version %x.%x (ROM=%d)\n", 585 (reg>>16) & 0xff, reg & 0xff, (reg>>24) & 1); 586 587 /* Available Isochrounous DMA channel probe */ 588 OWRITE(sc, OHCI_IT_MASK, 0xffffffff); 589 OWRITE(sc, OHCI_IR_MASK, 0xffffffff); 590 reg = OREAD(sc, OHCI_IT_MASK) & OREAD(sc, OHCI_IR_MASK); 591 OWRITE(sc, OHCI_IT_MASKCLR, 0xffffffff); 592 OWRITE(sc, OHCI_IR_MASKCLR, 0xffffffff); 593 for (i = 0; i < 0x20; i++) 594 if ((reg & (1 << i)) == 0) 595 break; 596 sc->fc.nisodma = i; 597 device_printf(dev, "No. of Isochronous channel is %d.\n", i); 598 599 sc->fc.arq = &sc->arrq.xferq; 600 sc->fc.ars = &sc->arrs.xferq; 601 sc->fc.atq = &sc->atrq.xferq; 602 sc->fc.ats = &sc->atrs.xferq; 603 604 sc->arrq.xferq.psize = roundup2(FWPMAX_S400, PAGE_SIZE); 605 sc->arrs.xferq.psize = roundup2(FWPMAX_S400, PAGE_SIZE); 606 sc->atrq.xferq.psize = roundup2(FWPMAX_S400, PAGE_SIZE); 607 sc->atrs.xferq.psize = roundup2(FWPMAX_S400, PAGE_SIZE); 608 609 sc->arrq.xferq.start = NULL; 610 sc->arrs.xferq.start = NULL; 611 sc->atrq.xferq.start = fwohci_start_atq; 612 sc->atrs.xferq.start = fwohci_start_ats; 613 614 sc->arrq.xferq.buf = NULL; 615 sc->arrs.xferq.buf = NULL; 616 sc->atrq.xferq.buf = NULL; 617 sc->atrs.xferq.buf = NULL; 618 619 sc->arrq.ndesc = 1; 620 sc->arrs.ndesc = 1; 621 sc->atrq.ndesc = 8; /* equal to maximum of mbuf chains */ 622 sc->atrs.ndesc = 2; 623 624 sc->arrq.ndb = NDB; 625 sc->arrs.ndb = NDB / 2; 626 sc->atrq.ndb = NDB; 627 sc->atrs.ndb = NDB / 2; 628 629 for( i = 0 ; i < sc->fc.nisodma ; i ++ ){ 630 sc->fc.it[i] = &sc->it[i].xferq; 631 sc->fc.ir[i] = &sc->ir[i].xferq; 632 sc->it[i].ndb = 0; 633 sc->ir[i].ndb = 0; 634 } 635 636 sc->fc.tcode = tinfo; 637 sc->fc.dev = dev; 638 639 sc->fc.config_rom = fwdma_malloc(&sc->fc, CROMSIZE, CROMSIZE, 640 &sc->crom_dma, BUS_DMA_WAITOK); 641 if(sc->fc.config_rom == NULL){ 642 device_printf(dev, "config_rom alloc failed."); 643 return ENOMEM; 644 } 645 646 #if 0 647 bzero(&sc->fc.config_rom[0], CROMSIZE); 648 sc->fc.config_rom[1] = 0x31333934; 649 sc->fc.config_rom[2] = 0xf000a002; 650 sc->fc.config_rom[3] = OREAD(sc, OHCI_EUID_HI); 651 sc->fc.config_rom[4] = OREAD(sc, OHCI_EUID_LO); 652 sc->fc.config_rom[5] = 0; 653 sc->fc.config_rom[0] = (4 << 24) | (5 << 16); 654 655 sc->fc.config_rom[0] |= fw_crc16(&sc->fc.config_rom[1], 5*4); 656 #endif 657 658 659 /* SID recieve buffer must allign 2^11 */ 660 #define OHCI_SIDSIZE (1 << 11) 661 sc->sid_buf = fwdma_malloc(&sc->fc, OHCI_SIDSIZE, OHCI_SIDSIZE, 662 &sc->sid_dma, BUS_DMA_WAITOK); 663 if (sc->sid_buf == NULL) { 664 device_printf(dev, "sid_buf alloc failed."); 665 return ENOMEM; 666 } 667 668 fwdma_malloc(&sc->fc, sizeof(u_int32_t), sizeof(u_int32_t), 669 &sc->dummy_dma, BUS_DMA_WAITOK); 670 671 if (sc->dummy_dma.v_addr == NULL) { 672 device_printf(dev, "dummy_dma alloc failed."); 673 return ENOMEM; 674 } 675 676 fwohci_db_init(sc, &sc->arrq); 677 if ((sc->arrq.flags & FWOHCI_DBCH_INIT) == 0) 678 return ENOMEM; 679 680 fwohci_db_init(sc, &sc->arrs); 681 if ((sc->arrs.flags & FWOHCI_DBCH_INIT) == 0) 682 return ENOMEM; 683 684 fwohci_db_init(sc, &sc->atrq); 685 if ((sc->atrq.flags & FWOHCI_DBCH_INIT) == 0) 686 return ENOMEM; 687 688 fwohci_db_init(sc, &sc->atrs); 689 if ((sc->atrs.flags & FWOHCI_DBCH_INIT) == 0) 690 return ENOMEM; 691 692 sc->fc.eui.hi = OREAD(sc, FWOHCIGUID_H); 693 sc->fc.eui.lo = OREAD(sc, FWOHCIGUID_L); 694 for( i = 0 ; i < 8 ; i ++) 695 ui[i] = FW_EUI64_BYTE(&sc->fc.eui,i); 696 device_printf(dev, "EUI64 %02x:%02x:%02x:%02x:%02x:%02x:%02x:%02x\n", 697 ui[0], ui[1], ui[2], ui[3], ui[4], ui[5], ui[6], ui[7]); 698 699 sc->fc.ioctl = fwohci_ioctl; 700 sc->fc.cyctimer = fwohci_cyctimer; 701 sc->fc.set_bmr = fwohci_set_bus_manager; 702 sc->fc.ibr = fwohci_ibr; 703 sc->fc.irx_enable = fwohci_irx_enable; 704 sc->fc.irx_disable = fwohci_irx_disable; 705 706 sc->fc.itx_enable = fwohci_itxbuf_enable; 707 sc->fc.itx_disable = fwohci_itx_disable; 708 #if BYTE_ORDER == BIG_ENDIAN 709 sc->fc.irx_post = fwohci_irx_post; 710 #else 711 sc->fc.irx_post = NULL; 712 #endif 713 sc->fc.itx_post = NULL; 714 sc->fc.timeout = fwohci_timeout; 715 sc->fc.poll = fwohci_poll; 716 sc->fc.set_intr = fwohci_set_intr; 717 718 sc->intmask = sc->irstat = sc->itstat = 0; 719 720 fw_init(&sc->fc); 721 fwohci_reset(sc, dev); 722 723 return 0; 724 } 725 726 void 727 fwohci_timeout(void *arg) 728 { 729 struct fwohci_softc *sc; 730 731 sc = (struct fwohci_softc *)arg; 732 } 733 734 u_int32_t 735 fwohci_cyctimer(struct firewire_comm *fc) 736 { 737 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 738 return(OREAD(sc, OHCI_CYCLETIMER)); 739 } 740 741 int 742 fwohci_detach(struct fwohci_softc *sc, device_t dev) 743 { 744 int i; 745 746 if (sc->sid_buf != NULL) 747 fwdma_free(&sc->fc, &sc->sid_dma); 748 if (sc->fc.config_rom != NULL) 749 fwdma_free(&sc->fc, &sc->crom_dma); 750 751 fwohci_db_free(&sc->arrq); 752 fwohci_db_free(&sc->arrs); 753 754 fwohci_db_free(&sc->atrq); 755 fwohci_db_free(&sc->atrs); 756 757 for( i = 0 ; i < sc->fc.nisodma ; i ++ ){ 758 fwohci_db_free(&sc->it[i]); 759 fwohci_db_free(&sc->ir[i]); 760 } 761 762 return 0; 763 } 764 765 #define LAST_DB(dbtr, db) do { \ 766 struct fwohcidb_tr *_dbtr = (dbtr); \ 767 int _cnt = _dbtr->dbcnt; \ 768 db = &_dbtr->db[ (_cnt > 2) ? (_cnt -1) : 0]; \ 769 } while (0) 770 771 static void 772 fwohci_execute_db(void *arg, bus_dma_segment_t *segs, int nseg, int error) 773 { 774 struct fwohcidb_tr *db_tr; 775 volatile struct fwohcidb *db; 776 bus_dma_segment_t *s; 777 int i; 778 779 db_tr = (struct fwohcidb_tr *)arg; 780 db = &db_tr->db[db_tr->dbcnt]; 781 if (error) { 782 if (firewire_debug || error != EFBIG) 783 printf("fwohci_execute_db: error=%d\n", error); 784 return; 785 } 786 for (i = 0; i < nseg; i++) { 787 s = &segs[i]; 788 FWOHCI_DMA_WRITE(db->db.desc.addr, s->ds_addr); 789 FWOHCI_DMA_WRITE(db->db.desc.cmd, s->ds_len); 790 FWOHCI_DMA_WRITE(db->db.desc.res, 0); 791 db++; 792 db_tr->dbcnt++; 793 } 794 } 795 796 static void 797 fwohci_execute_db2(void *arg, bus_dma_segment_t *segs, int nseg, 798 bus_size_t size, int error) 799 { 800 fwohci_execute_db(arg, segs, nseg, error); 801 } 802 803 static void 804 fwohci_start(struct fwohci_softc *sc, struct fwohci_dbch *dbch) 805 { 806 int i, s; 807 int tcode, hdr_len, pl_off, pl_len; 808 int fsegment = -1; 809 u_int32_t off; 810 struct fw_xfer *xfer; 811 struct fw_pkt *fp; 812 volatile struct fwohci_txpkthdr *ohcifp; 813 struct fwohcidb_tr *db_tr; 814 volatile struct fwohcidb *db; 815 struct tcode_info *info; 816 static int maxdesc=0; 817 818 if(&sc->atrq == dbch){ 819 off = OHCI_ATQOFF; 820 }else if(&sc->atrs == dbch){ 821 off = OHCI_ATSOFF; 822 }else{ 823 return; 824 } 825 826 if (dbch->flags & FWOHCI_DBCH_FULL) 827 return; 828 829 s = splfw(); 830 db_tr = dbch->top; 831 txloop: 832 xfer = STAILQ_FIRST(&dbch->xferq.q); 833 if(xfer == NULL){ 834 goto kick; 835 } 836 if(dbch->xferq.queued == 0 ){ 837 device_printf(sc->fc.dev, "TX queue empty\n"); 838 } 839 STAILQ_REMOVE_HEAD(&dbch->xferq.q, link); 840 db_tr->xfer = xfer; 841 xfer->state = FWXF_START; 842 843 fp = (struct fw_pkt *)xfer->send.buf; 844 tcode = fp->mode.common.tcode; 845 846 ohcifp = (volatile struct fwohci_txpkthdr *) db_tr->db[1].db.immed; 847 info = &tinfo[tcode]; 848 hdr_len = pl_off = info->hdr_len; 849 for( i = 0 ; i < pl_off ; i+= 4){ 850 ohcifp->mode.ld[i/4] = fp->mode.ld[i/4]; 851 } 852 ohcifp->mode.common.spd = xfer->spd; 853 if (tcode == FWTCODE_STREAM ){ 854 hdr_len = 8; 855 ohcifp->mode.stream.len = fp->mode.stream.len; 856 } else if (tcode == FWTCODE_PHY) { 857 hdr_len = 12; 858 ohcifp->mode.ld[1] = fp->mode.ld[1]; 859 ohcifp->mode.ld[2] = fp->mode.ld[2]; 860 ohcifp->mode.common.spd = 0; 861 ohcifp->mode.common.tcode = FWOHCITCODE_PHY; 862 } else { 863 ohcifp->mode.asycomm.dst = fp->mode.hdr.dst; 864 ohcifp->mode.asycomm.srcbus = OHCI_ASYSRCBUS; 865 ohcifp->mode.asycomm.tlrt |= FWRETRY_X; 866 } 867 db = &db_tr->db[0]; 868 FWOHCI_DMA_WRITE(db->db.desc.cmd, 869 OHCI_OUTPUT_MORE | OHCI_KEY_ST2 | hdr_len); 870 FWOHCI_DMA_WRITE(db->db.desc.res, 0); 871 /* Specify bound timer of asy. responce */ 872 if(&sc->atrs == dbch){ 873 FWOHCI_DMA_WRITE(db->db.desc.res, 874 (OREAD(sc, OHCI_CYCLETIMER) >> 12) + (1 << 13)); 875 } 876 #if BYTE_ORDER == BIG_ENDIAN 877 if (tcode == FWTCODE_WREQQ || tcode == FWTCODE_RRESQ) 878 hdr_len = 12; 879 for (i = 0; i < hdr_len/4; i ++) 880 FWOHCI_DMA_WRITE(ohcifp->mode.ld[i], ohcifp->mode.ld[i]); 881 #endif 882 883 again: 884 db_tr->dbcnt = 2; 885 db = &db_tr->db[db_tr->dbcnt]; 886 pl_len = xfer->send.len - pl_off; 887 if (pl_len > 0) { 888 int err; 889 /* handle payload */ 890 if (xfer->mbuf == NULL) { 891 caddr_t pl_addr; 892 893 pl_addr = xfer->send.buf + pl_off; 894 err = bus_dmamap_load(dbch->dmat, db_tr->dma_map, 895 pl_addr, pl_len, 896 fwohci_execute_db, db_tr, 897 /*flags*/0); 898 } else { 899 /* XXX we can handle only 6 (=8-2) mbuf chains */ 900 err = bus_dmamap_load_mbuf(dbch->dmat, db_tr->dma_map, 901 xfer->mbuf, 902 fwohci_execute_db2, db_tr, 903 /* flags */0); 904 if (err == EFBIG) { 905 struct mbuf *m0; 906 907 if (firewire_debug) 908 device_printf(sc->fc.dev, "EFBIG.\n"); 909 m0 = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 910 if (m0 != NULL) { 911 m_copydata(xfer->mbuf, 0, 912 xfer->mbuf->m_pkthdr.len, 913 mtod(m0, caddr_t)); 914 m0->m_len = m0->m_pkthdr.len = 915 xfer->mbuf->m_pkthdr.len; 916 m_freem(xfer->mbuf); 917 xfer->mbuf = m0; 918 goto again; 919 } 920 device_printf(sc->fc.dev, "m_getcl failed.\n"); 921 } 922 } 923 if (err) 924 printf("dmamap_load: err=%d\n", err); 925 bus_dmamap_sync(dbch->dmat, db_tr->dma_map, 926 BUS_DMASYNC_PREWRITE); 927 #if 0 /* OHCI_OUTPUT_MODE == 0 */ 928 for (i = 2; i < db_tr->dbcnt; i++) 929 FWOHCI_DMA_SET(db_tr->db[i].db.desc.cmd, 930 OHCI_OUTPUT_MORE); 931 #endif 932 } 933 if (maxdesc < db_tr->dbcnt) { 934 maxdesc = db_tr->dbcnt; 935 if (bootverbose) 936 device_printf(sc->fc.dev, "maxdesc: %d\n", maxdesc); 937 } 938 /* last db */ 939 LAST_DB(db_tr, db); 940 FWOHCI_DMA_SET(db->db.desc.cmd, 941 OHCI_OUTPUT_LAST | OHCI_INTERRUPT_ALWAYS | OHCI_BRANCH_ALWAYS); 942 FWOHCI_DMA_WRITE(db->db.desc.depend, 943 STAILQ_NEXT(db_tr, link)->bus_addr); 944 945 if(fsegment == -1 ) 946 fsegment = db_tr->dbcnt; 947 if (dbch->pdb_tr != NULL) { 948 LAST_DB(dbch->pdb_tr, db); 949 FWOHCI_DMA_SET(db->db.desc.depend, db_tr->dbcnt); 950 } 951 dbch->pdb_tr = db_tr; 952 db_tr = STAILQ_NEXT(db_tr, link); 953 if(db_tr != dbch->bottom){ 954 goto txloop; 955 } else { 956 device_printf(sc->fc.dev, "fwohci_start: lack of db_trq\n"); 957 dbch->flags |= FWOHCI_DBCH_FULL; 958 } 959 kick: 960 /* kick asy q */ 961 fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREREAD); 962 fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREWRITE); 963 964 if(dbch->xferq.flag & FWXFERQ_RUNNING) { 965 OWRITE(sc, OHCI_DMACTL(off), OHCI_CNTL_DMA_WAKE); 966 } else { 967 if (bootverbose) 968 device_printf(sc->fc.dev, "start AT DMA status=%x\n", 969 OREAD(sc, OHCI_DMACTL(off))); 970 OWRITE(sc, OHCI_DMACMD(off), dbch->top->bus_addr | fsegment); 971 OWRITE(sc, OHCI_DMACTL(off), OHCI_CNTL_DMA_RUN); 972 dbch->xferq.flag |= FWXFERQ_RUNNING; 973 } 974 975 dbch->top = db_tr; 976 splx(s); 977 return; 978 } 979 980 static void 981 fwohci_start_atq(struct firewire_comm *fc) 982 { 983 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 984 fwohci_start( sc, &(sc->atrq)); 985 return; 986 } 987 988 static void 989 fwohci_start_ats(struct firewire_comm *fc) 990 { 991 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 992 fwohci_start( sc, &(sc->atrs)); 993 return; 994 } 995 996 void 997 fwohci_txd(struct fwohci_softc *sc, struct fwohci_dbch *dbch) 998 { 999 int s, ch, err = 0; 1000 struct fwohcidb_tr *tr; 1001 volatile struct fwohcidb *db; 1002 struct fw_xfer *xfer; 1003 u_int32_t off; 1004 u_int stat, status; 1005 int packets; 1006 struct firewire_comm *fc = (struct firewire_comm *)sc; 1007 1008 if(&sc->atrq == dbch){ 1009 off = OHCI_ATQOFF; 1010 ch = ATRQ_CH; 1011 }else if(&sc->atrs == dbch){ 1012 off = OHCI_ATSOFF; 1013 ch = ATRS_CH; 1014 }else{ 1015 return; 1016 } 1017 s = splfw(); 1018 tr = dbch->bottom; 1019 packets = 0; 1020 fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_POSTREAD); 1021 fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_POSTWRITE); 1022 while(dbch->xferq.queued > 0){ 1023 LAST_DB(tr, db); 1024 status = FWOHCI_DMA_READ(db->db.desc.res) >> OHCI_STATUS_SHIFT; 1025 if(!(status & OHCI_CNTL_DMA_ACTIVE)){ 1026 if (fc->status != FWBUSRESET) 1027 /* maybe out of order?? */ 1028 goto out; 1029 } 1030 bus_dmamap_sync(dbch->dmat, tr->dma_map, 1031 BUS_DMASYNC_POSTWRITE); 1032 bus_dmamap_unload(dbch->dmat, tr->dma_map); 1033 #if 0 1034 dump_db(sc, ch); 1035 #endif 1036 if(status & OHCI_CNTL_DMA_DEAD) { 1037 /* Stop DMA */ 1038 OWRITE(sc, OHCI_DMACTLCLR(off), OHCI_CNTL_DMA_RUN); 1039 device_printf(sc->fc.dev, "force reset AT FIFO\n"); 1040 OWRITE(sc, OHCI_HCCCTLCLR, OHCI_HCC_LINKEN); 1041 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_LPS | OHCI_HCC_LINKEN); 1042 OWRITE(sc, OHCI_DMACTLCLR(off), OHCI_CNTL_DMA_RUN); 1043 } 1044 stat = status & FWOHCIEV_MASK; 1045 switch(stat){ 1046 case FWOHCIEV_ACKPEND: 1047 case FWOHCIEV_ACKCOMPL: 1048 err = 0; 1049 break; 1050 case FWOHCIEV_ACKBSA: 1051 case FWOHCIEV_ACKBSB: 1052 case FWOHCIEV_ACKBSX: 1053 device_printf(sc->fc.dev, "txd err=%2x %s\n", stat, fwohcicode[stat]); 1054 err = EBUSY; 1055 break; 1056 case FWOHCIEV_FLUSHED: 1057 case FWOHCIEV_ACKTARD: 1058 device_printf(sc->fc.dev, "txd err=%2x %s\n", stat, fwohcicode[stat]); 1059 err = EAGAIN; 1060 break; 1061 case FWOHCIEV_MISSACK: 1062 case FWOHCIEV_UNDRRUN: 1063 case FWOHCIEV_OVRRUN: 1064 case FWOHCIEV_DESCERR: 1065 case FWOHCIEV_DTRDERR: 1066 case FWOHCIEV_TIMEOUT: 1067 case FWOHCIEV_TCODERR: 1068 case FWOHCIEV_UNKNOWN: 1069 case FWOHCIEV_ACKDERR: 1070 case FWOHCIEV_ACKTERR: 1071 default: 1072 device_printf(sc->fc.dev, "txd err=%2x %s\n", 1073 stat, fwohcicode[stat]); 1074 err = EINVAL; 1075 break; 1076 } 1077 if (tr->xfer != NULL) { 1078 xfer = tr->xfer; 1079 if (xfer->state == FWXF_RCVD) { 1080 if (firewire_debug) 1081 printf("already rcvd\n"); 1082 fw_xfer_done(xfer); 1083 } else { 1084 xfer->state = FWXF_SENT; 1085 if (err == EBUSY && fc->status != FWBUSRESET) { 1086 xfer->state = FWXF_BUSY; 1087 xfer->resp = err; 1088 if (xfer->retry_req != NULL) 1089 xfer->retry_req(xfer); 1090 else { 1091 xfer->recv.len = 0; 1092 fw_xfer_done(xfer); 1093 } 1094 } else if (stat != FWOHCIEV_ACKPEND) { 1095 if (stat != FWOHCIEV_ACKCOMPL) 1096 xfer->state = FWXF_SENTERR; 1097 xfer->resp = err; 1098 xfer->recv.len = 0; 1099 fw_xfer_done(xfer); 1100 } 1101 } 1102 /* 1103 * The watchdog timer takes care of split 1104 * transcation timeout for ACKPEND case. 1105 */ 1106 } else { 1107 printf("this shouldn't happen\n"); 1108 } 1109 dbch->xferq.queued --; 1110 tr->xfer = NULL; 1111 1112 packets ++; 1113 tr = STAILQ_NEXT(tr, link); 1114 dbch->bottom = tr; 1115 if (dbch->bottom == dbch->top) { 1116 /* we reaches the end of context program */ 1117 if (firewire_debug && dbch->xferq.queued > 0) 1118 printf("queued > 0\n"); 1119 break; 1120 } 1121 } 1122 out: 1123 if ((dbch->flags & FWOHCI_DBCH_FULL) && packets > 0) { 1124 printf("make free slot\n"); 1125 dbch->flags &= ~FWOHCI_DBCH_FULL; 1126 fwohci_start(sc, dbch); 1127 } 1128 splx(s); 1129 } 1130 1131 static void 1132 fwohci_db_free(struct fwohci_dbch *dbch) 1133 { 1134 struct fwohcidb_tr *db_tr; 1135 int idb; 1136 1137 if ((dbch->flags & FWOHCI_DBCH_INIT) == 0) 1138 return; 1139 1140 for(db_tr = STAILQ_FIRST(&dbch->db_trq), idb = 0; idb < dbch->ndb; 1141 db_tr = STAILQ_NEXT(db_tr, link), idb++){ 1142 if ((dbch->xferq.flag & FWXFERQ_EXTBUF) == 0 && 1143 db_tr->buf != NULL) { 1144 fwdma_free_size(dbch->dmat, db_tr->dma_map, 1145 db_tr->buf, dbch->xferq.psize); 1146 db_tr->buf = NULL; 1147 } else if (db_tr->dma_map != NULL) 1148 bus_dmamap_destroy(dbch->dmat, db_tr->dma_map); 1149 } 1150 dbch->ndb = 0; 1151 db_tr = STAILQ_FIRST(&dbch->db_trq); 1152 fwdma_free_multiseg(dbch->am); 1153 free(db_tr, M_FW); 1154 STAILQ_INIT(&dbch->db_trq); 1155 dbch->flags &= ~FWOHCI_DBCH_INIT; 1156 } 1157 1158 static void 1159 fwohci_db_init(struct fwohci_softc *sc, struct fwohci_dbch *dbch) 1160 { 1161 int idb; 1162 struct fwohcidb_tr *db_tr; 1163 1164 if ((dbch->flags & FWOHCI_DBCH_INIT) != 0) 1165 goto out; 1166 1167 /* create dma_tag for buffers */ 1168 #define MAX_REQCOUNT 0xffff 1169 if (bus_dma_tag_create(/*parent*/ sc->fc.dmat, 1170 /*alignment*/ 1, /*boundary*/ 0, 1171 /*lowaddr*/ BUS_SPACE_MAXADDR_32BIT, 1172 /*highaddr*/ BUS_SPACE_MAXADDR, 1173 /*filter*/NULL, /*filterarg*/NULL, 1174 /*maxsize*/ dbch->xferq.psize, 1175 /*nsegments*/ dbch->ndesc > 3 ? dbch->ndesc - 2 : 1, 1176 /*maxsegsz*/ MAX_REQCOUNT, 1177 /*flags*/ 0, 1178 #if __FreeBSD_version >= 501102 1179 /*lockfunc*/busdma_lock_mutex, 1180 /*lockarg*/&Giant, 1181 #endif 1182 &dbch->dmat)) 1183 return; 1184 1185 /* allocate DB entries and attach one to each DMA channels */ 1186 /* DB entry must start at 16 bytes bounary. */ 1187 STAILQ_INIT(&dbch->db_trq); 1188 db_tr = (struct fwohcidb_tr *) 1189 malloc(sizeof(struct fwohcidb_tr) * dbch->ndb, 1190 M_FW, M_WAITOK | M_ZERO); 1191 if(db_tr == NULL){ 1192 printf("fwohci_db_init: malloc(1) failed\n"); 1193 return; 1194 } 1195 1196 #define DB_SIZE(x) (sizeof(struct fwohcidb) * (x)->ndesc) 1197 dbch->am = fwdma_malloc_multiseg(&sc->fc, DB_SIZE(dbch), 1198 DB_SIZE(dbch), dbch->ndb, BUS_DMA_WAITOK); 1199 if (dbch->am == NULL) { 1200 printf("fwohci_db_init: fwdma_malloc_multiseg failed\n"); 1201 return; 1202 } 1203 /* Attach DB to DMA ch. */ 1204 for(idb = 0 ; idb < dbch->ndb ; idb++){ 1205 db_tr->dbcnt = 0; 1206 db_tr->db = (struct fwohcidb *)fwdma_v_addr(dbch->am, idb); 1207 db_tr->bus_addr = fwdma_bus_addr(dbch->am, idb); 1208 /* create dmamap for buffers */ 1209 /* XXX do we need 4bytes alignment tag? */ 1210 /* XXX don't alloc dma_map for AR */ 1211 if (bus_dmamap_create(dbch->dmat, 0, &db_tr->dma_map) != 0) { 1212 printf("bus_dmamap_create failed\n"); 1213 dbch->flags = FWOHCI_DBCH_INIT; /* XXX fake */ 1214 fwohci_db_free(dbch); 1215 return; 1216 } 1217 STAILQ_INSERT_TAIL(&dbch->db_trq, db_tr, link); 1218 if (dbch->xferq.flag & FWXFERQ_EXTBUF) { 1219 if (idb % dbch->xferq.bnpacket == 0) 1220 dbch->xferq.bulkxfer[idb / dbch->xferq.bnpacket 1221 ].start = (caddr_t)db_tr; 1222 if ((idb + 1) % dbch->xferq.bnpacket == 0) 1223 dbch->xferq.bulkxfer[idb / dbch->xferq.bnpacket 1224 ].end = (caddr_t)db_tr; 1225 } 1226 db_tr++; 1227 } 1228 STAILQ_LAST(&dbch->db_trq, fwohcidb_tr,link)->link.stqe_next 1229 = STAILQ_FIRST(&dbch->db_trq); 1230 out: 1231 dbch->xferq.queued = 0; 1232 dbch->pdb_tr = NULL; 1233 dbch->top = STAILQ_FIRST(&dbch->db_trq); 1234 dbch->bottom = dbch->top; 1235 dbch->flags = FWOHCI_DBCH_INIT; 1236 } 1237 1238 static int 1239 fwohci_itx_disable(struct firewire_comm *fc, int dmach) 1240 { 1241 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 1242 int sleepch; 1243 1244 OWRITE(sc, OHCI_ITCTLCLR(dmach), 1245 OHCI_CNTL_DMA_RUN | OHCI_CNTL_CYCMATCH_S); 1246 OWRITE(sc, OHCI_IT_MASKCLR, 1 << dmach); 1247 OWRITE(sc, OHCI_IT_STATCLR, 1 << dmach); 1248 /* XXX we cannot free buffers until the DMA really stops */ 1249 tsleep((void *)&sleepch, FWPRI, "fwitxd", hz); 1250 fwohci_db_free(&sc->it[dmach]); 1251 sc->it[dmach].xferq.flag &= ~FWXFERQ_RUNNING; 1252 return 0; 1253 } 1254 1255 static int 1256 fwohci_irx_disable(struct firewire_comm *fc, int dmach) 1257 { 1258 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 1259 int sleepch; 1260 1261 OWRITE(sc, OHCI_IRCTLCLR(dmach), OHCI_CNTL_DMA_RUN); 1262 OWRITE(sc, OHCI_IR_MASKCLR, 1 << dmach); 1263 OWRITE(sc, OHCI_IR_STATCLR, 1 << dmach); 1264 /* XXX we cannot free buffers until the DMA really stops */ 1265 tsleep((void *)&sleepch, FWPRI, "fwirxd", hz); 1266 fwohci_db_free(&sc->ir[dmach]); 1267 sc->ir[dmach].xferq.flag &= ~FWXFERQ_RUNNING; 1268 return 0; 1269 } 1270 1271 #if BYTE_ORDER == BIG_ENDIAN 1272 static void 1273 fwohci_irx_post (struct firewire_comm *fc , u_int32_t *qld) 1274 { 1275 qld[0] = FWOHCI_DMA_READ(qld[0]); 1276 return; 1277 } 1278 #endif 1279 1280 static int 1281 fwohci_tx_enable(struct fwohci_softc *sc, struct fwohci_dbch *dbch) 1282 { 1283 int err = 0; 1284 int idb, z, i, dmach = 0, ldesc; 1285 u_int32_t off = NULL; 1286 struct fwohcidb_tr *db_tr; 1287 volatile struct fwohcidb *db; 1288 1289 if(!(dbch->xferq.flag & FWXFERQ_EXTBUF)){ 1290 err = EINVAL; 1291 return err; 1292 } 1293 z = dbch->ndesc; 1294 for(dmach = 0 ; dmach < sc->fc.nisodma ; dmach++){ 1295 if( &sc->it[dmach] == dbch){ 1296 off = OHCI_ITOFF(dmach); 1297 break; 1298 } 1299 } 1300 if(off == NULL){ 1301 err = EINVAL; 1302 return err; 1303 } 1304 if(dbch->xferq.flag & FWXFERQ_RUNNING) 1305 return err; 1306 dbch->xferq.flag |= FWXFERQ_RUNNING; 1307 for( i = 0, dbch->bottom = dbch->top; i < (dbch->ndb - 1); i++){ 1308 dbch->bottom = STAILQ_NEXT(dbch->bottom, link); 1309 } 1310 db_tr = dbch->top; 1311 for (idb = 0; idb < dbch->ndb; idb ++) { 1312 fwohci_add_tx_buf(dbch, db_tr, idb); 1313 if(STAILQ_NEXT(db_tr, link) == NULL){ 1314 break; 1315 } 1316 db = db_tr->db; 1317 ldesc = db_tr->dbcnt - 1; 1318 FWOHCI_DMA_WRITE(db[0].db.desc.depend, 1319 STAILQ_NEXT(db_tr, link)->bus_addr | z); 1320 db[ldesc].db.desc.depend = db[0].db.desc.depend; 1321 if(dbch->xferq.flag & FWXFERQ_EXTBUF){ 1322 if(((idb + 1 ) % dbch->xferq.bnpacket) == 0){ 1323 FWOHCI_DMA_SET( 1324 db[ldesc].db.desc.cmd, 1325 OHCI_INTERRUPT_ALWAYS); 1326 /* OHCI 1.1 and above */ 1327 FWOHCI_DMA_SET( 1328 db[0].db.desc.cmd, 1329 OHCI_INTERRUPT_ALWAYS); 1330 } 1331 } 1332 db_tr = STAILQ_NEXT(db_tr, link); 1333 } 1334 FWOHCI_DMA_CLEAR( 1335 dbch->bottom->db[dbch->bottom->dbcnt - 1].db.desc.depend, 0xf); 1336 return err; 1337 } 1338 1339 static int 1340 fwohci_rx_enable(struct fwohci_softc *sc, struct fwohci_dbch *dbch) 1341 { 1342 int err = 0; 1343 int idb, z, i, dmach = 0, ldesc; 1344 u_int32_t off = NULL; 1345 struct fwohcidb_tr *db_tr; 1346 volatile struct fwohcidb *db; 1347 1348 z = dbch->ndesc; 1349 if(&sc->arrq == dbch){ 1350 off = OHCI_ARQOFF; 1351 }else if(&sc->arrs == dbch){ 1352 off = OHCI_ARSOFF; 1353 }else{ 1354 for(dmach = 0 ; dmach < sc->fc.nisodma ; dmach++){ 1355 if( &sc->ir[dmach] == dbch){ 1356 off = OHCI_IROFF(dmach); 1357 break; 1358 } 1359 } 1360 } 1361 if(off == NULL){ 1362 err = EINVAL; 1363 return err; 1364 } 1365 if(dbch->xferq.flag & FWXFERQ_STREAM){ 1366 if(dbch->xferq.flag & FWXFERQ_RUNNING) 1367 return err; 1368 }else{ 1369 if(dbch->xferq.flag & FWXFERQ_RUNNING){ 1370 err = EBUSY; 1371 return err; 1372 } 1373 } 1374 dbch->xferq.flag |= FWXFERQ_RUNNING; 1375 dbch->top = STAILQ_FIRST(&dbch->db_trq); 1376 for( i = 0, dbch->bottom = dbch->top; i < (dbch->ndb - 1); i++){ 1377 dbch->bottom = STAILQ_NEXT(dbch->bottom, link); 1378 } 1379 db_tr = dbch->top; 1380 for (idb = 0; idb < dbch->ndb; idb ++) { 1381 fwohci_add_rx_buf(dbch, db_tr, idb, &sc->dummy_dma); 1382 if (STAILQ_NEXT(db_tr, link) == NULL) 1383 break; 1384 db = db_tr->db; 1385 ldesc = db_tr->dbcnt - 1; 1386 FWOHCI_DMA_WRITE(db[ldesc].db.desc.depend, 1387 STAILQ_NEXT(db_tr, link)->bus_addr | z); 1388 if(dbch->xferq.flag & FWXFERQ_EXTBUF){ 1389 if(((idb + 1 ) % dbch->xferq.bnpacket) == 0){ 1390 FWOHCI_DMA_SET( 1391 db[ldesc].db.desc.cmd, 1392 OHCI_INTERRUPT_ALWAYS); 1393 FWOHCI_DMA_CLEAR( 1394 db[ldesc].db.desc.depend, 1395 0xf); 1396 } 1397 } 1398 db_tr = STAILQ_NEXT(db_tr, link); 1399 } 1400 FWOHCI_DMA_CLEAR( 1401 dbch->bottom->db[db_tr->dbcnt - 1].db.desc.depend, 0xf); 1402 dbch->buf_offset = 0; 1403 fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREREAD); 1404 fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREWRITE); 1405 if(dbch->xferq.flag & FWXFERQ_STREAM){ 1406 return err; 1407 }else{ 1408 OWRITE(sc, OHCI_DMACMD(off), dbch->top->bus_addr | z); 1409 } 1410 OWRITE(sc, OHCI_DMACTL(off), OHCI_CNTL_DMA_RUN); 1411 return err; 1412 } 1413 1414 static int 1415 fwohci_next_cycle(struct firewire_comm *fc, int cycle_now) 1416 { 1417 int sec, cycle, cycle_match; 1418 1419 cycle = cycle_now & 0x1fff; 1420 sec = cycle_now >> 13; 1421 #define CYCLE_MOD 0x10 1422 #if 1 1423 #define CYCLE_DELAY 8 /* min delay to start DMA */ 1424 #else 1425 #define CYCLE_DELAY 7000 /* min delay to start DMA */ 1426 #endif 1427 cycle = cycle + CYCLE_DELAY; 1428 if (cycle >= 8000) { 1429 sec ++; 1430 cycle -= 8000; 1431 } 1432 cycle = roundup2(cycle, CYCLE_MOD); 1433 if (cycle >= 8000) { 1434 sec ++; 1435 if (cycle == 8000) 1436 cycle = 0; 1437 else 1438 cycle = CYCLE_MOD; 1439 } 1440 cycle_match = ((sec << 13) | cycle) & 0x7ffff; 1441 1442 return(cycle_match); 1443 } 1444 1445 static int 1446 fwohci_itxbuf_enable(struct firewire_comm *fc, int dmach) 1447 { 1448 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 1449 int err = 0; 1450 unsigned short tag, ich; 1451 struct fwohci_dbch *dbch; 1452 int cycle_match, cycle_now, s, ldesc; 1453 u_int32_t stat; 1454 struct fw_bulkxfer *first, *chunk, *prev; 1455 struct fw_xferq *it; 1456 1457 dbch = &sc->it[dmach]; 1458 it = &dbch->xferq; 1459 1460 tag = (it->flag >> 6) & 3; 1461 ich = it->flag & 0x3f; 1462 if ((dbch->flags & FWOHCI_DBCH_INIT) == 0) { 1463 dbch->ndb = it->bnpacket * it->bnchunk; 1464 dbch->ndesc = 3; 1465 fwohci_db_init(sc, dbch); 1466 if ((dbch->flags & FWOHCI_DBCH_INIT) == 0) 1467 return ENOMEM; 1468 err = fwohci_tx_enable(sc, dbch); 1469 } 1470 if(err) 1471 return err; 1472 1473 ldesc = dbch->ndesc - 1; 1474 s = splfw(); 1475 prev = STAILQ_LAST(&it->stdma, fw_bulkxfer, link); 1476 while ((chunk = STAILQ_FIRST(&it->stvalid)) != NULL) { 1477 volatile struct fwohcidb *db; 1478 1479 fwdma_sync_multiseg(it->buf, chunk->poffset, it->bnpacket, 1480 BUS_DMASYNC_PREWRITE); 1481 fwohci_txbufdb(sc, dmach, chunk); 1482 if (prev != NULL) { 1483 db = ((struct fwohcidb_tr *)(prev->end))->db; 1484 #if 0 /* XXX necessary? */ 1485 FWOHCI_DMA_SET(db[ldesc].db.desc.cmd, 1486 OHCI_BRANCH_ALWAYS); 1487 #endif 1488 #if 0 /* if bulkxfer->npacket changes */ 1489 db[ldesc].db.desc.depend = db[0].db.desc.depend = 1490 ((struct fwohcidb_tr *) 1491 (chunk->start))->bus_addr | dbch->ndesc; 1492 #else 1493 FWOHCI_DMA_SET(db[0].db.desc.depend, dbch->ndesc); 1494 FWOHCI_DMA_SET(db[ldesc].db.desc.depend, dbch->ndesc); 1495 #endif 1496 } 1497 STAILQ_REMOVE_HEAD(&it->stvalid, link); 1498 STAILQ_INSERT_TAIL(&it->stdma, chunk, link); 1499 prev = chunk; 1500 } 1501 fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREWRITE); 1502 fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREREAD); 1503 splx(s); 1504 stat = OREAD(sc, OHCI_ITCTL(dmach)); 1505 if (firewire_debug && (stat & OHCI_CNTL_CYCMATCH_S)) 1506 printf("stat 0x%x\n", stat); 1507 1508 if (stat & (OHCI_CNTL_DMA_ACTIVE | OHCI_CNTL_CYCMATCH_S)) 1509 return 0; 1510 1511 #if 0 1512 OWRITE(sc, OHCI_ITCTLCLR(dmach), OHCI_CNTL_DMA_RUN); 1513 #endif 1514 OWRITE(sc, OHCI_IT_MASKCLR, 1 << dmach); 1515 OWRITE(sc, OHCI_IT_STATCLR, 1 << dmach); 1516 OWRITE(sc, OHCI_IT_MASK, 1 << dmach); 1517 OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_DMA_IT); 1518 1519 first = STAILQ_FIRST(&it->stdma); 1520 OWRITE(sc, OHCI_ITCMD(dmach), 1521 ((struct fwohcidb_tr *)(first->start))->bus_addr | dbch->ndesc); 1522 if (firewire_debug) { 1523 printf("fwohci_itxbuf_enable: kick 0x%08x\n", stat); 1524 #if 1 1525 dump_dma(sc, ITX_CH + dmach); 1526 #endif 1527 } 1528 if ((stat & OHCI_CNTL_DMA_RUN) == 0) { 1529 #if 1 1530 /* Don't start until all chunks are buffered */ 1531 if (STAILQ_FIRST(&it->stfree) != NULL) 1532 goto out; 1533 #endif 1534 #if 1 1535 /* Clear cycle match counter bits */ 1536 OWRITE(sc, OHCI_ITCTLCLR(dmach), 0xffff0000); 1537 1538 /* 2bit second + 13bit cycle */ 1539 cycle_now = (fc->cyctimer(fc) >> 12) & 0x7fff; 1540 cycle_match = fwohci_next_cycle(fc, cycle_now); 1541 1542 OWRITE(sc, OHCI_ITCTL(dmach), 1543 OHCI_CNTL_CYCMATCH_S | (cycle_match << 16) 1544 | OHCI_CNTL_DMA_RUN); 1545 #else 1546 OWRITE(sc, OHCI_ITCTL(dmach), OHCI_CNTL_DMA_RUN); 1547 #endif 1548 if (firewire_debug) { 1549 printf("cycle_match: 0x%04x->0x%04x\n", 1550 cycle_now, cycle_match); 1551 dump_dma(sc, ITX_CH + dmach); 1552 dump_db(sc, ITX_CH + dmach); 1553 } 1554 } else if ((stat & OHCI_CNTL_CYCMATCH_S) == 0) { 1555 device_printf(sc->fc.dev, 1556 "IT DMA underrun (0x%08x)\n", stat); 1557 OWRITE(sc, OHCI_ITCTL(dmach), OHCI_CNTL_DMA_WAKE); 1558 } 1559 out: 1560 return err; 1561 } 1562 1563 static int 1564 fwohci_irx_enable(struct firewire_comm *fc, int dmach) 1565 { 1566 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 1567 int err = 0, s, ldesc; 1568 unsigned short tag, ich; 1569 u_int32_t stat; 1570 struct fwohci_dbch *dbch; 1571 struct fwohcidb_tr *db_tr; 1572 struct fw_bulkxfer *first, *prev, *chunk; 1573 struct fw_xferq *ir; 1574 1575 dbch = &sc->ir[dmach]; 1576 ir = &dbch->xferq; 1577 1578 if ((ir->flag & FWXFERQ_RUNNING) == 0) { 1579 tag = (ir->flag >> 6) & 3; 1580 ich = ir->flag & 0x3f; 1581 OWRITE(sc, OHCI_IRMATCH(dmach), tagbit[tag] | ich); 1582 1583 ir->queued = 0; 1584 dbch->ndb = ir->bnpacket * ir->bnchunk; 1585 dbch->ndesc = 2; 1586 fwohci_db_init(sc, dbch); 1587 if ((dbch->flags & FWOHCI_DBCH_INIT) == 0) 1588 return ENOMEM; 1589 err = fwohci_rx_enable(sc, dbch); 1590 } 1591 if(err) 1592 return err; 1593 1594 first = STAILQ_FIRST(&ir->stfree); 1595 if (first == NULL) { 1596 device_printf(fc->dev, "IR DMA no free chunk\n"); 1597 return 0; 1598 } 1599 1600 ldesc = dbch->ndesc - 1; 1601 s = splfw(); 1602 prev = STAILQ_LAST(&ir->stdma, fw_bulkxfer, link); 1603 while ((chunk = STAILQ_FIRST(&ir->stfree)) != NULL) { 1604 volatile struct fwohcidb *db; 1605 1606 #if 1 /* XXX for if_fwe */ 1607 if (chunk->mbuf != NULL) { 1608 db_tr = (struct fwohcidb_tr *)(chunk->start); 1609 db_tr->dbcnt = 1; 1610 err = bus_dmamap_load_mbuf(dbch->dmat, db_tr->dma_map, 1611 chunk->mbuf, fwohci_execute_db2, db_tr, 1612 /* flags */0); 1613 FWOHCI_DMA_SET(db_tr->db[1].db.desc.cmd, 1614 OHCI_UPDATE | OHCI_INPUT_LAST | 1615 OHCI_INTERRUPT_ALWAYS | OHCI_BRANCH_ALWAYS); 1616 } 1617 #endif 1618 db = ((struct fwohcidb_tr *)(chunk->end))->db; 1619 FWOHCI_DMA_WRITE(db[ldesc].db.desc.res, 0); 1620 FWOHCI_DMA_CLEAR(db[ldesc].db.desc.depend, 0xf); 1621 if (prev != NULL) { 1622 db = ((struct fwohcidb_tr *)(prev->end))->db; 1623 FWOHCI_DMA_SET(db[ldesc].db.desc.depend, dbch->ndesc); 1624 } 1625 STAILQ_REMOVE_HEAD(&ir->stfree, link); 1626 STAILQ_INSERT_TAIL(&ir->stdma, chunk, link); 1627 prev = chunk; 1628 } 1629 fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREWRITE); 1630 fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREREAD); 1631 splx(s); 1632 stat = OREAD(sc, OHCI_IRCTL(dmach)); 1633 if (stat & OHCI_CNTL_DMA_ACTIVE) 1634 return 0; 1635 if (stat & OHCI_CNTL_DMA_RUN) { 1636 OWRITE(sc, OHCI_IRCTLCLR(dmach), OHCI_CNTL_DMA_RUN); 1637 device_printf(sc->fc.dev, "IR DMA overrun (0x%08x)\n", stat); 1638 } 1639 1640 if (firewire_debug) 1641 printf("start IR DMA 0x%x\n", stat); 1642 OWRITE(sc, OHCI_IR_MASKCLR, 1 << dmach); 1643 OWRITE(sc, OHCI_IR_STATCLR, 1 << dmach); 1644 OWRITE(sc, OHCI_IR_MASK, 1 << dmach); 1645 OWRITE(sc, OHCI_IRCTLCLR(dmach), 0xf0000000); 1646 OWRITE(sc, OHCI_IRCTL(dmach), OHCI_CNTL_ISOHDR); 1647 OWRITE(sc, OHCI_IRCMD(dmach), 1648 ((struct fwohcidb_tr *)(first->start))->bus_addr 1649 | dbch->ndesc); 1650 OWRITE(sc, OHCI_IRCTL(dmach), OHCI_CNTL_DMA_RUN); 1651 OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_DMA_IR); 1652 #if 0 1653 dump_db(sc, IRX_CH + dmach); 1654 #endif 1655 return err; 1656 } 1657 1658 int 1659 fwohci_stop(struct fwohci_softc *sc, device_t dev) 1660 { 1661 u_int i; 1662 1663 /* Now stopping all DMA channel */ 1664 OWRITE(sc, OHCI_ARQCTLCLR, OHCI_CNTL_DMA_RUN); 1665 OWRITE(sc, OHCI_ARSCTLCLR, OHCI_CNTL_DMA_RUN); 1666 OWRITE(sc, OHCI_ATQCTLCLR, OHCI_CNTL_DMA_RUN); 1667 OWRITE(sc, OHCI_ATSCTLCLR, OHCI_CNTL_DMA_RUN); 1668 1669 for( i = 0 ; i < sc->fc.nisodma ; i ++ ){ 1670 OWRITE(sc, OHCI_IRCTLCLR(i), OHCI_CNTL_DMA_RUN); 1671 OWRITE(sc, OHCI_ITCTLCLR(i), OHCI_CNTL_DMA_RUN); 1672 } 1673 1674 /* FLUSH FIFO and reset Transmitter/Reciever */ 1675 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_RESET); 1676 1677 /* Stop interrupt */ 1678 OWRITE(sc, FWOHCI_INTMASKCLR, 1679 OHCI_INT_EN | OHCI_INT_ERR | OHCI_INT_PHY_SID 1680 | OHCI_INT_PHY_INT 1681 | OHCI_INT_DMA_ATRQ | OHCI_INT_DMA_ATRS 1682 | OHCI_INT_DMA_PRRQ | OHCI_INT_DMA_PRRS 1683 | OHCI_INT_DMA_ARRQ | OHCI_INT_DMA_ARRS 1684 | OHCI_INT_PHY_BUS_R); 1685 1686 fw_drain_txq(&sc->fc); 1687 1688 /* XXX Link down? Bus reset? */ 1689 return 0; 1690 } 1691 1692 int 1693 fwohci_resume(struct fwohci_softc *sc, device_t dev) 1694 { 1695 int i; 1696 struct fw_xferq *ir; 1697 struct fw_bulkxfer *chunk; 1698 1699 fwohci_reset(sc, dev); 1700 /* XXX resume isochronus receive automatically. (how about TX?) */ 1701 for(i = 0; i < sc->fc.nisodma; i ++) { 1702 ir = &sc->ir[i].xferq; 1703 if((ir->flag & FWXFERQ_RUNNING) != 0) { 1704 device_printf(sc->fc.dev, 1705 "resume iso receive ch: %d\n", i); 1706 ir->flag &= ~FWXFERQ_RUNNING; 1707 /* requeue stdma to stfree */ 1708 while((chunk = STAILQ_FIRST(&ir->stdma)) != NULL) { 1709 STAILQ_REMOVE_HEAD(&ir->stdma, link); 1710 STAILQ_INSERT_TAIL(&ir->stfree, chunk, link); 1711 } 1712 sc->fc.irx_enable(&sc->fc, i); 1713 } 1714 } 1715 1716 bus_generic_resume(dev); 1717 sc->fc.ibr(&sc->fc); 1718 return 0; 1719 } 1720 1721 #define ACK_ALL 1722 static void 1723 fwohci_intr_body(struct fwohci_softc *sc, u_int32_t stat, int count) 1724 { 1725 u_int32_t irstat, itstat; 1726 u_int i; 1727 struct firewire_comm *fc = (struct firewire_comm *)sc; 1728 1729 #ifdef OHCI_DEBUG 1730 if(stat & OREAD(sc, FWOHCI_INTMASK)) 1731 device_printf(fc->dev, "INTERRUPT < %s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s> 0x%08x, 0x%08x\n", 1732 stat & OHCI_INT_EN ? "DMA_EN ":"", 1733 stat & OHCI_INT_PHY_REG ? "PHY_REG ":"", 1734 stat & OHCI_INT_CYC_LONG ? "CYC_LONG ":"", 1735 stat & OHCI_INT_ERR ? "INT_ERR ":"", 1736 stat & OHCI_INT_CYC_ERR ? "CYC_ERR ":"", 1737 stat & OHCI_INT_CYC_LOST ? "CYC_LOST ":"", 1738 stat & OHCI_INT_CYC_64SECOND ? "CYC_64SECOND ":"", 1739 stat & OHCI_INT_CYC_START ? "CYC_START ":"", 1740 stat & OHCI_INT_PHY_INT ? "PHY_INT ":"", 1741 stat & OHCI_INT_PHY_BUS_R ? "BUS_RESET ":"", 1742 stat & OHCI_INT_PHY_SID ? "SID ":"", 1743 stat & OHCI_INT_LR_ERR ? "DMA_LR_ERR ":"", 1744 stat & OHCI_INT_PW_ERR ? "DMA_PW_ERR ":"", 1745 stat & OHCI_INT_DMA_IR ? "DMA_IR ":"", 1746 stat & OHCI_INT_DMA_IT ? "DMA_IT " :"", 1747 stat & OHCI_INT_DMA_PRRS ? "DMA_PRRS " :"", 1748 stat & OHCI_INT_DMA_PRRQ ? "DMA_PRRQ " :"", 1749 stat & OHCI_INT_DMA_ARRS ? "DMA_ARRS " :"", 1750 stat & OHCI_INT_DMA_ARRQ ? "DMA_ARRQ " :"", 1751 stat & OHCI_INT_DMA_ATRS ? "DMA_ATRS " :"", 1752 stat & OHCI_INT_DMA_ATRQ ? "DMA_ATRQ " :"", 1753 stat, OREAD(sc, FWOHCI_INTMASK) 1754 ); 1755 #endif 1756 /* Bus reset */ 1757 if(stat & OHCI_INT_PHY_BUS_R ){ 1758 if (fc->status == FWBUSRESET) 1759 goto busresetout; 1760 /* Disable bus reset interrupt until sid recv. */ 1761 OWRITE(sc, FWOHCI_INTMASKCLR, OHCI_INT_PHY_BUS_R); 1762 1763 device_printf(fc->dev, "BUS reset\n"); 1764 OWRITE(sc, FWOHCI_INTMASKCLR, OHCI_INT_CYC_LOST); 1765 OWRITE(sc, OHCI_LNKCTLCLR, OHCI_CNTL_CYCSRC); 1766 1767 OWRITE(sc, OHCI_ATQCTLCLR, OHCI_CNTL_DMA_RUN); 1768 sc->atrq.xferq.flag &= ~FWXFERQ_RUNNING; 1769 OWRITE(sc, OHCI_ATSCTLCLR, OHCI_CNTL_DMA_RUN); 1770 sc->atrs.xferq.flag &= ~FWXFERQ_RUNNING; 1771 1772 #ifndef ACK_ALL 1773 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_PHY_BUS_R); 1774 #endif 1775 fw_busreset(fc); 1776 OWRITE(sc, OHCI_CROMHDR, ntohl(sc->fc.config_rom[0])); 1777 OWRITE(sc, OHCI_BUS_OPT, ntohl(sc->fc.config_rom[2])); 1778 } 1779 busresetout: 1780 if((stat & OHCI_INT_DMA_IR )){ 1781 #ifndef ACK_ALL 1782 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_IR); 1783 #endif 1784 #if __FreeBSD_version >= 500000 1785 irstat = atomic_readandclear_int(&sc->irstat); 1786 #else 1787 irstat = sc->irstat; 1788 sc->irstat = 0; 1789 #endif 1790 for(i = 0; i < fc->nisodma ; i++){ 1791 struct fwohci_dbch *dbch; 1792 1793 if((irstat & (1 << i)) != 0){ 1794 dbch = &sc->ir[i]; 1795 if ((dbch->xferq.flag & FWXFERQ_OPEN) == 0) { 1796 device_printf(sc->fc.dev, 1797 "dma(%d) not active\n", i); 1798 continue; 1799 } 1800 fwohci_rbuf_update(sc, i); 1801 } 1802 } 1803 } 1804 if((stat & OHCI_INT_DMA_IT )){ 1805 #ifndef ACK_ALL 1806 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_IT); 1807 #endif 1808 #if __FreeBSD_version >= 500000 1809 itstat = atomic_readandclear_int(&sc->itstat); 1810 #else 1811 itstat = sc->itstat; 1812 sc->itstat = 0; 1813 #endif 1814 for(i = 0; i < fc->nisodma ; i++){ 1815 if((itstat & (1 << i)) != 0){ 1816 fwohci_tbuf_update(sc, i); 1817 } 1818 } 1819 } 1820 if((stat & OHCI_INT_DMA_PRRS )){ 1821 #ifndef ACK_ALL 1822 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_PRRS); 1823 #endif 1824 #if 0 1825 dump_dma(sc, ARRS_CH); 1826 dump_db(sc, ARRS_CH); 1827 #endif 1828 fwohci_arcv(sc, &sc->arrs, count); 1829 } 1830 if((stat & OHCI_INT_DMA_PRRQ )){ 1831 #ifndef ACK_ALL 1832 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_PRRQ); 1833 #endif 1834 #if 0 1835 dump_dma(sc, ARRQ_CH); 1836 dump_db(sc, ARRQ_CH); 1837 #endif 1838 fwohci_arcv(sc, &sc->arrq, count); 1839 } 1840 if(stat & OHCI_INT_PHY_SID){ 1841 u_int32_t *buf, node_id; 1842 int plen; 1843 1844 #ifndef ACK_ALL 1845 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_PHY_SID); 1846 #endif 1847 /* Enable bus reset interrupt */ 1848 OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_PHY_BUS_R); 1849 /* Allow async. request to us */ 1850 OWRITE(sc, OHCI_AREQHI, 1 << 31); 1851 /* XXX insecure ?? */ 1852 OWRITE(sc, OHCI_PREQHI, 0x7fffffff); 1853 OWRITE(sc, OHCI_PREQLO, 0xffffffff); 1854 OWRITE(sc, OHCI_PREQUPPER, 0x10000); 1855 /* Set ATRetries register */ 1856 OWRITE(sc, OHCI_ATRETRY, 1<<(13+16) | 0xfff); 1857 /* 1858 ** Checking whether the node is root or not. If root, turn on 1859 ** cycle master. 1860 */ 1861 node_id = OREAD(sc, FWOHCI_NODEID); 1862 plen = OREAD(sc, OHCI_SID_CNT); 1863 1864 device_printf(fc->dev, "node_id=0x%08x, gen=%d, ", 1865 node_id, (plen >> 16) & 0xff); 1866 if (!(node_id & OHCI_NODE_VALID)) { 1867 printf("Bus reset failure\n"); 1868 goto sidout; 1869 } 1870 if (node_id & OHCI_NODE_ROOT) { 1871 printf("CYCLEMASTER mode\n"); 1872 OWRITE(sc, OHCI_LNKCTL, 1873 OHCI_CNTL_CYCMTR | OHCI_CNTL_CYCTIMER); 1874 } else { 1875 printf("non CYCLEMASTER mode\n"); 1876 OWRITE(sc, OHCI_LNKCTLCLR, OHCI_CNTL_CYCMTR); 1877 OWRITE(sc, OHCI_LNKCTL, OHCI_CNTL_CYCTIMER); 1878 } 1879 fc->nodeid = node_id & 0x3f; 1880 1881 if (plen & OHCI_SID_ERR) { 1882 device_printf(fc->dev, "SID Error\n"); 1883 goto sidout; 1884 } 1885 plen &= OHCI_SID_CNT_MASK; 1886 if (plen < 4 || plen > OHCI_SIDSIZE) { 1887 device_printf(fc->dev, "invalid SID len = %d\n", plen); 1888 goto sidout; 1889 } 1890 plen -= 4; /* chop control info */ 1891 buf = (u_int32_t *)malloc(OHCI_SIDSIZE, M_FW, M_NOWAIT); 1892 if (buf == NULL) { 1893 device_printf(fc->dev, "malloc failed\n"); 1894 goto sidout; 1895 } 1896 for (i = 0; i < plen / 4; i ++) 1897 buf[i] = FWOHCI_DMA_READ(sc->sid_buf[i+1]); 1898 #if 1 1899 /* pending all pre-bus_reset packets */ 1900 fwohci_txd(sc, &sc->atrq); 1901 fwohci_txd(sc, &sc->atrs); 1902 fwohci_arcv(sc, &sc->arrs, -1); 1903 fwohci_arcv(sc, &sc->arrq, -1); 1904 fw_drain_txq(fc); 1905 #endif 1906 fw_sidrcv(fc, buf, plen); 1907 free(buf, M_FW); 1908 } 1909 sidout: 1910 if((stat & OHCI_INT_DMA_ATRQ )){ 1911 #ifndef ACK_ALL 1912 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_ATRQ); 1913 #endif 1914 fwohci_txd(sc, &(sc->atrq)); 1915 } 1916 if((stat & OHCI_INT_DMA_ATRS )){ 1917 #ifndef ACK_ALL 1918 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_ATRS); 1919 #endif 1920 fwohci_txd(sc, &(sc->atrs)); 1921 } 1922 if((stat & OHCI_INT_PW_ERR )){ 1923 #ifndef ACK_ALL 1924 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_PW_ERR); 1925 #endif 1926 device_printf(fc->dev, "posted write error\n"); 1927 } 1928 if((stat & OHCI_INT_ERR )){ 1929 #ifndef ACK_ALL 1930 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_ERR); 1931 #endif 1932 device_printf(fc->dev, "unrecoverable error\n"); 1933 } 1934 if((stat & OHCI_INT_PHY_INT)) { 1935 #ifndef ACK_ALL 1936 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_PHY_INT); 1937 #endif 1938 device_printf(fc->dev, "phy int\n"); 1939 } 1940 1941 return; 1942 } 1943 1944 #if FWOHCI_TASKQUEUE 1945 static void 1946 fwohci_complete(void *arg, int pending) 1947 { 1948 struct fwohci_softc *sc = (struct fwohci_softc *)arg; 1949 u_int32_t stat; 1950 1951 again: 1952 stat = atomic_readandclear_int(&sc->intstat); 1953 if (stat) 1954 fwohci_intr_body(sc, stat, -1); 1955 else 1956 return; 1957 goto again; 1958 } 1959 #endif 1960 1961 static u_int32_t 1962 fwochi_check_stat(struct fwohci_softc *sc) 1963 { 1964 u_int32_t stat, irstat, itstat; 1965 1966 stat = OREAD(sc, FWOHCI_INTSTAT); 1967 if (stat == 0xffffffff) { 1968 device_printf(sc->fc.dev, 1969 "device physically ejected?\n"); 1970 return(stat); 1971 } 1972 #ifdef ACK_ALL 1973 if (stat) 1974 OWRITE(sc, FWOHCI_INTSTATCLR, stat); 1975 #endif 1976 if (stat & OHCI_INT_DMA_IR) { 1977 irstat = OREAD(sc, OHCI_IR_STAT); 1978 OWRITE(sc, OHCI_IR_STATCLR, irstat); 1979 atomic_set_int(&sc->irstat, irstat); 1980 } 1981 if (stat & OHCI_INT_DMA_IT) { 1982 itstat = OREAD(sc, OHCI_IT_STAT); 1983 OWRITE(sc, OHCI_IT_STATCLR, itstat); 1984 atomic_set_int(&sc->itstat, itstat); 1985 } 1986 return(stat); 1987 } 1988 1989 void 1990 fwohci_intr(void *arg) 1991 { 1992 struct fwohci_softc *sc = (struct fwohci_softc *)arg; 1993 u_int32_t stat; 1994 #if !FWOHCI_TASKQUEUE 1995 u_int32_t bus_reset = 0; 1996 #endif 1997 1998 if (!(sc->intmask & OHCI_INT_EN)) { 1999 /* polling mode */ 2000 return; 2001 } 2002 2003 #if !FWOHCI_TASKQUEUE 2004 again: 2005 #endif 2006 stat = fwochi_check_stat(sc); 2007 if (stat == 0 || stat == 0xffffffff) 2008 return; 2009 #if FWOHCI_TASKQUEUE 2010 atomic_set_int(&sc->intstat, stat); 2011 /* XXX mask bus reset intr. during bus reset phase */ 2012 if (stat) 2013 taskqueue_enqueue(taskqueue_swi_giant, &sc->fwohci_task_complete); 2014 #else 2015 /* We cannot clear bus reset event during bus reset phase */ 2016 if ((stat & ~bus_reset) == 0) 2017 return; 2018 bus_reset = stat & OHCI_INT_PHY_BUS_R; 2019 fwohci_intr_body(sc, stat, -1); 2020 goto again; 2021 #endif 2022 } 2023 2024 void 2025 fwohci_poll(struct firewire_comm *fc, int quick, int count) 2026 { 2027 int s; 2028 u_int32_t stat; 2029 struct fwohci_softc *sc; 2030 2031 2032 sc = (struct fwohci_softc *)fc; 2033 stat = OHCI_INT_DMA_IR | OHCI_INT_DMA_IT | 2034 OHCI_INT_DMA_PRRS | OHCI_INT_DMA_PRRQ | 2035 OHCI_INT_DMA_ATRQ | OHCI_INT_DMA_ATRS; 2036 #if 0 2037 if (!quick) { 2038 #else 2039 if (1) { 2040 #endif 2041 stat = fwochi_check_stat(sc); 2042 if (stat == 0 || stat == 0xffffffff) 2043 return; 2044 } 2045 s = splfw(); 2046 fwohci_intr_body(sc, stat, count); 2047 splx(s); 2048 } 2049 2050 static void 2051 fwohci_set_intr(struct firewire_comm *fc, int enable) 2052 { 2053 struct fwohci_softc *sc; 2054 2055 sc = (struct fwohci_softc *)fc; 2056 if (bootverbose) 2057 device_printf(sc->fc.dev, "fwohci_set_intr: %d\n", enable); 2058 if (enable) { 2059 sc->intmask |= OHCI_INT_EN; 2060 OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_EN); 2061 } else { 2062 sc->intmask &= ~OHCI_INT_EN; 2063 OWRITE(sc, FWOHCI_INTMASKCLR, OHCI_INT_EN); 2064 } 2065 } 2066 2067 static void 2068 fwohci_tbuf_update(struct fwohci_softc *sc, int dmach) 2069 { 2070 struct firewire_comm *fc = &sc->fc; 2071 volatile struct fwohcidb *db; 2072 struct fw_bulkxfer *chunk; 2073 struct fw_xferq *it; 2074 u_int32_t stat, count; 2075 int s, w=0, ldesc; 2076 2077 it = fc->it[dmach]; 2078 ldesc = sc->it[dmach].ndesc - 1; 2079 s = splfw(); /* unnecessary ? */ 2080 fwdma_sync_multiseg_all(sc->it[dmach].am, BUS_DMASYNC_POSTREAD); 2081 while ((chunk = STAILQ_FIRST(&it->stdma)) != NULL) { 2082 db = ((struct fwohcidb_tr *)(chunk->end))->db; 2083 stat = FWOHCI_DMA_READ(db[ldesc].db.desc.res) 2084 >> OHCI_STATUS_SHIFT; 2085 db = ((struct fwohcidb_tr *)(chunk->start))->db; 2086 count = FWOHCI_DMA_READ(db[ldesc].db.desc.res) 2087 & OHCI_COUNT_MASK; 2088 if (stat == 0) 2089 break; 2090 STAILQ_REMOVE_HEAD(&it->stdma, link); 2091 switch (stat & FWOHCIEV_MASK){ 2092 case FWOHCIEV_ACKCOMPL: 2093 #if 0 2094 device_printf(fc->dev, "0x%08x\n", count); 2095 #endif 2096 break; 2097 default: 2098 device_printf(fc->dev, 2099 "Isochronous transmit err %02x(%s)\n", 2100 stat, fwohcicode[stat & 0x1f]); 2101 } 2102 STAILQ_INSERT_TAIL(&it->stfree, chunk, link); 2103 w++; 2104 } 2105 splx(s); 2106 if (w) 2107 wakeup(it); 2108 } 2109 2110 static void 2111 fwohci_rbuf_update(struct fwohci_softc *sc, int dmach) 2112 { 2113 struct firewire_comm *fc = &sc->fc; 2114 volatile struct fwohcidb_tr *db_tr; 2115 struct fw_bulkxfer *chunk; 2116 struct fw_xferq *ir; 2117 u_int32_t stat; 2118 int s, w=0, ldesc; 2119 2120 ir = fc->ir[dmach]; 2121 ldesc = sc->ir[dmach].ndesc - 1; 2122 #if 0 2123 dump_db(sc, dmach); 2124 #endif 2125 s = splfw(); 2126 fwdma_sync_multiseg_all(sc->ir[dmach].am, BUS_DMASYNC_POSTREAD); 2127 while ((chunk = STAILQ_FIRST(&ir->stdma)) != NULL) { 2128 db_tr = (struct fwohcidb_tr *)chunk->end; 2129 stat = FWOHCI_DMA_READ(db_tr->db[ldesc].db.desc.res) 2130 >> OHCI_STATUS_SHIFT; 2131 if (stat == 0) 2132 break; 2133 2134 if (chunk->mbuf != NULL) { 2135 bus_dmamap_sync(sc->ir[dmach].dmat, db_tr->dma_map, 2136 BUS_DMASYNC_POSTREAD); 2137 bus_dmamap_unload(sc->ir[dmach].dmat, db_tr->dma_map); 2138 } else if (ir->buf != NULL) { 2139 fwdma_sync_multiseg(ir->buf, chunk->poffset, 2140 ir->bnpacket, BUS_DMASYNC_POSTREAD); 2141 } else { 2142 /* XXX */ 2143 printf("fwohci_rbuf_update: this shouldn't happend\n"); 2144 } 2145 2146 STAILQ_REMOVE_HEAD(&ir->stdma, link); 2147 STAILQ_INSERT_TAIL(&ir->stvalid, chunk, link); 2148 switch (stat & FWOHCIEV_MASK) { 2149 case FWOHCIEV_ACKCOMPL: 2150 chunk->resp = 0; 2151 break; 2152 default: 2153 chunk->resp = EINVAL; 2154 device_printf(fc->dev, 2155 "Isochronous receive err %02x(%s)\n", 2156 stat, fwohcicode[stat & 0x1f]); 2157 } 2158 w++; 2159 } 2160 splx(s); 2161 if (w) { 2162 if (ir->flag & FWXFERQ_HANDLER) 2163 ir->hand(ir); 2164 else 2165 wakeup(ir); 2166 } 2167 } 2168 2169 void 2170 dump_dma(struct fwohci_softc *sc, u_int32_t ch) 2171 { 2172 u_int32_t off, cntl, stat, cmd, match; 2173 2174 if(ch == 0){ 2175 off = OHCI_ATQOFF; 2176 }else if(ch == 1){ 2177 off = OHCI_ATSOFF; 2178 }else if(ch == 2){ 2179 off = OHCI_ARQOFF; 2180 }else if(ch == 3){ 2181 off = OHCI_ARSOFF; 2182 }else if(ch < IRX_CH){ 2183 off = OHCI_ITCTL(ch - ITX_CH); 2184 }else{ 2185 off = OHCI_IRCTL(ch - IRX_CH); 2186 } 2187 cntl = stat = OREAD(sc, off); 2188 cmd = OREAD(sc, off + 0xc); 2189 match = OREAD(sc, off + 0x10); 2190 2191 device_printf(sc->fc.dev, "ch %1x cntl:0x%08x cmd:0x%08x match:0x%08x\n", 2192 ch, 2193 cntl, 2194 cmd, 2195 match); 2196 stat &= 0xffff ; 2197 if (stat) { 2198 device_printf(sc->fc.dev, "dma %d ch:%s%s%s%s%s%s %s(%x)\n", 2199 ch, 2200 stat & OHCI_CNTL_DMA_RUN ? "RUN," : "", 2201 stat & OHCI_CNTL_DMA_WAKE ? "WAKE," : "", 2202 stat & OHCI_CNTL_DMA_DEAD ? "DEAD," : "", 2203 stat & OHCI_CNTL_DMA_ACTIVE ? "ACTIVE," : "", 2204 stat & OHCI_CNTL_DMA_BT ? "BRANCH," : "", 2205 stat & OHCI_CNTL_DMA_BAD ? "BADDMA," : "", 2206 fwohcicode[stat & 0x1f], 2207 stat & 0x1f 2208 ); 2209 }else{ 2210 device_printf(sc->fc.dev, "dma %d ch: Nostat\n", ch); 2211 } 2212 } 2213 2214 void 2215 dump_db(struct fwohci_softc *sc, u_int32_t ch) 2216 { 2217 struct fwohci_dbch *dbch; 2218 struct fwohcidb_tr *cp = NULL, *pp, *np = NULL; 2219 volatile struct fwohcidb *curr = NULL, *prev, *next = NULL; 2220 int idb, jdb; 2221 u_int32_t cmd, off; 2222 if(ch == 0){ 2223 off = OHCI_ATQOFF; 2224 dbch = &sc->atrq; 2225 }else if(ch == 1){ 2226 off = OHCI_ATSOFF; 2227 dbch = &sc->atrs; 2228 }else if(ch == 2){ 2229 off = OHCI_ARQOFF; 2230 dbch = &sc->arrq; 2231 }else if(ch == 3){ 2232 off = OHCI_ARSOFF; 2233 dbch = &sc->arrs; 2234 }else if(ch < IRX_CH){ 2235 off = OHCI_ITCTL(ch - ITX_CH); 2236 dbch = &sc->it[ch - ITX_CH]; 2237 }else { 2238 off = OHCI_IRCTL(ch - IRX_CH); 2239 dbch = &sc->ir[ch - IRX_CH]; 2240 } 2241 cmd = OREAD(sc, off + 0xc); 2242 2243 if( dbch->ndb == 0 ){ 2244 device_printf(sc->fc.dev, "No DB is attached ch=%d\n", ch); 2245 return; 2246 } 2247 pp = dbch->top; 2248 prev = pp->db; 2249 for(idb = 0 ; idb < dbch->ndb ; idb ++ ){ 2250 if(pp == NULL){ 2251 curr = NULL; 2252 goto outdb; 2253 } 2254 cp = STAILQ_NEXT(pp, link); 2255 if(cp == NULL){ 2256 curr = NULL; 2257 goto outdb; 2258 } 2259 np = STAILQ_NEXT(cp, link); 2260 for(jdb = 0 ; jdb < dbch->ndesc ; jdb ++ ){ 2261 if ((cmd & 0xfffffff0) == cp->bus_addr) { 2262 curr = cp->db; 2263 if(np != NULL){ 2264 next = np->db; 2265 }else{ 2266 next = NULL; 2267 } 2268 goto outdb; 2269 } 2270 } 2271 pp = STAILQ_NEXT(pp, link); 2272 prev = pp->db; 2273 } 2274 outdb: 2275 if( curr != NULL){ 2276 #if 0 2277 printf("Prev DB %d\n", ch); 2278 print_db(pp, prev, ch, dbch->ndesc); 2279 #endif 2280 printf("Current DB %d\n", ch); 2281 print_db(cp, curr, ch, dbch->ndesc); 2282 #if 0 2283 printf("Next DB %d\n", ch); 2284 print_db(np, next, ch, dbch->ndesc); 2285 #endif 2286 }else{ 2287 printf("dbdump err ch = %d cmd = 0x%08x\n", ch, cmd); 2288 } 2289 return; 2290 } 2291 2292 void 2293 print_db(struct fwohcidb_tr *db_tr, volatile struct fwohcidb *db, 2294 u_int32_t ch, u_int32_t max) 2295 { 2296 fwohcireg_t stat; 2297 int i, key; 2298 u_int32_t cmd, res; 2299 2300 if(db == NULL){ 2301 printf("No Descriptor is found\n"); 2302 return; 2303 } 2304 2305 printf("ch = %d\n%8s %s %s %s %s %4s %8s %8s %4s:%4s\n", 2306 ch, 2307 "Current", 2308 "OP ", 2309 "KEY", 2310 "INT", 2311 "BR ", 2312 "len", 2313 "Addr", 2314 "Depend", 2315 "Stat", 2316 "Cnt"); 2317 for( i = 0 ; i <= max ; i ++){ 2318 cmd = FWOHCI_DMA_READ(db[i].db.desc.cmd); 2319 res = FWOHCI_DMA_READ(db[i].db.desc.res); 2320 key = cmd & OHCI_KEY_MASK; 2321 stat = res >> OHCI_STATUS_SHIFT; 2322 #if __FreeBSD_version >= 500000 2323 printf("%08jx %s %s %s %s %5d %08x %08x %04x:%04x", 2324 (uintmax_t)db_tr->bus_addr, 2325 #else 2326 printf("%08x %s %s %s %s %5d %08x %08x %04x:%04x", 2327 db_tr->bus_addr, 2328 #endif 2329 dbcode[(cmd >> 28) & 0xf], 2330 dbkey[(cmd >> 24) & 0x7], 2331 dbcond[(cmd >> 20) & 0x3], 2332 dbcond[(cmd >> 18) & 0x3], 2333 cmd & OHCI_COUNT_MASK, 2334 FWOHCI_DMA_READ(db[i].db.desc.addr), 2335 FWOHCI_DMA_READ(db[i].db.desc.depend), 2336 stat, 2337 res & OHCI_COUNT_MASK); 2338 if(stat & 0xff00){ 2339 printf(" %s%s%s%s%s%s %s(%x)\n", 2340 stat & OHCI_CNTL_DMA_RUN ? "RUN," : "", 2341 stat & OHCI_CNTL_DMA_WAKE ? "WAKE," : "", 2342 stat & OHCI_CNTL_DMA_DEAD ? "DEAD," : "", 2343 stat & OHCI_CNTL_DMA_ACTIVE ? "ACTIVE," : "", 2344 stat & OHCI_CNTL_DMA_BT ? "BRANCH," : "", 2345 stat & OHCI_CNTL_DMA_BAD ? "BADDMA," : "", 2346 fwohcicode[stat & 0x1f], 2347 stat & 0x1f 2348 ); 2349 }else{ 2350 printf(" Nostat\n"); 2351 } 2352 if(key == OHCI_KEY_ST2 ){ 2353 printf("0x%08x 0x%08x 0x%08x 0x%08x\n", 2354 FWOHCI_DMA_READ(db[i+1].db.immed[0]), 2355 FWOHCI_DMA_READ(db[i+1].db.immed[1]), 2356 FWOHCI_DMA_READ(db[i+1].db.immed[2]), 2357 FWOHCI_DMA_READ(db[i+1].db.immed[3])); 2358 } 2359 if(key == OHCI_KEY_DEVICE){ 2360 return; 2361 } 2362 if((cmd & OHCI_BRANCH_MASK) 2363 == OHCI_BRANCH_ALWAYS){ 2364 return; 2365 } 2366 if((cmd & OHCI_CMD_MASK) 2367 == OHCI_OUTPUT_LAST){ 2368 return; 2369 } 2370 if((cmd & OHCI_CMD_MASK) 2371 == OHCI_INPUT_LAST){ 2372 return; 2373 } 2374 if(key == OHCI_KEY_ST2 ){ 2375 i++; 2376 } 2377 } 2378 return; 2379 } 2380 2381 void 2382 fwohci_ibr(struct firewire_comm *fc) 2383 { 2384 struct fwohci_softc *sc; 2385 u_int32_t fun; 2386 2387 device_printf(fc->dev, "Initiate bus reset\n"); 2388 sc = (struct fwohci_softc *)fc; 2389 2390 /* 2391 * Set root hold-off bit so that non cyclemaster capable node 2392 * shouldn't became the root node. 2393 */ 2394 #if 1 2395 fun = fwphy_rddata(sc, FW_PHY_IBR_REG); 2396 fun |= FW_PHY_IBR | FW_PHY_RHB; 2397 fun = fwphy_wrdata(sc, FW_PHY_IBR_REG, fun); 2398 #else /* Short bus reset */ 2399 fun = fwphy_rddata(sc, FW_PHY_ISBR_REG); 2400 fun |= FW_PHY_ISBR | FW_PHY_RHB; 2401 fun = fwphy_wrdata(sc, FW_PHY_ISBR_REG, fun); 2402 #endif 2403 } 2404 2405 void 2406 fwohci_txbufdb(struct fwohci_softc *sc, int dmach, struct fw_bulkxfer *bulkxfer) 2407 { 2408 struct fwohcidb_tr *db_tr, *fdb_tr; 2409 struct fwohci_dbch *dbch; 2410 volatile struct fwohcidb *db; 2411 struct fw_pkt *fp; 2412 volatile struct fwohci_txpkthdr *ohcifp; 2413 unsigned short chtag; 2414 int idb; 2415 2416 dbch = &sc->it[dmach]; 2417 chtag = sc->it[dmach].xferq.flag & 0xff; 2418 2419 db_tr = (struct fwohcidb_tr *)(bulkxfer->start); 2420 fdb_tr = (struct fwohcidb_tr *)(bulkxfer->end); 2421 /* 2422 device_printf(sc->fc.dev, "DB %08x %08x %08x\n", bulkxfer, db_tr->bus_addr, fdb_tr->bus_addr); 2423 */ 2424 for (idb = 0; idb < dbch->xferq.bnpacket; idb ++) { 2425 db = db_tr->db; 2426 fp = (struct fw_pkt *)db_tr->buf; 2427 ohcifp = (volatile struct fwohci_txpkthdr *) db[1].db.immed; 2428 ohcifp->mode.ld[0] = fp->mode.ld[0]; 2429 ohcifp->mode.stream.len = fp->mode.stream.len; 2430 ohcifp->mode.stream.chtag = chtag; 2431 ohcifp->mode.stream.tcode = 0xa; 2432 ohcifp->mode.stream.spd = 0; 2433 #if BYTE_ORDER == BIG_ENDIAN 2434 FWOHCI_DMA_WRITE(db[1].db.immed[0], db[1].db.immed[0]); 2435 FWOHCI_DMA_WRITE(db[1].db.immed[1], db[1].db.immed[1]); 2436 #endif 2437 2438 FWOHCI_DMA_CLEAR(db[2].db.desc.cmd, OHCI_COUNT_MASK); 2439 FWOHCI_DMA_SET(db[2].db.desc.cmd, fp->mode.stream.len); 2440 FWOHCI_DMA_WRITE(db[2].db.desc.res, 0); 2441 #if 0 /* if bulkxfer->npackets changes */ 2442 db[2].db.desc.cmd = OHCI_OUTPUT_LAST 2443 | OHCI_UPDATE 2444 | OHCI_BRANCH_ALWAYS; 2445 db[0].db.desc.depend = 2446 = db[dbch->ndesc - 1].db.desc.depend 2447 = STAILQ_NEXT(db_tr, link)->bus_addr | dbch->ndesc; 2448 #else 2449 FWOHCI_DMA_SET(db[0].db.desc.depend, dbch->ndesc); 2450 FWOHCI_DMA_SET(db[dbch->ndesc - 1].db.desc.depend, dbch->ndesc); 2451 #endif 2452 bulkxfer->end = (caddr_t)db_tr; 2453 db_tr = STAILQ_NEXT(db_tr, link); 2454 } 2455 db = ((struct fwohcidb_tr *)bulkxfer->end)->db; 2456 FWOHCI_DMA_CLEAR(db[0].db.desc.depend, 0xf); 2457 FWOHCI_DMA_CLEAR(db[dbch->ndesc - 1].db.desc.depend, 0xf); 2458 #if 0 /* if bulkxfer->npackets changes */ 2459 db[dbch->ndesc - 1].db.desc.control |= OHCI_INTERRUPT_ALWAYS; 2460 /* OHCI 1.1 and above */ 2461 db[0].db.desc.control |= OHCI_INTERRUPT_ALWAYS; 2462 #endif 2463 /* 2464 db_tr = (struct fwohcidb_tr *)bulkxfer->start; 2465 fdb_tr = (struct fwohcidb_tr *)bulkxfer->end; 2466 device_printf(sc->fc.dev, "DB %08x %3d %08x %08x\n", bulkxfer, bulkxfer->npacket, db_tr->bus_addr, fdb_tr->bus_addr); 2467 */ 2468 return; 2469 } 2470 2471 static int 2472 fwohci_add_tx_buf(struct fwohci_dbch *dbch, struct fwohcidb_tr *db_tr, 2473 int poffset) 2474 { 2475 volatile struct fwohcidb *db = db_tr->db; 2476 struct fw_xferq *it; 2477 int err = 0; 2478 2479 it = &dbch->xferq; 2480 if(it->buf == 0){ 2481 err = EINVAL; 2482 return err; 2483 } 2484 db_tr->buf = fwdma_v_addr(it->buf, poffset); 2485 db_tr->dbcnt = 3; 2486 2487 FWOHCI_DMA_WRITE(db[0].db.desc.cmd, 2488 OHCI_OUTPUT_MORE | OHCI_KEY_ST2 | 8); 2489 FWOHCI_DMA_WRITE(db[2].db.desc.addr, 2490 fwdma_bus_addr(it->buf, poffset) + sizeof(u_int32_t)); 2491 2492 FWOHCI_DMA_WRITE(db[2].db.desc.cmd, 2493 OHCI_OUTPUT_LAST | OHCI_UPDATE | OHCI_BRANCH_ALWAYS); 2494 #if 1 2495 FWOHCI_DMA_WRITE(db[0].db.desc.res, 0); 2496 FWOHCI_DMA_WRITE(db[2].db.desc.res, 0); 2497 #endif 2498 return 0; 2499 } 2500 2501 int 2502 fwohci_add_rx_buf(struct fwohci_dbch *dbch, struct fwohcidb_tr *db_tr, 2503 int poffset, struct fwdma_alloc *dummy_dma) 2504 { 2505 volatile struct fwohcidb *db = db_tr->db; 2506 struct fw_xferq *ir; 2507 int i, ldesc; 2508 bus_addr_t dbuf[2]; 2509 int dsiz[2]; 2510 2511 ir = &dbch->xferq; 2512 if (ir->buf == NULL && (dbch->xferq.flag & FWXFERQ_EXTBUF) == 0) { 2513 db_tr->buf = fwdma_malloc_size(dbch->dmat, &db_tr->dma_map, 2514 ir->psize, &dbuf[0], BUS_DMA_NOWAIT); 2515 if (db_tr->buf == NULL) 2516 return(ENOMEM); 2517 db_tr->dbcnt = 1; 2518 dsiz[0] = ir->psize; 2519 bus_dmamap_sync(dbch->dmat, db_tr->dma_map, 2520 BUS_DMASYNC_PREREAD); 2521 } else { 2522 db_tr->dbcnt = 0; 2523 if (dummy_dma != NULL) { 2524 dsiz[db_tr->dbcnt] = sizeof(u_int32_t); 2525 dbuf[db_tr->dbcnt++] = dummy_dma->bus_addr; 2526 } 2527 dsiz[db_tr->dbcnt] = ir->psize; 2528 if (ir->buf != NULL) { 2529 db_tr->buf = fwdma_v_addr(ir->buf, poffset); 2530 dbuf[db_tr->dbcnt] = fwdma_bus_addr( ir->buf, poffset); 2531 } 2532 db_tr->dbcnt++; 2533 } 2534 for(i = 0 ; i < db_tr->dbcnt ; i++){ 2535 FWOHCI_DMA_WRITE(db[i].db.desc.addr, dbuf[i]); 2536 FWOHCI_DMA_WRITE(db[i].db.desc.cmd, OHCI_INPUT_MORE | dsiz[i]); 2537 if (ir->flag & FWXFERQ_STREAM) { 2538 FWOHCI_DMA_SET(db[i].db.desc.cmd, OHCI_UPDATE); 2539 } 2540 FWOHCI_DMA_WRITE(db[i].db.desc.res, dsiz[i]); 2541 } 2542 ldesc = db_tr->dbcnt - 1; 2543 if (ir->flag & FWXFERQ_STREAM) { 2544 FWOHCI_DMA_SET(db[ldesc].db.desc.cmd, OHCI_INPUT_LAST); 2545 } 2546 FWOHCI_DMA_SET(db[ldesc].db.desc.cmd, OHCI_BRANCH_ALWAYS); 2547 return 0; 2548 } 2549 2550 2551 static int 2552 fwohci_arcv_swap(struct fw_pkt *fp, int len) 2553 { 2554 struct fw_pkt *fp0; 2555 u_int32_t ld0; 2556 int slen; 2557 #if BYTE_ORDER == BIG_ENDIAN 2558 int i; 2559 #endif 2560 2561 ld0 = FWOHCI_DMA_READ(fp->mode.ld[0]); 2562 #if 0 2563 printf("ld0: x%08x\n", ld0); 2564 #endif 2565 fp0 = (struct fw_pkt *)&ld0; 2566 switch (fp0->mode.common.tcode) { 2567 case FWTCODE_RREQQ: 2568 case FWTCODE_WRES: 2569 case FWTCODE_WREQQ: 2570 case FWTCODE_RRESQ: 2571 case FWOHCITCODE_PHY: 2572 slen = 12; 2573 break; 2574 case FWTCODE_RREQB: 2575 case FWTCODE_WREQB: 2576 case FWTCODE_LREQ: 2577 case FWTCODE_RRESB: 2578 case FWTCODE_LRES: 2579 slen = 16; 2580 break; 2581 default: 2582 printf("Unknown tcode %d\n", fp0->mode.common.tcode); 2583 return(0); 2584 } 2585 if (slen > len) { 2586 if (firewire_debug) 2587 printf("splitted header\n"); 2588 return(-slen); 2589 } 2590 #if BYTE_ORDER == BIG_ENDIAN 2591 for(i = 0; i < slen/4; i ++) 2592 fp->mode.ld[i] = FWOHCI_DMA_READ(fp->mode.ld[i]); 2593 #endif 2594 return(slen); 2595 } 2596 2597 #define PLEN(x) roundup2(x, sizeof(u_int32_t)) 2598 static int 2599 fwohci_get_plen(struct fwohci_softc *sc, struct fwohci_dbch *dbch, struct fw_pkt *fp) 2600 { 2601 int r; 2602 2603 switch(fp->mode.common.tcode){ 2604 case FWTCODE_RREQQ: 2605 r = sizeof(fp->mode.rreqq) + sizeof(u_int32_t); 2606 break; 2607 case FWTCODE_WRES: 2608 r = sizeof(fp->mode.wres) + sizeof(u_int32_t); 2609 break; 2610 case FWTCODE_WREQQ: 2611 r = sizeof(fp->mode.wreqq) + sizeof(u_int32_t); 2612 break; 2613 case FWTCODE_RREQB: 2614 r = sizeof(fp->mode.rreqb) + sizeof(u_int32_t); 2615 break; 2616 case FWTCODE_RRESQ: 2617 r = sizeof(fp->mode.rresq) + sizeof(u_int32_t); 2618 break; 2619 case FWTCODE_WREQB: 2620 r = sizeof(struct fw_asyhdr) + PLEN(fp->mode.wreqb.len) 2621 + sizeof(u_int32_t); 2622 break; 2623 case FWTCODE_LREQ: 2624 r = sizeof(struct fw_asyhdr) + PLEN(fp->mode.lreq.len) 2625 + sizeof(u_int32_t); 2626 break; 2627 case FWTCODE_RRESB: 2628 r = sizeof(struct fw_asyhdr) + PLEN(fp->mode.rresb.len) 2629 + sizeof(u_int32_t); 2630 break; 2631 case FWTCODE_LRES: 2632 r = sizeof(struct fw_asyhdr) + PLEN(fp->mode.lres.len) 2633 + sizeof(u_int32_t); 2634 break; 2635 case FWOHCITCODE_PHY: 2636 r = 16; 2637 break; 2638 default: 2639 device_printf(sc->fc.dev, "Unknown tcode %d\n", 2640 fp->mode.common.tcode); 2641 r = 0; 2642 } 2643 if (r > dbch->xferq.psize) { 2644 device_printf(sc->fc.dev, "Invalid packet length %d\n", r); 2645 /* panic ? */ 2646 } 2647 return r; 2648 } 2649 2650 static void 2651 fwohci_arcv_free_buf(struct fwohci_dbch *dbch, struct fwohcidb_tr *db_tr) 2652 { 2653 volatile struct fwohcidb *db = &db_tr->db[0]; 2654 2655 FWOHCI_DMA_CLEAR(db->db.desc.depend, 0xf); 2656 FWOHCI_DMA_WRITE(db->db.desc.res, dbch->xferq.psize); 2657 FWOHCI_DMA_SET(dbch->bottom->db[0].db.desc.depend, 1); 2658 fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREWRITE); 2659 dbch->bottom = db_tr; 2660 } 2661 2662 static void 2663 fwohci_arcv(struct fwohci_softc *sc, struct fwohci_dbch *dbch, int count) 2664 { 2665 struct fwohcidb_tr *db_tr; 2666 struct iovec vec[2]; 2667 struct fw_pkt pktbuf; 2668 int nvec; 2669 struct fw_pkt *fp; 2670 u_int8_t *ld; 2671 u_int32_t stat, off, status; 2672 u_int spd; 2673 int len, plen, hlen, pcnt, offset; 2674 int s; 2675 caddr_t buf; 2676 int resCount; 2677 2678 if(&sc->arrq == dbch){ 2679 off = OHCI_ARQOFF; 2680 }else if(&sc->arrs == dbch){ 2681 off = OHCI_ARSOFF; 2682 }else{ 2683 return; 2684 } 2685 2686 s = splfw(); 2687 db_tr = dbch->top; 2688 pcnt = 0; 2689 /* XXX we cannot handle a packet which lies in more than two buf */ 2690 fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_POSTREAD); 2691 fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_POSTWRITE); 2692 status = FWOHCI_DMA_READ(db_tr->db[0].db.desc.res) >> OHCI_STATUS_SHIFT; 2693 resCount = FWOHCI_DMA_READ(db_tr->db[0].db.desc.res) & OHCI_COUNT_MASK; 2694 #if 0 2695 printf("status 0x%04x, resCount 0x%04x\n", status, resCount); 2696 #endif 2697 while (status & OHCI_CNTL_DMA_ACTIVE) { 2698 len = dbch->xferq.psize - resCount; 2699 ld = (u_int8_t *)db_tr->buf; 2700 if (dbch->pdb_tr == NULL) { 2701 len -= dbch->buf_offset; 2702 ld += dbch->buf_offset; 2703 } 2704 if (len > 0) 2705 bus_dmamap_sync(dbch->dmat, db_tr->dma_map, 2706 BUS_DMASYNC_POSTREAD); 2707 while (len > 0 ) { 2708 if (count >= 0 && count-- == 0) 2709 goto out; 2710 if(dbch->pdb_tr != NULL){ 2711 /* we have a fragment in previous buffer */ 2712 int rlen; 2713 2714 offset = dbch->buf_offset; 2715 if (offset < 0) 2716 offset = - offset; 2717 buf = dbch->pdb_tr->buf + offset; 2718 rlen = dbch->xferq.psize - offset; 2719 if (firewire_debug) 2720 printf("rlen=%d, offset=%d\n", 2721 rlen, dbch->buf_offset); 2722 if (dbch->buf_offset < 0) { 2723 /* splitted in header, pull up */ 2724 char *p; 2725 2726 p = (char *)&pktbuf; 2727 bcopy(buf, p, rlen); 2728 p += rlen; 2729 /* this must be too long but harmless */ 2730 rlen = sizeof(pktbuf) - rlen; 2731 if (rlen < 0) 2732 printf("why rlen < 0\n"); 2733 bcopy(db_tr->buf, p, rlen); 2734 ld += rlen; 2735 len -= rlen; 2736 hlen = fwohci_arcv_swap(&pktbuf, sizeof(pktbuf)); 2737 if (hlen < 0) { 2738 printf("hlen < 0 shouldn't happen"); 2739 } 2740 offset = sizeof(pktbuf); 2741 vec[0].iov_base = (char *)&pktbuf; 2742 vec[0].iov_len = offset; 2743 } else { 2744 /* splitted in payload */ 2745 offset = rlen; 2746 vec[0].iov_base = buf; 2747 vec[0].iov_len = rlen; 2748 } 2749 fp=(struct fw_pkt *)vec[0].iov_base; 2750 nvec = 1; 2751 } else { 2752 /* no fragment in previous buffer */ 2753 fp=(struct fw_pkt *)ld; 2754 hlen = fwohci_arcv_swap(fp, len); 2755 if (hlen == 0) 2756 /* XXX need reset */ 2757 goto out; 2758 if (hlen < 0) { 2759 dbch->pdb_tr = db_tr; 2760 dbch->buf_offset = - dbch->buf_offset; 2761 /* sanity check */ 2762 if (resCount != 0) 2763 printf("resCount != 0 !?\n"); 2764 goto out; 2765 } 2766 offset = 0; 2767 nvec = 0; 2768 } 2769 plen = fwohci_get_plen(sc, dbch, fp) - offset; 2770 if (plen < 0) { 2771 /* minimum header size + trailer 2772 = sizeof(fw_pkt) so this shouldn't happens */ 2773 printf("plen is negative! offset=%d\n", offset); 2774 goto out; 2775 } 2776 if (plen > 0) { 2777 len -= plen; 2778 if (len < 0) { 2779 dbch->pdb_tr = db_tr; 2780 if (firewire_debug) 2781 printf("splitted payload\n"); 2782 /* sanity check */ 2783 if (resCount != 0) 2784 printf("resCount != 0 !?\n"); 2785 goto out; 2786 } 2787 vec[nvec].iov_base = ld; 2788 vec[nvec].iov_len = plen; 2789 nvec ++; 2790 ld += plen; 2791 } 2792 dbch->buf_offset = ld - (u_int8_t *)db_tr->buf; 2793 if (nvec == 0) 2794 printf("nvec == 0\n"); 2795 2796 /* DMA result-code will be written at the tail of packet */ 2797 #if BYTE_ORDER == BIG_ENDIAN 2798 stat = FWOHCI_DMA_READ(((struct fwohci_trailer *)(ld - sizeof(struct fwohci_trailer)))->stat) >> 16; 2799 #else 2800 stat = ((struct fwohci_trailer *)(ld - sizeof(struct fwohci_trailer)))->stat; 2801 #endif 2802 #if 0 2803 printf("plen: %d, stat %x\n", plen ,stat); 2804 #endif 2805 spd = (stat >> 5) & 0x3; 2806 stat &= 0x1f; 2807 switch(stat){ 2808 case FWOHCIEV_ACKPEND: 2809 #if 0 2810 printf("fwohci_arcv: ack pending tcode=0x%x..\n", fp->mode.common.tcode); 2811 #endif 2812 /* fall through */ 2813 case FWOHCIEV_ACKCOMPL: 2814 if ((vec[nvec-1].iov_len -= 2815 sizeof(struct fwohci_trailer)) == 0) 2816 nvec--; 2817 fw_rcv(&sc->fc, vec, nvec, 0, spd); 2818 break; 2819 case FWOHCIEV_BUSRST: 2820 if (sc->fc.status != FWBUSRESET) 2821 printf("got BUSRST packet!?\n"); 2822 break; 2823 default: 2824 device_printf(sc->fc.dev, "Async DMA Receive error err = %02x %s\n", stat, fwohcicode[stat]); 2825 #if 0 /* XXX */ 2826 goto out; 2827 #endif 2828 break; 2829 } 2830 pcnt ++; 2831 if (dbch->pdb_tr != NULL) { 2832 fwohci_arcv_free_buf(dbch, dbch->pdb_tr); 2833 dbch->pdb_tr = NULL; 2834 } 2835 2836 } 2837 out: 2838 if (resCount == 0) { 2839 /* done on this buffer */ 2840 if (dbch->pdb_tr == NULL) { 2841 fwohci_arcv_free_buf(dbch, db_tr); 2842 dbch->buf_offset = 0; 2843 } else 2844 if (dbch->pdb_tr != db_tr) 2845 printf("pdb_tr != db_tr\n"); 2846 db_tr = STAILQ_NEXT(db_tr, link); 2847 status = FWOHCI_DMA_READ(db_tr->db[0].db.desc.res) 2848 >> OHCI_STATUS_SHIFT; 2849 resCount = FWOHCI_DMA_READ(db_tr->db[0].db.desc.res) 2850 & OHCI_COUNT_MASK; 2851 /* XXX check buffer overrun */ 2852 dbch->top = db_tr; 2853 } else { 2854 dbch->buf_offset = dbch->xferq.psize - resCount; 2855 break; 2856 } 2857 /* XXX make sure DMA is not dead */ 2858 } 2859 #if 0 2860 if (pcnt < 1) 2861 printf("fwohci_arcv: no packets\n"); 2862 #endif 2863 splx(s); 2864 } 2865