1 /* 2 * Copyright (c) 1998-2002 Katsushi Kobayashi and Hidetoshi Shimokawa 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the acknowledgement as bellow: 15 * 16 * This product includes software developed by K. Kobayashi and H. Shimokawa 17 * 18 * 4. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 23 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 24 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 25 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 26 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 27 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 28 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 29 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 30 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 * POSSIBILITY OF SUCH DAMAGE. 32 * 33 * $FreeBSD$ 34 * 35 */ 36 37 #define ATRQ_CH 0 38 #define ATRS_CH 1 39 #define ARRQ_CH 2 40 #define ARRS_CH 3 41 #define ITX_CH 4 42 #define IRX_CH 0x24 43 44 #include <sys/param.h> 45 #include <sys/proc.h> 46 #include <sys/systm.h> 47 #include <sys/types.h> 48 #include <sys/mbuf.h> 49 #include <sys/mman.h> 50 #include <sys/socket.h> 51 #include <sys/socketvar.h> 52 #include <sys/signalvar.h> 53 #include <sys/malloc.h> 54 #include <sys/uio.h> 55 #include <sys/sockio.h> 56 #include <sys/bus.h> 57 #include <sys/kernel.h> 58 #include <sys/conf.h> 59 60 #include <machine/bus.h> 61 #include <machine/resource.h> 62 #include <sys/rman.h> 63 64 #include <machine/cpufunc.h> /* for rdtsc proto for clock.h below */ 65 #include <machine/clock.h> 66 #include <pci/pcivar.h> 67 #include <pci/pcireg.h> 68 #include <vm/vm.h> 69 #include <vm/vm_extern.h> 70 #include <vm/pmap.h> /* for vtophys proto */ 71 72 #include <dev/firewire/firewire.h> 73 #include <dev/firewire/firewirereg.h> 74 #include <dev/firewire/fwohcireg.h> 75 #include <dev/firewire/fwohcivar.h> 76 #include <dev/firewire/firewire_phy.h> 77 78 #include <dev/firewire/iec68113.h> 79 80 #undef OHCI_DEBUG 81 82 static char dbcode[16][0x10]={"OUTM", "OUTL","INPM","INPL", 83 "STOR","LOAD","NOP ","STOP",}; 84 static char dbkey[8][0x10]={"ST0", "ST1","ST2","ST3", 85 "UNDEF","REG","SYS","DEV"}; 86 char fwohcicode[32][0x20]={ 87 "No stat","Undef","long","miss Ack err", 88 "underrun","overrun","desc err", "data read err", 89 "data write err","bus reset","timeout","tcode err", 90 "Undef","Undef","unknown event","flushed", 91 "Undef","ack complete","ack pend","Undef", 92 "ack busy_X","ack busy_A","ack busy_B","Undef", 93 "Undef","Undef","Undef","ack tardy", 94 "Undef","ack data_err","ack type_err",""}; 95 #define MAX_SPEED 2 96 extern char linkspeed[MAX_SPEED+1][0x10]; 97 static char dbcond[4][0x10]={"NEV","C=1", "C=0", "ALL"}; 98 u_int32_t tagbit[4] = { 1 << 28, 1 << 29, 1 << 30, 1 << 31}; 99 100 static struct tcode_info tinfo[] = { 101 /* hdr_len block flag*/ 102 /* 0 WREQQ */ {16, FWTI_REQ | FWTI_TLABEL}, 103 /* 1 WREQB */ {16, FWTI_REQ | FWTI_TLABEL | FWTI_BLOCK_ASY}, 104 /* 2 WRES */ {12, FWTI_RES}, 105 /* 3 XXX */ { 0, 0}, 106 /* 4 RREQQ */ {12, FWTI_REQ | FWTI_TLABEL}, 107 /* 5 RREQB */ {16, FWTI_REQ | FWTI_TLABEL}, 108 /* 6 RRESQ */ {16, FWTI_RES}, 109 /* 7 RRESB */ {16, FWTI_RES | FWTI_BLOCK_ASY}, 110 /* 8 CYCS */ { 0, 0}, 111 /* 9 LREQ */ {16, FWTI_REQ | FWTI_TLABEL | FWTI_BLOCK_ASY}, 112 /* a STREAM */ { 4, FWTI_REQ | FWTI_BLOCK_STR}, 113 /* b LRES */ {16, FWTI_RES | FWTI_BLOCK_ASY}, 114 /* c XXX */ { 0, 0}, 115 /* d XXX */ { 0, 0}, 116 /* e PHY */ {12, FWTI_REQ}, 117 /* f XXX */ { 0, 0} 118 }; 119 120 #define OHCI_WRITE_SIGMASK 0xffff0000 121 #define OHCI_READ_SIGMASK 0xffff0000 122 123 #define OWRITE(sc, r, x) bus_space_write_4((sc)->bst, (sc)->bsh, (r), (x)) 124 #define OREAD(sc, r) bus_space_read_4((sc)->bst, (sc)->bsh, (r)) 125 126 static void fwohci_ibr __P((struct firewire_comm *)); 127 static void fwohci_db_init __P((struct fwohci_dbch *)); 128 static void fwohci_db_free __P((struct fwohci_dbch *)); 129 static void fwohci_arcv __P((struct fwohci_softc *, struct fwohci_dbch *, int)); 130 static void fwohci_ircv __P((struct fwohci_softc *, struct fwohci_dbch *, int)); 131 static void fwohci_txd __P((struct fwohci_softc *, struct fwohci_dbch *)); 132 static void fwohci_start_atq __P((struct firewire_comm *)); 133 static void fwohci_start_ats __P((struct firewire_comm *)); 134 static void fwohci_start __P((struct fwohci_softc *, struct fwohci_dbch *)); 135 static void fwohci_drain_atq __P((struct firewire_comm *, struct fw_xfer *)); 136 static void fwohci_drain_ats __P((struct firewire_comm *, struct fw_xfer *)); 137 static void fwohci_drain __P((struct firewire_comm *, struct fw_xfer *, struct fwohci_dbch *)); 138 static u_int32_t fwphy_wrdata __P(( struct fwohci_softc *, u_int32_t, u_int32_t)); 139 static u_int32_t fwphy_rddata __P(( struct fwohci_softc *, u_int32_t)); 140 static int fwohci_rx_enable __P((struct fwohci_softc *, struct fwohci_dbch *)); 141 static int fwohci_tx_enable __P((struct fwohci_softc *, struct fwohci_dbch *)); 142 static int fwohci_irx_enable __P((struct firewire_comm *, int)); 143 static int fwohci_irxpp_enable __P((struct firewire_comm *, int)); 144 static int fwohci_irxbuf_enable __P((struct firewire_comm *, int)); 145 static int fwohci_irx_disable __P((struct firewire_comm *, int)); 146 static void fwohci_irx_post __P((struct firewire_comm *, u_int32_t *)); 147 static int fwohci_itxbuf_enable __P((struct firewire_comm *, int)); 148 static int fwohci_itx_disable __P((struct firewire_comm *, int)); 149 static void fwohci_timeout __P((void *)); 150 static void fwohci_poll __P((struct firewire_comm *, int, int)); 151 static void fwohci_set_intr __P((struct firewire_comm *, int)); 152 static int fwohci_add_rx_buf __P((struct fwohcidb_tr *, unsigned short, int, void *, void *)); 153 static int fwohci_add_tx_buf __P((struct fwohcidb_tr *, unsigned short, int, void *)); 154 static void dump_db __P((struct fwohci_softc *, u_int32_t)); 155 static void print_db __P((volatile struct fwohcidb *, u_int32_t , u_int32_t)); 156 static void dump_dma __P((struct fwohci_softc *, u_int32_t)); 157 static u_int32_t fwohci_cyctimer __P((struct firewire_comm *)); 158 static void fwohci_rbuf_update __P((struct fwohci_softc *, int)); 159 static void fwohci_tbuf_update __P((struct fwohci_softc *, int)); 160 void fwohci_txbufdb __P((struct fwohci_softc *, int , struct fw_bulkxfer *)); 161 162 /* 163 * memory allocated for DMA programs 164 */ 165 #define DMA_PROG_ALLOC (8 * PAGE_SIZE) 166 167 /* #define NDB 1024 */ 168 #define NDB FWMAXQUEUE 169 #define NDVDB (DVBUF * NDB) 170 171 #define OHCI_VERSION 0x00 172 #define OHCI_CROMHDR 0x18 173 #define OHCI_BUS_OPT 0x20 174 #define OHCI_BUSIRMC (1 << 31) 175 #define OHCI_BUSCMC (1 << 30) 176 #define OHCI_BUSISC (1 << 29) 177 #define OHCI_BUSBMC (1 << 28) 178 #define OHCI_BUSPMC (1 << 27) 179 #define OHCI_BUSFNC OHCI_BUSIRMC | OHCI_BUSCMC | OHCI_BUSISC |\ 180 OHCI_BUSBMC | OHCI_BUSPMC 181 182 #define OHCI_EUID_HI 0x24 183 #define OHCI_EUID_LO 0x28 184 185 #define OHCI_CROMPTR 0x34 186 #define OHCI_HCCCTL 0x50 187 #define OHCI_HCCCTLCLR 0x54 188 #define OHCI_AREQHI 0x100 189 #define OHCI_AREQHICLR 0x104 190 #define OHCI_AREQLO 0x108 191 #define OHCI_AREQLOCLR 0x10c 192 #define OHCI_PREQHI 0x110 193 #define OHCI_PREQHICLR 0x114 194 #define OHCI_PREQLO 0x118 195 #define OHCI_PREQLOCLR 0x11c 196 #define OHCI_PREQUPPER 0x120 197 198 #define OHCI_SID_BUF 0x64 199 #define OHCI_SID_CNT 0x68 200 #define OHCI_SID_CNT_MASK 0xffc 201 202 #define OHCI_IT_STAT 0x90 203 #define OHCI_IT_STATCLR 0x94 204 #define OHCI_IT_MASK 0x98 205 #define OHCI_IT_MASKCLR 0x9c 206 207 #define OHCI_IR_STAT 0xa0 208 #define OHCI_IR_STATCLR 0xa4 209 #define OHCI_IR_MASK 0xa8 210 #define OHCI_IR_MASKCLR 0xac 211 212 #define OHCI_LNKCTL 0xe0 213 #define OHCI_LNKCTLCLR 0xe4 214 215 #define OHCI_PHYACCESS 0xec 216 #define OHCI_CYCLETIMER 0xf0 217 218 #define OHCI_DMACTL(off) (off) 219 #define OHCI_DMACTLCLR(off) (off + 4) 220 #define OHCI_DMACMD(off) (off + 0xc) 221 #define OHCI_DMAMATCH(off) (off + 0x10) 222 223 #define OHCI_ATQOFF 0x180 224 #define OHCI_ATQCTL OHCI_ATQOFF 225 #define OHCI_ATQCTLCLR (OHCI_ATQOFF + 4) 226 #define OHCI_ATQCMD (OHCI_ATQOFF + 0xc) 227 #define OHCI_ATQMATCH (OHCI_ATQOFF + 0x10) 228 229 #define OHCI_ATSOFF 0x1a0 230 #define OHCI_ATSCTL OHCI_ATSOFF 231 #define OHCI_ATSCTLCLR (OHCI_ATSOFF + 4) 232 #define OHCI_ATSCMD (OHCI_ATSOFF + 0xc) 233 #define OHCI_ATSMATCH (OHCI_ATSOFF + 0x10) 234 235 #define OHCI_ARQOFF 0x1c0 236 #define OHCI_ARQCTL OHCI_ARQOFF 237 #define OHCI_ARQCTLCLR (OHCI_ARQOFF + 4) 238 #define OHCI_ARQCMD (OHCI_ARQOFF + 0xc) 239 #define OHCI_ARQMATCH (OHCI_ARQOFF + 0x10) 240 241 #define OHCI_ARSOFF 0x1e0 242 #define OHCI_ARSCTL OHCI_ARSOFF 243 #define OHCI_ARSCTLCLR (OHCI_ARSOFF + 4) 244 #define OHCI_ARSCMD (OHCI_ARSOFF + 0xc) 245 #define OHCI_ARSMATCH (OHCI_ARSOFF + 0x10) 246 247 #define OHCI_ITOFF(CH) (0x200 + 0x10 * (CH)) 248 #define OHCI_ITCTL(CH) (OHCI_ITOFF(CH)) 249 #define OHCI_ITCTLCLR(CH) (OHCI_ITOFF(CH) + 4) 250 #define OHCI_ITCMD(CH) (OHCI_ITOFF(CH) + 0xc) 251 252 #define OHCI_IROFF(CH) (0x400 + 0x20 * (CH)) 253 #define OHCI_IRCTL(CH) (OHCI_IROFF(CH)) 254 #define OHCI_IRCTLCLR(CH) (OHCI_IROFF(CH) + 4) 255 #define OHCI_IRCMD(CH) (OHCI_IROFF(CH) + 0xc) 256 #define OHCI_IRMATCH(CH) (OHCI_IROFF(CH) + 0x10) 257 258 d_ioctl_t fwohci_ioctl; 259 260 /* 261 * Communication with PHY device 262 */ 263 static u_int32_t 264 fwphy_wrdata( struct fwohci_softc *sc, u_int32_t addr, u_int32_t data) 265 { 266 u_int32_t fun; 267 268 addr &= 0xf; 269 data &= 0xff; 270 271 fun = (PHYDEV_WRCMD | (addr << PHYDEV_REGADDR) | (data << PHYDEV_WRDATA)); 272 OWRITE(sc, OHCI_PHYACCESS, fun); 273 DELAY(100); 274 275 return(fwphy_rddata( sc, addr)); 276 } 277 278 static u_int32_t 279 fwohci_set_bus_manager(struct firewire_comm *fc, u_int node) 280 { 281 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 282 int i; 283 u_int32_t bm; 284 285 #define OHCI_CSR_DATA 0x0c 286 #define OHCI_CSR_COMP 0x10 287 #define OHCI_CSR_CONT 0x14 288 #define OHCI_BUS_MANAGER_ID 0 289 290 OWRITE(sc, OHCI_CSR_DATA, node); 291 OWRITE(sc, OHCI_CSR_COMP, 0x3f); 292 OWRITE(sc, OHCI_CSR_CONT, OHCI_BUS_MANAGER_ID); 293 for (i = 0; !(OREAD(sc, OHCI_CSR_CONT) & (1<<31)) && (i < 1000); i++) 294 DELAY(10); 295 bm = OREAD(sc, OHCI_CSR_DATA); 296 if((bm & 0x3f) == 0x3f) 297 bm = node; 298 if (bootverbose) 299 device_printf(sc->fc.dev, 300 "fw_set_bus_manager: %d->%d (loop=%d)\n", bm, node, i); 301 302 return(bm); 303 } 304 305 static u_int32_t 306 fwphy_rddata(struct fwohci_softc *sc, u_int addr) 307 { 308 u_int32_t fun, stat; 309 u_int i, retry = 0; 310 311 addr &= 0xf; 312 #define MAX_RETRY 100 313 again: 314 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_REG_FAIL); 315 fun = PHYDEV_RDCMD | (addr << PHYDEV_REGADDR); 316 OWRITE(sc, OHCI_PHYACCESS, fun); 317 for ( i = 0 ; i < MAX_RETRY ; i ++ ){ 318 fun = OREAD(sc, OHCI_PHYACCESS); 319 if ((fun & PHYDEV_RDCMD) == 0 && (fun & PHYDEV_RDDONE) != 0) 320 break; 321 DELAY(100); 322 } 323 if(i >= MAX_RETRY) { 324 if (bootverbose) 325 device_printf(sc->fc.dev, "phy read failed(1).\n"); 326 if (++retry < MAX_RETRY) { 327 DELAY(100); 328 goto again; 329 } 330 } 331 /* Make sure that SCLK is started */ 332 stat = OREAD(sc, FWOHCI_INTSTAT); 333 if ((stat & OHCI_INT_REG_FAIL) != 0 || 334 ((fun >> PHYDEV_REGADDR) & 0xf) != addr) { 335 if (bootverbose) 336 device_printf(sc->fc.dev, "phy read failed(2).\n"); 337 if (++retry < MAX_RETRY) { 338 DELAY(100); 339 goto again; 340 } 341 } 342 if (bootverbose || retry >= MAX_RETRY) 343 device_printf(sc->fc.dev, 344 "fwphy_rddata: loop=%d, retry=%d\n", i, retry); 345 #undef MAX_RETRY 346 return((fun >> PHYDEV_RDDATA )& 0xff); 347 } 348 /* Device specific ioctl. */ 349 int 350 fwohci_ioctl (dev_t dev, u_long cmd, caddr_t data, int flag, fw_proc *td) 351 { 352 struct firewire_softc *sc; 353 struct fwohci_softc *fc; 354 int unit = DEV2UNIT(dev); 355 int err = 0; 356 struct fw_reg_req_t *reg = (struct fw_reg_req_t *) data; 357 u_int32_t *dmach = (u_int32_t *) data; 358 359 sc = devclass_get_softc(firewire_devclass, unit); 360 if(sc == NULL){ 361 return(EINVAL); 362 } 363 fc = (struct fwohci_softc *)sc->fc; 364 365 if (!data) 366 return(EINVAL); 367 368 switch (cmd) { 369 case FWOHCI_WRREG: 370 #define OHCI_MAX_REG 0x800 371 if(reg->addr <= OHCI_MAX_REG){ 372 OWRITE(fc, reg->addr, reg->data); 373 reg->data = OREAD(fc, reg->addr); 374 }else{ 375 err = EINVAL; 376 } 377 break; 378 case FWOHCI_RDREG: 379 if(reg->addr <= OHCI_MAX_REG){ 380 reg->data = OREAD(fc, reg->addr); 381 }else{ 382 err = EINVAL; 383 } 384 break; 385 /* Read DMA descriptors for debug */ 386 case DUMPDMA: 387 if(*dmach <= OHCI_MAX_DMA_CH ){ 388 dump_dma(fc, *dmach); 389 dump_db(fc, *dmach); 390 }else{ 391 err = EINVAL; 392 } 393 break; 394 default: 395 break; 396 } 397 return err; 398 } 399 400 static int 401 fwohci_probe_phy(struct fwohci_softc *sc, device_t dev) 402 { 403 u_int32_t reg, reg2; 404 int e1394a = 1; 405 /* 406 * probe PHY parameters 407 * 0. to prove PHY version, whether compliance of 1394a. 408 * 1. to probe maximum speed supported by the PHY and 409 * number of port supported by core-logic. 410 * It is not actually available port on your PC . 411 */ 412 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_LPS); 413 #if 0 414 /* XXX wait for SCLK. */ 415 DELAY(100000); 416 #endif 417 reg = fwphy_rddata(sc, FW_PHY_SPD_REG); 418 419 if((reg >> 5) != 7 ){ 420 sc->fc.mode &= ~FWPHYASYST; 421 sc->fc.nport = reg & FW_PHY_NP; 422 sc->fc.speed = reg & FW_PHY_SPD >> 6; 423 if (sc->fc.speed > MAX_SPEED) { 424 device_printf(dev, "invalid speed %d (fixed to %d).\n", 425 sc->fc.speed, MAX_SPEED); 426 sc->fc.speed = MAX_SPEED; 427 } 428 device_printf(dev, 429 "Phy 1394 only %s, %d ports.\n", 430 linkspeed[sc->fc.speed], sc->fc.nport); 431 }else{ 432 reg2 = fwphy_rddata(sc, FW_PHY_ESPD_REG); 433 sc->fc.mode |= FWPHYASYST; 434 sc->fc.nport = reg & FW_PHY_NP; 435 sc->fc.speed = (reg2 & FW_PHY_ESPD) >> 5; 436 if (sc->fc.speed > MAX_SPEED) { 437 device_printf(dev, "invalid speed %d (fixed to %d).\n", 438 sc->fc.speed, MAX_SPEED); 439 sc->fc.speed = MAX_SPEED; 440 } 441 device_printf(dev, 442 "Phy 1394a available %s, %d ports.\n", 443 linkspeed[sc->fc.speed], sc->fc.nport); 444 445 /* check programPhyEnable */ 446 reg2 = fwphy_rddata(sc, 5); 447 #if 0 448 if (e1394a && (OREAD(sc, OHCI_HCCCTL) & OHCI_HCC_PRPHY)) { 449 #else /* XXX force to enable 1394a */ 450 if (e1394a) { 451 #endif 452 if (bootverbose) 453 device_printf(dev, 454 "Enable 1394a Enhancements\n"); 455 /* enable EAA EMC */ 456 reg2 |= 0x03; 457 /* set aPhyEnhanceEnable */ 458 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_PHYEN); 459 OWRITE(sc, OHCI_HCCCTLCLR, OHCI_HCC_PRPHY); 460 } else { 461 /* for safe */ 462 reg2 &= ~0x83; 463 } 464 reg2 = fwphy_wrdata(sc, 5, reg2); 465 } 466 467 reg = fwphy_rddata(sc, FW_PHY_SPD_REG); 468 if((reg >> 5) == 7 ){ 469 reg = fwphy_rddata(sc, 4); 470 reg |= 1 << 6; 471 fwphy_wrdata(sc, 4, reg); 472 reg = fwphy_rddata(sc, 4); 473 } 474 return 0; 475 } 476 477 478 void 479 fwohci_reset(struct fwohci_softc *sc, device_t dev) 480 { 481 int i, max_rec, speed; 482 u_int32_t reg, reg2; 483 struct fwohcidb_tr *db_tr; 484 485 /* Disable interrupt */ 486 OWRITE(sc, FWOHCI_INTMASKCLR, ~0); 487 488 /* Now stopping all DMA channel */ 489 OWRITE(sc, OHCI_ARQCTLCLR, OHCI_CNTL_DMA_RUN); 490 OWRITE(sc, OHCI_ARSCTLCLR, OHCI_CNTL_DMA_RUN); 491 OWRITE(sc, OHCI_ATQCTLCLR, OHCI_CNTL_DMA_RUN); 492 OWRITE(sc, OHCI_ATSCTLCLR, OHCI_CNTL_DMA_RUN); 493 494 OWRITE(sc, OHCI_IR_MASKCLR, ~0); 495 for( i = 0 ; i < sc->fc.nisodma ; i ++ ){ 496 OWRITE(sc, OHCI_IRCTLCLR(i), OHCI_CNTL_DMA_RUN); 497 OWRITE(sc, OHCI_ITCTLCLR(i), OHCI_CNTL_DMA_RUN); 498 } 499 500 /* FLUSH FIFO and reset Transmitter/Reciever */ 501 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_RESET); 502 if (bootverbose) 503 device_printf(dev, "resetting OHCI..."); 504 i = 0; 505 while(OREAD(sc, OHCI_HCCCTL) & OHCI_HCC_RESET) { 506 if (i++ > 100) break; 507 DELAY(1000); 508 } 509 if (bootverbose) 510 printf("done (loop=%d)\n", i); 511 512 /* Probe phy */ 513 fwohci_probe_phy(sc, dev); 514 515 /* Probe link */ 516 reg = OREAD(sc, OHCI_BUS_OPT); 517 reg2 = reg | OHCI_BUSFNC; 518 max_rec = (reg & 0x0000f000) >> 12; 519 speed = (reg & 0x00000007); 520 device_printf(dev, "Link %s, max_rec %d bytes.\n", 521 linkspeed[speed], MAXREC(max_rec)); 522 /* XXX fix max_rec */ 523 sc->fc.maxrec = sc->fc.speed + 8; 524 if (max_rec != sc->fc.maxrec) { 525 reg2 = (reg2 & 0xffff0fff) | (sc->fc.maxrec << 12); 526 device_printf(dev, "max_rec %d -> %d\n", 527 MAXREC(max_rec), MAXREC(sc->fc.maxrec)); 528 } 529 if (bootverbose) 530 device_printf(dev, "BUS_OPT 0x%x -> 0x%x\n", reg, reg2); 531 OWRITE(sc, OHCI_BUS_OPT, reg2); 532 533 /* Initialize registers */ 534 OWRITE(sc, OHCI_CROMHDR, sc->fc.config_rom[0]); 535 OWRITE(sc, OHCI_CROMPTR, vtophys(&sc->fc.config_rom[0])); 536 OWRITE(sc, OHCI_HCCCTLCLR, OHCI_HCC_BIGEND); 537 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_POSTWR); 538 OWRITE(sc, OHCI_SID_BUF, vtophys(sc->fc.sid_buf)); 539 OWRITE(sc, OHCI_LNKCTL, OHCI_CNTL_SID); 540 fw_busreset(&sc->fc); 541 542 /* Enable link */ 543 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_LINKEN); 544 545 /* Force to start async RX DMA */ 546 sc->arrq.xferq.flag &= ~FWXFERQ_RUNNING; 547 sc->arrs.xferq.flag &= ~FWXFERQ_RUNNING; 548 fwohci_rx_enable(sc, &sc->arrq); 549 fwohci_rx_enable(sc, &sc->arrs); 550 551 /* Initialize async TX */ 552 OWRITE(sc, OHCI_ATQCTLCLR, OHCI_CNTL_DMA_RUN | OHCI_CNTL_DMA_DEAD); 553 OWRITE(sc, OHCI_ATSCTLCLR, OHCI_CNTL_DMA_RUN | OHCI_CNTL_DMA_DEAD); 554 /* AT Retries */ 555 OWRITE(sc, FWOHCI_RETRY, 556 /* CycleLimit PhyRespRetries ATRespRetries ATReqRetries */ 557 (0xffff << 16 ) | (0x0f << 8) | (0x0f << 4) | 0x0f) ; 558 for( i = 0, db_tr = sc->atrq.top; i < sc->atrq.ndb ; 559 i ++, db_tr = STAILQ_NEXT(db_tr, link)){ 560 db_tr->xfer = NULL; 561 } 562 for( i = 0, db_tr = sc->atrs.top; i < sc->atrs.ndb ; 563 i ++, db_tr = STAILQ_NEXT(db_tr, link)){ 564 db_tr->xfer = NULL; 565 } 566 567 568 /* Enable interrupt */ 569 OWRITE(sc, FWOHCI_INTMASK, 570 OHCI_INT_ERR | OHCI_INT_PHY_SID 571 | OHCI_INT_DMA_ATRQ | OHCI_INT_DMA_ATRS 572 | OHCI_INT_DMA_PRRQ | OHCI_INT_DMA_PRRS 573 | OHCI_INT_PHY_BUS_R | OHCI_INT_PW_ERR); 574 fwohci_set_intr(&sc->fc, 1); 575 576 } 577 578 int 579 fwohci_init(struct fwohci_softc *sc, device_t dev) 580 { 581 int i; 582 u_int32_t reg; 583 u_int8_t ui[8]; 584 585 reg = OREAD(sc, OHCI_VERSION); 586 device_printf(dev, "OHCI version %x.%x (ROM=%d)\n", 587 (reg>>16) & 0xff, reg & 0xff, (reg>>24) & 1); 588 589 /* Available Isochrounous DMA channel probe */ 590 OWRITE(sc, OHCI_IT_MASK, 0xffffffff); 591 OWRITE(sc, OHCI_IR_MASK, 0xffffffff); 592 reg = OREAD(sc, OHCI_IT_MASK) & OREAD(sc, OHCI_IR_MASK); 593 OWRITE(sc, OHCI_IT_MASKCLR, 0xffffffff); 594 OWRITE(sc, OHCI_IR_MASKCLR, 0xffffffff); 595 for (i = 0; i < 0x20; i++) 596 if ((reg & (1 << i)) == 0) 597 break; 598 sc->fc.nisodma = i; 599 device_printf(dev, "No. of Isochronous channel is %d.\n", i); 600 601 sc->fc.arq = &sc->arrq.xferq; 602 sc->fc.ars = &sc->arrs.xferq; 603 sc->fc.atq = &sc->atrq.xferq; 604 sc->fc.ats = &sc->atrs.xferq; 605 606 sc->arrq.xferq.start = NULL; 607 sc->arrs.xferq.start = NULL; 608 sc->atrq.xferq.start = fwohci_start_atq; 609 sc->atrs.xferq.start = fwohci_start_ats; 610 611 sc->arrq.xferq.drain = NULL; 612 sc->arrs.xferq.drain = NULL; 613 sc->atrq.xferq.drain = fwohci_drain_atq; 614 sc->atrs.xferq.drain = fwohci_drain_ats; 615 616 sc->arrq.ndesc = 1; 617 sc->arrs.ndesc = 1; 618 sc->atrq.ndesc = 8; /* equal to maximum of mbuf chains */ 619 sc->atrs.ndesc = 2; 620 621 sc->arrq.ndb = NDB; 622 sc->arrs.ndb = NDB / 2; 623 sc->atrq.ndb = NDB; 624 sc->atrs.ndb = NDB / 2; 625 626 sc->arrq.dummy = NULL; 627 sc->arrs.dummy = NULL; 628 sc->atrq.dummy = NULL; 629 sc->atrs.dummy = NULL; 630 for( i = 0 ; i < sc->fc.nisodma ; i ++ ){ 631 sc->fc.it[i] = &sc->it[i].xferq; 632 sc->fc.ir[i] = &sc->ir[i].xferq; 633 sc->it[i].ndb = 0; 634 sc->ir[i].ndb = 0; 635 } 636 637 sc->fc.tcode = tinfo; 638 639 sc->cromptr = (u_int32_t *) malloc(CROMSIZE * 2, M_FW, M_NOWAIT); 640 641 if(sc->cromptr == NULL){ 642 device_printf(dev, "cromptr alloc failed."); 643 return ENOMEM; 644 } 645 sc->fc.dev = dev; 646 sc->fc.config_rom = &(sc->cromptr[CROMSIZE/4]); 647 648 sc->fc.config_rom[1] = 0x31333934; 649 sc->fc.config_rom[2] = 0xf000a002; 650 sc->fc.config_rom[3] = OREAD(sc, OHCI_EUID_HI); 651 sc->fc.config_rom[4] = OREAD(sc, OHCI_EUID_LO); 652 sc->fc.config_rom[5] = 0; 653 sc->fc.config_rom[0] = (4 << 24) | (5 << 16); 654 655 sc->fc.config_rom[0] |= fw_crc16(&sc->fc.config_rom[1], 5*4); 656 657 658 /* SID recieve buffer must allign 2^11 */ 659 #define OHCI_SIDSIZE (1 << 11) 660 sc->fc.sid_buf = (u_int32_t *) malloc(OHCI_SIDSIZE, M_FW, M_NOWAIT); 661 if (sc->fc.sid_buf == NULL) { 662 device_printf(dev, "sid_buf alloc failed.\n"); 663 return ENOMEM; 664 } 665 if (((vm_offset_t) sc->fc.sid_buf & (OHCI_SIDSIZE - 1)) != 0) { 666 device_printf(dev, "sid_buf(%p) not aligned.\n", 667 sc->fc.sid_buf); 668 return ENOMEM; 669 } 670 671 fwohci_db_init(&sc->arrq); 672 if ((sc->arrq.flags & FWOHCI_DBCH_INIT) == 0) 673 return ENOMEM; 674 675 fwohci_db_init(&sc->arrs); 676 if ((sc->arrs.flags & FWOHCI_DBCH_INIT) == 0) 677 return ENOMEM; 678 679 fwohci_db_init(&sc->atrq); 680 if ((sc->atrq.flags & FWOHCI_DBCH_INIT) == 0) 681 return ENOMEM; 682 683 fwohci_db_init(&sc->atrs); 684 if ((sc->atrs.flags & FWOHCI_DBCH_INIT) == 0) 685 return ENOMEM; 686 687 sc->fc.eui.hi = OREAD(sc, FWOHCIGUID_H); 688 sc->fc.eui.lo = OREAD(sc, FWOHCIGUID_L); 689 for( i = 0 ; i < 8 ; i ++) 690 ui[i] = FW_EUI64_BYTE(&sc->fc.eui,i); 691 device_printf(dev, "EUI64 %02x:%02x:%02x:%02x:%02x:%02x:%02x:%02x\n", 692 ui[0], ui[1], ui[2], ui[3], ui[4], ui[5], ui[6], ui[7]); 693 694 sc->fc.ioctl = fwohci_ioctl; 695 sc->fc.cyctimer = fwohci_cyctimer; 696 sc->fc.set_bmr = fwohci_set_bus_manager; 697 sc->fc.ibr = fwohci_ibr; 698 sc->fc.irx_enable = fwohci_irx_enable; 699 sc->fc.irx_disable = fwohci_irx_disable; 700 701 sc->fc.itx_enable = fwohci_itxbuf_enable; 702 sc->fc.itx_disable = fwohci_itx_disable; 703 sc->fc.irx_post = fwohci_irx_post; 704 sc->fc.itx_post = NULL; 705 sc->fc.timeout = fwohci_timeout; 706 sc->fc.poll = fwohci_poll; 707 sc->fc.set_intr = fwohci_set_intr; 708 709 fw_init(&sc->fc); 710 fwohci_reset(sc, dev); 711 712 return 0; 713 } 714 715 void 716 fwohci_timeout(void *arg) 717 { 718 struct fwohci_softc *sc; 719 720 sc = (struct fwohci_softc *)arg; 721 } 722 723 u_int32_t 724 fwohci_cyctimer(struct firewire_comm *fc) 725 { 726 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 727 return(OREAD(sc, OHCI_CYCLETIMER)); 728 } 729 730 int 731 fwohci_detach(struct fwohci_softc *sc, device_t dev) 732 { 733 int i; 734 735 if (sc->fc.sid_buf != NULL) 736 free((void *)(uintptr_t)sc->fc.sid_buf, M_FW); 737 if (sc->cromptr != NULL) 738 free((void *)sc->cromptr, M_FW); 739 740 fwohci_db_free(&sc->arrq); 741 fwohci_db_free(&sc->arrs); 742 743 fwohci_db_free(&sc->atrq); 744 fwohci_db_free(&sc->atrs); 745 746 for( i = 0 ; i < sc->fc.nisodma ; i ++ ){ 747 fwohci_db_free(&sc->it[i]); 748 fwohci_db_free(&sc->ir[i]); 749 } 750 751 return 0; 752 } 753 754 #define LAST_DB(dbtr, db) do { \ 755 struct fwohcidb_tr *_dbtr = (dbtr); \ 756 int _cnt = _dbtr->dbcnt; \ 757 db = &_dbtr->db[ (_cnt > 2) ? (_cnt -1) : 0]; \ 758 } while (0) 759 760 static void 761 fwohci_start(struct fwohci_softc *sc, struct fwohci_dbch *dbch) 762 { 763 int i, s; 764 int tcode, hdr_len, hdr_off, len; 765 int fsegment = -1; 766 u_int32_t off; 767 struct fw_xfer *xfer; 768 struct fw_pkt *fp; 769 volatile struct fwohci_txpkthdr *ohcifp; 770 struct fwohcidb_tr *db_tr; 771 volatile struct fwohcidb *db; 772 struct mbuf *m; 773 struct tcode_info *info; 774 static int maxdesc=0; 775 776 if(&sc->atrq == dbch){ 777 off = OHCI_ATQOFF; 778 }else if(&sc->atrs == dbch){ 779 off = OHCI_ATSOFF; 780 }else{ 781 return; 782 } 783 784 if (dbch->flags & FWOHCI_DBCH_FULL) 785 return; 786 787 s = splfw(); 788 db_tr = dbch->top; 789 txloop: 790 xfer = STAILQ_FIRST(&dbch->xferq.q); 791 if(xfer == NULL){ 792 goto kick; 793 } 794 if(dbch->xferq.queued == 0 ){ 795 device_printf(sc->fc.dev, "TX queue empty\n"); 796 } 797 STAILQ_REMOVE_HEAD(&dbch->xferq.q, link); 798 db_tr->xfer = xfer; 799 xfer->state = FWXF_START; 800 dbch->xferq.packets++; 801 802 fp = (struct fw_pkt *)(xfer->send.buf + xfer->send.off); 803 tcode = fp->mode.common.tcode; 804 805 ohcifp = (volatile struct fwohci_txpkthdr *) db_tr->db[1].db.immed; 806 info = &tinfo[tcode]; 807 hdr_len = hdr_off = info->hdr_len; 808 /* fw_asyreq must pass valid send.len */ 809 len = xfer->send.len; 810 for( i = 0 ; i < hdr_off ; i+= 4){ 811 ohcifp->mode.ld[i/4] = ntohl(fp->mode.ld[i/4]); 812 } 813 ohcifp->mode.common.spd = xfer->spd; 814 if (tcode == FWTCODE_STREAM ){ 815 hdr_len = 8; 816 ohcifp->mode.stream.len = ntohs(fp->mode.stream.len); 817 } else if (tcode == FWTCODE_PHY) { 818 hdr_len = 12; 819 ohcifp->mode.ld[1] = ntohl(fp->mode.ld[1]); 820 ohcifp->mode.ld[2] = ntohl(fp->mode.ld[2]); 821 ohcifp->mode.common.spd = 0; 822 ohcifp->mode.common.tcode = FWOHCITCODE_PHY; 823 } else { 824 ohcifp->mode.asycomm.dst = ntohs(fp->mode.hdr.dst); 825 ohcifp->mode.asycomm.srcbus = OHCI_ASYSRCBUS; 826 ohcifp->mode.asycomm.tlrt |= FWRETRY_X; 827 } 828 db = &db_tr->db[0]; 829 db->db.desc.control = OHCI_OUTPUT_MORE | OHCI_KEY_ST2; 830 db->db.desc.reqcount = hdr_len; 831 db->db.desc.status = 0; 832 /* Specify bound timer of asy. responce */ 833 if(&sc->atrs == dbch){ 834 db->db.desc.count 835 = (OREAD(sc, OHCI_CYCLETIMER) >> 12) + (1 << 13); 836 } 837 838 again: 839 db_tr->dbcnt = 2; 840 db = &db_tr->db[db_tr->dbcnt]; 841 if(len > hdr_off){ 842 if (xfer->mbuf == NULL) { 843 db->db.desc.addr 844 = vtophys(xfer->send.buf + xfer->send.off) + hdr_off; 845 db->db.desc.control = OHCI_OUTPUT_MORE; 846 db->db.desc.reqcount = len - hdr_off; 847 db->db.desc.status = 0; 848 849 db_tr->dbcnt++; 850 } else { 851 int mchain=0; 852 /* XXX we can handle only 6 (=8-2) mbuf chains */ 853 for (m = xfer->mbuf; m != NULL; m = m->m_next) { 854 if (m->m_len == 0) 855 /* unrecoverable error could occur. */ 856 continue; 857 mchain++; 858 if (db_tr->dbcnt >= dbch->ndesc) 859 continue; 860 db->db.desc.addr 861 = vtophys(mtod(m, caddr_t)); 862 db->db.desc.control = OHCI_OUTPUT_MORE; 863 db->db.desc.reqcount = m->m_len; 864 db->db.desc.status = 0; 865 db++; 866 db_tr->dbcnt++; 867 } 868 if (mchain > dbch->ndesc - 2) { 869 struct mbuf *m_new; 870 if (bootverbose) 871 device_printf(sc->fc.dev, 872 "too long mbuf chain(%d)\n", 873 mchain); 874 m_new = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 875 if (m_new != NULL) { 876 m_copydata(xfer->mbuf, 0, 877 xfer->mbuf->m_pkthdr.len, 878 mtod(m_new, caddr_t)); 879 m_new->m_pkthdr.len = m_new->m_len = 880 xfer->mbuf->m_pkthdr.len; 881 m_freem(xfer->mbuf); 882 xfer->mbuf = m_new; 883 goto again; 884 } 885 device_printf(sc->fc.dev, "m_getcl failed.\n"); 886 } 887 } 888 } 889 if (maxdesc < db_tr->dbcnt) { 890 maxdesc = db_tr->dbcnt; 891 if (bootverbose) 892 device_printf(sc->fc.dev, "maxdesc: %d\n", maxdesc); 893 } 894 /* last db */ 895 LAST_DB(db_tr, db); 896 db->db.desc.control |= OHCI_OUTPUT_LAST 897 | OHCI_INTERRUPT_ALWAYS 898 | OHCI_BRANCH_ALWAYS; 899 db->db.desc.depend = vtophys(STAILQ_NEXT(db_tr, link)->db); 900 901 if(fsegment == -1 ) 902 fsegment = db_tr->dbcnt; 903 if (dbch->pdb_tr != NULL) { 904 LAST_DB(dbch->pdb_tr, db); 905 db->db.desc.depend |= db_tr->dbcnt; 906 } 907 dbch->pdb_tr = db_tr; 908 db_tr = STAILQ_NEXT(db_tr, link); 909 if(db_tr != dbch->bottom){ 910 goto txloop; 911 } else { 912 device_printf(sc->fc.dev, "fwohci_start: lack of db_trq\n"); 913 dbch->flags |= FWOHCI_DBCH_FULL; 914 } 915 kick: 916 /* kick asy q */ 917 918 if(dbch->xferq.flag & FWXFERQ_RUNNING) { 919 OWRITE(sc, OHCI_DMACTL(off), OHCI_CNTL_DMA_WAKE); 920 } else { 921 if (bootverbose) 922 device_printf(sc->fc.dev, "start AT DMA status=%x\n", 923 OREAD(sc, OHCI_DMACTL(off))); 924 OWRITE(sc, OHCI_DMACMD(off), vtophys(dbch->top->db) | fsegment); 925 OWRITE(sc, OHCI_DMACTL(off), OHCI_CNTL_DMA_RUN); 926 dbch->xferq.flag |= FWXFERQ_RUNNING; 927 } 928 929 dbch->top = db_tr; 930 splx(s); 931 return; 932 } 933 934 static void 935 fwohci_drain_atq(struct firewire_comm *fc, struct fw_xfer *xfer) 936 { 937 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 938 fwohci_drain(&sc->fc, xfer, &(sc->atrq)); 939 return; 940 } 941 942 static void 943 fwohci_drain_ats(struct firewire_comm *fc, struct fw_xfer *xfer) 944 { 945 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 946 fwohci_drain(&sc->fc, xfer, &(sc->atrs)); 947 return; 948 } 949 950 static void 951 fwohci_start_atq(struct firewire_comm *fc) 952 { 953 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 954 fwohci_start( sc, &(sc->atrq)); 955 return; 956 } 957 958 static void 959 fwohci_start_ats(struct firewire_comm *fc) 960 { 961 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 962 fwohci_start( sc, &(sc->atrs)); 963 return; 964 } 965 966 void 967 fwohci_txd(struct fwohci_softc *sc, struct fwohci_dbch *dbch) 968 { 969 int s, err = 0; 970 struct fwohcidb_tr *tr; 971 volatile struct fwohcidb *db; 972 struct fw_xfer *xfer; 973 u_int32_t off; 974 u_int stat; 975 int packets; 976 struct firewire_comm *fc = (struct firewire_comm *)sc; 977 if(&sc->atrq == dbch){ 978 off = OHCI_ATQOFF; 979 }else if(&sc->atrs == dbch){ 980 off = OHCI_ATSOFF; 981 }else{ 982 return; 983 } 984 s = splfw(); 985 tr = dbch->bottom; 986 packets = 0; 987 while(dbch->xferq.queued > 0){ 988 LAST_DB(tr, db); 989 if(!(db->db.desc.status & OHCI_CNTL_DMA_ACTIVE)){ 990 if (fc->status != FWBUSRESET) 991 /* maybe out of order?? */ 992 goto out; 993 } 994 if(db->db.desc.status & OHCI_CNTL_DMA_DEAD) { 995 #ifdef OHCI_DEBUG 996 dump_dma(sc, ch); 997 dump_db(sc, ch); 998 #endif 999 /* Stop DMA */ 1000 OWRITE(sc, OHCI_DMACTLCLR(off), OHCI_CNTL_DMA_RUN); 1001 device_printf(sc->fc.dev, "force reset AT FIFO\n"); 1002 OWRITE(sc, OHCI_HCCCTLCLR, OHCI_HCC_LINKEN); 1003 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_LPS | OHCI_HCC_LINKEN); 1004 OWRITE(sc, OHCI_DMACTLCLR(off), OHCI_CNTL_DMA_RUN); 1005 } 1006 stat = db->db.desc.status & FWOHCIEV_MASK; 1007 switch(stat){ 1008 case FWOHCIEV_ACKPEND: 1009 case FWOHCIEV_ACKCOMPL: 1010 err = 0; 1011 break; 1012 case FWOHCIEV_ACKBSA: 1013 case FWOHCIEV_ACKBSB: 1014 case FWOHCIEV_ACKBSX: 1015 device_printf(sc->fc.dev, "txd err=%2x %s\n", stat, fwohcicode[stat]); 1016 err = EBUSY; 1017 break; 1018 case FWOHCIEV_FLUSHED: 1019 case FWOHCIEV_ACKTARD: 1020 device_printf(sc->fc.dev, "txd err=%2x %s\n", stat, fwohcicode[stat]); 1021 err = EAGAIN; 1022 break; 1023 case FWOHCIEV_MISSACK: 1024 case FWOHCIEV_UNDRRUN: 1025 case FWOHCIEV_OVRRUN: 1026 case FWOHCIEV_DESCERR: 1027 case FWOHCIEV_DTRDERR: 1028 case FWOHCIEV_TIMEOUT: 1029 case FWOHCIEV_TCODERR: 1030 case FWOHCIEV_UNKNOWN: 1031 case FWOHCIEV_ACKDERR: 1032 case FWOHCIEV_ACKTERR: 1033 default: 1034 device_printf(sc->fc.dev, "txd err=%2x %s\n", 1035 stat, fwohcicode[stat]); 1036 err = EINVAL; 1037 break; 1038 } 1039 if (tr->xfer != NULL) { 1040 xfer = tr->xfer; 1041 xfer->state = FWXF_SENT; 1042 if (err == EBUSY && fc->status != FWBUSRESET) { 1043 xfer->state = FWXF_BUSY; 1044 switch (xfer->act_type) { 1045 case FWACT_XFER: 1046 xfer->resp = err; 1047 if (xfer->retry_req != NULL) 1048 xfer->retry_req(xfer); 1049 else 1050 fw_xfer_done(xfer); 1051 break; 1052 default: 1053 break; 1054 } 1055 } else if (stat != FWOHCIEV_ACKPEND) { 1056 if (stat != FWOHCIEV_ACKCOMPL) 1057 xfer->state = FWXF_SENTERR; 1058 xfer->resp = err; 1059 switch (xfer->act_type) { 1060 case FWACT_XFER: 1061 fw_xfer_done(xfer); 1062 break; 1063 default: 1064 break; 1065 } 1066 } 1067 /* 1068 * The watchdog timer takes care of split 1069 * transcation timeout for ACKPEND case. 1070 */ 1071 } 1072 dbch->xferq.queued --; 1073 tr->xfer = NULL; 1074 1075 packets ++; 1076 tr = STAILQ_NEXT(tr, link); 1077 dbch->bottom = tr; 1078 if (dbch->bottom == dbch->top) { 1079 /* we reaches the end of context program */ 1080 if (firewire_debug && dbch->xferq.queued > 0) 1081 printf("queued > 0\n"); 1082 break; 1083 } 1084 } 1085 out: 1086 if ((dbch->flags & FWOHCI_DBCH_FULL) && packets > 0) { 1087 printf("make free slot\n"); 1088 dbch->flags &= ~FWOHCI_DBCH_FULL; 1089 fwohci_start(sc, dbch); 1090 } 1091 splx(s); 1092 } 1093 1094 static void 1095 fwohci_drain(struct firewire_comm *fc, struct fw_xfer *xfer, struct fwohci_dbch *dbch) 1096 { 1097 int i, s, found=0; 1098 struct fwohcidb_tr *tr; 1099 1100 if(xfer->state != FWXF_START) return; 1101 1102 s = splfw(); 1103 tr = dbch->bottom; 1104 for (i = 0; i < dbch->xferq.queued; i ++) { 1105 if(tr->xfer == xfer){ 1106 tr->xfer = NULL; 1107 #if 0 1108 dbch->xferq.queued --; 1109 /* XXX */ 1110 if (tr == dbch->bottom) 1111 dbch->bottom = STAILQ_NEXT(tr, link); 1112 if (dbch->flags & FWOHCI_DBCH_FULL) { 1113 printf("fwohci_drain: make slot\n"); 1114 dbch->flags &= ~FWOHCI_DBCH_FULL; 1115 fwohci_start((struct fwohci_softc *)fc, dbch); 1116 } 1117 #endif 1118 found ++; 1119 break; 1120 } 1121 tr = STAILQ_NEXT(tr, link); 1122 } 1123 splx(s); 1124 if (!found) 1125 device_printf(fc->dev, "fwochi_drain: xfer not found\n"); 1126 return; 1127 } 1128 1129 static void 1130 fwohci_db_free(struct fwohci_dbch *dbch) 1131 { 1132 struct fwohcidb_tr *db_tr; 1133 int idb, i; 1134 1135 if ((dbch->flags & FWOHCI_DBCH_INIT) == 0) 1136 return; 1137 1138 if(!(dbch->xferq.flag & FWXFERQ_EXTBUF)){ 1139 for(db_tr = STAILQ_FIRST(&dbch->db_trq), idb = 0; 1140 idb < dbch->ndb; 1141 db_tr = STAILQ_NEXT(db_tr, link), idb++){ 1142 if (db_tr->buf != NULL) { 1143 free(db_tr->buf, M_FW); 1144 db_tr->buf = NULL; 1145 } 1146 } 1147 } 1148 dbch->ndb = 0; 1149 db_tr = STAILQ_FIRST(&dbch->db_trq); 1150 for (i = 0; i < dbch->npages; i++) 1151 free(dbch->pages[i], M_FW); 1152 free(db_tr, M_FW); 1153 STAILQ_INIT(&dbch->db_trq); 1154 dbch->flags &= ~FWOHCI_DBCH_INIT; 1155 } 1156 1157 static void 1158 fwohci_db_init(struct fwohci_dbch *dbch) 1159 { 1160 int idb; 1161 struct fwohcidb_tr *db_tr; 1162 int ndbpp, i, j; 1163 1164 if ((dbch->flags & FWOHCI_DBCH_INIT) != 0) 1165 goto out; 1166 1167 /* allocate DB entries and attach one to each DMA channels */ 1168 /* DB entry must start at 16 bytes bounary. */ 1169 STAILQ_INIT(&dbch->db_trq); 1170 db_tr = (struct fwohcidb_tr *) 1171 malloc(sizeof(struct fwohcidb_tr) * dbch->ndb, 1172 M_FW, M_ZERO); 1173 if(db_tr == NULL){ 1174 printf("fwohci_db_init: malloc(1) failed\n"); 1175 return; 1176 } 1177 1178 ndbpp = PAGE_SIZE / (sizeof(struct fwohcidb) * dbch->ndesc); 1179 dbch->npages = (dbch->ndb + ndbpp - 1)/ ndbpp; 1180 if (firewire_debug) 1181 printf("ndesc: %d, ndbpp: %d, ndb: %d, npages: %d\n", 1182 dbch->ndesc, ndbpp, dbch->ndb, dbch->npages); 1183 if (dbch->npages > FWOHCI_DBCH_MAX_PAGES) { 1184 printf("npages(%d) > DBCH_MAX_PAGES(%d)\n", 1185 dbch->npages, FWOHCI_DBCH_MAX_PAGES); 1186 return; 1187 } 1188 for (i = 0; i < dbch->npages; i++) { 1189 dbch->pages[i] = malloc(PAGE_SIZE, M_FW, M_ZERO); 1190 if (dbch->pages[i] == NULL) { 1191 printf("fwohci_db_init: malloc(2) failed\n"); 1192 for (j = 0; j < i; j ++) 1193 free(dbch->pages[j], M_FW); 1194 free(db_tr, M_FW); 1195 return; 1196 } 1197 } 1198 /* Attach DB to DMA ch. */ 1199 for(idb = 0 ; idb < dbch->ndb ; idb++){ 1200 db_tr->dbcnt = 0; 1201 db_tr->db = (struct fwohcidb *)dbch->pages[idb/ndbpp] 1202 + dbch->ndesc * (idb % ndbpp); 1203 STAILQ_INSERT_TAIL(&dbch->db_trq, db_tr, link); 1204 if (!(dbch->xferq.flag & FWXFERQ_PACKET) && 1205 dbch->xferq.bnpacket != 0) { 1206 if (idb % dbch->xferq.bnpacket == 0) 1207 dbch->xferq.bulkxfer[idb / dbch->xferq.bnpacket 1208 ].start = (caddr_t)db_tr; 1209 if ((idb + 1) % dbch->xferq.bnpacket == 0) 1210 dbch->xferq.bulkxfer[idb / dbch->xferq.bnpacket 1211 ].end = (caddr_t)db_tr; 1212 } 1213 db_tr++; 1214 } 1215 STAILQ_LAST(&dbch->db_trq, fwohcidb_tr,link)->link.stqe_next 1216 = STAILQ_FIRST(&dbch->db_trq); 1217 out: 1218 dbch->frag.buf = NULL; 1219 dbch->frag.len = 0; 1220 dbch->frag.plen = 0; 1221 dbch->xferq.queued = 0; 1222 dbch->pdb_tr = NULL; 1223 dbch->top = STAILQ_FIRST(&dbch->db_trq); 1224 dbch->bottom = dbch->top; 1225 dbch->flags = FWOHCI_DBCH_INIT; 1226 } 1227 1228 static int 1229 fwohci_itx_disable(struct firewire_comm *fc, int dmach) 1230 { 1231 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 1232 int dummy; 1233 1234 OWRITE(sc, OHCI_ITCTLCLR(dmach), OHCI_CNTL_DMA_RUN); 1235 OWRITE(sc, OHCI_IT_MASKCLR, 1 << dmach); 1236 OWRITE(sc, OHCI_IT_STATCLR, 1 << dmach); 1237 /* XXX we cannot free buffers until the DMA really stops */ 1238 tsleep((void *)&dummy, FWPRI, "fwitxd", hz); 1239 fwohci_db_free(&sc->it[dmach]); 1240 sc->it[dmach].xferq.flag &= ~FWXFERQ_RUNNING; 1241 return 0; 1242 } 1243 1244 static int 1245 fwohci_irx_disable(struct firewire_comm *fc, int dmach) 1246 { 1247 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 1248 int dummy; 1249 1250 OWRITE(sc, OHCI_IRCTLCLR(dmach), OHCI_CNTL_DMA_RUN); 1251 OWRITE(sc, OHCI_IR_MASKCLR, 1 << dmach); 1252 OWRITE(sc, OHCI_IR_STATCLR, 1 << dmach); 1253 /* XXX we cannot free buffers until the DMA really stops */ 1254 tsleep((void *)&dummy, FWPRI, "fwirxd", hz); 1255 if(sc->ir[dmach].dummy != NULL){ 1256 free(sc->ir[dmach].dummy, M_FW); 1257 } 1258 sc->ir[dmach].dummy = NULL; 1259 fwohci_db_free(&sc->ir[dmach]); 1260 sc->ir[dmach].xferq.flag &= ~FWXFERQ_RUNNING; 1261 return 0; 1262 } 1263 1264 static void 1265 fwohci_irx_post (struct firewire_comm *fc , u_int32_t *qld) 1266 { 1267 qld[0] = ntohl(qld[0]); 1268 return; 1269 } 1270 1271 static int 1272 fwohci_irxpp_enable(struct firewire_comm *fc, int dmach) 1273 { 1274 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 1275 int err = 0; 1276 unsigned short tag, ich; 1277 1278 tag = (sc->ir[dmach].xferq.flag >> 6) & 3; 1279 ich = sc->ir[dmach].xferq.flag & 0x3f; 1280 1281 #if 0 1282 if(STAILQ_FIRST(&fc->ir[dmach]->q) != NULL){ 1283 wakeup(fc->ir[dmach]); 1284 return err; 1285 } 1286 #endif 1287 1288 OWRITE(sc, OHCI_IRMATCH(dmach), tagbit[tag] | ich); 1289 if(!(sc->ir[dmach].xferq.flag & FWXFERQ_RUNNING)){ 1290 sc->ir[dmach].xferq.queued = 0; 1291 sc->ir[dmach].ndb = NDB; 1292 sc->ir[dmach].xferq.psize = PAGE_SIZE; 1293 sc->ir[dmach].ndesc = 1; 1294 fwohci_db_init(&sc->ir[dmach]); 1295 if ((sc->ir[dmach].flags & FWOHCI_DBCH_INIT) == 0) 1296 return ENOMEM; 1297 err = fwohci_rx_enable(sc, &sc->ir[dmach]); 1298 } 1299 if(err){ 1300 device_printf(sc->fc.dev, "err in IRX setting\n"); 1301 return err; 1302 } 1303 if(!(OREAD(sc, OHCI_IRCTL(dmach)) & OHCI_CNTL_DMA_ACTIVE)){ 1304 OWRITE(sc, OHCI_IRCTLCLR(dmach), OHCI_CNTL_DMA_RUN); 1305 OWRITE(sc, OHCI_IR_MASKCLR, 1 << dmach); 1306 OWRITE(sc, OHCI_IR_STATCLR, 1 << dmach); 1307 OWRITE(sc, OHCI_IR_MASK, 1 << dmach); 1308 OWRITE(sc, OHCI_IRCTLCLR(dmach), 0xf8000000); 1309 OWRITE(sc, OHCI_IRCTL(dmach), OHCI_CNTL_ISOHDR); 1310 OWRITE(sc, OHCI_IRCMD(dmach), 1311 vtophys(sc->ir[dmach].top->db) | 1); 1312 OWRITE(sc, OHCI_IRCTL(dmach), OHCI_CNTL_DMA_RUN); 1313 OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_DMA_IR); 1314 } 1315 return err; 1316 } 1317 1318 static int 1319 fwohci_tx_enable(struct fwohci_softc *sc, struct fwohci_dbch *dbch) 1320 { 1321 int err = 0; 1322 int idb, z, i, dmach = 0; 1323 u_int32_t off = NULL; 1324 struct fwohcidb_tr *db_tr; 1325 volatile struct fwohcidb *db; 1326 1327 if(!(dbch->xferq.flag & FWXFERQ_EXTBUF)){ 1328 err = EINVAL; 1329 return err; 1330 } 1331 z = dbch->ndesc; 1332 for(dmach = 0 ; dmach < sc->fc.nisodma ; dmach++){ 1333 if( &sc->it[dmach] == dbch){ 1334 off = OHCI_ITOFF(dmach); 1335 break; 1336 } 1337 } 1338 if(off == NULL){ 1339 err = EINVAL; 1340 return err; 1341 } 1342 if(dbch->xferq.flag & FWXFERQ_RUNNING) 1343 return err; 1344 dbch->xferq.flag |= FWXFERQ_RUNNING; 1345 for( i = 0, dbch->bottom = dbch->top; i < (dbch->ndb - 1); i++){ 1346 dbch->bottom = STAILQ_NEXT(dbch->bottom, link); 1347 } 1348 db_tr = dbch->top; 1349 for( idb = 0 ; idb < dbch->ndb ; idb ++){ 1350 fwohci_add_tx_buf(db_tr, 1351 dbch->xferq.psize, dbch->xferq.flag, 1352 dbch->xferq.buf + dbch->xferq.psize * idb); 1353 if(STAILQ_NEXT(db_tr, link) == NULL){ 1354 break; 1355 } 1356 db = db_tr->db; 1357 db[0].db.desc.depend = db[db_tr->dbcnt - 1].db.desc.depend 1358 = vtophys(STAILQ_NEXT(db_tr, link)->db) | z; 1359 if(dbch->xferq.flag & FWXFERQ_EXTBUF){ 1360 if(((idb + 1 ) % dbch->xferq.bnpacket) == 0){ 1361 db[db_tr->dbcnt - 1].db.desc.control 1362 |= OHCI_INTERRUPT_ALWAYS; 1363 /* OHCI 1.1 and above */ 1364 db[0].db.desc.control |= OHCI_INTERRUPT_ALWAYS; 1365 #if 0 1366 db[0].db.desc.depend &= ~0xf; 1367 db[db_tr->dbcnt - 1].db.desc.depend &= ~0xf; 1368 #endif 1369 } 1370 } 1371 db_tr = STAILQ_NEXT(db_tr, link); 1372 } 1373 dbch->bottom->db[db_tr->dbcnt - 1].db.desc.depend &= 0xfffffff0; 1374 return err; 1375 } 1376 1377 static int 1378 fwohci_rx_enable(struct fwohci_softc *sc, struct fwohci_dbch *dbch) 1379 { 1380 int err = 0; 1381 int idb, z, i, dmach = 0, ldesc; 1382 u_int32_t off = NULL; 1383 struct fwohcidb_tr *db_tr; 1384 volatile struct fwohcidb *db; 1385 1386 z = dbch->ndesc; 1387 if(&sc->arrq == dbch){ 1388 off = OHCI_ARQOFF; 1389 }else if(&sc->arrs == dbch){ 1390 off = OHCI_ARSOFF; 1391 }else{ 1392 for(dmach = 0 ; dmach < sc->fc.nisodma ; dmach++){ 1393 if( &sc->ir[dmach] == dbch){ 1394 off = OHCI_IROFF(dmach); 1395 break; 1396 } 1397 } 1398 } 1399 if(off == NULL){ 1400 err = EINVAL; 1401 return err; 1402 } 1403 if(dbch->xferq.flag & FWXFERQ_STREAM){ 1404 if(dbch->xferq.flag & FWXFERQ_RUNNING) 1405 return err; 1406 }else{ 1407 if(dbch->xferq.flag & FWXFERQ_RUNNING){ 1408 err = EBUSY; 1409 return err; 1410 } 1411 } 1412 dbch->xferq.flag |= FWXFERQ_RUNNING; 1413 dbch->top = STAILQ_FIRST(&dbch->db_trq); 1414 for( i = 0, dbch->bottom = dbch->top; i < (dbch->ndb - 1); i++){ 1415 dbch->bottom = STAILQ_NEXT(dbch->bottom, link); 1416 } 1417 db_tr = dbch->top; 1418 for( idb = 0 ; idb < dbch->ndb ; idb ++){ 1419 if(!(dbch->xferq.flag & FWXFERQ_EXTBUF)){ 1420 fwohci_add_rx_buf(db_tr, 1421 dbch->xferq.psize, dbch->xferq.flag, 0, NULL); 1422 }else{ 1423 fwohci_add_rx_buf(db_tr, 1424 dbch->xferq.psize, dbch->xferq.flag, 1425 dbch->xferq.bulkxfer[idb 1426 / dbch->xferq.bnpacket].buf 1427 + dbch->xferq.psize * 1428 (idb % dbch->xferq.bnpacket), 1429 dbch->dummy + sizeof(u_int32_t) * idb); 1430 } 1431 if(STAILQ_NEXT(db_tr, link) == NULL){ 1432 break; 1433 } 1434 db = db_tr->db; 1435 ldesc = db_tr->dbcnt - 1; 1436 db[ldesc].db.desc.depend 1437 = vtophys(STAILQ_NEXT(db_tr, link)->db) | z; 1438 if(dbch->xferq.flag & FWXFERQ_EXTBUF){ 1439 if(((idb + 1 ) % dbch->xferq.bnpacket) == 0){ 1440 db[ldesc].db.desc.control 1441 |= OHCI_INTERRUPT_ALWAYS; 1442 db[ldesc].db.desc.depend &= ~0xf; 1443 } 1444 } 1445 db_tr = STAILQ_NEXT(db_tr, link); 1446 } 1447 dbch->bottom->db[db_tr->dbcnt - 1].db.desc.depend &= 0xfffffff0; 1448 dbch->buf_offset = 0; 1449 if(dbch->xferq.flag & FWXFERQ_STREAM){ 1450 return err; 1451 }else{ 1452 OWRITE(sc, OHCI_DMACMD(off), vtophys(dbch->top->db) | z); 1453 } 1454 OWRITE(sc, OHCI_DMACTL(off), OHCI_CNTL_DMA_RUN); 1455 return err; 1456 } 1457 1458 static int 1459 fwochi_next_cycle(struct firewire_comm *fc, int cycle_now) 1460 { 1461 int sec, cycle, cycle_match; 1462 1463 cycle = cycle_now & 0x1fff; 1464 sec = cycle_now >> 13; 1465 #define CYCLE_MOD 0x10 1466 #define CYCLE_DELAY 8 /* min delay to start DMA */ 1467 cycle = cycle + CYCLE_DELAY; 1468 if (cycle >= 8000) { 1469 sec ++; 1470 cycle -= 8000; 1471 } 1472 cycle = ((cycle + CYCLE_MOD - 1) / CYCLE_MOD) * CYCLE_MOD; 1473 if (cycle >= 8000) { 1474 sec ++; 1475 if (cycle == 8000) 1476 cycle = 0; 1477 else 1478 cycle = CYCLE_MOD; 1479 } 1480 cycle_match = ((sec << 13) | cycle) & 0x7ffff; 1481 1482 return(cycle_match); 1483 } 1484 1485 static int 1486 fwohci_itxbuf_enable(struct firewire_comm *fc, int dmach) 1487 { 1488 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 1489 int err = 0; 1490 unsigned short tag, ich; 1491 struct fwohci_dbch *dbch; 1492 int cycle_match, cycle_now, s, ldesc; 1493 u_int32_t stat; 1494 struct fw_bulkxfer *first, *chunk, *prev; 1495 struct fw_xferq *it; 1496 1497 dbch = &sc->it[dmach]; 1498 it = &dbch->xferq; 1499 1500 tag = (it->flag >> 6) & 3; 1501 ich = it->flag & 0x3f; 1502 if ((dbch->flags & FWOHCI_DBCH_INIT) == 0) { 1503 dbch->ndb = it->bnpacket * it->bnchunk; 1504 dbch->ndesc = 3; 1505 fwohci_db_init(dbch); 1506 if ((dbch->flags & FWOHCI_DBCH_INIT) == 0) 1507 return ENOMEM; 1508 err = fwohci_tx_enable(sc, dbch); 1509 } 1510 if(err) 1511 return err; 1512 1513 ldesc = dbch->ndesc - 1; 1514 s = splfw(); 1515 prev = STAILQ_LAST(&it->stdma, fw_bulkxfer, link); 1516 while ((chunk = STAILQ_FIRST(&it->stvalid)) != NULL) { 1517 volatile struct fwohcidb *db; 1518 1519 fwohci_txbufdb(sc, dmach, chunk); 1520 #if 0 1521 db = ((struct fwohcidb_tr *)(chunk->end))->db; 1522 db[ldesc].db.desc.status = db[0].db.desc.status = 0; 1523 db[ldesc].db.desc.count = db[0].db.desc.count = 0; 1524 db[ldesc].db.desc.depend &= ~0xf; 1525 db[0].db.desc.depend &= ~0xf; 1526 #endif 1527 if (prev != NULL) { 1528 db = ((struct fwohcidb_tr *)(prev->end))->db; 1529 db[ldesc].db.desc.control |= OHCI_BRANCH_ALWAYS; 1530 #if 0 /* if bulkxfer->npacket changes */ 1531 db[ldesc].db.desc.depend = db[0].db.desc.depend = 1532 vtophys(((struct fwohcidb_tr *) 1533 (chunk->start))->db) | dbch->ndesc; 1534 #else 1535 db[0].db.desc.depend |= dbch->ndesc; 1536 db[ldesc].db.desc.depend |= dbch->ndesc; 1537 #endif 1538 } 1539 STAILQ_REMOVE_HEAD(&it->stvalid, link); 1540 STAILQ_INSERT_TAIL(&it->stdma, chunk, link); 1541 prev = chunk; 1542 } 1543 splx(s); 1544 stat = OREAD(sc, OHCI_ITCTL(dmach)); 1545 if (stat & (OHCI_CNTL_DMA_ACTIVE | OHCI_CNTL_CYCMATCH_S)) 1546 return 0; 1547 1548 OWRITE(sc, OHCI_ITCTLCLR(dmach), OHCI_CNTL_DMA_RUN); 1549 OWRITE(sc, OHCI_IT_MASKCLR, 1 << dmach); 1550 OWRITE(sc, OHCI_IT_STATCLR, 1 << dmach); 1551 OWRITE(sc, OHCI_IT_MASK, 1 << dmach); 1552 1553 first = STAILQ_FIRST(&it->stdma); 1554 OWRITE(sc, OHCI_ITCMD(dmach), vtophys(((struct fwohcidb_tr *) 1555 (first->start))->db) | dbch->ndesc); 1556 if (firewire_debug) 1557 printf("fwohci_itxbuf_enable: kick 0x%08x\n", stat); 1558 if ((stat & OHCI_CNTL_DMA_RUN) == 0) { 1559 #if 1 1560 /* Don't start until all chunks are buffered */ 1561 if (STAILQ_FIRST(&it->stfree) != NULL) 1562 goto out; 1563 #endif 1564 #ifdef FWXFERQ_DV 1565 #define CYCLE_OFFSET 1 1566 if(dbch->xferq.flag & FWXFERQ_DV){ 1567 struct fw_pkt *fp; 1568 struct fwohcidb_tr *db_tr; 1569 1570 db_tr = (struct fwohcidb_tr *)dbch->xferq.stdma->start; 1571 fp = (struct fw_pkt *)db_tr->buf; 1572 dbch->xferq.dvoffset = CYCLE_OFFSET; 1573 fp->mode.ld[2] |= htonl(dbch->xferq.dvoffset << 12); 1574 } 1575 #endif 1576 /* Clear cycle match counter bits */ 1577 OWRITE(sc, OHCI_ITCTLCLR(dmach), 0xffff0000); 1578 OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_DMA_IT); 1579 1580 /* 2bit second + 13bit cycle */ 1581 cycle_now = (fc->cyctimer(fc) >> 12) & 0x7fff; 1582 cycle_match = fwochi_next_cycle(fc, cycle_now); 1583 1584 OWRITE(sc, OHCI_ITCTL(dmach), 1585 OHCI_CNTL_CYCMATCH_S | (cycle_match << 16) 1586 | OHCI_CNTL_DMA_RUN); 1587 if (firewire_debug) 1588 printf("cycle_match: 0x%04x->0x%04x\n", 1589 cycle_now, cycle_match); 1590 } else if ((stat & OHCI_CNTL_CYCMATCH_S) == 0) { 1591 device_printf(sc->fc.dev, 1592 "IT DMA underrun (0x%08x)\n", stat); 1593 OWRITE(sc, OHCI_ITCTL(dmach), OHCI_CNTL_DMA_RUN); 1594 } 1595 out: 1596 return err; 1597 } 1598 1599 static int 1600 fwohci_irxbuf_enable(struct firewire_comm *fc, int dmach) 1601 { 1602 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 1603 int err = 0, s, ldesc; 1604 unsigned short tag, ich; 1605 u_int32_t stat; 1606 struct fwohci_dbch *dbch; 1607 struct fw_bulkxfer *first, *prev, *chunk; 1608 struct fw_xferq *ir; 1609 1610 dbch = &sc->ir[dmach]; 1611 ir = &dbch->xferq; 1612 1613 if ((ir->flag & FWXFERQ_RUNNING) == 0) { 1614 tag = (ir->flag >> 6) & 3; 1615 ich = ir->flag & 0x3f; 1616 OWRITE(sc, OHCI_IRMATCH(dmach), tagbit[tag] | ich); 1617 1618 ir->queued = 0; 1619 dbch->ndb = ir->bnpacket * ir->bnchunk; 1620 dbch->dummy = malloc(sizeof(u_int32_t) * dbch->ndb, 1621 M_FW, 0); 1622 if (dbch->dummy == NULL) { 1623 err = ENOMEM; 1624 return err; 1625 } 1626 dbch->ndesc = 2; 1627 fwohci_db_init(dbch); 1628 if ((dbch->flags & FWOHCI_DBCH_INIT) == 0) 1629 return ENOMEM; 1630 err = fwohci_rx_enable(sc, dbch); 1631 } 1632 if(err) 1633 return err; 1634 1635 first = STAILQ_FIRST(&ir->stfree); 1636 if (first == NULL) { 1637 device_printf(fc->dev, "IR DMA no free chunk\n"); 1638 return 0; 1639 } 1640 1641 ldesc = dbch->ndesc - 1; 1642 s = splfw(); 1643 prev = STAILQ_LAST(&ir->stdma, fw_bulkxfer, link); 1644 while ((chunk = STAILQ_FIRST(&ir->stfree)) != NULL) { 1645 volatile struct fwohcidb *db; 1646 1647 #if 1 /* XXX for if_fwe */ 1648 db = ((struct fwohcidb_tr *)(chunk->start))->db; 1649 db[ldesc].db.desc.addr = vtophys(chunk->buf); 1650 #endif 1651 db = ((struct fwohcidb_tr *)(chunk->end))->db; 1652 db[ldesc].db.desc.status = db[ldesc].db.desc.count = 0; 1653 db[ldesc].db.desc.depend &= ~0xf; 1654 if (prev != NULL) { 1655 db = ((struct fwohcidb_tr *)(prev->end))->db; 1656 #if 0 1657 db[ldesc].db.desc.depend = 1658 vtophys(((struct fwohcidb_tr *) 1659 (chunk->start))->db) | dbch->ndesc; 1660 #else 1661 db[ldesc].db.desc.depend |= dbch->ndesc; 1662 #endif 1663 } 1664 STAILQ_REMOVE_HEAD(&ir->stfree, link); 1665 STAILQ_INSERT_TAIL(&ir->stdma, chunk, link); 1666 prev = chunk; 1667 } 1668 splx(s); 1669 stat = OREAD(sc, OHCI_IRCTL(dmach)); 1670 if (stat & OHCI_CNTL_DMA_ACTIVE) 1671 return 0; 1672 if (stat & OHCI_CNTL_DMA_RUN) { 1673 OWRITE(sc, OHCI_IRCTLCLR(dmach), OHCI_CNTL_DMA_RUN); 1674 device_printf(sc->fc.dev, "IR DMA overrun (0x%08x)\n", stat); 1675 } 1676 1677 OWRITE(sc, OHCI_IR_MASKCLR, 1 << dmach); 1678 OWRITE(sc, OHCI_IR_STATCLR, 1 << dmach); 1679 OWRITE(sc, OHCI_IR_MASK, 1 << dmach); 1680 OWRITE(sc, OHCI_IRCTLCLR(dmach), 0xf0000000); 1681 OWRITE(sc, OHCI_IRCTL(dmach), OHCI_CNTL_ISOHDR); 1682 OWRITE(sc, OHCI_IRCMD(dmach), 1683 vtophys(((struct fwohcidb_tr *)(first->start))->db) 1684 | dbch->ndesc); 1685 OWRITE(sc, OHCI_IRCTL(dmach), OHCI_CNTL_DMA_RUN); 1686 OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_DMA_IR); 1687 return err; 1688 } 1689 1690 static int 1691 fwohci_irx_enable(struct firewire_comm *fc, int dmach) 1692 { 1693 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 1694 int err = 0; 1695 1696 if(sc->ir[dmach].xferq.flag & FWXFERQ_PACKET){ 1697 err = fwohci_irxpp_enable(fc, dmach); 1698 return err; 1699 }else{ 1700 err = fwohci_irxbuf_enable(fc, dmach); 1701 return err; 1702 } 1703 } 1704 1705 int 1706 fwohci_stop(struct fwohci_softc *sc, device_t dev) 1707 { 1708 u_int i; 1709 1710 /* Now stopping all DMA channel */ 1711 OWRITE(sc, OHCI_ARQCTLCLR, OHCI_CNTL_DMA_RUN); 1712 OWRITE(sc, OHCI_ARSCTLCLR, OHCI_CNTL_DMA_RUN); 1713 OWRITE(sc, OHCI_ATQCTLCLR, OHCI_CNTL_DMA_RUN); 1714 OWRITE(sc, OHCI_ATSCTLCLR, OHCI_CNTL_DMA_RUN); 1715 1716 for( i = 0 ; i < sc->fc.nisodma ; i ++ ){ 1717 OWRITE(sc, OHCI_IRCTLCLR(i), OHCI_CNTL_DMA_RUN); 1718 OWRITE(sc, OHCI_ITCTLCLR(i), OHCI_CNTL_DMA_RUN); 1719 } 1720 1721 /* FLUSH FIFO and reset Transmitter/Reciever */ 1722 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_RESET); 1723 1724 /* Stop interrupt */ 1725 OWRITE(sc, FWOHCI_INTMASKCLR, 1726 OHCI_INT_EN | OHCI_INT_ERR | OHCI_INT_PHY_SID 1727 | OHCI_INT_PHY_INT 1728 | OHCI_INT_DMA_ATRQ | OHCI_INT_DMA_ATRS 1729 | OHCI_INT_DMA_PRRQ | OHCI_INT_DMA_PRRS 1730 | OHCI_INT_DMA_ARRQ | OHCI_INT_DMA_ARRS 1731 | OHCI_INT_PHY_BUS_R); 1732 /* XXX Link down? Bus reset? */ 1733 return 0; 1734 } 1735 1736 int 1737 fwohci_resume(struct fwohci_softc *sc, device_t dev) 1738 { 1739 int i; 1740 1741 fwohci_reset(sc, dev); 1742 /* XXX resume isochronus receive automatically. (how about TX?) */ 1743 for(i = 0; i < sc->fc.nisodma; i ++) { 1744 if((sc->ir[i].xferq.flag & FWXFERQ_RUNNING) != 0) { 1745 device_printf(sc->fc.dev, 1746 "resume iso receive ch: %d\n", i); 1747 sc->ir[i].xferq.flag &= ~FWXFERQ_RUNNING; 1748 sc->fc.irx_enable(&sc->fc, i); 1749 } 1750 } 1751 1752 bus_generic_resume(dev); 1753 sc->fc.ibr(&sc->fc); 1754 return 0; 1755 } 1756 1757 #define ACK_ALL 1758 static void 1759 fwohci_intr_body(struct fwohci_softc *sc, u_int32_t stat, int count) 1760 { 1761 u_int32_t irstat, itstat; 1762 u_int i; 1763 struct firewire_comm *fc = (struct firewire_comm *)sc; 1764 1765 #ifdef OHCI_DEBUG 1766 if(stat & OREAD(sc, FWOHCI_INTMASK)) 1767 device_printf(fc->dev, "INTERRUPT < %s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s> 0x%08x, 0x%08x\n", 1768 stat & OHCI_INT_EN ? "DMA_EN ":"", 1769 stat & OHCI_INT_PHY_REG ? "PHY_REG ":"", 1770 stat & OHCI_INT_CYC_LONG ? "CYC_LONG ":"", 1771 stat & OHCI_INT_ERR ? "INT_ERR ":"", 1772 stat & OHCI_INT_CYC_ERR ? "CYC_ERR ":"", 1773 stat & OHCI_INT_CYC_LOST ? "CYC_LOST ":"", 1774 stat & OHCI_INT_CYC_64SECOND ? "CYC_64SECOND ":"", 1775 stat & OHCI_INT_CYC_START ? "CYC_START ":"", 1776 stat & OHCI_INT_PHY_INT ? "PHY_INT ":"", 1777 stat & OHCI_INT_PHY_BUS_R ? "BUS_RESET ":"", 1778 stat & OHCI_INT_PHY_SID ? "SID ":"", 1779 stat & OHCI_INT_LR_ERR ? "DMA_LR_ERR ":"", 1780 stat & OHCI_INT_PW_ERR ? "DMA_PW_ERR ":"", 1781 stat & OHCI_INT_DMA_IR ? "DMA_IR ":"", 1782 stat & OHCI_INT_DMA_IT ? "DMA_IT " :"", 1783 stat & OHCI_INT_DMA_PRRS ? "DMA_PRRS " :"", 1784 stat & OHCI_INT_DMA_PRRQ ? "DMA_PRRQ " :"", 1785 stat & OHCI_INT_DMA_ARRS ? "DMA_ARRS " :"", 1786 stat & OHCI_INT_DMA_ARRQ ? "DMA_ARRQ " :"", 1787 stat & OHCI_INT_DMA_ATRS ? "DMA_ATRS " :"", 1788 stat & OHCI_INT_DMA_ATRQ ? "DMA_ATRQ " :"", 1789 stat, OREAD(sc, FWOHCI_INTMASK) 1790 ); 1791 #endif 1792 /* Bus reset */ 1793 if(stat & OHCI_INT_PHY_BUS_R ){ 1794 if (fc->status == FWBUSRESET) 1795 goto busresetout; 1796 /* Disable bus reset interrupt until sid recv. */ 1797 OWRITE(sc, FWOHCI_INTMASKCLR, OHCI_INT_PHY_BUS_R); 1798 1799 device_printf(fc->dev, "BUS reset\n"); 1800 OWRITE(sc, FWOHCI_INTMASKCLR, OHCI_INT_CYC_LOST); 1801 OWRITE(sc, OHCI_LNKCTLCLR, OHCI_CNTL_CYCSRC); 1802 1803 OWRITE(sc, OHCI_ATQCTLCLR, OHCI_CNTL_DMA_RUN); 1804 sc->atrq.xferq.flag &= ~FWXFERQ_RUNNING; 1805 OWRITE(sc, OHCI_ATSCTLCLR, OHCI_CNTL_DMA_RUN); 1806 sc->atrs.xferq.flag &= ~FWXFERQ_RUNNING; 1807 1808 #ifndef ACK_ALL 1809 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_PHY_BUS_R); 1810 #endif 1811 fw_busreset(fc); 1812 } 1813 busresetout: 1814 if((stat & OHCI_INT_DMA_IR )){ 1815 #ifndef ACK_ALL 1816 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_IR); 1817 #endif 1818 irstat = OREAD(sc, OHCI_IR_STAT); 1819 OWRITE(sc, OHCI_IR_STATCLR, irstat); 1820 for(i = 0; i < fc->nisodma ; i++){ 1821 struct fwohci_dbch *dbch; 1822 1823 if((irstat & (1 << i)) != 0){ 1824 dbch = &sc->ir[i]; 1825 if ((dbch->xferq.flag & FWXFERQ_OPEN) == 0) { 1826 device_printf(sc->fc.dev, 1827 "dma(%d) not active\n", i); 1828 continue; 1829 } 1830 if (dbch->xferq.flag & FWXFERQ_PACKET) { 1831 fwohci_ircv(sc, dbch, count); 1832 } else { 1833 fwohci_rbuf_update(sc, i); 1834 } 1835 } 1836 } 1837 } 1838 if((stat & OHCI_INT_DMA_IT )){ 1839 #ifndef ACK_ALL 1840 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_IT); 1841 #endif 1842 itstat = OREAD(sc, OHCI_IT_STAT); 1843 OWRITE(sc, OHCI_IT_STATCLR, itstat); 1844 for(i = 0; i < fc->nisodma ; i++){ 1845 if((itstat & (1 << i)) != 0){ 1846 fwohci_tbuf_update(sc, i); 1847 } 1848 } 1849 } 1850 if((stat & OHCI_INT_DMA_PRRS )){ 1851 #ifndef ACK_ALL 1852 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_PRRS); 1853 #endif 1854 #if 0 1855 dump_dma(sc, ARRS_CH); 1856 dump_db(sc, ARRS_CH); 1857 #endif 1858 fwohci_arcv(sc, &sc->arrs, count); 1859 } 1860 if((stat & OHCI_INT_DMA_PRRQ )){ 1861 #ifndef ACK_ALL 1862 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_PRRQ); 1863 #endif 1864 #if 0 1865 dump_dma(sc, ARRQ_CH); 1866 dump_db(sc, ARRQ_CH); 1867 #endif 1868 fwohci_arcv(sc, &sc->arrq, count); 1869 } 1870 if(stat & OHCI_INT_PHY_SID){ 1871 caddr_t buf; 1872 int plen; 1873 1874 #ifndef ACK_ALL 1875 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_PHY_SID); 1876 #endif 1877 /* Enable bus reset interrupt */ 1878 OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_PHY_BUS_R); 1879 /* Allow async. request to us */ 1880 OWRITE(sc, OHCI_AREQHI, 1 << 31); 1881 /* XXX insecure ?? */ 1882 OWRITE(sc, OHCI_PREQHI, 0x7fffffff); 1883 OWRITE(sc, OHCI_PREQLO, 0xffffffff); 1884 OWRITE(sc, OHCI_PREQUPPER, 0x10000); 1885 /* 1886 ** Checking whether the node is root or not. If root, turn on 1887 ** cycle master. 1888 */ 1889 device_printf(fc->dev, "node_id = 0x%08x, ", OREAD(sc, FWOHCI_NODEID)); 1890 if(!(OREAD(sc, FWOHCI_NODEID) & OHCI_NODE_VALID)){ 1891 printf("Bus reset failure\n"); 1892 goto sidout; 1893 } 1894 if( OREAD(sc, FWOHCI_NODEID) & OHCI_NODE_ROOT ){ 1895 printf("CYCLEMASTER mode\n"); 1896 OWRITE(sc, OHCI_LNKCTL, 1897 OHCI_CNTL_CYCMTR | OHCI_CNTL_CYCTIMER); 1898 }else{ 1899 printf("non CYCLEMASTER mode\n"); 1900 OWRITE(sc, OHCI_LNKCTLCLR, OHCI_CNTL_CYCMTR); 1901 OWRITE(sc, OHCI_LNKCTL, OHCI_CNTL_CYCTIMER); 1902 } 1903 fc->nodeid = OREAD(sc, FWOHCI_NODEID) & 0x3f; 1904 1905 plen = OREAD(sc, OHCI_SID_CNT) & OHCI_SID_CNT_MASK; 1906 if (plen < 4 || plen > OHCI_SIDSIZE) { 1907 device_printf(fc->dev, "invalid SID len = %d\n", plen); 1908 goto sidout; 1909 } 1910 plen -= 4; /* chop control info */ 1911 buf = malloc(OHCI_SIDSIZE, M_FW, M_NOWAIT); 1912 if(buf == NULL) goto sidout; 1913 bcopy((void *)(uintptr_t)(volatile void *)(fc->sid_buf + 1), 1914 buf, plen); 1915 #if 1 1916 /* pending all pre-bus_reset packets */ 1917 fwohci_txd(sc, &sc->atrq); 1918 fwohci_txd(sc, &sc->atrs); 1919 fwohci_arcv(sc, &sc->arrs, -1); 1920 fwohci_arcv(sc, &sc->arrq, -1); 1921 fw_drain_txq(fc); 1922 #endif 1923 fw_sidrcv(fc, buf, plen, 0); 1924 } 1925 sidout: 1926 if((stat & OHCI_INT_DMA_ATRQ )){ 1927 #ifndef ACK_ALL 1928 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_ATRQ); 1929 #endif 1930 fwohci_txd(sc, &(sc->atrq)); 1931 } 1932 if((stat & OHCI_INT_DMA_ATRS )){ 1933 #ifndef ACK_ALL 1934 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_ATRS); 1935 #endif 1936 fwohci_txd(sc, &(sc->atrs)); 1937 } 1938 if((stat & OHCI_INT_PW_ERR )){ 1939 #ifndef ACK_ALL 1940 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_PW_ERR); 1941 #endif 1942 device_printf(fc->dev, "posted write error\n"); 1943 } 1944 if((stat & OHCI_INT_ERR )){ 1945 #ifndef ACK_ALL 1946 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_ERR); 1947 #endif 1948 device_printf(fc->dev, "unrecoverable error\n"); 1949 } 1950 if((stat & OHCI_INT_PHY_INT)) { 1951 #ifndef ACK_ALL 1952 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_PHY_INT); 1953 #endif 1954 device_printf(fc->dev, "phy int\n"); 1955 } 1956 1957 return; 1958 } 1959 1960 void 1961 fwohci_intr(void *arg) 1962 { 1963 struct fwohci_softc *sc = (struct fwohci_softc *)arg; 1964 u_int32_t stat, bus_reset = 0; 1965 1966 if (!(sc->intmask & OHCI_INT_EN)) { 1967 /* polling mode */ 1968 return; 1969 } 1970 1971 while ((stat = OREAD(sc, FWOHCI_INTSTAT)) != 0) { 1972 if (stat == 0xffffffff) { 1973 device_printf(sc->fc.dev, 1974 "device physically ejected?\n"); 1975 return; 1976 } 1977 #ifdef ACK_ALL 1978 OWRITE(sc, FWOHCI_INTSTATCLR, stat); 1979 #endif 1980 /* We cannot clear bus reset event during bus reset phase */ 1981 if ((stat & ~bus_reset) == 0) 1982 return; 1983 bus_reset = stat & OHCI_INT_PHY_BUS_R; 1984 fwohci_intr_body(sc, stat, -1); 1985 } 1986 } 1987 1988 static void 1989 fwohci_poll(struct firewire_comm *fc, int quick, int count) 1990 { 1991 int s; 1992 u_int32_t stat; 1993 struct fwohci_softc *sc; 1994 1995 1996 sc = (struct fwohci_softc *)fc; 1997 stat = OHCI_INT_DMA_IR | OHCI_INT_DMA_IT | 1998 OHCI_INT_DMA_PRRS | OHCI_INT_DMA_PRRQ | 1999 OHCI_INT_DMA_ATRQ | OHCI_INT_DMA_ATRS; 2000 #if 0 2001 if (!quick) { 2002 #else 2003 if (1) { 2004 #endif 2005 stat = OREAD(sc, FWOHCI_INTSTAT); 2006 if (stat == 0) 2007 return; 2008 if (stat == 0xffffffff) { 2009 device_printf(sc->fc.dev, 2010 "device physically ejected?\n"); 2011 return; 2012 } 2013 #ifdef ACK_ALL 2014 OWRITE(sc, FWOHCI_INTSTATCLR, stat); 2015 #endif 2016 } 2017 s = splfw(); 2018 fwohci_intr_body(sc, stat, count); 2019 splx(s); 2020 } 2021 2022 static void 2023 fwohci_set_intr(struct firewire_comm *fc, int enable) 2024 { 2025 struct fwohci_softc *sc; 2026 2027 sc = (struct fwohci_softc *)fc; 2028 if (bootverbose) 2029 device_printf(sc->fc.dev, "fwohci_set_intr: %d\n", enable); 2030 if (enable) { 2031 sc->intmask |= OHCI_INT_EN; 2032 OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_EN); 2033 } else { 2034 sc->intmask &= ~OHCI_INT_EN; 2035 OWRITE(sc, FWOHCI_INTMASKCLR, OHCI_INT_EN); 2036 } 2037 } 2038 2039 static void 2040 fwohci_tbuf_update(struct fwohci_softc *sc, int dmach) 2041 { 2042 struct firewire_comm *fc = &sc->fc; 2043 volatile struct fwohcidb *db; 2044 struct fw_bulkxfer *chunk; 2045 struct fw_xferq *it; 2046 u_int32_t stat, count; 2047 int s, w=0; 2048 2049 it = fc->it[dmach]; 2050 s = splfw(); /* unnecessary ? */ 2051 while ((chunk = STAILQ_FIRST(&it->stdma)) != NULL) { 2052 db = ((struct fwohcidb_tr *)(chunk->end))->db; 2053 stat = db[sc->it[dmach].ndesc - 1].db.desc.status; 2054 db = ((struct fwohcidb_tr *)(chunk->start))->db; 2055 count = db[sc->it[dmach].ndesc - 1].db.desc.count; 2056 if (stat == 0) 2057 break; 2058 STAILQ_REMOVE_HEAD(&it->stdma, link); 2059 switch (stat & FWOHCIEV_MASK){ 2060 case FWOHCIEV_ACKCOMPL: 2061 #if 0 2062 device_printf(fc->dev, "0x%08x\n", count); 2063 #endif 2064 break; 2065 default: 2066 device_printf(fc->dev, 2067 "Isochronous transmit err %02x\n", stat); 2068 } 2069 STAILQ_INSERT_TAIL(&it->stfree, chunk, link); 2070 w++; 2071 } 2072 splx(s); 2073 if (w) 2074 wakeup(it); 2075 } 2076 2077 static void 2078 fwohci_rbuf_update(struct fwohci_softc *sc, int dmach) 2079 { 2080 struct firewire_comm *fc = &sc->fc; 2081 volatile struct fwohcidb *db; 2082 struct fw_bulkxfer *chunk; 2083 struct fw_xferq *ir; 2084 u_int32_t stat; 2085 int s, w=0; 2086 2087 ir = fc->ir[dmach]; 2088 s = splfw(); 2089 while ((chunk = STAILQ_FIRST(&ir->stdma)) != NULL) { 2090 db = ((struct fwohcidb_tr *)(chunk->end))->db; 2091 stat = db[sc->ir[dmach].ndesc - 1].db.desc.status; 2092 if (stat == 0) 2093 break; 2094 STAILQ_REMOVE_HEAD(&ir->stdma, link); 2095 STAILQ_INSERT_TAIL(&ir->stvalid, chunk, link); 2096 switch (stat & FWOHCIEV_MASK) { 2097 case FWOHCIEV_ACKCOMPL: 2098 chunk->resp = 0; 2099 break; 2100 default: 2101 chunk->resp = EINVAL; 2102 device_printf(fc->dev, 2103 "Isochronous receive err %02x\n", stat); 2104 } 2105 w++; 2106 } 2107 splx(s); 2108 if (w) { 2109 if (ir->flag & FWXFERQ_HANDLER) 2110 ir->hand(ir); 2111 else 2112 wakeup(ir); 2113 } 2114 } 2115 2116 void 2117 dump_dma(struct fwohci_softc *sc, u_int32_t ch) 2118 { 2119 u_int32_t off, cntl, stat, cmd, match; 2120 2121 if(ch == 0){ 2122 off = OHCI_ATQOFF; 2123 }else if(ch == 1){ 2124 off = OHCI_ATSOFF; 2125 }else if(ch == 2){ 2126 off = OHCI_ARQOFF; 2127 }else if(ch == 3){ 2128 off = OHCI_ARSOFF; 2129 }else if(ch < IRX_CH){ 2130 off = OHCI_ITCTL(ch - ITX_CH); 2131 }else{ 2132 off = OHCI_IRCTL(ch - IRX_CH); 2133 } 2134 cntl = stat = OREAD(sc, off); 2135 cmd = OREAD(sc, off + 0xc); 2136 match = OREAD(sc, off + 0x10); 2137 2138 device_printf(sc->fc.dev, "dma ch %1x:dma regs 0x%08x 0x%08x 0x%08x 0x%08x \n", 2139 ch, 2140 cntl, 2141 stat, 2142 cmd, 2143 match); 2144 stat &= 0xffff ; 2145 if(stat & 0xff00){ 2146 device_printf(sc->fc.dev, "dma %d ch:%s%s%s%s%s%s %s(%x)\n", 2147 ch, 2148 stat & OHCI_CNTL_DMA_RUN ? "RUN," : "", 2149 stat & OHCI_CNTL_DMA_WAKE ? "WAKE," : "", 2150 stat & OHCI_CNTL_DMA_DEAD ? "DEAD," : "", 2151 stat & OHCI_CNTL_DMA_ACTIVE ? "ACTIVE," : "", 2152 stat & OHCI_CNTL_DMA_BT ? "BRANCH," : "", 2153 stat & OHCI_CNTL_DMA_BAD ? "BADDMA," : "", 2154 fwohcicode[stat & 0x1f], 2155 stat & 0x1f 2156 ); 2157 }else{ 2158 device_printf(sc->fc.dev, "dma %d ch: Nostat\n", ch); 2159 } 2160 } 2161 2162 void 2163 dump_db(struct fwohci_softc *sc, u_int32_t ch) 2164 { 2165 struct fwohci_dbch *dbch; 2166 struct fwohcidb_tr *cp = NULL, *pp, *np; 2167 volatile struct fwohcidb *curr = NULL, *prev, *next = NULL; 2168 int idb, jdb; 2169 u_int32_t cmd, off; 2170 if(ch == 0){ 2171 off = OHCI_ATQOFF; 2172 dbch = &sc->atrq; 2173 }else if(ch == 1){ 2174 off = OHCI_ATSOFF; 2175 dbch = &sc->atrs; 2176 }else if(ch == 2){ 2177 off = OHCI_ARQOFF; 2178 dbch = &sc->arrq; 2179 }else if(ch == 3){ 2180 off = OHCI_ARSOFF; 2181 dbch = &sc->arrs; 2182 }else if(ch < IRX_CH){ 2183 off = OHCI_ITCTL(ch - ITX_CH); 2184 dbch = &sc->it[ch - ITX_CH]; 2185 }else { 2186 off = OHCI_IRCTL(ch - IRX_CH); 2187 dbch = &sc->ir[ch - IRX_CH]; 2188 } 2189 cmd = OREAD(sc, off + 0xc); 2190 2191 if( dbch->ndb == 0 ){ 2192 device_printf(sc->fc.dev, "No DB is attached ch=%d\n", ch); 2193 return; 2194 } 2195 pp = dbch->top; 2196 prev = pp->db; 2197 for(idb = 0 ; idb < dbch->ndb ; idb ++ ){ 2198 if(pp == NULL){ 2199 curr = NULL; 2200 goto outdb; 2201 } 2202 cp = STAILQ_NEXT(pp, link); 2203 if(cp == NULL){ 2204 curr = NULL; 2205 goto outdb; 2206 } 2207 np = STAILQ_NEXT(cp, link); 2208 if(cp == NULL) break; 2209 for(jdb = 0 ; jdb < dbch->ndesc ; jdb ++ ){ 2210 if((cmd & 0xfffffff0) 2211 == vtophys(&(cp->db[jdb]))){ 2212 curr = cp->db; 2213 if(np != NULL){ 2214 next = np->db; 2215 }else{ 2216 next = NULL; 2217 } 2218 goto outdb; 2219 } 2220 } 2221 pp = STAILQ_NEXT(pp, link); 2222 prev = pp->db; 2223 } 2224 outdb: 2225 if( curr != NULL){ 2226 printf("Prev DB %d\n", ch); 2227 print_db(prev, ch, dbch->ndesc); 2228 printf("Current DB %d\n", ch); 2229 print_db(curr, ch, dbch->ndesc); 2230 printf("Next DB %d\n", ch); 2231 print_db(next, ch, dbch->ndesc); 2232 }else{ 2233 printf("dbdump err ch = %d cmd = 0x%08x\n", ch, cmd); 2234 } 2235 return; 2236 } 2237 2238 void 2239 print_db(volatile struct fwohcidb *db, u_int32_t ch, u_int32_t max) 2240 { 2241 fwohcireg_t stat; 2242 int i, key; 2243 2244 if(db == NULL){ 2245 printf("No Descriptor is found\n"); 2246 return; 2247 } 2248 2249 printf("ch = %d\n%8s %s %s %s %s %4s %8s %8s %4s:%4s\n", 2250 ch, 2251 "Current", 2252 "OP ", 2253 "KEY", 2254 "INT", 2255 "BR ", 2256 "len", 2257 "Addr", 2258 "Depend", 2259 "Stat", 2260 "Cnt"); 2261 for( i = 0 ; i <= max ; i ++){ 2262 key = db[i].db.desc.control & OHCI_KEY_MASK; 2263 #if __FreeBSD_version >= 500000 2264 printf("%08tx %s %s %s %s %5d %08x %08x %04x:%04x", 2265 #else 2266 printf("%08x %s %s %s %s %5d %08x %08x %04x:%04x", 2267 #endif 2268 vtophys(&db[i]), 2269 dbcode[(db[i].db.desc.control >> 12) & 0xf], 2270 dbkey[(db[i].db.desc.control >> 8) & 0x7], 2271 dbcond[(db[i].db.desc.control >> 4) & 0x3], 2272 dbcond[(db[i].db.desc.control >> 2) & 0x3], 2273 db[i].db.desc.reqcount, 2274 db[i].db.desc.addr, 2275 db[i].db.desc.depend, 2276 db[i].db.desc.status, 2277 db[i].db.desc.count); 2278 stat = db[i].db.desc.status; 2279 if(stat & 0xff00){ 2280 printf(" %s%s%s%s%s%s %s(%x)\n", 2281 stat & OHCI_CNTL_DMA_RUN ? "RUN," : "", 2282 stat & OHCI_CNTL_DMA_WAKE ? "WAKE," : "", 2283 stat & OHCI_CNTL_DMA_DEAD ? "DEAD," : "", 2284 stat & OHCI_CNTL_DMA_ACTIVE ? "ACTIVE," : "", 2285 stat & OHCI_CNTL_DMA_BT ? "BRANCH," : "", 2286 stat & OHCI_CNTL_DMA_BAD ? "BADDMA," : "", 2287 fwohcicode[stat & 0x1f], 2288 stat & 0x1f 2289 ); 2290 }else{ 2291 printf(" Nostat\n"); 2292 } 2293 if(key == OHCI_KEY_ST2 ){ 2294 printf("0x%08x 0x%08x 0x%08x 0x%08x\n", 2295 db[i+1].db.immed[0], 2296 db[i+1].db.immed[1], 2297 db[i+1].db.immed[2], 2298 db[i+1].db.immed[3]); 2299 } 2300 if(key == OHCI_KEY_DEVICE){ 2301 return; 2302 } 2303 if((db[i].db.desc.control & OHCI_BRANCH_MASK) 2304 == OHCI_BRANCH_ALWAYS){ 2305 return; 2306 } 2307 if((db[i].db.desc.control & OHCI_CMD_MASK) 2308 == OHCI_OUTPUT_LAST){ 2309 return; 2310 } 2311 if((db[i].db.desc.control & OHCI_CMD_MASK) 2312 == OHCI_INPUT_LAST){ 2313 return; 2314 } 2315 if(key == OHCI_KEY_ST2 ){ 2316 i++; 2317 } 2318 } 2319 return; 2320 } 2321 2322 void 2323 fwohci_ibr(struct firewire_comm *fc) 2324 { 2325 struct fwohci_softc *sc; 2326 u_int32_t fun; 2327 2328 device_printf(fc->dev, "Initiate bus reset\n"); 2329 sc = (struct fwohci_softc *)fc; 2330 2331 /* 2332 * Set root hold-off bit so that non cyclemaster capable node 2333 * shouldn't became the root node. 2334 */ 2335 #if 1 2336 fun = fwphy_rddata(sc, FW_PHY_IBR_REG); 2337 fun |= FW_PHY_IBR | FW_PHY_RHB; 2338 fun = fwphy_wrdata(sc, FW_PHY_IBR_REG, fun); 2339 #else /* Short bus reset */ 2340 fun = fwphy_rddata(sc, FW_PHY_ISBR_REG); 2341 fun |= FW_PHY_ISBR | FW_PHY_RHB; 2342 fun = fwphy_wrdata(sc, FW_PHY_ISBR_REG, fun); 2343 #endif 2344 } 2345 2346 void 2347 fwohci_txbufdb(struct fwohci_softc *sc, int dmach, struct fw_bulkxfer *bulkxfer) 2348 { 2349 struct fwohcidb_tr *db_tr, *fdb_tr; 2350 struct fwohci_dbch *dbch; 2351 volatile struct fwohcidb *db; 2352 struct fw_pkt *fp; 2353 volatile struct fwohci_txpkthdr *ohcifp; 2354 unsigned short chtag; 2355 int idb; 2356 2357 dbch = &sc->it[dmach]; 2358 chtag = sc->it[dmach].xferq.flag & 0xff; 2359 2360 db_tr = (struct fwohcidb_tr *)(bulkxfer->start); 2361 fdb_tr = (struct fwohcidb_tr *)(bulkxfer->end); 2362 /* 2363 device_printf(sc->fc.dev, "DB %08x %08x %08x\n", bulkxfer, vtophys(db_tr->db), vtophys(fdb_tr->db)); 2364 */ 2365 for( idb = 0 ; idb < bulkxfer->npacket ; idb ++){ 2366 db = db_tr->db; 2367 #if 0 2368 db[0].db.desc.control 2369 = OHCI_OUTPUT_MORE | OHCI_KEY_ST2; 2370 db[0].db.desc.reqcount = 8; 2371 #endif 2372 fp = (struct fw_pkt *)db_tr->buf; 2373 ohcifp = (volatile struct fwohci_txpkthdr *) db[1].db.immed; 2374 ohcifp->mode.ld[0] = ntohl(fp->mode.ld[0]); 2375 ohcifp->mode.stream.len = ntohs(fp->mode.stream.len); 2376 ohcifp->mode.stream.chtag = chtag; 2377 ohcifp->mode.stream.tcode = 0xa; 2378 ohcifp->mode.stream.spd = 0; 2379 2380 db[2].db.desc.reqcount = ntohs(fp->mode.stream.len); 2381 db[2].db.desc.status = 0; 2382 db[2].db.desc.count = 0; 2383 #if 0 /* if bulkxfer->npackets changes */ 2384 db[2].db.desc.control = OHCI_OUTPUT_LAST 2385 | OHCI_UPDATE 2386 | OHCI_BRANCH_ALWAYS; 2387 db[0].db.desc.depend = 2388 = db[dbch->ndesc - 1].db.desc.depend 2389 = vtophys(STAILQ_NEXT(db_tr, link)->db) | dbch->ndesc; 2390 #else 2391 db[0].db.desc.depend |= dbch->ndesc; 2392 db[dbch->ndesc - 1].db.desc.depend |= dbch->ndesc; 2393 #endif 2394 bulkxfer->end = (caddr_t)db_tr; 2395 db_tr = STAILQ_NEXT(db_tr, link); 2396 } 2397 db = ((struct fwohcidb_tr *)bulkxfer->end)->db; 2398 db[0].db.desc.depend &= ~0xf; 2399 db[dbch->ndesc - 1].db.desc.depend &= ~0xf; 2400 #if 0 /* if bulkxfer->npackets changes */ 2401 db[dbch->ndesc - 1].db.desc.control |= OHCI_INTERRUPT_ALWAYS; 2402 /* OHCI 1.1 and above */ 2403 db[0].db.desc.control |= OHCI_INTERRUPT_ALWAYS; 2404 #endif 2405 /* 2406 db_tr = (struct fwohcidb_tr *)bulkxfer->start; 2407 fdb_tr = (struct fwohcidb_tr *)bulkxfer->end; 2408 device_printf(sc->fc.dev, "DB %08x %3d %08x %08x\n", bulkxfer, bulkxfer->npacket, vtophys(db_tr->db), vtophys(fdb_tr->db)); 2409 */ 2410 return; 2411 } 2412 2413 static int 2414 fwohci_add_tx_buf(struct fwohcidb_tr *db_tr, unsigned short size, 2415 int mode, void *buf) 2416 { 2417 volatile struct fwohcidb *db = db_tr->db; 2418 int err = 0; 2419 if(buf == 0){ 2420 err = EINVAL; 2421 return err; 2422 } 2423 db_tr->buf = buf; 2424 db_tr->dbcnt = 3; 2425 db_tr->dummy = NULL; 2426 2427 db[0].db.desc.control = OHCI_OUTPUT_MORE | OHCI_KEY_ST2; 2428 db[0].db.desc.reqcount = 8; 2429 db[2].db.desc.addr = vtophys(buf) + sizeof(u_int32_t); 2430 db[2].db.desc.control = 2431 OHCI_OUTPUT_LAST | OHCI_UPDATE | OHCI_BRANCH_ALWAYS; 2432 #if 1 2433 db[0].db.desc.status = 0; 2434 db[0].db.desc.count = 0; 2435 db[2].db.desc.status = 0; 2436 db[2].db.desc.count = 0; 2437 #endif 2438 if( mode & FWXFERQ_STREAM ){ 2439 if(mode & FWXFERQ_PACKET ){ 2440 db[2].db.desc.control |= OHCI_INTERRUPT_ALWAYS; 2441 } 2442 } else { 2443 printf("fwohci_add_tx_buf: who calls me?"); 2444 } 2445 return 1; 2446 } 2447 2448 int 2449 fwohci_add_rx_buf(struct fwohcidb_tr *db_tr, unsigned short size, int mode, 2450 void *buf, void *dummy) 2451 { 2452 volatile struct fwohcidb *db = db_tr->db; 2453 int i; 2454 void *dbuf[2]; 2455 int dsiz[2]; 2456 2457 if(buf == 0){ 2458 buf = malloc(size, M_FW, M_NOWAIT); 2459 if(buf == NULL) return 0; 2460 db_tr->buf = buf; 2461 db_tr->dbcnt = 1; 2462 db_tr->dummy = NULL; 2463 dsiz[0] = size; 2464 dbuf[0] = buf; 2465 }else if(dummy == NULL){ 2466 db_tr->buf = buf; 2467 db_tr->dbcnt = 1; 2468 db_tr->dummy = NULL; 2469 dsiz[0] = size; 2470 dbuf[0] = buf; 2471 }else{ 2472 db_tr->buf = buf; 2473 db_tr->dbcnt = 2; 2474 db_tr->dummy = dummy; 2475 dsiz[0] = sizeof(u_int32_t); 2476 dsiz[1] = size; 2477 dbuf[0] = dummy; 2478 dbuf[1] = buf; 2479 } 2480 for(i = 0 ; i < db_tr->dbcnt ; i++){ 2481 db[i].db.desc.addr = vtophys(dbuf[i]) ; 2482 db[i].db.desc.control = OHCI_INPUT_MORE; 2483 db[i].db.desc.reqcount = dsiz[i]; 2484 if( mode & FWXFERQ_STREAM ){ 2485 db[i].db.desc.control |= OHCI_UPDATE; 2486 } 2487 db[i].db.desc.status = 0; 2488 db[i].db.desc.count = dsiz[i]; 2489 } 2490 if( mode & FWXFERQ_STREAM ){ 2491 db[db_tr->dbcnt - 1].db.desc.control |= OHCI_INPUT_LAST; 2492 if(mode & FWXFERQ_PACKET ){ 2493 db[db_tr->dbcnt - 1].db.desc.control 2494 |= OHCI_INTERRUPT_ALWAYS; 2495 } 2496 } 2497 db[db_tr->dbcnt - 1].db.desc.control |= OHCI_BRANCH_ALWAYS; 2498 return 1; 2499 } 2500 2501 static void 2502 fwohci_ircv(struct fwohci_softc *sc, struct fwohci_dbch *dbch, int count) 2503 { 2504 struct fwohcidb_tr *db_tr = dbch->top, *odb_tr; 2505 struct firewire_comm *fc = (struct firewire_comm *)sc; 2506 int z = 1; 2507 struct fw_pkt *fp; 2508 u_int8_t *ld; 2509 u_int32_t off = NULL; 2510 u_int32_t stat; 2511 u_int32_t *qld; 2512 u_int32_t reg; 2513 u_int spd; 2514 u_int dmach; 2515 int len, i, plen; 2516 caddr_t buf; 2517 2518 for(dmach = 0 ; dmach < sc->fc.nisodma ; dmach++){ 2519 if( &sc->ir[dmach] == dbch){ 2520 off = OHCI_IROFF(dmach); 2521 break; 2522 } 2523 } 2524 if(off == NULL){ 2525 return; 2526 } 2527 if(!(dbch->xferq.flag & FWXFERQ_RUNNING)){ 2528 fwohci_irx_disable(&sc->fc, dmach); 2529 return; 2530 } 2531 2532 odb_tr = NULL; 2533 db_tr = dbch->top; 2534 i = 0; 2535 while ((reg = db_tr->db[0].db.desc.status) & 0x1f) { 2536 if (count >= 0 && count-- == 0) 2537 break; 2538 ld = (u_int8_t *)db_tr->buf; 2539 if (dbch->xferq.flag & FWXFERQ_PACKET) { 2540 /* skip timeStamp */ 2541 ld += sizeof(struct fwohci_trailer); 2542 } 2543 qld = (u_int32_t *)ld; 2544 len = dbch->xferq.psize - (db_tr->db[0].db.desc.count); 2545 /* 2546 { 2547 device_printf(sc->fc.dev, "%04x %2x 0x%08x 0x%08x 0x%08x 0x%08x\n", len, 2548 db_tr->db[0].db.desc.status & 0x1f, qld[0],qld[1],qld[2],qld[3]); 2549 } 2550 */ 2551 fp=(struct fw_pkt *)ld; 2552 qld[0] = htonl(qld[0]); 2553 plen = sizeof(struct fw_isohdr) 2554 + ntohs(fp->mode.stream.len) + sizeof(u_int32_t); 2555 ld += plen; 2556 len -= plen; 2557 buf = db_tr->buf; 2558 db_tr->buf = NULL; 2559 stat = reg & 0x1f; 2560 spd = reg & 0x3; 2561 switch(stat){ 2562 case FWOHCIEV_ACKCOMPL: 2563 case FWOHCIEV_ACKPEND: 2564 fw_rcv(&sc->fc, buf, plen - sizeof(u_int32_t), dmach, sizeof(u_int32_t), spd); 2565 break; 2566 default: 2567 free(buf, M_FW); 2568 device_printf(sc->fc.dev, "Isochronous receive err %02x\n", stat); 2569 break; 2570 } 2571 i++; 2572 fwohci_add_rx_buf(db_tr, dbch->xferq.psize, 2573 dbch->xferq.flag, 0, NULL); 2574 db_tr->db[0].db.desc.depend &= ~0xf; 2575 if(dbch->pdb_tr != NULL){ 2576 dbch->pdb_tr->db[0].db.desc.depend |= z; 2577 } else { 2578 /* XXX should be rewritten in better way */ 2579 dbch->bottom->db[0].db.desc.depend |= z; 2580 } 2581 dbch->pdb_tr = db_tr; 2582 db_tr = STAILQ_NEXT(db_tr, link); 2583 } 2584 dbch->top = db_tr; 2585 reg = OREAD(sc, OHCI_DMACTL(off)); 2586 if (reg & OHCI_CNTL_DMA_ACTIVE) 2587 return; 2588 device_printf(sc->fc.dev, "IR DMA %d stopped at %x status=%x (%d)\n", 2589 dmach, OREAD(sc, OHCI_DMACMD(off)), reg, i); 2590 dbch->top = db_tr; 2591 fwohci_irx_enable(fc, dmach); 2592 } 2593 2594 #define PLEN(x) roundup2(ntohs(x), sizeof(u_int32_t)) 2595 static int 2596 fwohci_get_plen(struct fwohci_softc *sc, struct fwohci_dbch *dbch, struct fw_pkt *fp, int hlen) 2597 { 2598 int i, r; 2599 2600 for( i = 4; i < hlen ; i+=4){ 2601 fp->mode.ld[i/4] = htonl(fp->mode.ld[i/4]); 2602 } 2603 2604 switch(fp->mode.common.tcode){ 2605 case FWTCODE_RREQQ: 2606 r = sizeof(fp->mode.rreqq) + sizeof(u_int32_t); 2607 break; 2608 case FWTCODE_WRES: 2609 r = sizeof(fp->mode.wres) + sizeof(u_int32_t); 2610 break; 2611 case FWTCODE_WREQQ: 2612 r = sizeof(fp->mode.wreqq) + sizeof(u_int32_t); 2613 break; 2614 case FWTCODE_RREQB: 2615 r = sizeof(fp->mode.rreqb) + sizeof(u_int32_t); 2616 break; 2617 case FWTCODE_RRESQ: 2618 r = sizeof(fp->mode.rresq) + sizeof(u_int32_t); 2619 break; 2620 case FWTCODE_WREQB: 2621 r = sizeof(struct fw_asyhdr) + PLEN(fp->mode.wreqb.len) 2622 + sizeof(u_int32_t); 2623 break; 2624 case FWTCODE_LREQ: 2625 r = sizeof(struct fw_asyhdr) + PLEN(fp->mode.lreq.len) 2626 + sizeof(u_int32_t); 2627 break; 2628 case FWTCODE_RRESB: 2629 r = sizeof(struct fw_asyhdr) + PLEN(fp->mode.rresb.len) 2630 + sizeof(u_int32_t); 2631 break; 2632 case FWTCODE_LRES: 2633 r = sizeof(struct fw_asyhdr) + PLEN(fp->mode.lres.len) 2634 + sizeof(u_int32_t); 2635 break; 2636 case FWOHCITCODE_PHY: 2637 r = 16; 2638 break; 2639 default: 2640 device_printf(sc->fc.dev, "Unknown tcode %d\n", 2641 fp->mode.common.tcode); 2642 r = 0; 2643 } 2644 if (r > dbch->xferq.psize) { 2645 device_printf(sc->fc.dev, "Invalid packet length %d\n", r); 2646 /* panic ? */ 2647 } 2648 return r; 2649 } 2650 2651 static void 2652 fwohci_arcv(struct fwohci_softc *sc, struct fwohci_dbch *dbch, int count) 2653 { 2654 struct fwohcidb_tr *db_tr; 2655 int z = 1; 2656 struct fw_pkt *fp; 2657 u_int8_t *ld; 2658 u_int32_t stat, off; 2659 u_int spd; 2660 int len, plen, hlen, pcnt, poff = 0, rlen; 2661 int s; 2662 caddr_t buf; 2663 int resCount; 2664 2665 if(&sc->arrq == dbch){ 2666 off = OHCI_ARQOFF; 2667 }else if(&sc->arrs == dbch){ 2668 off = OHCI_ARSOFF; 2669 }else{ 2670 return; 2671 } 2672 2673 s = splfw(); 2674 db_tr = dbch->top; 2675 pcnt = 0; 2676 /* XXX we cannot handle a packet which lies in more than two buf */ 2677 while (db_tr->db[0].db.desc.status & OHCI_CNTL_DMA_ACTIVE) { 2678 ld = (u_int8_t *)db_tr->buf + dbch->buf_offset; 2679 resCount = db_tr->db[0].db.desc.count; 2680 len = dbch->xferq.psize - resCount 2681 - dbch->buf_offset; 2682 while (len > 0 ) { 2683 if (count >= 0 && count-- == 0) 2684 goto out; 2685 if(dbch->frag.buf != NULL){ 2686 buf = dbch->frag.buf; 2687 if (dbch->frag.plen < 0) { 2688 /* incomplete header */ 2689 int hlen; 2690 2691 hlen = - dbch->frag.plen; 2692 rlen = hlen - dbch->frag.len; 2693 bcopy(ld, dbch->frag.buf + dbch->frag.len, rlen); 2694 ld += rlen; 2695 len -= rlen; 2696 dbch->frag.len += rlen; 2697 #if 0 2698 printf("(1)frag.plen=%d frag.len=%d rlen=%d len=%d\n", dbch->frag.plen, dbch->frag.len, rlen, len); 2699 #endif 2700 fp=(struct fw_pkt *)dbch->frag.buf; 2701 dbch->frag.plen 2702 = fwohci_get_plen(sc, 2703 dbch, fp, hlen); 2704 if (dbch->frag.plen == 0) 2705 goto out; 2706 } 2707 rlen = dbch->frag.plen - dbch->frag.len; 2708 #if 0 2709 printf("(2)frag.plen=%d frag.len=%d rlen=%d len=%d\n", dbch->frag.plen, dbch->frag.len, rlen, len); 2710 #endif 2711 bcopy(ld, dbch->frag.buf + dbch->frag.len, 2712 rlen); 2713 ld += rlen; 2714 len -= rlen; 2715 plen = dbch->frag.plen; 2716 dbch->frag.buf = NULL; 2717 dbch->frag.plen = 0; 2718 dbch->frag.len = 0; 2719 poff = 0; 2720 }else{ 2721 fp=(struct fw_pkt *)ld; 2722 fp->mode.ld[0] = htonl(fp->mode.ld[0]); 2723 switch(fp->mode.common.tcode){ 2724 case FWTCODE_RREQQ: 2725 case FWTCODE_WRES: 2726 case FWTCODE_WREQQ: 2727 case FWTCODE_RRESQ: 2728 case FWOHCITCODE_PHY: 2729 hlen = 12; 2730 break; 2731 case FWTCODE_RREQB: 2732 case FWTCODE_WREQB: 2733 case FWTCODE_LREQ: 2734 case FWTCODE_RRESB: 2735 case FWTCODE_LRES: 2736 hlen = 16; 2737 break; 2738 default: 2739 device_printf(sc->fc.dev, "Unknown tcode %d\n", fp->mode.common.tcode); 2740 goto out; 2741 } 2742 if (len >= hlen) { 2743 plen = fwohci_get_plen(sc, 2744 dbch, fp, hlen); 2745 if (plen == 0) 2746 goto out; 2747 plen = (plen + 3) & ~3; 2748 len -= plen; 2749 } else { 2750 plen = -hlen; 2751 len -= hlen; 2752 } 2753 if(resCount > 0 || len > 0){ 2754 buf = malloc(plen, M_FW, M_NOWAIT); 2755 if(buf == NULL){ 2756 printf("cannot malloc!\n"); 2757 free(db_tr->buf, M_FW); 2758 goto out; 2759 } 2760 bcopy(ld, buf, plen); 2761 poff = 0; 2762 dbch->frag.buf = NULL; 2763 dbch->frag.plen = 0; 2764 dbch->frag.len = 0; 2765 }else if(len < 0){ 2766 dbch->frag.buf = db_tr->buf; 2767 if (plen < 0) { 2768 #if 0 2769 printf("plen < 0:" 2770 "hlen: %d len: %d\n", 2771 hlen, len); 2772 #endif 2773 dbch->frag.len = hlen + len; 2774 dbch->frag.plen = -hlen; 2775 } else { 2776 dbch->frag.len = plen + len; 2777 dbch->frag.plen = plen; 2778 } 2779 bcopy(ld, db_tr->buf, dbch->frag.len); 2780 buf = NULL; 2781 }else{ 2782 buf = db_tr->buf; 2783 poff = ld - (u_int8_t *)buf; 2784 dbch->frag.buf = NULL; 2785 dbch->frag.plen = 0; 2786 dbch->frag.len = 0; 2787 } 2788 ld += plen; 2789 } 2790 if( buf != NULL){ 2791 /* DMA result-code will be written at the tail of packet */ 2792 stat = ((struct fwohci_trailer *)(ld - sizeof(struct fwohci_trailer)))->stat; 2793 spd = (stat >> 5) & 0x3; 2794 stat &= 0x1f; 2795 switch(stat){ 2796 case FWOHCIEV_ACKPEND: 2797 #if 0 2798 printf("fwohci_arcv: ack pending..\n"); 2799 #endif 2800 /* fall through */ 2801 case FWOHCIEV_ACKCOMPL: 2802 if( poff != 0 ) 2803 bcopy(buf+poff, buf, plen - 4); 2804 fw_rcv(&sc->fc, buf, plen - sizeof(struct fwohci_trailer), 0, 0, spd); 2805 break; 2806 case FWOHCIEV_BUSRST: 2807 free(buf, M_FW); 2808 if (sc->fc.status != FWBUSRESET) 2809 printf("got BUSRST packet!?\n"); 2810 break; 2811 default: 2812 device_printf(sc->fc.dev, "Async DMA Receive error err = %02x %s\n", stat, fwohcicode[stat]); 2813 #if 0 /* XXX */ 2814 goto out; 2815 #endif 2816 break; 2817 } 2818 } 2819 pcnt ++; 2820 }; 2821 out: 2822 if (resCount == 0) { 2823 /* done on this buffer */ 2824 fwohci_add_rx_buf(db_tr, dbch->xferq.psize, 2825 dbch->xferq.flag, 0, NULL); 2826 dbch->bottom->db[0].db.desc.depend |= z; 2827 dbch->bottom = db_tr; 2828 db_tr = STAILQ_NEXT(db_tr, link); 2829 dbch->top = db_tr; 2830 dbch->buf_offset = 0; 2831 } else { 2832 dbch->buf_offset = dbch->xferq.psize - resCount; 2833 break; 2834 } 2835 /* XXX make sure DMA is not dead */ 2836 } 2837 #if 0 2838 if (pcnt < 1) 2839 printf("fwohci_arcv: no packets\n"); 2840 #endif 2841 splx(s); 2842 } 2843