xref: /freebsd/sys/dev/firewire/fwohci.c (revision a9148abd9da5db2f1c682fb17bed791845fc41c9)
1 /*-
2  * Copyright (c) 2003 Hidetoshi Shimokawa
3  * Copyright (c) 1998-2002 Katsushi Kobayashi and Hidetoshi Shimokawa
4  * All rights reserved.
5  *
6  * Redistribution and use in source and binary forms, with or without
7  * modification, are permitted provided that the following conditions
8  * are met:
9  * 1. Redistributions of source code must retain the above copyright
10  *    notice, this list of conditions and the following disclaimer.
11  * 2. Redistributions in binary form must reproduce the above copyright
12  *    notice, this list of conditions and the following disclaimer in the
13  *    documentation and/or other materials provided with the distribution.
14  * 3. All advertising materials mentioning features or use of this software
15  *    must display the acknowledgement as bellow:
16  *
17  *    This product includes software developed by K. Kobayashi and H. Shimokawa
18  *
19  * 4. The name of the author may not be used to endorse or promote products
20  *    derived from this software without specific prior written permission.
21  *
22  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
23  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
24  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
25  * DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
26  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
27  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
28  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
29  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
30  * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
31  * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
32  * POSSIBILITY OF SUCH DAMAGE.
33  *
34  * $FreeBSD$
35  *
36  */
37 
38 #define ATRQ_CH 0
39 #define ATRS_CH 1
40 #define ARRQ_CH 2
41 #define ARRS_CH 3
42 #define ITX_CH 4
43 #define IRX_CH 0x24
44 
45 #include <sys/param.h>
46 #include <sys/systm.h>
47 #include <sys/mbuf.h>
48 #include <sys/malloc.h>
49 #include <sys/sockio.h>
50 #include <sys/sysctl.h>
51 #include <sys/bus.h>
52 #include <sys/kernel.h>
53 #include <sys/conf.h>
54 #include <sys/endian.h>
55 #include <sys/kdb.h>
56 
57 #include <machine/bus.h>
58 
59 #if defined(__DragonFly__) || __FreeBSD_version < 500000
60 #include <machine/clock.h>		/* for DELAY() */
61 #endif
62 
63 #ifdef __DragonFly__
64 #include "firewire.h"
65 #include "firewirereg.h"
66 #include "fwdma.h"
67 #include "fwohcireg.h"
68 #include "fwohcivar.h"
69 #include "firewire_phy.h"
70 #else
71 #include <dev/firewire/firewire.h>
72 #include <dev/firewire/firewirereg.h>
73 #include <dev/firewire/fwdma.h>
74 #include <dev/firewire/fwohcireg.h>
75 #include <dev/firewire/fwohcivar.h>
76 #include <dev/firewire/firewire_phy.h>
77 #endif
78 
79 #undef OHCI_DEBUG
80 
81 static int nocyclemaster = 0;
82 int firewire_phydma_enable = 1;
83 SYSCTL_DECL(_hw_firewire);
84 SYSCTL_INT(_hw_firewire, OID_AUTO, nocyclemaster, CTLFLAG_RW, &nocyclemaster, 0,
85         "Do not send cycle start packets");
86 SYSCTL_INT(_hw_firewire, OID_AUTO, phydma_enable, CTLFLAG_RW,
87 	&firewire_phydma_enable, 1, "Allow physical request DMA from firewire");
88 TUNABLE_INT("hw.firewire.phydma_enable", &firewire_phydma_enable);
89 
90 static char dbcode[16][0x10]={"OUTM", "OUTL","INPM","INPL",
91 		"STOR","LOAD","NOP ","STOP",};
92 
93 static char dbkey[8][0x10]={"ST0", "ST1","ST2","ST3",
94 		"UNDEF","REG","SYS","DEV"};
95 static char dbcond[4][0x10]={"NEV","C=1", "C=0", "ALL"};
96 char fwohcicode[32][0x20]={
97 	"No stat","Undef","long","miss Ack err",
98 	"FIFO underrun","FIFO overrun","desc err", "data read err",
99 	"data write err","bus reset","timeout","tcode err",
100 	"Undef","Undef","unknown event","flushed",
101 	"Undef","ack complete","ack pend","Undef",
102 	"ack busy_X","ack busy_A","ack busy_B","Undef",
103 	"Undef","Undef","Undef","ack tardy",
104 	"Undef","ack data_err","ack type_err",""};
105 
106 #define MAX_SPEED 3
107 extern char *linkspeed[];
108 uint32_t tagbit[4] = { 1 << 28, 1 << 29, 1 << 30, 1 << 31};
109 
110 static struct tcode_info tinfo[] = {
111 /*		hdr_len block 	flag	valid_response */
112 /* 0 WREQQ  */ {16,	FWTI_REQ | FWTI_TLABEL,	FWTCODE_WRES},
113 /* 1 WREQB  */ {16,	FWTI_REQ | FWTI_TLABEL | FWTI_BLOCK_ASY, FWTCODE_WRES},
114 /* 2 WRES   */ {12,	FWTI_RES, 0xff},
115 /* 3 XXX    */ { 0,	0, 0xff},
116 /* 4 RREQQ  */ {12,	FWTI_REQ | FWTI_TLABEL, FWTCODE_RRESQ},
117 /* 5 RREQB  */ {16,	FWTI_REQ | FWTI_TLABEL, FWTCODE_RRESB},
118 /* 6 RRESQ  */ {16,	FWTI_RES, 0xff},
119 /* 7 RRESB  */ {16,	FWTI_RES | FWTI_BLOCK_ASY, 0xff},
120 /* 8 CYCS   */ { 0,	0, 0xff},
121 /* 9 LREQ   */ {16,	FWTI_REQ | FWTI_TLABEL | FWTI_BLOCK_ASY, FWTCODE_LRES},
122 /* a STREAM */ { 4,	FWTI_REQ | FWTI_BLOCK_STR, 0xff},
123 /* b LRES   */ {16,	FWTI_RES | FWTI_BLOCK_ASY, 0xff},
124 /* c XXX    */ { 0,	0, 0xff},
125 /* d XXX    */ { 0, 	0, 0xff},
126 /* e PHY    */ {12,	FWTI_REQ, 0xff},
127 /* f XXX    */ { 0,	0, 0xff}
128 };
129 
130 #define OHCI_WRITE_SIGMASK 0xffff0000
131 #define OHCI_READ_SIGMASK 0xffff0000
132 
133 #define OWRITE(sc, r, x) bus_space_write_4((sc)->bst, (sc)->bsh, (r), (x))
134 #define OREAD(sc, r) bus_space_read_4((sc)->bst, (sc)->bsh, (r))
135 
136 static void fwohci_ibr (struct firewire_comm *);
137 static void fwohci_db_init (struct fwohci_softc *, struct fwohci_dbch *);
138 static void fwohci_db_free (struct fwohci_dbch *);
139 static void fwohci_arcv (struct fwohci_softc *, struct fwohci_dbch *, int);
140 static void fwohci_txd (struct fwohci_softc *, struct fwohci_dbch *);
141 static void fwohci_start_atq (struct firewire_comm *);
142 static void fwohci_start_ats (struct firewire_comm *);
143 static void fwohci_start (struct fwohci_softc *, struct fwohci_dbch *);
144 static uint32_t fwphy_wrdata ( struct fwohci_softc *, uint32_t, uint32_t);
145 static uint32_t fwphy_rddata ( struct fwohci_softc *, uint32_t);
146 static int fwohci_rx_enable (struct fwohci_softc *, struct fwohci_dbch *);
147 static int fwohci_tx_enable (struct fwohci_softc *, struct fwohci_dbch *);
148 static int fwohci_irx_enable (struct firewire_comm *, int);
149 static int fwohci_irx_disable (struct firewire_comm *, int);
150 #if BYTE_ORDER == BIG_ENDIAN
151 static void fwohci_irx_post (struct firewire_comm *, uint32_t *);
152 #endif
153 static int fwohci_itxbuf_enable (struct firewire_comm *, int);
154 static int fwohci_itx_disable (struct firewire_comm *, int);
155 static void fwohci_timeout (void *);
156 static void fwohci_set_intr (struct firewire_comm *, int);
157 
158 static int fwohci_add_rx_buf (struct fwohci_dbch *, struct fwohcidb_tr *, int, struct fwdma_alloc *);
159 static int fwohci_add_tx_buf (struct fwohci_dbch *, struct fwohcidb_tr *, int);
160 static void	dump_db (struct fwohci_softc *, uint32_t);
161 static void 	print_db (struct fwohcidb_tr *, struct fwohcidb *, uint32_t , uint32_t);
162 static void	dump_dma (struct fwohci_softc *, uint32_t);
163 static uint32_t fwohci_cyctimer (struct firewire_comm *);
164 static void fwohci_rbuf_update (struct fwohci_softc *, int);
165 static void fwohci_tbuf_update (struct fwohci_softc *, int);
166 void fwohci_txbufdb (struct fwohci_softc *, int , struct fw_bulkxfer *);
167 static void fwohci_task_busreset(void *, int);
168 static void fwohci_task_sid(void *, int);
169 static void fwohci_task_dma(void *, int);
170 
171 /*
172  * memory allocated for DMA programs
173  */
174 #define DMA_PROG_ALLOC		(8 * PAGE_SIZE)
175 
176 #define NDB FWMAXQUEUE
177 
178 #define	OHCI_VERSION		0x00
179 #define	OHCI_ATRETRY		0x08
180 #define	OHCI_CROMHDR		0x18
181 #define	OHCI_BUS_OPT		0x20
182 #define	OHCI_BUSIRMC		(1 << 31)
183 #define	OHCI_BUSCMC		(1 << 30)
184 #define	OHCI_BUSISC		(1 << 29)
185 #define	OHCI_BUSBMC		(1 << 28)
186 #define	OHCI_BUSPMC		(1 << 27)
187 #define OHCI_BUSFNC		OHCI_BUSIRMC | OHCI_BUSCMC | OHCI_BUSISC |\
188 				OHCI_BUSBMC | OHCI_BUSPMC
189 
190 #define	OHCI_EUID_HI		0x24
191 #define	OHCI_EUID_LO		0x28
192 
193 #define	OHCI_CROMPTR		0x34
194 #define	OHCI_HCCCTL		0x50
195 #define	OHCI_HCCCTLCLR		0x54
196 #define	OHCI_AREQHI		0x100
197 #define	OHCI_AREQHICLR		0x104
198 #define	OHCI_AREQLO		0x108
199 #define	OHCI_AREQLOCLR		0x10c
200 #define	OHCI_PREQHI		0x110
201 #define	OHCI_PREQHICLR		0x114
202 #define	OHCI_PREQLO		0x118
203 #define	OHCI_PREQLOCLR		0x11c
204 #define	OHCI_PREQUPPER		0x120
205 
206 #define	OHCI_SID_BUF		0x64
207 #define	OHCI_SID_CNT		0x68
208 #define OHCI_SID_ERR		(1 << 31)
209 #define OHCI_SID_CNT_MASK	0xffc
210 
211 #define	OHCI_IT_STAT		0x90
212 #define	OHCI_IT_STATCLR		0x94
213 #define	OHCI_IT_MASK		0x98
214 #define	OHCI_IT_MASKCLR		0x9c
215 
216 #define	OHCI_IR_STAT		0xa0
217 #define	OHCI_IR_STATCLR		0xa4
218 #define	OHCI_IR_MASK		0xa8
219 #define	OHCI_IR_MASKCLR		0xac
220 
221 #define	OHCI_LNKCTL		0xe0
222 #define	OHCI_LNKCTLCLR		0xe4
223 
224 #define	OHCI_PHYACCESS		0xec
225 #define	OHCI_CYCLETIMER		0xf0
226 
227 #define	OHCI_DMACTL(off)	(off)
228 #define	OHCI_DMACTLCLR(off)	(off + 4)
229 #define	OHCI_DMACMD(off)	(off + 0xc)
230 #define	OHCI_DMAMATCH(off)	(off + 0x10)
231 
232 #define OHCI_ATQOFF		0x180
233 #define OHCI_ATQCTL		OHCI_ATQOFF
234 #define OHCI_ATQCTLCLR		(OHCI_ATQOFF + 4)
235 #define OHCI_ATQCMD		(OHCI_ATQOFF + 0xc)
236 #define OHCI_ATQMATCH		(OHCI_ATQOFF + 0x10)
237 
238 #define OHCI_ATSOFF		0x1a0
239 #define OHCI_ATSCTL		OHCI_ATSOFF
240 #define OHCI_ATSCTLCLR		(OHCI_ATSOFF + 4)
241 #define OHCI_ATSCMD		(OHCI_ATSOFF + 0xc)
242 #define OHCI_ATSMATCH		(OHCI_ATSOFF + 0x10)
243 
244 #define OHCI_ARQOFF		0x1c0
245 #define OHCI_ARQCTL		OHCI_ARQOFF
246 #define OHCI_ARQCTLCLR		(OHCI_ARQOFF + 4)
247 #define OHCI_ARQCMD		(OHCI_ARQOFF + 0xc)
248 #define OHCI_ARQMATCH		(OHCI_ARQOFF + 0x10)
249 
250 #define OHCI_ARSOFF		0x1e0
251 #define OHCI_ARSCTL		OHCI_ARSOFF
252 #define OHCI_ARSCTLCLR		(OHCI_ARSOFF + 4)
253 #define OHCI_ARSCMD		(OHCI_ARSOFF + 0xc)
254 #define OHCI_ARSMATCH		(OHCI_ARSOFF + 0x10)
255 
256 #define OHCI_ITOFF(CH)		(0x200 + 0x10 * (CH))
257 #define OHCI_ITCTL(CH)		(OHCI_ITOFF(CH))
258 #define OHCI_ITCTLCLR(CH)	(OHCI_ITOFF(CH) + 4)
259 #define OHCI_ITCMD(CH)		(OHCI_ITOFF(CH) + 0xc)
260 
261 #define OHCI_IROFF(CH)		(0x400 + 0x20 * (CH))
262 #define OHCI_IRCTL(CH)		(OHCI_IROFF(CH))
263 #define OHCI_IRCTLCLR(CH)	(OHCI_IROFF(CH) + 4)
264 #define OHCI_IRCMD(CH)		(OHCI_IROFF(CH) + 0xc)
265 #define OHCI_IRMATCH(CH)	(OHCI_IROFF(CH) + 0x10)
266 
267 d_ioctl_t fwohci_ioctl;
268 
269 /*
270  * Communication with PHY device
271  */
272 /* XXX need lock for phy access */
273 static uint32_t
274 fwphy_wrdata( struct fwohci_softc *sc, uint32_t addr, uint32_t data)
275 {
276 	uint32_t fun;
277 
278 	addr &= 0xf;
279 	data &= 0xff;
280 
281 	fun = (PHYDEV_WRCMD | (addr << PHYDEV_REGADDR) | (data << PHYDEV_WRDATA));
282 	OWRITE(sc, OHCI_PHYACCESS, fun);
283 	DELAY(100);
284 
285 	return(fwphy_rddata( sc, addr));
286 }
287 
288 static uint32_t
289 fwohci_set_bus_manager(struct firewire_comm *fc, u_int node)
290 {
291 	struct fwohci_softc *sc = (struct fwohci_softc *)fc;
292 	int i;
293 	uint32_t bm;
294 
295 #define OHCI_CSR_DATA	0x0c
296 #define OHCI_CSR_COMP	0x10
297 #define OHCI_CSR_CONT	0x14
298 #define OHCI_BUS_MANAGER_ID	0
299 
300 	OWRITE(sc, OHCI_CSR_DATA, node);
301 	OWRITE(sc, OHCI_CSR_COMP, 0x3f);
302 	OWRITE(sc, OHCI_CSR_CONT, OHCI_BUS_MANAGER_ID);
303  	for (i = 0; !(OREAD(sc, OHCI_CSR_CONT) & (1<<31)) && (i < 1000); i++)
304 		DELAY(10);
305 	bm = OREAD(sc, OHCI_CSR_DATA);
306 	if((bm & 0x3f) == 0x3f)
307 		bm = node;
308 	if (firewire_debug)
309 		device_printf(sc->fc.dev,
310 			"fw_set_bus_manager: %d->%d (loop=%d)\n", bm, node, i);
311 
312 	return(bm);
313 }
314 
315 static uint32_t
316 fwphy_rddata(struct fwohci_softc *sc,  u_int addr)
317 {
318 	uint32_t fun, stat;
319 	u_int i, retry = 0;
320 
321 	addr &= 0xf;
322 #define MAX_RETRY 100
323 again:
324 	OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_REG_FAIL);
325 	fun = PHYDEV_RDCMD | (addr << PHYDEV_REGADDR);
326 	OWRITE(sc, OHCI_PHYACCESS, fun);
327 	for ( i = 0 ; i < MAX_RETRY ; i ++ ){
328 		fun = OREAD(sc, OHCI_PHYACCESS);
329 		if ((fun & PHYDEV_RDCMD) == 0 && (fun & PHYDEV_RDDONE) != 0)
330 			break;
331 		DELAY(100);
332 	}
333 	if(i >= MAX_RETRY) {
334 		if (firewire_debug)
335 			device_printf(sc->fc.dev, "phy read failed(1).\n");
336 		if (++retry < MAX_RETRY) {
337 			DELAY(100);
338 			goto again;
339 		}
340 	}
341 	/* Make sure that SCLK is started */
342 	stat = OREAD(sc, FWOHCI_INTSTAT);
343 	if ((stat & OHCI_INT_REG_FAIL) != 0 ||
344 			((fun >> PHYDEV_REGADDR) & 0xf) != addr) {
345 		if (firewire_debug)
346 			device_printf(sc->fc.dev, "phy read failed(2).\n");
347 		if (++retry < MAX_RETRY) {
348 			DELAY(100);
349 			goto again;
350 		}
351 	}
352 	if (firewire_debug || retry >= MAX_RETRY)
353 		device_printf(sc->fc.dev,
354 		    "fwphy_rddata: 0x%x loop=%d, retry=%d\n", addr, i, retry);
355 #undef MAX_RETRY
356 	return((fun >> PHYDEV_RDDATA )& 0xff);
357 }
358 /* Device specific ioctl. */
359 int
360 fwohci_ioctl (struct cdev *dev, u_long cmd, caddr_t data, int flag, fw_proc *td)
361 {
362 	struct firewire_softc *sc;
363 	struct fwohci_softc *fc;
364 	int unit = DEV2UNIT(dev);
365 	int err = 0;
366 	struct fw_reg_req_t *reg  = (struct fw_reg_req_t *) data;
367 	uint32_t *dmach = (uint32_t *) data;
368 
369 	sc = devclass_get_softc(firewire_devclass, unit);
370 	if(sc == NULL){
371 		return(EINVAL);
372 	}
373 	fc = (struct fwohci_softc *)sc->fc;
374 
375 	if (!data)
376 		return(EINVAL);
377 
378 	switch (cmd) {
379 	case FWOHCI_WRREG:
380 #define OHCI_MAX_REG 0x800
381 		if(reg->addr <= OHCI_MAX_REG){
382 			OWRITE(fc, reg->addr, reg->data);
383 			reg->data = OREAD(fc, reg->addr);
384 		}else{
385 			err = EINVAL;
386 		}
387 		break;
388 	case FWOHCI_RDREG:
389 		if(reg->addr <= OHCI_MAX_REG){
390 			reg->data = OREAD(fc, reg->addr);
391 		}else{
392 			err = EINVAL;
393 		}
394 		break;
395 /* Read DMA descriptors for debug  */
396 	case DUMPDMA:
397 		if(*dmach <= OHCI_MAX_DMA_CH ){
398 			dump_dma(fc, *dmach);
399 			dump_db(fc, *dmach);
400 		}else{
401 			err = EINVAL;
402 		}
403 		break;
404 /* Read/Write Phy registers */
405 #define OHCI_MAX_PHY_REG 0xf
406 	case FWOHCI_RDPHYREG:
407 		if (reg->addr <= OHCI_MAX_PHY_REG)
408 			reg->data = fwphy_rddata(fc, reg->addr);
409 		else
410 			err = EINVAL;
411 		break;
412 	case FWOHCI_WRPHYREG:
413 		if (reg->addr <= OHCI_MAX_PHY_REG)
414 			reg->data = fwphy_wrdata(fc, reg->addr, reg->data);
415 		else
416 			err = EINVAL;
417 		break;
418 	default:
419 		err = EINVAL;
420 		break;
421 	}
422 	return err;
423 }
424 
425 static int
426 fwohci_probe_phy(struct fwohci_softc *sc, device_t dev)
427 {
428 	uint32_t reg, reg2;
429 	int e1394a = 1;
430 /*
431  * probe PHY parameters
432  * 0. to prove PHY version, whether compliance of 1394a.
433  * 1. to probe maximum speed supported by the PHY and
434  *    number of port supported by core-logic.
435  *    It is not actually available port on your PC .
436  */
437 	OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_LPS);
438 	DELAY(500);
439 
440 	reg = fwphy_rddata(sc, FW_PHY_SPD_REG);
441 
442 	if((reg >> 5) != 7 ){
443 		sc->fc.mode &= ~FWPHYASYST;
444 		sc->fc.nport = reg & FW_PHY_NP;
445 		sc->fc.speed = reg & FW_PHY_SPD >> 6;
446 		if (sc->fc.speed > MAX_SPEED) {
447 			device_printf(dev, "invalid speed %d (fixed to %d).\n",
448 				sc->fc.speed, MAX_SPEED);
449 			sc->fc.speed = MAX_SPEED;
450 		}
451 		device_printf(dev,
452 			"Phy 1394 only %s, %d ports.\n",
453 			linkspeed[sc->fc.speed], sc->fc.nport);
454 	}else{
455 		reg2 = fwphy_rddata(sc, FW_PHY_ESPD_REG);
456 		sc->fc.mode |= FWPHYASYST;
457 		sc->fc.nport = reg & FW_PHY_NP;
458 		sc->fc.speed = (reg2 & FW_PHY_ESPD) >> 5;
459 		if (sc->fc.speed > MAX_SPEED) {
460 			device_printf(dev, "invalid speed %d (fixed to %d).\n",
461 				sc->fc.speed, MAX_SPEED);
462 			sc->fc.speed = MAX_SPEED;
463 		}
464 		device_printf(dev,
465 			"Phy 1394a available %s, %d ports.\n",
466 			linkspeed[sc->fc.speed], sc->fc.nport);
467 
468 		/* check programPhyEnable */
469 		reg2 = fwphy_rddata(sc, 5);
470 #if 0
471 		if (e1394a && (OREAD(sc, OHCI_HCCCTL) & OHCI_HCC_PRPHY)) {
472 #else	/* XXX force to enable 1394a */
473 		if (e1394a) {
474 #endif
475 			if (firewire_debug)
476 				device_printf(dev,
477 					"Enable 1394a Enhancements\n");
478 			/* enable EAA EMC */
479 			reg2 |= 0x03;
480 			/* set aPhyEnhanceEnable */
481 			OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_PHYEN);
482 			OWRITE(sc, OHCI_HCCCTLCLR, OHCI_HCC_PRPHY);
483 		} else {
484 			/* for safe */
485 			reg2 &= ~0x83;
486 		}
487 		reg2 = fwphy_wrdata(sc, 5, reg2);
488 	}
489 
490 	reg = fwphy_rddata(sc, FW_PHY_SPD_REG);
491 	if((reg >> 5) == 7 ){
492 		reg = fwphy_rddata(sc, 4);
493 		reg |= 1 << 6;
494 		fwphy_wrdata(sc, 4, reg);
495 		reg = fwphy_rddata(sc, 4);
496 	}
497 	return 0;
498 }
499 
500 
501 void
502 fwohci_reset(struct fwohci_softc *sc, device_t dev)
503 {
504 	int i, max_rec, speed;
505 	uint32_t reg, reg2;
506 	struct fwohcidb_tr *db_tr;
507 
508 	/* Disable interrupts */
509 	OWRITE(sc, FWOHCI_INTMASKCLR, ~0);
510 
511 	/* Now stopping all DMA channels */
512 	OWRITE(sc,  OHCI_ARQCTLCLR, OHCI_CNTL_DMA_RUN);
513 	OWRITE(sc,  OHCI_ARSCTLCLR, OHCI_CNTL_DMA_RUN);
514 	OWRITE(sc,  OHCI_ATQCTLCLR, OHCI_CNTL_DMA_RUN);
515 	OWRITE(sc,  OHCI_ATSCTLCLR, OHCI_CNTL_DMA_RUN);
516 
517 	OWRITE(sc,  OHCI_IR_MASKCLR, ~0);
518 	for( i = 0 ; i < sc->fc.nisodma ; i ++ ){
519 		OWRITE(sc,  OHCI_IRCTLCLR(i), OHCI_CNTL_DMA_RUN);
520 		OWRITE(sc,  OHCI_ITCTLCLR(i), OHCI_CNTL_DMA_RUN);
521 	}
522 
523 	/* FLUSH FIFO and reset Transmitter/Reciever */
524 	OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_RESET);
525 	if (firewire_debug)
526 		device_printf(dev, "resetting OHCI...");
527 	i = 0;
528 	while(OREAD(sc, OHCI_HCCCTL) & OHCI_HCC_RESET) {
529 		if (i++ > 100) break;
530 		DELAY(1000);
531 	}
532 	if (firewire_debug)
533 		printf("done (loop=%d)\n", i);
534 
535 	/* Probe phy */
536 	fwohci_probe_phy(sc, dev);
537 
538 	/* Probe link */
539 	reg = OREAD(sc,  OHCI_BUS_OPT);
540 	reg2 = reg | OHCI_BUSFNC;
541 	max_rec = (reg & 0x0000f000) >> 12;
542 	speed = (reg & 0x00000007);
543 	device_printf(dev, "Link %s, max_rec %d bytes.\n",
544 			linkspeed[speed], MAXREC(max_rec));
545 	/* XXX fix max_rec */
546 	sc->fc.maxrec = sc->fc.speed + 8;
547 	if (max_rec != sc->fc.maxrec) {
548 		reg2 = (reg2 & 0xffff0fff) | (sc->fc.maxrec << 12);
549 		device_printf(dev, "max_rec %d -> %d\n",
550 				MAXREC(max_rec), MAXREC(sc->fc.maxrec));
551 	}
552 	if (firewire_debug)
553 		device_printf(dev, "BUS_OPT 0x%x -> 0x%x\n", reg, reg2);
554 	OWRITE(sc,  OHCI_BUS_OPT, reg2);
555 
556 	/* Initialize registers */
557 	OWRITE(sc, OHCI_CROMHDR, sc->fc.config_rom[0]);
558 	OWRITE(sc, OHCI_CROMPTR, sc->crom_dma.bus_addr);
559 	OWRITE(sc, OHCI_HCCCTLCLR, OHCI_HCC_BIGEND);
560 	OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_POSTWR);
561 	OWRITE(sc, OHCI_SID_BUF, sc->sid_dma.bus_addr);
562 	OWRITE(sc, OHCI_LNKCTL, OHCI_CNTL_SID);
563 
564 	/* Enable link */
565 	OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_LINKEN);
566 
567 	/* Force to start async RX DMA */
568 	sc->arrq.xferq.flag &= ~FWXFERQ_RUNNING;
569 	sc->arrs.xferq.flag &= ~FWXFERQ_RUNNING;
570 	fwohci_rx_enable(sc, &sc->arrq);
571 	fwohci_rx_enable(sc, &sc->arrs);
572 
573 	/* Initialize async TX */
574 	OWRITE(sc, OHCI_ATQCTLCLR, OHCI_CNTL_DMA_RUN | OHCI_CNTL_DMA_DEAD);
575 	OWRITE(sc, OHCI_ATSCTLCLR, OHCI_CNTL_DMA_RUN | OHCI_CNTL_DMA_DEAD);
576 
577 	/* AT Retries */
578 	OWRITE(sc, FWOHCI_RETRY,
579 		/* CycleLimit   PhyRespRetries ATRespRetries ATReqRetries */
580 		(0xffff << 16 ) | (0x0f << 8) | (0x0f << 4) | 0x0f) ;
581 
582 	sc->atrq.top = STAILQ_FIRST(&sc->atrq.db_trq);
583 	sc->atrs.top = STAILQ_FIRST(&sc->atrs.db_trq);
584 	sc->atrq.bottom = sc->atrq.top;
585 	sc->atrs.bottom = sc->atrs.top;
586 
587 	for( i = 0, db_tr = sc->atrq.top; i < sc->atrq.ndb ;
588 				i ++, db_tr = STAILQ_NEXT(db_tr, link)){
589 		db_tr->xfer = NULL;
590 	}
591 	for( i = 0, db_tr = sc->atrs.top; i < sc->atrs.ndb ;
592 				i ++, db_tr = STAILQ_NEXT(db_tr, link)){
593 		db_tr->xfer = NULL;
594 	}
595 
596 
597 	/* Enable interrupts */
598 	sc->intmask =  (OHCI_INT_ERR  | OHCI_INT_PHY_SID
599 			| OHCI_INT_DMA_ATRQ | OHCI_INT_DMA_ATRS
600 			| OHCI_INT_DMA_PRRQ | OHCI_INT_DMA_PRRS
601 			| OHCI_INT_PHY_BUS_R | OHCI_INT_PW_ERR);
602 	sc->intmask |=  OHCI_INT_DMA_IR | OHCI_INT_DMA_IT;
603 	sc->intmask |=	OHCI_INT_CYC_LOST | OHCI_INT_PHY_INT;
604 	OWRITE(sc, FWOHCI_INTMASK, sc->intmask);
605 	fwohci_set_intr(&sc->fc, 1);
606 
607 }
608 
609 int
610 fwohci_init(struct fwohci_softc *sc, device_t dev)
611 {
612 	int i, mver;
613 	uint32_t reg;
614 	uint8_t ui[8];
615 
616 /* OHCI version */
617 	reg = OREAD(sc, OHCI_VERSION);
618 	mver = (reg >> 16) & 0xff;
619 	device_printf(dev, "OHCI version %x.%x (ROM=%d)\n",
620 			mver, reg & 0xff, (reg>>24) & 1);
621 	if (mver < 1 || mver > 9) {
622 		device_printf(dev, "invalid OHCI version\n");
623 		return (ENXIO);
624 	}
625 
626 /* Available Isochronous DMA channel probe */
627 	OWRITE(sc, OHCI_IT_MASK, 0xffffffff);
628 	OWRITE(sc, OHCI_IR_MASK, 0xffffffff);
629 	reg = OREAD(sc, OHCI_IT_MASK) & OREAD(sc, OHCI_IR_MASK);
630 	OWRITE(sc, OHCI_IT_MASKCLR, 0xffffffff);
631 	OWRITE(sc, OHCI_IR_MASKCLR, 0xffffffff);
632 	for (i = 0; i < 0x20; i++)
633 		if ((reg & (1 << i)) == 0)
634 			break;
635 	sc->fc.nisodma = i;
636 	device_printf(dev, "No. of Isochronous channels is %d.\n", i);
637 	if (i == 0)
638 		return (ENXIO);
639 
640 	sc->fc.arq = &sc->arrq.xferq;
641 	sc->fc.ars = &sc->arrs.xferq;
642 	sc->fc.atq = &sc->atrq.xferq;
643 	sc->fc.ats = &sc->atrs.xferq;
644 
645 	sc->arrq.xferq.psize = roundup2(FWPMAX_S400, PAGE_SIZE);
646 	sc->arrs.xferq.psize = roundup2(FWPMAX_S400, PAGE_SIZE);
647 	sc->atrq.xferq.psize = roundup2(FWPMAX_S400, PAGE_SIZE);
648 	sc->atrs.xferq.psize = roundup2(FWPMAX_S400, PAGE_SIZE);
649 
650 	sc->arrq.xferq.start = NULL;
651 	sc->arrs.xferq.start = NULL;
652 	sc->atrq.xferq.start = fwohci_start_atq;
653 	sc->atrs.xferq.start = fwohci_start_ats;
654 
655 	sc->arrq.xferq.buf = NULL;
656 	sc->arrs.xferq.buf = NULL;
657 	sc->atrq.xferq.buf = NULL;
658 	sc->atrs.xferq.buf = NULL;
659 
660 	sc->arrq.xferq.dmach = -1;
661 	sc->arrs.xferq.dmach = -1;
662 	sc->atrq.xferq.dmach = -1;
663 	sc->atrs.xferq.dmach = -1;
664 
665 	sc->arrq.ndesc = 1;
666 	sc->arrs.ndesc = 1;
667 	sc->atrq.ndesc = 8;	/* equal to maximum of mbuf chains */
668 	sc->atrs.ndesc = 2;
669 
670 	sc->arrq.ndb = NDB;
671 	sc->arrs.ndb = NDB / 2;
672 	sc->atrq.ndb = NDB;
673 	sc->atrs.ndb = NDB / 2;
674 
675 	for( i = 0 ; i < sc->fc.nisodma ; i ++ ){
676 		sc->fc.it[i] = &sc->it[i].xferq;
677 		sc->fc.ir[i] = &sc->ir[i].xferq;
678 		sc->it[i].xferq.dmach = i;
679 		sc->ir[i].xferq.dmach = i;
680 		sc->it[i].ndb = 0;
681 		sc->ir[i].ndb = 0;
682 	}
683 
684 	sc->fc.tcode = tinfo;
685 	sc->fc.dev = dev;
686 
687 	sc->fc.config_rom = fwdma_malloc(&sc->fc, CROMSIZE, CROMSIZE,
688 						&sc->crom_dma, BUS_DMA_WAITOK);
689 	if(sc->fc.config_rom == NULL){
690 		device_printf(dev, "config_rom alloc failed.");
691 		return ENOMEM;
692 	}
693 
694 #if 0
695 	bzero(&sc->fc.config_rom[0], CROMSIZE);
696 	sc->fc.config_rom[1] = 0x31333934;
697 	sc->fc.config_rom[2] = 0xf000a002;
698 	sc->fc.config_rom[3] = OREAD(sc, OHCI_EUID_HI);
699 	sc->fc.config_rom[4] = OREAD(sc, OHCI_EUID_LO);
700 	sc->fc.config_rom[5] = 0;
701 	sc->fc.config_rom[0] = (4 << 24) | (5 << 16);
702 
703 	sc->fc.config_rom[0] |= fw_crc16(&sc->fc.config_rom[1], 5*4);
704 #endif
705 
706 
707 /* SID recieve buffer must align 2^11 */
708 #define	OHCI_SIDSIZE	(1 << 11)
709 	sc->sid_buf = fwdma_malloc(&sc->fc, OHCI_SIDSIZE, OHCI_SIDSIZE,
710 						&sc->sid_dma, BUS_DMA_WAITOK);
711 	if (sc->sid_buf == NULL) {
712 		device_printf(dev, "sid_buf alloc failed.");
713 		return ENOMEM;
714 	}
715 
716 	fwdma_malloc(&sc->fc, sizeof(uint32_t), sizeof(uint32_t),
717 					&sc->dummy_dma, BUS_DMA_WAITOK);
718 
719 	if (sc->dummy_dma.v_addr == NULL) {
720 		device_printf(dev, "dummy_dma alloc failed.");
721 		return ENOMEM;
722 	}
723 
724 	fwohci_db_init(sc, &sc->arrq);
725 	if ((sc->arrq.flags & FWOHCI_DBCH_INIT) == 0)
726 		return ENOMEM;
727 
728 	fwohci_db_init(sc, &sc->arrs);
729 	if ((sc->arrs.flags & FWOHCI_DBCH_INIT) == 0)
730 		return ENOMEM;
731 
732 	fwohci_db_init(sc, &sc->atrq);
733 	if ((sc->atrq.flags & FWOHCI_DBCH_INIT) == 0)
734 		return ENOMEM;
735 
736 	fwohci_db_init(sc, &sc->atrs);
737 	if ((sc->atrs.flags & FWOHCI_DBCH_INIT) == 0)
738 		return ENOMEM;
739 
740 	sc->fc.eui.hi = OREAD(sc, FWOHCIGUID_H);
741 	sc->fc.eui.lo = OREAD(sc, FWOHCIGUID_L);
742 	for( i = 0 ; i < 8 ; i ++)
743 		ui[i] = FW_EUI64_BYTE(&sc->fc.eui,i);
744 	device_printf(dev, "EUI64 %02x:%02x:%02x:%02x:%02x:%02x:%02x:%02x\n",
745 		ui[0], ui[1], ui[2], ui[3], ui[4], ui[5], ui[6], ui[7]);
746 
747 	sc->fc.ioctl = fwohci_ioctl;
748 	sc->fc.cyctimer = fwohci_cyctimer;
749 	sc->fc.set_bmr = fwohci_set_bus_manager;
750 	sc->fc.ibr = fwohci_ibr;
751 	sc->fc.irx_enable = fwohci_irx_enable;
752 	sc->fc.irx_disable = fwohci_irx_disable;
753 
754 	sc->fc.itx_enable = fwohci_itxbuf_enable;
755 	sc->fc.itx_disable = fwohci_itx_disable;
756 #if BYTE_ORDER == BIG_ENDIAN
757 	sc->fc.irx_post = fwohci_irx_post;
758 #else
759 	sc->fc.irx_post = NULL;
760 #endif
761 	sc->fc.itx_post = NULL;
762 	sc->fc.timeout = fwohci_timeout;
763 	sc->fc.poll = fwohci_poll;
764 	sc->fc.set_intr = fwohci_set_intr;
765 
766 	sc->intmask = sc->irstat = sc->itstat = 0;
767 
768 	/* Init task queue */
769 	sc->fc.taskqueue = taskqueue_create_fast("fw_taskq", M_WAITOK,
770 		taskqueue_thread_enqueue, &sc->fc.taskqueue);
771 	taskqueue_start_threads(&sc->fc.taskqueue, 1, PI_NET, "fw%d_taskq",
772 					device_get_unit(dev));
773 	TASK_INIT(&sc->fwohci_task_busreset, 2, fwohci_task_busreset, sc);
774 	TASK_INIT(&sc->fwohci_task_sid, 1, fwohci_task_sid, sc);
775 	TASK_INIT(&sc->fwohci_task_dma, 0, fwohci_task_dma, sc);
776 
777 	fw_init(&sc->fc);
778 	fwohci_reset(sc, dev);
779 
780 	return 0;
781 }
782 
783 void
784 fwohci_timeout(void *arg)
785 {
786 	struct fwohci_softc *sc;
787 
788 	sc = (struct fwohci_softc *)arg;
789 }
790 
791 uint32_t
792 fwohci_cyctimer(struct firewire_comm *fc)
793 {
794 	struct fwohci_softc *sc = (struct fwohci_softc *)fc;
795 	return(OREAD(sc, OHCI_CYCLETIMER));
796 }
797 
798 int
799 fwohci_detach(struct fwohci_softc *sc, device_t dev)
800 {
801 	int i;
802 
803 	if (sc->sid_buf != NULL)
804 		fwdma_free(&sc->fc, &sc->sid_dma);
805 	if (sc->fc.config_rom != NULL)
806 		fwdma_free(&sc->fc, &sc->crom_dma);
807 
808 	fwohci_db_free(&sc->arrq);
809 	fwohci_db_free(&sc->arrs);
810 
811 	fwohci_db_free(&sc->atrq);
812 	fwohci_db_free(&sc->atrs);
813 
814 	for( i = 0 ; i < sc->fc.nisodma ; i ++ ){
815 		fwohci_db_free(&sc->it[i]);
816 		fwohci_db_free(&sc->ir[i]);
817 	}
818 	if (sc->fc.taskqueue != NULL) {
819 		taskqueue_drain(sc->fc.taskqueue, &sc->fwohci_task_busreset);
820 		taskqueue_drain(sc->fc.taskqueue, &sc->fwohci_task_sid);
821 		taskqueue_drain(sc->fc.taskqueue, &sc->fwohci_task_dma);
822 		taskqueue_drain(sc->fc.taskqueue, &sc->fc.task_timeout);
823 		taskqueue_free(sc->fc.taskqueue);
824 		sc->fc.taskqueue = NULL;
825 	}
826 
827 	return 0;
828 }
829 
830 #define LAST_DB(dbtr, db) do {						\
831 	struct fwohcidb_tr *_dbtr = (dbtr);				\
832 	int _cnt = _dbtr->dbcnt;					\
833 	db = &_dbtr->db[ (_cnt > 2) ? (_cnt -1) : 0];			\
834 } while (0)
835 
836 static void
837 fwohci_execute_db(void *arg, bus_dma_segment_t *segs, int nseg, int error)
838 {
839 	struct fwohcidb_tr *db_tr;
840 	struct fwohcidb *db;
841 	bus_dma_segment_t *s;
842 	int i;
843 
844 	db_tr = (struct fwohcidb_tr *)arg;
845 	db = &db_tr->db[db_tr->dbcnt];
846 	if (error) {
847 		if (firewire_debug || error != EFBIG)
848 			printf("fwohci_execute_db: error=%d\n", error);
849 		return;
850 	}
851 	for (i = 0; i < nseg; i++) {
852 		s = &segs[i];
853 		FWOHCI_DMA_WRITE(db->db.desc.addr, s->ds_addr);
854 		FWOHCI_DMA_WRITE(db->db.desc.cmd, s->ds_len);
855  		FWOHCI_DMA_WRITE(db->db.desc.res, 0);
856 		db++;
857 		db_tr->dbcnt++;
858 	}
859 }
860 
861 static void
862 fwohci_execute_db2(void *arg, bus_dma_segment_t *segs, int nseg,
863 						bus_size_t size, int error)
864 {
865 	fwohci_execute_db(arg, segs, nseg, error);
866 }
867 
868 static void
869 fwohci_start(struct fwohci_softc *sc, struct fwohci_dbch *dbch)
870 {
871 	int i, s;
872 	int tcode, hdr_len, pl_off;
873 	int fsegment = -1;
874 	uint32_t off;
875 	struct fw_xfer *xfer;
876 	struct fw_pkt *fp;
877 	struct fwohci_txpkthdr *ohcifp;
878 	struct fwohcidb_tr *db_tr;
879 	struct fwohcidb *db;
880 	uint32_t *ld;
881 	struct tcode_info *info;
882 	static int maxdesc=0;
883 
884 	FW_GLOCK_ASSERT(&sc->fc);
885 
886 	if(&sc->atrq == dbch){
887 		off = OHCI_ATQOFF;
888 	}else if(&sc->atrs == dbch){
889 		off = OHCI_ATSOFF;
890 	}else{
891 		return;
892 	}
893 
894 	if (dbch->flags & FWOHCI_DBCH_FULL)
895 		return;
896 
897 	s = splfw();
898 	db_tr = dbch->top;
899 txloop:
900 	xfer = STAILQ_FIRST(&dbch->xferq.q);
901 	if(xfer == NULL){
902 		goto kick;
903 	}
904 #if 0
905 	if(dbch->xferq.queued == 0 ){
906 		device_printf(sc->fc.dev, "TX queue empty\n");
907 	}
908 #endif
909 	STAILQ_REMOVE_HEAD(&dbch->xferq.q, link);
910 	db_tr->xfer = xfer;
911 	xfer->flag = FWXF_START;
912 
913 	fp = &xfer->send.hdr;
914 	tcode = fp->mode.common.tcode;
915 
916 	ohcifp = (struct fwohci_txpkthdr *) db_tr->db[1].db.immed;
917 	info = &tinfo[tcode];
918 	hdr_len = pl_off = info->hdr_len;
919 
920 	ld = &ohcifp->mode.ld[0];
921 	ld[0] = ld[1] = ld[2] = ld[3] = 0;
922 	for( i = 0 ; i < pl_off ; i+= 4)
923 		ld[i/4] = fp->mode.ld[i/4];
924 
925 	ohcifp->mode.common.spd = xfer->send.spd & 0x7;
926 	if (tcode == FWTCODE_STREAM ){
927 		hdr_len = 8;
928 		ohcifp->mode.stream.len = fp->mode.stream.len;
929 	} else if (tcode == FWTCODE_PHY) {
930 		hdr_len = 12;
931 		ld[1] = fp->mode.ld[1];
932 		ld[2] = fp->mode.ld[2];
933 		ohcifp->mode.common.spd = 0;
934 		ohcifp->mode.common.tcode = FWOHCITCODE_PHY;
935 	} else {
936 		ohcifp->mode.asycomm.dst = fp->mode.hdr.dst;
937 		ohcifp->mode.asycomm.srcbus = OHCI_ASYSRCBUS;
938 		ohcifp->mode.asycomm.tlrt |= FWRETRY_X;
939 	}
940 	db = &db_tr->db[0];
941  	FWOHCI_DMA_WRITE(db->db.desc.cmd,
942 			OHCI_OUTPUT_MORE | OHCI_KEY_ST2 | hdr_len);
943  	FWOHCI_DMA_WRITE(db->db.desc.addr, 0);
944  	FWOHCI_DMA_WRITE(db->db.desc.res, 0);
945 /* Specify bound timer of asy. responce */
946 	if(&sc->atrs == dbch){
947  		FWOHCI_DMA_WRITE(db->db.desc.res,
948 			 (OREAD(sc, OHCI_CYCLETIMER) >> 12) + (1 << 13));
949 	}
950 #if BYTE_ORDER == BIG_ENDIAN
951 	if (tcode == FWTCODE_WREQQ || tcode == FWTCODE_RRESQ)
952 		hdr_len = 12;
953 	for (i = 0; i < hdr_len/4; i ++)
954 		FWOHCI_DMA_WRITE(ld[i], ld[i]);
955 #endif
956 
957 again:
958 	db_tr->dbcnt = 2;
959 	db = &db_tr->db[db_tr->dbcnt];
960 	if (xfer->send.pay_len > 0) {
961 		int err;
962 		/* handle payload */
963 		if (xfer->mbuf == NULL) {
964 			err = bus_dmamap_load(dbch->dmat, db_tr->dma_map,
965 				&xfer->send.payload[0], xfer->send.pay_len,
966 				fwohci_execute_db, db_tr,
967 				/*flags*/0);
968 		} else {
969 			/* XXX we can handle only 6 (=8-2) mbuf chains */
970 			err = bus_dmamap_load_mbuf(dbch->dmat, db_tr->dma_map,
971 				xfer->mbuf,
972 				fwohci_execute_db2, db_tr,
973 				/* flags */0);
974 			if (err == EFBIG) {
975 				struct mbuf *m0;
976 
977 				if (firewire_debug)
978 					device_printf(sc->fc.dev, "EFBIG.\n");
979 				m0 = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR);
980 				if (m0 != NULL) {
981 					m_copydata(xfer->mbuf, 0,
982 						xfer->mbuf->m_pkthdr.len,
983 						mtod(m0, caddr_t));
984 					m0->m_len = m0->m_pkthdr.len =
985 						xfer->mbuf->m_pkthdr.len;
986 					m_freem(xfer->mbuf);
987 					xfer->mbuf = m0;
988 					goto again;
989 				}
990 				device_printf(sc->fc.dev, "m_getcl failed.\n");
991 			}
992 		}
993 		if (err)
994 			printf("dmamap_load: err=%d\n", err);
995 		bus_dmamap_sync(dbch->dmat, db_tr->dma_map,
996 						BUS_DMASYNC_PREWRITE);
997 #if 0 /* OHCI_OUTPUT_MODE == 0 */
998 		for (i = 2; i < db_tr->dbcnt; i++)
999 			FWOHCI_DMA_SET(db_tr->db[i].db.desc.cmd,
1000 						OHCI_OUTPUT_MORE);
1001 #endif
1002 	}
1003 	if (maxdesc < db_tr->dbcnt) {
1004 		maxdesc = db_tr->dbcnt;
1005 		if (firewire_debug)
1006 			device_printf(sc->fc.dev, "maxdesc: %d\n", maxdesc);
1007 	}
1008 	/* last db */
1009 	LAST_DB(db_tr, db);
1010  	FWOHCI_DMA_SET(db->db.desc.cmd,
1011 		OHCI_OUTPUT_LAST | OHCI_INTERRUPT_ALWAYS | OHCI_BRANCH_ALWAYS);
1012  	FWOHCI_DMA_WRITE(db->db.desc.depend,
1013 			STAILQ_NEXT(db_tr, link)->bus_addr);
1014 
1015 	if(fsegment == -1 )
1016 		fsegment = db_tr->dbcnt;
1017 	if (dbch->pdb_tr != NULL) {
1018 		LAST_DB(dbch->pdb_tr, db);
1019  		FWOHCI_DMA_SET(db->db.desc.depend, db_tr->dbcnt);
1020 	}
1021 	dbch->xferq.queued ++;
1022 	dbch->pdb_tr = db_tr;
1023 	db_tr = STAILQ_NEXT(db_tr, link);
1024 	if(db_tr != dbch->bottom){
1025 		goto txloop;
1026 	} else {
1027 		device_printf(sc->fc.dev, "fwohci_start: lack of db_trq\n");
1028 		dbch->flags |= FWOHCI_DBCH_FULL;
1029 	}
1030 kick:
1031 	/* kick asy q */
1032 	fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREREAD);
1033 	fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREWRITE);
1034 
1035 	if(dbch->xferq.flag & FWXFERQ_RUNNING) {
1036 		OWRITE(sc, OHCI_DMACTL(off), OHCI_CNTL_DMA_WAKE);
1037 	} else {
1038 		if (firewire_debug)
1039 			device_printf(sc->fc.dev, "start AT DMA status=%x\n",
1040 					OREAD(sc, OHCI_DMACTL(off)));
1041 		OWRITE(sc, OHCI_DMACMD(off), dbch->top->bus_addr | fsegment);
1042 		OWRITE(sc, OHCI_DMACTL(off), OHCI_CNTL_DMA_RUN);
1043 		dbch->xferq.flag |= FWXFERQ_RUNNING;
1044 	}
1045 
1046 	dbch->top = db_tr;
1047 	splx(s);
1048 	return;
1049 }
1050 
1051 static void
1052 fwohci_start_atq(struct firewire_comm *fc)
1053 {
1054 	struct fwohci_softc *sc = (struct fwohci_softc *)fc;
1055 	FW_GLOCK(&sc->fc);
1056 	fwohci_start( sc, &(sc->atrq));
1057 	FW_GUNLOCK(&sc->fc);
1058 	return;
1059 }
1060 
1061 static void
1062 fwohci_start_ats(struct firewire_comm *fc)
1063 {
1064 	struct fwohci_softc *sc = (struct fwohci_softc *)fc;
1065 	FW_GLOCK(&sc->fc);
1066 	fwohci_start( sc, &(sc->atrs));
1067 	FW_GUNLOCK(&sc->fc);
1068 	return;
1069 }
1070 
1071 void
1072 fwohci_txd(struct fwohci_softc *sc, struct fwohci_dbch *dbch)
1073 {
1074 	int s, ch, err = 0;
1075 	struct fwohcidb_tr *tr;
1076 	struct fwohcidb *db;
1077 	struct fw_xfer *xfer;
1078 	uint32_t off;
1079 	u_int stat, status;
1080 	int	packets;
1081 	struct firewire_comm *fc = (struct firewire_comm *)sc;
1082 
1083 	if(&sc->atrq == dbch){
1084 		off = OHCI_ATQOFF;
1085 		ch = ATRQ_CH;
1086 	}else if(&sc->atrs == dbch){
1087 		off = OHCI_ATSOFF;
1088 		ch = ATRS_CH;
1089 	}else{
1090 		return;
1091 	}
1092 	s = splfw();
1093 	tr = dbch->bottom;
1094 	packets = 0;
1095 	fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_POSTREAD);
1096 	fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_POSTWRITE);
1097 	while(dbch->xferq.queued > 0){
1098 		LAST_DB(tr, db);
1099 		status = FWOHCI_DMA_READ(db->db.desc.res) >> OHCI_STATUS_SHIFT;
1100 		if(!(status & OHCI_CNTL_DMA_ACTIVE)){
1101 			if (fc->status != FWBUSINIT)
1102 				/* maybe out of order?? */
1103 				goto out;
1104 		}
1105 		bus_dmamap_sync(dbch->dmat, tr->dma_map,
1106 			BUS_DMASYNC_POSTWRITE);
1107 		bus_dmamap_unload(dbch->dmat, tr->dma_map);
1108 #if 1
1109 		if (firewire_debug > 1)
1110 			dump_db(sc, ch);
1111 #endif
1112 		if(status & OHCI_CNTL_DMA_DEAD) {
1113 			/* Stop DMA */
1114 			OWRITE(sc, OHCI_DMACTLCLR(off), OHCI_CNTL_DMA_RUN);
1115 			device_printf(sc->fc.dev, "force reset AT FIFO\n");
1116 			OWRITE(sc, OHCI_HCCCTLCLR, OHCI_HCC_LINKEN);
1117 			OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_LPS | OHCI_HCC_LINKEN);
1118 			OWRITE(sc, OHCI_DMACTLCLR(off), OHCI_CNTL_DMA_RUN);
1119 		}
1120 		stat = status & FWOHCIEV_MASK;
1121 		switch(stat){
1122 		case FWOHCIEV_ACKPEND:
1123 		case FWOHCIEV_ACKCOMPL:
1124 			err = 0;
1125 			break;
1126 		case FWOHCIEV_ACKBSA:
1127 		case FWOHCIEV_ACKBSB:
1128 		case FWOHCIEV_ACKBSX:
1129 			device_printf(sc->fc.dev, "txd err=%2x %s\n", stat, fwohcicode[stat]);
1130 			err = EBUSY;
1131 			break;
1132 		case FWOHCIEV_FLUSHED:
1133 		case FWOHCIEV_ACKTARD:
1134 			device_printf(sc->fc.dev, "txd err=%2x %s\n", stat, fwohcicode[stat]);
1135 			err = EAGAIN;
1136 			break;
1137 		case FWOHCIEV_MISSACK:
1138 		case FWOHCIEV_UNDRRUN:
1139 		case FWOHCIEV_OVRRUN:
1140 		case FWOHCIEV_DESCERR:
1141 		case FWOHCIEV_DTRDERR:
1142 		case FWOHCIEV_TIMEOUT:
1143 		case FWOHCIEV_TCODERR:
1144 		case FWOHCIEV_UNKNOWN:
1145 		case FWOHCIEV_ACKDERR:
1146 		case FWOHCIEV_ACKTERR:
1147 		default:
1148 			device_printf(sc->fc.dev, "txd err=%2x %s\n",
1149 							stat, fwohcicode[stat]);
1150 			err = EINVAL;
1151 			break;
1152 		}
1153 		if (tr->xfer != NULL) {
1154 			xfer = tr->xfer;
1155 			if (xfer->flag & FWXF_RCVD) {
1156 #if 0
1157 				if (firewire_debug)
1158 					printf("already rcvd\n");
1159 #endif
1160 				fw_xfer_done(xfer);
1161 			} else {
1162 				microtime(&xfer->tv);
1163 				xfer->flag = FWXF_SENT;
1164 				if (err == EBUSY) {
1165 					xfer->flag = FWXF_BUSY;
1166 					xfer->resp = err;
1167 					xfer->recv.pay_len = 0;
1168 					fw_xfer_done(xfer);
1169 				} else if (stat != FWOHCIEV_ACKPEND) {
1170 					if (stat != FWOHCIEV_ACKCOMPL)
1171 						xfer->flag = FWXF_SENTERR;
1172 					xfer->resp = err;
1173 					xfer->recv.pay_len = 0;
1174 					fw_xfer_done(xfer);
1175 				}
1176 			}
1177 			/*
1178 			 * The watchdog timer takes care of split
1179 			 * transcation timeout for ACKPEND case.
1180 			 */
1181 		} else {
1182 			printf("this shouldn't happen\n");
1183 		}
1184 		FW_GLOCK(fc);
1185 		dbch->xferq.queued --;
1186 		FW_GUNLOCK(fc);
1187 		tr->xfer = NULL;
1188 
1189 		packets ++;
1190 		tr = STAILQ_NEXT(tr, link);
1191 		dbch->bottom = tr;
1192 		if (dbch->bottom == dbch->top) {
1193 			/* we reaches the end of context program */
1194 			if (firewire_debug && dbch->xferq.queued > 0)
1195 				printf("queued > 0\n");
1196 			break;
1197 		}
1198 	}
1199 out:
1200 	if ((dbch->flags & FWOHCI_DBCH_FULL) && packets > 0) {
1201 		printf("make free slot\n");
1202 		dbch->flags &= ~FWOHCI_DBCH_FULL;
1203 		FW_GLOCK(fc);
1204 		fwohci_start(sc, dbch);
1205 		FW_GUNLOCK(fc);
1206 	}
1207 	splx(s);
1208 }
1209 
1210 static void
1211 fwohci_db_free(struct fwohci_dbch *dbch)
1212 {
1213 	struct fwohcidb_tr *db_tr;
1214 	int idb;
1215 
1216 	if ((dbch->flags & FWOHCI_DBCH_INIT) == 0)
1217 		return;
1218 
1219 	for(db_tr = STAILQ_FIRST(&dbch->db_trq), idb = 0; idb < dbch->ndb;
1220 			db_tr = STAILQ_NEXT(db_tr, link), idb++){
1221 		if ((dbch->xferq.flag & FWXFERQ_EXTBUF) == 0 &&
1222 					db_tr->buf != NULL) {
1223 			fwdma_free_size(dbch->dmat, db_tr->dma_map,
1224 					db_tr->buf, dbch->xferq.psize);
1225 			db_tr->buf = NULL;
1226 		} else if (db_tr->dma_map != NULL)
1227 			bus_dmamap_destroy(dbch->dmat, db_tr->dma_map);
1228 	}
1229 	dbch->ndb = 0;
1230 	db_tr = STAILQ_FIRST(&dbch->db_trq);
1231 	fwdma_free_multiseg(dbch->am);
1232 	free(db_tr, M_FW);
1233 	STAILQ_INIT(&dbch->db_trq);
1234 	dbch->flags &= ~FWOHCI_DBCH_INIT;
1235 }
1236 
1237 static void
1238 fwohci_db_init(struct fwohci_softc *sc, struct fwohci_dbch *dbch)
1239 {
1240 	int	idb;
1241 	struct fwohcidb_tr *db_tr;
1242 
1243 	if ((dbch->flags & FWOHCI_DBCH_INIT) != 0)
1244 		goto out;
1245 
1246 	/* create dma_tag for buffers */
1247 #define MAX_REQCOUNT	0xffff
1248 	if (bus_dma_tag_create(/*parent*/ sc->fc.dmat,
1249 			/*alignment*/ 1, /*boundary*/ 0,
1250 			/*lowaddr*/ BUS_SPACE_MAXADDR_32BIT,
1251 			/*highaddr*/ BUS_SPACE_MAXADDR,
1252 			/*filter*/NULL, /*filterarg*/NULL,
1253 			/*maxsize*/ dbch->xferq.psize,
1254 			/*nsegments*/ dbch->ndesc > 3 ? dbch->ndesc - 2 : 1,
1255 			/*maxsegsz*/ MAX_REQCOUNT,
1256 			/*flags*/ 0,
1257 #if defined(__FreeBSD__) && __FreeBSD_version >= 501102
1258 			/*lockfunc*/busdma_lock_mutex,
1259 			/*lockarg*/FW_GMTX(&sc->fc),
1260 #endif
1261 			&dbch->dmat))
1262 		return;
1263 
1264 	/* allocate DB entries and attach one to each DMA channels */
1265 	/* DB entry must start at 16 bytes bounary. */
1266 	STAILQ_INIT(&dbch->db_trq);
1267 	db_tr = (struct fwohcidb_tr *)
1268 		malloc(sizeof(struct fwohcidb_tr) * dbch->ndb,
1269 		M_FW, M_WAITOK | M_ZERO);
1270 	if(db_tr == NULL){
1271 		printf("fwohci_db_init: malloc(1) failed\n");
1272 		return;
1273 	}
1274 
1275 #define DB_SIZE(x) (sizeof(struct fwohcidb) * (x)->ndesc)
1276 	dbch->am = fwdma_malloc_multiseg(&sc->fc, DB_SIZE(dbch),
1277 		DB_SIZE(dbch), dbch->ndb, BUS_DMA_WAITOK);
1278 	if (dbch->am == NULL) {
1279 		printf("fwohci_db_init: fwdma_malloc_multiseg failed\n");
1280 		free(db_tr, M_FW);
1281 		return;
1282 	}
1283 	/* Attach DB to DMA ch. */
1284 	for(idb = 0 ; idb < dbch->ndb ; idb++){
1285 		db_tr->dbcnt = 0;
1286 		db_tr->db = (struct fwohcidb *)fwdma_v_addr(dbch->am, idb);
1287 		db_tr->bus_addr = fwdma_bus_addr(dbch->am, idb);
1288 		/* create dmamap for buffers */
1289 		/* XXX do we need 4bytes alignment tag? */
1290 		/* XXX don't alloc dma_map for AR */
1291 		if (bus_dmamap_create(dbch->dmat, 0, &db_tr->dma_map) != 0) {
1292 			printf("bus_dmamap_create failed\n");
1293 			dbch->flags = FWOHCI_DBCH_INIT; /* XXX fake */
1294 			fwohci_db_free(dbch);
1295 			return;
1296 		}
1297 		STAILQ_INSERT_TAIL(&dbch->db_trq, db_tr, link);
1298 		if (dbch->xferq.flag & FWXFERQ_EXTBUF) {
1299 			if (idb % dbch->xferq.bnpacket == 0)
1300 				dbch->xferq.bulkxfer[idb / dbch->xferq.bnpacket
1301 						].start = (caddr_t)db_tr;
1302 			if ((idb + 1) % dbch->xferq.bnpacket == 0)
1303 				dbch->xferq.bulkxfer[idb / dbch->xferq.bnpacket
1304 						].end = (caddr_t)db_tr;
1305 		}
1306 		db_tr++;
1307 	}
1308 	STAILQ_LAST(&dbch->db_trq, fwohcidb_tr,link)->link.stqe_next
1309 			= STAILQ_FIRST(&dbch->db_trq);
1310 out:
1311 	dbch->xferq.queued = 0;
1312 	dbch->pdb_tr = NULL;
1313 	dbch->top = STAILQ_FIRST(&dbch->db_trq);
1314 	dbch->bottom = dbch->top;
1315 	dbch->flags = FWOHCI_DBCH_INIT;
1316 }
1317 
1318 static int
1319 fwohci_itx_disable(struct firewire_comm *fc, int dmach)
1320 {
1321 	struct fwohci_softc *sc = (struct fwohci_softc *)fc;
1322 
1323 	OWRITE(sc, OHCI_ITCTLCLR(dmach),
1324 			OHCI_CNTL_DMA_RUN | OHCI_CNTL_CYCMATCH_S);
1325 	OWRITE(sc, OHCI_IT_MASKCLR, 1 << dmach);
1326 	OWRITE(sc, OHCI_IT_STATCLR, 1 << dmach);
1327 	/* XXX we cannot free buffers until the DMA really stops */
1328 	pause("fwitxd", hz);
1329 	fwohci_db_free(&sc->it[dmach]);
1330 	sc->it[dmach].xferq.flag &= ~FWXFERQ_RUNNING;
1331 	return 0;
1332 }
1333 
1334 static int
1335 fwohci_irx_disable(struct firewire_comm *fc, int dmach)
1336 {
1337 	struct fwohci_softc *sc = (struct fwohci_softc *)fc;
1338 
1339 	OWRITE(sc, OHCI_IRCTLCLR(dmach), OHCI_CNTL_DMA_RUN);
1340 	OWRITE(sc, OHCI_IR_MASKCLR, 1 << dmach);
1341 	OWRITE(sc, OHCI_IR_STATCLR, 1 << dmach);
1342 	/* XXX we cannot free buffers until the DMA really stops */
1343 	pause("fwirxd", hz);
1344 	fwohci_db_free(&sc->ir[dmach]);
1345 	sc->ir[dmach].xferq.flag &= ~FWXFERQ_RUNNING;
1346 	return 0;
1347 }
1348 
1349 #if BYTE_ORDER == BIG_ENDIAN
1350 static void
1351 fwohci_irx_post (struct firewire_comm *fc , uint32_t *qld)
1352 {
1353 	qld[0] = FWOHCI_DMA_READ(qld[0]);
1354 	return;
1355 }
1356 #endif
1357 
1358 static int
1359 fwohci_tx_enable(struct fwohci_softc *sc, struct fwohci_dbch *dbch)
1360 {
1361 	int err = 0;
1362 	int idb, z, i, dmach = 0, ldesc;
1363 	uint32_t off = 0;
1364 	struct fwohcidb_tr *db_tr;
1365 	struct fwohcidb *db;
1366 
1367 	if(!(dbch->xferq.flag & FWXFERQ_EXTBUF)){
1368 		err = EINVAL;
1369 		return err;
1370 	}
1371 	z = dbch->ndesc;
1372 	for(dmach = 0 ; dmach < sc->fc.nisodma ; dmach++){
1373 		if( &sc->it[dmach] == dbch){
1374 			off = OHCI_ITOFF(dmach);
1375 			break;
1376 		}
1377 	}
1378 	if(off == 0){
1379 		err = EINVAL;
1380 		return err;
1381 	}
1382 	if(dbch->xferq.flag & FWXFERQ_RUNNING)
1383 		return err;
1384 	dbch->xferq.flag |= FWXFERQ_RUNNING;
1385 	for( i = 0, dbch->bottom = dbch->top; i < (dbch->ndb - 1); i++){
1386 		dbch->bottom = STAILQ_NEXT(dbch->bottom, link);
1387 	}
1388 	db_tr = dbch->top;
1389 	for (idb = 0; idb < dbch->ndb; idb ++) {
1390 		fwohci_add_tx_buf(dbch, db_tr, idb);
1391 		if(STAILQ_NEXT(db_tr, link) == NULL){
1392 			break;
1393 		}
1394 		db = db_tr->db;
1395 		ldesc = db_tr->dbcnt - 1;
1396 		FWOHCI_DMA_WRITE(db[0].db.desc.depend,
1397 				STAILQ_NEXT(db_tr, link)->bus_addr | z);
1398 		db[ldesc].db.desc.depend = db[0].db.desc.depend;
1399 		if(dbch->xferq.flag & FWXFERQ_EXTBUF){
1400 			if(((idb + 1 ) % dbch->xferq.bnpacket) == 0){
1401 				FWOHCI_DMA_SET(
1402 					db[ldesc].db.desc.cmd,
1403 					OHCI_INTERRUPT_ALWAYS);
1404 				/* OHCI 1.1 and above */
1405 				FWOHCI_DMA_SET(
1406 					db[0].db.desc.cmd,
1407 					OHCI_INTERRUPT_ALWAYS);
1408 			}
1409 		}
1410 		db_tr = STAILQ_NEXT(db_tr, link);
1411 	}
1412 	FWOHCI_DMA_CLEAR(
1413 		dbch->bottom->db[dbch->bottom->dbcnt - 1].db.desc.depend, 0xf);
1414 	return err;
1415 }
1416 
1417 static int
1418 fwohci_rx_enable(struct fwohci_softc *sc, struct fwohci_dbch *dbch)
1419 {
1420 	int err = 0;
1421 	int idb, z, i, dmach = 0, ldesc;
1422 	uint32_t off = 0;
1423 	struct fwohcidb_tr *db_tr;
1424 	struct fwohcidb *db;
1425 
1426 	z = dbch->ndesc;
1427 	if(&sc->arrq == dbch){
1428 		off = OHCI_ARQOFF;
1429 	}else if(&sc->arrs == dbch){
1430 		off = OHCI_ARSOFF;
1431 	}else{
1432 		for(dmach = 0 ; dmach < sc->fc.nisodma ; dmach++){
1433 			if( &sc->ir[dmach] == dbch){
1434 				off = OHCI_IROFF(dmach);
1435 				break;
1436 			}
1437 		}
1438 	}
1439 	if(off == 0){
1440 		err = EINVAL;
1441 		return err;
1442 	}
1443 	if(dbch->xferq.flag & FWXFERQ_STREAM){
1444 		if(dbch->xferq.flag & FWXFERQ_RUNNING)
1445 			return err;
1446 	}else{
1447 		if(dbch->xferq.flag & FWXFERQ_RUNNING){
1448 			err = EBUSY;
1449 			return err;
1450 		}
1451 	}
1452 	dbch->xferq.flag |= FWXFERQ_RUNNING;
1453 	dbch->top = STAILQ_FIRST(&dbch->db_trq);
1454 	for( i = 0, dbch->bottom = dbch->top; i < (dbch->ndb - 1); i++){
1455 		dbch->bottom = STAILQ_NEXT(dbch->bottom, link);
1456 	}
1457 	db_tr = dbch->top;
1458 	for (idb = 0; idb < dbch->ndb; idb ++) {
1459 		fwohci_add_rx_buf(dbch, db_tr, idb, &sc->dummy_dma);
1460 		if (STAILQ_NEXT(db_tr, link) == NULL)
1461 			break;
1462 		db = db_tr->db;
1463 		ldesc = db_tr->dbcnt - 1;
1464 		FWOHCI_DMA_WRITE(db[ldesc].db.desc.depend,
1465 			STAILQ_NEXT(db_tr, link)->bus_addr | z);
1466 		if(dbch->xferq.flag & FWXFERQ_EXTBUF){
1467 			if(((idb + 1 ) % dbch->xferq.bnpacket) == 0){
1468 				FWOHCI_DMA_SET(
1469 					db[ldesc].db.desc.cmd,
1470 					OHCI_INTERRUPT_ALWAYS);
1471 				FWOHCI_DMA_CLEAR(
1472 					db[ldesc].db.desc.depend,
1473 					0xf);
1474 			}
1475 		}
1476 		db_tr = STAILQ_NEXT(db_tr, link);
1477 	}
1478 	FWOHCI_DMA_CLEAR(
1479 		dbch->bottom->db[db_tr->dbcnt - 1].db.desc.depend, 0xf);
1480 	dbch->buf_offset = 0;
1481 	fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREREAD);
1482 	fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREWRITE);
1483 	if(dbch->xferq.flag & FWXFERQ_STREAM){
1484 		return err;
1485 	}else{
1486 		OWRITE(sc, OHCI_DMACMD(off), dbch->top->bus_addr | z);
1487 	}
1488 	OWRITE(sc, OHCI_DMACTL(off), OHCI_CNTL_DMA_RUN);
1489 	return err;
1490 }
1491 
1492 static int
1493 fwohci_next_cycle(struct firewire_comm *fc, int cycle_now)
1494 {
1495 	int sec, cycle, cycle_match;
1496 
1497 	cycle = cycle_now & 0x1fff;
1498 	sec = cycle_now >> 13;
1499 #define CYCLE_MOD	0x10
1500 #if 1
1501 #define CYCLE_DELAY	8	/* min delay to start DMA */
1502 #else
1503 #define CYCLE_DELAY	7000	/* min delay to start DMA */
1504 #endif
1505 	cycle = cycle + CYCLE_DELAY;
1506 	if (cycle >= 8000) {
1507 		sec ++;
1508 		cycle -= 8000;
1509 	}
1510 	cycle = roundup2(cycle, CYCLE_MOD);
1511 	if (cycle >= 8000) {
1512 		sec ++;
1513 		if (cycle == 8000)
1514 			cycle = 0;
1515 		else
1516 			cycle = CYCLE_MOD;
1517 	}
1518 	cycle_match = ((sec << 13) | cycle) & 0x7ffff;
1519 
1520 	return(cycle_match);
1521 }
1522 
1523 static int
1524 fwohci_itxbuf_enable(struct firewire_comm *fc, int dmach)
1525 {
1526 	struct fwohci_softc *sc = (struct fwohci_softc *)fc;
1527 	int err = 0;
1528 	unsigned short tag, ich;
1529 	struct fwohci_dbch *dbch;
1530 	int cycle_match, cycle_now, s, ldesc;
1531 	uint32_t stat;
1532 	struct fw_bulkxfer *first, *chunk, *prev;
1533 	struct fw_xferq *it;
1534 
1535 	dbch = &sc->it[dmach];
1536 	it = &dbch->xferq;
1537 
1538 	tag = (it->flag >> 6) & 3;
1539 	ich = it->flag & 0x3f;
1540 	if ((dbch->flags & FWOHCI_DBCH_INIT) == 0) {
1541 		dbch->ndb = it->bnpacket * it->bnchunk;
1542 		dbch->ndesc = 3;
1543 		fwohci_db_init(sc, dbch);
1544 		if ((dbch->flags & FWOHCI_DBCH_INIT) == 0)
1545 			return ENOMEM;
1546 
1547 		err = fwohci_tx_enable(sc, dbch);
1548 	}
1549 	if(err)
1550 		return err;
1551 
1552 	ldesc = dbch->ndesc - 1;
1553 	s = splfw();
1554 	FW_GLOCK(fc);
1555 	prev = STAILQ_LAST(&it->stdma, fw_bulkxfer, link);
1556 	while  ((chunk = STAILQ_FIRST(&it->stvalid)) != NULL) {
1557 		struct fwohcidb *db;
1558 
1559 		fwdma_sync_multiseg(it->buf, chunk->poffset, it->bnpacket,
1560 					BUS_DMASYNC_PREWRITE);
1561 		fwohci_txbufdb(sc, dmach, chunk);
1562 		if (prev != NULL) {
1563 			db = ((struct fwohcidb_tr *)(prev->end))->db;
1564 #if 0 /* XXX necessary? */
1565 			FWOHCI_DMA_SET(db[ldesc].db.desc.cmd,
1566 						OHCI_BRANCH_ALWAYS);
1567 #endif
1568 #if 0 /* if bulkxfer->npacket changes */
1569 			db[ldesc].db.desc.depend = db[0].db.desc.depend =
1570 				((struct fwohcidb_tr *)
1571 				(chunk->start))->bus_addr | dbch->ndesc;
1572 #else
1573 			FWOHCI_DMA_SET(db[0].db.desc.depend, dbch->ndesc);
1574 			FWOHCI_DMA_SET(db[ldesc].db.desc.depend, dbch->ndesc);
1575 #endif
1576 		}
1577 		STAILQ_REMOVE_HEAD(&it->stvalid, link);
1578 		STAILQ_INSERT_TAIL(&it->stdma, chunk, link);
1579 		prev = chunk;
1580 	}
1581 	FW_GUNLOCK(fc);
1582 	fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREWRITE);
1583 	fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREREAD);
1584 	splx(s);
1585 	stat = OREAD(sc, OHCI_ITCTL(dmach));
1586 	if (firewire_debug && (stat & OHCI_CNTL_CYCMATCH_S))
1587 		printf("stat 0x%x\n", stat);
1588 
1589 	if (stat & (OHCI_CNTL_DMA_ACTIVE | OHCI_CNTL_CYCMATCH_S))
1590 		return 0;
1591 
1592 #if 0
1593 	OWRITE(sc, OHCI_ITCTLCLR(dmach), OHCI_CNTL_DMA_RUN);
1594 #endif
1595 	OWRITE(sc, OHCI_IT_MASKCLR, 1 << dmach);
1596 	OWRITE(sc, OHCI_IT_STATCLR, 1 << dmach);
1597 	OWRITE(sc, OHCI_IT_MASK, 1 << dmach);
1598 	OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_DMA_IT);
1599 
1600 	first = STAILQ_FIRST(&it->stdma);
1601 	OWRITE(sc, OHCI_ITCMD(dmach),
1602 		((struct fwohcidb_tr *)(first->start))->bus_addr | dbch->ndesc);
1603 	if (firewire_debug > 1) {
1604 		printf("fwohci_itxbuf_enable: kick 0x%08x\n", stat);
1605 #if 1
1606 		dump_dma(sc, ITX_CH + dmach);
1607 #endif
1608 	}
1609 	if ((stat & OHCI_CNTL_DMA_RUN) == 0) {
1610 #if 1
1611 		/* Don't start until all chunks are buffered */
1612 		if (STAILQ_FIRST(&it->stfree) != NULL)
1613 			goto out;
1614 #endif
1615 #if 1
1616 		/* Clear cycle match counter bits */
1617 		OWRITE(sc, OHCI_ITCTLCLR(dmach), 0xffff0000);
1618 
1619 		/* 2bit second + 13bit cycle */
1620 		cycle_now = (fc->cyctimer(fc) >> 12) & 0x7fff;
1621 		cycle_match = fwohci_next_cycle(fc, cycle_now);
1622 
1623 		OWRITE(sc, OHCI_ITCTL(dmach),
1624 				OHCI_CNTL_CYCMATCH_S | (cycle_match << 16)
1625 				| OHCI_CNTL_DMA_RUN);
1626 #else
1627 		OWRITE(sc, OHCI_ITCTL(dmach), OHCI_CNTL_DMA_RUN);
1628 #endif
1629 		if (firewire_debug > 1) {
1630 			printf("cycle_match: 0x%04x->0x%04x\n",
1631 						cycle_now, cycle_match);
1632 			dump_dma(sc, ITX_CH + dmach);
1633 			dump_db(sc, ITX_CH + dmach);
1634 		}
1635 	} else if ((stat & OHCI_CNTL_CYCMATCH_S) == 0) {
1636 		device_printf(sc->fc.dev,
1637 			"IT DMA underrun (0x%08x)\n", stat);
1638 		OWRITE(sc, OHCI_ITCTL(dmach), OHCI_CNTL_DMA_WAKE);
1639 	}
1640 out:
1641 	return err;
1642 }
1643 
1644 static int
1645 fwohci_irx_enable(struct firewire_comm *fc, int dmach)
1646 {
1647 	struct fwohci_softc *sc = (struct fwohci_softc *)fc;
1648 	int err = 0, s, ldesc;
1649 	unsigned short tag, ich;
1650 	uint32_t stat;
1651 	struct fwohci_dbch *dbch;
1652 	struct fwohcidb_tr *db_tr;
1653 	struct fw_bulkxfer *first, *prev, *chunk;
1654 	struct fw_xferq *ir;
1655 
1656 	dbch = &sc->ir[dmach];
1657 	ir = &dbch->xferq;
1658 
1659 	if ((ir->flag & FWXFERQ_RUNNING) == 0) {
1660 		tag = (ir->flag >> 6) & 3;
1661 		ich = ir->flag & 0x3f;
1662 		OWRITE(sc, OHCI_IRMATCH(dmach), tagbit[tag] | ich);
1663 
1664 		ir->queued = 0;
1665 		dbch->ndb = ir->bnpacket * ir->bnchunk;
1666 		dbch->ndesc = 2;
1667 		fwohci_db_init(sc, dbch);
1668 		if ((dbch->flags & FWOHCI_DBCH_INIT) == 0)
1669 			return ENOMEM;
1670 		err = fwohci_rx_enable(sc, dbch);
1671 	}
1672 	if(err)
1673 		return err;
1674 
1675 	first = STAILQ_FIRST(&ir->stfree);
1676 	if (first == NULL) {
1677 		device_printf(fc->dev, "IR DMA no free chunk\n");
1678 		return 0;
1679 	}
1680 
1681 	ldesc = dbch->ndesc - 1;
1682 	s = splfw();
1683 	if ((ir->flag & FWXFERQ_HANDLER) == 0)
1684 		FW_GLOCK(fc);
1685 	prev = STAILQ_LAST(&ir->stdma, fw_bulkxfer, link);
1686 	while  ((chunk = STAILQ_FIRST(&ir->stfree)) != NULL) {
1687 		struct fwohcidb *db;
1688 
1689 #if 1 /* XXX for if_fwe */
1690 		if (chunk->mbuf != NULL) {
1691 			db_tr = (struct fwohcidb_tr *)(chunk->start);
1692 			db_tr->dbcnt = 1;
1693 			err = bus_dmamap_load_mbuf(dbch->dmat, db_tr->dma_map,
1694 					chunk->mbuf, fwohci_execute_db2, db_tr,
1695 					/* flags */0);
1696  			FWOHCI_DMA_SET(db_tr->db[1].db.desc.cmd,
1697 				OHCI_UPDATE | OHCI_INPUT_LAST |
1698 				OHCI_INTERRUPT_ALWAYS | OHCI_BRANCH_ALWAYS);
1699 		}
1700 #endif
1701 		db = ((struct fwohcidb_tr *)(chunk->end))->db;
1702 		FWOHCI_DMA_WRITE(db[ldesc].db.desc.res, 0);
1703 		FWOHCI_DMA_CLEAR(db[ldesc].db.desc.depend, 0xf);
1704 		if (prev != NULL) {
1705 			db = ((struct fwohcidb_tr *)(prev->end))->db;
1706 			FWOHCI_DMA_SET(db[ldesc].db.desc.depend, dbch->ndesc);
1707 		}
1708 		STAILQ_REMOVE_HEAD(&ir->stfree, link);
1709 		STAILQ_INSERT_TAIL(&ir->stdma, chunk, link);
1710 		prev = chunk;
1711 	}
1712 	if ((ir->flag & FWXFERQ_HANDLER) == 0)
1713 		FW_GUNLOCK(fc);
1714 	fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREWRITE);
1715 	fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREREAD);
1716 	splx(s);
1717 	stat = OREAD(sc, OHCI_IRCTL(dmach));
1718 	if (stat & OHCI_CNTL_DMA_ACTIVE)
1719 		return 0;
1720 	if (stat & OHCI_CNTL_DMA_RUN) {
1721 		OWRITE(sc, OHCI_IRCTLCLR(dmach), OHCI_CNTL_DMA_RUN);
1722 		device_printf(sc->fc.dev, "IR DMA overrun (0x%08x)\n", stat);
1723 	}
1724 
1725 	if (firewire_debug)
1726 		printf("start IR DMA 0x%x\n", stat);
1727 	OWRITE(sc, OHCI_IR_MASKCLR, 1 << dmach);
1728 	OWRITE(sc, OHCI_IR_STATCLR, 1 << dmach);
1729 	OWRITE(sc, OHCI_IR_MASK, 1 << dmach);
1730 	OWRITE(sc, OHCI_IRCTLCLR(dmach), 0xf0000000);
1731 	OWRITE(sc, OHCI_IRCTL(dmach), OHCI_CNTL_ISOHDR);
1732 	OWRITE(sc, OHCI_IRCMD(dmach),
1733 		((struct fwohcidb_tr *)(first->start))->bus_addr
1734 							| dbch->ndesc);
1735 	OWRITE(sc, OHCI_IRCTL(dmach), OHCI_CNTL_DMA_RUN);
1736 	OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_DMA_IR);
1737 #if 0
1738 	dump_db(sc, IRX_CH + dmach);
1739 #endif
1740 	return err;
1741 }
1742 
1743 int
1744 fwohci_stop(struct fwohci_softc *sc, device_t dev)
1745 {
1746 	u_int i;
1747 
1748 	fwohci_set_intr(&sc->fc, 0);
1749 
1750 /* Now stopping all DMA channel */
1751 	OWRITE(sc,  OHCI_ARQCTLCLR, OHCI_CNTL_DMA_RUN);
1752 	OWRITE(sc,  OHCI_ARSCTLCLR, OHCI_CNTL_DMA_RUN);
1753 	OWRITE(sc,  OHCI_ATQCTLCLR, OHCI_CNTL_DMA_RUN);
1754 	OWRITE(sc,  OHCI_ATSCTLCLR, OHCI_CNTL_DMA_RUN);
1755 
1756 	for( i = 0 ; i < sc->fc.nisodma ; i ++ ){
1757 		OWRITE(sc,  OHCI_IRCTLCLR(i), OHCI_CNTL_DMA_RUN);
1758 		OWRITE(sc,  OHCI_ITCTLCLR(i), OHCI_CNTL_DMA_RUN);
1759 	}
1760 
1761 #if 0 /* Let dcons(4) be accessed */
1762 /* Stop interrupt */
1763 	OWRITE(sc, FWOHCI_INTMASKCLR,
1764 			OHCI_INT_EN | OHCI_INT_ERR | OHCI_INT_PHY_SID
1765 			| OHCI_INT_PHY_INT
1766 			| OHCI_INT_DMA_ATRQ | OHCI_INT_DMA_ATRS
1767 			| OHCI_INT_DMA_PRRQ | OHCI_INT_DMA_PRRS
1768 			| OHCI_INT_DMA_ARRQ | OHCI_INT_DMA_ARRS
1769 			| OHCI_INT_PHY_BUS_R);
1770 
1771 /* FLUSH FIFO and reset Transmitter/Reciever */
1772 	OWRITE(sc,  OHCI_HCCCTL, OHCI_HCC_RESET);
1773 #endif
1774 
1775 /* XXX Link down?  Bus reset? */
1776 	return 0;
1777 }
1778 
1779 int
1780 fwohci_resume(struct fwohci_softc *sc, device_t dev)
1781 {
1782 	int i;
1783 	struct fw_xferq *ir;
1784 	struct fw_bulkxfer *chunk;
1785 
1786 	fwohci_reset(sc, dev);
1787 	/* XXX resume isochronous receive automatically. (how about TX?) */
1788 	for(i = 0; i < sc->fc.nisodma; i ++) {
1789 		ir = &sc->ir[i].xferq;
1790 		if((ir->flag & FWXFERQ_RUNNING) != 0) {
1791 			device_printf(sc->fc.dev,
1792 				"resume iso receive ch: %d\n", i);
1793 			ir->flag &= ~FWXFERQ_RUNNING;
1794 			/* requeue stdma to stfree */
1795 			while((chunk = STAILQ_FIRST(&ir->stdma)) != NULL) {
1796 				STAILQ_REMOVE_HEAD(&ir->stdma, link);
1797 				STAILQ_INSERT_TAIL(&ir->stfree, chunk, link);
1798 			}
1799 			sc->fc.irx_enable(&sc->fc, i);
1800 		}
1801 	}
1802 
1803 	bus_generic_resume(dev);
1804 	sc->fc.ibr(&sc->fc);
1805 	return 0;
1806 }
1807 
1808 #ifdef OHCI_DEBUG
1809 static void
1810 fwohci_dump_intr(struct fwohci_softc *sc, uint32_t stat)
1811 {
1812 	if(stat & OREAD(sc, FWOHCI_INTMASK))
1813 		device_printf(fc->dev, "INTERRUPT < %s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s> 0x%08x, 0x%08x\n",
1814 			stat & OHCI_INT_EN ? "DMA_EN ":"",
1815 			stat & OHCI_INT_PHY_REG ? "PHY_REG ":"",
1816 			stat & OHCI_INT_CYC_LONG ? "CYC_LONG ":"",
1817 			stat & OHCI_INT_ERR ? "INT_ERR ":"",
1818 			stat & OHCI_INT_CYC_ERR ? "CYC_ERR ":"",
1819 			stat & OHCI_INT_CYC_LOST ? "CYC_LOST ":"",
1820 			stat & OHCI_INT_CYC_64SECOND ? "CYC_64SECOND ":"",
1821 			stat & OHCI_INT_CYC_START ? "CYC_START ":"",
1822 			stat & OHCI_INT_PHY_INT ? "PHY_INT ":"",
1823 			stat & OHCI_INT_PHY_BUS_R ? "BUS_RESET ":"",
1824 			stat & OHCI_INT_PHY_SID ? "SID ":"",
1825 			stat & OHCI_INT_LR_ERR ? "DMA_LR_ERR ":"",
1826 			stat & OHCI_INT_PW_ERR ? "DMA_PW_ERR ":"",
1827 			stat & OHCI_INT_DMA_IR ? "DMA_IR ":"",
1828 			stat & OHCI_INT_DMA_IT  ? "DMA_IT " :"",
1829 			stat & OHCI_INT_DMA_PRRS  ? "DMA_PRRS " :"",
1830 			stat & OHCI_INT_DMA_PRRQ  ? "DMA_PRRQ " :"",
1831 			stat & OHCI_INT_DMA_ARRS  ? "DMA_ARRS " :"",
1832 			stat & OHCI_INT_DMA_ARRQ  ? "DMA_ARRQ " :"",
1833 			stat & OHCI_INT_DMA_ATRS  ? "DMA_ATRS " :"",
1834 			stat & OHCI_INT_DMA_ATRQ  ? "DMA_ATRQ " :"",
1835 			stat, OREAD(sc, FWOHCI_INTMASK)
1836 		);
1837 }
1838 #endif
1839 static void
1840 fwohci_intr_core(struct fwohci_softc *sc, uint32_t stat, int count)
1841 {
1842 	struct firewire_comm *fc = (struct firewire_comm *)sc;
1843 	uint32_t node_id, plen;
1844 
1845 	if ((stat & OHCI_INT_PHY_BUS_R) && (fc->status != FWBUSRESET)) {
1846 		fc->status = FWBUSRESET;
1847 		/* Disable bus reset interrupt until sid recv. */
1848 		OWRITE(sc, FWOHCI_INTMASKCLR,  OHCI_INT_PHY_BUS_R);
1849 
1850 		device_printf(fc->dev, "BUS reset\n");
1851 		OWRITE(sc, FWOHCI_INTMASKCLR,  OHCI_INT_CYC_LOST);
1852 		OWRITE(sc, OHCI_LNKCTLCLR, OHCI_CNTL_CYCSRC);
1853 
1854 		OWRITE(sc,  OHCI_ATQCTLCLR, OHCI_CNTL_DMA_RUN);
1855 		sc->atrq.xferq.flag &= ~FWXFERQ_RUNNING;
1856 		OWRITE(sc,  OHCI_ATSCTLCLR, OHCI_CNTL_DMA_RUN);
1857 		sc->atrs.xferq.flag &= ~FWXFERQ_RUNNING;
1858 
1859 		if (!kdb_active)
1860 			taskqueue_enqueue(sc->fc.taskqueue, &sc->fwohci_task_busreset);
1861 	}
1862 	if (stat & OHCI_INT_PHY_SID) {
1863 		/* Enable bus reset interrupt */
1864 		OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_PHY_BUS_R);
1865 		OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_PHY_BUS_R);
1866 
1867 		/* Allow async. request to us */
1868 		OWRITE(sc, OHCI_AREQHI, 1 << 31);
1869 		if (firewire_phydma_enable) {
1870 			/* allow from all nodes */
1871 			OWRITE(sc, OHCI_PREQHI, 0x7fffffff);
1872 			OWRITE(sc, OHCI_PREQLO, 0xffffffff);
1873 			/* 0 to 4GB region */
1874 			OWRITE(sc, OHCI_PREQUPPER, 0x10000);
1875 		}
1876 		/* Set ATRetries register */
1877 		OWRITE(sc, OHCI_ATRETRY, 1<<(13+16) | 0xfff);
1878 
1879 		/*
1880 		 * Checking whether the node is root or not. If root, turn on
1881 		 * cycle master.
1882 		 */
1883 		node_id = OREAD(sc, FWOHCI_NODEID);
1884 		plen = OREAD(sc, OHCI_SID_CNT);
1885 
1886 		fc->nodeid = node_id & 0x3f;
1887 		device_printf(fc->dev, "node_id=0x%08x, gen=%d, ",
1888 			node_id, (plen >> 16) & 0xff);
1889 		if (!(node_id & OHCI_NODE_VALID)) {
1890 			printf("Bus reset failure\n");
1891 			goto sidout;
1892 		}
1893 
1894 		/* cycle timer */
1895 		sc->cycle_lost = 0;
1896 		OWRITE(sc, FWOHCI_INTMASK,  OHCI_INT_CYC_LOST);
1897 		if ((node_id & OHCI_NODE_ROOT) && !nocyclemaster) {
1898 			printf("CYCLEMASTER mode\n");
1899 			OWRITE(sc, OHCI_LNKCTL,
1900 				OHCI_CNTL_CYCMTR | OHCI_CNTL_CYCTIMER);
1901 		} else {
1902 			printf("non CYCLEMASTER mode\n");
1903 			OWRITE(sc, OHCI_LNKCTLCLR, OHCI_CNTL_CYCMTR);
1904 			OWRITE(sc, OHCI_LNKCTL, OHCI_CNTL_CYCTIMER);
1905 		}
1906 
1907 		fc->status = FWBUSINIT;
1908 
1909 		if (!kdb_active)
1910 			taskqueue_enqueue(sc->fc.taskqueue, &sc->fwohci_task_sid);
1911 	}
1912 sidout:
1913 	if ((stat & ~(OHCI_INT_PHY_BUS_R | OHCI_INT_PHY_SID)) && (!kdb_active))
1914 		taskqueue_enqueue(sc->fc.taskqueue, &sc->fwohci_task_dma);
1915 }
1916 
1917 static void
1918 fwohci_intr_dma(struct fwohci_softc *sc, uint32_t stat, int count)
1919 {
1920 	uint32_t irstat, itstat;
1921 	u_int i;
1922 	struct firewire_comm *fc = (struct firewire_comm *)sc;
1923 
1924 	if (stat & OHCI_INT_DMA_IR) {
1925 		irstat = atomic_readandclear_int(&sc->irstat);
1926 		for(i = 0; i < fc->nisodma ; i++){
1927 			struct fwohci_dbch *dbch;
1928 
1929 			if((irstat & (1 << i)) != 0){
1930 				dbch = &sc->ir[i];
1931 				if ((dbch->xferq.flag & FWXFERQ_OPEN) == 0) {
1932 					device_printf(sc->fc.dev,
1933 						"dma(%d) not active\n", i);
1934 					continue;
1935 				}
1936 				fwohci_rbuf_update(sc, i);
1937 			}
1938 		}
1939 	}
1940 	if (stat & OHCI_INT_DMA_IT) {
1941 		itstat = atomic_readandclear_int(&sc->itstat);
1942 		for(i = 0; i < fc->nisodma ; i++){
1943 			if((itstat & (1 << i)) != 0){
1944 				fwohci_tbuf_update(sc, i);
1945 			}
1946 		}
1947 	}
1948 	if (stat & OHCI_INT_DMA_PRRS) {
1949 #if 0
1950 		dump_dma(sc, ARRS_CH);
1951 		dump_db(sc, ARRS_CH);
1952 #endif
1953 		fwohci_arcv(sc, &sc->arrs, count);
1954 	}
1955 	if (stat & OHCI_INT_DMA_PRRQ) {
1956 #if 0
1957 		dump_dma(sc, ARRQ_CH);
1958 		dump_db(sc, ARRQ_CH);
1959 #endif
1960 		fwohci_arcv(sc, &sc->arrq, count);
1961 	}
1962 	if (stat & OHCI_INT_CYC_LOST) {
1963 		if (sc->cycle_lost >= 0)
1964 			sc->cycle_lost ++;
1965 		if (sc->cycle_lost > 10) {
1966 			sc->cycle_lost = -1;
1967 #if 0
1968 			OWRITE(sc, OHCI_LNKCTLCLR, OHCI_CNTL_CYCTIMER);
1969 #endif
1970 			OWRITE(sc, FWOHCI_INTMASKCLR,  OHCI_INT_CYC_LOST);
1971 			device_printf(fc->dev, "too many cycle lost, "
1972 			 "no cycle master presents?\n");
1973 		}
1974 	}
1975 	if (stat & OHCI_INT_DMA_ATRQ) {
1976 		fwohci_txd(sc, &(sc->atrq));
1977 	}
1978 	if (stat & OHCI_INT_DMA_ATRS) {
1979 		fwohci_txd(sc, &(sc->atrs));
1980 	}
1981 	if (stat & OHCI_INT_PW_ERR) {
1982 		device_printf(fc->dev, "posted write error\n");
1983 	}
1984 	if (stat & OHCI_INT_ERR) {
1985 		device_printf(fc->dev, "unrecoverable error\n");
1986 	}
1987 	if (stat & OHCI_INT_PHY_INT) {
1988 		device_printf(fc->dev, "phy int\n");
1989 	}
1990 
1991 	return;
1992 }
1993 
1994 static void
1995 fwohci_task_busreset(void *arg, int pending)
1996 {
1997 	struct fwohci_softc *sc = (struct fwohci_softc *)arg;
1998 
1999 	fw_busreset(&sc->fc, FWBUSRESET);
2000 	OWRITE(sc, OHCI_CROMHDR, ntohl(sc->fc.config_rom[0]));
2001 	OWRITE(sc, OHCI_BUS_OPT, ntohl(sc->fc.config_rom[2]));
2002 }
2003 
2004 static void
2005 fwohci_task_sid(void *arg, int pending)
2006 {
2007 	struct fwohci_softc *sc = (struct fwohci_softc *)arg;
2008 	struct firewire_comm *fc = &sc->fc;
2009 	uint32_t *buf;
2010 	int i, plen;
2011 
2012 
2013 	plen = OREAD(sc, OHCI_SID_CNT);
2014 
2015 	if (plen & OHCI_SID_ERR) {
2016 		device_printf(fc->dev, "SID Error\n");
2017 		return;
2018 	}
2019 	plen &= OHCI_SID_CNT_MASK;
2020 	if (plen < 4 || plen > OHCI_SIDSIZE) {
2021 		device_printf(fc->dev, "invalid SID len = %d\n", plen);
2022 		return;
2023 	}
2024 	plen -= 4; /* chop control info */
2025 	buf = (uint32_t *)malloc(OHCI_SIDSIZE, M_FW, M_NOWAIT);
2026 	if (buf == NULL) {
2027 		device_printf(fc->dev, "malloc failed\n");
2028 		return;
2029 	}
2030 	for (i = 0; i < plen / 4; i ++)
2031 		buf[i] = FWOHCI_DMA_READ(sc->sid_buf[i+1]);
2032 #if 1 /* XXX needed?? */
2033 	/* pending all pre-bus_reset packets */
2034 	fwohci_txd(sc, &sc->atrq);
2035 	fwohci_txd(sc, &sc->atrs);
2036 	fwohci_arcv(sc, &sc->arrs, -1);
2037 	fwohci_arcv(sc, &sc->arrq, -1);
2038 	fw_drain_txq(fc);
2039 #endif
2040 	fw_sidrcv(fc, buf, plen);
2041 	free(buf, M_FW);
2042 }
2043 
2044 static void
2045 fwohci_task_dma(void *arg, int pending)
2046 {
2047 	struct fwohci_softc *sc = (struct fwohci_softc *)arg;
2048 	uint32_t stat;
2049 
2050 again:
2051 	stat = atomic_readandclear_int(&sc->intstat);
2052 	if (stat)
2053 		fwohci_intr_dma(sc, stat, -1);
2054 	else
2055 		return;
2056 	goto again;
2057 }
2058 
2059 static int
2060 fwohci_check_stat(struct fwohci_softc *sc)
2061 {
2062 	uint32_t stat, irstat, itstat;
2063 
2064 	stat = OREAD(sc, FWOHCI_INTSTAT);
2065 	if (stat == 0xffffffff) {
2066 		device_printf(sc->fc.dev,
2067 			"device physically ejected?\n");
2068 		return (FILTER_STRAY);
2069 	}
2070 	if (stat)
2071 		OWRITE(sc, FWOHCI_INTSTATCLR, stat & ~OHCI_INT_PHY_BUS_R);
2072 
2073 	stat &= sc->intmask;
2074 	if (stat == 0)
2075 		return (FILTER_STRAY);
2076 
2077 	atomic_set_int(&sc->intstat, stat);
2078 	if (stat & OHCI_INT_DMA_IR) {
2079 		irstat = OREAD(sc, OHCI_IR_STAT);
2080 		OWRITE(sc, OHCI_IR_STATCLR, irstat);
2081 		atomic_set_int(&sc->irstat, irstat);
2082 	}
2083 	if (stat & OHCI_INT_DMA_IT) {
2084 		itstat = OREAD(sc, OHCI_IT_STAT);
2085 		OWRITE(sc, OHCI_IT_STATCLR, itstat);
2086 		atomic_set_int(&sc->itstat, itstat);
2087 	}
2088 
2089 	fwohci_intr_core(sc, stat, -1);
2090 	return (FILTER_HANDLED);
2091 }
2092 
2093 int
2094 fwohci_filt(void *arg)
2095 {
2096 	struct fwohci_softc *sc = (struct fwohci_softc *)arg;
2097 
2098 	if (!(sc->intmask & OHCI_INT_EN)) {
2099 		/* polling mode */
2100 		return (FILTER_STRAY);
2101 	}
2102 	return (fwohci_check_stat(sc));
2103 }
2104 
2105 void
2106 fwohci_intr(void *arg)
2107 {
2108 	fwohci_filt(arg);
2109 }
2110 
2111 void
2112 fwohci_poll(struct firewire_comm *fc, int quick, int count)
2113 {
2114 	struct fwohci_softc *sc = (struct fwohci_softc *)fc;
2115 	fwohci_check_stat(sc);
2116 }
2117 
2118 static void
2119 fwohci_set_intr(struct firewire_comm *fc, int enable)
2120 {
2121 	struct fwohci_softc *sc;
2122 
2123 	sc = (struct fwohci_softc *)fc;
2124 	if (firewire_debug)
2125 		device_printf(sc->fc.dev, "fwohci_set_intr: %d\n", enable);
2126 	if (enable) {
2127 		sc->intmask |= OHCI_INT_EN;
2128 		OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_EN);
2129 	} else {
2130 		sc->intmask &= ~OHCI_INT_EN;
2131 		OWRITE(sc, FWOHCI_INTMASKCLR, OHCI_INT_EN);
2132 	}
2133 }
2134 
2135 static void
2136 fwohci_tbuf_update(struct fwohci_softc *sc, int dmach)
2137 {
2138 	struct firewire_comm *fc = &sc->fc;
2139 	struct fwohcidb *db;
2140 	struct fw_bulkxfer *chunk;
2141 	struct fw_xferq *it;
2142 	uint32_t stat, count;
2143 	int s, w=0, ldesc;
2144 
2145 	it = fc->it[dmach];
2146 	ldesc = sc->it[dmach].ndesc - 1;
2147 	s = splfw(); /* unnecessary ? */
2148 	FW_GLOCK(fc);
2149 	fwdma_sync_multiseg_all(sc->it[dmach].am, BUS_DMASYNC_POSTREAD);
2150 	if (firewire_debug)
2151 		dump_db(sc, ITX_CH + dmach);
2152 	while ((chunk = STAILQ_FIRST(&it->stdma)) != NULL) {
2153 		db = ((struct fwohcidb_tr *)(chunk->end))->db;
2154 		stat = FWOHCI_DMA_READ(db[ldesc].db.desc.res)
2155 				>> OHCI_STATUS_SHIFT;
2156 		db = ((struct fwohcidb_tr *)(chunk->start))->db;
2157 		/* timestamp */
2158 		count = FWOHCI_DMA_READ(db[ldesc].db.desc.res)
2159 				& OHCI_COUNT_MASK;
2160 		if (stat == 0)
2161 			break;
2162 		STAILQ_REMOVE_HEAD(&it->stdma, link);
2163 		switch (stat & FWOHCIEV_MASK){
2164 		case FWOHCIEV_ACKCOMPL:
2165 #if 0
2166 			device_printf(fc->dev, "0x%08x\n", count);
2167 #endif
2168 			break;
2169 		default:
2170 			device_printf(fc->dev,
2171 				"Isochronous transmit err %02x(%s)\n",
2172 					stat, fwohcicode[stat & 0x1f]);
2173 		}
2174 		STAILQ_INSERT_TAIL(&it->stfree, chunk, link);
2175 		w++;
2176 	}
2177 	FW_GUNLOCK(fc);
2178 	splx(s);
2179 	if (w)
2180 		wakeup(it);
2181 }
2182 
2183 static void
2184 fwohci_rbuf_update(struct fwohci_softc *sc, int dmach)
2185 {
2186 	struct firewire_comm *fc = &sc->fc;
2187 	struct fwohcidb_tr *db_tr;
2188 	struct fw_bulkxfer *chunk;
2189 	struct fw_xferq *ir;
2190 	uint32_t stat;
2191 	int s, w = 0, ldesc;
2192 
2193 	ir = fc->ir[dmach];
2194 	ldesc = sc->ir[dmach].ndesc - 1;
2195 
2196 #if 0
2197 	dump_db(sc, dmach);
2198 #endif
2199 	s = splfw();
2200 	if ((ir->flag & FWXFERQ_HANDLER) == 0)
2201 		FW_GLOCK(fc);
2202 	fwdma_sync_multiseg_all(sc->ir[dmach].am, BUS_DMASYNC_POSTREAD);
2203 	while ((chunk = STAILQ_FIRST(&ir->stdma)) != NULL) {
2204 		db_tr = (struct fwohcidb_tr *)chunk->end;
2205 		stat = FWOHCI_DMA_READ(db_tr->db[ldesc].db.desc.res)
2206 				>> OHCI_STATUS_SHIFT;
2207 		if (stat == 0)
2208 			break;
2209 
2210 		if (chunk->mbuf != NULL) {
2211 			bus_dmamap_sync(sc->ir[dmach].dmat, db_tr->dma_map,
2212 						BUS_DMASYNC_POSTREAD);
2213 			bus_dmamap_unload(sc->ir[dmach].dmat, db_tr->dma_map);
2214 		} else if (ir->buf != NULL) {
2215 			fwdma_sync_multiseg(ir->buf, chunk->poffset,
2216 				ir->bnpacket, BUS_DMASYNC_POSTREAD);
2217 		} else {
2218 			/* XXX */
2219 			printf("fwohci_rbuf_update: this shouldn't happend\n");
2220 		}
2221 
2222 		STAILQ_REMOVE_HEAD(&ir->stdma, link);
2223 		STAILQ_INSERT_TAIL(&ir->stvalid, chunk, link);
2224 		switch (stat & FWOHCIEV_MASK) {
2225 		case FWOHCIEV_ACKCOMPL:
2226 			chunk->resp = 0;
2227 			break;
2228 		default:
2229 			chunk->resp = EINVAL;
2230 			device_printf(fc->dev,
2231 				"Isochronous receive err %02x(%s)\n",
2232 					stat, fwohcicode[stat & 0x1f]);
2233 		}
2234 		w++;
2235 	}
2236 	if ((ir->flag & FWXFERQ_HANDLER) == 0)
2237 		FW_GUNLOCK(fc);
2238 	splx(s);
2239 	if (w == 0)
2240 		return;
2241 
2242 	if (ir->flag & FWXFERQ_HANDLER)
2243 		ir->hand(ir);
2244 	else
2245 		wakeup(ir);
2246 }
2247 
2248 void
2249 dump_dma(struct fwohci_softc *sc, uint32_t ch)
2250 {
2251 	uint32_t off, cntl, stat, cmd, match;
2252 
2253 	if(ch == 0){
2254 		off = OHCI_ATQOFF;
2255 	}else if(ch == 1){
2256 		off = OHCI_ATSOFF;
2257 	}else if(ch == 2){
2258 		off = OHCI_ARQOFF;
2259 	}else if(ch == 3){
2260 		off = OHCI_ARSOFF;
2261 	}else if(ch < IRX_CH){
2262 		off = OHCI_ITCTL(ch - ITX_CH);
2263 	}else{
2264 		off = OHCI_IRCTL(ch - IRX_CH);
2265 	}
2266 	cntl = stat = OREAD(sc, off);
2267 	cmd = OREAD(sc, off + 0xc);
2268 	match = OREAD(sc, off + 0x10);
2269 
2270 	device_printf(sc->fc.dev, "ch %1x cntl:0x%08x cmd:0x%08x match:0x%08x\n",
2271 		ch,
2272 		cntl,
2273 		cmd,
2274 		match);
2275 	stat &= 0xffff ;
2276 	if (stat) {
2277 		device_printf(sc->fc.dev, "dma %d ch:%s%s%s%s%s%s %s(%x)\n",
2278 			ch,
2279 			stat & OHCI_CNTL_DMA_RUN ? "RUN," : "",
2280 			stat & OHCI_CNTL_DMA_WAKE ? "WAKE," : "",
2281 			stat & OHCI_CNTL_DMA_DEAD ? "DEAD," : "",
2282 			stat & OHCI_CNTL_DMA_ACTIVE ? "ACTIVE," : "",
2283 			stat & OHCI_CNTL_DMA_BT ? "BRANCH," : "",
2284 			stat & OHCI_CNTL_DMA_BAD ? "BADDMA," : "",
2285 			fwohcicode[stat & 0x1f],
2286 			stat & 0x1f
2287 		);
2288 	}else{
2289 		device_printf(sc->fc.dev, "dma %d ch: Nostat\n", ch);
2290 	}
2291 }
2292 
2293 void
2294 dump_db(struct fwohci_softc *sc, uint32_t ch)
2295 {
2296 	struct fwohci_dbch *dbch;
2297 	struct fwohcidb_tr *cp = NULL, *pp, *np = NULL;
2298 	struct fwohcidb *curr = NULL, *prev, *next = NULL;
2299 	int idb, jdb;
2300 	uint32_t cmd, off;
2301 	if(ch == 0){
2302 		off = OHCI_ATQOFF;
2303 		dbch = &sc->atrq;
2304 	}else if(ch == 1){
2305 		off = OHCI_ATSOFF;
2306 		dbch = &sc->atrs;
2307 	}else if(ch == 2){
2308 		off = OHCI_ARQOFF;
2309 		dbch = &sc->arrq;
2310 	}else if(ch == 3){
2311 		off = OHCI_ARSOFF;
2312 		dbch = &sc->arrs;
2313 	}else if(ch < IRX_CH){
2314 		off = OHCI_ITCTL(ch - ITX_CH);
2315 		dbch = &sc->it[ch - ITX_CH];
2316 	}else {
2317 		off = OHCI_IRCTL(ch - IRX_CH);
2318 		dbch = &sc->ir[ch - IRX_CH];
2319 	}
2320 	cmd = OREAD(sc, off + 0xc);
2321 
2322 	if( dbch->ndb == 0 ){
2323 		device_printf(sc->fc.dev, "No DB is attached ch=%d\n", ch);
2324 		return;
2325 	}
2326 	pp = dbch->top;
2327 	prev = pp->db;
2328 	for(idb = 0 ; idb < dbch->ndb ; idb ++ ){
2329 		cp = STAILQ_NEXT(pp, link);
2330 		if(cp == NULL){
2331 			curr = NULL;
2332 			goto outdb;
2333 		}
2334 		np = STAILQ_NEXT(cp, link);
2335 		for(jdb = 0 ; jdb < dbch->ndesc ; jdb ++ ){
2336 			if ((cmd  & 0xfffffff0) == cp->bus_addr) {
2337 				curr = cp->db;
2338 				if(np != NULL){
2339 					next = np->db;
2340 				}else{
2341 					next = NULL;
2342 				}
2343 				goto outdb;
2344 			}
2345 		}
2346 		pp = STAILQ_NEXT(pp, link);
2347 		if(pp == NULL){
2348 			curr = NULL;
2349 			goto outdb;
2350 		}
2351 		prev = pp->db;
2352 	}
2353 outdb:
2354 	if( curr != NULL){
2355 #if 0
2356 		printf("Prev DB %d\n", ch);
2357 		print_db(pp, prev, ch, dbch->ndesc);
2358 #endif
2359 		printf("Current DB %d\n", ch);
2360 		print_db(cp, curr, ch, dbch->ndesc);
2361 #if 0
2362 		printf("Next DB %d\n", ch);
2363 		print_db(np, next, ch, dbch->ndesc);
2364 #endif
2365 	}else{
2366 		printf("dbdump err ch = %d cmd = 0x%08x\n", ch, cmd);
2367 	}
2368 	return;
2369 }
2370 
2371 void
2372 print_db(struct fwohcidb_tr *db_tr, struct fwohcidb *db,
2373 		uint32_t ch, uint32_t max)
2374 {
2375 	fwohcireg_t stat;
2376 	int i, key;
2377 	uint32_t cmd, res;
2378 
2379 	if(db == NULL){
2380 		printf("No Descriptor is found\n");
2381 		return;
2382 	}
2383 
2384 	printf("ch = %d\n%8s %s %s %s %s %4s %8s %8s %4s:%4s\n",
2385 		ch,
2386 		"Current",
2387 		"OP  ",
2388 		"KEY",
2389 		"INT",
2390 		"BR ",
2391 		"len",
2392 		"Addr",
2393 		"Depend",
2394 		"Stat",
2395 		"Cnt");
2396 	for( i = 0 ; i <= max ; i ++){
2397 		cmd = FWOHCI_DMA_READ(db[i].db.desc.cmd);
2398 		res = FWOHCI_DMA_READ(db[i].db.desc.res);
2399 		key = cmd & OHCI_KEY_MASK;
2400 		stat = res >> OHCI_STATUS_SHIFT;
2401 #if defined(__DragonFly__) || __FreeBSD_version < 500000
2402 		printf("%08x %s %s %s %s %5d %08x %08x %04x:%04x",
2403 				db_tr->bus_addr,
2404 #else
2405 		printf("%08jx %s %s %s %s %5d %08x %08x %04x:%04x",
2406 				(uintmax_t)db_tr->bus_addr,
2407 #endif
2408 				dbcode[(cmd >> 28) & 0xf],
2409 				dbkey[(cmd >> 24) & 0x7],
2410 				dbcond[(cmd >> 20) & 0x3],
2411 				dbcond[(cmd >> 18) & 0x3],
2412 				cmd & OHCI_COUNT_MASK,
2413 				FWOHCI_DMA_READ(db[i].db.desc.addr),
2414 				FWOHCI_DMA_READ(db[i].db.desc.depend),
2415 				stat,
2416 				res & OHCI_COUNT_MASK);
2417 		if(stat & 0xff00){
2418 			printf(" %s%s%s%s%s%s %s(%x)\n",
2419 				stat & OHCI_CNTL_DMA_RUN ? "RUN," : "",
2420 				stat & OHCI_CNTL_DMA_WAKE ? "WAKE," : "",
2421 				stat & OHCI_CNTL_DMA_DEAD ? "DEAD," : "",
2422 				stat & OHCI_CNTL_DMA_ACTIVE ? "ACTIVE," : "",
2423 				stat & OHCI_CNTL_DMA_BT ? "BRANCH," : "",
2424 				stat & OHCI_CNTL_DMA_BAD ? "BADDMA," : "",
2425 				fwohcicode[stat & 0x1f],
2426 				stat & 0x1f
2427 			);
2428 		}else{
2429 			printf(" Nostat\n");
2430 		}
2431 		if(key == OHCI_KEY_ST2 ){
2432 			printf("0x%08x 0x%08x 0x%08x 0x%08x\n",
2433 				FWOHCI_DMA_READ(db[i+1].db.immed[0]),
2434 				FWOHCI_DMA_READ(db[i+1].db.immed[1]),
2435 				FWOHCI_DMA_READ(db[i+1].db.immed[2]),
2436 				FWOHCI_DMA_READ(db[i+1].db.immed[3]));
2437 		}
2438 		if(key == OHCI_KEY_DEVICE){
2439 			return;
2440 		}
2441 		if((cmd & OHCI_BRANCH_MASK)
2442 				== OHCI_BRANCH_ALWAYS){
2443 			return;
2444 		}
2445 		if((cmd & OHCI_CMD_MASK)
2446 				== OHCI_OUTPUT_LAST){
2447 			return;
2448 		}
2449 		if((cmd & OHCI_CMD_MASK)
2450 				== OHCI_INPUT_LAST){
2451 			return;
2452 		}
2453 		if(key == OHCI_KEY_ST2 ){
2454 			i++;
2455 		}
2456 	}
2457 	return;
2458 }
2459 
2460 void
2461 fwohci_ibr(struct firewire_comm *fc)
2462 {
2463 	struct fwohci_softc *sc;
2464 	uint32_t fun;
2465 
2466 	device_printf(fc->dev, "Initiate bus reset\n");
2467 	sc = (struct fwohci_softc *)fc;
2468 
2469 	/*
2470 	 * Make sure our cached values from the config rom are
2471 	 * initialised.
2472 	 */
2473 	OWRITE(sc, OHCI_CROMHDR, ntohl(sc->fc.config_rom[0]));
2474 	OWRITE(sc, OHCI_BUS_OPT, ntohl(sc->fc.config_rom[2]));
2475 
2476 	/*
2477 	 * Set root hold-off bit so that non cyclemaster capable node
2478 	 * shouldn't became the root node.
2479 	 */
2480 #if 1
2481 	fun = fwphy_rddata(sc, FW_PHY_IBR_REG);
2482 	fun |= FW_PHY_IBR | FW_PHY_RHB;
2483 	fun = fwphy_wrdata(sc, FW_PHY_IBR_REG, fun);
2484 #else	/* Short bus reset */
2485 	fun = fwphy_rddata(sc, FW_PHY_ISBR_REG);
2486 	fun |= FW_PHY_ISBR | FW_PHY_RHB;
2487 	fun = fwphy_wrdata(sc, FW_PHY_ISBR_REG, fun);
2488 #endif
2489 }
2490 
2491 void
2492 fwohci_txbufdb(struct fwohci_softc *sc, int dmach, struct fw_bulkxfer *bulkxfer)
2493 {
2494 	struct fwohcidb_tr *db_tr, *fdb_tr;
2495 	struct fwohci_dbch *dbch;
2496 	struct fwohcidb *db;
2497 	struct fw_pkt *fp;
2498 	struct fwohci_txpkthdr *ohcifp;
2499 	unsigned short chtag;
2500 	int idb;
2501 
2502 	FW_GLOCK_ASSERT(&sc->fc);
2503 
2504 	dbch = &sc->it[dmach];
2505 	chtag = sc->it[dmach].xferq.flag & 0xff;
2506 
2507 	db_tr = (struct fwohcidb_tr *)(bulkxfer->start);
2508 	fdb_tr = (struct fwohcidb_tr *)(bulkxfer->end);
2509 /*
2510 device_printf(sc->fc.dev, "DB %08x %08x %08x\n", bulkxfer, db_tr->bus_addr, fdb_tr->bus_addr);
2511 */
2512 	for (idb = 0; idb < dbch->xferq.bnpacket; idb ++) {
2513 		db = db_tr->db;
2514 		fp = (struct fw_pkt *)db_tr->buf;
2515 		ohcifp = (struct fwohci_txpkthdr *) db[1].db.immed;
2516 		ohcifp->mode.ld[0] = fp->mode.ld[0];
2517 		ohcifp->mode.common.spd = 0 & 0x7;
2518 		ohcifp->mode.stream.len = fp->mode.stream.len;
2519 		ohcifp->mode.stream.chtag = chtag;
2520 		ohcifp->mode.stream.tcode = 0xa;
2521 #if BYTE_ORDER == BIG_ENDIAN
2522 		FWOHCI_DMA_WRITE(db[1].db.immed[0], db[1].db.immed[0]);
2523 		FWOHCI_DMA_WRITE(db[1].db.immed[1], db[1].db.immed[1]);
2524 #endif
2525 
2526 		FWOHCI_DMA_CLEAR(db[2].db.desc.cmd, OHCI_COUNT_MASK);
2527 		FWOHCI_DMA_SET(db[2].db.desc.cmd, fp->mode.stream.len);
2528 		FWOHCI_DMA_WRITE(db[2].db.desc.res, 0);
2529 #if 0 /* if bulkxfer->npackets changes */
2530 		db[2].db.desc.cmd = OHCI_OUTPUT_LAST
2531 			| OHCI_UPDATE
2532 			| OHCI_BRANCH_ALWAYS;
2533 		db[0].db.desc.depend =
2534 			= db[dbch->ndesc - 1].db.desc.depend
2535 			= STAILQ_NEXT(db_tr, link)->bus_addr | dbch->ndesc;
2536 #else
2537 		FWOHCI_DMA_SET(db[0].db.desc.depend, dbch->ndesc);
2538 		FWOHCI_DMA_SET(db[dbch->ndesc - 1].db.desc.depend, dbch->ndesc);
2539 #endif
2540 		bulkxfer->end = (caddr_t)db_tr;
2541 		db_tr = STAILQ_NEXT(db_tr, link);
2542 	}
2543 	db = ((struct fwohcidb_tr *)bulkxfer->end)->db;
2544 	FWOHCI_DMA_CLEAR(db[0].db.desc.depend, 0xf);
2545 	FWOHCI_DMA_CLEAR(db[dbch->ndesc - 1].db.desc.depend, 0xf);
2546 #if 0 /* if bulkxfer->npackets changes */
2547 	db[dbch->ndesc - 1].db.desc.control |= OHCI_INTERRUPT_ALWAYS;
2548 	/* OHCI 1.1 and above */
2549 	db[0].db.desc.control |= OHCI_INTERRUPT_ALWAYS;
2550 #endif
2551 /*
2552 	db_tr = (struct fwohcidb_tr *)bulkxfer->start;
2553 	fdb_tr = (struct fwohcidb_tr *)bulkxfer->end;
2554 device_printf(sc->fc.dev, "DB %08x %3d %08x %08x\n", bulkxfer, bulkxfer->npacket, db_tr->bus_addr, fdb_tr->bus_addr);
2555 */
2556 	return;
2557 }
2558 
2559 static int
2560 fwohci_add_tx_buf(struct fwohci_dbch *dbch, struct fwohcidb_tr *db_tr,
2561 								int poffset)
2562 {
2563 	struct fwohcidb *db = db_tr->db;
2564 	struct fw_xferq *it;
2565 	int err = 0;
2566 
2567 	it = &dbch->xferq;
2568 	if(it->buf == 0){
2569 		err = EINVAL;
2570 		return err;
2571 	}
2572 	db_tr->buf = fwdma_v_addr(it->buf, poffset);
2573 	db_tr->dbcnt = 3;
2574 
2575 	FWOHCI_DMA_WRITE(db[0].db.desc.cmd,
2576 		OHCI_OUTPUT_MORE | OHCI_KEY_ST2 | 8);
2577 	FWOHCI_DMA_WRITE(db[0].db.desc.addr, 0);
2578 	bzero((void *)&db[1].db.immed[0], sizeof(db[1].db.immed));
2579 	FWOHCI_DMA_WRITE(db[2].db.desc.addr,
2580 	fwdma_bus_addr(it->buf, poffset) + sizeof(uint32_t));
2581 
2582 	FWOHCI_DMA_WRITE(db[2].db.desc.cmd,
2583 		OHCI_OUTPUT_LAST | OHCI_UPDATE | OHCI_BRANCH_ALWAYS);
2584 #if 1
2585 	FWOHCI_DMA_WRITE(db[0].db.desc.res, 0);
2586 	FWOHCI_DMA_WRITE(db[2].db.desc.res, 0);
2587 #endif
2588 	return 0;
2589 }
2590 
2591 int
2592 fwohci_add_rx_buf(struct fwohci_dbch *dbch, struct fwohcidb_tr *db_tr,
2593 		int poffset, struct fwdma_alloc *dummy_dma)
2594 {
2595 	struct fwohcidb *db = db_tr->db;
2596 	struct fw_xferq *ir;
2597 	int i, ldesc;
2598 	bus_addr_t dbuf[2];
2599 	int dsiz[2];
2600 
2601 	ir = &dbch->xferq;
2602 	if (ir->buf == NULL && (dbch->xferq.flag & FWXFERQ_EXTBUF) == 0) {
2603 		if (db_tr->buf == NULL) {
2604 			db_tr->buf = fwdma_malloc_size(dbch->dmat,
2605 			    &db_tr->dma_map, ir->psize, &dbuf[0],
2606 			    BUS_DMA_NOWAIT);
2607 			if (db_tr->buf == NULL)
2608 				return(ENOMEM);
2609 		}
2610 		db_tr->dbcnt = 1;
2611 		dsiz[0] = ir->psize;
2612 		bus_dmamap_sync(dbch->dmat, db_tr->dma_map,
2613 			BUS_DMASYNC_PREREAD);
2614 	} else {
2615 		db_tr->dbcnt = 0;
2616 		if (dummy_dma != NULL) {
2617 			dsiz[db_tr->dbcnt] = sizeof(uint32_t);
2618 			dbuf[db_tr->dbcnt++] = dummy_dma->bus_addr;
2619 		}
2620 		dsiz[db_tr->dbcnt] = ir->psize;
2621 		if (ir->buf != NULL) {
2622 			db_tr->buf = fwdma_v_addr(ir->buf, poffset);
2623 			dbuf[db_tr->dbcnt] = fwdma_bus_addr( ir->buf, poffset);
2624 		}
2625 		db_tr->dbcnt++;
2626 	}
2627 	for(i = 0 ; i < db_tr->dbcnt ; i++){
2628 		FWOHCI_DMA_WRITE(db[i].db.desc.addr, dbuf[i]);
2629 		FWOHCI_DMA_WRITE(db[i].db.desc.cmd, OHCI_INPUT_MORE | dsiz[i]);
2630 		if (ir->flag & FWXFERQ_STREAM) {
2631 			FWOHCI_DMA_SET(db[i].db.desc.cmd, OHCI_UPDATE);
2632 		}
2633 		FWOHCI_DMA_WRITE(db[i].db.desc.res, dsiz[i]);
2634 	}
2635 	ldesc = db_tr->dbcnt - 1;
2636 	if (ir->flag & FWXFERQ_STREAM) {
2637 		FWOHCI_DMA_SET(db[ldesc].db.desc.cmd, OHCI_INPUT_LAST);
2638 	}
2639 	FWOHCI_DMA_SET(db[ldesc].db.desc.cmd, OHCI_BRANCH_ALWAYS);
2640 	return 0;
2641 }
2642 
2643 
2644 static int
2645 fwohci_arcv_swap(struct fw_pkt *fp, int len)
2646 {
2647 	struct fw_pkt *fp0;
2648 	uint32_t ld0;
2649 	int slen, hlen;
2650 #if BYTE_ORDER == BIG_ENDIAN
2651 	int i;
2652 #endif
2653 
2654 	ld0 = FWOHCI_DMA_READ(fp->mode.ld[0]);
2655 #if 0
2656 	printf("ld0: x%08x\n", ld0);
2657 #endif
2658 	fp0 = (struct fw_pkt *)&ld0;
2659 	/* determine length to swap */
2660 	switch (fp0->mode.common.tcode) {
2661 	case FWTCODE_RREQQ:
2662 	case FWTCODE_WRES:
2663 	case FWTCODE_WREQQ:
2664 	case FWTCODE_RRESQ:
2665 	case FWOHCITCODE_PHY:
2666 		slen = 12;
2667 		break;
2668 	case FWTCODE_RREQB:
2669 	case FWTCODE_WREQB:
2670 	case FWTCODE_LREQ:
2671 	case FWTCODE_RRESB:
2672 	case FWTCODE_LRES:
2673 		slen = 16;
2674 		break;
2675 	default:
2676 		printf("Unknown tcode %d\n", fp0->mode.common.tcode);
2677 		return(0);
2678 	}
2679 	hlen = tinfo[fp0->mode.common.tcode].hdr_len;
2680 	if (hlen > len) {
2681 		if (firewire_debug)
2682 			printf("splitted header\n");
2683 		return(-hlen);
2684 	}
2685 #if BYTE_ORDER == BIG_ENDIAN
2686 	for(i = 0; i < slen/4; i ++)
2687 		fp->mode.ld[i] = FWOHCI_DMA_READ(fp->mode.ld[i]);
2688 #endif
2689 	return(hlen);
2690 }
2691 
2692 static int
2693 fwohci_get_plen(struct fwohci_softc *sc, struct fwohci_dbch *dbch, struct fw_pkt *fp)
2694 {
2695 	struct tcode_info *info;
2696 	int r;
2697 
2698 	info = &tinfo[fp->mode.common.tcode];
2699 	r = info->hdr_len + sizeof(uint32_t);
2700 	if ((info->flag & FWTI_BLOCK_ASY) != 0)
2701 		r += roundup2(fp->mode.wreqb.len, sizeof(uint32_t));
2702 
2703 	if (r == sizeof(uint32_t)) {
2704 		/* XXX */
2705 		device_printf(sc->fc.dev, "Unknown tcode %d\n",
2706 						fp->mode.common.tcode);
2707 		return (-1);
2708 	}
2709 
2710 	if (r > dbch->xferq.psize) {
2711 		device_printf(sc->fc.dev, "Invalid packet length %d\n", r);
2712 		return (-1);
2713 		/* panic ? */
2714 	}
2715 
2716 	return r;
2717 }
2718 
2719 static void
2720 fwohci_arcv_free_buf(struct fwohci_softc *sc, struct fwohci_dbch *dbch,
2721     struct fwohcidb_tr *db_tr, uint32_t off, int wake)
2722 {
2723 	struct fwohcidb *db = &db_tr->db[0];
2724 
2725 	FWOHCI_DMA_CLEAR(db->db.desc.depend, 0xf);
2726 	FWOHCI_DMA_WRITE(db->db.desc.res, dbch->xferq.psize);
2727 	FWOHCI_DMA_SET(dbch->bottom->db[0].db.desc.depend, 1);
2728 	fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREWRITE);
2729 	dbch->bottom = db_tr;
2730 
2731 	if (wake)
2732 		OWRITE(sc, OHCI_DMACTL(off), OHCI_CNTL_DMA_WAKE);
2733 }
2734 
2735 static void
2736 fwohci_arcv(struct fwohci_softc *sc, struct fwohci_dbch *dbch, int count)
2737 {
2738 	struct fwohcidb_tr *db_tr;
2739 	struct iovec vec[2];
2740 	struct fw_pkt pktbuf;
2741 	int nvec;
2742 	struct fw_pkt *fp;
2743 	uint8_t *ld;
2744 	uint32_t stat, off, status, event;
2745 	u_int spd;
2746 	int len, plen, hlen, pcnt, offset;
2747 	int s;
2748 	caddr_t buf;
2749 	int resCount;
2750 
2751 	if(&sc->arrq == dbch){
2752 		off = OHCI_ARQOFF;
2753 	}else if(&sc->arrs == dbch){
2754 		off = OHCI_ARSOFF;
2755 	}else{
2756 		return;
2757 	}
2758 
2759 	s = splfw();
2760 	db_tr = dbch->top;
2761 	pcnt = 0;
2762 	/* XXX we cannot handle a packet which lies in more than two buf */
2763 	fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_POSTREAD);
2764 	fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_POSTWRITE);
2765 	status = FWOHCI_DMA_READ(db_tr->db[0].db.desc.res) >> OHCI_STATUS_SHIFT;
2766 	resCount = FWOHCI_DMA_READ(db_tr->db[0].db.desc.res) & OHCI_COUNT_MASK;
2767 	while (status & OHCI_CNTL_DMA_ACTIVE) {
2768 #if 0
2769 
2770 		if (off == OHCI_ARQOFF)
2771 			printf("buf 0x%08x, status 0x%04x, resCount 0x%04x\n",
2772 			    db_tr->bus_addr, status, resCount);
2773 #endif
2774 		len = dbch->xferq.psize - resCount;
2775 		ld = (uint8_t *)db_tr->buf;
2776 		if (dbch->pdb_tr == NULL) {
2777 			len -= dbch->buf_offset;
2778 			ld += dbch->buf_offset;
2779 		}
2780 		if (len > 0)
2781 			bus_dmamap_sync(dbch->dmat, db_tr->dma_map,
2782 					BUS_DMASYNC_POSTREAD);
2783 		while (len > 0 ) {
2784 			if (count >= 0 && count-- == 0)
2785 				goto out;
2786 			if(dbch->pdb_tr != NULL){
2787 				/* we have a fragment in previous buffer */
2788 				int rlen;
2789 
2790 				offset = dbch->buf_offset;
2791 				if (offset < 0)
2792 					offset = - offset;
2793 				buf = dbch->pdb_tr->buf + offset;
2794 				rlen = dbch->xferq.psize - offset;
2795 				if (firewire_debug)
2796 					printf("rlen=%d, offset=%d\n",
2797 						rlen, dbch->buf_offset);
2798 				if (dbch->buf_offset < 0) {
2799 					/* splitted in header, pull up */
2800 					char *p;
2801 
2802 					p = (char *)&pktbuf;
2803 					bcopy(buf, p, rlen);
2804 					p += rlen;
2805 					/* this must be too long but harmless */
2806 					rlen = sizeof(pktbuf) - rlen;
2807 					if (rlen < 0)
2808 						printf("why rlen < 0\n");
2809 					bcopy(db_tr->buf, p, rlen);
2810 					ld += rlen;
2811 					len -= rlen;
2812 					hlen = fwohci_arcv_swap(&pktbuf, sizeof(pktbuf));
2813 					if (hlen <= 0) {
2814 						printf("hlen should be positive.");
2815 						goto err;
2816 					}
2817 					offset = sizeof(pktbuf);
2818 					vec[0].iov_base = (char *)&pktbuf;
2819 					vec[0].iov_len = offset;
2820 				} else {
2821 					/* splitted in payload */
2822 					offset = rlen;
2823 					vec[0].iov_base = buf;
2824 					vec[0].iov_len = rlen;
2825 				}
2826 				fp=(struct fw_pkt *)vec[0].iov_base;
2827 				nvec = 1;
2828 			} else {
2829 				/* no fragment in previous buffer */
2830 				fp=(struct fw_pkt *)ld;
2831 				hlen = fwohci_arcv_swap(fp, len);
2832 				if (hlen == 0)
2833 					goto err;
2834 				if (hlen < 0) {
2835 					dbch->pdb_tr = db_tr;
2836 					dbch->buf_offset = - dbch->buf_offset;
2837 					/* sanity check */
2838 					if (resCount != 0)  {
2839 						printf("resCount=%d hlen=%d\n",
2840 						    resCount, hlen);
2841 						    goto err;
2842 					}
2843 					goto out;
2844 				}
2845 				offset = 0;
2846 				nvec = 0;
2847 			}
2848 			plen = fwohci_get_plen(sc, dbch, fp) - offset;
2849 			if (plen < 0) {
2850 				/* minimum header size + trailer
2851 				= sizeof(fw_pkt) so this shouldn't happens */
2852 				printf("plen(%d) is negative! offset=%d\n",
2853 				    plen, offset);
2854 				goto err;
2855 			}
2856 			if (plen > 0) {
2857 				len -= plen;
2858 				if (len < 0) {
2859 					dbch->pdb_tr = db_tr;
2860 					if (firewire_debug)
2861 						printf("splitted payload\n");
2862 					/* sanity check */
2863 					if (resCount != 0)  {
2864 						printf("resCount=%d plen=%d"
2865 						    " len=%d\n",
2866 						    resCount, plen, len);
2867 						goto err;
2868 					}
2869 					goto out;
2870 				}
2871 				vec[nvec].iov_base = ld;
2872 				vec[nvec].iov_len = plen;
2873 				nvec ++;
2874 				ld += plen;
2875 			}
2876 			dbch->buf_offset = ld - (uint8_t *)db_tr->buf;
2877 			if (nvec == 0)
2878 				printf("nvec == 0\n");
2879 
2880 /* DMA result-code will be written at the tail of packet */
2881 			stat = FWOHCI_DMA_READ(*(uint32_t *)(ld - sizeof(struct fwohci_trailer)));
2882 #if 0
2883 			printf("plen: %d, stat %x\n",
2884 			    plen ,stat);
2885 #endif
2886 			spd = (stat >> 21) & 0x3;
2887 			event = (stat >> 16) & 0x1f;
2888 			switch (event) {
2889 			case FWOHCIEV_ACKPEND:
2890 #if 0
2891 				printf("fwohci_arcv: ack pending tcode=0x%x..\n", fp->mode.common.tcode);
2892 #endif
2893 				/* fall through */
2894 			case FWOHCIEV_ACKCOMPL:
2895 			{
2896 				struct fw_rcv_buf rb;
2897 
2898 				if ((vec[nvec-1].iov_len -=
2899 					sizeof(struct fwohci_trailer)) == 0)
2900 					nvec--;
2901 				rb.fc = &sc->fc;
2902 				rb.vec = vec;
2903 				rb.nvec = nvec;
2904 				rb.spd = spd;
2905 				fw_rcv(&rb);
2906 				break;
2907 			}
2908 			case FWOHCIEV_BUSRST:
2909 				if ((sc->fc.status != FWBUSRESET) &&
2910 				    (sc->fc.status != FWBUSINIT))
2911 					printf("got BUSRST packet!?\n");
2912 				break;
2913 			default:
2914 				device_printf(sc->fc.dev,
2915 				    "Async DMA Receive error err=%02x %s"
2916 				    " plen=%d offset=%d len=%d status=0x%08x"
2917 				    " tcode=0x%x, stat=0x%08x\n",
2918 				    event, fwohcicode[event], plen,
2919 				    dbch->buf_offset, len,
2920 				    OREAD(sc, OHCI_DMACTL(off)),
2921 				    fp->mode.common.tcode, stat);
2922 #if 1 /* XXX */
2923 				goto err;
2924 #endif
2925 				break;
2926 			}
2927 			pcnt ++;
2928 			if (dbch->pdb_tr != NULL) {
2929 				fwohci_arcv_free_buf(sc, dbch, dbch->pdb_tr,
2930 				    off, 1);
2931 				dbch->pdb_tr = NULL;
2932 			}
2933 
2934 		}
2935 out:
2936 		if (resCount == 0) {
2937 			/* done on this buffer */
2938 			if (dbch->pdb_tr == NULL) {
2939 				fwohci_arcv_free_buf(sc, dbch, db_tr, off, 1);
2940 				dbch->buf_offset = 0;
2941 			} else
2942 				if (dbch->pdb_tr != db_tr)
2943 					printf("pdb_tr != db_tr\n");
2944 			db_tr = STAILQ_NEXT(db_tr, link);
2945 			status = FWOHCI_DMA_READ(db_tr->db[0].db.desc.res)
2946 						>> OHCI_STATUS_SHIFT;
2947 			resCount = FWOHCI_DMA_READ(db_tr->db[0].db.desc.res)
2948 						& OHCI_COUNT_MASK;
2949 			/* XXX check buffer overrun */
2950 			dbch->top = db_tr;
2951 		} else {
2952 			dbch->buf_offset = dbch->xferq.psize - resCount;
2953 			break;
2954 		}
2955 		/* XXX make sure DMA is not dead */
2956 	}
2957 #if 0
2958 	if (pcnt < 1)
2959 		printf("fwohci_arcv: no packets\n");
2960 #endif
2961 	splx(s);
2962 	return;
2963 
2964 err:
2965 	device_printf(sc->fc.dev, "AR DMA status=%x, ",
2966 					OREAD(sc, OHCI_DMACTL(off)));
2967 	dbch->pdb_tr = NULL;
2968 	/* skip until resCount != 0 */
2969 	printf(" skip buffer");
2970 	while (resCount == 0) {
2971 		printf(" #");
2972 		fwohci_arcv_free_buf(sc, dbch, db_tr, off, 0);
2973 		db_tr = STAILQ_NEXT(db_tr, link);
2974 		resCount = FWOHCI_DMA_READ(db_tr->db[0].db.desc.res)
2975 						& OHCI_COUNT_MASK;
2976 	} while (resCount == 0)
2977 	printf(" done\n");
2978 	dbch->top = db_tr;
2979 	dbch->buf_offset = dbch->xferq.psize - resCount;
2980 	OWRITE(sc, OHCI_DMACTL(off), OHCI_CNTL_DMA_WAKE);
2981 	splx(s);
2982 }
2983