1 /* 2 * Copyright (c) 1998-2002 Katsushi Kobayashi and Hidetoshi Shimokawa 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the acknowledgement as bellow: 15 * 16 * This product includes software developed by K. Kobayashi and H. Shimokawa 17 * 18 * 4. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 23 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 24 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 25 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 26 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 27 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 28 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 29 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 30 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 * POSSIBILITY OF SUCH DAMAGE. 32 * 33 * $FreeBSD$ 34 * 35 */ 36 37 #define ATRQ_CH 0 38 #define ATRS_CH 1 39 #define ARRQ_CH 2 40 #define ARRS_CH 3 41 #define ITX_CH 4 42 #define IRX_CH 0x24 43 44 #include <sys/param.h> 45 #include <sys/proc.h> 46 #include <sys/systm.h> 47 #include <sys/types.h> 48 #include <sys/mbuf.h> 49 #include <sys/mman.h> 50 #include <sys/socket.h> 51 #include <sys/socketvar.h> 52 #include <sys/signalvar.h> 53 #include <sys/malloc.h> 54 #include <sys/uio.h> 55 #include <sys/sockio.h> 56 #include <sys/bus.h> 57 #include <sys/kernel.h> 58 #include <sys/conf.h> 59 60 #include <machine/bus.h> 61 #include <machine/resource.h> 62 #include <sys/rman.h> 63 64 #include <machine/cpufunc.h> /* for rdtsc proto for clock.h below */ 65 #include <machine/clock.h> 66 #include <pci/pcivar.h> 67 #include <pci/pcireg.h> 68 #include <vm/vm.h> 69 #include <vm/vm_extern.h> 70 #include <vm/pmap.h> /* for vtophys proto */ 71 72 #include <dev/firewire/firewire.h> 73 #include <dev/firewire/firewirereg.h> 74 #include <dev/firewire/fwohcireg.h> 75 #include <dev/firewire/fwohcivar.h> 76 #include <dev/firewire/firewire_phy.h> 77 78 #include <dev/firewire/iec68113.h> 79 80 #undef OHCI_DEBUG 81 82 static char dbcode[16][0x10]={"OUTM", "OUTL","INPM","INPL", 83 "STOR","LOAD","NOP ","STOP",}; 84 static char dbkey[8][0x10]={"ST0", "ST1","ST2","ST3", 85 "UNDEF","REG","SYS","DEV"}; 86 char fwohcicode[32][0x20]={ 87 "No stat","Undef","long","miss Ack err", 88 "underrun","overrun","desc err", "data read err", 89 "data write err","bus reset","timeout","tcode err", 90 "Undef","Undef","unknown event","flushed", 91 "Undef","ack complete","ack pend","Undef", 92 "ack busy_X","ack busy_A","ack busy_B","Undef", 93 "Undef","Undef","Undef","ack tardy", 94 "Undef","ack data_err","ack type_err",""}; 95 #define MAX_SPEED 2 96 extern char linkspeed[MAX_SPEED+1][0x10]; 97 static char dbcond[4][0x10]={"NEV","C=1", "C=0", "ALL"}; 98 u_int32_t tagbit[4] = { 1 << 28, 1 << 29, 1 << 30, 1 << 31}; 99 100 static struct tcode_info tinfo[] = { 101 /* hdr_len block flag*/ 102 /* 0 WREQQ */ {16, FWTI_REQ | FWTI_TLABEL}, 103 /* 1 WREQB */ {16, FWTI_REQ | FWTI_TLABEL | FWTI_BLOCK_ASY}, 104 /* 2 WRES */ {12, FWTI_RES}, 105 /* 3 XXX */ { 0, 0}, 106 /* 4 RREQQ */ {12, FWTI_REQ | FWTI_TLABEL}, 107 /* 5 RREQB */ {16, FWTI_REQ | FWTI_TLABEL}, 108 /* 6 RRESQ */ {16, FWTI_RES}, 109 /* 7 RRESB */ {16, FWTI_RES | FWTI_BLOCK_ASY}, 110 /* 8 CYCS */ { 0, 0}, 111 /* 9 LREQ */ {16, FWTI_REQ | FWTI_TLABEL | FWTI_BLOCK_ASY}, 112 /* a STREAM */ { 4, FWTI_REQ | FWTI_BLOCK_STR}, 113 /* b LRES */ {16, FWTI_RES | FWTI_BLOCK_ASY}, 114 /* c XXX */ { 0, 0}, 115 /* d XXX */ { 0, 0}, 116 /* e PHY */ {12, FWTI_REQ}, 117 /* f XXX */ { 0, 0} 118 }; 119 120 #define OHCI_WRITE_SIGMASK 0xffff0000 121 #define OHCI_READ_SIGMASK 0xffff0000 122 123 #define OWRITE(sc, r, x) bus_space_write_4((sc)->bst, (sc)->bsh, (r), (x)) 124 #define OREAD(sc, r) bus_space_read_4((sc)->bst, (sc)->bsh, (r)) 125 126 static void fwohci_ibr __P((struct firewire_comm *)); 127 static void fwohci_db_init __P((struct fwohci_dbch *)); 128 static void fwohci_db_free __P((struct fwohci_dbch *)); 129 static void fwohci_arcv __P((struct fwohci_softc *, struct fwohci_dbch *, int)); 130 static void fwohci_ircv __P((struct fwohci_softc *, struct fwohci_dbch *, int)); 131 static void fwohci_txd __P((struct fwohci_softc *, struct fwohci_dbch *)); 132 static void fwohci_start_atq __P((struct firewire_comm *)); 133 static void fwohci_start_ats __P((struct firewire_comm *)); 134 static void fwohci_start __P((struct fwohci_softc *, struct fwohci_dbch *)); 135 static void fwohci_drain_atq __P((struct firewire_comm *, struct fw_xfer *)); 136 static void fwohci_drain_ats __P((struct firewire_comm *, struct fw_xfer *)); 137 static void fwohci_drain __P((struct firewire_comm *, struct fw_xfer *, struct fwohci_dbch *)); 138 static u_int32_t fwphy_wrdata __P(( struct fwohci_softc *, u_int32_t, u_int32_t)); 139 static u_int32_t fwphy_rddata __P(( struct fwohci_softc *, u_int32_t)); 140 static int fwohci_rx_enable __P((struct fwohci_softc *, struct fwohci_dbch *)); 141 static int fwohci_tx_enable __P((struct fwohci_softc *, struct fwohci_dbch *)); 142 static int fwohci_irx_enable __P((struct firewire_comm *, int)); 143 static int fwohci_irxpp_enable __P((struct firewire_comm *, int)); 144 static int fwohci_irxbuf_enable __P((struct firewire_comm *, int)); 145 static int fwohci_irx_disable __P((struct firewire_comm *, int)); 146 static void fwohci_irx_post __P((struct firewire_comm *, u_int32_t *)); 147 static int fwohci_itxbuf_enable __P((struct firewire_comm *, int)); 148 static int fwohci_itx_disable __P((struct firewire_comm *, int)); 149 static void fwohci_timeout __P((void *)); 150 static void fwohci_poll __P((struct firewire_comm *, int, int)); 151 static void fwohci_set_intr __P((struct firewire_comm *, int)); 152 static int fwohci_add_rx_buf __P((struct fwohcidb_tr *, unsigned short, int, void *, void *)); 153 static int fwohci_add_tx_buf __P((struct fwohcidb_tr *, unsigned short, int, void *)); 154 static void dump_db __P((struct fwohci_softc *, u_int32_t)); 155 static void print_db __P((volatile struct fwohcidb *, u_int32_t , u_int32_t)); 156 static void dump_dma __P((struct fwohci_softc *, u_int32_t)); 157 static u_int32_t fwohci_cyctimer __P((struct firewire_comm *)); 158 static void fwohci_rbuf_update __P((struct fwohci_softc *, int)); 159 static void fwohci_tbuf_update __P((struct fwohci_softc *, int)); 160 void fwohci_txbufdb __P((struct fwohci_softc *, int , struct fw_bulkxfer *)); 161 162 /* 163 * memory allocated for DMA programs 164 */ 165 #define DMA_PROG_ALLOC (8 * PAGE_SIZE) 166 167 /* #define NDB 1024 */ 168 #define NDB FWMAXQUEUE 169 #define NDVDB (DVBUF * NDB) 170 171 #define OHCI_VERSION 0x00 172 #define OHCI_CROMHDR 0x18 173 #define OHCI_BUS_OPT 0x20 174 #define OHCI_BUSIRMC (1 << 31) 175 #define OHCI_BUSCMC (1 << 30) 176 #define OHCI_BUSISC (1 << 29) 177 #define OHCI_BUSBMC (1 << 28) 178 #define OHCI_BUSPMC (1 << 27) 179 #define OHCI_BUSFNC OHCI_BUSIRMC | OHCI_BUSCMC | OHCI_BUSISC |\ 180 OHCI_BUSBMC | OHCI_BUSPMC 181 182 #define OHCI_EUID_HI 0x24 183 #define OHCI_EUID_LO 0x28 184 185 #define OHCI_CROMPTR 0x34 186 #define OHCI_HCCCTL 0x50 187 #define OHCI_HCCCTLCLR 0x54 188 #define OHCI_AREQHI 0x100 189 #define OHCI_AREQHICLR 0x104 190 #define OHCI_AREQLO 0x108 191 #define OHCI_AREQLOCLR 0x10c 192 #define OHCI_PREQHI 0x110 193 #define OHCI_PREQHICLR 0x114 194 #define OHCI_PREQLO 0x118 195 #define OHCI_PREQLOCLR 0x11c 196 #define OHCI_PREQUPPER 0x120 197 198 #define OHCI_SID_BUF 0x64 199 #define OHCI_SID_CNT 0x68 200 #define OHCI_SID_CNT_MASK 0xffc 201 202 #define OHCI_IT_STAT 0x90 203 #define OHCI_IT_STATCLR 0x94 204 #define OHCI_IT_MASK 0x98 205 #define OHCI_IT_MASKCLR 0x9c 206 207 #define OHCI_IR_STAT 0xa0 208 #define OHCI_IR_STATCLR 0xa4 209 #define OHCI_IR_MASK 0xa8 210 #define OHCI_IR_MASKCLR 0xac 211 212 #define OHCI_LNKCTL 0xe0 213 #define OHCI_LNKCTLCLR 0xe4 214 215 #define OHCI_PHYACCESS 0xec 216 #define OHCI_CYCLETIMER 0xf0 217 218 #define OHCI_DMACTL(off) (off) 219 #define OHCI_DMACTLCLR(off) (off + 4) 220 #define OHCI_DMACMD(off) (off + 0xc) 221 #define OHCI_DMAMATCH(off) (off + 0x10) 222 223 #define OHCI_ATQOFF 0x180 224 #define OHCI_ATQCTL OHCI_ATQOFF 225 #define OHCI_ATQCTLCLR (OHCI_ATQOFF + 4) 226 #define OHCI_ATQCMD (OHCI_ATQOFF + 0xc) 227 #define OHCI_ATQMATCH (OHCI_ATQOFF + 0x10) 228 229 #define OHCI_ATSOFF 0x1a0 230 #define OHCI_ATSCTL OHCI_ATSOFF 231 #define OHCI_ATSCTLCLR (OHCI_ATSOFF + 4) 232 #define OHCI_ATSCMD (OHCI_ATSOFF + 0xc) 233 #define OHCI_ATSMATCH (OHCI_ATSOFF + 0x10) 234 235 #define OHCI_ARQOFF 0x1c0 236 #define OHCI_ARQCTL OHCI_ARQOFF 237 #define OHCI_ARQCTLCLR (OHCI_ARQOFF + 4) 238 #define OHCI_ARQCMD (OHCI_ARQOFF + 0xc) 239 #define OHCI_ARQMATCH (OHCI_ARQOFF + 0x10) 240 241 #define OHCI_ARSOFF 0x1e0 242 #define OHCI_ARSCTL OHCI_ARSOFF 243 #define OHCI_ARSCTLCLR (OHCI_ARSOFF + 4) 244 #define OHCI_ARSCMD (OHCI_ARSOFF + 0xc) 245 #define OHCI_ARSMATCH (OHCI_ARSOFF + 0x10) 246 247 #define OHCI_ITOFF(CH) (0x200 + 0x10 * (CH)) 248 #define OHCI_ITCTL(CH) (OHCI_ITOFF(CH)) 249 #define OHCI_ITCTLCLR(CH) (OHCI_ITOFF(CH) + 4) 250 #define OHCI_ITCMD(CH) (OHCI_ITOFF(CH) + 0xc) 251 252 #define OHCI_IROFF(CH) (0x400 + 0x20 * (CH)) 253 #define OHCI_IRCTL(CH) (OHCI_IROFF(CH)) 254 #define OHCI_IRCTLCLR(CH) (OHCI_IROFF(CH) + 4) 255 #define OHCI_IRCMD(CH) (OHCI_IROFF(CH) + 0xc) 256 #define OHCI_IRMATCH(CH) (OHCI_IROFF(CH) + 0x10) 257 258 d_ioctl_t fwohci_ioctl; 259 260 /* 261 * Communication with PHY device 262 */ 263 static u_int32_t 264 fwphy_wrdata( struct fwohci_softc *sc, u_int32_t addr, u_int32_t data) 265 { 266 u_int32_t fun; 267 268 addr &= 0xf; 269 data &= 0xff; 270 271 fun = (PHYDEV_WRCMD | (addr << PHYDEV_REGADDR) | (data << PHYDEV_WRDATA)); 272 OWRITE(sc, OHCI_PHYACCESS, fun); 273 DELAY(100); 274 275 return(fwphy_rddata( sc, addr)); 276 } 277 278 static u_int32_t 279 fwohci_set_bus_manager(struct firewire_comm *fc, u_int node) 280 { 281 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 282 int i; 283 u_int32_t bm; 284 285 #define OHCI_CSR_DATA 0x0c 286 #define OHCI_CSR_COMP 0x10 287 #define OHCI_CSR_CONT 0x14 288 #define OHCI_BUS_MANAGER_ID 0 289 290 OWRITE(sc, OHCI_CSR_DATA, node); 291 OWRITE(sc, OHCI_CSR_COMP, 0x3f); 292 OWRITE(sc, OHCI_CSR_CONT, OHCI_BUS_MANAGER_ID); 293 for (i = 0; !(OREAD(sc, OHCI_CSR_CONT) & (1<<31)) && (i < 1000); i++) 294 DELAY(10); 295 bm = OREAD(sc, OHCI_CSR_DATA); 296 if((bm & 0x3f) == 0x3f) 297 bm = node; 298 if (bootverbose) 299 device_printf(sc->fc.dev, 300 "fw_set_bus_manager: %d->%d (loop=%d)\n", bm, node, i); 301 302 return(bm); 303 } 304 305 static u_int32_t 306 fwphy_rddata(struct fwohci_softc *sc, u_int addr) 307 { 308 u_int32_t fun, stat; 309 u_int i, retry = 0; 310 311 addr &= 0xf; 312 #define MAX_RETRY 100 313 again: 314 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_REG_FAIL); 315 fun = PHYDEV_RDCMD | (addr << PHYDEV_REGADDR); 316 OWRITE(sc, OHCI_PHYACCESS, fun); 317 for ( i = 0 ; i < MAX_RETRY ; i ++ ){ 318 fun = OREAD(sc, OHCI_PHYACCESS); 319 if ((fun & PHYDEV_RDCMD) == 0 && (fun & PHYDEV_RDDONE) != 0) 320 break; 321 DELAY(100); 322 } 323 if(i >= MAX_RETRY) { 324 if (bootverbose) 325 device_printf(sc->fc.dev, "phy read failed(1).\n"); 326 if (++retry < MAX_RETRY) { 327 DELAY(100); 328 goto again; 329 } 330 } 331 /* Make sure that SCLK is started */ 332 stat = OREAD(sc, FWOHCI_INTSTAT); 333 if ((stat & OHCI_INT_REG_FAIL) != 0 || 334 ((fun >> PHYDEV_REGADDR) & 0xf) != addr) { 335 if (bootverbose) 336 device_printf(sc->fc.dev, "phy read failed(2).\n"); 337 if (++retry < MAX_RETRY) { 338 DELAY(100); 339 goto again; 340 } 341 } 342 if (bootverbose || retry >= MAX_RETRY) 343 device_printf(sc->fc.dev, 344 "fwphy_rddata: loop=%d, retry=%d\n", i, retry); 345 #undef MAX_RETRY 346 return((fun >> PHYDEV_RDDATA )& 0xff); 347 } 348 /* Device specific ioctl. */ 349 int 350 fwohci_ioctl (dev_t dev, u_long cmd, caddr_t data, int flag, fw_proc *td) 351 { 352 struct firewire_softc *sc; 353 struct fwohci_softc *fc; 354 int unit = DEV2UNIT(dev); 355 int err = 0; 356 struct fw_reg_req_t *reg = (struct fw_reg_req_t *) data; 357 u_int32_t *dmach = (u_int32_t *) data; 358 359 sc = devclass_get_softc(firewire_devclass, unit); 360 if(sc == NULL){ 361 return(EINVAL); 362 } 363 fc = (struct fwohci_softc *)sc->fc; 364 365 if (!data) 366 return(EINVAL); 367 368 switch (cmd) { 369 case FWOHCI_WRREG: 370 #define OHCI_MAX_REG 0x800 371 if(reg->addr <= OHCI_MAX_REG){ 372 OWRITE(fc, reg->addr, reg->data); 373 reg->data = OREAD(fc, reg->addr); 374 }else{ 375 err = EINVAL; 376 } 377 break; 378 case FWOHCI_RDREG: 379 if(reg->addr <= OHCI_MAX_REG){ 380 reg->data = OREAD(fc, reg->addr); 381 }else{ 382 err = EINVAL; 383 } 384 break; 385 /* Read DMA descriptors for debug */ 386 case DUMPDMA: 387 if(*dmach <= OHCI_MAX_DMA_CH ){ 388 dump_dma(fc, *dmach); 389 dump_db(fc, *dmach); 390 }else{ 391 err = EINVAL; 392 } 393 break; 394 default: 395 break; 396 } 397 return err; 398 } 399 400 static int 401 fwohci_probe_phy(struct fwohci_softc *sc, device_t dev) 402 { 403 u_int32_t reg, reg2; 404 int e1394a = 1; 405 /* 406 * probe PHY parameters 407 * 0. to prove PHY version, whether compliance of 1394a. 408 * 1. to probe maximum speed supported by the PHY and 409 * number of port supported by core-logic. 410 * It is not actually available port on your PC . 411 */ 412 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_LPS); 413 #if 0 414 /* XXX wait for SCLK. */ 415 DELAY(100000); 416 #endif 417 reg = fwphy_rddata(sc, FW_PHY_SPD_REG); 418 419 if((reg >> 5) != 7 ){ 420 sc->fc.mode &= ~FWPHYASYST; 421 sc->fc.nport = reg & FW_PHY_NP; 422 sc->fc.speed = reg & FW_PHY_SPD >> 6; 423 if (sc->fc.speed > MAX_SPEED) { 424 device_printf(dev, "invalid speed %d (fixed to %d).\n", 425 sc->fc.speed, MAX_SPEED); 426 sc->fc.speed = MAX_SPEED; 427 } 428 device_printf(dev, 429 "Phy 1394 only %s, %d ports.\n", 430 linkspeed[sc->fc.speed], sc->fc.nport); 431 }else{ 432 reg2 = fwphy_rddata(sc, FW_PHY_ESPD_REG); 433 sc->fc.mode |= FWPHYASYST; 434 sc->fc.nport = reg & FW_PHY_NP; 435 sc->fc.speed = (reg2 & FW_PHY_ESPD) >> 5; 436 if (sc->fc.speed > MAX_SPEED) { 437 device_printf(dev, "invalid speed %d (fixed to %d).\n", 438 sc->fc.speed, MAX_SPEED); 439 sc->fc.speed = MAX_SPEED; 440 } 441 device_printf(dev, 442 "Phy 1394a available %s, %d ports.\n", 443 linkspeed[sc->fc.speed], sc->fc.nport); 444 445 /* check programPhyEnable */ 446 reg2 = fwphy_rddata(sc, 5); 447 #if 0 448 if (e1394a && (OREAD(sc, OHCI_HCCCTL) & OHCI_HCC_PRPHY)) { 449 #else /* XXX force to enable 1394a */ 450 if (e1394a) { 451 #endif 452 if (bootverbose) 453 device_printf(dev, 454 "Enable 1394a Enhancements\n"); 455 /* enable EAA EMC */ 456 reg2 |= 0x03; 457 /* set aPhyEnhanceEnable */ 458 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_PHYEN); 459 OWRITE(sc, OHCI_HCCCTLCLR, OHCI_HCC_PRPHY); 460 } else { 461 /* for safe */ 462 reg2 &= ~0x83; 463 } 464 reg2 = fwphy_wrdata(sc, 5, reg2); 465 } 466 467 reg = fwphy_rddata(sc, FW_PHY_SPD_REG); 468 if((reg >> 5) == 7 ){ 469 reg = fwphy_rddata(sc, 4); 470 reg |= 1 << 6; 471 fwphy_wrdata(sc, 4, reg); 472 reg = fwphy_rddata(sc, 4); 473 } 474 return 0; 475 } 476 477 478 void 479 fwohci_reset(struct fwohci_softc *sc, device_t dev) 480 { 481 int i, max_rec, speed; 482 u_int32_t reg, reg2; 483 struct fwohcidb_tr *db_tr; 484 485 /* Disable interrupt */ 486 OWRITE(sc, FWOHCI_INTMASKCLR, ~0); 487 488 /* Now stopping all DMA channel */ 489 OWRITE(sc, OHCI_ARQCTLCLR, OHCI_CNTL_DMA_RUN); 490 OWRITE(sc, OHCI_ARSCTLCLR, OHCI_CNTL_DMA_RUN); 491 OWRITE(sc, OHCI_ATQCTLCLR, OHCI_CNTL_DMA_RUN); 492 OWRITE(sc, OHCI_ATSCTLCLR, OHCI_CNTL_DMA_RUN); 493 494 OWRITE(sc, OHCI_IR_MASKCLR, ~0); 495 for( i = 0 ; i < sc->fc.nisodma ; i ++ ){ 496 OWRITE(sc, OHCI_IRCTLCLR(i), OHCI_CNTL_DMA_RUN); 497 OWRITE(sc, OHCI_ITCTLCLR(i), OHCI_CNTL_DMA_RUN); 498 } 499 500 /* FLUSH FIFO and reset Transmitter/Reciever */ 501 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_RESET); 502 if (bootverbose) 503 device_printf(dev, "resetting OHCI..."); 504 i = 0; 505 while(OREAD(sc, OHCI_HCCCTL) & OHCI_HCC_RESET) { 506 if (i++ > 100) break; 507 DELAY(1000); 508 } 509 if (bootverbose) 510 printf("done (loop=%d)\n", i); 511 512 /* Probe phy */ 513 fwohci_probe_phy(sc, dev); 514 515 /* Probe link */ 516 reg = OREAD(sc, OHCI_BUS_OPT); 517 reg2 = reg | OHCI_BUSFNC; 518 max_rec = (reg & 0x0000f000) >> 12; 519 speed = (reg & 0x00000007); 520 device_printf(dev, "Link %s, max_rec %d bytes.\n", 521 linkspeed[speed], MAXREC(max_rec)); 522 /* XXX fix max_rec */ 523 sc->fc.maxrec = sc->fc.speed + 8; 524 if (max_rec != sc->fc.maxrec) { 525 reg2 = (reg2 & 0xffff0fff) | (sc->fc.maxrec << 12); 526 device_printf(dev, "max_rec %d -> %d\n", 527 MAXREC(max_rec), MAXREC(sc->fc.maxrec)); 528 } 529 if (bootverbose) 530 device_printf(dev, "BUS_OPT 0x%x -> 0x%x\n", reg, reg2); 531 OWRITE(sc, OHCI_BUS_OPT, reg2); 532 533 /* Initialize registers */ 534 OWRITE(sc, OHCI_CROMHDR, sc->fc.config_rom[0]); 535 OWRITE(sc, OHCI_CROMPTR, vtophys(&sc->fc.config_rom[0])); 536 OWRITE(sc, OHCI_HCCCTLCLR, OHCI_HCC_BIGEND); 537 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_POSTWR); 538 OWRITE(sc, OHCI_SID_BUF, vtophys(sc->fc.sid_buf)); 539 OWRITE(sc, OHCI_LNKCTL, OHCI_CNTL_SID); 540 fw_busreset(&sc->fc); 541 542 /* Enable link */ 543 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_LINKEN); 544 545 /* Force to start async RX DMA */ 546 sc->arrq.xferq.flag &= ~FWXFERQ_RUNNING; 547 sc->arrs.xferq.flag &= ~FWXFERQ_RUNNING; 548 fwohci_rx_enable(sc, &sc->arrq); 549 fwohci_rx_enable(sc, &sc->arrs); 550 551 /* Initialize async TX */ 552 OWRITE(sc, OHCI_ATQCTLCLR, OHCI_CNTL_DMA_RUN | OHCI_CNTL_DMA_DEAD); 553 OWRITE(sc, OHCI_ATSCTLCLR, OHCI_CNTL_DMA_RUN | OHCI_CNTL_DMA_DEAD); 554 /* AT Retries */ 555 OWRITE(sc, FWOHCI_RETRY, 556 /* CycleLimit PhyRespRetries ATRespRetries ATReqRetries */ 557 (0xffff << 16 ) | (0x0f << 8) | (0x0f << 4) | 0x0f) ; 558 for( i = 0, db_tr = sc->atrq.top; i < sc->atrq.ndb ; 559 i ++, db_tr = STAILQ_NEXT(db_tr, link)){ 560 db_tr->xfer = NULL; 561 } 562 for( i = 0, db_tr = sc->atrs.top; i < sc->atrs.ndb ; 563 i ++, db_tr = STAILQ_NEXT(db_tr, link)){ 564 db_tr->xfer = NULL; 565 } 566 567 568 /* Enable interrupt */ 569 OWRITE(sc, FWOHCI_INTMASK, 570 OHCI_INT_ERR | OHCI_INT_PHY_SID 571 | OHCI_INT_DMA_ATRQ | OHCI_INT_DMA_ATRS 572 | OHCI_INT_DMA_PRRQ | OHCI_INT_DMA_PRRS 573 | OHCI_INT_PHY_BUS_R | OHCI_INT_PW_ERR); 574 fwohci_set_intr(&sc->fc, 1); 575 576 } 577 578 int 579 fwohci_init(struct fwohci_softc *sc, device_t dev) 580 { 581 int i; 582 u_int32_t reg; 583 u_int8_t ui[8]; 584 585 reg = OREAD(sc, OHCI_VERSION); 586 device_printf(dev, "OHCI version %x.%x (ROM=%d)\n", 587 (reg>>16) & 0xff, reg & 0xff, (reg>>24) & 1); 588 589 /* Available Isochrounous DMA channel probe */ 590 OWRITE(sc, OHCI_IT_MASK, 0xffffffff); 591 OWRITE(sc, OHCI_IR_MASK, 0xffffffff); 592 reg = OREAD(sc, OHCI_IT_MASK) & OREAD(sc, OHCI_IR_MASK); 593 OWRITE(sc, OHCI_IT_MASKCLR, 0xffffffff); 594 OWRITE(sc, OHCI_IR_MASKCLR, 0xffffffff); 595 for (i = 0; i < 0x20; i++) 596 if ((reg & (1 << i)) == 0) 597 break; 598 sc->fc.nisodma = i; 599 device_printf(dev, "No. of Isochronous channel is %d.\n", i); 600 601 sc->fc.arq = &sc->arrq.xferq; 602 sc->fc.ars = &sc->arrs.xferq; 603 sc->fc.atq = &sc->atrq.xferq; 604 sc->fc.ats = &sc->atrs.xferq; 605 606 sc->arrq.xferq.start = NULL; 607 sc->arrs.xferq.start = NULL; 608 sc->atrq.xferq.start = fwohci_start_atq; 609 sc->atrs.xferq.start = fwohci_start_ats; 610 611 sc->arrq.xferq.drain = NULL; 612 sc->arrs.xferq.drain = NULL; 613 sc->atrq.xferq.drain = fwohci_drain_atq; 614 sc->atrs.xferq.drain = fwohci_drain_ats; 615 616 sc->arrq.ndesc = 1; 617 sc->arrs.ndesc = 1; 618 sc->atrq.ndesc = 8; /* equal to maximum of mbuf chains */ 619 sc->atrs.ndesc = 2; 620 621 sc->arrq.ndb = NDB; 622 sc->arrs.ndb = NDB / 2; 623 sc->atrq.ndb = NDB; 624 sc->atrs.ndb = NDB / 2; 625 626 sc->arrq.dummy = NULL; 627 sc->arrs.dummy = NULL; 628 sc->atrq.dummy = NULL; 629 sc->atrs.dummy = NULL; 630 for( i = 0 ; i < sc->fc.nisodma ; i ++ ){ 631 sc->fc.it[i] = &sc->it[i].xferq; 632 sc->fc.ir[i] = &sc->ir[i].xferq; 633 sc->it[i].ndb = 0; 634 sc->ir[i].ndb = 0; 635 } 636 637 sc->fc.tcode = tinfo; 638 639 sc->cromptr = (u_int32_t *) malloc(CROMSIZE * 2, M_FW, M_NOWAIT); 640 641 if(sc->cromptr == NULL){ 642 device_printf(dev, "cromptr alloc failed."); 643 return ENOMEM; 644 } 645 sc->fc.dev = dev; 646 sc->fc.config_rom = &(sc->cromptr[CROMSIZE/4]); 647 648 sc->fc.config_rom[1] = 0x31333934; 649 sc->fc.config_rom[2] = 0xf000a002; 650 sc->fc.config_rom[3] = OREAD(sc, OHCI_EUID_HI); 651 sc->fc.config_rom[4] = OREAD(sc, OHCI_EUID_LO); 652 sc->fc.config_rom[5] = 0; 653 sc->fc.config_rom[0] = (4 << 24) | (5 << 16); 654 655 sc->fc.config_rom[0] |= fw_crc16(&sc->fc.config_rom[1], 5*4); 656 657 658 /* SID recieve buffer must allign 2^11 */ 659 #define OHCI_SIDSIZE (1 << 11) 660 sc->fc.sid_buf = (u_int32_t *) malloc(OHCI_SIDSIZE, M_FW, M_NOWAIT); 661 if (sc->fc.sid_buf == NULL) { 662 device_printf(dev, "sid_buf alloc failed.\n"); 663 return ENOMEM; 664 } 665 if (((vm_offset_t) sc->fc.sid_buf & (OHCI_SIDSIZE - 1)) != 0) { 666 device_printf(dev, "sid_buf(%p) not aligned.\n", 667 sc->fc.sid_buf); 668 return ENOMEM; 669 } 670 671 fwohci_db_init(&sc->arrq); 672 if ((sc->arrq.flags & FWOHCI_DBCH_INIT) == 0) 673 return ENOMEM; 674 675 fwohci_db_init(&sc->arrs); 676 if ((sc->arrs.flags & FWOHCI_DBCH_INIT) == 0) 677 return ENOMEM; 678 679 fwohci_db_init(&sc->atrq); 680 if ((sc->atrq.flags & FWOHCI_DBCH_INIT) == 0) 681 return ENOMEM; 682 683 fwohci_db_init(&sc->atrs); 684 if ((sc->atrs.flags & FWOHCI_DBCH_INIT) == 0) 685 return ENOMEM; 686 687 sc->fc.eui.hi = OREAD(sc, FWOHCIGUID_H); 688 sc->fc.eui.lo = OREAD(sc, FWOHCIGUID_L); 689 for( i = 0 ; i < 8 ; i ++) 690 ui[i] = FW_EUI64_BYTE(&sc->fc.eui,i); 691 device_printf(dev, "EUI64 %02x:%02x:%02x:%02x:%02x:%02x:%02x:%02x\n", 692 ui[0], ui[1], ui[2], ui[3], ui[4], ui[5], ui[6], ui[7]); 693 694 sc->fc.ioctl = fwohci_ioctl; 695 sc->fc.cyctimer = fwohci_cyctimer; 696 sc->fc.set_bmr = fwohci_set_bus_manager; 697 sc->fc.ibr = fwohci_ibr; 698 sc->fc.irx_enable = fwohci_irx_enable; 699 sc->fc.irx_disable = fwohci_irx_disable; 700 701 sc->fc.itx_enable = fwohci_itxbuf_enable; 702 sc->fc.itx_disable = fwohci_itx_disable; 703 sc->fc.irx_post = fwohci_irx_post; 704 sc->fc.itx_post = NULL; 705 sc->fc.timeout = fwohci_timeout; 706 sc->fc.poll = fwohci_poll; 707 sc->fc.set_intr = fwohci_set_intr; 708 709 fw_init(&sc->fc); 710 fwohci_reset(sc, dev); 711 712 return 0; 713 } 714 715 void 716 fwohci_timeout(void *arg) 717 { 718 struct fwohci_softc *sc; 719 720 sc = (struct fwohci_softc *)arg; 721 } 722 723 u_int32_t 724 fwohci_cyctimer(struct firewire_comm *fc) 725 { 726 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 727 return(OREAD(sc, OHCI_CYCLETIMER)); 728 } 729 730 int 731 fwohci_detach(struct fwohci_softc *sc, device_t dev) 732 { 733 int i; 734 735 if (sc->fc.sid_buf != NULL) 736 free((void *)(uintptr_t)sc->fc.sid_buf, M_FW); 737 if (sc->cromptr != NULL) 738 free((void *)sc->cromptr, M_FW); 739 740 fwohci_db_free(&sc->arrq); 741 fwohci_db_free(&sc->arrs); 742 743 fwohci_db_free(&sc->atrq); 744 fwohci_db_free(&sc->atrs); 745 746 for( i = 0 ; i < sc->fc.nisodma ; i ++ ){ 747 fwohci_db_free(&sc->it[i]); 748 fwohci_db_free(&sc->ir[i]); 749 } 750 751 return 0; 752 } 753 754 #define LAST_DB(dbtr, db) do { \ 755 struct fwohcidb_tr *_dbtr = (dbtr); \ 756 int _cnt = _dbtr->dbcnt; \ 757 db = &_dbtr->db[ (_cnt > 2) ? (_cnt -1) : 0]; \ 758 } while (0) 759 760 static void 761 fwohci_start(struct fwohci_softc *sc, struct fwohci_dbch *dbch) 762 { 763 int i, s; 764 int tcode, hdr_len, hdr_off, len; 765 int fsegment = -1; 766 u_int32_t off; 767 struct fw_xfer *xfer; 768 struct fw_pkt *fp; 769 volatile struct fwohci_txpkthdr *ohcifp; 770 struct fwohcidb_tr *db_tr; 771 volatile struct fwohcidb *db; 772 struct mbuf *m; 773 struct tcode_info *info; 774 static int maxdesc=0; 775 776 if(&sc->atrq == dbch){ 777 off = OHCI_ATQOFF; 778 }else if(&sc->atrs == dbch){ 779 off = OHCI_ATSOFF; 780 }else{ 781 return; 782 } 783 784 if (dbch->flags & FWOHCI_DBCH_FULL) 785 return; 786 787 s = splfw(); 788 db_tr = dbch->top; 789 txloop: 790 xfer = STAILQ_FIRST(&dbch->xferq.q); 791 if(xfer == NULL){ 792 goto kick; 793 } 794 if(dbch->xferq.queued == 0 ){ 795 device_printf(sc->fc.dev, "TX queue empty\n"); 796 } 797 STAILQ_REMOVE_HEAD(&dbch->xferq.q, link); 798 db_tr->xfer = xfer; 799 xfer->state = FWXF_START; 800 dbch->xferq.packets++; 801 802 fp = (struct fw_pkt *)(xfer->send.buf + xfer->send.off); 803 tcode = fp->mode.common.tcode; 804 805 ohcifp = (volatile struct fwohci_txpkthdr *) db_tr->db[1].db.immed; 806 info = &tinfo[tcode]; 807 hdr_len = hdr_off = info->hdr_len; 808 /* fw_asyreq must pass valid send.len */ 809 len = xfer->send.len; 810 for( i = 0 ; i < hdr_off ; i+= 4){ 811 ohcifp->mode.ld[i/4] = ntohl(fp->mode.ld[i/4]); 812 } 813 ohcifp->mode.common.spd = xfer->spd; 814 if (tcode == FWTCODE_STREAM ){ 815 hdr_len = 8; 816 ohcifp->mode.stream.len = ntohs(fp->mode.stream.len); 817 } else if (tcode == FWTCODE_PHY) { 818 hdr_len = 12; 819 ohcifp->mode.ld[1] = ntohl(fp->mode.ld[1]); 820 ohcifp->mode.ld[2] = ntohl(fp->mode.ld[2]); 821 ohcifp->mode.common.spd = 0; 822 ohcifp->mode.common.tcode = FWOHCITCODE_PHY; 823 } else { 824 ohcifp->mode.asycomm.dst = ntohs(fp->mode.hdr.dst); 825 ohcifp->mode.asycomm.srcbus = OHCI_ASYSRCBUS; 826 ohcifp->mode.asycomm.tlrt |= FWRETRY_X; 827 } 828 db = &db_tr->db[0]; 829 db->db.desc.control = OHCI_OUTPUT_MORE | OHCI_KEY_ST2; 830 db->db.desc.reqcount = hdr_len; 831 db->db.desc.status = 0; 832 /* Specify bound timer of asy. responce */ 833 if(&sc->atrs == dbch){ 834 db->db.desc.count 835 = (OREAD(sc, OHCI_CYCLETIMER) >> 12) + (1 << 13); 836 } 837 838 again: 839 db_tr->dbcnt = 2; 840 db = &db_tr->db[db_tr->dbcnt]; 841 if(len > hdr_off){ 842 if (xfer->mbuf == NULL) { 843 db->db.desc.addr 844 = vtophys(xfer->send.buf + xfer->send.off) + hdr_off; 845 db->db.desc.control = OHCI_OUTPUT_MORE; 846 db->db.desc.reqcount = len - hdr_off; 847 db->db.desc.status = 0; 848 849 db_tr->dbcnt++; 850 } else { 851 int mchain=0; 852 /* XXX we can handle only 6 (=8-2) mbuf chains */ 853 for (m = xfer->mbuf; m != NULL; m = m->m_next) { 854 if (m->m_len == 0) 855 /* unrecoverable error could occur. */ 856 continue; 857 mchain++; 858 if (db_tr->dbcnt >= dbch->ndesc) 859 continue; 860 db->db.desc.addr 861 = vtophys(mtod(m, caddr_t)); 862 db->db.desc.control = OHCI_OUTPUT_MORE; 863 db->db.desc.reqcount = m->m_len; 864 db->db.desc.status = 0; 865 db++; 866 db_tr->dbcnt++; 867 } 868 if (mchain > dbch->ndesc - 2) { 869 struct mbuf *m_new; 870 if (bootverbose) 871 device_printf(sc->fc.dev, 872 "too long mbuf chain(%d)\n", 873 mchain); 874 m_new = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 875 if (m_new != NULL) { 876 m_copydata(xfer->mbuf, 0, 877 xfer->mbuf->m_pkthdr.len, 878 mtod(m_new, caddr_t)); 879 m_new->m_pkthdr.len = m_new->m_len = 880 xfer->mbuf->m_pkthdr.len; 881 m_freem(xfer->mbuf); 882 xfer->mbuf = m_new; 883 goto again; 884 } 885 device_printf(sc->fc.dev, "m_getcl failed.\n"); 886 } 887 } 888 } 889 if (maxdesc < db_tr->dbcnt) { 890 maxdesc = db_tr->dbcnt; 891 if (bootverbose) 892 device_printf(sc->fc.dev, "maxdesc: %d\n", maxdesc); 893 } 894 /* last db */ 895 LAST_DB(db_tr, db); 896 db->db.desc.control |= OHCI_OUTPUT_LAST 897 | OHCI_INTERRUPT_ALWAYS 898 | OHCI_BRANCH_ALWAYS; 899 db->db.desc.depend = vtophys(STAILQ_NEXT(db_tr, link)->db); 900 901 if(fsegment == -1 ) 902 fsegment = db_tr->dbcnt; 903 if (dbch->pdb_tr != NULL) { 904 LAST_DB(dbch->pdb_tr, db); 905 db->db.desc.depend |= db_tr->dbcnt; 906 } 907 dbch->pdb_tr = db_tr; 908 db_tr = STAILQ_NEXT(db_tr, link); 909 if(db_tr != dbch->bottom){ 910 goto txloop; 911 } else { 912 device_printf(sc->fc.dev, "fwohci_start: lack of db_trq\n"); 913 dbch->flags |= FWOHCI_DBCH_FULL; 914 } 915 kick: 916 /* kick asy q */ 917 918 if(dbch->xferq.flag & FWXFERQ_RUNNING) { 919 OWRITE(sc, OHCI_DMACTL(off), OHCI_CNTL_DMA_WAKE); 920 } else { 921 if (bootverbose) 922 device_printf(sc->fc.dev, "start AT DMA status=%x\n", 923 OREAD(sc, OHCI_DMACTL(off))); 924 OWRITE(sc, OHCI_DMACMD(off), vtophys(dbch->top->db) | fsegment); 925 OWRITE(sc, OHCI_DMACTL(off), OHCI_CNTL_DMA_RUN); 926 dbch->xferq.flag |= FWXFERQ_RUNNING; 927 } 928 929 dbch->top = db_tr; 930 splx(s); 931 return; 932 } 933 934 static void 935 fwohci_drain_atq(struct firewire_comm *fc, struct fw_xfer *xfer) 936 { 937 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 938 fwohci_drain(&sc->fc, xfer, &(sc->atrq)); 939 return; 940 } 941 942 static void 943 fwohci_drain_ats(struct firewire_comm *fc, struct fw_xfer *xfer) 944 { 945 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 946 fwohci_drain(&sc->fc, xfer, &(sc->atrs)); 947 return; 948 } 949 950 static void 951 fwohci_start_atq(struct firewire_comm *fc) 952 { 953 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 954 fwohci_start( sc, &(sc->atrq)); 955 return; 956 } 957 958 static void 959 fwohci_start_ats(struct firewire_comm *fc) 960 { 961 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 962 fwohci_start( sc, &(sc->atrs)); 963 return; 964 } 965 966 void 967 fwohci_txd(struct fwohci_softc *sc, struct fwohci_dbch *dbch) 968 { 969 int s, err = 0; 970 struct fwohcidb_tr *tr; 971 volatile struct fwohcidb *db; 972 struct fw_xfer *xfer; 973 u_int32_t off; 974 u_int stat; 975 int packets; 976 struct firewire_comm *fc = (struct firewire_comm *)sc; 977 if(&sc->atrq == dbch){ 978 off = OHCI_ATQOFF; 979 }else if(&sc->atrs == dbch){ 980 off = OHCI_ATSOFF; 981 }else{ 982 return; 983 } 984 s = splfw(); 985 tr = dbch->bottom; 986 packets = 0; 987 while(dbch->xferq.queued > 0){ 988 LAST_DB(tr, db); 989 if(!(db->db.desc.status & OHCI_CNTL_DMA_ACTIVE)){ 990 if (fc->status != FWBUSRESET) 991 /* maybe out of order?? */ 992 goto out; 993 } 994 if(db->db.desc.status & OHCI_CNTL_DMA_DEAD) { 995 #ifdef OHCI_DEBUG 996 dump_dma(sc, ch); 997 dump_db(sc, ch); 998 #endif 999 /* Stop DMA */ 1000 OWRITE(sc, OHCI_DMACTLCLR(off), OHCI_CNTL_DMA_RUN); 1001 device_printf(sc->fc.dev, "force reset AT FIFO\n"); 1002 OWRITE(sc, OHCI_HCCCTLCLR, OHCI_HCC_LINKEN); 1003 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_LPS | OHCI_HCC_LINKEN); 1004 OWRITE(sc, OHCI_DMACTLCLR(off), OHCI_CNTL_DMA_RUN); 1005 } 1006 stat = db->db.desc.status & FWOHCIEV_MASK; 1007 switch(stat){ 1008 case FWOHCIEV_ACKPEND: 1009 case FWOHCIEV_ACKCOMPL: 1010 err = 0; 1011 break; 1012 case FWOHCIEV_ACKBSA: 1013 case FWOHCIEV_ACKBSB: 1014 case FWOHCIEV_ACKBSX: 1015 device_printf(sc->fc.dev, "txd err=%2x %s\n", stat, fwohcicode[stat]); 1016 err = EBUSY; 1017 break; 1018 case FWOHCIEV_FLUSHED: 1019 case FWOHCIEV_ACKTARD: 1020 device_printf(sc->fc.dev, "txd err=%2x %s\n", stat, fwohcicode[stat]); 1021 err = EAGAIN; 1022 break; 1023 case FWOHCIEV_MISSACK: 1024 case FWOHCIEV_UNDRRUN: 1025 case FWOHCIEV_OVRRUN: 1026 case FWOHCIEV_DESCERR: 1027 case FWOHCIEV_DTRDERR: 1028 case FWOHCIEV_TIMEOUT: 1029 case FWOHCIEV_TCODERR: 1030 case FWOHCIEV_UNKNOWN: 1031 case FWOHCIEV_ACKDERR: 1032 case FWOHCIEV_ACKTERR: 1033 default: 1034 device_printf(sc->fc.dev, "txd err=%2x %s\n", 1035 stat, fwohcicode[stat]); 1036 err = EINVAL; 1037 break; 1038 } 1039 if (tr->xfer != NULL) { 1040 xfer = tr->xfer; 1041 xfer->state = FWXF_SENT; 1042 if (err == EBUSY && fc->status != FWBUSRESET) { 1043 xfer->state = FWXF_BUSY; 1044 switch (xfer->act_type) { 1045 case FWACT_XFER: 1046 xfer->resp = err; 1047 if (xfer->retry_req != NULL) 1048 xfer->retry_req(xfer); 1049 else 1050 fw_xfer_done(xfer); 1051 break; 1052 default: 1053 break; 1054 } 1055 } else if (stat != FWOHCIEV_ACKPEND) { 1056 if (stat != FWOHCIEV_ACKCOMPL) 1057 xfer->state = FWXF_SENTERR; 1058 xfer->resp = err; 1059 switch (xfer->act_type) { 1060 case FWACT_XFER: 1061 fw_xfer_done(xfer); 1062 break; 1063 default: 1064 break; 1065 } 1066 } 1067 /* 1068 * The watchdog timer takes care of split 1069 * transcation timeout for ACKPEND case. 1070 */ 1071 } 1072 dbch->xferq.queued --; 1073 tr->xfer = NULL; 1074 1075 packets ++; 1076 tr = STAILQ_NEXT(tr, link); 1077 dbch->bottom = tr; 1078 } 1079 out: 1080 if ((dbch->flags & FWOHCI_DBCH_FULL) && packets > 0) { 1081 printf("make free slot\n"); 1082 dbch->flags &= ~FWOHCI_DBCH_FULL; 1083 fwohci_start(sc, dbch); 1084 } 1085 splx(s); 1086 } 1087 1088 static void 1089 fwohci_drain(struct firewire_comm *fc, struct fw_xfer *xfer, struct fwohci_dbch *dbch) 1090 { 1091 int i, s, found=0; 1092 struct fwohcidb_tr *tr; 1093 1094 if(xfer->state != FWXF_START) return; 1095 1096 s = splfw(); 1097 tr = dbch->bottom; 1098 for (i = 0; i < dbch->xferq.queued; i ++) { 1099 if(tr->xfer == xfer){ 1100 tr->xfer = NULL; 1101 #if 0 1102 dbch->xferq.queued --; 1103 /* XXX */ 1104 if (tr == dbch->bottom) 1105 dbch->bottom = STAILQ_NEXT(tr, link); 1106 if (dbch->flags & FWOHCI_DBCH_FULL) { 1107 printf("fwohci_drain: make slot\n"); 1108 dbch->flags &= ~FWOHCI_DBCH_FULL; 1109 fwohci_start((struct fwohci_softc *)fc, dbch); 1110 } 1111 #endif 1112 found ++; 1113 break; 1114 } 1115 tr = STAILQ_NEXT(tr, link); 1116 } 1117 splx(s); 1118 if (!found) 1119 device_printf(fc->dev, "fwochi_drain: xfer not found\n"); 1120 return; 1121 } 1122 1123 static void 1124 fwohci_db_free(struct fwohci_dbch *dbch) 1125 { 1126 struct fwohcidb_tr *db_tr; 1127 int idb, i; 1128 1129 if ((dbch->flags & FWOHCI_DBCH_INIT) == 0) 1130 return; 1131 1132 if(!(dbch->xferq.flag & FWXFERQ_EXTBUF)){ 1133 for(db_tr = STAILQ_FIRST(&dbch->db_trq), idb = 0; 1134 idb < dbch->ndb; 1135 db_tr = STAILQ_NEXT(db_tr, link), idb++){ 1136 if (db_tr->buf != NULL) { 1137 free(db_tr->buf, M_FW); 1138 db_tr->buf = NULL; 1139 } 1140 } 1141 } 1142 dbch->ndb = 0; 1143 db_tr = STAILQ_FIRST(&dbch->db_trq); 1144 for (i = 0; i < dbch->npages; i++) 1145 free(dbch->pages[i], M_FW); 1146 free(db_tr, M_FW); 1147 STAILQ_INIT(&dbch->db_trq); 1148 dbch->flags &= ~FWOHCI_DBCH_INIT; 1149 } 1150 1151 static void 1152 fwohci_db_init(struct fwohci_dbch *dbch) 1153 { 1154 int idb; 1155 struct fwohcidb_tr *db_tr; 1156 int ndbpp, i, j; 1157 1158 if ((dbch->flags & FWOHCI_DBCH_INIT) != 0) 1159 goto out; 1160 1161 /* allocate DB entries and attach one to each DMA channels */ 1162 /* DB entry must start at 16 bytes bounary. */ 1163 STAILQ_INIT(&dbch->db_trq); 1164 db_tr = (struct fwohcidb_tr *) 1165 malloc(sizeof(struct fwohcidb_tr) * dbch->ndb, 1166 M_FW, M_ZERO); 1167 if(db_tr == NULL){ 1168 printf("fwohci_db_init: malloc(1) failed\n"); 1169 return; 1170 } 1171 1172 ndbpp = PAGE_SIZE / (sizeof(struct fwohcidb) * dbch->ndesc); 1173 dbch->npages = (dbch->ndb + ndbpp - 1)/ ndbpp; 1174 if (firewire_debug) 1175 printf("ndesc: %d, ndbpp: %d, ndb: %d, npages: %d\n", 1176 dbch->ndesc, ndbpp, dbch->ndb, dbch->npages); 1177 if (dbch->npages > FWOHCI_DBCH_MAX_PAGES) { 1178 printf("npages(%d) > DBCH_MAX_PAGES(%d)\n", 1179 dbch->npages, FWOHCI_DBCH_MAX_PAGES); 1180 return; 1181 } 1182 for (i = 0; i < dbch->npages; i++) { 1183 dbch->pages[i] = malloc(PAGE_SIZE, M_FW, M_ZERO); 1184 if (dbch->pages[i] == NULL) { 1185 printf("fwohci_db_init: malloc(2) failed\n"); 1186 for (j = 0; j < i; j ++) 1187 free(dbch->pages[j], M_FW); 1188 free(db_tr, M_FW); 1189 return; 1190 } 1191 } 1192 /* Attach DB to DMA ch. */ 1193 for(idb = 0 ; idb < dbch->ndb ; idb++){ 1194 db_tr->dbcnt = 0; 1195 db_tr->db = (struct fwohcidb *)dbch->pages[idb/ndbpp] 1196 + dbch->ndesc * (idb % ndbpp); 1197 STAILQ_INSERT_TAIL(&dbch->db_trq, db_tr, link); 1198 if (!(dbch->xferq.flag & FWXFERQ_PACKET) && 1199 dbch->xferq.bnpacket != 0) { 1200 if (idb % dbch->xferq.bnpacket == 0) 1201 dbch->xferq.bulkxfer[idb / dbch->xferq.bnpacket 1202 ].start = (caddr_t)db_tr; 1203 if ((idb + 1) % dbch->xferq.bnpacket == 0) 1204 dbch->xferq.bulkxfer[idb / dbch->xferq.bnpacket 1205 ].end = (caddr_t)db_tr; 1206 } 1207 db_tr++; 1208 } 1209 STAILQ_LAST(&dbch->db_trq, fwohcidb_tr,link)->link.stqe_next 1210 = STAILQ_FIRST(&dbch->db_trq); 1211 out: 1212 dbch->frag.buf = NULL; 1213 dbch->frag.len = 0; 1214 dbch->frag.plen = 0; 1215 dbch->xferq.queued = 0; 1216 dbch->pdb_tr = NULL; 1217 dbch->top = STAILQ_FIRST(&dbch->db_trq); 1218 dbch->bottom = dbch->top; 1219 dbch->flags = FWOHCI_DBCH_INIT; 1220 } 1221 1222 static int 1223 fwohci_itx_disable(struct firewire_comm *fc, int dmach) 1224 { 1225 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 1226 int dummy; 1227 1228 OWRITE(sc, OHCI_ITCTLCLR(dmach), OHCI_CNTL_DMA_RUN); 1229 OWRITE(sc, OHCI_IT_MASKCLR, 1 << dmach); 1230 OWRITE(sc, OHCI_IT_STATCLR, 1 << dmach); 1231 /* XXX we cannot free buffers until the DMA really stops */ 1232 tsleep((void *)&dummy, FWPRI, "fwitxd", hz); 1233 fwohci_db_free(&sc->it[dmach]); 1234 sc->it[dmach].xferq.flag &= ~FWXFERQ_RUNNING; 1235 return 0; 1236 } 1237 1238 static int 1239 fwohci_irx_disable(struct firewire_comm *fc, int dmach) 1240 { 1241 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 1242 int dummy; 1243 1244 OWRITE(sc, OHCI_IRCTLCLR(dmach), OHCI_CNTL_DMA_RUN); 1245 OWRITE(sc, OHCI_IR_MASKCLR, 1 << dmach); 1246 OWRITE(sc, OHCI_IR_STATCLR, 1 << dmach); 1247 /* XXX we cannot free buffers until the DMA really stops */ 1248 tsleep((void *)&dummy, FWPRI, "fwirxd", hz); 1249 if(sc->ir[dmach].dummy != NULL){ 1250 free(sc->ir[dmach].dummy, M_FW); 1251 } 1252 sc->ir[dmach].dummy = NULL; 1253 fwohci_db_free(&sc->ir[dmach]); 1254 sc->ir[dmach].xferq.flag &= ~FWXFERQ_RUNNING; 1255 return 0; 1256 } 1257 1258 static void 1259 fwohci_irx_post (struct firewire_comm *fc , u_int32_t *qld) 1260 { 1261 qld[0] = ntohl(qld[0]); 1262 return; 1263 } 1264 1265 static int 1266 fwohci_irxpp_enable(struct firewire_comm *fc, int dmach) 1267 { 1268 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 1269 int err = 0; 1270 unsigned short tag, ich; 1271 1272 tag = (sc->ir[dmach].xferq.flag >> 6) & 3; 1273 ich = sc->ir[dmach].xferq.flag & 0x3f; 1274 1275 #if 0 1276 if(STAILQ_FIRST(&fc->ir[dmach]->q) != NULL){ 1277 wakeup(fc->ir[dmach]); 1278 return err; 1279 } 1280 #endif 1281 1282 OWRITE(sc, OHCI_IRMATCH(dmach), tagbit[tag] | ich); 1283 if(!(sc->ir[dmach].xferq.flag & FWXFERQ_RUNNING)){ 1284 sc->ir[dmach].xferq.queued = 0; 1285 sc->ir[dmach].ndb = NDB; 1286 sc->ir[dmach].xferq.psize = PAGE_SIZE; 1287 sc->ir[dmach].ndesc = 1; 1288 fwohci_db_init(&sc->ir[dmach]); 1289 if ((sc->ir[dmach].flags & FWOHCI_DBCH_INIT) == 0) 1290 return ENOMEM; 1291 err = fwohci_rx_enable(sc, &sc->ir[dmach]); 1292 } 1293 if(err){ 1294 device_printf(sc->fc.dev, "err in IRX setting\n"); 1295 return err; 1296 } 1297 if(!(OREAD(sc, OHCI_IRCTL(dmach)) & OHCI_CNTL_DMA_ACTIVE)){ 1298 OWRITE(sc, OHCI_IRCTLCLR(dmach), OHCI_CNTL_DMA_RUN); 1299 OWRITE(sc, OHCI_IR_MASKCLR, 1 << dmach); 1300 OWRITE(sc, OHCI_IR_STATCLR, 1 << dmach); 1301 OWRITE(sc, OHCI_IR_MASK, 1 << dmach); 1302 OWRITE(sc, OHCI_IRCTLCLR(dmach), 0xf8000000); 1303 OWRITE(sc, OHCI_IRCTL(dmach), OHCI_CNTL_ISOHDR); 1304 OWRITE(sc, OHCI_IRCMD(dmach), 1305 vtophys(sc->ir[dmach].top->db) | 1); 1306 OWRITE(sc, OHCI_IRCTL(dmach), OHCI_CNTL_DMA_RUN); 1307 OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_DMA_IR); 1308 } 1309 return err; 1310 } 1311 1312 static int 1313 fwohci_tx_enable(struct fwohci_softc *sc, struct fwohci_dbch *dbch) 1314 { 1315 int err = 0; 1316 int idb, z, i, dmach = 0; 1317 u_int32_t off = NULL; 1318 struct fwohcidb_tr *db_tr; 1319 volatile struct fwohcidb *db; 1320 1321 if(!(dbch->xferq.flag & FWXFERQ_EXTBUF)){ 1322 err = EINVAL; 1323 return err; 1324 } 1325 z = dbch->ndesc; 1326 for(dmach = 0 ; dmach < sc->fc.nisodma ; dmach++){ 1327 if( &sc->it[dmach] == dbch){ 1328 off = OHCI_ITOFF(dmach); 1329 break; 1330 } 1331 } 1332 if(off == NULL){ 1333 err = EINVAL; 1334 return err; 1335 } 1336 if(dbch->xferq.flag & FWXFERQ_RUNNING) 1337 return err; 1338 dbch->xferq.flag |= FWXFERQ_RUNNING; 1339 for( i = 0, dbch->bottom = dbch->top; i < (dbch->ndb - 1); i++){ 1340 dbch->bottom = STAILQ_NEXT(dbch->bottom, link); 1341 } 1342 db_tr = dbch->top; 1343 for( idb = 0 ; idb < dbch->ndb ; idb ++){ 1344 fwohci_add_tx_buf(db_tr, 1345 dbch->xferq.psize, dbch->xferq.flag, 1346 dbch->xferq.buf + dbch->xferq.psize * idb); 1347 if(STAILQ_NEXT(db_tr, link) == NULL){ 1348 break; 1349 } 1350 db = db_tr->db; 1351 db[0].db.desc.depend = db[db_tr->dbcnt - 1].db.desc.depend 1352 = vtophys(STAILQ_NEXT(db_tr, link)->db) | z; 1353 if(dbch->xferq.flag & FWXFERQ_EXTBUF){ 1354 if(((idb + 1 ) % dbch->xferq.bnpacket) == 0){ 1355 db[db_tr->dbcnt - 1].db.desc.control 1356 |= OHCI_INTERRUPT_ALWAYS; 1357 /* OHCI 1.1 and above */ 1358 db[0].db.desc.control |= OHCI_INTERRUPT_ALWAYS; 1359 #if 0 1360 db[0].db.desc.depend &= ~0xf; 1361 db[db_tr->dbcnt - 1].db.desc.depend &= ~0xf; 1362 #endif 1363 } 1364 } 1365 db_tr = STAILQ_NEXT(db_tr, link); 1366 } 1367 dbch->bottom->db[db_tr->dbcnt - 1].db.desc.depend &= 0xfffffff0; 1368 return err; 1369 } 1370 1371 static int 1372 fwohci_rx_enable(struct fwohci_softc *sc, struct fwohci_dbch *dbch) 1373 { 1374 int err = 0; 1375 int idb, z, i, dmach = 0, ldesc; 1376 u_int32_t off = NULL; 1377 struct fwohcidb_tr *db_tr; 1378 volatile struct fwohcidb *db; 1379 1380 z = dbch->ndesc; 1381 if(&sc->arrq == dbch){ 1382 off = OHCI_ARQOFF; 1383 }else if(&sc->arrs == dbch){ 1384 off = OHCI_ARSOFF; 1385 }else{ 1386 for(dmach = 0 ; dmach < sc->fc.nisodma ; dmach++){ 1387 if( &sc->ir[dmach] == dbch){ 1388 off = OHCI_IROFF(dmach); 1389 break; 1390 } 1391 } 1392 } 1393 if(off == NULL){ 1394 err = EINVAL; 1395 return err; 1396 } 1397 if(dbch->xferq.flag & FWXFERQ_STREAM){ 1398 if(dbch->xferq.flag & FWXFERQ_RUNNING) 1399 return err; 1400 }else{ 1401 if(dbch->xferq.flag & FWXFERQ_RUNNING){ 1402 err = EBUSY; 1403 return err; 1404 } 1405 } 1406 dbch->xferq.flag |= FWXFERQ_RUNNING; 1407 dbch->top = STAILQ_FIRST(&dbch->db_trq); 1408 for( i = 0, dbch->bottom = dbch->top; i < (dbch->ndb - 1); i++){ 1409 dbch->bottom = STAILQ_NEXT(dbch->bottom, link); 1410 } 1411 db_tr = dbch->top; 1412 for( idb = 0 ; idb < dbch->ndb ; idb ++){ 1413 if(!(dbch->xferq.flag & FWXFERQ_EXTBUF)){ 1414 fwohci_add_rx_buf(db_tr, 1415 dbch->xferq.psize, dbch->xferq.flag, 0, NULL); 1416 }else{ 1417 fwohci_add_rx_buf(db_tr, 1418 dbch->xferq.psize, dbch->xferq.flag, 1419 dbch->xferq.bulkxfer[idb 1420 / dbch->xferq.bnpacket].buf 1421 + dbch->xferq.psize * 1422 (idb % dbch->xferq.bnpacket), 1423 dbch->dummy + sizeof(u_int32_t) * idb); 1424 } 1425 if(STAILQ_NEXT(db_tr, link) == NULL){ 1426 break; 1427 } 1428 db = db_tr->db; 1429 ldesc = db_tr->dbcnt - 1; 1430 db[ldesc].db.desc.depend 1431 = vtophys(STAILQ_NEXT(db_tr, link)->db) | z; 1432 if(dbch->xferq.flag & FWXFERQ_EXTBUF){ 1433 if(((idb + 1 ) % dbch->xferq.bnpacket) == 0){ 1434 db[ldesc].db.desc.control 1435 |= OHCI_INTERRUPT_ALWAYS; 1436 db[ldesc].db.desc.depend &= ~0xf; 1437 } 1438 } 1439 db_tr = STAILQ_NEXT(db_tr, link); 1440 } 1441 dbch->bottom->db[db_tr->dbcnt - 1].db.desc.depend &= 0xfffffff0; 1442 dbch->buf_offset = 0; 1443 if(dbch->xferq.flag & FWXFERQ_STREAM){ 1444 return err; 1445 }else{ 1446 OWRITE(sc, OHCI_DMACMD(off), vtophys(dbch->top->db) | z); 1447 } 1448 OWRITE(sc, OHCI_DMACTL(off), OHCI_CNTL_DMA_RUN); 1449 return err; 1450 } 1451 1452 static int 1453 fwochi_next_cycle(struct firewire_comm *fc, int cycle_now) 1454 { 1455 int sec, cycle, cycle_match; 1456 1457 cycle = cycle_now & 0x1fff; 1458 sec = cycle_now >> 13; 1459 #define CYCLE_MOD 0x10 1460 #define CYCLE_DELAY 8 /* min delay to start DMA */ 1461 cycle = cycle + CYCLE_DELAY; 1462 if (cycle >= 8000) { 1463 sec ++; 1464 cycle -= 8000; 1465 } 1466 cycle = ((cycle + CYCLE_MOD - 1) / CYCLE_MOD) * CYCLE_MOD; 1467 if (cycle >= 8000) { 1468 sec ++; 1469 if (cycle == 8000) 1470 cycle = 0; 1471 else 1472 cycle = CYCLE_MOD; 1473 } 1474 cycle_match = ((sec << 13) | cycle) & 0x7ffff; 1475 1476 return(cycle_match); 1477 } 1478 1479 static int 1480 fwohci_itxbuf_enable(struct firewire_comm *fc, int dmach) 1481 { 1482 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 1483 int err = 0; 1484 unsigned short tag, ich; 1485 struct fwohci_dbch *dbch; 1486 int cycle_match, cycle_now, s, ldesc; 1487 u_int32_t stat; 1488 struct fw_bulkxfer *first, *chunk, *prev; 1489 struct fw_xferq *it; 1490 1491 dbch = &sc->it[dmach]; 1492 it = &dbch->xferq; 1493 1494 tag = (it->flag >> 6) & 3; 1495 ich = it->flag & 0x3f; 1496 if ((dbch->flags & FWOHCI_DBCH_INIT) == 0) { 1497 dbch->ndb = it->bnpacket * it->bnchunk; 1498 dbch->ndesc = 3; 1499 fwohci_db_init(dbch); 1500 if ((dbch->flags & FWOHCI_DBCH_INIT) == 0) 1501 return ENOMEM; 1502 err = fwohci_tx_enable(sc, dbch); 1503 } 1504 if(err) 1505 return err; 1506 1507 ldesc = dbch->ndesc - 1; 1508 s = splfw(); 1509 prev = STAILQ_LAST(&it->stdma, fw_bulkxfer, link); 1510 while ((chunk = STAILQ_FIRST(&it->stvalid)) != NULL) { 1511 volatile struct fwohcidb *db; 1512 1513 fwohci_txbufdb(sc, dmach, chunk); 1514 #if 0 1515 db = ((struct fwohcidb_tr *)(chunk->end))->db; 1516 db[ldesc].db.desc.status = db[0].db.desc.status = 0; 1517 db[ldesc].db.desc.count = db[0].db.desc.count = 0; 1518 db[ldesc].db.desc.depend &= ~0xf; 1519 db[0].db.desc.depend &= ~0xf; 1520 #endif 1521 if (prev != NULL) { 1522 db = ((struct fwohcidb_tr *)(prev->end))->db; 1523 db[ldesc].db.desc.control |= OHCI_BRANCH_ALWAYS; 1524 #if 0 /* if bulkxfer->npacket changes */ 1525 db[ldesc].db.desc.depend = db[0].db.desc.depend = 1526 vtophys(((struct fwohcidb_tr *) 1527 (chunk->start))->db) | dbch->ndesc; 1528 #else 1529 db[0].db.desc.depend |= dbch->ndesc; 1530 db[ldesc].db.desc.depend |= dbch->ndesc; 1531 #endif 1532 } 1533 STAILQ_REMOVE_HEAD(&it->stvalid, link); 1534 STAILQ_INSERT_TAIL(&it->stdma, chunk, link); 1535 prev = chunk; 1536 } 1537 splx(s); 1538 stat = OREAD(sc, OHCI_ITCTL(dmach)); 1539 if (stat & (OHCI_CNTL_DMA_ACTIVE | OHCI_CNTL_CYCMATCH_S)) 1540 return 0; 1541 1542 OWRITE(sc, OHCI_ITCTLCLR(dmach), OHCI_CNTL_DMA_RUN); 1543 OWRITE(sc, OHCI_IT_MASKCLR, 1 << dmach); 1544 OWRITE(sc, OHCI_IT_STATCLR, 1 << dmach); 1545 OWRITE(sc, OHCI_IT_MASK, 1 << dmach); 1546 1547 first = STAILQ_FIRST(&it->stdma); 1548 OWRITE(sc, OHCI_ITCMD(dmach), vtophys(((struct fwohcidb_tr *) 1549 (first->start))->db) | dbch->ndesc); 1550 if (firewire_debug) 1551 printf("fwohci_itxbuf_enable: kick 0x%08x\n", stat); 1552 if ((stat & OHCI_CNTL_DMA_RUN) == 0) { 1553 #if 1 1554 /* Don't start until all chunks are buffered */ 1555 if (STAILQ_FIRST(&it->stfree) != NULL) 1556 goto out; 1557 #endif 1558 #ifdef FWXFERQ_DV 1559 #define CYCLE_OFFSET 1 1560 if(dbch->xferq.flag & FWXFERQ_DV){ 1561 struct fw_pkt *fp; 1562 struct fwohcidb_tr *db_tr; 1563 1564 db_tr = (struct fwohcidb_tr *)dbch->xferq.stdma->start; 1565 fp = (struct fw_pkt *)db_tr->buf; 1566 dbch->xferq.dvoffset = CYCLE_OFFSET; 1567 fp->mode.ld[2] |= htonl(dbch->xferq.dvoffset << 12); 1568 } 1569 #endif 1570 /* Clear cycle match counter bits */ 1571 OWRITE(sc, OHCI_ITCTLCLR(dmach), 0xffff0000); 1572 OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_DMA_IT); 1573 1574 /* 2bit second + 13bit cycle */ 1575 cycle_now = (fc->cyctimer(fc) >> 12) & 0x7fff; 1576 cycle_match = fwochi_next_cycle(fc, cycle_now); 1577 1578 OWRITE(sc, OHCI_ITCTL(dmach), 1579 OHCI_CNTL_CYCMATCH_S | (cycle_match << 16) 1580 | OHCI_CNTL_DMA_RUN); 1581 if (firewire_debug) 1582 printf("cycle_match: 0x%04x->0x%04x\n", 1583 cycle_now, cycle_match); 1584 } else if ((stat & OHCI_CNTL_CYCMATCH_S) == 0) { 1585 device_printf(sc->fc.dev, 1586 "IT DMA underrun (0x%08x)\n", stat); 1587 OWRITE(sc, OHCI_ITCTL(dmach), OHCI_CNTL_DMA_RUN); 1588 } 1589 out: 1590 return err; 1591 } 1592 1593 static int 1594 fwohci_irxbuf_enable(struct firewire_comm *fc, int dmach) 1595 { 1596 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 1597 int err = 0, s, ldesc; 1598 unsigned short tag, ich; 1599 u_int32_t stat; 1600 struct fwohci_dbch *dbch; 1601 struct fw_bulkxfer *first, *prev, *chunk; 1602 struct fw_xferq *ir; 1603 1604 dbch = &sc->ir[dmach]; 1605 ir = &dbch->xferq; 1606 1607 if ((ir->flag & FWXFERQ_RUNNING) == 0) { 1608 tag = (ir->flag >> 6) & 3; 1609 ich = ir->flag & 0x3f; 1610 OWRITE(sc, OHCI_IRMATCH(dmach), tagbit[tag] | ich); 1611 1612 ir->queued = 0; 1613 dbch->ndb = ir->bnpacket * ir->bnchunk; 1614 dbch->dummy = malloc(sizeof(u_int32_t) * dbch->ndb, 1615 M_FW, 0); 1616 if (dbch->dummy == NULL) { 1617 err = ENOMEM; 1618 return err; 1619 } 1620 dbch->ndesc = 2; 1621 fwohci_db_init(dbch); 1622 if ((dbch->flags & FWOHCI_DBCH_INIT) == 0) 1623 return ENOMEM; 1624 err = fwohci_rx_enable(sc, dbch); 1625 } 1626 if(err) 1627 return err; 1628 1629 first = STAILQ_FIRST(&ir->stfree); 1630 if (first == NULL) { 1631 device_printf(fc->dev, "IR DMA no free chunk\n"); 1632 return 0; 1633 } 1634 1635 ldesc = dbch->ndesc - 1; 1636 s = splfw(); 1637 prev = STAILQ_LAST(&ir->stdma, fw_bulkxfer, link); 1638 while ((chunk = STAILQ_FIRST(&ir->stfree)) != NULL) { 1639 volatile struct fwohcidb *db; 1640 1641 #if 1 /* XXX for if_fwe */ 1642 db = ((struct fwohcidb_tr *)(chunk->start))->db; 1643 db[ldesc].db.desc.addr = vtophys(chunk->buf); 1644 #endif 1645 db = ((struct fwohcidb_tr *)(chunk->end))->db; 1646 db[ldesc].db.desc.status = db[ldesc].db.desc.count = 0; 1647 db[ldesc].db.desc.depend &= ~0xf; 1648 if (prev != NULL) { 1649 db = ((struct fwohcidb_tr *)(prev->end))->db; 1650 #if 0 1651 db[ldesc].db.desc.depend = 1652 vtophys(((struct fwohcidb_tr *) 1653 (chunk->start))->db) | dbch->ndesc; 1654 #else 1655 db[ldesc].db.desc.depend |= dbch->ndesc; 1656 #endif 1657 } 1658 STAILQ_REMOVE_HEAD(&ir->stfree, link); 1659 STAILQ_INSERT_TAIL(&ir->stdma, chunk, link); 1660 prev = chunk; 1661 } 1662 splx(s); 1663 stat = OREAD(sc, OHCI_IRCTL(dmach)); 1664 if (stat & OHCI_CNTL_DMA_ACTIVE) 1665 return 0; 1666 if (stat & OHCI_CNTL_DMA_RUN) { 1667 OWRITE(sc, OHCI_IRCTLCLR(dmach), OHCI_CNTL_DMA_RUN); 1668 device_printf(sc->fc.dev, "IR DMA overrun (0x%08x)\n", stat); 1669 } 1670 1671 OWRITE(sc, OHCI_IR_MASKCLR, 1 << dmach); 1672 OWRITE(sc, OHCI_IR_STATCLR, 1 << dmach); 1673 OWRITE(sc, OHCI_IR_MASK, 1 << dmach); 1674 OWRITE(sc, OHCI_IRCTLCLR(dmach), 0xf0000000); 1675 OWRITE(sc, OHCI_IRCTL(dmach), OHCI_CNTL_ISOHDR); 1676 OWRITE(sc, OHCI_IRCMD(dmach), 1677 vtophys(((struct fwohcidb_tr *)(first->start))->db) 1678 | dbch->ndesc); 1679 OWRITE(sc, OHCI_IRCTL(dmach), OHCI_CNTL_DMA_RUN); 1680 OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_DMA_IR); 1681 return err; 1682 } 1683 1684 static int 1685 fwohci_irx_enable(struct firewire_comm *fc, int dmach) 1686 { 1687 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 1688 int err = 0; 1689 1690 if(sc->ir[dmach].xferq.flag & FWXFERQ_PACKET){ 1691 err = fwohci_irxpp_enable(fc, dmach); 1692 return err; 1693 }else{ 1694 err = fwohci_irxbuf_enable(fc, dmach); 1695 return err; 1696 } 1697 } 1698 1699 int 1700 fwohci_stop(struct fwohci_softc *sc, device_t dev) 1701 { 1702 u_int i; 1703 1704 /* Now stopping all DMA channel */ 1705 OWRITE(sc, OHCI_ARQCTLCLR, OHCI_CNTL_DMA_RUN); 1706 OWRITE(sc, OHCI_ARSCTLCLR, OHCI_CNTL_DMA_RUN); 1707 OWRITE(sc, OHCI_ATQCTLCLR, OHCI_CNTL_DMA_RUN); 1708 OWRITE(sc, OHCI_ATSCTLCLR, OHCI_CNTL_DMA_RUN); 1709 1710 for( i = 0 ; i < sc->fc.nisodma ; i ++ ){ 1711 OWRITE(sc, OHCI_IRCTLCLR(i), OHCI_CNTL_DMA_RUN); 1712 OWRITE(sc, OHCI_ITCTLCLR(i), OHCI_CNTL_DMA_RUN); 1713 } 1714 1715 /* FLUSH FIFO and reset Transmitter/Reciever */ 1716 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_RESET); 1717 1718 /* Stop interrupt */ 1719 OWRITE(sc, FWOHCI_INTMASKCLR, 1720 OHCI_INT_EN | OHCI_INT_ERR | OHCI_INT_PHY_SID 1721 | OHCI_INT_PHY_INT 1722 | OHCI_INT_DMA_ATRQ | OHCI_INT_DMA_ATRS 1723 | OHCI_INT_DMA_PRRQ | OHCI_INT_DMA_PRRS 1724 | OHCI_INT_DMA_ARRQ | OHCI_INT_DMA_ARRS 1725 | OHCI_INT_PHY_BUS_R); 1726 /* XXX Link down? Bus reset? */ 1727 return 0; 1728 } 1729 1730 int 1731 fwohci_resume(struct fwohci_softc *sc, device_t dev) 1732 { 1733 int i; 1734 1735 fwohci_reset(sc, dev); 1736 /* XXX resume isochronus receive automatically. (how about TX?) */ 1737 for(i = 0; i < sc->fc.nisodma; i ++) { 1738 if((sc->ir[i].xferq.flag & FWXFERQ_RUNNING) != 0) { 1739 device_printf(sc->fc.dev, 1740 "resume iso receive ch: %d\n", i); 1741 sc->ir[i].xferq.flag &= ~FWXFERQ_RUNNING; 1742 sc->fc.irx_enable(&sc->fc, i); 1743 } 1744 } 1745 1746 bus_generic_resume(dev); 1747 sc->fc.ibr(&sc->fc); 1748 return 0; 1749 } 1750 1751 #define ACK_ALL 1752 static void 1753 fwohci_intr_body(struct fwohci_softc *sc, u_int32_t stat, int count) 1754 { 1755 u_int32_t irstat, itstat; 1756 u_int i; 1757 struct firewire_comm *fc = (struct firewire_comm *)sc; 1758 1759 #ifdef OHCI_DEBUG 1760 if(stat & OREAD(sc, FWOHCI_INTMASK)) 1761 device_printf(fc->dev, "INTERRUPT < %s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s> 0x%08x, 0x%08x\n", 1762 stat & OHCI_INT_EN ? "DMA_EN ":"", 1763 stat & OHCI_INT_PHY_REG ? "PHY_REG ":"", 1764 stat & OHCI_INT_CYC_LONG ? "CYC_LONG ":"", 1765 stat & OHCI_INT_ERR ? "INT_ERR ":"", 1766 stat & OHCI_INT_CYC_ERR ? "CYC_ERR ":"", 1767 stat & OHCI_INT_CYC_LOST ? "CYC_LOST ":"", 1768 stat & OHCI_INT_CYC_64SECOND ? "CYC_64SECOND ":"", 1769 stat & OHCI_INT_CYC_START ? "CYC_START ":"", 1770 stat & OHCI_INT_PHY_INT ? "PHY_INT ":"", 1771 stat & OHCI_INT_PHY_BUS_R ? "BUS_RESET ":"", 1772 stat & OHCI_INT_PHY_SID ? "SID ":"", 1773 stat & OHCI_INT_LR_ERR ? "DMA_LR_ERR ":"", 1774 stat & OHCI_INT_PW_ERR ? "DMA_PW_ERR ":"", 1775 stat & OHCI_INT_DMA_IR ? "DMA_IR ":"", 1776 stat & OHCI_INT_DMA_IT ? "DMA_IT " :"", 1777 stat & OHCI_INT_DMA_PRRS ? "DMA_PRRS " :"", 1778 stat & OHCI_INT_DMA_PRRQ ? "DMA_PRRQ " :"", 1779 stat & OHCI_INT_DMA_ARRS ? "DMA_ARRS " :"", 1780 stat & OHCI_INT_DMA_ARRQ ? "DMA_ARRQ " :"", 1781 stat & OHCI_INT_DMA_ATRS ? "DMA_ATRS " :"", 1782 stat & OHCI_INT_DMA_ATRQ ? "DMA_ATRQ " :"", 1783 stat, OREAD(sc, FWOHCI_INTMASK) 1784 ); 1785 #endif 1786 /* Bus reset */ 1787 if(stat & OHCI_INT_PHY_BUS_R ){ 1788 if (fc->status == FWBUSRESET) 1789 goto busresetout; 1790 /* Disable bus reset interrupt until sid recv. */ 1791 OWRITE(sc, FWOHCI_INTMASKCLR, OHCI_INT_PHY_BUS_R); 1792 1793 device_printf(fc->dev, "BUS reset\n"); 1794 OWRITE(sc, FWOHCI_INTMASKCLR, OHCI_INT_CYC_LOST); 1795 OWRITE(sc, OHCI_LNKCTLCLR, OHCI_CNTL_CYCSRC); 1796 1797 OWRITE(sc, OHCI_ATQCTLCLR, OHCI_CNTL_DMA_RUN); 1798 sc->atrq.xferq.flag &= ~FWXFERQ_RUNNING; 1799 OWRITE(sc, OHCI_ATSCTLCLR, OHCI_CNTL_DMA_RUN); 1800 sc->atrs.xferq.flag &= ~FWXFERQ_RUNNING; 1801 1802 #ifndef ACK_ALL 1803 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_PHY_BUS_R); 1804 #endif 1805 fw_busreset(fc); 1806 } 1807 busresetout: 1808 if((stat & OHCI_INT_DMA_IR )){ 1809 #ifndef ACK_ALL 1810 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_IR); 1811 #endif 1812 irstat = OREAD(sc, OHCI_IR_STAT); 1813 OWRITE(sc, OHCI_IR_STATCLR, irstat); 1814 for(i = 0; i < fc->nisodma ; i++){ 1815 struct fwohci_dbch *dbch; 1816 1817 if((irstat & (1 << i)) != 0){ 1818 dbch = &sc->ir[i]; 1819 if ((dbch->xferq.flag & FWXFERQ_OPEN) == 0) { 1820 device_printf(sc->fc.dev, 1821 "dma(%d) not active\n", i); 1822 continue; 1823 } 1824 if (dbch->xferq.flag & FWXFERQ_PACKET) { 1825 fwohci_ircv(sc, dbch, count); 1826 } else { 1827 fwohci_rbuf_update(sc, i); 1828 } 1829 } 1830 } 1831 } 1832 if((stat & OHCI_INT_DMA_IT )){ 1833 #ifndef ACK_ALL 1834 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_IT); 1835 #endif 1836 itstat = OREAD(sc, OHCI_IT_STAT); 1837 OWRITE(sc, OHCI_IT_STATCLR, itstat); 1838 for(i = 0; i < fc->nisodma ; i++){ 1839 if((itstat & (1 << i)) != 0){ 1840 fwohci_tbuf_update(sc, i); 1841 } 1842 } 1843 } 1844 if((stat & OHCI_INT_DMA_PRRS )){ 1845 #ifndef ACK_ALL 1846 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_PRRS); 1847 #endif 1848 #if 0 1849 dump_dma(sc, ARRS_CH); 1850 dump_db(sc, ARRS_CH); 1851 #endif 1852 fwohci_arcv(sc, &sc->arrs, count); 1853 } 1854 if((stat & OHCI_INT_DMA_PRRQ )){ 1855 #ifndef ACK_ALL 1856 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_PRRQ); 1857 #endif 1858 #if 0 1859 dump_dma(sc, ARRQ_CH); 1860 dump_db(sc, ARRQ_CH); 1861 #endif 1862 fwohci_arcv(sc, &sc->arrq, count); 1863 } 1864 if(stat & OHCI_INT_PHY_SID){ 1865 caddr_t buf; 1866 int plen; 1867 1868 #ifndef ACK_ALL 1869 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_PHY_SID); 1870 #endif 1871 /* Enable bus reset interrupt */ 1872 OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_PHY_BUS_R); 1873 /* Allow async. request to us */ 1874 OWRITE(sc, OHCI_AREQHI, 1 << 31); 1875 /* XXX insecure ?? */ 1876 OWRITE(sc, OHCI_PREQHI, 0x7fffffff); 1877 OWRITE(sc, OHCI_PREQLO, 0xffffffff); 1878 OWRITE(sc, OHCI_PREQUPPER, 0x10000); 1879 /* 1880 ** Checking whether the node is root or not. If root, turn on 1881 ** cycle master. 1882 */ 1883 device_printf(fc->dev, "node_id = 0x%08x, ", OREAD(sc, FWOHCI_NODEID)); 1884 if(!(OREAD(sc, FWOHCI_NODEID) & OHCI_NODE_VALID)){ 1885 printf("Bus reset failure\n"); 1886 goto sidout; 1887 } 1888 if( OREAD(sc, FWOHCI_NODEID) & OHCI_NODE_ROOT ){ 1889 printf("CYCLEMASTER mode\n"); 1890 OWRITE(sc, OHCI_LNKCTL, 1891 OHCI_CNTL_CYCMTR | OHCI_CNTL_CYCTIMER); 1892 }else{ 1893 printf("non CYCLEMASTER mode\n"); 1894 OWRITE(sc, OHCI_LNKCTLCLR, OHCI_CNTL_CYCMTR); 1895 OWRITE(sc, OHCI_LNKCTL, OHCI_CNTL_CYCTIMER); 1896 } 1897 fc->nodeid = OREAD(sc, FWOHCI_NODEID) & 0x3f; 1898 1899 plen = OREAD(sc, OHCI_SID_CNT) & OHCI_SID_CNT_MASK; 1900 if (plen < 4 || plen > OHCI_SIDSIZE) { 1901 device_printf(fc->dev, "invalid SID len = %d\n", plen); 1902 goto sidout; 1903 } 1904 plen -= 4; /* chop control info */ 1905 buf = malloc(OHCI_SIDSIZE, M_FW, M_NOWAIT); 1906 if(buf == NULL) goto sidout; 1907 bcopy((void *)(uintptr_t)(volatile void *)(fc->sid_buf + 1), 1908 buf, plen); 1909 #if 1 1910 /* pending all pre-bus_reset packets */ 1911 fwohci_txd(sc, &sc->atrq); 1912 fwohci_txd(sc, &sc->atrs); 1913 fwohci_arcv(sc, &sc->arrs, -1); 1914 fwohci_arcv(sc, &sc->arrq, -1); 1915 fw_drain_txq(fc); 1916 #endif 1917 fw_sidrcv(fc, buf, plen, 0); 1918 } 1919 sidout: 1920 if((stat & OHCI_INT_DMA_ATRQ )){ 1921 #ifndef ACK_ALL 1922 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_ATRQ); 1923 #endif 1924 fwohci_txd(sc, &(sc->atrq)); 1925 } 1926 if((stat & OHCI_INT_DMA_ATRS )){ 1927 #ifndef ACK_ALL 1928 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_ATRS); 1929 #endif 1930 fwohci_txd(sc, &(sc->atrs)); 1931 } 1932 if((stat & OHCI_INT_PW_ERR )){ 1933 #ifndef ACK_ALL 1934 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_PW_ERR); 1935 #endif 1936 device_printf(fc->dev, "posted write error\n"); 1937 } 1938 if((stat & OHCI_INT_ERR )){ 1939 #ifndef ACK_ALL 1940 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_ERR); 1941 #endif 1942 device_printf(fc->dev, "unrecoverable error\n"); 1943 } 1944 if((stat & OHCI_INT_PHY_INT)) { 1945 #ifndef ACK_ALL 1946 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_PHY_INT); 1947 #endif 1948 device_printf(fc->dev, "phy int\n"); 1949 } 1950 1951 return; 1952 } 1953 1954 void 1955 fwohci_intr(void *arg) 1956 { 1957 struct fwohci_softc *sc = (struct fwohci_softc *)arg; 1958 u_int32_t stat, bus_reset = 0; 1959 1960 if (!(sc->intmask & OHCI_INT_EN)) { 1961 /* polling mode */ 1962 return; 1963 } 1964 1965 while ((stat = OREAD(sc, FWOHCI_INTSTAT)) != 0) { 1966 if (stat == 0xffffffff) { 1967 device_printf(sc->fc.dev, 1968 "device physically ejected?\n"); 1969 return; 1970 } 1971 #ifdef ACK_ALL 1972 OWRITE(sc, FWOHCI_INTSTATCLR, stat); 1973 #endif 1974 /* We cannot clear bus reset event during bus reset phase */ 1975 if ((stat & ~bus_reset) == 0) 1976 return; 1977 bus_reset = stat & OHCI_INT_PHY_BUS_R; 1978 fwohci_intr_body(sc, stat, -1); 1979 } 1980 } 1981 1982 static void 1983 fwohci_poll(struct firewire_comm *fc, int quick, int count) 1984 { 1985 int s; 1986 u_int32_t stat; 1987 struct fwohci_softc *sc; 1988 1989 1990 sc = (struct fwohci_softc *)fc; 1991 stat = OHCI_INT_DMA_IR | OHCI_INT_DMA_IT | 1992 OHCI_INT_DMA_PRRS | OHCI_INT_DMA_PRRQ | 1993 OHCI_INT_DMA_ATRQ | OHCI_INT_DMA_ATRS; 1994 #if 0 1995 if (!quick) { 1996 #else 1997 if (1) { 1998 #endif 1999 stat = OREAD(sc, FWOHCI_INTSTAT); 2000 if (stat == 0) 2001 return; 2002 if (stat == 0xffffffff) { 2003 device_printf(sc->fc.dev, 2004 "device physically ejected?\n"); 2005 return; 2006 } 2007 #ifdef ACK_ALL 2008 OWRITE(sc, FWOHCI_INTSTATCLR, stat); 2009 #endif 2010 } 2011 s = splfw(); 2012 fwohci_intr_body(sc, stat, count); 2013 splx(s); 2014 } 2015 2016 static void 2017 fwohci_set_intr(struct firewire_comm *fc, int enable) 2018 { 2019 struct fwohci_softc *sc; 2020 2021 sc = (struct fwohci_softc *)fc; 2022 if (bootverbose) 2023 device_printf(sc->fc.dev, "fwohci_set_intr: %d\n", enable); 2024 if (enable) { 2025 sc->intmask |= OHCI_INT_EN; 2026 OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_EN); 2027 } else { 2028 sc->intmask &= ~OHCI_INT_EN; 2029 OWRITE(sc, FWOHCI_INTMASKCLR, OHCI_INT_EN); 2030 } 2031 } 2032 2033 static void 2034 fwohci_tbuf_update(struct fwohci_softc *sc, int dmach) 2035 { 2036 struct firewire_comm *fc = &sc->fc; 2037 volatile struct fwohcidb *db; 2038 struct fw_bulkxfer *chunk; 2039 struct fw_xferq *it; 2040 u_int32_t stat, count; 2041 int s, w=0; 2042 2043 it = fc->it[dmach]; 2044 s = splfw(); /* unnecessary ? */ 2045 while ((chunk = STAILQ_FIRST(&it->stdma)) != NULL) { 2046 db = ((struct fwohcidb_tr *)(chunk->end))->db; 2047 stat = db[sc->it[dmach].ndesc - 1].db.desc.status; 2048 db = ((struct fwohcidb_tr *)(chunk->start))->db; 2049 count = db[sc->it[dmach].ndesc - 1].db.desc.count; 2050 if (stat == 0) 2051 break; 2052 STAILQ_REMOVE_HEAD(&it->stdma, link); 2053 switch (stat & FWOHCIEV_MASK){ 2054 case FWOHCIEV_ACKCOMPL: 2055 #if 0 2056 device_printf(fc->dev, "0x%08x\n", count); 2057 #endif 2058 break; 2059 default: 2060 device_printf(fc->dev, 2061 "Isochronous transmit err %02x\n", stat); 2062 } 2063 STAILQ_INSERT_TAIL(&it->stfree, chunk, link); 2064 w++; 2065 } 2066 splx(s); 2067 if (w) 2068 wakeup(it); 2069 } 2070 2071 static void 2072 fwohci_rbuf_update(struct fwohci_softc *sc, int dmach) 2073 { 2074 struct firewire_comm *fc = &sc->fc; 2075 volatile struct fwohcidb *db; 2076 struct fw_bulkxfer *chunk; 2077 struct fw_xferq *ir; 2078 u_int32_t stat; 2079 int s, w=0; 2080 2081 ir = fc->ir[dmach]; 2082 s = splfw(); 2083 while ((chunk = STAILQ_FIRST(&ir->stdma)) != NULL) { 2084 db = ((struct fwohcidb_tr *)(chunk->end))->db; 2085 stat = db[sc->ir[dmach].ndesc - 1].db.desc.status; 2086 if (stat == 0) 2087 break; 2088 STAILQ_REMOVE_HEAD(&ir->stdma, link); 2089 STAILQ_INSERT_TAIL(&ir->stvalid, chunk, link); 2090 switch (stat & FWOHCIEV_MASK) { 2091 case FWOHCIEV_ACKCOMPL: 2092 chunk->resp = 0; 2093 break; 2094 default: 2095 chunk->resp = EINVAL; 2096 device_printf(fc->dev, 2097 "Isochronous receive err %02x\n", stat); 2098 } 2099 w++; 2100 } 2101 splx(s); 2102 if (w) { 2103 if (ir->flag & FWXFERQ_HANDLER) 2104 ir->hand(ir); 2105 else 2106 wakeup(ir); 2107 } 2108 } 2109 2110 void 2111 dump_dma(struct fwohci_softc *sc, u_int32_t ch) 2112 { 2113 u_int32_t off, cntl, stat, cmd, match; 2114 2115 if(ch == 0){ 2116 off = OHCI_ATQOFF; 2117 }else if(ch == 1){ 2118 off = OHCI_ATSOFF; 2119 }else if(ch == 2){ 2120 off = OHCI_ARQOFF; 2121 }else if(ch == 3){ 2122 off = OHCI_ARSOFF; 2123 }else if(ch < IRX_CH){ 2124 off = OHCI_ITCTL(ch - ITX_CH); 2125 }else{ 2126 off = OHCI_IRCTL(ch - IRX_CH); 2127 } 2128 cntl = stat = OREAD(sc, off); 2129 cmd = OREAD(sc, off + 0xc); 2130 match = OREAD(sc, off + 0x10); 2131 2132 device_printf(sc->fc.dev, "dma ch %1x:dma regs 0x%08x 0x%08x 0x%08x 0x%08x \n", 2133 ch, 2134 cntl, 2135 stat, 2136 cmd, 2137 match); 2138 stat &= 0xffff ; 2139 if(stat & 0xff00){ 2140 device_printf(sc->fc.dev, "dma %d ch:%s%s%s%s%s%s %s(%x)\n", 2141 ch, 2142 stat & OHCI_CNTL_DMA_RUN ? "RUN," : "", 2143 stat & OHCI_CNTL_DMA_WAKE ? "WAKE," : "", 2144 stat & OHCI_CNTL_DMA_DEAD ? "DEAD," : "", 2145 stat & OHCI_CNTL_DMA_ACTIVE ? "ACTIVE," : "", 2146 stat & OHCI_CNTL_DMA_BT ? "BRANCH," : "", 2147 stat & OHCI_CNTL_DMA_BAD ? "BADDMA," : "", 2148 fwohcicode[stat & 0x1f], 2149 stat & 0x1f 2150 ); 2151 }else{ 2152 device_printf(sc->fc.dev, "dma %d ch: Nostat\n", ch); 2153 } 2154 } 2155 2156 void 2157 dump_db(struct fwohci_softc *sc, u_int32_t ch) 2158 { 2159 struct fwohci_dbch *dbch; 2160 struct fwohcidb_tr *cp = NULL, *pp, *np; 2161 volatile struct fwohcidb *curr = NULL, *prev, *next = NULL; 2162 int idb, jdb; 2163 u_int32_t cmd, off; 2164 if(ch == 0){ 2165 off = OHCI_ATQOFF; 2166 dbch = &sc->atrq; 2167 }else if(ch == 1){ 2168 off = OHCI_ATSOFF; 2169 dbch = &sc->atrs; 2170 }else if(ch == 2){ 2171 off = OHCI_ARQOFF; 2172 dbch = &sc->arrq; 2173 }else if(ch == 3){ 2174 off = OHCI_ARSOFF; 2175 dbch = &sc->arrs; 2176 }else if(ch < IRX_CH){ 2177 off = OHCI_ITCTL(ch - ITX_CH); 2178 dbch = &sc->it[ch - ITX_CH]; 2179 }else { 2180 off = OHCI_IRCTL(ch - IRX_CH); 2181 dbch = &sc->ir[ch - IRX_CH]; 2182 } 2183 cmd = OREAD(sc, off + 0xc); 2184 2185 if( dbch->ndb == 0 ){ 2186 device_printf(sc->fc.dev, "No DB is attached ch=%d\n", ch); 2187 return; 2188 } 2189 pp = dbch->top; 2190 prev = pp->db; 2191 for(idb = 0 ; idb < dbch->ndb ; idb ++ ){ 2192 if(pp == NULL){ 2193 curr = NULL; 2194 goto outdb; 2195 } 2196 cp = STAILQ_NEXT(pp, link); 2197 if(cp == NULL){ 2198 curr = NULL; 2199 goto outdb; 2200 } 2201 np = STAILQ_NEXT(cp, link); 2202 if(cp == NULL) break; 2203 for(jdb = 0 ; jdb < dbch->ndesc ; jdb ++ ){ 2204 if((cmd & 0xfffffff0) 2205 == vtophys(&(cp->db[jdb]))){ 2206 curr = cp->db; 2207 if(np != NULL){ 2208 next = np->db; 2209 }else{ 2210 next = NULL; 2211 } 2212 goto outdb; 2213 } 2214 } 2215 pp = STAILQ_NEXT(pp, link); 2216 prev = pp->db; 2217 } 2218 outdb: 2219 if( curr != NULL){ 2220 printf("Prev DB %d\n", ch); 2221 print_db(prev, ch, dbch->ndesc); 2222 printf("Current DB %d\n", ch); 2223 print_db(curr, ch, dbch->ndesc); 2224 printf("Next DB %d\n", ch); 2225 print_db(next, ch, dbch->ndesc); 2226 }else{ 2227 printf("dbdump err ch = %d cmd = 0x%08x\n", ch, cmd); 2228 } 2229 return; 2230 } 2231 2232 void 2233 print_db(volatile struct fwohcidb *db, u_int32_t ch, u_int32_t max) 2234 { 2235 fwohcireg_t stat; 2236 int i, key; 2237 2238 if(db == NULL){ 2239 printf("No Descriptor is found\n"); 2240 return; 2241 } 2242 2243 printf("ch = %d\n%8s %s %s %s %s %4s %8s %8s %4s:%4s\n", 2244 ch, 2245 "Current", 2246 "OP ", 2247 "KEY", 2248 "INT", 2249 "BR ", 2250 "len", 2251 "Addr", 2252 "Depend", 2253 "Stat", 2254 "Cnt"); 2255 for( i = 0 ; i <= max ; i ++){ 2256 key = db[i].db.desc.control & OHCI_KEY_MASK; 2257 #if __FreeBSD_version >= 500000 2258 printf("%08tx %s %s %s %s %5d %08x %08x %04x:%04x", 2259 #else 2260 printf("%08x %s %s %s %s %5d %08x %08x %04x:%04x", 2261 #endif 2262 vtophys(&db[i]), 2263 dbcode[(db[i].db.desc.control >> 12) & 0xf], 2264 dbkey[(db[i].db.desc.control >> 8) & 0x7], 2265 dbcond[(db[i].db.desc.control >> 4) & 0x3], 2266 dbcond[(db[i].db.desc.control >> 2) & 0x3], 2267 db[i].db.desc.reqcount, 2268 db[i].db.desc.addr, 2269 db[i].db.desc.depend, 2270 db[i].db.desc.status, 2271 db[i].db.desc.count); 2272 stat = db[i].db.desc.status; 2273 if(stat & 0xff00){ 2274 printf(" %s%s%s%s%s%s %s(%x)\n", 2275 stat & OHCI_CNTL_DMA_RUN ? "RUN," : "", 2276 stat & OHCI_CNTL_DMA_WAKE ? "WAKE," : "", 2277 stat & OHCI_CNTL_DMA_DEAD ? "DEAD," : "", 2278 stat & OHCI_CNTL_DMA_ACTIVE ? "ACTIVE," : "", 2279 stat & OHCI_CNTL_DMA_BT ? "BRANCH," : "", 2280 stat & OHCI_CNTL_DMA_BAD ? "BADDMA," : "", 2281 fwohcicode[stat & 0x1f], 2282 stat & 0x1f 2283 ); 2284 }else{ 2285 printf(" Nostat\n"); 2286 } 2287 if(key == OHCI_KEY_ST2 ){ 2288 printf("0x%08x 0x%08x 0x%08x 0x%08x\n", 2289 db[i+1].db.immed[0], 2290 db[i+1].db.immed[1], 2291 db[i+1].db.immed[2], 2292 db[i+1].db.immed[3]); 2293 } 2294 if(key == OHCI_KEY_DEVICE){ 2295 return; 2296 } 2297 if((db[i].db.desc.control & OHCI_BRANCH_MASK) 2298 == OHCI_BRANCH_ALWAYS){ 2299 return; 2300 } 2301 if((db[i].db.desc.control & OHCI_CMD_MASK) 2302 == OHCI_OUTPUT_LAST){ 2303 return; 2304 } 2305 if((db[i].db.desc.control & OHCI_CMD_MASK) 2306 == OHCI_INPUT_LAST){ 2307 return; 2308 } 2309 if(key == OHCI_KEY_ST2 ){ 2310 i++; 2311 } 2312 } 2313 return; 2314 } 2315 2316 void 2317 fwohci_ibr(struct firewire_comm *fc) 2318 { 2319 struct fwohci_softc *sc; 2320 u_int32_t fun; 2321 2322 device_printf(fc->dev, "Initiate bus reset\n"); 2323 sc = (struct fwohci_softc *)fc; 2324 2325 /* 2326 * Set root hold-off bit so that non cyclemaster capable node 2327 * shouldn't became the root node. 2328 */ 2329 #if 1 2330 fun = fwphy_rddata(sc, FW_PHY_IBR_REG); 2331 fun |= FW_PHY_IBR | FW_PHY_RHB; 2332 fun = fwphy_wrdata(sc, FW_PHY_IBR_REG, fun); 2333 #else /* Short bus reset */ 2334 fun = fwphy_rddata(sc, FW_PHY_ISBR_REG); 2335 fun |= FW_PHY_ISBR | FW_PHY_RHB; 2336 fun = fwphy_wrdata(sc, FW_PHY_ISBR_REG, fun); 2337 #endif 2338 } 2339 2340 void 2341 fwohci_txbufdb(struct fwohci_softc *sc, int dmach, struct fw_bulkxfer *bulkxfer) 2342 { 2343 struct fwohcidb_tr *db_tr, *fdb_tr; 2344 struct fwohci_dbch *dbch; 2345 volatile struct fwohcidb *db; 2346 struct fw_pkt *fp; 2347 volatile struct fwohci_txpkthdr *ohcifp; 2348 unsigned short chtag; 2349 int idb; 2350 2351 dbch = &sc->it[dmach]; 2352 chtag = sc->it[dmach].xferq.flag & 0xff; 2353 2354 db_tr = (struct fwohcidb_tr *)(bulkxfer->start); 2355 fdb_tr = (struct fwohcidb_tr *)(bulkxfer->end); 2356 /* 2357 device_printf(sc->fc.dev, "DB %08x %08x %08x\n", bulkxfer, vtophys(db_tr->db), vtophys(fdb_tr->db)); 2358 */ 2359 for( idb = 0 ; idb < bulkxfer->npacket ; idb ++){ 2360 db = db_tr->db; 2361 #if 0 2362 db[0].db.desc.control 2363 = OHCI_OUTPUT_MORE | OHCI_KEY_ST2; 2364 db[0].db.desc.reqcount = 8; 2365 #endif 2366 fp = (struct fw_pkt *)db_tr->buf; 2367 ohcifp = (volatile struct fwohci_txpkthdr *) db[1].db.immed; 2368 ohcifp->mode.ld[0] = ntohl(fp->mode.ld[0]); 2369 ohcifp->mode.stream.len = ntohs(fp->mode.stream.len); 2370 ohcifp->mode.stream.chtag = chtag; 2371 ohcifp->mode.stream.tcode = 0xa; 2372 ohcifp->mode.stream.spd = 0; 2373 2374 db[2].db.desc.reqcount = ntohs(fp->mode.stream.len); 2375 db[2].db.desc.status = 0; 2376 db[2].db.desc.count = 0; 2377 #if 0 /* if bulkxfer->npackets changes */ 2378 db[2].db.desc.control = OHCI_OUTPUT_LAST 2379 | OHCI_UPDATE 2380 | OHCI_BRANCH_ALWAYS; 2381 db[0].db.desc.depend = 2382 = db[dbch->ndesc - 1].db.desc.depend 2383 = vtophys(STAILQ_NEXT(db_tr, link)->db) | dbch->ndesc; 2384 #else 2385 db[0].db.desc.depend |= dbch->ndesc; 2386 db[dbch->ndesc - 1].db.desc.depend |= dbch->ndesc; 2387 #endif 2388 bulkxfer->end = (caddr_t)db_tr; 2389 db_tr = STAILQ_NEXT(db_tr, link); 2390 } 2391 db = ((struct fwohcidb_tr *)bulkxfer->end)->db; 2392 db[0].db.desc.depend &= ~0xf; 2393 db[dbch->ndesc - 1].db.desc.depend &= ~0xf; 2394 #if 0 /* if bulkxfer->npackets changes */ 2395 db[dbch->ndesc - 1].db.desc.control |= OHCI_INTERRUPT_ALWAYS; 2396 /* OHCI 1.1 and above */ 2397 db[0].db.desc.control |= OHCI_INTERRUPT_ALWAYS; 2398 #endif 2399 /* 2400 db_tr = (struct fwohcidb_tr *)bulkxfer->start; 2401 fdb_tr = (struct fwohcidb_tr *)bulkxfer->end; 2402 device_printf(sc->fc.dev, "DB %08x %3d %08x %08x\n", bulkxfer, bulkxfer->npacket, vtophys(db_tr->db), vtophys(fdb_tr->db)); 2403 */ 2404 return; 2405 } 2406 2407 static int 2408 fwohci_add_tx_buf(struct fwohcidb_tr *db_tr, unsigned short size, 2409 int mode, void *buf) 2410 { 2411 volatile struct fwohcidb *db = db_tr->db; 2412 int err = 0; 2413 if(buf == 0){ 2414 err = EINVAL; 2415 return err; 2416 } 2417 db_tr->buf = buf; 2418 db_tr->dbcnt = 3; 2419 db_tr->dummy = NULL; 2420 2421 db[0].db.desc.control = OHCI_OUTPUT_MORE | OHCI_KEY_ST2; 2422 db[0].db.desc.reqcount = 8; 2423 db[2].db.desc.addr = vtophys(buf) + sizeof(u_int32_t); 2424 db[2].db.desc.control = 2425 OHCI_OUTPUT_LAST | OHCI_UPDATE | OHCI_BRANCH_ALWAYS; 2426 #if 1 2427 db[0].db.desc.status = 0; 2428 db[0].db.desc.count = 0; 2429 db[2].db.desc.status = 0; 2430 db[2].db.desc.count = 0; 2431 #endif 2432 if( mode & FWXFERQ_STREAM ){ 2433 if(mode & FWXFERQ_PACKET ){ 2434 db[2].db.desc.control |= OHCI_INTERRUPT_ALWAYS; 2435 } 2436 } else { 2437 printf("fwohci_add_tx_buf: who calls me?"); 2438 } 2439 return 1; 2440 } 2441 2442 int 2443 fwohci_add_rx_buf(struct fwohcidb_tr *db_tr, unsigned short size, int mode, 2444 void *buf, void *dummy) 2445 { 2446 volatile struct fwohcidb *db = db_tr->db; 2447 int i; 2448 void *dbuf[2]; 2449 int dsiz[2]; 2450 2451 if(buf == 0){ 2452 buf = malloc(size, M_FW, M_NOWAIT); 2453 if(buf == NULL) return 0; 2454 db_tr->buf = buf; 2455 db_tr->dbcnt = 1; 2456 db_tr->dummy = NULL; 2457 dsiz[0] = size; 2458 dbuf[0] = buf; 2459 }else if(dummy == NULL){ 2460 db_tr->buf = buf; 2461 db_tr->dbcnt = 1; 2462 db_tr->dummy = NULL; 2463 dsiz[0] = size; 2464 dbuf[0] = buf; 2465 }else{ 2466 db_tr->buf = buf; 2467 db_tr->dbcnt = 2; 2468 db_tr->dummy = dummy; 2469 dsiz[0] = sizeof(u_int32_t); 2470 dsiz[1] = size; 2471 dbuf[0] = dummy; 2472 dbuf[1] = buf; 2473 } 2474 for(i = 0 ; i < db_tr->dbcnt ; i++){ 2475 db[i].db.desc.addr = vtophys(dbuf[i]) ; 2476 db[i].db.desc.control = OHCI_INPUT_MORE; 2477 db[i].db.desc.reqcount = dsiz[i]; 2478 if( mode & FWXFERQ_STREAM ){ 2479 db[i].db.desc.control |= OHCI_UPDATE; 2480 } 2481 db[i].db.desc.status = 0; 2482 db[i].db.desc.count = dsiz[i]; 2483 } 2484 if( mode & FWXFERQ_STREAM ){ 2485 db[db_tr->dbcnt - 1].db.desc.control |= OHCI_INPUT_LAST; 2486 if(mode & FWXFERQ_PACKET ){ 2487 db[db_tr->dbcnt - 1].db.desc.control 2488 |= OHCI_INTERRUPT_ALWAYS; 2489 } 2490 } 2491 db[db_tr->dbcnt - 1].db.desc.control |= OHCI_BRANCH_ALWAYS; 2492 return 1; 2493 } 2494 2495 static void 2496 fwohci_ircv(struct fwohci_softc *sc, struct fwohci_dbch *dbch, int count) 2497 { 2498 struct fwohcidb_tr *db_tr = dbch->top, *odb_tr; 2499 struct firewire_comm *fc = (struct firewire_comm *)sc; 2500 int z = 1; 2501 struct fw_pkt *fp; 2502 u_int8_t *ld; 2503 u_int32_t off = NULL; 2504 u_int32_t stat; 2505 u_int32_t *qld; 2506 u_int32_t reg; 2507 u_int spd; 2508 u_int dmach; 2509 int len, i, plen; 2510 caddr_t buf; 2511 2512 for(dmach = 0 ; dmach < sc->fc.nisodma ; dmach++){ 2513 if( &sc->ir[dmach] == dbch){ 2514 off = OHCI_IROFF(dmach); 2515 break; 2516 } 2517 } 2518 if(off == NULL){ 2519 return; 2520 } 2521 if(!(dbch->xferq.flag & FWXFERQ_RUNNING)){ 2522 fwohci_irx_disable(&sc->fc, dmach); 2523 return; 2524 } 2525 2526 odb_tr = NULL; 2527 db_tr = dbch->top; 2528 i = 0; 2529 while ((reg = db_tr->db[0].db.desc.status) & 0x1f) { 2530 if (count >= 0 && count-- == 0) 2531 break; 2532 ld = (u_int8_t *)db_tr->buf; 2533 if (dbch->xferq.flag & FWXFERQ_PACKET) { 2534 /* skip timeStamp */ 2535 ld += sizeof(struct fwohci_trailer); 2536 } 2537 qld = (u_int32_t *)ld; 2538 len = dbch->xferq.psize - (db_tr->db[0].db.desc.count); 2539 /* 2540 { 2541 device_printf(sc->fc.dev, "%04x %2x 0x%08x 0x%08x 0x%08x 0x%08x\n", len, 2542 db_tr->db[0].db.desc.status & 0x1f, qld[0],qld[1],qld[2],qld[3]); 2543 } 2544 */ 2545 fp=(struct fw_pkt *)ld; 2546 qld[0] = htonl(qld[0]); 2547 plen = sizeof(struct fw_isohdr) 2548 + ntohs(fp->mode.stream.len) + sizeof(u_int32_t); 2549 ld += plen; 2550 len -= plen; 2551 buf = db_tr->buf; 2552 db_tr->buf = NULL; 2553 stat = reg & 0x1f; 2554 spd = reg & 0x3; 2555 switch(stat){ 2556 case FWOHCIEV_ACKCOMPL: 2557 case FWOHCIEV_ACKPEND: 2558 fw_rcv(&sc->fc, buf, plen - sizeof(u_int32_t), dmach, sizeof(u_int32_t), spd); 2559 break; 2560 default: 2561 free(buf, M_FW); 2562 device_printf(sc->fc.dev, "Isochronous receive err %02x\n", stat); 2563 break; 2564 } 2565 i++; 2566 fwohci_add_rx_buf(db_tr, dbch->xferq.psize, 2567 dbch->xferq.flag, 0, NULL); 2568 db_tr->db[0].db.desc.depend &= ~0xf; 2569 if(dbch->pdb_tr != NULL){ 2570 dbch->pdb_tr->db[0].db.desc.depend |= z; 2571 } else { 2572 /* XXX should be rewritten in better way */ 2573 dbch->bottom->db[0].db.desc.depend |= z; 2574 } 2575 dbch->pdb_tr = db_tr; 2576 db_tr = STAILQ_NEXT(db_tr, link); 2577 } 2578 dbch->top = db_tr; 2579 reg = OREAD(sc, OHCI_DMACTL(off)); 2580 if (reg & OHCI_CNTL_DMA_ACTIVE) 2581 return; 2582 device_printf(sc->fc.dev, "IR DMA %d stopped at %x status=%x (%d)\n", 2583 dmach, OREAD(sc, OHCI_DMACMD(off)), reg, i); 2584 dbch->top = db_tr; 2585 fwohci_irx_enable(fc, dmach); 2586 } 2587 2588 #define PLEN(x) roundup2(ntohs(x), sizeof(u_int32_t)) 2589 static int 2590 fwohci_get_plen(struct fwohci_softc *sc, struct fwohci_dbch *dbch, struct fw_pkt *fp, int hlen) 2591 { 2592 int i, r; 2593 2594 for( i = 4; i < hlen ; i+=4){ 2595 fp->mode.ld[i/4] = htonl(fp->mode.ld[i/4]); 2596 } 2597 2598 switch(fp->mode.common.tcode){ 2599 case FWTCODE_RREQQ: 2600 r = sizeof(fp->mode.rreqq) + sizeof(u_int32_t); 2601 break; 2602 case FWTCODE_WRES: 2603 r = sizeof(fp->mode.wres) + sizeof(u_int32_t); 2604 break; 2605 case FWTCODE_WREQQ: 2606 r = sizeof(fp->mode.wreqq) + sizeof(u_int32_t); 2607 break; 2608 case FWTCODE_RREQB: 2609 r = sizeof(fp->mode.rreqb) + sizeof(u_int32_t); 2610 break; 2611 case FWTCODE_RRESQ: 2612 r = sizeof(fp->mode.rresq) + sizeof(u_int32_t); 2613 break; 2614 case FWTCODE_WREQB: 2615 r = sizeof(struct fw_asyhdr) + PLEN(fp->mode.wreqb.len) 2616 + sizeof(u_int32_t); 2617 break; 2618 case FWTCODE_LREQ: 2619 r = sizeof(struct fw_asyhdr) + PLEN(fp->mode.lreq.len) 2620 + sizeof(u_int32_t); 2621 break; 2622 case FWTCODE_RRESB: 2623 r = sizeof(struct fw_asyhdr) + PLEN(fp->mode.rresb.len) 2624 + sizeof(u_int32_t); 2625 break; 2626 case FWTCODE_LRES: 2627 r = sizeof(struct fw_asyhdr) + PLEN(fp->mode.lres.len) 2628 + sizeof(u_int32_t); 2629 break; 2630 case FWOHCITCODE_PHY: 2631 r = 16; 2632 break; 2633 default: 2634 device_printf(sc->fc.dev, "Unknown tcode %d\n", 2635 fp->mode.common.tcode); 2636 r = 0; 2637 } 2638 if (r > dbch->xferq.psize) { 2639 device_printf(sc->fc.dev, "Invalid packet length %d\n", r); 2640 /* panic ? */ 2641 } 2642 return r; 2643 } 2644 2645 static void 2646 fwohci_arcv(struct fwohci_softc *sc, struct fwohci_dbch *dbch, int count) 2647 { 2648 struct fwohcidb_tr *db_tr; 2649 int z = 1; 2650 struct fw_pkt *fp; 2651 u_int8_t *ld; 2652 u_int32_t stat, off; 2653 u_int spd; 2654 int len, plen, hlen, pcnt, poff = 0, rlen; 2655 int s; 2656 caddr_t buf; 2657 int resCount; 2658 2659 if(&sc->arrq == dbch){ 2660 off = OHCI_ARQOFF; 2661 }else if(&sc->arrs == dbch){ 2662 off = OHCI_ARSOFF; 2663 }else{ 2664 return; 2665 } 2666 2667 s = splfw(); 2668 db_tr = dbch->top; 2669 pcnt = 0; 2670 /* XXX we cannot handle a packet which lies in more than two buf */ 2671 while (db_tr->db[0].db.desc.status & OHCI_CNTL_DMA_ACTIVE) { 2672 ld = (u_int8_t *)db_tr->buf + dbch->buf_offset; 2673 resCount = db_tr->db[0].db.desc.count; 2674 len = dbch->xferq.psize - resCount 2675 - dbch->buf_offset; 2676 while (len > 0 ) { 2677 if (count >= 0 && count-- == 0) 2678 goto out; 2679 if(dbch->frag.buf != NULL){ 2680 buf = dbch->frag.buf; 2681 if (dbch->frag.plen < 0) { 2682 /* incomplete header */ 2683 int hlen; 2684 2685 hlen = - dbch->frag.plen; 2686 rlen = hlen - dbch->frag.len; 2687 bcopy(ld, dbch->frag.buf + dbch->frag.len, rlen); 2688 ld += rlen; 2689 len -= rlen; 2690 dbch->frag.len += rlen; 2691 #if 0 2692 printf("(1)frag.plen=%d frag.len=%d rlen=%d len=%d\n", dbch->frag.plen, dbch->frag.len, rlen, len); 2693 #endif 2694 fp=(struct fw_pkt *)dbch->frag.buf; 2695 dbch->frag.plen 2696 = fwohci_get_plen(sc, 2697 dbch, fp, hlen); 2698 if (dbch->frag.plen == 0) 2699 goto out; 2700 } 2701 rlen = dbch->frag.plen - dbch->frag.len; 2702 #if 0 2703 printf("(2)frag.plen=%d frag.len=%d rlen=%d len=%d\n", dbch->frag.plen, dbch->frag.len, rlen, len); 2704 #endif 2705 bcopy(ld, dbch->frag.buf + dbch->frag.len, 2706 rlen); 2707 ld += rlen; 2708 len -= rlen; 2709 plen = dbch->frag.plen; 2710 dbch->frag.buf = NULL; 2711 dbch->frag.plen = 0; 2712 dbch->frag.len = 0; 2713 poff = 0; 2714 }else{ 2715 fp=(struct fw_pkt *)ld; 2716 fp->mode.ld[0] = htonl(fp->mode.ld[0]); 2717 switch(fp->mode.common.tcode){ 2718 case FWTCODE_RREQQ: 2719 case FWTCODE_WRES: 2720 case FWTCODE_WREQQ: 2721 case FWTCODE_RRESQ: 2722 case FWOHCITCODE_PHY: 2723 hlen = 12; 2724 break; 2725 case FWTCODE_RREQB: 2726 case FWTCODE_WREQB: 2727 case FWTCODE_LREQ: 2728 case FWTCODE_RRESB: 2729 case FWTCODE_LRES: 2730 hlen = 16; 2731 break; 2732 default: 2733 device_printf(sc->fc.dev, "Unknown tcode %d\n", fp->mode.common.tcode); 2734 goto out; 2735 } 2736 if (len >= hlen) { 2737 plen = fwohci_get_plen(sc, 2738 dbch, fp, hlen); 2739 if (plen == 0) 2740 goto out; 2741 plen = (plen + 3) & ~3; 2742 len -= plen; 2743 } else { 2744 plen = -hlen; 2745 len -= hlen; 2746 } 2747 if(resCount > 0 || len > 0){ 2748 buf = malloc(plen, M_FW, M_NOWAIT); 2749 if(buf == NULL){ 2750 printf("cannot malloc!\n"); 2751 free(db_tr->buf, M_FW); 2752 goto out; 2753 } 2754 bcopy(ld, buf, plen); 2755 poff = 0; 2756 dbch->frag.buf = NULL; 2757 dbch->frag.plen = 0; 2758 dbch->frag.len = 0; 2759 }else if(len < 0){ 2760 dbch->frag.buf = db_tr->buf; 2761 if (plen < 0) { 2762 #if 0 2763 printf("plen < 0:" 2764 "hlen: %d len: %d\n", 2765 hlen, len); 2766 #endif 2767 dbch->frag.len = hlen + len; 2768 dbch->frag.plen = -hlen; 2769 } else { 2770 dbch->frag.len = plen + len; 2771 dbch->frag.plen = plen; 2772 } 2773 bcopy(ld, db_tr->buf, dbch->frag.len); 2774 buf = NULL; 2775 }else{ 2776 buf = db_tr->buf; 2777 poff = ld - (u_int8_t *)buf; 2778 dbch->frag.buf = NULL; 2779 dbch->frag.plen = 0; 2780 dbch->frag.len = 0; 2781 } 2782 ld += plen; 2783 } 2784 if( buf != NULL){ 2785 /* DMA result-code will be written at the tail of packet */ 2786 stat = ((struct fwohci_trailer *)(ld - sizeof(struct fwohci_trailer)))->stat; 2787 spd = (stat >> 5) & 0x3; 2788 stat &= 0x1f; 2789 switch(stat){ 2790 case FWOHCIEV_ACKPEND: 2791 #if 0 2792 printf("fwohci_arcv: ack pending..\n"); 2793 #endif 2794 /* fall through */ 2795 case FWOHCIEV_ACKCOMPL: 2796 if( poff != 0 ) 2797 bcopy(buf+poff, buf, plen - 4); 2798 fw_rcv(&sc->fc, buf, plen - sizeof(struct fwohci_trailer), 0, 0, spd); 2799 break; 2800 case FWOHCIEV_BUSRST: 2801 free(buf, M_FW); 2802 if (sc->fc.status != FWBUSRESET) 2803 printf("got BUSRST packet!?\n"); 2804 break; 2805 default: 2806 device_printf(sc->fc.dev, "Async DMA Receive error err = %02x %s\n", stat, fwohcicode[stat]); 2807 #if 0 /* XXX */ 2808 goto out; 2809 #endif 2810 break; 2811 } 2812 } 2813 pcnt ++; 2814 }; 2815 out: 2816 if (resCount == 0) { 2817 /* done on this buffer */ 2818 fwohci_add_rx_buf(db_tr, dbch->xferq.psize, 2819 dbch->xferq.flag, 0, NULL); 2820 dbch->bottom->db[0].db.desc.depend |= z; 2821 dbch->bottom = db_tr; 2822 db_tr = STAILQ_NEXT(db_tr, link); 2823 dbch->top = db_tr; 2824 dbch->buf_offset = 0; 2825 } else { 2826 dbch->buf_offset = dbch->xferq.psize - resCount; 2827 break; 2828 } 2829 /* XXX make sure DMA is not dead */ 2830 } 2831 #if 0 2832 if (pcnt < 1) 2833 printf("fwohci_arcv: no packets\n"); 2834 #endif 2835 splx(s); 2836 } 2837