1 /* 2 * Copyright (c) 2003 Hidetoshi Shimokawa 3 * Copyright (c) 1998-2002 Katsushi Kobayashi and Hidetoshi Shimokawa 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the acknowledgement as bellow: 16 * 17 * This product includes software developed by K. Kobayashi and H. Shimokawa 18 * 19 * 4. The name of the author may not be used to endorse or promote products 20 * derived from this software without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 24 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 25 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 26 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 27 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 28 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 29 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 30 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 31 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 32 * POSSIBILITY OF SUCH DAMAGE. 33 * 34 * $FreeBSD$ 35 * 36 */ 37 38 #define ATRQ_CH 0 39 #define ATRS_CH 1 40 #define ARRQ_CH 2 41 #define ARRS_CH 3 42 #define ITX_CH 4 43 #define IRX_CH 0x24 44 45 #include <sys/param.h> 46 #include <sys/proc.h> 47 #include <sys/systm.h> 48 #include <sys/types.h> 49 #include <sys/mbuf.h> 50 #include <sys/mman.h> 51 #include <sys/socket.h> 52 #include <sys/socketvar.h> 53 #include <sys/signalvar.h> 54 #include <sys/malloc.h> 55 #include <sys/sockio.h> 56 #include <sys/bus.h> 57 #include <sys/kernel.h> 58 #include <sys/conf.h> 59 #include <sys/endian.h> 60 61 #include <machine/bus.h> 62 #include <machine/resource.h> 63 #include <sys/rman.h> 64 65 #include <machine/cpufunc.h> /* for rdtsc proto for clock.h below */ 66 #include <machine/clock.h> 67 #include <pci/pcivar.h> 68 #include <pci/pcireg.h> 69 70 #include <dev/firewire/firewire.h> 71 #include <dev/firewire/firewirereg.h> 72 #include <dev/firewire/fwdma.h> 73 #include <dev/firewire/fwohcireg.h> 74 #include <dev/firewire/fwohcivar.h> 75 #include <dev/firewire/firewire_phy.h> 76 77 #include <dev/firewire/iec68113.h> 78 79 #undef OHCI_DEBUG 80 81 static char dbcode[16][0x10]={"OUTM", "OUTL","INPM","INPL", 82 "STOR","LOAD","NOP ","STOP",}; 83 84 static char dbkey[8][0x10]={"ST0", "ST1","ST2","ST3", 85 "UNDEF","REG","SYS","DEV"}; 86 static char dbcond[4][0x10]={"NEV","C=1", "C=0", "ALL"}; 87 char fwohcicode[32][0x20]={ 88 "No stat","Undef","long","miss Ack err", 89 "underrun","overrun","desc err", "data read err", 90 "data write err","bus reset","timeout","tcode err", 91 "Undef","Undef","unknown event","flushed", 92 "Undef","ack complete","ack pend","Undef", 93 "ack busy_X","ack busy_A","ack busy_B","Undef", 94 "Undef","Undef","Undef","ack tardy", 95 "Undef","ack data_err","ack type_err",""}; 96 97 #define MAX_SPEED 2 98 extern char linkspeed[MAX_SPEED+1][0x10]; 99 u_int32_t tagbit[4] = { 1 << 28, 1 << 29, 1 << 30, 1 << 31}; 100 101 static struct tcode_info tinfo[] = { 102 /* hdr_len block flag*/ 103 /* 0 WREQQ */ {16, FWTI_REQ | FWTI_TLABEL}, 104 /* 1 WREQB */ {16, FWTI_REQ | FWTI_TLABEL | FWTI_BLOCK_ASY}, 105 /* 2 WRES */ {12, FWTI_RES}, 106 /* 3 XXX */ { 0, 0}, 107 /* 4 RREQQ */ {12, FWTI_REQ | FWTI_TLABEL}, 108 /* 5 RREQB */ {16, FWTI_REQ | FWTI_TLABEL}, 109 /* 6 RRESQ */ {16, FWTI_RES}, 110 /* 7 RRESB */ {16, FWTI_RES | FWTI_BLOCK_ASY}, 111 /* 8 CYCS */ { 0, 0}, 112 /* 9 LREQ */ {16, FWTI_REQ | FWTI_TLABEL | FWTI_BLOCK_ASY}, 113 /* a STREAM */ { 4, FWTI_REQ | FWTI_BLOCK_STR}, 114 /* b LRES */ {16, FWTI_RES | FWTI_BLOCK_ASY}, 115 /* c XXX */ { 0, 0}, 116 /* d XXX */ { 0, 0}, 117 /* e PHY */ {12, FWTI_REQ}, 118 /* f XXX */ { 0, 0} 119 }; 120 121 #define OHCI_WRITE_SIGMASK 0xffff0000 122 #define OHCI_READ_SIGMASK 0xffff0000 123 124 #define OWRITE(sc, r, x) bus_space_write_4((sc)->bst, (sc)->bsh, (r), (x)) 125 #define OREAD(sc, r) bus_space_read_4((sc)->bst, (sc)->bsh, (r)) 126 127 static void fwohci_ibr __P((struct firewire_comm *)); 128 static void fwohci_db_init __P((struct fwohci_softc *, struct fwohci_dbch *)); 129 static void fwohci_db_free __P((struct fwohci_dbch *)); 130 static void fwohci_arcv __P((struct fwohci_softc *, struct fwohci_dbch *, int)); 131 static void fwohci_txd __P((struct fwohci_softc *, struct fwohci_dbch *)); 132 static void fwohci_start_atq __P((struct firewire_comm *)); 133 static void fwohci_start_ats __P((struct firewire_comm *)); 134 static void fwohci_start __P((struct fwohci_softc *, struct fwohci_dbch *)); 135 static u_int32_t fwphy_wrdata __P(( struct fwohci_softc *, u_int32_t, u_int32_t)); 136 static u_int32_t fwphy_rddata __P(( struct fwohci_softc *, u_int32_t)); 137 static int fwohci_rx_enable __P((struct fwohci_softc *, struct fwohci_dbch *)); 138 static int fwohci_tx_enable __P((struct fwohci_softc *, struct fwohci_dbch *)); 139 static int fwohci_irx_enable __P((struct firewire_comm *, int)); 140 static int fwohci_irx_disable __P((struct firewire_comm *, int)); 141 #if BYTE_ORDER == BIG_ENDIAN 142 static void fwohci_irx_post __P((struct firewire_comm *, u_int32_t *)); 143 #endif 144 static int fwohci_itxbuf_enable __P((struct firewire_comm *, int)); 145 static int fwohci_itx_disable __P((struct firewire_comm *, int)); 146 static void fwohci_timeout __P((void *)); 147 static void fwohci_poll __P((struct firewire_comm *, int, int)); 148 static void fwohci_set_intr __P((struct firewire_comm *, int)); 149 150 static int fwohci_add_rx_buf __P((struct fwohci_dbch *, struct fwohcidb_tr *, int, struct fwdma_alloc *)); 151 static int fwohci_add_tx_buf __P((struct fwohci_dbch *, struct fwohcidb_tr *, int)); 152 static void dump_db __P((struct fwohci_softc *, u_int32_t)); 153 static void print_db __P((struct fwohcidb_tr *, volatile struct fwohcidb *, u_int32_t , u_int32_t)); 154 static void dump_dma __P((struct fwohci_softc *, u_int32_t)); 155 static u_int32_t fwohci_cyctimer __P((struct firewire_comm *)); 156 static void fwohci_rbuf_update __P((struct fwohci_softc *, int)); 157 static void fwohci_tbuf_update __P((struct fwohci_softc *, int)); 158 void fwohci_txbufdb __P((struct fwohci_softc *, int , struct fw_bulkxfer *)); 159 #if FWOHCI_TASKQUEUE 160 static void fwohci_complete(void *, int); 161 #endif 162 163 /* 164 * memory allocated for DMA programs 165 */ 166 #define DMA_PROG_ALLOC (8 * PAGE_SIZE) 167 168 /* #define NDB 1024 */ 169 #define NDB FWMAXQUEUE 170 #define NDVDB (DVBUF * NDB) 171 172 #define OHCI_VERSION 0x00 173 #define OHCI_ATRETRY 0x08 174 #define OHCI_CROMHDR 0x18 175 #define OHCI_BUS_OPT 0x20 176 #define OHCI_BUSIRMC (1 << 31) 177 #define OHCI_BUSCMC (1 << 30) 178 #define OHCI_BUSISC (1 << 29) 179 #define OHCI_BUSBMC (1 << 28) 180 #define OHCI_BUSPMC (1 << 27) 181 #define OHCI_BUSFNC OHCI_BUSIRMC | OHCI_BUSCMC | OHCI_BUSISC |\ 182 OHCI_BUSBMC | OHCI_BUSPMC 183 184 #define OHCI_EUID_HI 0x24 185 #define OHCI_EUID_LO 0x28 186 187 #define OHCI_CROMPTR 0x34 188 #define OHCI_HCCCTL 0x50 189 #define OHCI_HCCCTLCLR 0x54 190 #define OHCI_AREQHI 0x100 191 #define OHCI_AREQHICLR 0x104 192 #define OHCI_AREQLO 0x108 193 #define OHCI_AREQLOCLR 0x10c 194 #define OHCI_PREQHI 0x110 195 #define OHCI_PREQHICLR 0x114 196 #define OHCI_PREQLO 0x118 197 #define OHCI_PREQLOCLR 0x11c 198 #define OHCI_PREQUPPER 0x120 199 200 #define OHCI_SID_BUF 0x64 201 #define OHCI_SID_CNT 0x68 202 #define OHCI_SID_ERR (1 << 31) 203 #define OHCI_SID_CNT_MASK 0xffc 204 205 #define OHCI_IT_STAT 0x90 206 #define OHCI_IT_STATCLR 0x94 207 #define OHCI_IT_MASK 0x98 208 #define OHCI_IT_MASKCLR 0x9c 209 210 #define OHCI_IR_STAT 0xa0 211 #define OHCI_IR_STATCLR 0xa4 212 #define OHCI_IR_MASK 0xa8 213 #define OHCI_IR_MASKCLR 0xac 214 215 #define OHCI_LNKCTL 0xe0 216 #define OHCI_LNKCTLCLR 0xe4 217 218 #define OHCI_PHYACCESS 0xec 219 #define OHCI_CYCLETIMER 0xf0 220 221 #define OHCI_DMACTL(off) (off) 222 #define OHCI_DMACTLCLR(off) (off + 4) 223 #define OHCI_DMACMD(off) (off + 0xc) 224 #define OHCI_DMAMATCH(off) (off + 0x10) 225 226 #define OHCI_ATQOFF 0x180 227 #define OHCI_ATQCTL OHCI_ATQOFF 228 #define OHCI_ATQCTLCLR (OHCI_ATQOFF + 4) 229 #define OHCI_ATQCMD (OHCI_ATQOFF + 0xc) 230 #define OHCI_ATQMATCH (OHCI_ATQOFF + 0x10) 231 232 #define OHCI_ATSOFF 0x1a0 233 #define OHCI_ATSCTL OHCI_ATSOFF 234 #define OHCI_ATSCTLCLR (OHCI_ATSOFF + 4) 235 #define OHCI_ATSCMD (OHCI_ATSOFF + 0xc) 236 #define OHCI_ATSMATCH (OHCI_ATSOFF + 0x10) 237 238 #define OHCI_ARQOFF 0x1c0 239 #define OHCI_ARQCTL OHCI_ARQOFF 240 #define OHCI_ARQCTLCLR (OHCI_ARQOFF + 4) 241 #define OHCI_ARQCMD (OHCI_ARQOFF + 0xc) 242 #define OHCI_ARQMATCH (OHCI_ARQOFF + 0x10) 243 244 #define OHCI_ARSOFF 0x1e0 245 #define OHCI_ARSCTL OHCI_ARSOFF 246 #define OHCI_ARSCTLCLR (OHCI_ARSOFF + 4) 247 #define OHCI_ARSCMD (OHCI_ARSOFF + 0xc) 248 #define OHCI_ARSMATCH (OHCI_ARSOFF + 0x10) 249 250 #define OHCI_ITOFF(CH) (0x200 + 0x10 * (CH)) 251 #define OHCI_ITCTL(CH) (OHCI_ITOFF(CH)) 252 #define OHCI_ITCTLCLR(CH) (OHCI_ITOFF(CH) + 4) 253 #define OHCI_ITCMD(CH) (OHCI_ITOFF(CH) + 0xc) 254 255 #define OHCI_IROFF(CH) (0x400 + 0x20 * (CH)) 256 #define OHCI_IRCTL(CH) (OHCI_IROFF(CH)) 257 #define OHCI_IRCTLCLR(CH) (OHCI_IROFF(CH) + 4) 258 #define OHCI_IRCMD(CH) (OHCI_IROFF(CH) + 0xc) 259 #define OHCI_IRMATCH(CH) (OHCI_IROFF(CH) + 0x10) 260 261 d_ioctl_t fwohci_ioctl; 262 263 /* 264 * Communication with PHY device 265 */ 266 static u_int32_t 267 fwphy_wrdata( struct fwohci_softc *sc, u_int32_t addr, u_int32_t data) 268 { 269 u_int32_t fun; 270 271 addr &= 0xf; 272 data &= 0xff; 273 274 fun = (PHYDEV_WRCMD | (addr << PHYDEV_REGADDR) | (data << PHYDEV_WRDATA)); 275 OWRITE(sc, OHCI_PHYACCESS, fun); 276 DELAY(100); 277 278 return(fwphy_rddata( sc, addr)); 279 } 280 281 static u_int32_t 282 fwohci_set_bus_manager(struct firewire_comm *fc, u_int node) 283 { 284 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 285 int i; 286 u_int32_t bm; 287 288 #define OHCI_CSR_DATA 0x0c 289 #define OHCI_CSR_COMP 0x10 290 #define OHCI_CSR_CONT 0x14 291 #define OHCI_BUS_MANAGER_ID 0 292 293 OWRITE(sc, OHCI_CSR_DATA, node); 294 OWRITE(sc, OHCI_CSR_COMP, 0x3f); 295 OWRITE(sc, OHCI_CSR_CONT, OHCI_BUS_MANAGER_ID); 296 for (i = 0; !(OREAD(sc, OHCI_CSR_CONT) & (1<<31)) && (i < 1000); i++) 297 DELAY(10); 298 bm = OREAD(sc, OHCI_CSR_DATA); 299 if((bm & 0x3f) == 0x3f) 300 bm = node; 301 if (bootverbose) 302 device_printf(sc->fc.dev, 303 "fw_set_bus_manager: %d->%d (loop=%d)\n", bm, node, i); 304 305 return(bm); 306 } 307 308 static u_int32_t 309 fwphy_rddata(struct fwohci_softc *sc, u_int addr) 310 { 311 u_int32_t fun, stat; 312 u_int i, retry = 0; 313 314 addr &= 0xf; 315 #define MAX_RETRY 100 316 again: 317 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_REG_FAIL); 318 fun = PHYDEV_RDCMD | (addr << PHYDEV_REGADDR); 319 OWRITE(sc, OHCI_PHYACCESS, fun); 320 for ( i = 0 ; i < MAX_RETRY ; i ++ ){ 321 fun = OREAD(sc, OHCI_PHYACCESS); 322 if ((fun & PHYDEV_RDCMD) == 0 && (fun & PHYDEV_RDDONE) != 0) 323 break; 324 DELAY(100); 325 } 326 if(i >= MAX_RETRY) { 327 if (bootverbose) 328 device_printf(sc->fc.dev, "phy read failed(1).\n"); 329 if (++retry < MAX_RETRY) { 330 DELAY(100); 331 goto again; 332 } 333 } 334 /* Make sure that SCLK is started */ 335 stat = OREAD(sc, FWOHCI_INTSTAT); 336 if ((stat & OHCI_INT_REG_FAIL) != 0 || 337 ((fun >> PHYDEV_REGADDR) & 0xf) != addr) { 338 if (bootverbose) 339 device_printf(sc->fc.dev, "phy read failed(2).\n"); 340 if (++retry < MAX_RETRY) { 341 DELAY(100); 342 goto again; 343 } 344 } 345 if (bootverbose || retry >= MAX_RETRY) 346 device_printf(sc->fc.dev, 347 "fwphy_rddata: loop=%d, retry=%d\n", i, retry); 348 #undef MAX_RETRY 349 return((fun >> PHYDEV_RDDATA )& 0xff); 350 } 351 /* Device specific ioctl. */ 352 int 353 fwohci_ioctl (dev_t dev, u_long cmd, caddr_t data, int flag, fw_proc *td) 354 { 355 struct firewire_softc *sc; 356 struct fwohci_softc *fc; 357 int unit = DEV2UNIT(dev); 358 int err = 0; 359 struct fw_reg_req_t *reg = (struct fw_reg_req_t *) data; 360 u_int32_t *dmach = (u_int32_t *) data; 361 362 sc = devclass_get_softc(firewire_devclass, unit); 363 if(sc == NULL){ 364 return(EINVAL); 365 } 366 fc = (struct fwohci_softc *)sc->fc; 367 368 if (!data) 369 return(EINVAL); 370 371 switch (cmd) { 372 case FWOHCI_WRREG: 373 #define OHCI_MAX_REG 0x800 374 if(reg->addr <= OHCI_MAX_REG){ 375 OWRITE(fc, reg->addr, reg->data); 376 reg->data = OREAD(fc, reg->addr); 377 }else{ 378 err = EINVAL; 379 } 380 break; 381 case FWOHCI_RDREG: 382 if(reg->addr <= OHCI_MAX_REG){ 383 reg->data = OREAD(fc, reg->addr); 384 }else{ 385 err = EINVAL; 386 } 387 break; 388 /* Read DMA descriptors for debug */ 389 case DUMPDMA: 390 if(*dmach <= OHCI_MAX_DMA_CH ){ 391 dump_dma(fc, *dmach); 392 dump_db(fc, *dmach); 393 }else{ 394 err = EINVAL; 395 } 396 break; 397 default: 398 break; 399 } 400 return err; 401 } 402 403 static int 404 fwohci_probe_phy(struct fwohci_softc *sc, device_t dev) 405 { 406 u_int32_t reg, reg2; 407 int e1394a = 1; 408 /* 409 * probe PHY parameters 410 * 0. to prove PHY version, whether compliance of 1394a. 411 * 1. to probe maximum speed supported by the PHY and 412 * number of port supported by core-logic. 413 * It is not actually available port on your PC . 414 */ 415 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_LPS); 416 reg = fwphy_rddata(sc, FW_PHY_SPD_REG); 417 418 if((reg >> 5) != 7 ){ 419 sc->fc.mode &= ~FWPHYASYST; 420 sc->fc.nport = reg & FW_PHY_NP; 421 sc->fc.speed = reg & FW_PHY_SPD >> 6; 422 if (sc->fc.speed > MAX_SPEED) { 423 device_printf(dev, "invalid speed %d (fixed to %d).\n", 424 sc->fc.speed, MAX_SPEED); 425 sc->fc.speed = MAX_SPEED; 426 } 427 device_printf(dev, 428 "Phy 1394 only %s, %d ports.\n", 429 linkspeed[sc->fc.speed], sc->fc.nport); 430 }else{ 431 reg2 = fwphy_rddata(sc, FW_PHY_ESPD_REG); 432 sc->fc.mode |= FWPHYASYST; 433 sc->fc.nport = reg & FW_PHY_NP; 434 sc->fc.speed = (reg2 & FW_PHY_ESPD) >> 5; 435 if (sc->fc.speed > MAX_SPEED) { 436 device_printf(dev, "invalid speed %d (fixed to %d).\n", 437 sc->fc.speed, MAX_SPEED); 438 sc->fc.speed = MAX_SPEED; 439 } 440 device_printf(dev, 441 "Phy 1394a available %s, %d ports.\n", 442 linkspeed[sc->fc.speed], sc->fc.nport); 443 444 /* check programPhyEnable */ 445 reg2 = fwphy_rddata(sc, 5); 446 #if 0 447 if (e1394a && (OREAD(sc, OHCI_HCCCTL) & OHCI_HCC_PRPHY)) { 448 #else /* XXX force to enable 1394a */ 449 if (e1394a) { 450 #endif 451 if (bootverbose) 452 device_printf(dev, 453 "Enable 1394a Enhancements\n"); 454 /* enable EAA EMC */ 455 reg2 |= 0x03; 456 /* set aPhyEnhanceEnable */ 457 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_PHYEN); 458 OWRITE(sc, OHCI_HCCCTLCLR, OHCI_HCC_PRPHY); 459 } else { 460 /* for safe */ 461 reg2 &= ~0x83; 462 } 463 reg2 = fwphy_wrdata(sc, 5, reg2); 464 } 465 466 reg = fwphy_rddata(sc, FW_PHY_SPD_REG); 467 if((reg >> 5) == 7 ){ 468 reg = fwphy_rddata(sc, 4); 469 reg |= 1 << 6; 470 fwphy_wrdata(sc, 4, reg); 471 reg = fwphy_rddata(sc, 4); 472 } 473 return 0; 474 } 475 476 477 void 478 fwohci_reset(struct fwohci_softc *sc, device_t dev) 479 { 480 int i, max_rec, speed; 481 u_int32_t reg, reg2; 482 struct fwohcidb_tr *db_tr; 483 484 /* Disable interrupt */ 485 OWRITE(sc, FWOHCI_INTMASKCLR, ~0); 486 487 /* Now stopping all DMA channel */ 488 OWRITE(sc, OHCI_ARQCTLCLR, OHCI_CNTL_DMA_RUN); 489 OWRITE(sc, OHCI_ARSCTLCLR, OHCI_CNTL_DMA_RUN); 490 OWRITE(sc, OHCI_ATQCTLCLR, OHCI_CNTL_DMA_RUN); 491 OWRITE(sc, OHCI_ATSCTLCLR, OHCI_CNTL_DMA_RUN); 492 493 OWRITE(sc, OHCI_IR_MASKCLR, ~0); 494 for( i = 0 ; i < sc->fc.nisodma ; i ++ ){ 495 OWRITE(sc, OHCI_IRCTLCLR(i), OHCI_CNTL_DMA_RUN); 496 OWRITE(sc, OHCI_ITCTLCLR(i), OHCI_CNTL_DMA_RUN); 497 } 498 499 /* FLUSH FIFO and reset Transmitter/Reciever */ 500 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_RESET); 501 if (bootverbose) 502 device_printf(dev, "resetting OHCI..."); 503 i = 0; 504 while(OREAD(sc, OHCI_HCCCTL) & OHCI_HCC_RESET) { 505 if (i++ > 100) break; 506 DELAY(1000); 507 } 508 if (bootverbose) 509 printf("done (loop=%d)\n", i); 510 511 /* Probe phy */ 512 fwohci_probe_phy(sc, dev); 513 514 /* Probe link */ 515 reg = OREAD(sc, OHCI_BUS_OPT); 516 reg2 = reg | OHCI_BUSFNC; 517 max_rec = (reg & 0x0000f000) >> 12; 518 speed = (reg & 0x00000007); 519 device_printf(dev, "Link %s, max_rec %d bytes.\n", 520 linkspeed[speed], MAXREC(max_rec)); 521 /* XXX fix max_rec */ 522 sc->fc.maxrec = sc->fc.speed + 8; 523 if (max_rec != sc->fc.maxrec) { 524 reg2 = (reg2 & 0xffff0fff) | (sc->fc.maxrec << 12); 525 device_printf(dev, "max_rec %d -> %d\n", 526 MAXREC(max_rec), MAXREC(sc->fc.maxrec)); 527 } 528 if (bootverbose) 529 device_printf(dev, "BUS_OPT 0x%x -> 0x%x\n", reg, reg2); 530 OWRITE(sc, OHCI_BUS_OPT, reg2); 531 532 /* Initialize registers */ 533 OWRITE(sc, OHCI_CROMHDR, sc->fc.config_rom[0]); 534 OWRITE(sc, OHCI_CROMPTR, sc->crom_dma.bus_addr); 535 OWRITE(sc, OHCI_HCCCTLCLR, OHCI_HCC_BIGEND); 536 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_POSTWR); 537 OWRITE(sc, OHCI_SID_BUF, sc->sid_dma.bus_addr); 538 OWRITE(sc, OHCI_LNKCTL, OHCI_CNTL_SID); 539 fw_busreset(&sc->fc); 540 541 /* Enable link */ 542 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_LINKEN); 543 544 /* Force to start async RX DMA */ 545 sc->arrq.xferq.flag &= ~FWXFERQ_RUNNING; 546 sc->arrs.xferq.flag &= ~FWXFERQ_RUNNING; 547 fwohci_rx_enable(sc, &sc->arrq); 548 fwohci_rx_enable(sc, &sc->arrs); 549 550 /* Initialize async TX */ 551 OWRITE(sc, OHCI_ATQCTLCLR, OHCI_CNTL_DMA_RUN | OHCI_CNTL_DMA_DEAD); 552 OWRITE(sc, OHCI_ATSCTLCLR, OHCI_CNTL_DMA_RUN | OHCI_CNTL_DMA_DEAD); 553 /* AT Retries */ 554 OWRITE(sc, FWOHCI_RETRY, 555 /* CycleLimit PhyRespRetries ATRespRetries ATReqRetries */ 556 (0xffff << 16 ) | (0x0f << 8) | (0x0f << 4) | 0x0f) ; 557 for( i = 0, db_tr = sc->atrq.top; i < sc->atrq.ndb ; 558 i ++, db_tr = STAILQ_NEXT(db_tr, link)){ 559 db_tr->xfer = NULL; 560 } 561 for( i = 0, db_tr = sc->atrs.top; i < sc->atrs.ndb ; 562 i ++, db_tr = STAILQ_NEXT(db_tr, link)){ 563 db_tr->xfer = NULL; 564 } 565 566 567 /* Enable interrupt */ 568 OWRITE(sc, FWOHCI_INTMASK, 569 OHCI_INT_ERR | OHCI_INT_PHY_SID 570 | OHCI_INT_DMA_ATRQ | OHCI_INT_DMA_ATRS 571 | OHCI_INT_DMA_PRRQ | OHCI_INT_DMA_PRRS 572 | OHCI_INT_PHY_BUS_R | OHCI_INT_PW_ERR); 573 fwohci_set_intr(&sc->fc, 1); 574 575 } 576 577 int 578 fwohci_init(struct fwohci_softc *sc, device_t dev) 579 { 580 int i; 581 u_int32_t reg; 582 u_int8_t ui[8]; 583 584 #if FWOHCI_TASKQUEUE 585 TASK_INIT(&sc->fwohci_task_complete, 0, fwohci_complete, sc); 586 #endif 587 588 reg = OREAD(sc, OHCI_VERSION); 589 device_printf(dev, "OHCI version %x.%x (ROM=%d)\n", 590 (reg>>16) & 0xff, reg & 0xff, (reg>>24) & 1); 591 592 /* Available Isochrounous DMA channel probe */ 593 OWRITE(sc, OHCI_IT_MASK, 0xffffffff); 594 OWRITE(sc, OHCI_IR_MASK, 0xffffffff); 595 reg = OREAD(sc, OHCI_IT_MASK) & OREAD(sc, OHCI_IR_MASK); 596 OWRITE(sc, OHCI_IT_MASKCLR, 0xffffffff); 597 OWRITE(sc, OHCI_IR_MASKCLR, 0xffffffff); 598 for (i = 0; i < 0x20; i++) 599 if ((reg & (1 << i)) == 0) 600 break; 601 sc->fc.nisodma = i; 602 device_printf(dev, "No. of Isochronous channel is %d.\n", i); 603 604 sc->fc.arq = &sc->arrq.xferq; 605 sc->fc.ars = &sc->arrs.xferq; 606 sc->fc.atq = &sc->atrq.xferq; 607 sc->fc.ats = &sc->atrs.xferq; 608 609 sc->arrq.xferq.psize = roundup2(FWPMAX_S400, PAGE_SIZE); 610 sc->arrs.xferq.psize = roundup2(FWPMAX_S400, PAGE_SIZE); 611 sc->atrq.xferq.psize = roundup2(FWPMAX_S400, PAGE_SIZE); 612 sc->atrs.xferq.psize = roundup2(FWPMAX_S400, PAGE_SIZE); 613 614 sc->arrq.xferq.start = NULL; 615 sc->arrs.xferq.start = NULL; 616 sc->atrq.xferq.start = fwohci_start_atq; 617 sc->atrs.xferq.start = fwohci_start_ats; 618 619 sc->arrq.xferq.buf = NULL; 620 sc->arrs.xferq.buf = NULL; 621 sc->atrq.xferq.buf = NULL; 622 sc->atrs.xferq.buf = NULL; 623 624 sc->arrq.ndesc = 1; 625 sc->arrs.ndesc = 1; 626 sc->atrq.ndesc = 8; /* equal to maximum of mbuf chains */ 627 sc->atrs.ndesc = 2; 628 629 sc->arrq.ndb = NDB; 630 sc->arrs.ndb = NDB / 2; 631 sc->atrq.ndb = NDB; 632 sc->atrs.ndb = NDB / 2; 633 634 for( i = 0 ; i < sc->fc.nisodma ; i ++ ){ 635 sc->fc.it[i] = &sc->it[i].xferq; 636 sc->fc.ir[i] = &sc->ir[i].xferq; 637 sc->it[i].ndb = 0; 638 sc->ir[i].ndb = 0; 639 } 640 641 sc->fc.tcode = tinfo; 642 sc->fc.dev = dev; 643 644 sc->fc.config_rom = fwdma_malloc(&sc->fc, CROMSIZE, CROMSIZE, 645 &sc->crom_dma, BUS_DMA_WAITOK); 646 if(sc->fc.config_rom == NULL){ 647 device_printf(dev, "config_rom alloc failed."); 648 return ENOMEM; 649 } 650 651 #if 1 652 sc->fc.config_rom[1] = 0x31333934; 653 sc->fc.config_rom[2] = 0xf000a002; 654 sc->fc.config_rom[3] = OREAD(sc, OHCI_EUID_HI); 655 sc->fc.config_rom[4] = OREAD(sc, OHCI_EUID_LO); 656 sc->fc.config_rom[5] = 0; 657 sc->fc.config_rom[0] = (4 << 24) | (5 << 16); 658 659 sc->fc.config_rom[0] |= fw_crc16(&sc->fc.config_rom[1], 5*4); 660 #endif 661 662 663 /* SID recieve buffer must allign 2^11 */ 664 #define OHCI_SIDSIZE (1 << 11) 665 sc->sid_buf = fwdma_malloc(&sc->fc, OHCI_SIDSIZE, OHCI_SIDSIZE, 666 &sc->sid_dma, BUS_DMA_WAITOK); 667 if (sc->sid_buf == NULL) { 668 device_printf(dev, "sid_buf alloc failed."); 669 return ENOMEM; 670 } 671 672 fwdma_malloc(&sc->fc, sizeof(u_int32_t), sizeof(u_int32_t), 673 &sc->dummy_dma, BUS_DMA_WAITOK); 674 675 if (sc->dummy_dma.v_addr == NULL) { 676 device_printf(dev, "dummy_dma alloc failed."); 677 return ENOMEM; 678 } 679 680 fwohci_db_init(sc, &sc->arrq); 681 if ((sc->arrq.flags & FWOHCI_DBCH_INIT) == 0) 682 return ENOMEM; 683 684 fwohci_db_init(sc, &sc->arrs); 685 if ((sc->arrs.flags & FWOHCI_DBCH_INIT) == 0) 686 return ENOMEM; 687 688 fwohci_db_init(sc, &sc->atrq); 689 if ((sc->atrq.flags & FWOHCI_DBCH_INIT) == 0) 690 return ENOMEM; 691 692 fwohci_db_init(sc, &sc->atrs); 693 if ((sc->atrs.flags & FWOHCI_DBCH_INIT) == 0) 694 return ENOMEM; 695 696 sc->fc.eui.hi = OREAD(sc, FWOHCIGUID_H); 697 sc->fc.eui.lo = OREAD(sc, FWOHCIGUID_L); 698 for( i = 0 ; i < 8 ; i ++) 699 ui[i] = FW_EUI64_BYTE(&sc->fc.eui,i); 700 device_printf(dev, "EUI64 %02x:%02x:%02x:%02x:%02x:%02x:%02x:%02x\n", 701 ui[0], ui[1], ui[2], ui[3], ui[4], ui[5], ui[6], ui[7]); 702 703 sc->fc.ioctl = fwohci_ioctl; 704 sc->fc.cyctimer = fwohci_cyctimer; 705 sc->fc.set_bmr = fwohci_set_bus_manager; 706 sc->fc.ibr = fwohci_ibr; 707 sc->fc.irx_enable = fwohci_irx_enable; 708 sc->fc.irx_disable = fwohci_irx_disable; 709 710 sc->fc.itx_enable = fwohci_itxbuf_enable; 711 sc->fc.itx_disable = fwohci_itx_disable; 712 #if BYTE_ORDER == BIG_ENDIAN 713 sc->fc.irx_post = fwohci_irx_post; 714 #else 715 sc->fc.irx_post = NULL; 716 #endif 717 sc->fc.itx_post = NULL; 718 sc->fc.timeout = fwohci_timeout; 719 sc->fc.poll = fwohci_poll; 720 sc->fc.set_intr = fwohci_set_intr; 721 722 sc->intmask = sc->irstat = sc->itstat = 0; 723 724 fw_init(&sc->fc); 725 fwohci_reset(sc, dev); 726 727 return 0; 728 } 729 730 void 731 fwohci_timeout(void *arg) 732 { 733 struct fwohci_softc *sc; 734 735 sc = (struct fwohci_softc *)arg; 736 } 737 738 u_int32_t 739 fwohci_cyctimer(struct firewire_comm *fc) 740 { 741 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 742 return(OREAD(sc, OHCI_CYCLETIMER)); 743 } 744 745 int 746 fwohci_detach(struct fwohci_softc *sc, device_t dev) 747 { 748 int i; 749 750 if (sc->sid_buf != NULL) 751 fwdma_free(&sc->fc, &sc->sid_dma); 752 if (sc->fc.config_rom != NULL) 753 fwdma_free(&sc->fc, &sc->crom_dma); 754 755 fwohci_db_free(&sc->arrq); 756 fwohci_db_free(&sc->arrs); 757 758 fwohci_db_free(&sc->atrq); 759 fwohci_db_free(&sc->atrs); 760 761 for( i = 0 ; i < sc->fc.nisodma ; i ++ ){ 762 fwohci_db_free(&sc->it[i]); 763 fwohci_db_free(&sc->ir[i]); 764 } 765 766 return 0; 767 } 768 769 #define LAST_DB(dbtr, db) do { \ 770 struct fwohcidb_tr *_dbtr = (dbtr); \ 771 int _cnt = _dbtr->dbcnt; \ 772 db = &_dbtr->db[ (_cnt > 2) ? (_cnt -1) : 0]; \ 773 } while (0) 774 775 static void 776 fwohci_execute_db(void *arg, bus_dma_segment_t *segs, int nseg, int error) 777 { 778 struct fwohcidb_tr *db_tr; 779 volatile struct fwohcidb *db; 780 bus_dma_segment_t *s; 781 int i; 782 783 db_tr = (struct fwohcidb_tr *)arg; 784 db = &db_tr->db[db_tr->dbcnt]; 785 if (error) { 786 if (firewire_debug || error != EFBIG) 787 printf("fwohci_execute_db: error=%d\n", error); 788 return; 789 } 790 for (i = 0; i < nseg; i++) { 791 s = &segs[i]; 792 FWOHCI_DMA_WRITE(db->db.desc.addr, s->ds_addr); 793 FWOHCI_DMA_WRITE(db->db.desc.cmd, s->ds_len); 794 FWOHCI_DMA_WRITE(db->db.desc.res, 0); 795 db++; 796 db_tr->dbcnt++; 797 } 798 } 799 800 static void 801 fwohci_execute_db2(void *arg, bus_dma_segment_t *segs, int nseg, 802 bus_size_t size, int error) 803 { 804 fwohci_execute_db(arg, segs, nseg, error); 805 } 806 807 static void 808 fwohci_start(struct fwohci_softc *sc, struct fwohci_dbch *dbch) 809 { 810 int i, s; 811 int tcode, hdr_len, pl_off, pl_len; 812 int fsegment = -1; 813 u_int32_t off; 814 struct fw_xfer *xfer; 815 struct fw_pkt *fp; 816 volatile struct fwohci_txpkthdr *ohcifp; 817 struct fwohcidb_tr *db_tr; 818 volatile struct fwohcidb *db; 819 struct tcode_info *info; 820 static int maxdesc=0; 821 822 if(&sc->atrq == dbch){ 823 off = OHCI_ATQOFF; 824 }else if(&sc->atrs == dbch){ 825 off = OHCI_ATSOFF; 826 }else{ 827 return; 828 } 829 830 if (dbch->flags & FWOHCI_DBCH_FULL) 831 return; 832 833 s = splfw(); 834 db_tr = dbch->top; 835 txloop: 836 xfer = STAILQ_FIRST(&dbch->xferq.q); 837 if(xfer == NULL){ 838 goto kick; 839 } 840 if(dbch->xferq.queued == 0 ){ 841 device_printf(sc->fc.dev, "TX queue empty\n"); 842 } 843 STAILQ_REMOVE_HEAD(&dbch->xferq.q, link); 844 db_tr->xfer = xfer; 845 xfer->state = FWXF_START; 846 847 fp = (struct fw_pkt *)xfer->send.buf; 848 tcode = fp->mode.common.tcode; 849 850 ohcifp = (volatile struct fwohci_txpkthdr *) db_tr->db[1].db.immed; 851 info = &tinfo[tcode]; 852 hdr_len = pl_off = info->hdr_len; 853 for( i = 0 ; i < pl_off ; i+= 4){ 854 ohcifp->mode.ld[i/4] = fp->mode.ld[i/4]; 855 } 856 ohcifp->mode.common.spd = xfer->spd; 857 if (tcode == FWTCODE_STREAM ){ 858 hdr_len = 8; 859 ohcifp->mode.stream.len = fp->mode.stream.len; 860 } else if (tcode == FWTCODE_PHY) { 861 hdr_len = 12; 862 ohcifp->mode.ld[1] = fp->mode.ld[1]; 863 ohcifp->mode.ld[2] = fp->mode.ld[2]; 864 ohcifp->mode.common.spd = 0; 865 ohcifp->mode.common.tcode = FWOHCITCODE_PHY; 866 } else { 867 ohcifp->mode.asycomm.dst = fp->mode.hdr.dst; 868 ohcifp->mode.asycomm.srcbus = OHCI_ASYSRCBUS; 869 ohcifp->mode.asycomm.tlrt |= FWRETRY_X; 870 } 871 db = &db_tr->db[0]; 872 FWOHCI_DMA_WRITE(db->db.desc.cmd, 873 OHCI_OUTPUT_MORE | OHCI_KEY_ST2 | hdr_len); 874 FWOHCI_DMA_WRITE(db->db.desc.res, 0); 875 /* Specify bound timer of asy. responce */ 876 if(&sc->atrs == dbch){ 877 FWOHCI_DMA_WRITE(db->db.desc.res, 878 (OREAD(sc, OHCI_CYCLETIMER) >> 12) + (1 << 13)); 879 } 880 #if BYTE_ORDER == BIG_ENDIAN 881 if (tcode == FWTCODE_WREQQ || tcode == FWTCODE_RRESQ) 882 hdr_len = 12; 883 for (i = 0; i < hdr_len/4; i ++) 884 FWOHCI_DMA_WRITE(ohcifp->mode.ld[i], ohcifp->mode.ld[i]); 885 #endif 886 887 again: 888 db_tr->dbcnt = 2; 889 db = &db_tr->db[db_tr->dbcnt]; 890 pl_len = xfer->send.len - pl_off; 891 if (pl_len > 0) { 892 int err; 893 /* handle payload */ 894 if (xfer->mbuf == NULL) { 895 caddr_t pl_addr; 896 897 pl_addr = xfer->send.buf + pl_off; 898 err = bus_dmamap_load(dbch->dmat, db_tr->dma_map, 899 pl_addr, pl_len, 900 fwohci_execute_db, db_tr, 901 /*flags*/0); 902 } else { 903 /* XXX we can handle only 6 (=8-2) mbuf chains */ 904 err = bus_dmamap_load_mbuf(dbch->dmat, db_tr->dma_map, 905 xfer->mbuf, 906 fwohci_execute_db2, db_tr, 907 /* flags */0); 908 if (err == EFBIG) { 909 struct mbuf *m0; 910 911 if (firewire_debug) 912 device_printf(sc->fc.dev, "EFBIG.\n"); 913 m0 = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 914 if (m0 != NULL) { 915 m_copydata(xfer->mbuf, 0, 916 xfer->mbuf->m_pkthdr.len, 917 mtod(m0, caddr_t)); 918 m0->m_len = m0->m_pkthdr.len = 919 xfer->mbuf->m_pkthdr.len; 920 m_freem(xfer->mbuf); 921 xfer->mbuf = m0; 922 goto again; 923 } 924 device_printf(sc->fc.dev, "m_getcl failed.\n"); 925 } 926 } 927 if (err) 928 printf("dmamap_load: err=%d\n", err); 929 bus_dmamap_sync(dbch->dmat, db_tr->dma_map, 930 BUS_DMASYNC_PREWRITE); 931 #if 0 /* OHCI_OUTPUT_MODE == 0 */ 932 for (i = 2; i < db_tr->dbcnt; i++) 933 FWOHCI_DMA_SET(db_tr->db[i].db.desc.cmd, 934 OHCI_OUTPUT_MORE); 935 #endif 936 } 937 if (maxdesc < db_tr->dbcnt) { 938 maxdesc = db_tr->dbcnt; 939 if (bootverbose) 940 device_printf(sc->fc.dev, "maxdesc: %d\n", maxdesc); 941 } 942 /* last db */ 943 LAST_DB(db_tr, db); 944 FWOHCI_DMA_SET(db->db.desc.cmd, 945 OHCI_OUTPUT_LAST | OHCI_INTERRUPT_ALWAYS | OHCI_BRANCH_ALWAYS); 946 FWOHCI_DMA_WRITE(db->db.desc.depend, 947 STAILQ_NEXT(db_tr, link)->bus_addr); 948 949 if(fsegment == -1 ) 950 fsegment = db_tr->dbcnt; 951 if (dbch->pdb_tr != NULL) { 952 LAST_DB(dbch->pdb_tr, db); 953 FWOHCI_DMA_SET(db->db.desc.depend, db_tr->dbcnt); 954 } 955 dbch->pdb_tr = db_tr; 956 db_tr = STAILQ_NEXT(db_tr, link); 957 if(db_tr != dbch->bottom){ 958 goto txloop; 959 } else { 960 device_printf(sc->fc.dev, "fwohci_start: lack of db_trq\n"); 961 dbch->flags |= FWOHCI_DBCH_FULL; 962 } 963 kick: 964 /* kick asy q */ 965 fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREREAD); 966 fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREWRITE); 967 968 if(dbch->xferq.flag & FWXFERQ_RUNNING) { 969 OWRITE(sc, OHCI_DMACTL(off), OHCI_CNTL_DMA_WAKE); 970 } else { 971 if (bootverbose) 972 device_printf(sc->fc.dev, "start AT DMA status=%x\n", 973 OREAD(sc, OHCI_DMACTL(off))); 974 OWRITE(sc, OHCI_DMACMD(off), dbch->top->bus_addr | fsegment); 975 OWRITE(sc, OHCI_DMACTL(off), OHCI_CNTL_DMA_RUN); 976 dbch->xferq.flag |= FWXFERQ_RUNNING; 977 } 978 979 dbch->top = db_tr; 980 splx(s); 981 return; 982 } 983 984 static void 985 fwohci_start_atq(struct firewire_comm *fc) 986 { 987 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 988 fwohci_start( sc, &(sc->atrq)); 989 return; 990 } 991 992 static void 993 fwohci_start_ats(struct firewire_comm *fc) 994 { 995 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 996 fwohci_start( sc, &(sc->atrs)); 997 return; 998 } 999 1000 void 1001 fwohci_txd(struct fwohci_softc *sc, struct fwohci_dbch *dbch) 1002 { 1003 int s, ch, err = 0; 1004 struct fwohcidb_tr *tr; 1005 volatile struct fwohcidb *db; 1006 struct fw_xfer *xfer; 1007 u_int32_t off; 1008 u_int stat, status; 1009 int packets; 1010 struct firewire_comm *fc = (struct firewire_comm *)sc; 1011 1012 if(&sc->atrq == dbch){ 1013 off = OHCI_ATQOFF; 1014 ch = ATRQ_CH; 1015 }else if(&sc->atrs == dbch){ 1016 off = OHCI_ATSOFF; 1017 ch = ATRS_CH; 1018 }else{ 1019 return; 1020 } 1021 s = splfw(); 1022 tr = dbch->bottom; 1023 packets = 0; 1024 fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_POSTREAD); 1025 fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_POSTWRITE); 1026 while(dbch->xferq.queued > 0){ 1027 LAST_DB(tr, db); 1028 status = FWOHCI_DMA_READ(db->db.desc.res) >> OHCI_STATUS_SHIFT; 1029 if(!(status & OHCI_CNTL_DMA_ACTIVE)){ 1030 if (fc->status != FWBUSRESET) 1031 /* maybe out of order?? */ 1032 goto out; 1033 } 1034 bus_dmamap_sync(dbch->dmat, tr->dma_map, 1035 BUS_DMASYNC_POSTWRITE); 1036 bus_dmamap_unload(dbch->dmat, tr->dma_map); 1037 #if 0 1038 dump_db(sc, ch); 1039 #endif 1040 if(status & OHCI_CNTL_DMA_DEAD) { 1041 /* Stop DMA */ 1042 OWRITE(sc, OHCI_DMACTLCLR(off), OHCI_CNTL_DMA_RUN); 1043 device_printf(sc->fc.dev, "force reset AT FIFO\n"); 1044 OWRITE(sc, OHCI_HCCCTLCLR, OHCI_HCC_LINKEN); 1045 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_LPS | OHCI_HCC_LINKEN); 1046 OWRITE(sc, OHCI_DMACTLCLR(off), OHCI_CNTL_DMA_RUN); 1047 } 1048 stat = status & FWOHCIEV_MASK; 1049 switch(stat){ 1050 case FWOHCIEV_ACKPEND: 1051 case FWOHCIEV_ACKCOMPL: 1052 err = 0; 1053 break; 1054 case FWOHCIEV_ACKBSA: 1055 case FWOHCIEV_ACKBSB: 1056 case FWOHCIEV_ACKBSX: 1057 device_printf(sc->fc.dev, "txd err=%2x %s\n", stat, fwohcicode[stat]); 1058 err = EBUSY; 1059 break; 1060 case FWOHCIEV_FLUSHED: 1061 case FWOHCIEV_ACKTARD: 1062 device_printf(sc->fc.dev, "txd err=%2x %s\n", stat, fwohcicode[stat]); 1063 err = EAGAIN; 1064 break; 1065 case FWOHCIEV_MISSACK: 1066 case FWOHCIEV_UNDRRUN: 1067 case FWOHCIEV_OVRRUN: 1068 case FWOHCIEV_DESCERR: 1069 case FWOHCIEV_DTRDERR: 1070 case FWOHCIEV_TIMEOUT: 1071 case FWOHCIEV_TCODERR: 1072 case FWOHCIEV_UNKNOWN: 1073 case FWOHCIEV_ACKDERR: 1074 case FWOHCIEV_ACKTERR: 1075 default: 1076 device_printf(sc->fc.dev, "txd err=%2x %s\n", 1077 stat, fwohcicode[stat]); 1078 err = EINVAL; 1079 break; 1080 } 1081 if (tr->xfer != NULL) { 1082 xfer = tr->xfer; 1083 if (xfer->state == FWXF_RCVD) { 1084 if (firewire_debug) 1085 printf("already rcvd\n"); 1086 fw_xfer_done(xfer); 1087 } else { 1088 xfer->state = FWXF_SENT; 1089 if (err == EBUSY && fc->status != FWBUSRESET) { 1090 xfer->state = FWXF_BUSY; 1091 xfer->resp = err; 1092 if (xfer->retry_req != NULL) 1093 xfer->retry_req(xfer); 1094 else { 1095 xfer->recv.len = 0; 1096 fw_xfer_done(xfer); 1097 } 1098 } else if (stat != FWOHCIEV_ACKPEND) { 1099 if (stat != FWOHCIEV_ACKCOMPL) 1100 xfer->state = FWXF_SENTERR; 1101 xfer->resp = err; 1102 xfer->recv.len = 0; 1103 fw_xfer_done(xfer); 1104 } 1105 } 1106 /* 1107 * The watchdog timer takes care of split 1108 * transcation timeout for ACKPEND case. 1109 */ 1110 } else { 1111 printf("this shouldn't happen\n"); 1112 } 1113 dbch->xferq.queued --; 1114 tr->xfer = NULL; 1115 1116 packets ++; 1117 tr = STAILQ_NEXT(tr, link); 1118 dbch->bottom = tr; 1119 if (dbch->bottom == dbch->top) { 1120 /* we reaches the end of context program */ 1121 if (firewire_debug && dbch->xferq.queued > 0) 1122 printf("queued > 0\n"); 1123 break; 1124 } 1125 } 1126 out: 1127 if ((dbch->flags & FWOHCI_DBCH_FULL) && packets > 0) { 1128 printf("make free slot\n"); 1129 dbch->flags &= ~FWOHCI_DBCH_FULL; 1130 fwohci_start(sc, dbch); 1131 } 1132 splx(s); 1133 } 1134 1135 static void 1136 fwohci_db_free(struct fwohci_dbch *dbch) 1137 { 1138 struct fwohcidb_tr *db_tr; 1139 int idb; 1140 1141 if ((dbch->flags & FWOHCI_DBCH_INIT) == 0) 1142 return; 1143 1144 for(db_tr = STAILQ_FIRST(&dbch->db_trq), idb = 0; idb < dbch->ndb; 1145 db_tr = STAILQ_NEXT(db_tr, link), idb++){ 1146 if ((dbch->xferq.flag & FWXFERQ_EXTBUF) == 0 && 1147 db_tr->buf != NULL) { 1148 fwdma_free_size(dbch->dmat, db_tr->dma_map, 1149 db_tr->buf, dbch->xferq.psize); 1150 db_tr->buf = NULL; 1151 } else if (db_tr->dma_map != NULL) 1152 bus_dmamap_destroy(dbch->dmat, db_tr->dma_map); 1153 } 1154 dbch->ndb = 0; 1155 db_tr = STAILQ_FIRST(&dbch->db_trq); 1156 fwdma_free_multiseg(dbch->am); 1157 free(db_tr, M_FW); 1158 STAILQ_INIT(&dbch->db_trq); 1159 dbch->flags &= ~FWOHCI_DBCH_INIT; 1160 } 1161 1162 static void 1163 fwohci_db_init(struct fwohci_softc *sc, struct fwohci_dbch *dbch) 1164 { 1165 int idb; 1166 struct fwohcidb_tr *db_tr; 1167 1168 if ((dbch->flags & FWOHCI_DBCH_INIT) != 0) 1169 goto out; 1170 1171 /* create dma_tag for buffers */ 1172 #define MAX_REQCOUNT 0xffff 1173 if (bus_dma_tag_create(/*parent*/ sc->fc.dmat, 1174 /*alignment*/ 1, /*boundary*/ 0, 1175 /*lowaddr*/ BUS_SPACE_MAXADDR_32BIT, 1176 /*highaddr*/ BUS_SPACE_MAXADDR, 1177 /*filter*/NULL, /*filterarg*/NULL, 1178 /*maxsize*/ dbch->xferq.psize, 1179 /*nsegments*/ dbch->ndesc > 3 ? dbch->ndesc - 2 : 1, 1180 /*maxsegsz*/ MAX_REQCOUNT, 1181 /*flags*/ 0, &dbch->dmat)) 1182 return; 1183 1184 /* allocate DB entries and attach one to each DMA channels */ 1185 /* DB entry must start at 16 bytes bounary. */ 1186 STAILQ_INIT(&dbch->db_trq); 1187 db_tr = (struct fwohcidb_tr *) 1188 malloc(sizeof(struct fwohcidb_tr) * dbch->ndb, 1189 M_FW, M_WAITOK | M_ZERO); 1190 if(db_tr == NULL){ 1191 printf("fwohci_db_init: malloc(1) failed\n"); 1192 return; 1193 } 1194 1195 #define DB_SIZE(x) (sizeof(struct fwohcidb) * (x)->ndesc) 1196 dbch->am = fwdma_malloc_multiseg(&sc->fc, DB_SIZE(dbch), 1197 DB_SIZE(dbch), dbch->ndb, BUS_DMA_WAITOK); 1198 if (dbch->am == NULL) { 1199 printf("fwohci_db_init: fwdma_malloc_multiseg failed\n"); 1200 return; 1201 } 1202 /* Attach DB to DMA ch. */ 1203 for(idb = 0 ; idb < dbch->ndb ; idb++){ 1204 db_tr->dbcnt = 0; 1205 db_tr->db = (struct fwohcidb *)fwdma_v_addr(dbch->am, idb); 1206 db_tr->bus_addr = fwdma_bus_addr(dbch->am, idb); 1207 /* create dmamap for buffers */ 1208 /* XXX do we need 4bytes alignment tag? */ 1209 /* XXX don't alloc dma_map for AR */ 1210 if (bus_dmamap_create(dbch->dmat, 0, &db_tr->dma_map) != 0) { 1211 printf("bus_dmamap_create failed\n"); 1212 dbch->flags = FWOHCI_DBCH_INIT; /* XXX fake */ 1213 fwohci_db_free(dbch); 1214 return; 1215 } 1216 STAILQ_INSERT_TAIL(&dbch->db_trq, db_tr, link); 1217 if (dbch->xferq.flag & FWXFERQ_EXTBUF) { 1218 if (idb % dbch->xferq.bnpacket == 0) 1219 dbch->xferq.bulkxfer[idb / dbch->xferq.bnpacket 1220 ].start = (caddr_t)db_tr; 1221 if ((idb + 1) % dbch->xferq.bnpacket == 0) 1222 dbch->xferq.bulkxfer[idb / dbch->xferq.bnpacket 1223 ].end = (caddr_t)db_tr; 1224 } 1225 db_tr++; 1226 } 1227 STAILQ_LAST(&dbch->db_trq, fwohcidb_tr,link)->link.stqe_next 1228 = STAILQ_FIRST(&dbch->db_trq); 1229 out: 1230 dbch->xferq.queued = 0; 1231 dbch->pdb_tr = NULL; 1232 dbch->top = STAILQ_FIRST(&dbch->db_trq); 1233 dbch->bottom = dbch->top; 1234 dbch->flags = FWOHCI_DBCH_INIT; 1235 } 1236 1237 static int 1238 fwohci_itx_disable(struct firewire_comm *fc, int dmach) 1239 { 1240 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 1241 int sleepch; 1242 1243 OWRITE(sc, OHCI_ITCTLCLR(dmach), 1244 OHCI_CNTL_DMA_RUN | OHCI_CNTL_CYCMATCH_S); 1245 OWRITE(sc, OHCI_IT_MASKCLR, 1 << dmach); 1246 OWRITE(sc, OHCI_IT_STATCLR, 1 << dmach); 1247 /* XXX we cannot free buffers until the DMA really stops */ 1248 tsleep((void *)&sleepch, FWPRI, "fwitxd", hz); 1249 fwohci_db_free(&sc->it[dmach]); 1250 sc->it[dmach].xferq.flag &= ~FWXFERQ_RUNNING; 1251 return 0; 1252 } 1253 1254 static int 1255 fwohci_irx_disable(struct firewire_comm *fc, int dmach) 1256 { 1257 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 1258 int sleepch; 1259 1260 OWRITE(sc, OHCI_IRCTLCLR(dmach), OHCI_CNTL_DMA_RUN); 1261 OWRITE(sc, OHCI_IR_MASKCLR, 1 << dmach); 1262 OWRITE(sc, OHCI_IR_STATCLR, 1 << dmach); 1263 /* XXX we cannot free buffers until the DMA really stops */ 1264 tsleep((void *)&sleepch, FWPRI, "fwirxd", hz); 1265 fwohci_db_free(&sc->ir[dmach]); 1266 sc->ir[dmach].xferq.flag &= ~FWXFERQ_RUNNING; 1267 return 0; 1268 } 1269 1270 #if BYTE_ORDER == BIG_ENDIAN 1271 static void 1272 fwohci_irx_post (struct firewire_comm *fc , u_int32_t *qld) 1273 { 1274 qld[0] = FWOHCI_DMA_READ(qld[0]); 1275 return; 1276 } 1277 #endif 1278 1279 static int 1280 fwohci_tx_enable(struct fwohci_softc *sc, struct fwohci_dbch *dbch) 1281 { 1282 int err = 0; 1283 int idb, z, i, dmach = 0, ldesc; 1284 u_int32_t off = NULL; 1285 struct fwohcidb_tr *db_tr; 1286 volatile struct fwohcidb *db; 1287 1288 if(!(dbch->xferq.flag & FWXFERQ_EXTBUF)){ 1289 err = EINVAL; 1290 return err; 1291 } 1292 z = dbch->ndesc; 1293 for(dmach = 0 ; dmach < sc->fc.nisodma ; dmach++){ 1294 if( &sc->it[dmach] == dbch){ 1295 off = OHCI_ITOFF(dmach); 1296 break; 1297 } 1298 } 1299 if(off == NULL){ 1300 err = EINVAL; 1301 return err; 1302 } 1303 if(dbch->xferq.flag & FWXFERQ_RUNNING) 1304 return err; 1305 dbch->xferq.flag |= FWXFERQ_RUNNING; 1306 for( i = 0, dbch->bottom = dbch->top; i < (dbch->ndb - 1); i++){ 1307 dbch->bottom = STAILQ_NEXT(dbch->bottom, link); 1308 } 1309 db_tr = dbch->top; 1310 for (idb = 0; idb < dbch->ndb; idb ++) { 1311 fwohci_add_tx_buf(dbch, db_tr, idb); 1312 if(STAILQ_NEXT(db_tr, link) == NULL){ 1313 break; 1314 } 1315 db = db_tr->db; 1316 ldesc = db_tr->dbcnt - 1; 1317 FWOHCI_DMA_WRITE(db[0].db.desc.depend, 1318 STAILQ_NEXT(db_tr, link)->bus_addr | z); 1319 db[ldesc].db.desc.depend = db[0].db.desc.depend; 1320 if(dbch->xferq.flag & FWXFERQ_EXTBUF){ 1321 if(((idb + 1 ) % dbch->xferq.bnpacket) == 0){ 1322 FWOHCI_DMA_SET( 1323 db[ldesc].db.desc.cmd, 1324 OHCI_INTERRUPT_ALWAYS); 1325 /* OHCI 1.1 and above */ 1326 FWOHCI_DMA_SET( 1327 db[0].db.desc.cmd, 1328 OHCI_INTERRUPT_ALWAYS); 1329 } 1330 } 1331 db_tr = STAILQ_NEXT(db_tr, link); 1332 } 1333 FWOHCI_DMA_CLEAR( 1334 dbch->bottom->db[dbch->bottom->dbcnt - 1].db.desc.depend, 0xf); 1335 return err; 1336 } 1337 1338 static int 1339 fwohci_rx_enable(struct fwohci_softc *sc, struct fwohci_dbch *dbch) 1340 { 1341 int err = 0; 1342 int idb, z, i, dmach = 0, ldesc; 1343 u_int32_t off = NULL; 1344 struct fwohcidb_tr *db_tr; 1345 volatile struct fwohcidb *db; 1346 1347 z = dbch->ndesc; 1348 if(&sc->arrq == dbch){ 1349 off = OHCI_ARQOFF; 1350 }else if(&sc->arrs == dbch){ 1351 off = OHCI_ARSOFF; 1352 }else{ 1353 for(dmach = 0 ; dmach < sc->fc.nisodma ; dmach++){ 1354 if( &sc->ir[dmach] == dbch){ 1355 off = OHCI_IROFF(dmach); 1356 break; 1357 } 1358 } 1359 } 1360 if(off == NULL){ 1361 err = EINVAL; 1362 return err; 1363 } 1364 if(dbch->xferq.flag & FWXFERQ_STREAM){ 1365 if(dbch->xferq.flag & FWXFERQ_RUNNING) 1366 return err; 1367 }else{ 1368 if(dbch->xferq.flag & FWXFERQ_RUNNING){ 1369 err = EBUSY; 1370 return err; 1371 } 1372 } 1373 dbch->xferq.flag |= FWXFERQ_RUNNING; 1374 dbch->top = STAILQ_FIRST(&dbch->db_trq); 1375 for( i = 0, dbch->bottom = dbch->top; i < (dbch->ndb - 1); i++){ 1376 dbch->bottom = STAILQ_NEXT(dbch->bottom, link); 1377 } 1378 db_tr = dbch->top; 1379 for (idb = 0; idb < dbch->ndb; idb ++) { 1380 fwohci_add_rx_buf(dbch, db_tr, idb, &sc->dummy_dma); 1381 if (STAILQ_NEXT(db_tr, link) == NULL) 1382 break; 1383 db = db_tr->db; 1384 ldesc = db_tr->dbcnt - 1; 1385 FWOHCI_DMA_WRITE(db[ldesc].db.desc.depend, 1386 STAILQ_NEXT(db_tr, link)->bus_addr | z); 1387 if(dbch->xferq.flag & FWXFERQ_EXTBUF){ 1388 if(((idb + 1 ) % dbch->xferq.bnpacket) == 0){ 1389 FWOHCI_DMA_SET( 1390 db[ldesc].db.desc.cmd, 1391 OHCI_INTERRUPT_ALWAYS); 1392 FWOHCI_DMA_CLEAR( 1393 db[ldesc].db.desc.depend, 1394 0xf); 1395 } 1396 } 1397 db_tr = STAILQ_NEXT(db_tr, link); 1398 } 1399 FWOHCI_DMA_CLEAR( 1400 dbch->bottom->db[db_tr->dbcnt - 1].db.desc.depend, 0xf); 1401 dbch->buf_offset = 0; 1402 fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREREAD); 1403 fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREWRITE); 1404 if(dbch->xferq.flag & FWXFERQ_STREAM){ 1405 return err; 1406 }else{ 1407 OWRITE(sc, OHCI_DMACMD(off), dbch->top->bus_addr | z); 1408 } 1409 OWRITE(sc, OHCI_DMACTL(off), OHCI_CNTL_DMA_RUN); 1410 return err; 1411 } 1412 1413 static int 1414 fwohci_next_cycle(struct firewire_comm *fc, int cycle_now) 1415 { 1416 int sec, cycle, cycle_match; 1417 1418 cycle = cycle_now & 0x1fff; 1419 sec = cycle_now >> 13; 1420 #define CYCLE_MOD 0x10 1421 #if 1 1422 #define CYCLE_DELAY 8 /* min delay to start DMA */ 1423 #else 1424 #define CYCLE_DELAY 7000 /* min delay to start DMA */ 1425 #endif 1426 cycle = cycle + CYCLE_DELAY; 1427 if (cycle >= 8000) { 1428 sec ++; 1429 cycle -= 8000; 1430 } 1431 cycle = roundup2(cycle, CYCLE_MOD); 1432 if (cycle >= 8000) { 1433 sec ++; 1434 if (cycle == 8000) 1435 cycle = 0; 1436 else 1437 cycle = CYCLE_MOD; 1438 } 1439 cycle_match = ((sec << 13) | cycle) & 0x7ffff; 1440 1441 return(cycle_match); 1442 } 1443 1444 static int 1445 fwohci_itxbuf_enable(struct firewire_comm *fc, int dmach) 1446 { 1447 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 1448 int err = 0; 1449 unsigned short tag, ich; 1450 struct fwohci_dbch *dbch; 1451 int cycle_match, cycle_now, s, ldesc; 1452 u_int32_t stat; 1453 struct fw_bulkxfer *first, *chunk, *prev; 1454 struct fw_xferq *it; 1455 1456 dbch = &sc->it[dmach]; 1457 it = &dbch->xferq; 1458 1459 tag = (it->flag >> 6) & 3; 1460 ich = it->flag & 0x3f; 1461 if ((dbch->flags & FWOHCI_DBCH_INIT) == 0) { 1462 dbch->ndb = it->bnpacket * it->bnchunk; 1463 dbch->ndesc = 3; 1464 fwohci_db_init(sc, dbch); 1465 if ((dbch->flags & FWOHCI_DBCH_INIT) == 0) 1466 return ENOMEM; 1467 err = fwohci_tx_enable(sc, dbch); 1468 } 1469 if(err) 1470 return err; 1471 1472 ldesc = dbch->ndesc - 1; 1473 s = splfw(); 1474 prev = STAILQ_LAST(&it->stdma, fw_bulkxfer, link); 1475 while ((chunk = STAILQ_FIRST(&it->stvalid)) != NULL) { 1476 volatile struct fwohcidb *db; 1477 1478 fwdma_sync_multiseg(it->buf, chunk->poffset, it->bnpacket, 1479 BUS_DMASYNC_PREWRITE); 1480 fwohci_txbufdb(sc, dmach, chunk); 1481 if (prev != NULL) { 1482 db = ((struct fwohcidb_tr *)(prev->end))->db; 1483 #if 0 /* XXX necessary? */ 1484 FWOHCI_DMA_SET(db[ldesc].db.desc.cmd, 1485 OHCI_BRANCH_ALWAYS); 1486 #endif 1487 #if 0 /* if bulkxfer->npacket changes */ 1488 db[ldesc].db.desc.depend = db[0].db.desc.depend = 1489 ((struct fwohcidb_tr *) 1490 (chunk->start))->bus_addr | dbch->ndesc; 1491 #else 1492 FWOHCI_DMA_SET(db[0].db.desc.depend, dbch->ndesc); 1493 FWOHCI_DMA_SET(db[ldesc].db.desc.depend, dbch->ndesc); 1494 #endif 1495 } 1496 STAILQ_REMOVE_HEAD(&it->stvalid, link); 1497 STAILQ_INSERT_TAIL(&it->stdma, chunk, link); 1498 prev = chunk; 1499 } 1500 fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREWRITE); 1501 fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREREAD); 1502 splx(s); 1503 stat = OREAD(sc, OHCI_ITCTL(dmach)); 1504 if (firewire_debug && (stat & OHCI_CNTL_CYCMATCH_S)) 1505 printf("stat 0x%x\n", stat); 1506 1507 if (stat & (OHCI_CNTL_DMA_ACTIVE | OHCI_CNTL_CYCMATCH_S)) 1508 return 0; 1509 1510 #if 0 1511 OWRITE(sc, OHCI_ITCTLCLR(dmach), OHCI_CNTL_DMA_RUN); 1512 #endif 1513 OWRITE(sc, OHCI_IT_MASKCLR, 1 << dmach); 1514 OWRITE(sc, OHCI_IT_STATCLR, 1 << dmach); 1515 OWRITE(sc, OHCI_IT_MASK, 1 << dmach); 1516 OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_DMA_IT); 1517 1518 first = STAILQ_FIRST(&it->stdma); 1519 OWRITE(sc, OHCI_ITCMD(dmach), 1520 ((struct fwohcidb_tr *)(first->start))->bus_addr | dbch->ndesc); 1521 if (firewire_debug) { 1522 printf("fwohci_itxbuf_enable: kick 0x%08x\n", stat); 1523 #if 1 1524 dump_dma(sc, ITX_CH + dmach); 1525 #endif 1526 } 1527 if ((stat & OHCI_CNTL_DMA_RUN) == 0) { 1528 #if 1 1529 /* Don't start until all chunks are buffered */ 1530 if (STAILQ_FIRST(&it->stfree) != NULL) 1531 goto out; 1532 #endif 1533 #if 1 1534 /* Clear cycle match counter bits */ 1535 OWRITE(sc, OHCI_ITCTLCLR(dmach), 0xffff0000); 1536 1537 /* 2bit second + 13bit cycle */ 1538 cycle_now = (fc->cyctimer(fc) >> 12) & 0x7fff; 1539 cycle_match = fwohci_next_cycle(fc, cycle_now); 1540 1541 OWRITE(sc, OHCI_ITCTL(dmach), 1542 OHCI_CNTL_CYCMATCH_S | (cycle_match << 16) 1543 | OHCI_CNTL_DMA_RUN); 1544 #else 1545 OWRITE(sc, OHCI_ITCTL(dmach), OHCI_CNTL_DMA_RUN); 1546 #endif 1547 if (firewire_debug) { 1548 printf("cycle_match: 0x%04x->0x%04x\n", 1549 cycle_now, cycle_match); 1550 dump_dma(sc, ITX_CH + dmach); 1551 dump_db(sc, ITX_CH + dmach); 1552 } 1553 } else if ((stat & OHCI_CNTL_CYCMATCH_S) == 0) { 1554 device_printf(sc->fc.dev, 1555 "IT DMA underrun (0x%08x)\n", stat); 1556 OWRITE(sc, OHCI_ITCTL(dmach), OHCI_CNTL_DMA_WAKE); 1557 } 1558 out: 1559 return err; 1560 } 1561 1562 static int 1563 fwohci_irx_enable(struct firewire_comm *fc, int dmach) 1564 { 1565 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 1566 int err = 0, s, ldesc; 1567 unsigned short tag, ich; 1568 u_int32_t stat; 1569 struct fwohci_dbch *dbch; 1570 struct fwohcidb_tr *db_tr; 1571 struct fw_bulkxfer *first, *prev, *chunk; 1572 struct fw_xferq *ir; 1573 1574 dbch = &sc->ir[dmach]; 1575 ir = &dbch->xferq; 1576 1577 if ((ir->flag & FWXFERQ_RUNNING) == 0) { 1578 tag = (ir->flag >> 6) & 3; 1579 ich = ir->flag & 0x3f; 1580 OWRITE(sc, OHCI_IRMATCH(dmach), tagbit[tag] | ich); 1581 1582 ir->queued = 0; 1583 dbch->ndb = ir->bnpacket * ir->bnchunk; 1584 dbch->ndesc = 2; 1585 fwohci_db_init(sc, dbch); 1586 if ((dbch->flags & FWOHCI_DBCH_INIT) == 0) 1587 return ENOMEM; 1588 err = fwohci_rx_enable(sc, dbch); 1589 } 1590 if(err) 1591 return err; 1592 1593 first = STAILQ_FIRST(&ir->stfree); 1594 if (first == NULL) { 1595 device_printf(fc->dev, "IR DMA no free chunk\n"); 1596 return 0; 1597 } 1598 1599 ldesc = dbch->ndesc - 1; 1600 s = splfw(); 1601 prev = STAILQ_LAST(&ir->stdma, fw_bulkxfer, link); 1602 while ((chunk = STAILQ_FIRST(&ir->stfree)) != NULL) { 1603 volatile struct fwohcidb *db; 1604 1605 #if 1 /* XXX for if_fwe */ 1606 if (chunk->mbuf != NULL) { 1607 db_tr = (struct fwohcidb_tr *)(chunk->start); 1608 db_tr->dbcnt = 1; 1609 err = bus_dmamap_load_mbuf(dbch->dmat, db_tr->dma_map, 1610 chunk->mbuf, fwohci_execute_db2, db_tr, 1611 /* flags */0); 1612 FWOHCI_DMA_SET(db_tr->db[1].db.desc.cmd, 1613 OHCI_UPDATE | OHCI_INPUT_LAST | 1614 OHCI_INTERRUPT_ALWAYS | OHCI_BRANCH_ALWAYS); 1615 } 1616 #endif 1617 db = ((struct fwohcidb_tr *)(chunk->end))->db; 1618 FWOHCI_DMA_WRITE(db[ldesc].db.desc.res, 0); 1619 FWOHCI_DMA_CLEAR(db[ldesc].db.desc.depend, 0xf); 1620 if (prev != NULL) { 1621 db = ((struct fwohcidb_tr *)(prev->end))->db; 1622 FWOHCI_DMA_SET(db[ldesc].db.desc.depend, dbch->ndesc); 1623 } 1624 STAILQ_REMOVE_HEAD(&ir->stfree, link); 1625 STAILQ_INSERT_TAIL(&ir->stdma, chunk, link); 1626 prev = chunk; 1627 } 1628 fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREWRITE); 1629 fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREREAD); 1630 splx(s); 1631 stat = OREAD(sc, OHCI_IRCTL(dmach)); 1632 if (stat & OHCI_CNTL_DMA_ACTIVE) 1633 return 0; 1634 if (stat & OHCI_CNTL_DMA_RUN) { 1635 OWRITE(sc, OHCI_IRCTLCLR(dmach), OHCI_CNTL_DMA_RUN); 1636 device_printf(sc->fc.dev, "IR DMA overrun (0x%08x)\n", stat); 1637 } 1638 1639 if (firewire_debug) 1640 printf("start IR DMA 0x%x\n", stat); 1641 OWRITE(sc, OHCI_IR_MASKCLR, 1 << dmach); 1642 OWRITE(sc, OHCI_IR_STATCLR, 1 << dmach); 1643 OWRITE(sc, OHCI_IR_MASK, 1 << dmach); 1644 OWRITE(sc, OHCI_IRCTLCLR(dmach), 0xf0000000); 1645 OWRITE(sc, OHCI_IRCTL(dmach), OHCI_CNTL_ISOHDR); 1646 OWRITE(sc, OHCI_IRCMD(dmach), 1647 ((struct fwohcidb_tr *)(first->start))->bus_addr 1648 | dbch->ndesc); 1649 OWRITE(sc, OHCI_IRCTL(dmach), OHCI_CNTL_DMA_RUN); 1650 OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_DMA_IR); 1651 #if 0 1652 dump_db(sc, IRX_CH + dmach); 1653 #endif 1654 return err; 1655 } 1656 1657 int 1658 fwohci_stop(struct fwohci_softc *sc, device_t dev) 1659 { 1660 u_int i; 1661 1662 /* Now stopping all DMA channel */ 1663 OWRITE(sc, OHCI_ARQCTLCLR, OHCI_CNTL_DMA_RUN); 1664 OWRITE(sc, OHCI_ARSCTLCLR, OHCI_CNTL_DMA_RUN); 1665 OWRITE(sc, OHCI_ATQCTLCLR, OHCI_CNTL_DMA_RUN); 1666 OWRITE(sc, OHCI_ATSCTLCLR, OHCI_CNTL_DMA_RUN); 1667 1668 for( i = 0 ; i < sc->fc.nisodma ; i ++ ){ 1669 OWRITE(sc, OHCI_IRCTLCLR(i), OHCI_CNTL_DMA_RUN); 1670 OWRITE(sc, OHCI_ITCTLCLR(i), OHCI_CNTL_DMA_RUN); 1671 } 1672 1673 /* FLUSH FIFO and reset Transmitter/Reciever */ 1674 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_RESET); 1675 1676 /* Stop interrupt */ 1677 OWRITE(sc, FWOHCI_INTMASKCLR, 1678 OHCI_INT_EN | OHCI_INT_ERR | OHCI_INT_PHY_SID 1679 | OHCI_INT_PHY_INT 1680 | OHCI_INT_DMA_ATRQ | OHCI_INT_DMA_ATRS 1681 | OHCI_INT_DMA_PRRQ | OHCI_INT_DMA_PRRS 1682 | OHCI_INT_DMA_ARRQ | OHCI_INT_DMA_ARRS 1683 | OHCI_INT_PHY_BUS_R); 1684 /* XXX Link down? Bus reset? */ 1685 return 0; 1686 } 1687 1688 int 1689 fwohci_resume(struct fwohci_softc *sc, device_t dev) 1690 { 1691 int i; 1692 1693 fwohci_reset(sc, dev); 1694 /* XXX resume isochronus receive automatically. (how about TX?) */ 1695 for(i = 0; i < sc->fc.nisodma; i ++) { 1696 if((sc->ir[i].xferq.flag & FWXFERQ_RUNNING) != 0) { 1697 device_printf(sc->fc.dev, 1698 "resume iso receive ch: %d\n", i); 1699 sc->ir[i].xferq.flag &= ~FWXFERQ_RUNNING; 1700 sc->fc.irx_enable(&sc->fc, i); 1701 } 1702 } 1703 1704 bus_generic_resume(dev); 1705 sc->fc.ibr(&sc->fc); 1706 return 0; 1707 } 1708 1709 #define ACK_ALL 1710 static void 1711 fwohci_intr_body(struct fwohci_softc *sc, u_int32_t stat, int count) 1712 { 1713 u_int32_t irstat, itstat; 1714 u_int i; 1715 struct firewire_comm *fc = (struct firewire_comm *)sc; 1716 1717 #ifdef OHCI_DEBUG 1718 if(stat & OREAD(sc, FWOHCI_INTMASK)) 1719 device_printf(fc->dev, "INTERRUPT < %s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s> 0x%08x, 0x%08x\n", 1720 stat & OHCI_INT_EN ? "DMA_EN ":"", 1721 stat & OHCI_INT_PHY_REG ? "PHY_REG ":"", 1722 stat & OHCI_INT_CYC_LONG ? "CYC_LONG ":"", 1723 stat & OHCI_INT_ERR ? "INT_ERR ":"", 1724 stat & OHCI_INT_CYC_ERR ? "CYC_ERR ":"", 1725 stat & OHCI_INT_CYC_LOST ? "CYC_LOST ":"", 1726 stat & OHCI_INT_CYC_64SECOND ? "CYC_64SECOND ":"", 1727 stat & OHCI_INT_CYC_START ? "CYC_START ":"", 1728 stat & OHCI_INT_PHY_INT ? "PHY_INT ":"", 1729 stat & OHCI_INT_PHY_BUS_R ? "BUS_RESET ":"", 1730 stat & OHCI_INT_PHY_SID ? "SID ":"", 1731 stat & OHCI_INT_LR_ERR ? "DMA_LR_ERR ":"", 1732 stat & OHCI_INT_PW_ERR ? "DMA_PW_ERR ":"", 1733 stat & OHCI_INT_DMA_IR ? "DMA_IR ":"", 1734 stat & OHCI_INT_DMA_IT ? "DMA_IT " :"", 1735 stat & OHCI_INT_DMA_PRRS ? "DMA_PRRS " :"", 1736 stat & OHCI_INT_DMA_PRRQ ? "DMA_PRRQ " :"", 1737 stat & OHCI_INT_DMA_ARRS ? "DMA_ARRS " :"", 1738 stat & OHCI_INT_DMA_ARRQ ? "DMA_ARRQ " :"", 1739 stat & OHCI_INT_DMA_ATRS ? "DMA_ATRS " :"", 1740 stat & OHCI_INT_DMA_ATRQ ? "DMA_ATRQ " :"", 1741 stat, OREAD(sc, FWOHCI_INTMASK) 1742 ); 1743 #endif 1744 /* Bus reset */ 1745 if(stat & OHCI_INT_PHY_BUS_R ){ 1746 if (fc->status == FWBUSRESET) 1747 goto busresetout; 1748 /* Disable bus reset interrupt until sid recv. */ 1749 OWRITE(sc, FWOHCI_INTMASKCLR, OHCI_INT_PHY_BUS_R); 1750 1751 device_printf(fc->dev, "BUS reset\n"); 1752 OWRITE(sc, FWOHCI_INTMASKCLR, OHCI_INT_CYC_LOST); 1753 OWRITE(sc, OHCI_LNKCTLCLR, OHCI_CNTL_CYCSRC); 1754 1755 OWRITE(sc, OHCI_ATQCTLCLR, OHCI_CNTL_DMA_RUN); 1756 sc->atrq.xferq.flag &= ~FWXFERQ_RUNNING; 1757 OWRITE(sc, OHCI_ATSCTLCLR, OHCI_CNTL_DMA_RUN); 1758 sc->atrs.xferq.flag &= ~FWXFERQ_RUNNING; 1759 1760 #ifndef ACK_ALL 1761 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_PHY_BUS_R); 1762 #endif 1763 fw_busreset(fc); 1764 } 1765 busresetout: 1766 if((stat & OHCI_INT_DMA_IR )){ 1767 #ifndef ACK_ALL 1768 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_IR); 1769 #endif 1770 #if __FreeBSD_version >= 500000 1771 irstat = atomic_readandclear_int(&sc->irstat); 1772 #else 1773 irstat = sc->irstat; 1774 sc->irstat = 0; 1775 #endif 1776 for(i = 0; i < fc->nisodma ; i++){ 1777 struct fwohci_dbch *dbch; 1778 1779 if((irstat & (1 << i)) != 0){ 1780 dbch = &sc->ir[i]; 1781 if ((dbch->xferq.flag & FWXFERQ_OPEN) == 0) { 1782 device_printf(sc->fc.dev, 1783 "dma(%d) not active\n", i); 1784 continue; 1785 } 1786 fwohci_rbuf_update(sc, i); 1787 } 1788 } 1789 } 1790 if((stat & OHCI_INT_DMA_IT )){ 1791 #ifndef ACK_ALL 1792 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_IT); 1793 #endif 1794 #if __FreeBSD_version >= 500000 1795 itstat = atomic_readandclear_int(&sc->itstat); 1796 #else 1797 itstat = sc->itstat; 1798 sc->itstat = 0; 1799 #endif 1800 for(i = 0; i < fc->nisodma ; i++){ 1801 if((itstat & (1 << i)) != 0){ 1802 fwohci_tbuf_update(sc, i); 1803 } 1804 } 1805 } 1806 if((stat & OHCI_INT_DMA_PRRS )){ 1807 #ifndef ACK_ALL 1808 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_PRRS); 1809 #endif 1810 #if 0 1811 dump_dma(sc, ARRS_CH); 1812 dump_db(sc, ARRS_CH); 1813 #endif 1814 fwohci_arcv(sc, &sc->arrs, count); 1815 } 1816 if((stat & OHCI_INT_DMA_PRRQ )){ 1817 #ifndef ACK_ALL 1818 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_PRRQ); 1819 #endif 1820 #if 0 1821 dump_dma(sc, ARRQ_CH); 1822 dump_db(sc, ARRQ_CH); 1823 #endif 1824 fwohci_arcv(sc, &sc->arrq, count); 1825 } 1826 if(stat & OHCI_INT_PHY_SID){ 1827 u_int32_t *buf, node_id; 1828 int plen; 1829 1830 #ifndef ACK_ALL 1831 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_PHY_SID); 1832 #endif 1833 /* Enable bus reset interrupt */ 1834 OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_PHY_BUS_R); 1835 /* Allow async. request to us */ 1836 OWRITE(sc, OHCI_AREQHI, 1 << 31); 1837 /* XXX insecure ?? */ 1838 OWRITE(sc, OHCI_PREQHI, 0x7fffffff); 1839 OWRITE(sc, OHCI_PREQLO, 0xffffffff); 1840 OWRITE(sc, OHCI_PREQUPPER, 0x10000); 1841 /* Set ATRetries register */ 1842 OWRITE(sc, OHCI_ATRETRY, 1<<(13+16) | 0xfff); 1843 /* 1844 ** Checking whether the node is root or not. If root, turn on 1845 ** cycle master. 1846 */ 1847 node_id = OREAD(sc, FWOHCI_NODEID); 1848 plen = OREAD(sc, OHCI_SID_CNT); 1849 1850 device_printf(fc->dev, "node_id=0x%08x, gen=%d, ", 1851 node_id, (plen >> 16) & 0xff); 1852 if (!(node_id & OHCI_NODE_VALID)) { 1853 printf("Bus reset failure\n"); 1854 goto sidout; 1855 } 1856 if (node_id & OHCI_NODE_ROOT) { 1857 printf("CYCLEMASTER mode\n"); 1858 OWRITE(sc, OHCI_LNKCTL, 1859 OHCI_CNTL_CYCMTR | OHCI_CNTL_CYCTIMER); 1860 } else { 1861 printf("non CYCLEMASTER mode\n"); 1862 OWRITE(sc, OHCI_LNKCTLCLR, OHCI_CNTL_CYCMTR); 1863 OWRITE(sc, OHCI_LNKCTL, OHCI_CNTL_CYCTIMER); 1864 } 1865 fc->nodeid = node_id & 0x3f; 1866 1867 if (plen & OHCI_SID_ERR) { 1868 device_printf(fc->dev, "SID Error\n"); 1869 goto sidout; 1870 } 1871 plen &= OHCI_SID_CNT_MASK; 1872 if (plen < 4 || plen > OHCI_SIDSIZE) { 1873 device_printf(fc->dev, "invalid SID len = %d\n", plen); 1874 goto sidout; 1875 } 1876 plen -= 4; /* chop control info */ 1877 buf = (u_int32_t *)malloc(OHCI_SIDSIZE, M_FW, M_NOWAIT); 1878 if (buf == NULL) { 1879 device_printf(fc->dev, "malloc failed\n"); 1880 goto sidout; 1881 } 1882 for (i = 0; i < plen / 4; i ++) 1883 buf[i] = FWOHCI_DMA_READ(sc->sid_buf[i+1]); 1884 #if 1 1885 /* pending all pre-bus_reset packets */ 1886 fwohci_txd(sc, &sc->atrq); 1887 fwohci_txd(sc, &sc->atrs); 1888 fwohci_arcv(sc, &sc->arrs, -1); 1889 fwohci_arcv(sc, &sc->arrq, -1); 1890 fw_drain_txq(fc); 1891 #endif 1892 fw_sidrcv(fc, buf, plen); 1893 free(buf, M_FW); 1894 } 1895 sidout: 1896 if((stat & OHCI_INT_DMA_ATRQ )){ 1897 #ifndef ACK_ALL 1898 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_ATRQ); 1899 #endif 1900 fwohci_txd(sc, &(sc->atrq)); 1901 } 1902 if((stat & OHCI_INT_DMA_ATRS )){ 1903 #ifndef ACK_ALL 1904 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_ATRS); 1905 #endif 1906 fwohci_txd(sc, &(sc->atrs)); 1907 } 1908 if((stat & OHCI_INT_PW_ERR )){ 1909 #ifndef ACK_ALL 1910 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_PW_ERR); 1911 #endif 1912 device_printf(fc->dev, "posted write error\n"); 1913 } 1914 if((stat & OHCI_INT_ERR )){ 1915 #ifndef ACK_ALL 1916 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_ERR); 1917 #endif 1918 device_printf(fc->dev, "unrecoverable error\n"); 1919 } 1920 if((stat & OHCI_INT_PHY_INT)) { 1921 #ifndef ACK_ALL 1922 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_PHY_INT); 1923 #endif 1924 device_printf(fc->dev, "phy int\n"); 1925 } 1926 1927 return; 1928 } 1929 1930 #if FWOHCI_TASKQUEUE 1931 static void 1932 fwohci_complete(void *arg, int pending) 1933 { 1934 struct fwohci_softc *sc = (struct fwohci_softc *)arg; 1935 u_int32_t stat; 1936 1937 again: 1938 stat = atomic_readandclear_int(&sc->intstat); 1939 if (stat) 1940 fwohci_intr_body(sc, stat, -1); 1941 else 1942 return; 1943 goto again; 1944 } 1945 #endif 1946 1947 static u_int32_t 1948 fwochi_check_stat(struct fwohci_softc *sc) 1949 { 1950 u_int32_t stat, irstat, itstat; 1951 1952 stat = OREAD(sc, FWOHCI_INTSTAT); 1953 if (stat == 0xffffffff) { 1954 device_printf(sc->fc.dev, 1955 "device physically ejected?\n"); 1956 return(stat); 1957 } 1958 #ifdef ACK_ALL 1959 if (stat) 1960 OWRITE(sc, FWOHCI_INTSTATCLR, stat); 1961 #endif 1962 if (stat & OHCI_INT_DMA_IR) { 1963 irstat = OREAD(sc, OHCI_IR_STAT); 1964 OWRITE(sc, OHCI_IR_STATCLR, irstat); 1965 atomic_set_int(&sc->irstat, irstat); 1966 } 1967 if (stat & OHCI_INT_DMA_IT) { 1968 itstat = OREAD(sc, OHCI_IT_STAT); 1969 OWRITE(sc, OHCI_IT_STATCLR, itstat); 1970 atomic_set_int(&sc->itstat, itstat); 1971 } 1972 return(stat); 1973 } 1974 1975 void 1976 fwohci_intr(void *arg) 1977 { 1978 struct fwohci_softc *sc = (struct fwohci_softc *)arg; 1979 u_int32_t stat; 1980 #if !FWOHCI_TASKQUEUE 1981 u_int32_t bus_reset = 0; 1982 #endif 1983 1984 if (!(sc->intmask & OHCI_INT_EN)) { 1985 /* polling mode */ 1986 return; 1987 } 1988 1989 #if !FWOHCI_TASKQUEUE 1990 again: 1991 #endif 1992 stat = fwochi_check_stat(sc); 1993 if (stat == 0 || stat == 0xffffffff) 1994 return; 1995 #if FWOHCI_TASKQUEUE 1996 atomic_set_int(&sc->intstat, stat); 1997 /* XXX mask bus reset intr. during bus reset phase */ 1998 if (stat) 1999 taskqueue_enqueue(taskqueue_swi_giant, &sc->fwohci_task_complete); 2000 #else 2001 /* We cannot clear bus reset event during bus reset phase */ 2002 if ((stat & ~bus_reset) == 0) 2003 return; 2004 bus_reset = stat & OHCI_INT_PHY_BUS_R; 2005 fwohci_intr_body(sc, stat, -1); 2006 goto again; 2007 #endif 2008 } 2009 2010 static void 2011 fwohci_poll(struct firewire_comm *fc, int quick, int count) 2012 { 2013 int s; 2014 u_int32_t stat; 2015 struct fwohci_softc *sc; 2016 2017 2018 sc = (struct fwohci_softc *)fc; 2019 stat = OHCI_INT_DMA_IR | OHCI_INT_DMA_IT | 2020 OHCI_INT_DMA_PRRS | OHCI_INT_DMA_PRRQ | 2021 OHCI_INT_DMA_ATRQ | OHCI_INT_DMA_ATRS; 2022 #if 0 2023 if (!quick) { 2024 #else 2025 if (1) { 2026 #endif 2027 stat = fwochi_check_stat(sc); 2028 if (stat == 0 || stat == 0xffffffff) 2029 return; 2030 } 2031 s = splfw(); 2032 fwohci_intr_body(sc, stat, count); 2033 splx(s); 2034 } 2035 2036 static void 2037 fwohci_set_intr(struct firewire_comm *fc, int enable) 2038 { 2039 struct fwohci_softc *sc; 2040 2041 sc = (struct fwohci_softc *)fc; 2042 if (bootverbose) 2043 device_printf(sc->fc.dev, "fwohci_set_intr: %d\n", enable); 2044 if (enable) { 2045 sc->intmask |= OHCI_INT_EN; 2046 OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_EN); 2047 } else { 2048 sc->intmask &= ~OHCI_INT_EN; 2049 OWRITE(sc, FWOHCI_INTMASKCLR, OHCI_INT_EN); 2050 } 2051 } 2052 2053 static void 2054 fwohci_tbuf_update(struct fwohci_softc *sc, int dmach) 2055 { 2056 struct firewire_comm *fc = &sc->fc; 2057 volatile struct fwohcidb *db; 2058 struct fw_bulkxfer *chunk; 2059 struct fw_xferq *it; 2060 u_int32_t stat, count; 2061 int s, w=0, ldesc; 2062 2063 it = fc->it[dmach]; 2064 ldesc = sc->it[dmach].ndesc - 1; 2065 s = splfw(); /* unnecessary ? */ 2066 fwdma_sync_multiseg_all(sc->it[dmach].am, BUS_DMASYNC_POSTREAD); 2067 while ((chunk = STAILQ_FIRST(&it->stdma)) != NULL) { 2068 db = ((struct fwohcidb_tr *)(chunk->end))->db; 2069 stat = FWOHCI_DMA_READ(db[ldesc].db.desc.res) 2070 >> OHCI_STATUS_SHIFT; 2071 db = ((struct fwohcidb_tr *)(chunk->start))->db; 2072 count = FWOHCI_DMA_READ(db[ldesc].db.desc.res) 2073 & OHCI_COUNT_MASK; 2074 if (stat == 0) 2075 break; 2076 STAILQ_REMOVE_HEAD(&it->stdma, link); 2077 switch (stat & FWOHCIEV_MASK){ 2078 case FWOHCIEV_ACKCOMPL: 2079 #if 0 2080 device_printf(fc->dev, "0x%08x\n", count); 2081 #endif 2082 break; 2083 default: 2084 device_printf(fc->dev, 2085 "Isochronous transmit err %02x(%s)\n", 2086 stat, fwohcicode[stat & 0x1f]); 2087 } 2088 STAILQ_INSERT_TAIL(&it->stfree, chunk, link); 2089 w++; 2090 } 2091 splx(s); 2092 if (w) 2093 wakeup(it); 2094 } 2095 2096 static void 2097 fwohci_rbuf_update(struct fwohci_softc *sc, int dmach) 2098 { 2099 struct firewire_comm *fc = &sc->fc; 2100 volatile struct fwohcidb_tr *db_tr; 2101 struct fw_bulkxfer *chunk; 2102 struct fw_xferq *ir; 2103 u_int32_t stat; 2104 int s, w=0, ldesc; 2105 2106 ir = fc->ir[dmach]; 2107 ldesc = sc->ir[dmach].ndesc - 1; 2108 #if 0 2109 dump_db(sc, dmach); 2110 #endif 2111 s = splfw(); 2112 fwdma_sync_multiseg_all(sc->ir[dmach].am, BUS_DMASYNC_POSTREAD); 2113 while ((chunk = STAILQ_FIRST(&ir->stdma)) != NULL) { 2114 db_tr = (struct fwohcidb_tr *)chunk->end; 2115 stat = FWOHCI_DMA_READ(db_tr->db[ldesc].db.desc.res) 2116 >> OHCI_STATUS_SHIFT; 2117 if (stat == 0) 2118 break; 2119 2120 if (chunk->mbuf != NULL) { 2121 bus_dmamap_sync(sc->ir[dmach].dmat, db_tr->dma_map, 2122 BUS_DMASYNC_POSTREAD); 2123 bus_dmamap_unload(sc->ir[dmach].dmat, db_tr->dma_map); 2124 } else if (ir->buf != NULL) { 2125 fwdma_sync_multiseg(ir->buf, chunk->poffset, 2126 ir->bnpacket, BUS_DMASYNC_POSTREAD); 2127 } else { 2128 /* XXX */ 2129 printf("fwohci_rbuf_update: this shouldn't happend\n"); 2130 } 2131 2132 STAILQ_REMOVE_HEAD(&ir->stdma, link); 2133 STAILQ_INSERT_TAIL(&ir->stvalid, chunk, link); 2134 switch (stat & FWOHCIEV_MASK) { 2135 case FWOHCIEV_ACKCOMPL: 2136 chunk->resp = 0; 2137 break; 2138 default: 2139 chunk->resp = EINVAL; 2140 device_printf(fc->dev, 2141 "Isochronous receive err %02x(%s)\n", 2142 stat, fwohcicode[stat & 0x1f]); 2143 } 2144 w++; 2145 } 2146 splx(s); 2147 if (w) { 2148 if (ir->flag & FWXFERQ_HANDLER) 2149 ir->hand(ir); 2150 else 2151 wakeup(ir); 2152 } 2153 } 2154 2155 void 2156 dump_dma(struct fwohci_softc *sc, u_int32_t ch) 2157 { 2158 u_int32_t off, cntl, stat, cmd, match; 2159 2160 if(ch == 0){ 2161 off = OHCI_ATQOFF; 2162 }else if(ch == 1){ 2163 off = OHCI_ATSOFF; 2164 }else if(ch == 2){ 2165 off = OHCI_ARQOFF; 2166 }else if(ch == 3){ 2167 off = OHCI_ARSOFF; 2168 }else if(ch < IRX_CH){ 2169 off = OHCI_ITCTL(ch - ITX_CH); 2170 }else{ 2171 off = OHCI_IRCTL(ch - IRX_CH); 2172 } 2173 cntl = stat = OREAD(sc, off); 2174 cmd = OREAD(sc, off + 0xc); 2175 match = OREAD(sc, off + 0x10); 2176 2177 device_printf(sc->fc.dev, "ch %1x cntl:0x%08x cmd:0x%08x match:0x%08x\n", 2178 ch, 2179 cntl, 2180 cmd, 2181 match); 2182 stat &= 0xffff ; 2183 if (stat) { 2184 device_printf(sc->fc.dev, "dma %d ch:%s%s%s%s%s%s %s(%x)\n", 2185 ch, 2186 stat & OHCI_CNTL_DMA_RUN ? "RUN," : "", 2187 stat & OHCI_CNTL_DMA_WAKE ? "WAKE," : "", 2188 stat & OHCI_CNTL_DMA_DEAD ? "DEAD," : "", 2189 stat & OHCI_CNTL_DMA_ACTIVE ? "ACTIVE," : "", 2190 stat & OHCI_CNTL_DMA_BT ? "BRANCH," : "", 2191 stat & OHCI_CNTL_DMA_BAD ? "BADDMA," : "", 2192 fwohcicode[stat & 0x1f], 2193 stat & 0x1f 2194 ); 2195 }else{ 2196 device_printf(sc->fc.dev, "dma %d ch: Nostat\n", ch); 2197 } 2198 } 2199 2200 void 2201 dump_db(struct fwohci_softc *sc, u_int32_t ch) 2202 { 2203 struct fwohci_dbch *dbch; 2204 struct fwohcidb_tr *cp = NULL, *pp, *np = NULL; 2205 volatile struct fwohcidb *curr = NULL, *prev, *next = NULL; 2206 int idb, jdb; 2207 u_int32_t cmd, off; 2208 if(ch == 0){ 2209 off = OHCI_ATQOFF; 2210 dbch = &sc->atrq; 2211 }else if(ch == 1){ 2212 off = OHCI_ATSOFF; 2213 dbch = &sc->atrs; 2214 }else if(ch == 2){ 2215 off = OHCI_ARQOFF; 2216 dbch = &sc->arrq; 2217 }else if(ch == 3){ 2218 off = OHCI_ARSOFF; 2219 dbch = &sc->arrs; 2220 }else if(ch < IRX_CH){ 2221 off = OHCI_ITCTL(ch - ITX_CH); 2222 dbch = &sc->it[ch - ITX_CH]; 2223 }else { 2224 off = OHCI_IRCTL(ch - IRX_CH); 2225 dbch = &sc->ir[ch - IRX_CH]; 2226 } 2227 cmd = OREAD(sc, off + 0xc); 2228 2229 if( dbch->ndb == 0 ){ 2230 device_printf(sc->fc.dev, "No DB is attached ch=%d\n", ch); 2231 return; 2232 } 2233 pp = dbch->top; 2234 prev = pp->db; 2235 for(idb = 0 ; idb < dbch->ndb ; idb ++ ){ 2236 if(pp == NULL){ 2237 curr = NULL; 2238 goto outdb; 2239 } 2240 cp = STAILQ_NEXT(pp, link); 2241 if(cp == NULL){ 2242 curr = NULL; 2243 goto outdb; 2244 } 2245 np = STAILQ_NEXT(cp, link); 2246 for(jdb = 0 ; jdb < dbch->ndesc ; jdb ++ ){ 2247 if ((cmd & 0xfffffff0) == cp->bus_addr) { 2248 curr = cp->db; 2249 if(np != NULL){ 2250 next = np->db; 2251 }else{ 2252 next = NULL; 2253 } 2254 goto outdb; 2255 } 2256 } 2257 pp = STAILQ_NEXT(pp, link); 2258 prev = pp->db; 2259 } 2260 outdb: 2261 if( curr != NULL){ 2262 #if 0 2263 printf("Prev DB %d\n", ch); 2264 print_db(pp, prev, ch, dbch->ndesc); 2265 #endif 2266 printf("Current DB %d\n", ch); 2267 print_db(cp, curr, ch, dbch->ndesc); 2268 #if 0 2269 printf("Next DB %d\n", ch); 2270 print_db(np, next, ch, dbch->ndesc); 2271 #endif 2272 }else{ 2273 printf("dbdump err ch = %d cmd = 0x%08x\n", ch, cmd); 2274 } 2275 return; 2276 } 2277 2278 void 2279 print_db(struct fwohcidb_tr *db_tr, volatile struct fwohcidb *db, 2280 u_int32_t ch, u_int32_t max) 2281 { 2282 fwohcireg_t stat; 2283 int i, key; 2284 u_int32_t cmd, res; 2285 2286 if(db == NULL){ 2287 printf("No Descriptor is found\n"); 2288 return; 2289 } 2290 2291 printf("ch = %d\n%8s %s %s %s %s %4s %8s %8s %4s:%4s\n", 2292 ch, 2293 "Current", 2294 "OP ", 2295 "KEY", 2296 "INT", 2297 "BR ", 2298 "len", 2299 "Addr", 2300 "Depend", 2301 "Stat", 2302 "Cnt"); 2303 for( i = 0 ; i <= max ; i ++){ 2304 cmd = FWOHCI_DMA_READ(db[i].db.desc.cmd); 2305 res = FWOHCI_DMA_READ(db[i].db.desc.res); 2306 key = cmd & OHCI_KEY_MASK; 2307 stat = res >> OHCI_STATUS_SHIFT; 2308 #if __FreeBSD_version >= 500000 2309 printf("%08jx %s %s %s %s %5d %08x %08x %04x:%04x", 2310 (uintmax_t)db_tr->bus_addr, 2311 #else 2312 printf("%08x %s %s %s %s %5d %08x %08x %04x:%04x", 2313 db_tr->bus_addr, 2314 #endif 2315 dbcode[(cmd >> 28) & 0xf], 2316 dbkey[(cmd >> 24) & 0x7], 2317 dbcond[(cmd >> 20) & 0x3], 2318 dbcond[(cmd >> 18) & 0x3], 2319 cmd & OHCI_COUNT_MASK, 2320 FWOHCI_DMA_READ(db[i].db.desc.addr), 2321 FWOHCI_DMA_READ(db[i].db.desc.depend), 2322 stat, 2323 res & OHCI_COUNT_MASK); 2324 if(stat & 0xff00){ 2325 printf(" %s%s%s%s%s%s %s(%x)\n", 2326 stat & OHCI_CNTL_DMA_RUN ? "RUN," : "", 2327 stat & OHCI_CNTL_DMA_WAKE ? "WAKE," : "", 2328 stat & OHCI_CNTL_DMA_DEAD ? "DEAD," : "", 2329 stat & OHCI_CNTL_DMA_ACTIVE ? "ACTIVE," : "", 2330 stat & OHCI_CNTL_DMA_BT ? "BRANCH," : "", 2331 stat & OHCI_CNTL_DMA_BAD ? "BADDMA," : "", 2332 fwohcicode[stat & 0x1f], 2333 stat & 0x1f 2334 ); 2335 }else{ 2336 printf(" Nostat\n"); 2337 } 2338 if(key == OHCI_KEY_ST2 ){ 2339 printf("0x%08x 0x%08x 0x%08x 0x%08x\n", 2340 FWOHCI_DMA_READ(db[i+1].db.immed[0]), 2341 FWOHCI_DMA_READ(db[i+1].db.immed[1]), 2342 FWOHCI_DMA_READ(db[i+1].db.immed[2]), 2343 FWOHCI_DMA_READ(db[i+1].db.immed[3])); 2344 } 2345 if(key == OHCI_KEY_DEVICE){ 2346 return; 2347 } 2348 if((cmd & OHCI_BRANCH_MASK) 2349 == OHCI_BRANCH_ALWAYS){ 2350 return; 2351 } 2352 if((cmd & OHCI_CMD_MASK) 2353 == OHCI_OUTPUT_LAST){ 2354 return; 2355 } 2356 if((cmd & OHCI_CMD_MASK) 2357 == OHCI_INPUT_LAST){ 2358 return; 2359 } 2360 if(key == OHCI_KEY_ST2 ){ 2361 i++; 2362 } 2363 } 2364 return; 2365 } 2366 2367 void 2368 fwohci_ibr(struct firewire_comm *fc) 2369 { 2370 struct fwohci_softc *sc; 2371 u_int32_t fun; 2372 2373 device_printf(fc->dev, "Initiate bus reset\n"); 2374 sc = (struct fwohci_softc *)fc; 2375 2376 /* 2377 * Set root hold-off bit so that non cyclemaster capable node 2378 * shouldn't became the root node. 2379 */ 2380 #if 1 2381 fun = fwphy_rddata(sc, FW_PHY_IBR_REG); 2382 fun |= FW_PHY_IBR | FW_PHY_RHB; 2383 fun = fwphy_wrdata(sc, FW_PHY_IBR_REG, fun); 2384 #else /* Short bus reset */ 2385 fun = fwphy_rddata(sc, FW_PHY_ISBR_REG); 2386 fun |= FW_PHY_ISBR | FW_PHY_RHB; 2387 fun = fwphy_wrdata(sc, FW_PHY_ISBR_REG, fun); 2388 #endif 2389 } 2390 2391 void 2392 fwohci_txbufdb(struct fwohci_softc *sc, int dmach, struct fw_bulkxfer *bulkxfer) 2393 { 2394 struct fwohcidb_tr *db_tr, *fdb_tr; 2395 struct fwohci_dbch *dbch; 2396 volatile struct fwohcidb *db; 2397 struct fw_pkt *fp; 2398 volatile struct fwohci_txpkthdr *ohcifp; 2399 unsigned short chtag; 2400 int idb; 2401 2402 dbch = &sc->it[dmach]; 2403 chtag = sc->it[dmach].xferq.flag & 0xff; 2404 2405 db_tr = (struct fwohcidb_tr *)(bulkxfer->start); 2406 fdb_tr = (struct fwohcidb_tr *)(bulkxfer->end); 2407 /* 2408 device_printf(sc->fc.dev, "DB %08x %08x %08x\n", bulkxfer, db_tr->bus_addr, fdb_tr->bus_addr); 2409 */ 2410 for (idb = 0; idb < dbch->xferq.bnpacket; idb ++) { 2411 db = db_tr->db; 2412 fp = (struct fw_pkt *)db_tr->buf; 2413 ohcifp = (volatile struct fwohci_txpkthdr *) db[1].db.immed; 2414 ohcifp->mode.ld[0] = fp->mode.ld[0]; 2415 ohcifp->mode.stream.len = fp->mode.stream.len; 2416 ohcifp->mode.stream.chtag = chtag; 2417 ohcifp->mode.stream.tcode = 0xa; 2418 ohcifp->mode.stream.spd = 0; 2419 #if BYTE_ORDER == BIG_ENDIAN 2420 FWOHCI_DMA_WRITE(db[1].db.immed[0], db[1].db.immed[0]); 2421 FWOHCI_DMA_WRITE(db[1].db.immed[1], db[1].db.immed[1]); 2422 #endif 2423 2424 FWOHCI_DMA_CLEAR(db[2].db.desc.cmd, OHCI_COUNT_MASK); 2425 FWOHCI_DMA_SET(db[2].db.desc.cmd, fp->mode.stream.len); 2426 FWOHCI_DMA_WRITE(db[2].db.desc.res, 0); 2427 #if 0 /* if bulkxfer->npackets changes */ 2428 db[2].db.desc.cmd = OHCI_OUTPUT_LAST 2429 | OHCI_UPDATE 2430 | OHCI_BRANCH_ALWAYS; 2431 db[0].db.desc.depend = 2432 = db[dbch->ndesc - 1].db.desc.depend 2433 = STAILQ_NEXT(db_tr, link)->bus_addr | dbch->ndesc; 2434 #else 2435 FWOHCI_DMA_SET(db[0].db.desc.depend, dbch->ndesc); 2436 FWOHCI_DMA_SET(db[dbch->ndesc - 1].db.desc.depend, dbch->ndesc); 2437 #endif 2438 bulkxfer->end = (caddr_t)db_tr; 2439 db_tr = STAILQ_NEXT(db_tr, link); 2440 } 2441 db = ((struct fwohcidb_tr *)bulkxfer->end)->db; 2442 FWOHCI_DMA_CLEAR(db[0].db.desc.depend, 0xf); 2443 FWOHCI_DMA_CLEAR(db[dbch->ndesc - 1].db.desc.depend, 0xf); 2444 #if 0 /* if bulkxfer->npackets changes */ 2445 db[dbch->ndesc - 1].db.desc.control |= OHCI_INTERRUPT_ALWAYS; 2446 /* OHCI 1.1 and above */ 2447 db[0].db.desc.control |= OHCI_INTERRUPT_ALWAYS; 2448 #endif 2449 /* 2450 db_tr = (struct fwohcidb_tr *)bulkxfer->start; 2451 fdb_tr = (struct fwohcidb_tr *)bulkxfer->end; 2452 device_printf(sc->fc.dev, "DB %08x %3d %08x %08x\n", bulkxfer, bulkxfer->npacket, db_tr->bus_addr, fdb_tr->bus_addr); 2453 */ 2454 return; 2455 } 2456 2457 static int 2458 fwohci_add_tx_buf(struct fwohci_dbch *dbch, struct fwohcidb_tr *db_tr, 2459 int poffset) 2460 { 2461 volatile struct fwohcidb *db = db_tr->db; 2462 struct fw_xferq *it; 2463 int err = 0; 2464 2465 it = &dbch->xferq; 2466 if(it->buf == 0){ 2467 err = EINVAL; 2468 return err; 2469 } 2470 db_tr->buf = fwdma_v_addr(it->buf, poffset); 2471 db_tr->dbcnt = 3; 2472 2473 FWOHCI_DMA_WRITE(db[0].db.desc.cmd, 2474 OHCI_OUTPUT_MORE | OHCI_KEY_ST2 | 8); 2475 FWOHCI_DMA_WRITE(db[2].db.desc.addr, 2476 fwdma_bus_addr(it->buf, poffset) + sizeof(u_int32_t)); 2477 2478 FWOHCI_DMA_WRITE(db[2].db.desc.cmd, 2479 OHCI_OUTPUT_LAST | OHCI_UPDATE | OHCI_BRANCH_ALWAYS); 2480 #if 1 2481 FWOHCI_DMA_WRITE(db[0].db.desc.res, 0); 2482 FWOHCI_DMA_WRITE(db[2].db.desc.res, 0); 2483 #endif 2484 return 0; 2485 } 2486 2487 int 2488 fwohci_add_rx_buf(struct fwohci_dbch *dbch, struct fwohcidb_tr *db_tr, 2489 int poffset, struct fwdma_alloc *dummy_dma) 2490 { 2491 volatile struct fwohcidb *db = db_tr->db; 2492 struct fw_xferq *ir; 2493 int i, ldesc; 2494 bus_addr_t dbuf[2]; 2495 int dsiz[2]; 2496 2497 ir = &dbch->xferq; 2498 if (ir->buf == NULL && (dbch->xferq.flag & FWXFERQ_EXTBUF) == 0) { 2499 db_tr->buf = fwdma_malloc_size(dbch->dmat, &db_tr->dma_map, 2500 ir->psize, &dbuf[0], BUS_DMA_NOWAIT); 2501 if (db_tr->buf == NULL) 2502 return(ENOMEM); 2503 db_tr->dbcnt = 1; 2504 dsiz[0] = ir->psize; 2505 bus_dmamap_sync(dbch->dmat, db_tr->dma_map, 2506 BUS_DMASYNC_PREREAD); 2507 } else { 2508 db_tr->dbcnt = 0; 2509 if (dummy_dma != NULL) { 2510 dsiz[db_tr->dbcnt] = sizeof(u_int32_t); 2511 dbuf[db_tr->dbcnt++] = dummy_dma->bus_addr; 2512 } 2513 dsiz[db_tr->dbcnt] = ir->psize; 2514 if (ir->buf != NULL) { 2515 db_tr->buf = fwdma_v_addr(ir->buf, poffset); 2516 dbuf[db_tr->dbcnt] = fwdma_bus_addr( ir->buf, poffset); 2517 } 2518 db_tr->dbcnt++; 2519 } 2520 for(i = 0 ; i < db_tr->dbcnt ; i++){ 2521 FWOHCI_DMA_WRITE(db[i].db.desc.addr, dbuf[i]); 2522 FWOHCI_DMA_WRITE(db[i].db.desc.cmd, OHCI_INPUT_MORE | dsiz[i]); 2523 if (ir->flag & FWXFERQ_STREAM) { 2524 FWOHCI_DMA_SET(db[i].db.desc.cmd, OHCI_UPDATE); 2525 } 2526 FWOHCI_DMA_WRITE(db[i].db.desc.res, dsiz[i]); 2527 } 2528 ldesc = db_tr->dbcnt - 1; 2529 if (ir->flag & FWXFERQ_STREAM) { 2530 FWOHCI_DMA_SET(db[ldesc].db.desc.cmd, OHCI_INPUT_LAST); 2531 } 2532 FWOHCI_DMA_SET(db[ldesc].db.desc.cmd, OHCI_BRANCH_ALWAYS); 2533 return 0; 2534 } 2535 2536 2537 static int 2538 fwohci_arcv_swap(struct fw_pkt *fp, int len) 2539 { 2540 struct fw_pkt *fp0; 2541 u_int32_t ld0; 2542 int slen; 2543 #if BYTE_ORDER == BIG_ENDIAN 2544 int i; 2545 #endif 2546 2547 ld0 = FWOHCI_DMA_READ(fp->mode.ld[0]); 2548 #if 0 2549 printf("ld0: x%08x\n", ld0); 2550 #endif 2551 fp0 = (struct fw_pkt *)&ld0; 2552 switch (fp0->mode.common.tcode) { 2553 case FWTCODE_RREQQ: 2554 case FWTCODE_WRES: 2555 case FWTCODE_WREQQ: 2556 case FWTCODE_RRESQ: 2557 case FWOHCITCODE_PHY: 2558 slen = 12; 2559 break; 2560 case FWTCODE_RREQB: 2561 case FWTCODE_WREQB: 2562 case FWTCODE_LREQ: 2563 case FWTCODE_RRESB: 2564 case FWTCODE_LRES: 2565 slen = 16; 2566 break; 2567 default: 2568 printf("Unknown tcode %d\n", fp0->mode.common.tcode); 2569 return(0); 2570 } 2571 if (slen > len) { 2572 if (firewire_debug) 2573 printf("splitted header\n"); 2574 return(-slen); 2575 } 2576 #if BYTE_ORDER == BIG_ENDIAN 2577 for(i = 0; i < slen/4; i ++) 2578 fp->mode.ld[i] = FWOHCI_DMA_READ(fp->mode.ld[i]); 2579 #endif 2580 return(slen); 2581 } 2582 2583 #define PLEN(x) roundup2(x, sizeof(u_int32_t)) 2584 static int 2585 fwohci_get_plen(struct fwohci_softc *sc, struct fwohci_dbch *dbch, struct fw_pkt *fp) 2586 { 2587 int r; 2588 2589 switch(fp->mode.common.tcode){ 2590 case FWTCODE_RREQQ: 2591 r = sizeof(fp->mode.rreqq) + sizeof(u_int32_t); 2592 break; 2593 case FWTCODE_WRES: 2594 r = sizeof(fp->mode.wres) + sizeof(u_int32_t); 2595 break; 2596 case FWTCODE_WREQQ: 2597 r = sizeof(fp->mode.wreqq) + sizeof(u_int32_t); 2598 break; 2599 case FWTCODE_RREQB: 2600 r = sizeof(fp->mode.rreqb) + sizeof(u_int32_t); 2601 break; 2602 case FWTCODE_RRESQ: 2603 r = sizeof(fp->mode.rresq) + sizeof(u_int32_t); 2604 break; 2605 case FWTCODE_WREQB: 2606 r = sizeof(struct fw_asyhdr) + PLEN(fp->mode.wreqb.len) 2607 + sizeof(u_int32_t); 2608 break; 2609 case FWTCODE_LREQ: 2610 r = sizeof(struct fw_asyhdr) + PLEN(fp->mode.lreq.len) 2611 + sizeof(u_int32_t); 2612 break; 2613 case FWTCODE_RRESB: 2614 r = sizeof(struct fw_asyhdr) + PLEN(fp->mode.rresb.len) 2615 + sizeof(u_int32_t); 2616 break; 2617 case FWTCODE_LRES: 2618 r = sizeof(struct fw_asyhdr) + PLEN(fp->mode.lres.len) 2619 + sizeof(u_int32_t); 2620 break; 2621 case FWOHCITCODE_PHY: 2622 r = 16; 2623 break; 2624 default: 2625 device_printf(sc->fc.dev, "Unknown tcode %d\n", 2626 fp->mode.common.tcode); 2627 r = 0; 2628 } 2629 if (r > dbch->xferq.psize) { 2630 device_printf(sc->fc.dev, "Invalid packet length %d\n", r); 2631 /* panic ? */ 2632 } 2633 return r; 2634 } 2635 2636 static void 2637 fwohci_arcv_free_buf(struct fwohci_dbch *dbch, struct fwohcidb_tr *db_tr) 2638 { 2639 volatile struct fwohcidb *db = &db_tr->db[0]; 2640 2641 FWOHCI_DMA_CLEAR(db->db.desc.depend, 0xf); 2642 FWOHCI_DMA_WRITE(db->db.desc.res, dbch->xferq.psize); 2643 FWOHCI_DMA_SET(dbch->bottom->db[0].db.desc.depend, 1); 2644 fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREWRITE); 2645 dbch->bottom = db_tr; 2646 } 2647 2648 static void 2649 fwohci_arcv(struct fwohci_softc *sc, struct fwohci_dbch *dbch, int count) 2650 { 2651 struct fwohcidb_tr *db_tr; 2652 struct iovec vec[2]; 2653 struct fw_pkt pktbuf; 2654 int nvec; 2655 struct fw_pkt *fp; 2656 u_int8_t *ld; 2657 u_int32_t stat, off, status; 2658 u_int spd; 2659 int len, plen, hlen, pcnt, offset; 2660 int s; 2661 caddr_t buf; 2662 int resCount; 2663 2664 if(&sc->arrq == dbch){ 2665 off = OHCI_ARQOFF; 2666 }else if(&sc->arrs == dbch){ 2667 off = OHCI_ARSOFF; 2668 }else{ 2669 return; 2670 } 2671 2672 s = splfw(); 2673 db_tr = dbch->top; 2674 pcnt = 0; 2675 /* XXX we cannot handle a packet which lies in more than two buf */ 2676 fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_POSTREAD); 2677 fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_POSTWRITE); 2678 status = FWOHCI_DMA_READ(db_tr->db[0].db.desc.res) >> OHCI_STATUS_SHIFT; 2679 resCount = FWOHCI_DMA_READ(db_tr->db[0].db.desc.res) & OHCI_COUNT_MASK; 2680 #if 0 2681 printf("status 0x%04x, resCount 0x%04x\n", status, resCount); 2682 #endif 2683 while (status & OHCI_CNTL_DMA_ACTIVE) { 2684 len = dbch->xferq.psize - resCount; 2685 ld = (u_int8_t *)db_tr->buf; 2686 if (dbch->pdb_tr == NULL) { 2687 len -= dbch->buf_offset; 2688 ld += dbch->buf_offset; 2689 } 2690 if (len > 0) 2691 bus_dmamap_sync(dbch->dmat, db_tr->dma_map, 2692 BUS_DMASYNC_POSTREAD); 2693 while (len > 0 ) { 2694 if (count >= 0 && count-- == 0) 2695 goto out; 2696 if(dbch->pdb_tr != NULL){ 2697 /* we have a fragment in previous buffer */ 2698 int rlen; 2699 2700 offset = dbch->buf_offset; 2701 if (offset < 0) 2702 offset = - offset; 2703 buf = dbch->pdb_tr->buf + offset; 2704 rlen = dbch->xferq.psize - offset; 2705 if (firewire_debug) 2706 printf("rlen=%d, offset=%d\n", 2707 rlen, dbch->buf_offset); 2708 if (dbch->buf_offset < 0) { 2709 /* splitted in header, pull up */ 2710 char *p; 2711 2712 p = (char *)&pktbuf; 2713 bcopy(buf, p, rlen); 2714 p += rlen; 2715 /* this must be too long but harmless */ 2716 rlen = sizeof(pktbuf) - rlen; 2717 if (rlen < 0) 2718 printf("why rlen < 0\n"); 2719 bcopy(db_tr->buf, p, rlen); 2720 ld += rlen; 2721 len -= rlen; 2722 hlen = fwohci_arcv_swap(&pktbuf, sizeof(pktbuf)); 2723 if (hlen < 0) { 2724 printf("hlen < 0 shouldn't happen"); 2725 } 2726 offset = sizeof(pktbuf); 2727 vec[0].iov_base = (char *)&pktbuf; 2728 vec[0].iov_len = offset; 2729 } else { 2730 /* splitted in payload */ 2731 offset = rlen; 2732 vec[0].iov_base = buf; 2733 vec[0].iov_len = rlen; 2734 } 2735 fp=(struct fw_pkt *)vec[0].iov_base; 2736 nvec = 1; 2737 } else { 2738 /* no fragment in previous buffer */ 2739 fp=(struct fw_pkt *)ld; 2740 hlen = fwohci_arcv_swap(fp, len); 2741 if (hlen == 0) 2742 /* XXX need reset */ 2743 goto out; 2744 if (hlen < 0) { 2745 dbch->pdb_tr = db_tr; 2746 dbch->buf_offset = - dbch->buf_offset; 2747 /* sanity check */ 2748 if (resCount != 0) 2749 printf("resCount != 0 !?\n"); 2750 goto out; 2751 } 2752 offset = 0; 2753 nvec = 0; 2754 } 2755 plen = fwohci_get_plen(sc, dbch, fp) - offset; 2756 if (plen < 0) { 2757 /* minimum header size + trailer 2758 = sizeof(fw_pkt) so this shouldn't happens */ 2759 printf("plen is negative! offset=%d\n", offset); 2760 goto out; 2761 } 2762 if (plen > 0) { 2763 len -= plen; 2764 if (len < 0) { 2765 dbch->pdb_tr = db_tr; 2766 if (firewire_debug) 2767 printf("splitted payload\n"); 2768 /* sanity check */ 2769 if (resCount != 0) 2770 printf("resCount != 0 !?\n"); 2771 goto out; 2772 } 2773 vec[nvec].iov_base = ld; 2774 vec[nvec].iov_len = plen; 2775 nvec ++; 2776 ld += plen; 2777 } 2778 dbch->buf_offset = ld - (u_int8_t *)db_tr->buf; 2779 if (nvec == 0) 2780 printf("nvec == 0\n"); 2781 2782 /* DMA result-code will be written at the tail of packet */ 2783 #if BYTE_ORDER == BIG_ENDIAN 2784 stat = FWOHCI_DMA_READ(((struct fwohci_trailer *)(ld - sizeof(struct fwohci_trailer)))->stat) >> 16; 2785 #else 2786 stat = ((struct fwohci_trailer *)(ld - sizeof(struct fwohci_trailer)))->stat; 2787 #endif 2788 #if 0 2789 printf("plen: %d, stat %x\n", plen ,stat); 2790 #endif 2791 spd = (stat >> 5) & 0x3; 2792 stat &= 0x1f; 2793 switch(stat){ 2794 case FWOHCIEV_ACKPEND: 2795 #if 0 2796 printf("fwohci_arcv: ack pending tcode=0x%x..\n", fp->mode.common.tcode); 2797 #endif 2798 /* fall through */ 2799 case FWOHCIEV_ACKCOMPL: 2800 if ((vec[nvec-1].iov_len -= 2801 sizeof(struct fwohci_trailer)) == 0) 2802 nvec--; 2803 fw_rcv(&sc->fc, vec, nvec, 0, spd); 2804 break; 2805 case FWOHCIEV_BUSRST: 2806 if (sc->fc.status != FWBUSRESET) 2807 printf("got BUSRST packet!?\n"); 2808 break; 2809 default: 2810 device_printf(sc->fc.dev, "Async DMA Receive error err = %02x %s\n", stat, fwohcicode[stat]); 2811 #if 0 /* XXX */ 2812 goto out; 2813 #endif 2814 break; 2815 } 2816 pcnt ++; 2817 if (dbch->pdb_tr != NULL) { 2818 fwohci_arcv_free_buf(dbch, dbch->pdb_tr); 2819 dbch->pdb_tr = NULL; 2820 } 2821 2822 } 2823 out: 2824 if (resCount == 0) { 2825 /* done on this buffer */ 2826 if (dbch->pdb_tr == NULL) { 2827 fwohci_arcv_free_buf(dbch, db_tr); 2828 dbch->buf_offset = 0; 2829 } else 2830 if (dbch->pdb_tr != db_tr) 2831 printf("pdb_tr != db_tr\n"); 2832 db_tr = STAILQ_NEXT(db_tr, link); 2833 status = FWOHCI_DMA_READ(db_tr->db[0].db.desc.res) 2834 >> OHCI_STATUS_SHIFT; 2835 resCount = FWOHCI_DMA_READ(db_tr->db[0].db.desc.res) 2836 & OHCI_COUNT_MASK; 2837 /* XXX check buffer overrun */ 2838 dbch->top = db_tr; 2839 } else { 2840 dbch->buf_offset = dbch->xferq.psize - resCount; 2841 break; 2842 } 2843 /* XXX make sure DMA is not dead */ 2844 } 2845 #if 0 2846 if (pcnt < 1) 2847 printf("fwohci_arcv: no packets\n"); 2848 #endif 2849 splx(s); 2850 } 2851