13c60ba66SKatsushi Kobayashi /* 277ee030bSHidetoshi Shimokawa * Copyright (c) 2003 Hidetoshi Shimokawa 33c60ba66SKatsushi Kobayashi * Copyright (c) 1998-2002 Katsushi Kobayashi and Hidetoshi Shimokawa 43c60ba66SKatsushi Kobayashi * All rights reserved. 53c60ba66SKatsushi Kobayashi * 63c60ba66SKatsushi Kobayashi * Redistribution and use in source and binary forms, with or without 73c60ba66SKatsushi Kobayashi * modification, are permitted provided that the following conditions 83c60ba66SKatsushi Kobayashi * are met: 93c60ba66SKatsushi Kobayashi * 1. Redistributions of source code must retain the above copyright 103c60ba66SKatsushi Kobayashi * notice, this list of conditions and the following disclaimer. 113c60ba66SKatsushi Kobayashi * 2. Redistributions in binary form must reproduce the above copyright 123c60ba66SKatsushi Kobayashi * notice, this list of conditions and the following disclaimer in the 133c60ba66SKatsushi Kobayashi * documentation and/or other materials provided with the distribution. 143c60ba66SKatsushi Kobayashi * 3. All advertising materials mentioning features or use of this software 153c60ba66SKatsushi Kobayashi * must display the acknowledgement as bellow: 163c60ba66SKatsushi Kobayashi * 178da326fdSHidetoshi Shimokawa * This product includes software developed by K. Kobayashi and H. Shimokawa 183c60ba66SKatsushi Kobayashi * 193c60ba66SKatsushi Kobayashi * 4. The name of the author may not be used to endorse or promote products 203c60ba66SKatsushi Kobayashi * derived from this software without specific prior written permission. 213c60ba66SKatsushi Kobayashi * 223c60ba66SKatsushi Kobayashi * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 233c60ba66SKatsushi Kobayashi * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 243c60ba66SKatsushi Kobayashi * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 253c60ba66SKatsushi Kobayashi * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 263c60ba66SKatsushi Kobayashi * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 273c60ba66SKatsushi Kobayashi * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 283c60ba66SKatsushi Kobayashi * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 293c60ba66SKatsushi Kobayashi * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 303c60ba66SKatsushi Kobayashi * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 313c60ba66SKatsushi Kobayashi * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 323c60ba66SKatsushi Kobayashi * POSSIBILITY OF SUCH DAMAGE. 333c60ba66SKatsushi Kobayashi * 343c60ba66SKatsushi Kobayashi * $FreeBSD$ 353c60ba66SKatsushi Kobayashi * 363c60ba66SKatsushi Kobayashi */ 378da326fdSHidetoshi Shimokawa 383c60ba66SKatsushi Kobayashi #define ATRQ_CH 0 393c60ba66SKatsushi Kobayashi #define ATRS_CH 1 403c60ba66SKatsushi Kobayashi #define ARRQ_CH 2 413c60ba66SKatsushi Kobayashi #define ARRS_CH 3 423c60ba66SKatsushi Kobayashi #define ITX_CH 4 433c60ba66SKatsushi Kobayashi #define IRX_CH 0x24 443c60ba66SKatsushi Kobayashi 453c60ba66SKatsushi Kobayashi #include <sys/param.h> 465a7ba74dSHidetoshi Shimokawa #include <sys/proc.h> 473c60ba66SKatsushi Kobayashi #include <sys/systm.h> 483c60ba66SKatsushi Kobayashi #include <sys/types.h> 493c60ba66SKatsushi Kobayashi #include <sys/mbuf.h> 503c60ba66SKatsushi Kobayashi #include <sys/mman.h> 513c60ba66SKatsushi Kobayashi #include <sys/socket.h> 523c60ba66SKatsushi Kobayashi #include <sys/socketvar.h> 533c60ba66SKatsushi Kobayashi #include <sys/signalvar.h> 543c60ba66SKatsushi Kobayashi #include <sys/malloc.h> 553c60ba66SKatsushi Kobayashi #include <sys/sockio.h> 563c60ba66SKatsushi Kobayashi #include <sys/bus.h> 573c60ba66SKatsushi Kobayashi #include <sys/kernel.h> 583c60ba66SKatsushi Kobayashi #include <sys/conf.h> 5977ee030bSHidetoshi Shimokawa #include <sys/endian.h> 603c60ba66SKatsushi Kobayashi 613c60ba66SKatsushi Kobayashi #include <machine/bus.h> 623c60ba66SKatsushi Kobayashi #include <machine/resource.h> 633c60ba66SKatsushi Kobayashi #include <sys/rman.h> 643c60ba66SKatsushi Kobayashi 653c60ba66SKatsushi Kobayashi #include <machine/cpufunc.h> /* for rdtsc proto for clock.h below */ 663c60ba66SKatsushi Kobayashi #include <machine/clock.h> 673c60ba66SKatsushi Kobayashi #include <pci/pcivar.h> 683c60ba66SKatsushi Kobayashi #include <pci/pcireg.h> 693c60ba66SKatsushi Kobayashi 703c60ba66SKatsushi Kobayashi #include <dev/firewire/firewire.h> 713c60ba66SKatsushi Kobayashi #include <dev/firewire/firewirereg.h> 7277ee030bSHidetoshi Shimokawa #include <dev/firewire/fwdma.h> 733c60ba66SKatsushi Kobayashi #include <dev/firewire/fwohcireg.h> 743c60ba66SKatsushi Kobayashi #include <dev/firewire/fwohcivar.h> 753c60ba66SKatsushi Kobayashi #include <dev/firewire/firewire_phy.h> 763c60ba66SKatsushi Kobayashi 770aaa9a23SHidetoshi Shimokawa #include <dev/firewire/iec68113.h> 780aaa9a23SHidetoshi Shimokawa 793c60ba66SKatsushi Kobayashi #undef OHCI_DEBUG 808da326fdSHidetoshi Shimokawa 813c60ba66SKatsushi Kobayashi static char dbcode[16][0x10]={"OUTM", "OUTL","INPM","INPL", 823c60ba66SKatsushi Kobayashi "STOR","LOAD","NOP ","STOP",}; 8377ee030bSHidetoshi Shimokawa 843c60ba66SKatsushi Kobayashi static char dbkey[8][0x10]={"ST0", "ST1","ST2","ST3", 853c60ba66SKatsushi Kobayashi "UNDEF","REG","SYS","DEV"}; 8677ee030bSHidetoshi Shimokawa static char dbcond[4][0x10]={"NEV","C=1", "C=0", "ALL"}; 873c60ba66SKatsushi Kobayashi char fwohcicode[32][0x20]={ 883c60ba66SKatsushi Kobayashi "No stat","Undef","long","miss Ack err", 893c60ba66SKatsushi Kobayashi "underrun","overrun","desc err", "data read err", 903c60ba66SKatsushi Kobayashi "data write err","bus reset","timeout","tcode err", 913c60ba66SKatsushi Kobayashi "Undef","Undef","unknown event","flushed", 923c60ba66SKatsushi Kobayashi "Undef","ack complete","ack pend","Undef", 933c60ba66SKatsushi Kobayashi "ack busy_X","ack busy_A","ack busy_B","Undef", 943c60ba66SKatsushi Kobayashi "Undef","Undef","Undef","ack tardy", 953c60ba66SKatsushi Kobayashi "Undef","ack data_err","ack type_err",""}; 9677ee030bSHidetoshi Shimokawa 973c60ba66SKatsushi Kobayashi #define MAX_SPEED 2 983c60ba66SKatsushi Kobayashi extern char linkspeed[MAX_SPEED+1][0x10]; 993c60ba66SKatsushi Kobayashi u_int32_t tagbit[4] = { 1 << 28, 1 << 29, 1 << 30, 1 << 31}; 1003c60ba66SKatsushi Kobayashi 1013c60ba66SKatsushi Kobayashi static struct tcode_info tinfo[] = { 1023c60ba66SKatsushi Kobayashi /* hdr_len block flag*/ 1033c60ba66SKatsushi Kobayashi /* 0 WREQQ */ {16, FWTI_REQ | FWTI_TLABEL}, 1043c60ba66SKatsushi Kobayashi /* 1 WREQB */ {16, FWTI_REQ | FWTI_TLABEL | FWTI_BLOCK_ASY}, 1053c60ba66SKatsushi Kobayashi /* 2 WRES */ {12, FWTI_RES}, 1063c60ba66SKatsushi Kobayashi /* 3 XXX */ { 0, 0}, 1073c60ba66SKatsushi Kobayashi /* 4 RREQQ */ {12, FWTI_REQ | FWTI_TLABEL}, 1083c60ba66SKatsushi Kobayashi /* 5 RREQB */ {16, FWTI_REQ | FWTI_TLABEL}, 1093c60ba66SKatsushi Kobayashi /* 6 RRESQ */ {16, FWTI_RES}, 1103c60ba66SKatsushi Kobayashi /* 7 RRESB */ {16, FWTI_RES | FWTI_BLOCK_ASY}, 1113c60ba66SKatsushi Kobayashi /* 8 CYCS */ { 0, 0}, 1123c60ba66SKatsushi Kobayashi /* 9 LREQ */ {16, FWTI_REQ | FWTI_TLABEL | FWTI_BLOCK_ASY}, 1133c60ba66SKatsushi Kobayashi /* a STREAM */ { 4, FWTI_REQ | FWTI_BLOCK_STR}, 1143c60ba66SKatsushi Kobayashi /* b LRES */ {16, FWTI_RES | FWTI_BLOCK_ASY}, 1153c60ba66SKatsushi Kobayashi /* c XXX */ { 0, 0}, 1163c60ba66SKatsushi Kobayashi /* d XXX */ { 0, 0}, 1173c60ba66SKatsushi Kobayashi /* e PHY */ {12, FWTI_REQ}, 1183c60ba66SKatsushi Kobayashi /* f XXX */ { 0, 0} 1193c60ba66SKatsushi Kobayashi }; 1203c60ba66SKatsushi Kobayashi 1213c60ba66SKatsushi Kobayashi #define OHCI_WRITE_SIGMASK 0xffff0000 1223c60ba66SKatsushi Kobayashi #define OHCI_READ_SIGMASK 0xffff0000 1233c60ba66SKatsushi Kobayashi 1243c60ba66SKatsushi Kobayashi #define OWRITE(sc, r, x) bus_space_write_4((sc)->bst, (sc)->bsh, (r), (x)) 1253c60ba66SKatsushi Kobayashi #define OREAD(sc, r) bus_space_read_4((sc)->bst, (sc)->bsh, (r)) 1263c60ba66SKatsushi Kobayashi 1273c60ba66SKatsushi Kobayashi static void fwohci_ibr __P((struct firewire_comm *)); 12877ee030bSHidetoshi Shimokawa static void fwohci_db_init __P((struct fwohci_softc *, struct fwohci_dbch *)); 1293c60ba66SKatsushi Kobayashi static void fwohci_db_free __P((struct fwohci_dbch *)); 130783058faSHidetoshi Shimokawa static void fwohci_arcv __P((struct fwohci_softc *, struct fwohci_dbch *, int)); 1313c60ba66SKatsushi Kobayashi static void fwohci_txd __P((struct fwohci_softc *, struct fwohci_dbch *)); 1323c60ba66SKatsushi Kobayashi static void fwohci_start_atq __P((struct firewire_comm *)); 1333c60ba66SKatsushi Kobayashi static void fwohci_start_ats __P((struct firewire_comm *)); 1343c60ba66SKatsushi Kobayashi static void fwohci_start __P((struct fwohci_softc *, struct fwohci_dbch *)); 1353c60ba66SKatsushi Kobayashi static u_int32_t fwphy_wrdata __P(( struct fwohci_softc *, u_int32_t, u_int32_t)); 1363c60ba66SKatsushi Kobayashi static u_int32_t fwphy_rddata __P(( struct fwohci_softc *, u_int32_t)); 1373c60ba66SKatsushi Kobayashi static int fwohci_rx_enable __P((struct fwohci_softc *, struct fwohci_dbch *)); 1383c60ba66SKatsushi Kobayashi static int fwohci_tx_enable __P((struct fwohci_softc *, struct fwohci_dbch *)); 1393c60ba66SKatsushi Kobayashi static int fwohci_irx_enable __P((struct firewire_comm *, int)); 1403c60ba66SKatsushi Kobayashi static int fwohci_irx_disable __P((struct firewire_comm *, int)); 14177ee030bSHidetoshi Shimokawa #if BYTE_ORDER == BIG_ENDIAN 1423c60ba66SKatsushi Kobayashi static void fwohci_irx_post __P((struct firewire_comm *, u_int32_t *)); 14377ee030bSHidetoshi Shimokawa #endif 1443c60ba66SKatsushi Kobayashi static int fwohci_itxbuf_enable __P((struct firewire_comm *, int)); 1453c60ba66SKatsushi Kobayashi static int fwohci_itx_disable __P((struct firewire_comm *, int)); 1463c60ba66SKatsushi Kobayashi static void fwohci_timeout __P((void *)); 1473c60ba66SKatsushi Kobayashi static void fwohci_poll __P((struct firewire_comm *, int, int)); 1483c60ba66SKatsushi Kobayashi static void fwohci_set_intr __P((struct firewire_comm *, int)); 14977ee030bSHidetoshi Shimokawa 15077ee030bSHidetoshi Shimokawa static int fwohci_add_rx_buf __P((struct fwohci_dbch *, struct fwohcidb_tr *, int, struct fwdma_alloc *)); 15177ee030bSHidetoshi Shimokawa static int fwohci_add_tx_buf __P((struct fwohci_dbch *, struct fwohcidb_tr *, int)); 1523c60ba66SKatsushi Kobayashi static void dump_db __P((struct fwohci_softc *, u_int32_t)); 15377ee030bSHidetoshi Shimokawa static void print_db __P((struct fwohcidb_tr *, volatile struct fwohcidb *, u_int32_t , u_int32_t)); 1543c60ba66SKatsushi Kobayashi static void dump_dma __P((struct fwohci_softc *, u_int32_t)); 1553c60ba66SKatsushi Kobayashi static u_int32_t fwohci_cyctimer __P((struct firewire_comm *)); 1563c60ba66SKatsushi Kobayashi static void fwohci_rbuf_update __P((struct fwohci_softc *, int)); 1573c60ba66SKatsushi Kobayashi static void fwohci_tbuf_update __P((struct fwohci_softc *, int)); 1583c60ba66SKatsushi Kobayashi void fwohci_txbufdb __P((struct fwohci_softc *, int , struct fw_bulkxfer *)); 15977ee030bSHidetoshi Shimokawa #if FWOHCI_TASKQUEUE 16077ee030bSHidetoshi Shimokawa static void fwohci_complete(void *, int); 16177ee030bSHidetoshi Shimokawa #endif 1623c60ba66SKatsushi Kobayashi 1633c60ba66SKatsushi Kobayashi /* 1643c60ba66SKatsushi Kobayashi * memory allocated for DMA programs 1653c60ba66SKatsushi Kobayashi */ 1663c60ba66SKatsushi Kobayashi #define DMA_PROG_ALLOC (8 * PAGE_SIZE) 1673c60ba66SKatsushi Kobayashi 1683c60ba66SKatsushi Kobayashi /* #define NDB 1024 */ 1693c60ba66SKatsushi Kobayashi #define NDB FWMAXQUEUE 1703c60ba66SKatsushi Kobayashi #define NDVDB (DVBUF * NDB) 1713c60ba66SKatsushi Kobayashi 1723c60ba66SKatsushi Kobayashi #define OHCI_VERSION 0x00 17373aa55baSHidetoshi Shimokawa #define OHCI_ATRETRY 0x08 1743c60ba66SKatsushi Kobayashi #define OHCI_CROMHDR 0x18 1753c60ba66SKatsushi Kobayashi #define OHCI_BUS_OPT 0x20 1763c60ba66SKatsushi Kobayashi #define OHCI_BUSIRMC (1 << 31) 1773c60ba66SKatsushi Kobayashi #define OHCI_BUSCMC (1 << 30) 1783c60ba66SKatsushi Kobayashi #define OHCI_BUSISC (1 << 29) 1793c60ba66SKatsushi Kobayashi #define OHCI_BUSBMC (1 << 28) 1803c60ba66SKatsushi Kobayashi #define OHCI_BUSPMC (1 << 27) 1813c60ba66SKatsushi Kobayashi #define OHCI_BUSFNC OHCI_BUSIRMC | OHCI_BUSCMC | OHCI_BUSISC |\ 1823c60ba66SKatsushi Kobayashi OHCI_BUSBMC | OHCI_BUSPMC 1833c60ba66SKatsushi Kobayashi 1843c60ba66SKatsushi Kobayashi #define OHCI_EUID_HI 0x24 1853c60ba66SKatsushi Kobayashi #define OHCI_EUID_LO 0x28 1863c60ba66SKatsushi Kobayashi 1873c60ba66SKatsushi Kobayashi #define OHCI_CROMPTR 0x34 1883c60ba66SKatsushi Kobayashi #define OHCI_HCCCTL 0x50 1893c60ba66SKatsushi Kobayashi #define OHCI_HCCCTLCLR 0x54 1903c60ba66SKatsushi Kobayashi #define OHCI_AREQHI 0x100 1913c60ba66SKatsushi Kobayashi #define OHCI_AREQHICLR 0x104 1923c60ba66SKatsushi Kobayashi #define OHCI_AREQLO 0x108 1933c60ba66SKatsushi Kobayashi #define OHCI_AREQLOCLR 0x10c 1943c60ba66SKatsushi Kobayashi #define OHCI_PREQHI 0x110 1953c60ba66SKatsushi Kobayashi #define OHCI_PREQHICLR 0x114 1963c60ba66SKatsushi Kobayashi #define OHCI_PREQLO 0x118 1973c60ba66SKatsushi Kobayashi #define OHCI_PREQLOCLR 0x11c 1983c60ba66SKatsushi Kobayashi #define OHCI_PREQUPPER 0x120 1993c60ba66SKatsushi Kobayashi 2003c60ba66SKatsushi Kobayashi #define OHCI_SID_BUF 0x64 2013c60ba66SKatsushi Kobayashi #define OHCI_SID_CNT 0x68 20277ee030bSHidetoshi Shimokawa #define OHCI_SID_ERR (1 << 31) 2033c60ba66SKatsushi Kobayashi #define OHCI_SID_CNT_MASK 0xffc 2043c60ba66SKatsushi Kobayashi 2053c60ba66SKatsushi Kobayashi #define OHCI_IT_STAT 0x90 2063c60ba66SKatsushi Kobayashi #define OHCI_IT_STATCLR 0x94 2073c60ba66SKatsushi Kobayashi #define OHCI_IT_MASK 0x98 2083c60ba66SKatsushi Kobayashi #define OHCI_IT_MASKCLR 0x9c 2093c60ba66SKatsushi Kobayashi 2103c60ba66SKatsushi Kobayashi #define OHCI_IR_STAT 0xa0 2113c60ba66SKatsushi Kobayashi #define OHCI_IR_STATCLR 0xa4 2123c60ba66SKatsushi Kobayashi #define OHCI_IR_MASK 0xa8 2133c60ba66SKatsushi Kobayashi #define OHCI_IR_MASKCLR 0xac 2143c60ba66SKatsushi Kobayashi 2153c60ba66SKatsushi Kobayashi #define OHCI_LNKCTL 0xe0 2163c60ba66SKatsushi Kobayashi #define OHCI_LNKCTLCLR 0xe4 2173c60ba66SKatsushi Kobayashi 2183c60ba66SKatsushi Kobayashi #define OHCI_PHYACCESS 0xec 2193c60ba66SKatsushi Kobayashi #define OHCI_CYCLETIMER 0xf0 2203c60ba66SKatsushi Kobayashi 2213c60ba66SKatsushi Kobayashi #define OHCI_DMACTL(off) (off) 2223c60ba66SKatsushi Kobayashi #define OHCI_DMACTLCLR(off) (off + 4) 2233c60ba66SKatsushi Kobayashi #define OHCI_DMACMD(off) (off + 0xc) 2243c60ba66SKatsushi Kobayashi #define OHCI_DMAMATCH(off) (off + 0x10) 2253c60ba66SKatsushi Kobayashi 2263c60ba66SKatsushi Kobayashi #define OHCI_ATQOFF 0x180 2273c60ba66SKatsushi Kobayashi #define OHCI_ATQCTL OHCI_ATQOFF 2283c60ba66SKatsushi Kobayashi #define OHCI_ATQCTLCLR (OHCI_ATQOFF + 4) 2293c60ba66SKatsushi Kobayashi #define OHCI_ATQCMD (OHCI_ATQOFF + 0xc) 2303c60ba66SKatsushi Kobayashi #define OHCI_ATQMATCH (OHCI_ATQOFF + 0x10) 2313c60ba66SKatsushi Kobayashi 2323c60ba66SKatsushi Kobayashi #define OHCI_ATSOFF 0x1a0 2333c60ba66SKatsushi Kobayashi #define OHCI_ATSCTL OHCI_ATSOFF 2343c60ba66SKatsushi Kobayashi #define OHCI_ATSCTLCLR (OHCI_ATSOFF + 4) 2353c60ba66SKatsushi Kobayashi #define OHCI_ATSCMD (OHCI_ATSOFF + 0xc) 2363c60ba66SKatsushi Kobayashi #define OHCI_ATSMATCH (OHCI_ATSOFF + 0x10) 2373c60ba66SKatsushi Kobayashi 2383c60ba66SKatsushi Kobayashi #define OHCI_ARQOFF 0x1c0 2393c60ba66SKatsushi Kobayashi #define OHCI_ARQCTL OHCI_ARQOFF 2403c60ba66SKatsushi Kobayashi #define OHCI_ARQCTLCLR (OHCI_ARQOFF + 4) 2413c60ba66SKatsushi Kobayashi #define OHCI_ARQCMD (OHCI_ARQOFF + 0xc) 2423c60ba66SKatsushi Kobayashi #define OHCI_ARQMATCH (OHCI_ARQOFF + 0x10) 2433c60ba66SKatsushi Kobayashi 2443c60ba66SKatsushi Kobayashi #define OHCI_ARSOFF 0x1e0 2453c60ba66SKatsushi Kobayashi #define OHCI_ARSCTL OHCI_ARSOFF 2463c60ba66SKatsushi Kobayashi #define OHCI_ARSCTLCLR (OHCI_ARSOFF + 4) 2473c60ba66SKatsushi Kobayashi #define OHCI_ARSCMD (OHCI_ARSOFF + 0xc) 2483c60ba66SKatsushi Kobayashi #define OHCI_ARSMATCH (OHCI_ARSOFF + 0x10) 2493c60ba66SKatsushi Kobayashi 2503c60ba66SKatsushi Kobayashi #define OHCI_ITOFF(CH) (0x200 + 0x10 * (CH)) 2513c60ba66SKatsushi Kobayashi #define OHCI_ITCTL(CH) (OHCI_ITOFF(CH)) 2523c60ba66SKatsushi Kobayashi #define OHCI_ITCTLCLR(CH) (OHCI_ITOFF(CH) + 4) 2533c60ba66SKatsushi Kobayashi #define OHCI_ITCMD(CH) (OHCI_ITOFF(CH) + 0xc) 2543c60ba66SKatsushi Kobayashi 2553c60ba66SKatsushi Kobayashi #define OHCI_IROFF(CH) (0x400 + 0x20 * (CH)) 2563c60ba66SKatsushi Kobayashi #define OHCI_IRCTL(CH) (OHCI_IROFF(CH)) 2573c60ba66SKatsushi Kobayashi #define OHCI_IRCTLCLR(CH) (OHCI_IROFF(CH) + 4) 2583c60ba66SKatsushi Kobayashi #define OHCI_IRCMD(CH) (OHCI_IROFF(CH) + 0xc) 2593c60ba66SKatsushi Kobayashi #define OHCI_IRMATCH(CH) (OHCI_IROFF(CH) + 0x10) 2603c60ba66SKatsushi Kobayashi 2613c60ba66SKatsushi Kobayashi d_ioctl_t fwohci_ioctl; 2623c60ba66SKatsushi Kobayashi 2633c60ba66SKatsushi Kobayashi /* 2643c60ba66SKatsushi Kobayashi * Communication with PHY device 2653c60ba66SKatsushi Kobayashi */ 266c572b810SHidetoshi Shimokawa static u_int32_t 267c572b810SHidetoshi Shimokawa fwphy_wrdata( struct fwohci_softc *sc, u_int32_t addr, u_int32_t data) 2683c60ba66SKatsushi Kobayashi { 2693c60ba66SKatsushi Kobayashi u_int32_t fun; 2703c60ba66SKatsushi Kobayashi 2713c60ba66SKatsushi Kobayashi addr &= 0xf; 2723c60ba66SKatsushi Kobayashi data &= 0xff; 2733c60ba66SKatsushi Kobayashi 2743c60ba66SKatsushi Kobayashi fun = (PHYDEV_WRCMD | (addr << PHYDEV_REGADDR) | (data << PHYDEV_WRDATA)); 2753c60ba66SKatsushi Kobayashi OWRITE(sc, OHCI_PHYACCESS, fun); 2763c60ba66SKatsushi Kobayashi DELAY(100); 2773c60ba66SKatsushi Kobayashi 2783c60ba66SKatsushi Kobayashi return(fwphy_rddata( sc, addr)); 2793c60ba66SKatsushi Kobayashi } 2803c60ba66SKatsushi Kobayashi 2813c60ba66SKatsushi Kobayashi static u_int32_t 2823c60ba66SKatsushi Kobayashi fwohci_set_bus_manager(struct firewire_comm *fc, u_int node) 2833c60ba66SKatsushi Kobayashi { 2843c60ba66SKatsushi Kobayashi struct fwohci_softc *sc = (struct fwohci_softc *)fc; 2853c60ba66SKatsushi Kobayashi int i; 2863c60ba66SKatsushi Kobayashi u_int32_t bm; 2873c60ba66SKatsushi Kobayashi 2883c60ba66SKatsushi Kobayashi #define OHCI_CSR_DATA 0x0c 2893c60ba66SKatsushi Kobayashi #define OHCI_CSR_COMP 0x10 2903c60ba66SKatsushi Kobayashi #define OHCI_CSR_CONT 0x14 2913c60ba66SKatsushi Kobayashi #define OHCI_BUS_MANAGER_ID 0 2923c60ba66SKatsushi Kobayashi 2933c60ba66SKatsushi Kobayashi OWRITE(sc, OHCI_CSR_DATA, node); 2943c60ba66SKatsushi Kobayashi OWRITE(sc, OHCI_CSR_COMP, 0x3f); 2953c60ba66SKatsushi Kobayashi OWRITE(sc, OHCI_CSR_CONT, OHCI_BUS_MANAGER_ID); 2963c60ba66SKatsushi Kobayashi for (i = 0; !(OREAD(sc, OHCI_CSR_CONT) & (1<<31)) && (i < 1000); i++) 2974ed65ce9SHidetoshi Shimokawa DELAY(10); 2983c60ba66SKatsushi Kobayashi bm = OREAD(sc, OHCI_CSR_DATA); 29917c3d42cSHidetoshi Shimokawa if((bm & 0x3f) == 0x3f) 3003c60ba66SKatsushi Kobayashi bm = node; 30117c3d42cSHidetoshi Shimokawa if (bootverbose) 30217c3d42cSHidetoshi Shimokawa device_printf(sc->fc.dev, 30317c3d42cSHidetoshi Shimokawa "fw_set_bus_manager: %d->%d (loop=%d)\n", bm, node, i); 3043c60ba66SKatsushi Kobayashi 3053c60ba66SKatsushi Kobayashi return(bm); 3063c60ba66SKatsushi Kobayashi } 3073c60ba66SKatsushi Kobayashi 308c572b810SHidetoshi Shimokawa static u_int32_t 309c572b810SHidetoshi Shimokawa fwphy_rddata(struct fwohci_softc *sc, u_int addr) 3103c60ba66SKatsushi Kobayashi { 311e4b13179SHidetoshi Shimokawa u_int32_t fun, stat; 312e4b13179SHidetoshi Shimokawa u_int i, retry = 0; 3133c60ba66SKatsushi Kobayashi 3143c60ba66SKatsushi Kobayashi addr &= 0xf; 315e4b13179SHidetoshi Shimokawa #define MAX_RETRY 100 316e4b13179SHidetoshi Shimokawa again: 317e4b13179SHidetoshi Shimokawa OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_REG_FAIL); 3183c60ba66SKatsushi Kobayashi fun = PHYDEV_RDCMD | (addr << PHYDEV_REGADDR); 3193c60ba66SKatsushi Kobayashi OWRITE(sc, OHCI_PHYACCESS, fun); 320e4b13179SHidetoshi Shimokawa for ( i = 0 ; i < MAX_RETRY ; i ++ ){ 3213c60ba66SKatsushi Kobayashi fun = OREAD(sc, OHCI_PHYACCESS); 3223c60ba66SKatsushi Kobayashi if ((fun & PHYDEV_RDCMD) == 0 && (fun & PHYDEV_RDDONE) != 0) 3233c60ba66SKatsushi Kobayashi break; 3244ed65ce9SHidetoshi Shimokawa DELAY(100); 3253c60ba66SKatsushi Kobayashi } 326e4b13179SHidetoshi Shimokawa if(i >= MAX_RETRY) { 3274ed65ce9SHidetoshi Shimokawa if (bootverbose) 3284ed65ce9SHidetoshi Shimokawa device_printf(sc->fc.dev, "phy read failed(1).\n"); 3291f2361f8SHidetoshi Shimokawa if (++retry < MAX_RETRY) { 3304ed65ce9SHidetoshi Shimokawa DELAY(100); 3311f2361f8SHidetoshi Shimokawa goto again; 3321f2361f8SHidetoshi Shimokawa } 333e4b13179SHidetoshi Shimokawa } 334e4b13179SHidetoshi Shimokawa /* Make sure that SCLK is started */ 335e4b13179SHidetoshi Shimokawa stat = OREAD(sc, FWOHCI_INTSTAT); 336e4b13179SHidetoshi Shimokawa if ((stat & OHCI_INT_REG_FAIL) != 0 || 337e4b13179SHidetoshi Shimokawa ((fun >> PHYDEV_REGADDR) & 0xf) != addr) { 3384ed65ce9SHidetoshi Shimokawa if (bootverbose) 3394ed65ce9SHidetoshi Shimokawa device_printf(sc->fc.dev, "phy read failed(2).\n"); 340e4b13179SHidetoshi Shimokawa if (++retry < MAX_RETRY) { 3414ed65ce9SHidetoshi Shimokawa DELAY(100); 342e4b13179SHidetoshi Shimokawa goto again; 343e4b13179SHidetoshi Shimokawa } 344e4b13179SHidetoshi Shimokawa } 345e4b13179SHidetoshi Shimokawa if (bootverbose || retry >= MAX_RETRY) 346e4b13179SHidetoshi Shimokawa device_printf(sc->fc.dev, 347e4b13179SHidetoshi Shimokawa "fwphy_rddata: loop=%d, retry=%d\n", i, retry); 348e4b13179SHidetoshi Shimokawa #undef MAX_RETRY 3493c60ba66SKatsushi Kobayashi return((fun >> PHYDEV_RDDATA )& 0xff); 3503c60ba66SKatsushi Kobayashi } 3513c60ba66SKatsushi Kobayashi /* Device specific ioctl. */ 3523c60ba66SKatsushi Kobayashi int 3533c60ba66SKatsushi Kobayashi fwohci_ioctl (dev_t dev, u_long cmd, caddr_t data, int flag, fw_proc *td) 3543c60ba66SKatsushi Kobayashi { 3553c60ba66SKatsushi Kobayashi struct firewire_softc *sc; 3563c60ba66SKatsushi Kobayashi struct fwohci_softc *fc; 3573c60ba66SKatsushi Kobayashi int unit = DEV2UNIT(dev); 3583c60ba66SKatsushi Kobayashi int err = 0; 3593c60ba66SKatsushi Kobayashi struct fw_reg_req_t *reg = (struct fw_reg_req_t *) data; 3603c60ba66SKatsushi Kobayashi u_int32_t *dmach = (u_int32_t *) data; 3613c60ba66SKatsushi Kobayashi 3623c60ba66SKatsushi Kobayashi sc = devclass_get_softc(firewire_devclass, unit); 3633c60ba66SKatsushi Kobayashi if(sc == NULL){ 3643c60ba66SKatsushi Kobayashi return(EINVAL); 3653c60ba66SKatsushi Kobayashi } 3663c60ba66SKatsushi Kobayashi fc = (struct fwohci_softc *)sc->fc; 3673c60ba66SKatsushi Kobayashi 3683c60ba66SKatsushi Kobayashi if (!data) 3693c60ba66SKatsushi Kobayashi return(EINVAL); 3703c60ba66SKatsushi Kobayashi 3713c60ba66SKatsushi Kobayashi switch (cmd) { 3723c60ba66SKatsushi Kobayashi case FWOHCI_WRREG: 3733c60ba66SKatsushi Kobayashi #define OHCI_MAX_REG 0x800 3743c60ba66SKatsushi Kobayashi if(reg->addr <= OHCI_MAX_REG){ 3753c60ba66SKatsushi Kobayashi OWRITE(fc, reg->addr, reg->data); 3763c60ba66SKatsushi Kobayashi reg->data = OREAD(fc, reg->addr); 3773c60ba66SKatsushi Kobayashi }else{ 3783c60ba66SKatsushi Kobayashi err = EINVAL; 3793c60ba66SKatsushi Kobayashi } 3803c60ba66SKatsushi Kobayashi break; 3813c60ba66SKatsushi Kobayashi case FWOHCI_RDREG: 3823c60ba66SKatsushi Kobayashi if(reg->addr <= OHCI_MAX_REG){ 3833c60ba66SKatsushi Kobayashi reg->data = OREAD(fc, reg->addr); 3843c60ba66SKatsushi Kobayashi }else{ 3853c60ba66SKatsushi Kobayashi err = EINVAL; 3863c60ba66SKatsushi Kobayashi } 3873c60ba66SKatsushi Kobayashi break; 3883c60ba66SKatsushi Kobayashi /* Read DMA descriptors for debug */ 3893c60ba66SKatsushi Kobayashi case DUMPDMA: 3903c60ba66SKatsushi Kobayashi if(*dmach <= OHCI_MAX_DMA_CH ){ 3913c60ba66SKatsushi Kobayashi dump_dma(fc, *dmach); 3923c60ba66SKatsushi Kobayashi dump_db(fc, *dmach); 3933c60ba66SKatsushi Kobayashi }else{ 3943c60ba66SKatsushi Kobayashi err = EINVAL; 3953c60ba66SKatsushi Kobayashi } 3963c60ba66SKatsushi Kobayashi break; 3973c60ba66SKatsushi Kobayashi default: 3983c60ba66SKatsushi Kobayashi break; 3993c60ba66SKatsushi Kobayashi } 4003c60ba66SKatsushi Kobayashi return err; 4013c60ba66SKatsushi Kobayashi } 402c572b810SHidetoshi Shimokawa 403d0fd7bc6SHidetoshi Shimokawa static int 404d0fd7bc6SHidetoshi Shimokawa fwohci_probe_phy(struct fwohci_softc *sc, device_t dev) 4053c60ba66SKatsushi Kobayashi { 406d0fd7bc6SHidetoshi Shimokawa u_int32_t reg, reg2; 407d0fd7bc6SHidetoshi Shimokawa int e1394a = 1; 408d0fd7bc6SHidetoshi Shimokawa /* 409d0fd7bc6SHidetoshi Shimokawa * probe PHY parameters 410d0fd7bc6SHidetoshi Shimokawa * 0. to prove PHY version, whether compliance of 1394a. 411d0fd7bc6SHidetoshi Shimokawa * 1. to probe maximum speed supported by the PHY and 412d0fd7bc6SHidetoshi Shimokawa * number of port supported by core-logic. 413d0fd7bc6SHidetoshi Shimokawa * It is not actually available port on your PC . 414d0fd7bc6SHidetoshi Shimokawa */ 415d0fd7bc6SHidetoshi Shimokawa OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_LPS); 416d0fd7bc6SHidetoshi Shimokawa reg = fwphy_rddata(sc, FW_PHY_SPD_REG); 417d0fd7bc6SHidetoshi Shimokawa 418d0fd7bc6SHidetoshi Shimokawa if((reg >> 5) != 7 ){ 419d0fd7bc6SHidetoshi Shimokawa sc->fc.mode &= ~FWPHYASYST; 420d0fd7bc6SHidetoshi Shimokawa sc->fc.nport = reg & FW_PHY_NP; 421d0fd7bc6SHidetoshi Shimokawa sc->fc.speed = reg & FW_PHY_SPD >> 6; 422d0fd7bc6SHidetoshi Shimokawa if (sc->fc.speed > MAX_SPEED) { 423d0fd7bc6SHidetoshi Shimokawa device_printf(dev, "invalid speed %d (fixed to %d).\n", 424d0fd7bc6SHidetoshi Shimokawa sc->fc.speed, MAX_SPEED); 425d0fd7bc6SHidetoshi Shimokawa sc->fc.speed = MAX_SPEED; 426d0fd7bc6SHidetoshi Shimokawa } 427d0fd7bc6SHidetoshi Shimokawa device_printf(dev, 42894b6f028SHidetoshi Shimokawa "Phy 1394 only %s, %d ports.\n", 42994b6f028SHidetoshi Shimokawa linkspeed[sc->fc.speed], sc->fc.nport); 430d0fd7bc6SHidetoshi Shimokawa }else{ 431d0fd7bc6SHidetoshi Shimokawa reg2 = fwphy_rddata(sc, FW_PHY_ESPD_REG); 432d0fd7bc6SHidetoshi Shimokawa sc->fc.mode |= FWPHYASYST; 433d0fd7bc6SHidetoshi Shimokawa sc->fc.nport = reg & FW_PHY_NP; 434d0fd7bc6SHidetoshi Shimokawa sc->fc.speed = (reg2 & FW_PHY_ESPD) >> 5; 435d0fd7bc6SHidetoshi Shimokawa if (sc->fc.speed > MAX_SPEED) { 436d0fd7bc6SHidetoshi Shimokawa device_printf(dev, "invalid speed %d (fixed to %d).\n", 437d0fd7bc6SHidetoshi Shimokawa sc->fc.speed, MAX_SPEED); 438d0fd7bc6SHidetoshi Shimokawa sc->fc.speed = MAX_SPEED; 439d0fd7bc6SHidetoshi Shimokawa } 440d0fd7bc6SHidetoshi Shimokawa device_printf(dev, 44194b6f028SHidetoshi Shimokawa "Phy 1394a available %s, %d ports.\n", 44294b6f028SHidetoshi Shimokawa linkspeed[sc->fc.speed], sc->fc.nport); 443d0fd7bc6SHidetoshi Shimokawa 444d0fd7bc6SHidetoshi Shimokawa /* check programPhyEnable */ 445d0fd7bc6SHidetoshi Shimokawa reg2 = fwphy_rddata(sc, 5); 446d0fd7bc6SHidetoshi Shimokawa #if 0 447d0fd7bc6SHidetoshi Shimokawa if (e1394a && (OREAD(sc, OHCI_HCCCTL) & OHCI_HCC_PRPHY)) { 448d0fd7bc6SHidetoshi Shimokawa #else /* XXX force to enable 1394a */ 449d0fd7bc6SHidetoshi Shimokawa if (e1394a) { 450d0fd7bc6SHidetoshi Shimokawa #endif 451d0fd7bc6SHidetoshi Shimokawa if (bootverbose) 452d0fd7bc6SHidetoshi Shimokawa device_printf(dev, 453d0fd7bc6SHidetoshi Shimokawa "Enable 1394a Enhancements\n"); 454d0fd7bc6SHidetoshi Shimokawa /* enable EAA EMC */ 455d0fd7bc6SHidetoshi Shimokawa reg2 |= 0x03; 456d0fd7bc6SHidetoshi Shimokawa /* set aPhyEnhanceEnable */ 457d0fd7bc6SHidetoshi Shimokawa OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_PHYEN); 458d0fd7bc6SHidetoshi Shimokawa OWRITE(sc, OHCI_HCCCTLCLR, OHCI_HCC_PRPHY); 459d0fd7bc6SHidetoshi Shimokawa } else { 460d0fd7bc6SHidetoshi Shimokawa /* for safe */ 461d0fd7bc6SHidetoshi Shimokawa reg2 &= ~0x83; 462d0fd7bc6SHidetoshi Shimokawa } 463d0fd7bc6SHidetoshi Shimokawa reg2 = fwphy_wrdata(sc, 5, reg2); 464d0fd7bc6SHidetoshi Shimokawa } 465d0fd7bc6SHidetoshi Shimokawa 466d0fd7bc6SHidetoshi Shimokawa reg = fwphy_rddata(sc, FW_PHY_SPD_REG); 467d0fd7bc6SHidetoshi Shimokawa if((reg >> 5) == 7 ){ 468d0fd7bc6SHidetoshi Shimokawa reg = fwphy_rddata(sc, 4); 469d0fd7bc6SHidetoshi Shimokawa reg |= 1 << 6; 470d0fd7bc6SHidetoshi Shimokawa fwphy_wrdata(sc, 4, reg); 471d0fd7bc6SHidetoshi Shimokawa reg = fwphy_rddata(sc, 4); 472d0fd7bc6SHidetoshi Shimokawa } 473d0fd7bc6SHidetoshi Shimokawa return 0; 474d0fd7bc6SHidetoshi Shimokawa } 475d0fd7bc6SHidetoshi Shimokawa 476d0fd7bc6SHidetoshi Shimokawa 477d0fd7bc6SHidetoshi Shimokawa void 478d0fd7bc6SHidetoshi Shimokawa fwohci_reset(struct fwohci_softc *sc, device_t dev) 479d0fd7bc6SHidetoshi Shimokawa { 48094b6f028SHidetoshi Shimokawa int i, max_rec, speed; 4813c60ba66SKatsushi Kobayashi u_int32_t reg, reg2; 4823c60ba66SKatsushi Kobayashi struct fwohcidb_tr *db_tr; 483d0fd7bc6SHidetoshi Shimokawa 484d0fd7bc6SHidetoshi Shimokawa /* Disable interrupt */ 485d0fd7bc6SHidetoshi Shimokawa OWRITE(sc, FWOHCI_INTMASKCLR, ~0); 486d0fd7bc6SHidetoshi Shimokawa 487d0fd7bc6SHidetoshi Shimokawa /* Now stopping all DMA channel */ 488d0fd7bc6SHidetoshi Shimokawa OWRITE(sc, OHCI_ARQCTLCLR, OHCI_CNTL_DMA_RUN); 489d0fd7bc6SHidetoshi Shimokawa OWRITE(sc, OHCI_ARSCTLCLR, OHCI_CNTL_DMA_RUN); 490d0fd7bc6SHidetoshi Shimokawa OWRITE(sc, OHCI_ATQCTLCLR, OHCI_CNTL_DMA_RUN); 491d0fd7bc6SHidetoshi Shimokawa OWRITE(sc, OHCI_ATSCTLCLR, OHCI_CNTL_DMA_RUN); 492d0fd7bc6SHidetoshi Shimokawa 493d0fd7bc6SHidetoshi Shimokawa OWRITE(sc, OHCI_IR_MASKCLR, ~0); 494d0fd7bc6SHidetoshi Shimokawa for( i = 0 ; i < sc->fc.nisodma ; i ++ ){ 495d0fd7bc6SHidetoshi Shimokawa OWRITE(sc, OHCI_IRCTLCLR(i), OHCI_CNTL_DMA_RUN); 496d0fd7bc6SHidetoshi Shimokawa OWRITE(sc, OHCI_ITCTLCLR(i), OHCI_CNTL_DMA_RUN); 497d0fd7bc6SHidetoshi Shimokawa } 498d0fd7bc6SHidetoshi Shimokawa 499d0fd7bc6SHidetoshi Shimokawa /* FLUSH FIFO and reset Transmitter/Reciever */ 500d0fd7bc6SHidetoshi Shimokawa OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_RESET); 501d0fd7bc6SHidetoshi Shimokawa if (bootverbose) 502d0fd7bc6SHidetoshi Shimokawa device_printf(dev, "resetting OHCI..."); 503d0fd7bc6SHidetoshi Shimokawa i = 0; 504d0fd7bc6SHidetoshi Shimokawa while(OREAD(sc, OHCI_HCCCTL) & OHCI_HCC_RESET) { 505d0fd7bc6SHidetoshi Shimokawa if (i++ > 100) break; 506d0fd7bc6SHidetoshi Shimokawa DELAY(1000); 507d0fd7bc6SHidetoshi Shimokawa } 508d0fd7bc6SHidetoshi Shimokawa if (bootverbose) 509d0fd7bc6SHidetoshi Shimokawa printf("done (loop=%d)\n", i); 510d0fd7bc6SHidetoshi Shimokawa 51194b6f028SHidetoshi Shimokawa /* Probe phy */ 51294b6f028SHidetoshi Shimokawa fwohci_probe_phy(sc, dev); 51394b6f028SHidetoshi Shimokawa 51494b6f028SHidetoshi Shimokawa /* Probe link */ 515d0fd7bc6SHidetoshi Shimokawa reg = OREAD(sc, OHCI_BUS_OPT); 516d0fd7bc6SHidetoshi Shimokawa reg2 = reg | OHCI_BUSFNC; 51794b6f028SHidetoshi Shimokawa max_rec = (reg & 0x0000f000) >> 12; 51894b6f028SHidetoshi Shimokawa speed = (reg & 0x00000007); 51994b6f028SHidetoshi Shimokawa device_printf(dev, "Link %s, max_rec %d bytes.\n", 52094b6f028SHidetoshi Shimokawa linkspeed[speed], MAXREC(max_rec)); 52194b6f028SHidetoshi Shimokawa /* XXX fix max_rec */ 52294b6f028SHidetoshi Shimokawa sc->fc.maxrec = sc->fc.speed + 8; 52394b6f028SHidetoshi Shimokawa if (max_rec != sc->fc.maxrec) { 52494b6f028SHidetoshi Shimokawa reg2 = (reg2 & 0xffff0fff) | (sc->fc.maxrec << 12); 52594b6f028SHidetoshi Shimokawa device_printf(dev, "max_rec %d -> %d\n", 52694b6f028SHidetoshi Shimokawa MAXREC(max_rec), MAXREC(sc->fc.maxrec)); 52794b6f028SHidetoshi Shimokawa } 528d0fd7bc6SHidetoshi Shimokawa if (bootverbose) 529d0fd7bc6SHidetoshi Shimokawa device_printf(dev, "BUS_OPT 0x%x -> 0x%x\n", reg, reg2); 530d0fd7bc6SHidetoshi Shimokawa OWRITE(sc, OHCI_BUS_OPT, reg2); 531d0fd7bc6SHidetoshi Shimokawa 53294b6f028SHidetoshi Shimokawa /* Initialize registers */ 533d0fd7bc6SHidetoshi Shimokawa OWRITE(sc, OHCI_CROMHDR, sc->fc.config_rom[0]); 53477ee030bSHidetoshi Shimokawa OWRITE(sc, OHCI_CROMPTR, sc->crom_dma.bus_addr); 535d0fd7bc6SHidetoshi Shimokawa OWRITE(sc, OHCI_HCCCTLCLR, OHCI_HCC_BIGEND); 536d0fd7bc6SHidetoshi Shimokawa OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_POSTWR); 53777ee030bSHidetoshi Shimokawa OWRITE(sc, OHCI_SID_BUF, sc->sid_dma.bus_addr); 538d0fd7bc6SHidetoshi Shimokawa OWRITE(sc, OHCI_LNKCTL, OHCI_CNTL_SID); 539d0fd7bc6SHidetoshi Shimokawa fw_busreset(&sc->fc); 5409339321dSHidetoshi Shimokawa 54194b6f028SHidetoshi Shimokawa /* Enable link */ 54294b6f028SHidetoshi Shimokawa OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_LINKEN); 54394b6f028SHidetoshi Shimokawa 54494b6f028SHidetoshi Shimokawa /* Force to start async RX DMA */ 5459339321dSHidetoshi Shimokawa sc->arrq.xferq.flag &= ~FWXFERQ_RUNNING; 5469339321dSHidetoshi Shimokawa sc->arrs.xferq.flag &= ~FWXFERQ_RUNNING; 547d0fd7bc6SHidetoshi Shimokawa fwohci_rx_enable(sc, &sc->arrq); 548d0fd7bc6SHidetoshi Shimokawa fwohci_rx_enable(sc, &sc->arrs); 549d0fd7bc6SHidetoshi Shimokawa 55094b6f028SHidetoshi Shimokawa /* Initialize async TX */ 55194b6f028SHidetoshi Shimokawa OWRITE(sc, OHCI_ATQCTLCLR, OHCI_CNTL_DMA_RUN | OHCI_CNTL_DMA_DEAD); 55294b6f028SHidetoshi Shimokawa OWRITE(sc, OHCI_ATSCTLCLR, OHCI_CNTL_DMA_RUN | OHCI_CNTL_DMA_DEAD); 55394b6f028SHidetoshi Shimokawa /* AT Retries */ 55494b6f028SHidetoshi Shimokawa OWRITE(sc, FWOHCI_RETRY, 55594b6f028SHidetoshi Shimokawa /* CycleLimit PhyRespRetries ATRespRetries ATReqRetries */ 55694b6f028SHidetoshi Shimokawa (0xffff << 16 ) | (0x0f << 8) | (0x0f << 4) | 0x0f) ; 557d0fd7bc6SHidetoshi Shimokawa for( i = 0, db_tr = sc->atrq.top; i < sc->atrq.ndb ; 558d0fd7bc6SHidetoshi Shimokawa i ++, db_tr = STAILQ_NEXT(db_tr, link)){ 559d0fd7bc6SHidetoshi Shimokawa db_tr->xfer = NULL; 560d0fd7bc6SHidetoshi Shimokawa } 561d0fd7bc6SHidetoshi Shimokawa for( i = 0, db_tr = sc->atrs.top; i < sc->atrs.ndb ; 562d0fd7bc6SHidetoshi Shimokawa i ++, db_tr = STAILQ_NEXT(db_tr, link)){ 563d0fd7bc6SHidetoshi Shimokawa db_tr->xfer = NULL; 564d0fd7bc6SHidetoshi Shimokawa } 565d0fd7bc6SHidetoshi Shimokawa 56694b6f028SHidetoshi Shimokawa 56794b6f028SHidetoshi Shimokawa /* Enable interrupt */ 568d0fd7bc6SHidetoshi Shimokawa OWRITE(sc, FWOHCI_INTMASK, 569d0fd7bc6SHidetoshi Shimokawa OHCI_INT_ERR | OHCI_INT_PHY_SID 570d0fd7bc6SHidetoshi Shimokawa | OHCI_INT_DMA_ATRQ | OHCI_INT_DMA_ATRS 571d0fd7bc6SHidetoshi Shimokawa | OHCI_INT_DMA_PRRQ | OHCI_INT_DMA_PRRS 572d0fd7bc6SHidetoshi Shimokawa | OHCI_INT_PHY_BUS_R | OHCI_INT_PW_ERR); 573d0fd7bc6SHidetoshi Shimokawa fwohci_set_intr(&sc->fc, 1); 574d0fd7bc6SHidetoshi Shimokawa 575d0fd7bc6SHidetoshi Shimokawa } 576d0fd7bc6SHidetoshi Shimokawa 577d0fd7bc6SHidetoshi Shimokawa int 578d0fd7bc6SHidetoshi Shimokawa fwohci_init(struct fwohci_softc *sc, device_t dev) 579d0fd7bc6SHidetoshi Shimokawa { 580d0fd7bc6SHidetoshi Shimokawa int i; 581d0fd7bc6SHidetoshi Shimokawa u_int32_t reg; 582c547b896SHidetoshi Shimokawa u_int8_t ui[8]; 5833c60ba66SKatsushi Kobayashi 58477ee030bSHidetoshi Shimokawa #if FWOHCI_TASKQUEUE 58577ee030bSHidetoshi Shimokawa TASK_INIT(&sc->fwohci_task_complete, 0, fwohci_complete, sc); 58677ee030bSHidetoshi Shimokawa #endif 58777ee030bSHidetoshi Shimokawa 5883c60ba66SKatsushi Kobayashi reg = OREAD(sc, OHCI_VERSION); 5893c60ba66SKatsushi Kobayashi device_printf(dev, "OHCI version %x.%x (ROM=%d)\n", 5903c60ba66SKatsushi Kobayashi (reg>>16) & 0xff, reg & 0xff, (reg>>24) & 1); 5913c60ba66SKatsushi Kobayashi 5927054e848SHidetoshi Shimokawa /* Available Isochrounous DMA channel probe */ 5937054e848SHidetoshi Shimokawa OWRITE(sc, OHCI_IT_MASK, 0xffffffff); 5947054e848SHidetoshi Shimokawa OWRITE(sc, OHCI_IR_MASK, 0xffffffff); 5957054e848SHidetoshi Shimokawa reg = OREAD(sc, OHCI_IT_MASK) & OREAD(sc, OHCI_IR_MASK); 5967054e848SHidetoshi Shimokawa OWRITE(sc, OHCI_IT_MASKCLR, 0xffffffff); 5977054e848SHidetoshi Shimokawa OWRITE(sc, OHCI_IR_MASKCLR, 0xffffffff); 5987054e848SHidetoshi Shimokawa for (i = 0; i < 0x20; i++) 5997054e848SHidetoshi Shimokawa if ((reg & (1 << i)) == 0) 6007054e848SHidetoshi Shimokawa break; 6013c60ba66SKatsushi Kobayashi sc->fc.nisodma = i; 6023c60ba66SKatsushi Kobayashi device_printf(dev, "No. of Isochronous channel is %d.\n", i); 6033c60ba66SKatsushi Kobayashi 6043c60ba66SKatsushi Kobayashi sc->fc.arq = &sc->arrq.xferq; 6053c60ba66SKatsushi Kobayashi sc->fc.ars = &sc->arrs.xferq; 6063c60ba66SKatsushi Kobayashi sc->fc.atq = &sc->atrq.xferq; 6073c60ba66SKatsushi Kobayashi sc->fc.ats = &sc->atrs.xferq; 6083c60ba66SKatsushi Kobayashi 60977ee030bSHidetoshi Shimokawa sc->arrq.xferq.psize = roundup2(FWPMAX_S400, PAGE_SIZE); 61077ee030bSHidetoshi Shimokawa sc->arrs.xferq.psize = roundup2(FWPMAX_S400, PAGE_SIZE); 61177ee030bSHidetoshi Shimokawa sc->atrq.xferq.psize = roundup2(FWPMAX_S400, PAGE_SIZE); 61277ee030bSHidetoshi Shimokawa sc->atrs.xferq.psize = roundup2(FWPMAX_S400, PAGE_SIZE); 61377ee030bSHidetoshi Shimokawa 6143c60ba66SKatsushi Kobayashi sc->arrq.xferq.start = NULL; 6153c60ba66SKatsushi Kobayashi sc->arrs.xferq.start = NULL; 6163c60ba66SKatsushi Kobayashi sc->atrq.xferq.start = fwohci_start_atq; 6173c60ba66SKatsushi Kobayashi sc->atrs.xferq.start = fwohci_start_ats; 6183c60ba66SKatsushi Kobayashi 61977ee030bSHidetoshi Shimokawa sc->arrq.xferq.buf = NULL; 62077ee030bSHidetoshi Shimokawa sc->arrs.xferq.buf = NULL; 62177ee030bSHidetoshi Shimokawa sc->atrq.xferq.buf = NULL; 62277ee030bSHidetoshi Shimokawa sc->atrs.xferq.buf = NULL; 6233c60ba66SKatsushi Kobayashi 6243c60ba66SKatsushi Kobayashi sc->arrq.ndesc = 1; 6253c60ba66SKatsushi Kobayashi sc->arrs.ndesc = 1; 626645394e6SHidetoshi Shimokawa sc->atrq.ndesc = 8; /* equal to maximum of mbuf chains */ 627645394e6SHidetoshi Shimokawa sc->atrs.ndesc = 2; 6283c60ba66SKatsushi Kobayashi 6293c60ba66SKatsushi Kobayashi sc->arrq.ndb = NDB; 6303c60ba66SKatsushi Kobayashi sc->arrs.ndb = NDB / 2; 6313c60ba66SKatsushi Kobayashi sc->atrq.ndb = NDB; 6323c60ba66SKatsushi Kobayashi sc->atrs.ndb = NDB / 2; 6333c60ba66SKatsushi Kobayashi 6343c60ba66SKatsushi Kobayashi for( i = 0 ; i < sc->fc.nisodma ; i ++ ){ 6353c60ba66SKatsushi Kobayashi sc->fc.it[i] = &sc->it[i].xferq; 6363c60ba66SKatsushi Kobayashi sc->fc.ir[i] = &sc->ir[i].xferq; 6373c60ba66SKatsushi Kobayashi sc->it[i].ndb = 0; 6383c60ba66SKatsushi Kobayashi sc->ir[i].ndb = 0; 6393c60ba66SKatsushi Kobayashi } 6403c60ba66SKatsushi Kobayashi 6413c60ba66SKatsushi Kobayashi sc->fc.tcode = tinfo; 64277ee030bSHidetoshi Shimokawa sc->fc.dev = dev; 6433c60ba66SKatsushi Kobayashi 64477ee030bSHidetoshi Shimokawa sc->fc.config_rom = fwdma_malloc(&sc->fc, CROMSIZE, CROMSIZE, 64577ee030bSHidetoshi Shimokawa &sc->crom_dma, BUS_DMA_WAITOK); 64677ee030bSHidetoshi Shimokawa if(sc->fc.config_rom == NULL){ 64777ee030bSHidetoshi Shimokawa device_printf(dev, "config_rom alloc failed."); 6483c60ba66SKatsushi Kobayashi return ENOMEM; 6493c60ba66SKatsushi Kobayashi } 6503c60ba66SKatsushi Kobayashi 65177ee030bSHidetoshi Shimokawa #if 1 6523c60ba66SKatsushi Kobayashi sc->fc.config_rom[1] = 0x31333934; 6533c60ba66SKatsushi Kobayashi sc->fc.config_rom[2] = 0xf000a002; 6543c60ba66SKatsushi Kobayashi sc->fc.config_rom[3] = OREAD(sc, OHCI_EUID_HI); 6553c60ba66SKatsushi Kobayashi sc->fc.config_rom[4] = OREAD(sc, OHCI_EUID_LO); 6563c60ba66SKatsushi Kobayashi sc->fc.config_rom[5] = 0; 6573c60ba66SKatsushi Kobayashi sc->fc.config_rom[0] = (4 << 24) | (5 << 16); 6583c60ba66SKatsushi Kobayashi 6593c60ba66SKatsushi Kobayashi sc->fc.config_rom[0] |= fw_crc16(&sc->fc.config_rom[1], 5*4); 66077ee030bSHidetoshi Shimokawa #endif 6613c60ba66SKatsushi Kobayashi 6623c60ba66SKatsushi Kobayashi 6633c60ba66SKatsushi Kobayashi /* SID recieve buffer must allign 2^11 */ 6643c60ba66SKatsushi Kobayashi #define OHCI_SIDSIZE (1 << 11) 66577ee030bSHidetoshi Shimokawa sc->sid_buf = fwdma_malloc(&sc->fc, OHCI_SIDSIZE, OHCI_SIDSIZE, 66677ee030bSHidetoshi Shimokawa &sc->sid_dma, BUS_DMA_WAITOK); 66777ee030bSHidetoshi Shimokawa if (sc->sid_buf == NULL) { 66877ee030bSHidetoshi Shimokawa device_printf(dev, "sid_buf alloc failed."); 66916e0f484SHidetoshi Shimokawa return ENOMEM; 67016e0f484SHidetoshi Shimokawa } 6713c60ba66SKatsushi Kobayashi 67277ee030bSHidetoshi Shimokawa fwdma_malloc(&sc->fc, sizeof(u_int32_t), sizeof(u_int32_t), 67377ee030bSHidetoshi Shimokawa &sc->dummy_dma, BUS_DMA_WAITOK); 67477ee030bSHidetoshi Shimokawa 67577ee030bSHidetoshi Shimokawa if (sc->dummy_dma.v_addr == NULL) { 67677ee030bSHidetoshi Shimokawa device_printf(dev, "dummy_dma alloc failed."); 67777ee030bSHidetoshi Shimokawa return ENOMEM; 67877ee030bSHidetoshi Shimokawa } 67977ee030bSHidetoshi Shimokawa 68077ee030bSHidetoshi Shimokawa fwohci_db_init(sc, &sc->arrq); 6811f2361f8SHidetoshi Shimokawa if ((sc->arrq.flags & FWOHCI_DBCH_INIT) == 0) 6821f2361f8SHidetoshi Shimokawa return ENOMEM; 6831f2361f8SHidetoshi Shimokawa 68477ee030bSHidetoshi Shimokawa fwohci_db_init(sc, &sc->arrs); 6851f2361f8SHidetoshi Shimokawa if ((sc->arrs.flags & FWOHCI_DBCH_INIT) == 0) 6861f2361f8SHidetoshi Shimokawa return ENOMEM; 6873c60ba66SKatsushi Kobayashi 68877ee030bSHidetoshi Shimokawa fwohci_db_init(sc, &sc->atrq); 6891f2361f8SHidetoshi Shimokawa if ((sc->atrq.flags & FWOHCI_DBCH_INIT) == 0) 6901f2361f8SHidetoshi Shimokawa return ENOMEM; 6911f2361f8SHidetoshi Shimokawa 69277ee030bSHidetoshi Shimokawa fwohci_db_init(sc, &sc->atrs); 6931f2361f8SHidetoshi Shimokawa if ((sc->atrs.flags & FWOHCI_DBCH_INIT) == 0) 6941f2361f8SHidetoshi Shimokawa return ENOMEM; 6953c60ba66SKatsushi Kobayashi 696c547b896SHidetoshi Shimokawa sc->fc.eui.hi = OREAD(sc, FWOHCIGUID_H); 697c547b896SHidetoshi Shimokawa sc->fc.eui.lo = OREAD(sc, FWOHCIGUID_L); 698c547b896SHidetoshi Shimokawa for( i = 0 ; i < 8 ; i ++) 699c547b896SHidetoshi Shimokawa ui[i] = FW_EUI64_BYTE(&sc->fc.eui,i); 7003c60ba66SKatsushi Kobayashi device_printf(dev, "EUI64 %02x:%02x:%02x:%02x:%02x:%02x:%02x:%02x\n", 701c547b896SHidetoshi Shimokawa ui[0], ui[1], ui[2], ui[3], ui[4], ui[5], ui[6], ui[7]); 702c547b896SHidetoshi Shimokawa 7033c60ba66SKatsushi Kobayashi sc->fc.ioctl = fwohci_ioctl; 7043c60ba66SKatsushi Kobayashi sc->fc.cyctimer = fwohci_cyctimer; 7053c60ba66SKatsushi Kobayashi sc->fc.set_bmr = fwohci_set_bus_manager; 7063c60ba66SKatsushi Kobayashi sc->fc.ibr = fwohci_ibr; 7073c60ba66SKatsushi Kobayashi sc->fc.irx_enable = fwohci_irx_enable; 7083c60ba66SKatsushi Kobayashi sc->fc.irx_disable = fwohci_irx_disable; 7093c60ba66SKatsushi Kobayashi 7103c60ba66SKatsushi Kobayashi sc->fc.itx_enable = fwohci_itxbuf_enable; 7113c60ba66SKatsushi Kobayashi sc->fc.itx_disable = fwohci_itx_disable; 71277ee030bSHidetoshi Shimokawa #if BYTE_ORDER == BIG_ENDIAN 7133c60ba66SKatsushi Kobayashi sc->fc.irx_post = fwohci_irx_post; 71477ee030bSHidetoshi Shimokawa #else 71577ee030bSHidetoshi Shimokawa sc->fc.irx_post = NULL; 71677ee030bSHidetoshi Shimokawa #endif 7173c60ba66SKatsushi Kobayashi sc->fc.itx_post = NULL; 7183c60ba66SKatsushi Kobayashi sc->fc.timeout = fwohci_timeout; 7193c60ba66SKatsushi Kobayashi sc->fc.poll = fwohci_poll; 7203c60ba66SKatsushi Kobayashi sc->fc.set_intr = fwohci_set_intr; 721c572b810SHidetoshi Shimokawa 72277ee030bSHidetoshi Shimokawa sc->intmask = sc->irstat = sc->itstat = 0; 72377ee030bSHidetoshi Shimokawa 724d0fd7bc6SHidetoshi Shimokawa fw_init(&sc->fc); 725d0fd7bc6SHidetoshi Shimokawa fwohci_reset(sc, dev); 7263c60ba66SKatsushi Kobayashi 727d0fd7bc6SHidetoshi Shimokawa return 0; 7283c60ba66SKatsushi Kobayashi } 729c572b810SHidetoshi Shimokawa 730c572b810SHidetoshi Shimokawa void 731c572b810SHidetoshi Shimokawa fwohci_timeout(void *arg) 7323c60ba66SKatsushi Kobayashi { 7333c60ba66SKatsushi Kobayashi struct fwohci_softc *sc; 7343c60ba66SKatsushi Kobayashi 7353c60ba66SKatsushi Kobayashi sc = (struct fwohci_softc *)arg; 7363c60ba66SKatsushi Kobayashi } 737c572b810SHidetoshi Shimokawa 738c572b810SHidetoshi Shimokawa u_int32_t 739c572b810SHidetoshi Shimokawa fwohci_cyctimer(struct firewire_comm *fc) 7403c60ba66SKatsushi Kobayashi { 7413c60ba66SKatsushi Kobayashi struct fwohci_softc *sc = (struct fwohci_softc *)fc; 7423c60ba66SKatsushi Kobayashi return(OREAD(sc, OHCI_CYCLETIMER)); 7433c60ba66SKatsushi Kobayashi } 7443c60ba66SKatsushi Kobayashi 7451f2361f8SHidetoshi Shimokawa int 7461f2361f8SHidetoshi Shimokawa fwohci_detach(struct fwohci_softc *sc, device_t dev) 7471f2361f8SHidetoshi Shimokawa { 7481f2361f8SHidetoshi Shimokawa int i; 7491f2361f8SHidetoshi Shimokawa 75077ee030bSHidetoshi Shimokawa if (sc->sid_buf != NULL) 75177ee030bSHidetoshi Shimokawa fwdma_free(&sc->fc, &sc->sid_dma); 75277ee030bSHidetoshi Shimokawa if (sc->fc.config_rom != NULL) 75377ee030bSHidetoshi Shimokawa fwdma_free(&sc->fc, &sc->crom_dma); 7541f2361f8SHidetoshi Shimokawa 7551f2361f8SHidetoshi Shimokawa fwohci_db_free(&sc->arrq); 7561f2361f8SHidetoshi Shimokawa fwohci_db_free(&sc->arrs); 7571f2361f8SHidetoshi Shimokawa 7581f2361f8SHidetoshi Shimokawa fwohci_db_free(&sc->atrq); 7591f2361f8SHidetoshi Shimokawa fwohci_db_free(&sc->atrs); 7601f2361f8SHidetoshi Shimokawa 7611f2361f8SHidetoshi Shimokawa for( i = 0 ; i < sc->fc.nisodma ; i ++ ){ 7621f2361f8SHidetoshi Shimokawa fwohci_db_free(&sc->it[i]); 7631f2361f8SHidetoshi Shimokawa fwohci_db_free(&sc->ir[i]); 7641f2361f8SHidetoshi Shimokawa } 7651f2361f8SHidetoshi Shimokawa 7661f2361f8SHidetoshi Shimokawa return 0; 7671f2361f8SHidetoshi Shimokawa } 7681f2361f8SHidetoshi Shimokawa 769d6105b60SHidetoshi Shimokawa #define LAST_DB(dbtr, db) do { \ 770d6105b60SHidetoshi Shimokawa struct fwohcidb_tr *_dbtr = (dbtr); \ 771d6105b60SHidetoshi Shimokawa int _cnt = _dbtr->dbcnt; \ 772d6105b60SHidetoshi Shimokawa db = &_dbtr->db[ (_cnt > 2) ? (_cnt -1) : 0]; \ 773d6105b60SHidetoshi Shimokawa } while (0) 774d6105b60SHidetoshi Shimokawa 775c572b810SHidetoshi Shimokawa static void 77677ee030bSHidetoshi Shimokawa fwohci_execute_db(void *arg, bus_dma_segment_t *segs, int nseg, int error) 77777ee030bSHidetoshi Shimokawa { 77877ee030bSHidetoshi Shimokawa struct fwohcidb_tr *db_tr; 77977ee030bSHidetoshi Shimokawa volatile struct fwohcidb *db; 78077ee030bSHidetoshi Shimokawa bus_dma_segment_t *s; 78177ee030bSHidetoshi Shimokawa int i; 78277ee030bSHidetoshi Shimokawa 78377ee030bSHidetoshi Shimokawa db_tr = (struct fwohcidb_tr *)arg; 78477ee030bSHidetoshi Shimokawa db = &db_tr->db[db_tr->dbcnt]; 78577ee030bSHidetoshi Shimokawa if (error) { 78677ee030bSHidetoshi Shimokawa if (firewire_debug || error != EFBIG) 78777ee030bSHidetoshi Shimokawa printf("fwohci_execute_db: error=%d\n", error); 78877ee030bSHidetoshi Shimokawa return; 78977ee030bSHidetoshi Shimokawa } 79077ee030bSHidetoshi Shimokawa for (i = 0; i < nseg; i++) { 79177ee030bSHidetoshi Shimokawa s = &segs[i]; 79277ee030bSHidetoshi Shimokawa FWOHCI_DMA_WRITE(db->db.desc.addr, s->ds_addr); 79377ee030bSHidetoshi Shimokawa FWOHCI_DMA_WRITE(db->db.desc.cmd, s->ds_len); 79477ee030bSHidetoshi Shimokawa FWOHCI_DMA_WRITE(db->db.desc.res, 0); 79577ee030bSHidetoshi Shimokawa db++; 79677ee030bSHidetoshi Shimokawa db_tr->dbcnt++; 79777ee030bSHidetoshi Shimokawa } 79877ee030bSHidetoshi Shimokawa } 79977ee030bSHidetoshi Shimokawa 80077ee030bSHidetoshi Shimokawa static void 80177ee030bSHidetoshi Shimokawa fwohci_execute_db2(void *arg, bus_dma_segment_t *segs, int nseg, 80277ee030bSHidetoshi Shimokawa bus_size_t size, int error) 80377ee030bSHidetoshi Shimokawa { 80477ee030bSHidetoshi Shimokawa fwohci_execute_db(arg, segs, nseg, error); 80577ee030bSHidetoshi Shimokawa } 80677ee030bSHidetoshi Shimokawa 80777ee030bSHidetoshi Shimokawa static void 808c572b810SHidetoshi Shimokawa fwohci_start(struct fwohci_softc *sc, struct fwohci_dbch *dbch) 8093c60ba66SKatsushi Kobayashi { 8103c60ba66SKatsushi Kobayashi int i, s; 81177ee030bSHidetoshi Shimokawa int tcode, hdr_len, pl_off, pl_len; 8123c60ba66SKatsushi Kobayashi int fsegment = -1; 8133c60ba66SKatsushi Kobayashi u_int32_t off; 8143c60ba66SKatsushi Kobayashi struct fw_xfer *xfer; 8153c60ba66SKatsushi Kobayashi struct fw_pkt *fp; 8163c60ba66SKatsushi Kobayashi volatile struct fwohci_txpkthdr *ohcifp; 8173c60ba66SKatsushi Kobayashi struct fwohcidb_tr *db_tr; 8183c60ba66SKatsushi Kobayashi volatile struct fwohcidb *db; 8193c60ba66SKatsushi Kobayashi struct tcode_info *info; 820d6105b60SHidetoshi Shimokawa static int maxdesc=0; 8213c60ba66SKatsushi Kobayashi 8223c60ba66SKatsushi Kobayashi if(&sc->atrq == dbch){ 8233c60ba66SKatsushi Kobayashi off = OHCI_ATQOFF; 8243c60ba66SKatsushi Kobayashi }else if(&sc->atrs == dbch){ 8253c60ba66SKatsushi Kobayashi off = OHCI_ATSOFF; 8263c60ba66SKatsushi Kobayashi }else{ 8273c60ba66SKatsushi Kobayashi return; 8283c60ba66SKatsushi Kobayashi } 8293c60ba66SKatsushi Kobayashi 8303c60ba66SKatsushi Kobayashi if (dbch->flags & FWOHCI_DBCH_FULL) 8313c60ba66SKatsushi Kobayashi return; 8323c60ba66SKatsushi Kobayashi 8333c60ba66SKatsushi Kobayashi s = splfw(); 8343c60ba66SKatsushi Kobayashi db_tr = dbch->top; 8353c60ba66SKatsushi Kobayashi txloop: 8363c60ba66SKatsushi Kobayashi xfer = STAILQ_FIRST(&dbch->xferq.q); 8373c60ba66SKatsushi Kobayashi if(xfer == NULL){ 8383c60ba66SKatsushi Kobayashi goto kick; 8393c60ba66SKatsushi Kobayashi } 8403c60ba66SKatsushi Kobayashi if(dbch->xferq.queued == 0 ){ 8413c60ba66SKatsushi Kobayashi device_printf(sc->fc.dev, "TX queue empty\n"); 8423c60ba66SKatsushi Kobayashi } 8433c60ba66SKatsushi Kobayashi STAILQ_REMOVE_HEAD(&dbch->xferq.q, link); 8443c60ba66SKatsushi Kobayashi db_tr->xfer = xfer; 8453c60ba66SKatsushi Kobayashi xfer->state = FWXF_START; 8463c60ba66SKatsushi Kobayashi 84777ee030bSHidetoshi Shimokawa fp = (struct fw_pkt *)xfer->send.buf; 8483c60ba66SKatsushi Kobayashi tcode = fp->mode.common.tcode; 8493c60ba66SKatsushi Kobayashi 8503c60ba66SKatsushi Kobayashi ohcifp = (volatile struct fwohci_txpkthdr *) db_tr->db[1].db.immed; 8513c60ba66SKatsushi Kobayashi info = &tinfo[tcode]; 85277ee030bSHidetoshi Shimokawa hdr_len = pl_off = info->hdr_len; 85377ee030bSHidetoshi Shimokawa for( i = 0 ; i < pl_off ; i+= 4){ 85477ee030bSHidetoshi Shimokawa ohcifp->mode.ld[i/4] = fp->mode.ld[i/4]; 85573aa55baSHidetoshi Shimokawa } 8563c60ba66SKatsushi Kobayashi ohcifp->mode.common.spd = xfer->spd; 8573c60ba66SKatsushi Kobayashi if (tcode == FWTCODE_STREAM ){ 8583c60ba66SKatsushi Kobayashi hdr_len = 8; 85977ee030bSHidetoshi Shimokawa ohcifp->mode.stream.len = fp->mode.stream.len; 8603c60ba66SKatsushi Kobayashi } else if (tcode == FWTCODE_PHY) { 8613c60ba66SKatsushi Kobayashi hdr_len = 12; 86277ee030bSHidetoshi Shimokawa ohcifp->mode.ld[1] = fp->mode.ld[1]; 86377ee030bSHidetoshi Shimokawa ohcifp->mode.ld[2] = fp->mode.ld[2]; 8643c60ba66SKatsushi Kobayashi ohcifp->mode.common.spd = 0; 8653c60ba66SKatsushi Kobayashi ohcifp->mode.common.tcode = FWOHCITCODE_PHY; 8663c60ba66SKatsushi Kobayashi } else { 86777ee030bSHidetoshi Shimokawa ohcifp->mode.asycomm.dst = fp->mode.hdr.dst; 8683c60ba66SKatsushi Kobayashi ohcifp->mode.asycomm.srcbus = OHCI_ASYSRCBUS; 8693c60ba66SKatsushi Kobayashi ohcifp->mode.asycomm.tlrt |= FWRETRY_X; 8703c60ba66SKatsushi Kobayashi } 8713c60ba66SKatsushi Kobayashi db = &db_tr->db[0]; 87277ee030bSHidetoshi Shimokawa FWOHCI_DMA_WRITE(db->db.desc.cmd, 87377ee030bSHidetoshi Shimokawa OHCI_OUTPUT_MORE | OHCI_KEY_ST2 | hdr_len); 87477ee030bSHidetoshi Shimokawa FWOHCI_DMA_WRITE(db->db.desc.res, 0); 8753c60ba66SKatsushi Kobayashi /* Specify bound timer of asy. responce */ 8763c60ba66SKatsushi Kobayashi if(&sc->atrs == dbch){ 87777ee030bSHidetoshi Shimokawa FWOHCI_DMA_WRITE(db->db.desc.res, 87877ee030bSHidetoshi Shimokawa (OREAD(sc, OHCI_CYCLETIMER) >> 12) + (1 << 13)); 8793c60ba66SKatsushi Kobayashi } 88077ee030bSHidetoshi Shimokawa #if BYTE_ORDER == BIG_ENDIAN 88177ee030bSHidetoshi Shimokawa if (tcode == FWTCODE_WREQQ || tcode == FWTCODE_RRESQ) 88277ee030bSHidetoshi Shimokawa hdr_len = 12; 88377ee030bSHidetoshi Shimokawa for (i = 0; i < hdr_len/4; i ++) 88477ee030bSHidetoshi Shimokawa FWOHCI_DMA_WRITE(ohcifp->mode.ld[i], ohcifp->mode.ld[i]); 88577ee030bSHidetoshi Shimokawa #endif 8863c60ba66SKatsushi Kobayashi 8872b4601d1SHidetoshi Shimokawa again: 8883c60ba66SKatsushi Kobayashi db_tr->dbcnt = 2; 8893c60ba66SKatsushi Kobayashi db = &db_tr->db[db_tr->dbcnt]; 89077ee030bSHidetoshi Shimokawa pl_len = xfer->send.len - pl_off; 89177ee030bSHidetoshi Shimokawa if (pl_len > 0) { 89277ee030bSHidetoshi Shimokawa int err; 89377ee030bSHidetoshi Shimokawa /* handle payload */ 8943c60ba66SKatsushi Kobayashi if (xfer->mbuf == NULL) { 89577ee030bSHidetoshi Shimokawa caddr_t pl_addr; 8963c60ba66SKatsushi Kobayashi 89777ee030bSHidetoshi Shimokawa pl_addr = xfer->send.buf + pl_off; 89877ee030bSHidetoshi Shimokawa err = bus_dmamap_load(dbch->dmat, db_tr->dma_map, 89977ee030bSHidetoshi Shimokawa pl_addr, pl_len, 90077ee030bSHidetoshi Shimokawa fwohci_execute_db, db_tr, 90177ee030bSHidetoshi Shimokawa /*flags*/0); 9023c60ba66SKatsushi Kobayashi } else { 9032b4601d1SHidetoshi Shimokawa /* XXX we can handle only 6 (=8-2) mbuf chains */ 90477ee030bSHidetoshi Shimokawa err = bus_dmamap_load_mbuf(dbch->dmat, db_tr->dma_map, 90577ee030bSHidetoshi Shimokawa xfer->mbuf, 90677ee030bSHidetoshi Shimokawa fwohci_execute_db2, db_tr, 90777ee030bSHidetoshi Shimokawa /* flags */0); 90877ee030bSHidetoshi Shimokawa if (err == EFBIG) { 90977ee030bSHidetoshi Shimokawa struct mbuf *m0; 91077ee030bSHidetoshi Shimokawa 91177ee030bSHidetoshi Shimokawa if (firewire_debug) 91277ee030bSHidetoshi Shimokawa device_printf(sc->fc.dev, "EFBIG.\n"); 91377ee030bSHidetoshi Shimokawa m0 = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 91477ee030bSHidetoshi Shimokawa if (m0 != NULL) { 9152b4601d1SHidetoshi Shimokawa m_copydata(xfer->mbuf, 0, 9162b4601d1SHidetoshi Shimokawa xfer->mbuf->m_pkthdr.len, 91777ee030bSHidetoshi Shimokawa mtod(m0, caddr_t)); 91877ee030bSHidetoshi Shimokawa m0->m_len = m0->m_pkthdr.len = 9192b4601d1SHidetoshi Shimokawa xfer->mbuf->m_pkthdr.len; 9202b4601d1SHidetoshi Shimokawa m_freem(xfer->mbuf); 92177ee030bSHidetoshi Shimokawa xfer->mbuf = m0; 9222b4601d1SHidetoshi Shimokawa goto again; 9232b4601d1SHidetoshi Shimokawa } 9242b4601d1SHidetoshi Shimokawa device_printf(sc->fc.dev, "m_getcl failed.\n"); 9252b4601d1SHidetoshi Shimokawa } 9263c60ba66SKatsushi Kobayashi } 92777ee030bSHidetoshi Shimokawa if (err) 92877ee030bSHidetoshi Shimokawa printf("dmamap_load: err=%d\n", err); 92977ee030bSHidetoshi Shimokawa bus_dmamap_sync(dbch->dmat, db_tr->dma_map, 93077ee030bSHidetoshi Shimokawa BUS_DMASYNC_PREWRITE); 93177ee030bSHidetoshi Shimokawa #if 0 /* OHCI_OUTPUT_MODE == 0 */ 93277ee030bSHidetoshi Shimokawa for (i = 2; i < db_tr->dbcnt; i++) 93377ee030bSHidetoshi Shimokawa FWOHCI_DMA_SET(db_tr->db[i].db.desc.cmd, 93477ee030bSHidetoshi Shimokawa OHCI_OUTPUT_MORE); 93577ee030bSHidetoshi Shimokawa #endif 936d6105b60SHidetoshi Shimokawa } 937d6105b60SHidetoshi Shimokawa if (maxdesc < db_tr->dbcnt) { 938d6105b60SHidetoshi Shimokawa maxdesc = db_tr->dbcnt; 939d6105b60SHidetoshi Shimokawa if (bootverbose) 940d6105b60SHidetoshi Shimokawa device_printf(sc->fc.dev, "maxdesc: %d\n", maxdesc); 941d6105b60SHidetoshi Shimokawa } 9423c60ba66SKatsushi Kobayashi /* last db */ 9433c60ba66SKatsushi Kobayashi LAST_DB(db_tr, db); 94477ee030bSHidetoshi Shimokawa FWOHCI_DMA_SET(db->db.desc.cmd, 94577ee030bSHidetoshi Shimokawa OHCI_OUTPUT_LAST | OHCI_INTERRUPT_ALWAYS | OHCI_BRANCH_ALWAYS); 94677ee030bSHidetoshi Shimokawa FWOHCI_DMA_WRITE(db->db.desc.depend, 94777ee030bSHidetoshi Shimokawa STAILQ_NEXT(db_tr, link)->bus_addr); 9483c60ba66SKatsushi Kobayashi 9493c60ba66SKatsushi Kobayashi if(fsegment == -1 ) 9503c60ba66SKatsushi Kobayashi fsegment = db_tr->dbcnt; 9513c60ba66SKatsushi Kobayashi if (dbch->pdb_tr != NULL) { 9523c60ba66SKatsushi Kobayashi LAST_DB(dbch->pdb_tr, db); 95377ee030bSHidetoshi Shimokawa FWOHCI_DMA_SET(db->db.desc.depend, db_tr->dbcnt); 9543c60ba66SKatsushi Kobayashi } 9553c60ba66SKatsushi Kobayashi dbch->pdb_tr = db_tr; 9563c60ba66SKatsushi Kobayashi db_tr = STAILQ_NEXT(db_tr, link); 9573c60ba66SKatsushi Kobayashi if(db_tr != dbch->bottom){ 9583c60ba66SKatsushi Kobayashi goto txloop; 9593c60ba66SKatsushi Kobayashi } else { 96017c3d42cSHidetoshi Shimokawa device_printf(sc->fc.dev, "fwohci_start: lack of db_trq\n"); 9613c60ba66SKatsushi Kobayashi dbch->flags |= FWOHCI_DBCH_FULL; 9623c60ba66SKatsushi Kobayashi } 9633c60ba66SKatsushi Kobayashi kick: 9643c60ba66SKatsushi Kobayashi /* kick asy q */ 96577ee030bSHidetoshi Shimokawa fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREREAD); 96677ee030bSHidetoshi Shimokawa fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREWRITE); 9673c60ba66SKatsushi Kobayashi 9683c60ba66SKatsushi Kobayashi if(dbch->xferq.flag & FWXFERQ_RUNNING) { 9693c60ba66SKatsushi Kobayashi OWRITE(sc, OHCI_DMACTL(off), OHCI_CNTL_DMA_WAKE); 9703c60ba66SKatsushi Kobayashi } else { 97117c3d42cSHidetoshi Shimokawa if (bootverbose) 97217c3d42cSHidetoshi Shimokawa device_printf(sc->fc.dev, "start AT DMA status=%x\n", 9733c60ba66SKatsushi Kobayashi OREAD(sc, OHCI_DMACTL(off))); 97477ee030bSHidetoshi Shimokawa OWRITE(sc, OHCI_DMACMD(off), dbch->top->bus_addr | fsegment); 9753c60ba66SKatsushi Kobayashi OWRITE(sc, OHCI_DMACTL(off), OHCI_CNTL_DMA_RUN); 9763c60ba66SKatsushi Kobayashi dbch->xferq.flag |= FWXFERQ_RUNNING; 9773c60ba66SKatsushi Kobayashi } 978c572b810SHidetoshi Shimokawa 9793c60ba66SKatsushi Kobayashi dbch->top = db_tr; 9803c60ba66SKatsushi Kobayashi splx(s); 9813c60ba66SKatsushi Kobayashi return; 9823c60ba66SKatsushi Kobayashi } 983c572b810SHidetoshi Shimokawa 984c572b810SHidetoshi Shimokawa static void 985c572b810SHidetoshi Shimokawa fwohci_start_atq(struct firewire_comm *fc) 9863c60ba66SKatsushi Kobayashi { 9873c60ba66SKatsushi Kobayashi struct fwohci_softc *sc = (struct fwohci_softc *)fc; 9883c60ba66SKatsushi Kobayashi fwohci_start( sc, &(sc->atrq)); 9893c60ba66SKatsushi Kobayashi return; 9903c60ba66SKatsushi Kobayashi } 991c572b810SHidetoshi Shimokawa 992c572b810SHidetoshi Shimokawa static void 993c572b810SHidetoshi Shimokawa fwohci_start_ats(struct firewire_comm *fc) 9943c60ba66SKatsushi Kobayashi { 9953c60ba66SKatsushi Kobayashi struct fwohci_softc *sc = (struct fwohci_softc *)fc; 9963c60ba66SKatsushi Kobayashi fwohci_start( sc, &(sc->atrs)); 9973c60ba66SKatsushi Kobayashi return; 9983c60ba66SKatsushi Kobayashi } 999c572b810SHidetoshi Shimokawa 1000c572b810SHidetoshi Shimokawa void 1001c572b810SHidetoshi Shimokawa fwohci_txd(struct fwohci_softc *sc, struct fwohci_dbch *dbch) 10023c60ba66SKatsushi Kobayashi { 100377ee030bSHidetoshi Shimokawa int s, ch, err = 0; 10043c60ba66SKatsushi Kobayashi struct fwohcidb_tr *tr; 10053c60ba66SKatsushi Kobayashi volatile struct fwohcidb *db; 10063c60ba66SKatsushi Kobayashi struct fw_xfer *xfer; 10073c60ba66SKatsushi Kobayashi u_int32_t off; 100877ee030bSHidetoshi Shimokawa u_int stat, status; 10093c60ba66SKatsushi Kobayashi int packets; 10103c60ba66SKatsushi Kobayashi struct firewire_comm *fc = (struct firewire_comm *)sc; 101177ee030bSHidetoshi Shimokawa 10123c60ba66SKatsushi Kobayashi if(&sc->atrq == dbch){ 10133c60ba66SKatsushi Kobayashi off = OHCI_ATQOFF; 101477ee030bSHidetoshi Shimokawa ch = ATRQ_CH; 10153c60ba66SKatsushi Kobayashi }else if(&sc->atrs == dbch){ 10163c60ba66SKatsushi Kobayashi off = OHCI_ATSOFF; 101777ee030bSHidetoshi Shimokawa ch = ATRS_CH; 10183c60ba66SKatsushi Kobayashi }else{ 10193c60ba66SKatsushi Kobayashi return; 10203c60ba66SKatsushi Kobayashi } 10213c60ba66SKatsushi Kobayashi s = splfw(); 10223c60ba66SKatsushi Kobayashi tr = dbch->bottom; 10233c60ba66SKatsushi Kobayashi packets = 0; 102477ee030bSHidetoshi Shimokawa fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_POSTREAD); 102577ee030bSHidetoshi Shimokawa fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_POSTWRITE); 10263c60ba66SKatsushi Kobayashi while(dbch->xferq.queued > 0){ 10273c60ba66SKatsushi Kobayashi LAST_DB(tr, db); 102877ee030bSHidetoshi Shimokawa status = FWOHCI_DMA_READ(db->db.desc.res) >> OHCI_STATUS_SHIFT; 102977ee030bSHidetoshi Shimokawa if(!(status & OHCI_CNTL_DMA_ACTIVE)){ 10303c60ba66SKatsushi Kobayashi if (fc->status != FWBUSRESET) 10313c60ba66SKatsushi Kobayashi /* maybe out of order?? */ 10323c60ba66SKatsushi Kobayashi goto out; 10333c60ba66SKatsushi Kobayashi } 103477ee030bSHidetoshi Shimokawa bus_dmamap_sync(dbch->dmat, tr->dma_map, 103577ee030bSHidetoshi Shimokawa BUS_DMASYNC_POSTWRITE); 103677ee030bSHidetoshi Shimokawa bus_dmamap_unload(dbch->dmat, tr->dma_map); 103777ee030bSHidetoshi Shimokawa #if 0 10383c60ba66SKatsushi Kobayashi dump_db(sc, ch); 10393c60ba66SKatsushi Kobayashi #endif 104077ee030bSHidetoshi Shimokawa if(status & OHCI_CNTL_DMA_DEAD) { 10413c60ba66SKatsushi Kobayashi /* Stop DMA */ 10423c60ba66SKatsushi Kobayashi OWRITE(sc, OHCI_DMACTLCLR(off), OHCI_CNTL_DMA_RUN); 10433c60ba66SKatsushi Kobayashi device_printf(sc->fc.dev, "force reset AT FIFO\n"); 10443c60ba66SKatsushi Kobayashi OWRITE(sc, OHCI_HCCCTLCLR, OHCI_HCC_LINKEN); 10453c60ba66SKatsushi Kobayashi OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_LPS | OHCI_HCC_LINKEN); 10463c60ba66SKatsushi Kobayashi OWRITE(sc, OHCI_DMACTLCLR(off), OHCI_CNTL_DMA_RUN); 10473c60ba66SKatsushi Kobayashi } 104877ee030bSHidetoshi Shimokawa stat = status & FWOHCIEV_MASK; 10493c60ba66SKatsushi Kobayashi switch(stat){ 10503c60ba66SKatsushi Kobayashi case FWOHCIEV_ACKPEND: 1051864d7e72SHidetoshi Shimokawa case FWOHCIEV_ACKCOMPL: 10523c60ba66SKatsushi Kobayashi err = 0; 10533c60ba66SKatsushi Kobayashi break; 10543c60ba66SKatsushi Kobayashi case FWOHCIEV_ACKBSA: 10553c60ba66SKatsushi Kobayashi case FWOHCIEV_ACKBSB: 10563c60ba66SKatsushi Kobayashi case FWOHCIEV_ACKBSX: 1057864d7e72SHidetoshi Shimokawa device_printf(sc->fc.dev, "txd err=%2x %s\n", stat, fwohcicode[stat]); 10583c60ba66SKatsushi Kobayashi err = EBUSY; 10593c60ba66SKatsushi Kobayashi break; 10603c60ba66SKatsushi Kobayashi case FWOHCIEV_FLUSHED: 10613c60ba66SKatsushi Kobayashi case FWOHCIEV_ACKTARD: 10623c60ba66SKatsushi Kobayashi device_printf(sc->fc.dev, "txd err=%2x %s\n", stat, fwohcicode[stat]); 10633c60ba66SKatsushi Kobayashi err = EAGAIN; 10643c60ba66SKatsushi Kobayashi break; 10653c60ba66SKatsushi Kobayashi case FWOHCIEV_MISSACK: 10663c60ba66SKatsushi Kobayashi case FWOHCIEV_UNDRRUN: 10673c60ba66SKatsushi Kobayashi case FWOHCIEV_OVRRUN: 10683c60ba66SKatsushi Kobayashi case FWOHCIEV_DESCERR: 10693c60ba66SKatsushi Kobayashi case FWOHCIEV_DTRDERR: 10703c60ba66SKatsushi Kobayashi case FWOHCIEV_TIMEOUT: 10713c60ba66SKatsushi Kobayashi case FWOHCIEV_TCODERR: 10723c60ba66SKatsushi Kobayashi case FWOHCIEV_UNKNOWN: 10733c60ba66SKatsushi Kobayashi case FWOHCIEV_ACKDERR: 10743c60ba66SKatsushi Kobayashi case FWOHCIEV_ACKTERR: 10753c60ba66SKatsushi Kobayashi default: 10763c60ba66SKatsushi Kobayashi device_printf(sc->fc.dev, "txd err=%2x %s\n", 10773c60ba66SKatsushi Kobayashi stat, fwohcicode[stat]); 10783c60ba66SKatsushi Kobayashi err = EINVAL; 10793c60ba66SKatsushi Kobayashi break; 10803c60ba66SKatsushi Kobayashi } 10813c60ba66SKatsushi Kobayashi if (tr->xfer != NULL) { 10823c60ba66SKatsushi Kobayashi xfer = tr->xfer; 108377ee030bSHidetoshi Shimokawa if (xfer->state == FWXF_RCVD) { 108477ee030bSHidetoshi Shimokawa if (firewire_debug) 108577ee030bSHidetoshi Shimokawa printf("already rcvd\n"); 108677ee030bSHidetoshi Shimokawa fw_xfer_done(xfer); 108777ee030bSHidetoshi Shimokawa } else { 10883c60ba66SKatsushi Kobayashi xfer->state = FWXF_SENT; 10893c60ba66SKatsushi Kobayashi if (err == EBUSY && fc->status != FWBUSRESET) { 10903c60ba66SKatsushi Kobayashi xfer->state = FWXF_BUSY; 10913c60ba66SKatsushi Kobayashi xfer->resp = err; 1092864d7e72SHidetoshi Shimokawa if (xfer->retry_req != NULL) 10933c60ba66SKatsushi Kobayashi xfer->retry_req(xfer); 1094864d7e72SHidetoshi Shimokawa else 1095864d7e72SHidetoshi Shimokawa fw_xfer_done(xfer); 10963c60ba66SKatsushi Kobayashi } else if (stat != FWOHCIEV_ACKPEND) { 10973c60ba66SKatsushi Kobayashi if (stat != FWOHCIEV_ACKCOMPL) 10983c60ba66SKatsushi Kobayashi xfer->state = FWXF_SENTERR; 10993c60ba66SKatsushi Kobayashi xfer->resp = err; 11003c60ba66SKatsushi Kobayashi fw_xfer_done(xfer); 11013c60ba66SKatsushi Kobayashi } 11023c60ba66SKatsushi Kobayashi } 1103864d7e72SHidetoshi Shimokawa /* 1104864d7e72SHidetoshi Shimokawa * The watchdog timer takes care of split 1105864d7e72SHidetoshi Shimokawa * transcation timeout for ACKPEND case. 1106864d7e72SHidetoshi Shimokawa */ 110777ee030bSHidetoshi Shimokawa } else { 110877ee030bSHidetoshi Shimokawa printf("this shouldn't happen\n"); 11093c60ba66SKatsushi Kobayashi } 111048249fe0SHidetoshi Shimokawa dbch->xferq.queued --; 11113c60ba66SKatsushi Kobayashi tr->xfer = NULL; 11123c60ba66SKatsushi Kobayashi 11133c60ba66SKatsushi Kobayashi packets ++; 11143c60ba66SKatsushi Kobayashi tr = STAILQ_NEXT(tr, link); 11153c60ba66SKatsushi Kobayashi dbch->bottom = tr; 11163b79dd16SHidetoshi Shimokawa if (dbch->bottom == dbch->top) { 11173b79dd16SHidetoshi Shimokawa /* we reaches the end of context program */ 11183b79dd16SHidetoshi Shimokawa if (firewire_debug && dbch->xferq.queued > 0) 11193b79dd16SHidetoshi Shimokawa printf("queued > 0\n"); 11203b79dd16SHidetoshi Shimokawa break; 11213b79dd16SHidetoshi Shimokawa } 11223c60ba66SKatsushi Kobayashi } 11233c60ba66SKatsushi Kobayashi out: 11243c60ba66SKatsushi Kobayashi if ((dbch->flags & FWOHCI_DBCH_FULL) && packets > 0) { 11253c60ba66SKatsushi Kobayashi printf("make free slot\n"); 11263c60ba66SKatsushi Kobayashi dbch->flags &= ~FWOHCI_DBCH_FULL; 11273c60ba66SKatsushi Kobayashi fwohci_start(sc, dbch); 11283c60ba66SKatsushi Kobayashi } 11293c60ba66SKatsushi Kobayashi splx(s); 11303c60ba66SKatsushi Kobayashi } 1131c572b810SHidetoshi Shimokawa 1132c572b810SHidetoshi Shimokawa static void 1133c572b810SHidetoshi Shimokawa fwohci_db_free(struct fwohci_dbch *dbch) 11343c60ba66SKatsushi Kobayashi { 11353c60ba66SKatsushi Kobayashi struct fwohcidb_tr *db_tr; 113677ee030bSHidetoshi Shimokawa int idb; 11373c60ba66SKatsushi Kobayashi 11381f2361f8SHidetoshi Shimokawa if ((dbch->flags & FWOHCI_DBCH_INIT) == 0) 11391f2361f8SHidetoshi Shimokawa return; 11401f2361f8SHidetoshi Shimokawa 114177ee030bSHidetoshi Shimokawa for(db_tr = STAILQ_FIRST(&dbch->db_trq), idb = 0; idb < dbch->ndb; 11423c60ba66SKatsushi Kobayashi db_tr = STAILQ_NEXT(db_tr, link), idb++){ 114377ee030bSHidetoshi Shimokawa if ((dbch->xferq.flag & FWXFERQ_EXTBUF) == 0 && 114477ee030bSHidetoshi Shimokawa db_tr->buf != NULL) { 114577ee030bSHidetoshi Shimokawa fwdma_free_size(dbch->dmat, db_tr->dma_map, 114677ee030bSHidetoshi Shimokawa db_tr->buf, dbch->xferq.psize); 11473c60ba66SKatsushi Kobayashi db_tr->buf = NULL; 114877ee030bSHidetoshi Shimokawa } else if (db_tr->dma_map != NULL) 114977ee030bSHidetoshi Shimokawa bus_dmamap_destroy(dbch->dmat, db_tr->dma_map); 11501f2361f8SHidetoshi Shimokawa } 11513c60ba66SKatsushi Kobayashi dbch->ndb = 0; 11523c60ba66SKatsushi Kobayashi db_tr = STAILQ_FIRST(&dbch->db_trq); 115377ee030bSHidetoshi Shimokawa fwdma_free_multiseg(dbch->am); 11545166f1dfSHidetoshi Shimokawa free(db_tr, M_FW); 11553c60ba66SKatsushi Kobayashi STAILQ_INIT(&dbch->db_trq); 11561f2361f8SHidetoshi Shimokawa dbch->flags &= ~FWOHCI_DBCH_INIT; 11573c60ba66SKatsushi Kobayashi } 1158c572b810SHidetoshi Shimokawa 1159c572b810SHidetoshi Shimokawa static void 116077ee030bSHidetoshi Shimokawa fwohci_db_init(struct fwohci_softc *sc, struct fwohci_dbch *dbch) 11613c60ba66SKatsushi Kobayashi { 11623c60ba66SKatsushi Kobayashi int idb; 11633c60ba66SKatsushi Kobayashi struct fwohcidb_tr *db_tr; 11649339321dSHidetoshi Shimokawa 11659339321dSHidetoshi Shimokawa if ((dbch->flags & FWOHCI_DBCH_INIT) != 0) 11669339321dSHidetoshi Shimokawa goto out; 11679339321dSHidetoshi Shimokawa 116877ee030bSHidetoshi Shimokawa /* create dma_tag for buffers */ 116977ee030bSHidetoshi Shimokawa #define MAX_REQCOUNT 0xffff 117077ee030bSHidetoshi Shimokawa if (bus_dma_tag_create(/*parent*/ sc->fc.dmat, 117177ee030bSHidetoshi Shimokawa /*alignment*/ 1, /*boundary*/ 0, 117277ee030bSHidetoshi Shimokawa /*lowaddr*/ BUS_SPACE_MAXADDR_32BIT, 117377ee030bSHidetoshi Shimokawa /*highaddr*/ BUS_SPACE_MAXADDR, 117477ee030bSHidetoshi Shimokawa /*filter*/NULL, /*filterarg*/NULL, 117577ee030bSHidetoshi Shimokawa /*maxsize*/ dbch->xferq.psize, 117677ee030bSHidetoshi Shimokawa /*nsegments*/ dbch->ndesc > 3 ? dbch->ndesc - 2 : 1, 117777ee030bSHidetoshi Shimokawa /*maxsegsz*/ MAX_REQCOUNT, 117877ee030bSHidetoshi Shimokawa /*flags*/ 0, &dbch->dmat)) 117977ee030bSHidetoshi Shimokawa return; 118077ee030bSHidetoshi Shimokawa 11813c60ba66SKatsushi Kobayashi /* allocate DB entries and attach one to each DMA channels */ 11823c60ba66SKatsushi Kobayashi /* DB entry must start at 16 bytes bounary. */ 11833c60ba66SKatsushi Kobayashi STAILQ_INIT(&dbch->db_trq); 11843c60ba66SKatsushi Kobayashi db_tr = (struct fwohcidb_tr *) 11853c60ba66SKatsushi Kobayashi malloc(sizeof(struct fwohcidb_tr) * dbch->ndb, 118677ee030bSHidetoshi Shimokawa M_FW, M_WAITOK | M_ZERO); 11873c60ba66SKatsushi Kobayashi if(db_tr == NULL){ 1188e2ad5d6eSHidetoshi Shimokawa printf("fwohci_db_init: malloc(1) failed\n"); 11893c60ba66SKatsushi Kobayashi return; 11903c60ba66SKatsushi Kobayashi } 1191e2ad5d6eSHidetoshi Shimokawa 119277ee030bSHidetoshi Shimokawa #define DB_SIZE(x) (sizeof(struct fwohcidb) * (x)->ndesc) 119377ee030bSHidetoshi Shimokawa dbch->am = fwdma_malloc_multiseg(&sc->fc, DB_SIZE(dbch), 119477ee030bSHidetoshi Shimokawa DB_SIZE(dbch), dbch->ndb, BUS_DMA_WAITOK); 119577ee030bSHidetoshi Shimokawa if (dbch->am == NULL) { 119677ee030bSHidetoshi Shimokawa printf("fwohci_db_init: fwdma_malloc_multiseg failed\n"); 1197e2ad5d6eSHidetoshi Shimokawa return; 1198e2ad5d6eSHidetoshi Shimokawa } 11993c60ba66SKatsushi Kobayashi /* Attach DB to DMA ch. */ 12003c60ba66SKatsushi Kobayashi for(idb = 0 ; idb < dbch->ndb ; idb++){ 12013c60ba66SKatsushi Kobayashi db_tr->dbcnt = 0; 120277ee030bSHidetoshi Shimokawa db_tr->db = (struct fwohcidb *)fwdma_v_addr(dbch->am, idb); 120377ee030bSHidetoshi Shimokawa db_tr->bus_addr = fwdma_bus_addr(dbch->am, idb); 120477ee030bSHidetoshi Shimokawa /* create dmamap for buffers */ 120577ee030bSHidetoshi Shimokawa /* XXX do we need 4bytes alignment tag? */ 120677ee030bSHidetoshi Shimokawa /* XXX don't alloc dma_map for AR */ 120777ee030bSHidetoshi Shimokawa if (bus_dmamap_create(dbch->dmat, 0, &db_tr->dma_map) != 0) { 120877ee030bSHidetoshi Shimokawa printf("bus_dmamap_create failed\n"); 120977ee030bSHidetoshi Shimokawa dbch->flags = FWOHCI_DBCH_INIT; /* XXX fake */ 121077ee030bSHidetoshi Shimokawa fwohci_db_free(dbch); 121177ee030bSHidetoshi Shimokawa return; 121277ee030bSHidetoshi Shimokawa } 12133c60ba66SKatsushi Kobayashi STAILQ_INSERT_TAIL(&dbch->db_trq, db_tr, link); 121477ee030bSHidetoshi Shimokawa if (dbch->xferq.flag & FWXFERQ_EXTBUF) { 1215d0fd7bc6SHidetoshi Shimokawa if (idb % dbch->xferq.bnpacket == 0) 1216d0fd7bc6SHidetoshi Shimokawa dbch->xferq.bulkxfer[idb / dbch->xferq.bnpacket 1217d0fd7bc6SHidetoshi Shimokawa ].start = (caddr_t)db_tr; 1218d0fd7bc6SHidetoshi Shimokawa if ((idb + 1) % dbch->xferq.bnpacket == 0) 1219d0fd7bc6SHidetoshi Shimokawa dbch->xferq.bulkxfer[idb / dbch->xferq.bnpacket 1220d0fd7bc6SHidetoshi Shimokawa ].end = (caddr_t)db_tr; 12213c60ba66SKatsushi Kobayashi } 12223c60ba66SKatsushi Kobayashi db_tr++; 12233c60ba66SKatsushi Kobayashi } 12243c60ba66SKatsushi Kobayashi STAILQ_LAST(&dbch->db_trq, fwohcidb_tr,link)->link.stqe_next 12253c60ba66SKatsushi Kobayashi = STAILQ_FIRST(&dbch->db_trq); 12269339321dSHidetoshi Shimokawa out: 12279339321dSHidetoshi Shimokawa dbch->xferq.queued = 0; 12289339321dSHidetoshi Shimokawa dbch->pdb_tr = NULL; 12293c60ba66SKatsushi Kobayashi dbch->top = STAILQ_FIRST(&dbch->db_trq); 12303c60ba66SKatsushi Kobayashi dbch->bottom = dbch->top; 12311f2361f8SHidetoshi Shimokawa dbch->flags = FWOHCI_DBCH_INIT; 12323c60ba66SKatsushi Kobayashi } 1233c572b810SHidetoshi Shimokawa 1234c572b810SHidetoshi Shimokawa static int 1235c572b810SHidetoshi Shimokawa fwohci_itx_disable(struct firewire_comm *fc, int dmach) 12363c60ba66SKatsushi Kobayashi { 12373c60ba66SKatsushi Kobayashi struct fwohci_softc *sc = (struct fwohci_softc *)fc; 123877ee030bSHidetoshi Shimokawa int sleepch; 12395a7ba74dSHidetoshi Shimokawa 124077ee030bSHidetoshi Shimokawa OWRITE(sc, OHCI_ITCTLCLR(dmach), 124177ee030bSHidetoshi Shimokawa OHCI_CNTL_DMA_RUN | OHCI_CNTL_CYCMATCH_S); 12423c60ba66SKatsushi Kobayashi OWRITE(sc, OHCI_IT_MASKCLR, 1 << dmach); 12433c60ba66SKatsushi Kobayashi OWRITE(sc, OHCI_IT_STATCLR, 1 << dmach); 12445a7ba74dSHidetoshi Shimokawa /* XXX we cannot free buffers until the DMA really stops */ 124577ee030bSHidetoshi Shimokawa tsleep((void *)&sleepch, FWPRI, "fwitxd", hz); 12463c60ba66SKatsushi Kobayashi fwohci_db_free(&sc->it[dmach]); 12473c60ba66SKatsushi Kobayashi sc->it[dmach].xferq.flag &= ~FWXFERQ_RUNNING; 12483c60ba66SKatsushi Kobayashi return 0; 12493c60ba66SKatsushi Kobayashi } 1250c572b810SHidetoshi Shimokawa 1251c572b810SHidetoshi Shimokawa static int 1252c572b810SHidetoshi Shimokawa fwohci_irx_disable(struct firewire_comm *fc, int dmach) 12533c60ba66SKatsushi Kobayashi { 12543c60ba66SKatsushi Kobayashi struct fwohci_softc *sc = (struct fwohci_softc *)fc; 125577ee030bSHidetoshi Shimokawa int sleepch; 12563c60ba66SKatsushi Kobayashi 12573c60ba66SKatsushi Kobayashi OWRITE(sc, OHCI_IRCTLCLR(dmach), OHCI_CNTL_DMA_RUN); 12583c60ba66SKatsushi Kobayashi OWRITE(sc, OHCI_IR_MASKCLR, 1 << dmach); 12593c60ba66SKatsushi Kobayashi OWRITE(sc, OHCI_IR_STATCLR, 1 << dmach); 12605a7ba74dSHidetoshi Shimokawa /* XXX we cannot free buffers until the DMA really stops */ 126177ee030bSHidetoshi Shimokawa tsleep((void *)&sleepch, FWPRI, "fwirxd", hz); 12623c60ba66SKatsushi Kobayashi fwohci_db_free(&sc->ir[dmach]); 12633c60ba66SKatsushi Kobayashi sc->ir[dmach].xferq.flag &= ~FWXFERQ_RUNNING; 12643c60ba66SKatsushi Kobayashi return 0; 12653c60ba66SKatsushi Kobayashi } 1266c572b810SHidetoshi Shimokawa 126777ee030bSHidetoshi Shimokawa #if BYTE_ORDER == BIG_ENDIAN 1268c572b810SHidetoshi Shimokawa static void 1269c572b810SHidetoshi Shimokawa fwohci_irx_post (struct firewire_comm *fc , u_int32_t *qld) 12703c60ba66SKatsushi Kobayashi { 127177ee030bSHidetoshi Shimokawa qld[0] = FWOHCI_DMA_READ(qld[0]); 12723c60ba66SKatsushi Kobayashi return; 12733c60ba66SKatsushi Kobayashi } 12743c60ba66SKatsushi Kobayashi #endif 12753c60ba66SKatsushi Kobayashi 1276c572b810SHidetoshi Shimokawa static int 1277c572b810SHidetoshi Shimokawa fwohci_tx_enable(struct fwohci_softc *sc, struct fwohci_dbch *dbch) 12783c60ba66SKatsushi Kobayashi { 12793c60ba66SKatsushi Kobayashi int err = 0; 128077ee030bSHidetoshi Shimokawa int idb, z, i, dmach = 0, ldesc; 12813c60ba66SKatsushi Kobayashi u_int32_t off = NULL; 12823c60ba66SKatsushi Kobayashi struct fwohcidb_tr *db_tr; 128353f1eb86SHidetoshi Shimokawa volatile struct fwohcidb *db; 12843c60ba66SKatsushi Kobayashi 12853c60ba66SKatsushi Kobayashi if(!(dbch->xferq.flag & FWXFERQ_EXTBUF)){ 12863c60ba66SKatsushi Kobayashi err = EINVAL; 12873c60ba66SKatsushi Kobayashi return err; 12883c60ba66SKatsushi Kobayashi } 12893c60ba66SKatsushi Kobayashi z = dbch->ndesc; 12903c60ba66SKatsushi Kobayashi for(dmach = 0 ; dmach < sc->fc.nisodma ; dmach++){ 12913c60ba66SKatsushi Kobayashi if( &sc->it[dmach] == dbch){ 12923c60ba66SKatsushi Kobayashi off = OHCI_ITOFF(dmach); 12933c60ba66SKatsushi Kobayashi break; 12943c60ba66SKatsushi Kobayashi } 12953c60ba66SKatsushi Kobayashi } 12963c60ba66SKatsushi Kobayashi if(off == NULL){ 12973c60ba66SKatsushi Kobayashi err = EINVAL; 12983c60ba66SKatsushi Kobayashi return err; 12993c60ba66SKatsushi Kobayashi } 13003c60ba66SKatsushi Kobayashi if(dbch->xferq.flag & FWXFERQ_RUNNING) 13013c60ba66SKatsushi Kobayashi return err; 13023c60ba66SKatsushi Kobayashi dbch->xferq.flag |= FWXFERQ_RUNNING; 13033c60ba66SKatsushi Kobayashi for( i = 0, dbch->bottom = dbch->top; i < (dbch->ndb - 1); i++){ 13043c60ba66SKatsushi Kobayashi dbch->bottom = STAILQ_NEXT(dbch->bottom, link); 13053c60ba66SKatsushi Kobayashi } 13063c60ba66SKatsushi Kobayashi db_tr = dbch->top; 13073c60ba66SKatsushi Kobayashi for (idb = 0; idb < dbch->ndb; idb ++) { 130877ee030bSHidetoshi Shimokawa fwohci_add_tx_buf(dbch, db_tr, idb); 13093c60ba66SKatsushi Kobayashi if(STAILQ_NEXT(db_tr, link) == NULL){ 13103c60ba66SKatsushi Kobayashi break; 13113c60ba66SKatsushi Kobayashi } 131253f1eb86SHidetoshi Shimokawa db = db_tr->db; 131377ee030bSHidetoshi Shimokawa ldesc = db_tr->dbcnt - 1; 131477ee030bSHidetoshi Shimokawa FWOHCI_DMA_WRITE(db[0].db.desc.depend, 131577ee030bSHidetoshi Shimokawa STAILQ_NEXT(db_tr, link)->bus_addr | z); 131677ee030bSHidetoshi Shimokawa db[ldesc].db.desc.depend = db[0].db.desc.depend; 13173c60ba66SKatsushi Kobayashi if(dbch->xferq.flag & FWXFERQ_EXTBUF){ 13183c60ba66SKatsushi Kobayashi if(((idb + 1 ) % dbch->xferq.bnpacket) == 0){ 131977ee030bSHidetoshi Shimokawa FWOHCI_DMA_SET( 132077ee030bSHidetoshi Shimokawa db[ldesc].db.desc.cmd, 132177ee030bSHidetoshi Shimokawa OHCI_INTERRUPT_ALWAYS); 13224ed65ce9SHidetoshi Shimokawa /* OHCI 1.1 and above */ 132377ee030bSHidetoshi Shimokawa FWOHCI_DMA_SET( 132477ee030bSHidetoshi Shimokawa db[0].db.desc.cmd, 132577ee030bSHidetoshi Shimokawa OHCI_INTERRUPT_ALWAYS); 13263c60ba66SKatsushi Kobayashi } 13273c60ba66SKatsushi Kobayashi } 13283c60ba66SKatsushi Kobayashi db_tr = STAILQ_NEXT(db_tr, link); 13293c60ba66SKatsushi Kobayashi } 133077ee030bSHidetoshi Shimokawa FWOHCI_DMA_CLEAR( 133177ee030bSHidetoshi Shimokawa dbch->bottom->db[dbch->bottom->dbcnt - 1].db.desc.depend, 0xf); 13323c60ba66SKatsushi Kobayashi return err; 13333c60ba66SKatsushi Kobayashi } 1334c572b810SHidetoshi Shimokawa 1335c572b810SHidetoshi Shimokawa static int 1336c572b810SHidetoshi Shimokawa fwohci_rx_enable(struct fwohci_softc *sc, struct fwohci_dbch *dbch) 13373c60ba66SKatsushi Kobayashi { 13383c60ba66SKatsushi Kobayashi int err = 0; 133953f1eb86SHidetoshi Shimokawa int idb, z, i, dmach = 0, ldesc; 13403c60ba66SKatsushi Kobayashi u_int32_t off = NULL; 13413c60ba66SKatsushi Kobayashi struct fwohcidb_tr *db_tr; 134253f1eb86SHidetoshi Shimokawa volatile struct fwohcidb *db; 13433c60ba66SKatsushi Kobayashi 13443c60ba66SKatsushi Kobayashi z = dbch->ndesc; 13453c60ba66SKatsushi Kobayashi if(&sc->arrq == dbch){ 13463c60ba66SKatsushi Kobayashi off = OHCI_ARQOFF; 13473c60ba66SKatsushi Kobayashi }else if(&sc->arrs == dbch){ 13483c60ba66SKatsushi Kobayashi off = OHCI_ARSOFF; 13493c60ba66SKatsushi Kobayashi }else{ 13503c60ba66SKatsushi Kobayashi for(dmach = 0 ; dmach < sc->fc.nisodma ; dmach++){ 13513c60ba66SKatsushi Kobayashi if( &sc->ir[dmach] == dbch){ 13523c60ba66SKatsushi Kobayashi off = OHCI_IROFF(dmach); 13533c60ba66SKatsushi Kobayashi break; 13543c60ba66SKatsushi Kobayashi } 13553c60ba66SKatsushi Kobayashi } 13563c60ba66SKatsushi Kobayashi } 13573c60ba66SKatsushi Kobayashi if(off == NULL){ 13583c60ba66SKatsushi Kobayashi err = EINVAL; 13593c60ba66SKatsushi Kobayashi return err; 13603c60ba66SKatsushi Kobayashi } 13613c60ba66SKatsushi Kobayashi if(dbch->xferq.flag & FWXFERQ_STREAM){ 13623c60ba66SKatsushi Kobayashi if(dbch->xferq.flag & FWXFERQ_RUNNING) 13633c60ba66SKatsushi Kobayashi return err; 13643c60ba66SKatsushi Kobayashi }else{ 13653c60ba66SKatsushi Kobayashi if(dbch->xferq.flag & FWXFERQ_RUNNING){ 13663c60ba66SKatsushi Kobayashi err = EBUSY; 13673c60ba66SKatsushi Kobayashi return err; 13683c60ba66SKatsushi Kobayashi } 13693c60ba66SKatsushi Kobayashi } 13703c60ba66SKatsushi Kobayashi dbch->xferq.flag |= FWXFERQ_RUNNING; 13719339321dSHidetoshi Shimokawa dbch->top = STAILQ_FIRST(&dbch->db_trq); 13723c60ba66SKatsushi Kobayashi for( i = 0, dbch->bottom = dbch->top; i < (dbch->ndb - 1); i++){ 13733c60ba66SKatsushi Kobayashi dbch->bottom = STAILQ_NEXT(dbch->bottom, link); 13743c60ba66SKatsushi Kobayashi } 13753c60ba66SKatsushi Kobayashi db_tr = dbch->top; 13763c60ba66SKatsushi Kobayashi for (idb = 0; idb < dbch->ndb; idb ++) { 137777ee030bSHidetoshi Shimokawa fwohci_add_rx_buf(dbch, db_tr, idb, &sc->dummy_dma); 137877ee030bSHidetoshi Shimokawa if (STAILQ_NEXT(db_tr, link) == NULL) 13793c60ba66SKatsushi Kobayashi break; 138053f1eb86SHidetoshi Shimokawa db = db_tr->db; 138153f1eb86SHidetoshi Shimokawa ldesc = db_tr->dbcnt - 1; 138277ee030bSHidetoshi Shimokawa FWOHCI_DMA_WRITE(db[ldesc].db.desc.depend, 138377ee030bSHidetoshi Shimokawa STAILQ_NEXT(db_tr, link)->bus_addr | z); 13843c60ba66SKatsushi Kobayashi if(dbch->xferq.flag & FWXFERQ_EXTBUF){ 13853c60ba66SKatsushi Kobayashi if(((idb + 1 ) % dbch->xferq.bnpacket) == 0){ 138677ee030bSHidetoshi Shimokawa FWOHCI_DMA_SET( 138777ee030bSHidetoshi Shimokawa db[ldesc].db.desc.cmd, 138877ee030bSHidetoshi Shimokawa OHCI_INTERRUPT_ALWAYS); 138977ee030bSHidetoshi Shimokawa FWOHCI_DMA_CLEAR( 139077ee030bSHidetoshi Shimokawa db[ldesc].db.desc.depend, 139177ee030bSHidetoshi Shimokawa 0xf); 13923c60ba66SKatsushi Kobayashi } 13933c60ba66SKatsushi Kobayashi } 13943c60ba66SKatsushi Kobayashi db_tr = STAILQ_NEXT(db_tr, link); 13953c60ba66SKatsushi Kobayashi } 139677ee030bSHidetoshi Shimokawa FWOHCI_DMA_CLEAR( 139777ee030bSHidetoshi Shimokawa dbch->bottom->db[db_tr->dbcnt - 1].db.desc.depend, 0xf); 13983c60ba66SKatsushi Kobayashi dbch->buf_offset = 0; 139977ee030bSHidetoshi Shimokawa fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREREAD); 140077ee030bSHidetoshi Shimokawa fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREWRITE); 14013c60ba66SKatsushi Kobayashi if(dbch->xferq.flag & FWXFERQ_STREAM){ 14023c60ba66SKatsushi Kobayashi return err; 14033c60ba66SKatsushi Kobayashi }else{ 140477ee030bSHidetoshi Shimokawa OWRITE(sc, OHCI_DMACMD(off), dbch->top->bus_addr | z); 14053c60ba66SKatsushi Kobayashi } 14063c60ba66SKatsushi Kobayashi OWRITE(sc, OHCI_DMACTL(off), OHCI_CNTL_DMA_RUN); 14073c60ba66SKatsushi Kobayashi return err; 14083c60ba66SKatsushi Kobayashi } 1409c572b810SHidetoshi Shimokawa 1410c572b810SHidetoshi Shimokawa static int 141177ee030bSHidetoshi Shimokawa fwohci_next_cycle(struct firewire_comm *fc, int cycle_now) 14123c60ba66SKatsushi Kobayashi { 14135a7ba74dSHidetoshi Shimokawa int sec, cycle, cycle_match; 14143c60ba66SKatsushi Kobayashi 141597ae6c1fSHidetoshi Shimokawa cycle = cycle_now & 0x1fff; 141697ae6c1fSHidetoshi Shimokawa sec = cycle_now >> 13; 141797ae6c1fSHidetoshi Shimokawa #define CYCLE_MOD 0x10 141877ee030bSHidetoshi Shimokawa #if 1 141997ae6c1fSHidetoshi Shimokawa #define CYCLE_DELAY 8 /* min delay to start DMA */ 142077ee030bSHidetoshi Shimokawa #else 142177ee030bSHidetoshi Shimokawa #define CYCLE_DELAY 7000 /* min delay to start DMA */ 142277ee030bSHidetoshi Shimokawa #endif 142397ae6c1fSHidetoshi Shimokawa cycle = cycle + CYCLE_DELAY; 142497ae6c1fSHidetoshi Shimokawa if (cycle >= 8000) { 142597ae6c1fSHidetoshi Shimokawa sec ++; 142697ae6c1fSHidetoshi Shimokawa cycle -= 8000; 142797ae6c1fSHidetoshi Shimokawa } 142877ee030bSHidetoshi Shimokawa cycle = roundup2(cycle, CYCLE_MOD); 142997ae6c1fSHidetoshi Shimokawa if (cycle >= 8000) { 143097ae6c1fSHidetoshi Shimokawa sec ++; 143197ae6c1fSHidetoshi Shimokawa if (cycle == 8000) 143297ae6c1fSHidetoshi Shimokawa cycle = 0; 143397ae6c1fSHidetoshi Shimokawa else 143497ae6c1fSHidetoshi Shimokawa cycle = CYCLE_MOD; 143597ae6c1fSHidetoshi Shimokawa } 143697ae6c1fSHidetoshi Shimokawa cycle_match = ((sec << 13) | cycle) & 0x7ffff; 14375a7ba74dSHidetoshi Shimokawa 14385a7ba74dSHidetoshi Shimokawa return(cycle_match); 14395a7ba74dSHidetoshi Shimokawa } 14405a7ba74dSHidetoshi Shimokawa 14415a7ba74dSHidetoshi Shimokawa static int 14425a7ba74dSHidetoshi Shimokawa fwohci_itxbuf_enable(struct firewire_comm *fc, int dmach) 14435a7ba74dSHidetoshi Shimokawa { 14445a7ba74dSHidetoshi Shimokawa struct fwohci_softc *sc = (struct fwohci_softc *)fc; 14455a7ba74dSHidetoshi Shimokawa int err = 0; 14465a7ba74dSHidetoshi Shimokawa unsigned short tag, ich; 14475a7ba74dSHidetoshi Shimokawa struct fwohci_dbch *dbch; 14485a7ba74dSHidetoshi Shimokawa int cycle_match, cycle_now, s, ldesc; 14495a7ba74dSHidetoshi Shimokawa u_int32_t stat; 14505a7ba74dSHidetoshi Shimokawa struct fw_bulkxfer *first, *chunk, *prev; 14515a7ba74dSHidetoshi Shimokawa struct fw_xferq *it; 14525a7ba74dSHidetoshi Shimokawa 14535a7ba74dSHidetoshi Shimokawa dbch = &sc->it[dmach]; 14545a7ba74dSHidetoshi Shimokawa it = &dbch->xferq; 14555a7ba74dSHidetoshi Shimokawa 14565a7ba74dSHidetoshi Shimokawa tag = (it->flag >> 6) & 3; 14575a7ba74dSHidetoshi Shimokawa ich = it->flag & 0x3f; 14585a7ba74dSHidetoshi Shimokawa if ((dbch->flags & FWOHCI_DBCH_INIT) == 0) { 14595a7ba74dSHidetoshi Shimokawa dbch->ndb = it->bnpacket * it->bnchunk; 14605a7ba74dSHidetoshi Shimokawa dbch->ndesc = 3; 146177ee030bSHidetoshi Shimokawa fwohci_db_init(sc, dbch); 14625a7ba74dSHidetoshi Shimokawa if ((dbch->flags & FWOHCI_DBCH_INIT) == 0) 14635a7ba74dSHidetoshi Shimokawa return ENOMEM; 14645a7ba74dSHidetoshi Shimokawa err = fwohci_tx_enable(sc, dbch); 14655a7ba74dSHidetoshi Shimokawa } 14665a7ba74dSHidetoshi Shimokawa if(err) 14675a7ba74dSHidetoshi Shimokawa return err; 14685a7ba74dSHidetoshi Shimokawa 146953f1eb86SHidetoshi Shimokawa ldesc = dbch->ndesc - 1; 14705a7ba74dSHidetoshi Shimokawa s = splfw(); 14715a7ba74dSHidetoshi Shimokawa prev = STAILQ_LAST(&it->stdma, fw_bulkxfer, link); 14725a7ba74dSHidetoshi Shimokawa while ((chunk = STAILQ_FIRST(&it->stvalid)) != NULL) { 14735a7ba74dSHidetoshi Shimokawa volatile struct fwohcidb *db; 14745a7ba74dSHidetoshi Shimokawa 147577ee030bSHidetoshi Shimokawa fwdma_sync_multiseg(it->buf, chunk->poffset, it->bnpacket, 147677ee030bSHidetoshi Shimokawa BUS_DMASYNC_PREWRITE); 14775a7ba74dSHidetoshi Shimokawa fwohci_txbufdb(sc, dmach, chunk); 14785a7ba74dSHidetoshi Shimokawa if (prev != NULL) { 14795a7ba74dSHidetoshi Shimokawa db = ((struct fwohcidb_tr *)(prev->end))->db; 148077ee030bSHidetoshi Shimokawa #if 0 /* XXX necessary? */ 148177ee030bSHidetoshi Shimokawa FWOHCI_DMA_SET(db[ldesc].db.desc.cmd, 148277ee030bSHidetoshi Shimokawa OHCI_BRANCH_ALWAYS); 148377ee030bSHidetoshi Shimokawa #endif 148453f1eb86SHidetoshi Shimokawa #if 0 /* if bulkxfer->npacket changes */ 14855a7ba74dSHidetoshi Shimokawa db[ldesc].db.desc.depend = db[0].db.desc.depend = 148677ee030bSHidetoshi Shimokawa ((struct fwohcidb_tr *) 148777ee030bSHidetoshi Shimokawa (chunk->start))->bus_addr | dbch->ndesc; 148853f1eb86SHidetoshi Shimokawa #else 148977ee030bSHidetoshi Shimokawa FWOHCI_DMA_SET(db[0].db.desc.depend, dbch->ndesc); 149077ee030bSHidetoshi Shimokawa FWOHCI_DMA_SET(db[ldesc].db.desc.depend, dbch->ndesc); 149153f1eb86SHidetoshi Shimokawa #endif 14925a7ba74dSHidetoshi Shimokawa } 14935a7ba74dSHidetoshi Shimokawa STAILQ_REMOVE_HEAD(&it->stvalid, link); 14945a7ba74dSHidetoshi Shimokawa STAILQ_INSERT_TAIL(&it->stdma, chunk, link); 14955a7ba74dSHidetoshi Shimokawa prev = chunk; 14965a7ba74dSHidetoshi Shimokawa } 149777ee030bSHidetoshi Shimokawa fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREWRITE); 149877ee030bSHidetoshi Shimokawa fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREREAD); 14995a7ba74dSHidetoshi Shimokawa splx(s); 15005a7ba74dSHidetoshi Shimokawa stat = OREAD(sc, OHCI_ITCTL(dmach)); 150177ee030bSHidetoshi Shimokawa if (firewire_debug && (stat & OHCI_CNTL_CYCMATCH_S)) 150277ee030bSHidetoshi Shimokawa printf("stat 0x%x\n", stat); 150377ee030bSHidetoshi Shimokawa 15045a7ba74dSHidetoshi Shimokawa if (stat & (OHCI_CNTL_DMA_ACTIVE | OHCI_CNTL_CYCMATCH_S)) 15055a7ba74dSHidetoshi Shimokawa return 0; 15065a7ba74dSHidetoshi Shimokawa 150777ee030bSHidetoshi Shimokawa #if 0 15085a7ba74dSHidetoshi Shimokawa OWRITE(sc, OHCI_ITCTLCLR(dmach), OHCI_CNTL_DMA_RUN); 150977ee030bSHidetoshi Shimokawa #endif 15105a7ba74dSHidetoshi Shimokawa OWRITE(sc, OHCI_IT_MASKCLR, 1 << dmach); 15115a7ba74dSHidetoshi Shimokawa OWRITE(sc, OHCI_IT_STATCLR, 1 << dmach); 15125a7ba74dSHidetoshi Shimokawa OWRITE(sc, OHCI_IT_MASK, 1 << dmach); 151377ee030bSHidetoshi Shimokawa OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_DMA_IT); 15145a7ba74dSHidetoshi Shimokawa 15155a7ba74dSHidetoshi Shimokawa first = STAILQ_FIRST(&it->stdma); 151677ee030bSHidetoshi Shimokawa OWRITE(sc, OHCI_ITCMD(dmach), 151777ee030bSHidetoshi Shimokawa ((struct fwohcidb_tr *)(first->start))->bus_addr | dbch->ndesc); 151877ee030bSHidetoshi Shimokawa if (firewire_debug) { 15195a7ba74dSHidetoshi Shimokawa printf("fwohci_itxbuf_enable: kick 0x%08x\n", stat); 152077ee030bSHidetoshi Shimokawa #if 1 152177ee030bSHidetoshi Shimokawa dump_dma(sc, ITX_CH + dmach); 152277ee030bSHidetoshi Shimokawa #endif 152377ee030bSHidetoshi Shimokawa } 15245a7ba74dSHidetoshi Shimokawa if ((stat & OHCI_CNTL_DMA_RUN) == 0) { 15255a7ba74dSHidetoshi Shimokawa #if 1 15265a7ba74dSHidetoshi Shimokawa /* Don't start until all chunks are buffered */ 15275a7ba74dSHidetoshi Shimokawa if (STAILQ_FIRST(&it->stfree) != NULL) 15285a7ba74dSHidetoshi Shimokawa goto out; 15295a7ba74dSHidetoshi Shimokawa #endif 153077ee030bSHidetoshi Shimokawa #if 1 153197ae6c1fSHidetoshi Shimokawa /* Clear cycle match counter bits */ 153297ae6c1fSHidetoshi Shimokawa OWRITE(sc, OHCI_ITCTLCLR(dmach), 0xffff0000); 15335a7ba74dSHidetoshi Shimokawa 15345a7ba74dSHidetoshi Shimokawa /* 2bit second + 13bit cycle */ 15355a7ba74dSHidetoshi Shimokawa cycle_now = (fc->cyctimer(fc) >> 12) & 0x7fff; 153677ee030bSHidetoshi Shimokawa cycle_match = fwohci_next_cycle(fc, cycle_now); 15375a7ba74dSHidetoshi Shimokawa 153897ae6c1fSHidetoshi Shimokawa OWRITE(sc, OHCI_ITCTL(dmach), 153997ae6c1fSHidetoshi Shimokawa OHCI_CNTL_CYCMATCH_S | (cycle_match << 16) 154097ae6c1fSHidetoshi Shimokawa | OHCI_CNTL_DMA_RUN); 154177ee030bSHidetoshi Shimokawa #else 154277ee030bSHidetoshi Shimokawa OWRITE(sc, OHCI_ITCTL(dmach), OHCI_CNTL_DMA_RUN); 154377ee030bSHidetoshi Shimokawa #endif 154477ee030bSHidetoshi Shimokawa if (firewire_debug) { 15457643dc18SHidetoshi Shimokawa printf("cycle_match: 0x%04x->0x%04x\n", 15467643dc18SHidetoshi Shimokawa cycle_now, cycle_match); 154777ee030bSHidetoshi Shimokawa dump_dma(sc, ITX_CH + dmach); 154877ee030bSHidetoshi Shimokawa dump_db(sc, ITX_CH + dmach); 154977ee030bSHidetoshi Shimokawa } 15507643dc18SHidetoshi Shimokawa } else if ((stat & OHCI_CNTL_CYCMATCH_S) == 0) { 15515a7ba74dSHidetoshi Shimokawa device_printf(sc->fc.dev, 15525a7ba74dSHidetoshi Shimokawa "IT DMA underrun (0x%08x)\n", stat); 155377ee030bSHidetoshi Shimokawa OWRITE(sc, OHCI_ITCTL(dmach), OHCI_CNTL_DMA_WAKE); 15543c60ba66SKatsushi Kobayashi } 15555a7ba74dSHidetoshi Shimokawa out: 15563c60ba66SKatsushi Kobayashi return err; 15573c60ba66SKatsushi Kobayashi } 1558c572b810SHidetoshi Shimokawa 1559c572b810SHidetoshi Shimokawa static int 156077ee030bSHidetoshi Shimokawa fwohci_irx_enable(struct firewire_comm *fc, int dmach) 15613c60ba66SKatsushi Kobayashi { 15623c60ba66SKatsushi Kobayashi struct fwohci_softc *sc = (struct fwohci_softc *)fc; 15635a7ba74dSHidetoshi Shimokawa int err = 0, s, ldesc; 15643c60ba66SKatsushi Kobayashi unsigned short tag, ich; 156516e0f484SHidetoshi Shimokawa u_int32_t stat; 15665a7ba74dSHidetoshi Shimokawa struct fwohci_dbch *dbch; 156777ee030bSHidetoshi Shimokawa struct fwohcidb_tr *db_tr; 15685a7ba74dSHidetoshi Shimokawa struct fw_bulkxfer *first, *prev, *chunk; 15695a7ba74dSHidetoshi Shimokawa struct fw_xferq *ir; 1570435dd29bSHidetoshi Shimokawa 15715a7ba74dSHidetoshi Shimokawa dbch = &sc->ir[dmach]; 15725a7ba74dSHidetoshi Shimokawa ir = &dbch->xferq; 15735a7ba74dSHidetoshi Shimokawa 15745a7ba74dSHidetoshi Shimokawa if ((ir->flag & FWXFERQ_RUNNING) == 0) { 15755a7ba74dSHidetoshi Shimokawa tag = (ir->flag >> 6) & 3; 15765a7ba74dSHidetoshi Shimokawa ich = ir->flag & 0x3f; 15773c60ba66SKatsushi Kobayashi OWRITE(sc, OHCI_IRMATCH(dmach), tagbit[tag] | ich); 15783c60ba66SKatsushi Kobayashi 15795a7ba74dSHidetoshi Shimokawa ir->queued = 0; 15805a7ba74dSHidetoshi Shimokawa dbch->ndb = ir->bnpacket * ir->bnchunk; 15815a7ba74dSHidetoshi Shimokawa dbch->ndesc = 2; 158277ee030bSHidetoshi Shimokawa fwohci_db_init(sc, dbch); 15835a7ba74dSHidetoshi Shimokawa if ((dbch->flags & FWOHCI_DBCH_INIT) == 0) 15840aaa9a23SHidetoshi Shimokawa return ENOMEM; 15855a7ba74dSHidetoshi Shimokawa err = fwohci_rx_enable(sc, dbch); 15863c60ba66SKatsushi Kobayashi } 15873c60ba66SKatsushi Kobayashi if(err) 15883c60ba66SKatsushi Kobayashi return err; 15893c60ba66SKatsushi Kobayashi 15905a7ba74dSHidetoshi Shimokawa first = STAILQ_FIRST(&ir->stfree); 15915a7ba74dSHidetoshi Shimokawa if (first == NULL) { 15925a7ba74dSHidetoshi Shimokawa device_printf(fc->dev, "IR DMA no free chunk\n"); 15935a7ba74dSHidetoshi Shimokawa return 0; 15945a7ba74dSHidetoshi Shimokawa } 15955a7ba74dSHidetoshi Shimokawa 15969ca8add3SHidetoshi Shimokawa ldesc = dbch->ndesc - 1; 15979ca8add3SHidetoshi Shimokawa s = splfw(); 15985a7ba74dSHidetoshi Shimokawa prev = STAILQ_LAST(&ir->stdma, fw_bulkxfer, link); 15995a7ba74dSHidetoshi Shimokawa while ((chunk = STAILQ_FIRST(&ir->stfree)) != NULL) { 16005a7ba74dSHidetoshi Shimokawa volatile struct fwohcidb *db; 16015a7ba74dSHidetoshi Shimokawa 16022b4601d1SHidetoshi Shimokawa #if 1 /* XXX for if_fwe */ 160377ee030bSHidetoshi Shimokawa if (chunk->mbuf != NULL) { 160477ee030bSHidetoshi Shimokawa db_tr = (struct fwohcidb_tr *)(chunk->start); 160577ee030bSHidetoshi Shimokawa db_tr->dbcnt = 1; 160677ee030bSHidetoshi Shimokawa err = bus_dmamap_load_mbuf(dbch->dmat, db_tr->dma_map, 160777ee030bSHidetoshi Shimokawa chunk->mbuf, fwohci_execute_db2, db_tr, 160877ee030bSHidetoshi Shimokawa /* flags */0); 160977ee030bSHidetoshi Shimokawa FWOHCI_DMA_SET(db_tr->db[1].db.desc.cmd, 161077ee030bSHidetoshi Shimokawa OHCI_UPDATE | OHCI_INPUT_LAST | 161177ee030bSHidetoshi Shimokawa OHCI_INTERRUPT_ALWAYS | OHCI_BRANCH_ALWAYS); 161277ee030bSHidetoshi Shimokawa } 16132b4601d1SHidetoshi Shimokawa #endif 16145a7ba74dSHidetoshi Shimokawa db = ((struct fwohcidb_tr *)(chunk->end))->db; 161577ee030bSHidetoshi Shimokawa FWOHCI_DMA_WRITE(db[ldesc].db.desc.res, 0); 161677ee030bSHidetoshi Shimokawa FWOHCI_DMA_CLEAR(db[ldesc].db.desc.depend, 0xf); 16175a7ba74dSHidetoshi Shimokawa if (prev != NULL) { 16185a7ba74dSHidetoshi Shimokawa db = ((struct fwohcidb_tr *)(prev->end))->db; 161977ee030bSHidetoshi Shimokawa FWOHCI_DMA_SET(db[ldesc].db.desc.depend, dbch->ndesc); 16205a7ba74dSHidetoshi Shimokawa } 16215a7ba74dSHidetoshi Shimokawa STAILQ_REMOVE_HEAD(&ir->stfree, link); 16225a7ba74dSHidetoshi Shimokawa STAILQ_INSERT_TAIL(&ir->stdma, chunk, link); 16235a7ba74dSHidetoshi Shimokawa prev = chunk; 16245a7ba74dSHidetoshi Shimokawa } 162577ee030bSHidetoshi Shimokawa fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREWRITE); 162677ee030bSHidetoshi Shimokawa fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREREAD); 16275a7ba74dSHidetoshi Shimokawa splx(s); 16285a7ba74dSHidetoshi Shimokawa stat = OREAD(sc, OHCI_IRCTL(dmach)); 16295a7ba74dSHidetoshi Shimokawa if (stat & OHCI_CNTL_DMA_ACTIVE) 16305a7ba74dSHidetoshi Shimokawa return 0; 16315a7ba74dSHidetoshi Shimokawa if (stat & OHCI_CNTL_DMA_RUN) { 16323c60ba66SKatsushi Kobayashi OWRITE(sc, OHCI_IRCTLCLR(dmach), OHCI_CNTL_DMA_RUN); 16335a7ba74dSHidetoshi Shimokawa device_printf(sc->fc.dev, "IR DMA overrun (0x%08x)\n", stat); 16345a7ba74dSHidetoshi Shimokawa } 16355a7ba74dSHidetoshi Shimokawa 163677ee030bSHidetoshi Shimokawa if (firewire_debug) 163777ee030bSHidetoshi Shimokawa printf("start IR DMA 0x%x\n", stat); 16383c60ba66SKatsushi Kobayashi OWRITE(sc, OHCI_IR_MASKCLR, 1 << dmach); 16393c60ba66SKatsushi Kobayashi OWRITE(sc, OHCI_IR_STATCLR, 1 << dmach); 16403c60ba66SKatsushi Kobayashi OWRITE(sc, OHCI_IR_MASK, 1 << dmach); 16413c60ba66SKatsushi Kobayashi OWRITE(sc, OHCI_IRCTLCLR(dmach), 0xf0000000); 16423c60ba66SKatsushi Kobayashi OWRITE(sc, OHCI_IRCTL(dmach), OHCI_CNTL_ISOHDR); 16433c60ba66SKatsushi Kobayashi OWRITE(sc, OHCI_IRCMD(dmach), 164477ee030bSHidetoshi Shimokawa ((struct fwohcidb_tr *)(first->start))->bus_addr 16455a7ba74dSHidetoshi Shimokawa | dbch->ndesc); 16463c60ba66SKatsushi Kobayashi OWRITE(sc, OHCI_IRCTL(dmach), OHCI_CNTL_DMA_RUN); 16473c60ba66SKatsushi Kobayashi OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_DMA_IR); 164877ee030bSHidetoshi Shimokawa #if 0 164977ee030bSHidetoshi Shimokawa dump_db(sc, IRX_CH + dmach); 165077ee030bSHidetoshi Shimokawa #endif 16513c60ba66SKatsushi Kobayashi return err; 16523c60ba66SKatsushi Kobayashi } 1653c572b810SHidetoshi Shimokawa 1654c572b810SHidetoshi Shimokawa int 165564cf5240SHidetoshi Shimokawa fwohci_stop(struct fwohci_softc *sc, device_t dev) 16563c60ba66SKatsushi Kobayashi { 16573c60ba66SKatsushi Kobayashi u_int i; 16583c60ba66SKatsushi Kobayashi 16593c60ba66SKatsushi Kobayashi /* Now stopping all DMA channel */ 16603c60ba66SKatsushi Kobayashi OWRITE(sc, OHCI_ARQCTLCLR, OHCI_CNTL_DMA_RUN); 16613c60ba66SKatsushi Kobayashi OWRITE(sc, OHCI_ARSCTLCLR, OHCI_CNTL_DMA_RUN); 16623c60ba66SKatsushi Kobayashi OWRITE(sc, OHCI_ATQCTLCLR, OHCI_CNTL_DMA_RUN); 16633c60ba66SKatsushi Kobayashi OWRITE(sc, OHCI_ATSCTLCLR, OHCI_CNTL_DMA_RUN); 16643c60ba66SKatsushi Kobayashi 16653c60ba66SKatsushi Kobayashi for( i = 0 ; i < sc->fc.nisodma ; i ++ ){ 16663c60ba66SKatsushi Kobayashi OWRITE(sc, OHCI_IRCTLCLR(i), OHCI_CNTL_DMA_RUN); 16673c60ba66SKatsushi Kobayashi OWRITE(sc, OHCI_ITCTLCLR(i), OHCI_CNTL_DMA_RUN); 16683c60ba66SKatsushi Kobayashi } 16693c60ba66SKatsushi Kobayashi 16703c60ba66SKatsushi Kobayashi /* FLUSH FIFO and reset Transmitter/Reciever */ 16713c60ba66SKatsushi Kobayashi OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_RESET); 16723c60ba66SKatsushi Kobayashi 16733c60ba66SKatsushi Kobayashi /* Stop interrupt */ 16743c60ba66SKatsushi Kobayashi OWRITE(sc, FWOHCI_INTMASKCLR, 16753c60ba66SKatsushi Kobayashi OHCI_INT_EN | OHCI_INT_ERR | OHCI_INT_PHY_SID 16763c60ba66SKatsushi Kobayashi | OHCI_INT_PHY_INT 16773c60ba66SKatsushi Kobayashi | OHCI_INT_DMA_ATRQ | OHCI_INT_DMA_ATRS 16783c60ba66SKatsushi Kobayashi | OHCI_INT_DMA_PRRQ | OHCI_INT_DMA_PRRS 16793c60ba66SKatsushi Kobayashi | OHCI_INT_DMA_ARRQ | OHCI_INT_DMA_ARRS 16803c60ba66SKatsushi Kobayashi | OHCI_INT_PHY_BUS_R); 16819339321dSHidetoshi Shimokawa /* XXX Link down? Bus reset? */ 16829339321dSHidetoshi Shimokawa return 0; 16839339321dSHidetoshi Shimokawa } 16849339321dSHidetoshi Shimokawa 16859339321dSHidetoshi Shimokawa int 16869339321dSHidetoshi Shimokawa fwohci_resume(struct fwohci_softc *sc, device_t dev) 16879339321dSHidetoshi Shimokawa { 16889339321dSHidetoshi Shimokawa int i; 16899339321dSHidetoshi Shimokawa 16909339321dSHidetoshi Shimokawa fwohci_reset(sc, dev); 16919339321dSHidetoshi Shimokawa /* XXX resume isochronus receive automatically. (how about TX?) */ 16929339321dSHidetoshi Shimokawa for(i = 0; i < sc->fc.nisodma; i ++) { 16939339321dSHidetoshi Shimokawa if((sc->ir[i].xferq.flag & FWXFERQ_RUNNING) != 0) { 16949339321dSHidetoshi Shimokawa device_printf(sc->fc.dev, 16959339321dSHidetoshi Shimokawa "resume iso receive ch: %d\n", i); 16969339321dSHidetoshi Shimokawa sc->ir[i].xferq.flag &= ~FWXFERQ_RUNNING; 16979339321dSHidetoshi Shimokawa sc->fc.irx_enable(&sc->fc, i); 16989339321dSHidetoshi Shimokawa } 16999339321dSHidetoshi Shimokawa } 17009339321dSHidetoshi Shimokawa 17019339321dSHidetoshi Shimokawa bus_generic_resume(dev); 17029339321dSHidetoshi Shimokawa sc->fc.ibr(&sc->fc); 17033c60ba66SKatsushi Kobayashi return 0; 17043c60ba66SKatsushi Kobayashi } 17053c60ba66SKatsushi Kobayashi 17063c60ba66SKatsushi Kobayashi #define ACK_ALL 17073c60ba66SKatsushi Kobayashi static void 1708783058faSHidetoshi Shimokawa fwohci_intr_body(struct fwohci_softc *sc, u_int32_t stat, int count) 17093c60ba66SKatsushi Kobayashi { 17103c60ba66SKatsushi Kobayashi u_int32_t irstat, itstat; 17113c60ba66SKatsushi Kobayashi u_int i; 17123c60ba66SKatsushi Kobayashi struct firewire_comm *fc = (struct firewire_comm *)sc; 17133c60ba66SKatsushi Kobayashi 17143c60ba66SKatsushi Kobayashi #ifdef OHCI_DEBUG 17153c60ba66SKatsushi Kobayashi if(stat & OREAD(sc, FWOHCI_INTMASK)) 17163c60ba66SKatsushi Kobayashi device_printf(fc->dev, "INTERRUPT < %s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s> 0x%08x, 0x%08x\n", 17173c60ba66SKatsushi Kobayashi stat & OHCI_INT_EN ? "DMA_EN ":"", 17183c60ba66SKatsushi Kobayashi stat & OHCI_INT_PHY_REG ? "PHY_REG ":"", 17193c60ba66SKatsushi Kobayashi stat & OHCI_INT_CYC_LONG ? "CYC_LONG ":"", 17203c60ba66SKatsushi Kobayashi stat & OHCI_INT_ERR ? "INT_ERR ":"", 17213c60ba66SKatsushi Kobayashi stat & OHCI_INT_CYC_ERR ? "CYC_ERR ":"", 17223c60ba66SKatsushi Kobayashi stat & OHCI_INT_CYC_LOST ? "CYC_LOST ":"", 17233c60ba66SKatsushi Kobayashi stat & OHCI_INT_CYC_64SECOND ? "CYC_64SECOND ":"", 17243c60ba66SKatsushi Kobayashi stat & OHCI_INT_CYC_START ? "CYC_START ":"", 17253c60ba66SKatsushi Kobayashi stat & OHCI_INT_PHY_INT ? "PHY_INT ":"", 17263c60ba66SKatsushi Kobayashi stat & OHCI_INT_PHY_BUS_R ? "BUS_RESET ":"", 17273c60ba66SKatsushi Kobayashi stat & OHCI_INT_PHY_SID ? "SID ":"", 17283c60ba66SKatsushi Kobayashi stat & OHCI_INT_LR_ERR ? "DMA_LR_ERR ":"", 17293c60ba66SKatsushi Kobayashi stat & OHCI_INT_PW_ERR ? "DMA_PW_ERR ":"", 17303c60ba66SKatsushi Kobayashi stat & OHCI_INT_DMA_IR ? "DMA_IR ":"", 17313c60ba66SKatsushi Kobayashi stat & OHCI_INT_DMA_IT ? "DMA_IT " :"", 17323c60ba66SKatsushi Kobayashi stat & OHCI_INT_DMA_PRRS ? "DMA_PRRS " :"", 17333c60ba66SKatsushi Kobayashi stat & OHCI_INT_DMA_PRRQ ? "DMA_PRRQ " :"", 17343c60ba66SKatsushi Kobayashi stat & OHCI_INT_DMA_ARRS ? "DMA_ARRS " :"", 17353c60ba66SKatsushi Kobayashi stat & OHCI_INT_DMA_ARRQ ? "DMA_ARRQ " :"", 17363c60ba66SKatsushi Kobayashi stat & OHCI_INT_DMA_ATRS ? "DMA_ATRS " :"", 17373c60ba66SKatsushi Kobayashi stat & OHCI_INT_DMA_ATRQ ? "DMA_ATRQ " :"", 17383c60ba66SKatsushi Kobayashi stat, OREAD(sc, FWOHCI_INTMASK) 17393c60ba66SKatsushi Kobayashi ); 17403c60ba66SKatsushi Kobayashi #endif 17413c60ba66SKatsushi Kobayashi /* Bus reset */ 17423c60ba66SKatsushi Kobayashi if(stat & OHCI_INT_PHY_BUS_R ){ 17431adf6842SHidetoshi Shimokawa if (fc->status == FWBUSRESET) 17441adf6842SHidetoshi Shimokawa goto busresetout; 17451adf6842SHidetoshi Shimokawa /* Disable bus reset interrupt until sid recv. */ 17461adf6842SHidetoshi Shimokawa OWRITE(sc, FWOHCI_INTMASKCLR, OHCI_INT_PHY_BUS_R); 17471adf6842SHidetoshi Shimokawa 17483c60ba66SKatsushi Kobayashi device_printf(fc->dev, "BUS reset\n"); 17493c60ba66SKatsushi Kobayashi OWRITE(sc, FWOHCI_INTMASKCLR, OHCI_INT_CYC_LOST); 17503c60ba66SKatsushi Kobayashi OWRITE(sc, OHCI_LNKCTLCLR, OHCI_CNTL_CYCSRC); 17513c60ba66SKatsushi Kobayashi 17523c60ba66SKatsushi Kobayashi OWRITE(sc, OHCI_ATQCTLCLR, OHCI_CNTL_DMA_RUN); 17533c60ba66SKatsushi Kobayashi sc->atrq.xferq.flag &= ~FWXFERQ_RUNNING; 17543c60ba66SKatsushi Kobayashi OWRITE(sc, OHCI_ATSCTLCLR, OHCI_CNTL_DMA_RUN); 17553c60ba66SKatsushi Kobayashi sc->atrs.xferq.flag &= ~FWXFERQ_RUNNING; 17563c60ba66SKatsushi Kobayashi 17573c60ba66SKatsushi Kobayashi #ifndef ACK_ALL 17583c60ba66SKatsushi Kobayashi OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_PHY_BUS_R); 17593c60ba66SKatsushi Kobayashi #endif 1760627d85fbSHidetoshi Shimokawa fw_busreset(fc); 17613c60ba66SKatsushi Kobayashi } 17621adf6842SHidetoshi Shimokawa busresetout: 17633c60ba66SKatsushi Kobayashi if((stat & OHCI_INT_DMA_IR )){ 17643c60ba66SKatsushi Kobayashi #ifndef ACK_ALL 17653c60ba66SKatsushi Kobayashi OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_IR); 17663c60ba66SKatsushi Kobayashi #endif 176777ee030bSHidetoshi Shimokawa #if __FreeBSD_version >= 500000 176877ee030bSHidetoshi Shimokawa irstat = atomic_readandclear_int(&sc->irstat); 176977ee030bSHidetoshi Shimokawa #else 177077ee030bSHidetoshi Shimokawa irstat = sc->irstat; 177177ee030bSHidetoshi Shimokawa sc->irstat = 0; 177277ee030bSHidetoshi Shimokawa #endif 17733c60ba66SKatsushi Kobayashi for(i = 0; i < fc->nisodma ; i++){ 1774b9b35d19SHidetoshi Shimokawa struct fwohci_dbch *dbch; 1775b9b35d19SHidetoshi Shimokawa 17763c60ba66SKatsushi Kobayashi if((irstat & (1 << i)) != 0){ 1777b9b35d19SHidetoshi Shimokawa dbch = &sc->ir[i]; 1778b9b35d19SHidetoshi Shimokawa if ((dbch->xferq.flag & FWXFERQ_OPEN) == 0) { 1779b9b35d19SHidetoshi Shimokawa device_printf(sc->fc.dev, 1780b9b35d19SHidetoshi Shimokawa "dma(%d) not active\n", i); 1781b9b35d19SHidetoshi Shimokawa continue; 1782b9b35d19SHidetoshi Shimokawa } 17833c60ba66SKatsushi Kobayashi fwohci_rbuf_update(sc, i); 17843c60ba66SKatsushi Kobayashi } 17853c60ba66SKatsushi Kobayashi } 17863c60ba66SKatsushi Kobayashi } 17873c60ba66SKatsushi Kobayashi if((stat & OHCI_INT_DMA_IT )){ 17883c60ba66SKatsushi Kobayashi #ifndef ACK_ALL 17893c60ba66SKatsushi Kobayashi OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_IT); 17903c60ba66SKatsushi Kobayashi #endif 179177ee030bSHidetoshi Shimokawa #if __FreeBSD_version >= 500000 179277ee030bSHidetoshi Shimokawa itstat = atomic_readandclear_int(&sc->itstat); 179377ee030bSHidetoshi Shimokawa #else 179477ee030bSHidetoshi Shimokawa itstat = sc->itstat; 179577ee030bSHidetoshi Shimokawa sc->itstat = 0; 179677ee030bSHidetoshi Shimokawa #endif 17973c60ba66SKatsushi Kobayashi for(i = 0; i < fc->nisodma ; i++){ 17983c60ba66SKatsushi Kobayashi if((itstat & (1 << i)) != 0){ 17993c60ba66SKatsushi Kobayashi fwohci_tbuf_update(sc, i); 18003c60ba66SKatsushi Kobayashi } 18013c60ba66SKatsushi Kobayashi } 18023c60ba66SKatsushi Kobayashi } 18033c60ba66SKatsushi Kobayashi if((stat & OHCI_INT_DMA_PRRS )){ 18043c60ba66SKatsushi Kobayashi #ifndef ACK_ALL 18053c60ba66SKatsushi Kobayashi OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_PRRS); 18063c60ba66SKatsushi Kobayashi #endif 18073c60ba66SKatsushi Kobayashi #if 0 18083c60ba66SKatsushi Kobayashi dump_dma(sc, ARRS_CH); 18093c60ba66SKatsushi Kobayashi dump_db(sc, ARRS_CH); 18103c60ba66SKatsushi Kobayashi #endif 1811783058faSHidetoshi Shimokawa fwohci_arcv(sc, &sc->arrs, count); 18123c60ba66SKatsushi Kobayashi } 18133c60ba66SKatsushi Kobayashi if((stat & OHCI_INT_DMA_PRRQ )){ 18143c60ba66SKatsushi Kobayashi #ifndef ACK_ALL 18153c60ba66SKatsushi Kobayashi OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_PRRQ); 18163c60ba66SKatsushi Kobayashi #endif 18173c60ba66SKatsushi Kobayashi #if 0 18183c60ba66SKatsushi Kobayashi dump_dma(sc, ARRQ_CH); 18193c60ba66SKatsushi Kobayashi dump_db(sc, ARRQ_CH); 18203c60ba66SKatsushi Kobayashi #endif 1821783058faSHidetoshi Shimokawa fwohci_arcv(sc, &sc->arrq, count); 18223c60ba66SKatsushi Kobayashi } 18233c60ba66SKatsushi Kobayashi if(stat & OHCI_INT_PHY_SID){ 182477ee030bSHidetoshi Shimokawa u_int32_t *buf, node_id; 18253c60ba66SKatsushi Kobayashi int plen; 18263c60ba66SKatsushi Kobayashi 18273c60ba66SKatsushi Kobayashi #ifndef ACK_ALL 18283c60ba66SKatsushi Kobayashi OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_PHY_SID); 18293c60ba66SKatsushi Kobayashi #endif 18301adf6842SHidetoshi Shimokawa /* Enable bus reset interrupt */ 18311adf6842SHidetoshi Shimokawa OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_PHY_BUS_R); 1832dcae7539SHidetoshi Shimokawa /* Allow async. request to us */ 1833dcae7539SHidetoshi Shimokawa OWRITE(sc, OHCI_AREQHI, 1 << 31); 1834dcae7539SHidetoshi Shimokawa /* XXX insecure ?? */ 1835dcae7539SHidetoshi Shimokawa OWRITE(sc, OHCI_PREQHI, 0x7fffffff); 1836dcae7539SHidetoshi Shimokawa OWRITE(sc, OHCI_PREQLO, 0xffffffff); 1837dcae7539SHidetoshi Shimokawa OWRITE(sc, OHCI_PREQUPPER, 0x10000); 183873aa55baSHidetoshi Shimokawa /* Set ATRetries register */ 183973aa55baSHidetoshi Shimokawa OWRITE(sc, OHCI_ATRETRY, 1<<(13+16) | 0xfff); 18403c60ba66SKatsushi Kobayashi /* 18413c60ba66SKatsushi Kobayashi ** Checking whether the node is root or not. If root, turn on 18423c60ba66SKatsushi Kobayashi ** cycle master. 18433c60ba66SKatsushi Kobayashi */ 184477ee030bSHidetoshi Shimokawa node_id = OREAD(sc, FWOHCI_NODEID); 184577ee030bSHidetoshi Shimokawa plen = OREAD(sc, OHCI_SID_CNT); 184677ee030bSHidetoshi Shimokawa 184777ee030bSHidetoshi Shimokawa device_printf(fc->dev, "node_id=0x%08x, gen=%d, ", 184877ee030bSHidetoshi Shimokawa node_id, (plen >> 16) & 0xff); 184977ee030bSHidetoshi Shimokawa if (!(node_id & OHCI_NODE_VALID)) { 18503c60ba66SKatsushi Kobayashi printf("Bus reset failure\n"); 18513c60ba66SKatsushi Kobayashi goto sidout; 18523c60ba66SKatsushi Kobayashi } 185377ee030bSHidetoshi Shimokawa if (node_id & OHCI_NODE_ROOT) { 18543c60ba66SKatsushi Kobayashi printf("CYCLEMASTER mode\n"); 18553c60ba66SKatsushi Kobayashi OWRITE(sc, OHCI_LNKCTL, 18563c60ba66SKatsushi Kobayashi OHCI_CNTL_CYCMTR | OHCI_CNTL_CYCTIMER); 18573c60ba66SKatsushi Kobayashi } else { 18583c60ba66SKatsushi Kobayashi printf("non CYCLEMASTER mode\n"); 18593c60ba66SKatsushi Kobayashi OWRITE(sc, OHCI_LNKCTLCLR, OHCI_CNTL_CYCMTR); 18603c60ba66SKatsushi Kobayashi OWRITE(sc, OHCI_LNKCTL, OHCI_CNTL_CYCTIMER); 18613c60ba66SKatsushi Kobayashi } 186277ee030bSHidetoshi Shimokawa fc->nodeid = node_id & 0x3f; 18633c60ba66SKatsushi Kobayashi 186477ee030bSHidetoshi Shimokawa if (plen & OHCI_SID_ERR) { 186577ee030bSHidetoshi Shimokawa device_printf(fc->dev, "SID Error\n"); 186677ee030bSHidetoshi Shimokawa goto sidout; 186777ee030bSHidetoshi Shimokawa } 186877ee030bSHidetoshi Shimokawa plen &= OHCI_SID_CNT_MASK; 186916e0f484SHidetoshi Shimokawa if (plen < 4 || plen > OHCI_SIDSIZE) { 187016e0f484SHidetoshi Shimokawa device_printf(fc->dev, "invalid SID len = %d\n", plen); 187116e0f484SHidetoshi Shimokawa goto sidout; 187216e0f484SHidetoshi Shimokawa } 18733c60ba66SKatsushi Kobayashi plen -= 4; /* chop control info */ 187477ee030bSHidetoshi Shimokawa buf = (u_int32_t *)malloc(OHCI_SIDSIZE, M_FW, M_NOWAIT); 187577ee030bSHidetoshi Shimokawa if (buf == NULL) { 187677ee030bSHidetoshi Shimokawa device_printf(fc->dev, "malloc failed\n"); 187777ee030bSHidetoshi Shimokawa goto sidout; 187877ee030bSHidetoshi Shimokawa } 187977ee030bSHidetoshi Shimokawa for (i = 0; i < plen / 4; i ++) 188077ee030bSHidetoshi Shimokawa buf[i] = FWOHCI_DMA_READ(sc->sid_buf[i+1]); 188148249fe0SHidetoshi Shimokawa #if 1 188248249fe0SHidetoshi Shimokawa /* pending all pre-bus_reset packets */ 188348249fe0SHidetoshi Shimokawa fwohci_txd(sc, &sc->atrq); 188448249fe0SHidetoshi Shimokawa fwohci_txd(sc, &sc->atrs); 188548249fe0SHidetoshi Shimokawa fwohci_arcv(sc, &sc->arrs, -1); 188648249fe0SHidetoshi Shimokawa fwohci_arcv(sc, &sc->arrq, -1); 1887627d85fbSHidetoshi Shimokawa fw_drain_txq(fc); 188848249fe0SHidetoshi Shimokawa #endif 188977ee030bSHidetoshi Shimokawa fw_sidrcv(fc, buf, plen); 189077ee030bSHidetoshi Shimokawa free(buf, M_FW); 18913c60ba66SKatsushi Kobayashi } 18923c60ba66SKatsushi Kobayashi sidout: 18933c60ba66SKatsushi Kobayashi if((stat & OHCI_INT_DMA_ATRQ )){ 18943c60ba66SKatsushi Kobayashi #ifndef ACK_ALL 18953c60ba66SKatsushi Kobayashi OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_ATRQ); 18963c60ba66SKatsushi Kobayashi #endif 18973c60ba66SKatsushi Kobayashi fwohci_txd(sc, &(sc->atrq)); 18983c60ba66SKatsushi Kobayashi } 18993c60ba66SKatsushi Kobayashi if((stat & OHCI_INT_DMA_ATRS )){ 19003c60ba66SKatsushi Kobayashi #ifndef ACK_ALL 19013c60ba66SKatsushi Kobayashi OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_ATRS); 19023c60ba66SKatsushi Kobayashi #endif 19033c60ba66SKatsushi Kobayashi fwohci_txd(sc, &(sc->atrs)); 19043c60ba66SKatsushi Kobayashi } 19053c60ba66SKatsushi Kobayashi if((stat & OHCI_INT_PW_ERR )){ 19063c60ba66SKatsushi Kobayashi #ifndef ACK_ALL 19073c60ba66SKatsushi Kobayashi OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_PW_ERR); 19083c60ba66SKatsushi Kobayashi #endif 19093c60ba66SKatsushi Kobayashi device_printf(fc->dev, "posted write error\n"); 19103c60ba66SKatsushi Kobayashi } 19113c60ba66SKatsushi Kobayashi if((stat & OHCI_INT_ERR )){ 19123c60ba66SKatsushi Kobayashi #ifndef ACK_ALL 19133c60ba66SKatsushi Kobayashi OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_ERR); 19143c60ba66SKatsushi Kobayashi #endif 19153c60ba66SKatsushi Kobayashi device_printf(fc->dev, "unrecoverable error\n"); 19163c60ba66SKatsushi Kobayashi } 19173c60ba66SKatsushi Kobayashi if((stat & OHCI_INT_PHY_INT)) { 19183c60ba66SKatsushi Kobayashi #ifndef ACK_ALL 19193c60ba66SKatsushi Kobayashi OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_PHY_INT); 19203c60ba66SKatsushi Kobayashi #endif 19213c60ba66SKatsushi Kobayashi device_printf(fc->dev, "phy int\n"); 19223c60ba66SKatsushi Kobayashi } 19233c60ba66SKatsushi Kobayashi 19243c60ba66SKatsushi Kobayashi return; 19253c60ba66SKatsushi Kobayashi } 19263c60ba66SKatsushi Kobayashi 192777ee030bSHidetoshi Shimokawa #if FWOHCI_TASKQUEUE 192877ee030bSHidetoshi Shimokawa static void 192977ee030bSHidetoshi Shimokawa fwohci_complete(void *arg, int pending) 193077ee030bSHidetoshi Shimokawa { 193177ee030bSHidetoshi Shimokawa struct fwohci_softc *sc = (struct fwohci_softc *)arg; 193277ee030bSHidetoshi Shimokawa u_int32_t stat; 193377ee030bSHidetoshi Shimokawa 193477ee030bSHidetoshi Shimokawa again: 193577ee030bSHidetoshi Shimokawa stat = atomic_readandclear_int(&sc->intstat); 193677ee030bSHidetoshi Shimokawa if (stat) 193777ee030bSHidetoshi Shimokawa fwohci_intr_body(sc, stat, -1); 193877ee030bSHidetoshi Shimokawa else 193977ee030bSHidetoshi Shimokawa return; 194077ee030bSHidetoshi Shimokawa goto again; 194177ee030bSHidetoshi Shimokawa } 194277ee030bSHidetoshi Shimokawa #endif 194377ee030bSHidetoshi Shimokawa 194477ee030bSHidetoshi Shimokawa static u_int32_t 194577ee030bSHidetoshi Shimokawa fwochi_check_stat(struct fwohci_softc *sc) 194677ee030bSHidetoshi Shimokawa { 194777ee030bSHidetoshi Shimokawa u_int32_t stat, irstat, itstat; 194877ee030bSHidetoshi Shimokawa 194977ee030bSHidetoshi Shimokawa stat = OREAD(sc, FWOHCI_INTSTAT); 195077ee030bSHidetoshi Shimokawa if (stat == 0xffffffff) { 195177ee030bSHidetoshi Shimokawa device_printf(sc->fc.dev, 195277ee030bSHidetoshi Shimokawa "device physically ejected?\n"); 195377ee030bSHidetoshi Shimokawa return(stat); 195477ee030bSHidetoshi Shimokawa } 195577ee030bSHidetoshi Shimokawa #ifdef ACK_ALL 195677ee030bSHidetoshi Shimokawa if (stat) 195777ee030bSHidetoshi Shimokawa OWRITE(sc, FWOHCI_INTSTATCLR, stat); 195877ee030bSHidetoshi Shimokawa #endif 195977ee030bSHidetoshi Shimokawa if (stat & OHCI_INT_DMA_IR) { 196077ee030bSHidetoshi Shimokawa irstat = OREAD(sc, OHCI_IR_STAT); 196177ee030bSHidetoshi Shimokawa OWRITE(sc, OHCI_IR_STATCLR, irstat); 196277ee030bSHidetoshi Shimokawa atomic_set_int(&sc->irstat, irstat); 196377ee030bSHidetoshi Shimokawa } 196477ee030bSHidetoshi Shimokawa if (stat & OHCI_INT_DMA_IT) { 196577ee030bSHidetoshi Shimokawa itstat = OREAD(sc, OHCI_IT_STAT); 196677ee030bSHidetoshi Shimokawa OWRITE(sc, OHCI_IT_STATCLR, itstat); 196777ee030bSHidetoshi Shimokawa atomic_set_int(&sc->itstat, itstat); 196877ee030bSHidetoshi Shimokawa } 196977ee030bSHidetoshi Shimokawa return(stat); 197077ee030bSHidetoshi Shimokawa } 197177ee030bSHidetoshi Shimokawa 19723c60ba66SKatsushi Kobayashi void 19733c60ba66SKatsushi Kobayashi fwohci_intr(void *arg) 19743c60ba66SKatsushi Kobayashi { 19753c60ba66SKatsushi Kobayashi struct fwohci_softc *sc = (struct fwohci_softc *)arg; 197677ee030bSHidetoshi Shimokawa u_int32_t stat; 197777ee030bSHidetoshi Shimokawa #if !FWOHCI_TASKQUEUE 197877ee030bSHidetoshi Shimokawa u_int32_t bus_reset = 0; 197977ee030bSHidetoshi Shimokawa #endif 19803c60ba66SKatsushi Kobayashi 19813c60ba66SKatsushi Kobayashi if (!(sc->intmask & OHCI_INT_EN)) { 19823c60ba66SKatsushi Kobayashi /* polling mode */ 19833c60ba66SKatsushi Kobayashi return; 19843c60ba66SKatsushi Kobayashi } 19853c60ba66SKatsushi Kobayashi 198677ee030bSHidetoshi Shimokawa #if !FWOHCI_TASKQUEUE 198777ee030bSHidetoshi Shimokawa again: 19883c60ba66SKatsushi Kobayashi #endif 198977ee030bSHidetoshi Shimokawa stat = fwochi_check_stat(sc); 199077ee030bSHidetoshi Shimokawa if (stat == 0 || stat == 0xffffffff) 199177ee030bSHidetoshi Shimokawa return; 199277ee030bSHidetoshi Shimokawa #if FWOHCI_TASKQUEUE 199377ee030bSHidetoshi Shimokawa atomic_set_int(&sc->intstat, stat); 199477ee030bSHidetoshi Shimokawa /* XXX mask bus reset intr. during bus reset phase */ 199577ee030bSHidetoshi Shimokawa if (stat) 199677ee030bSHidetoshi Shimokawa taskqueue_enqueue(taskqueue_swi_giant, &sc->fwohci_task_complete); 199777ee030bSHidetoshi Shimokawa #else 19981adf6842SHidetoshi Shimokawa /* We cannot clear bus reset event during bus reset phase */ 19991adf6842SHidetoshi Shimokawa if ((stat & ~bus_reset) == 0) 20001adf6842SHidetoshi Shimokawa return; 20011adf6842SHidetoshi Shimokawa bus_reset = stat & OHCI_INT_PHY_BUS_R; 2002783058faSHidetoshi Shimokawa fwohci_intr_body(sc, stat, -1); 200377ee030bSHidetoshi Shimokawa goto again; 200477ee030bSHidetoshi Shimokawa #endif 20053c60ba66SKatsushi Kobayashi } 20063c60ba66SKatsushi Kobayashi 20073c60ba66SKatsushi Kobayashi static void 20083c60ba66SKatsushi Kobayashi fwohci_poll(struct firewire_comm *fc, int quick, int count) 20093c60ba66SKatsushi Kobayashi { 20103c60ba66SKatsushi Kobayashi int s; 20113c60ba66SKatsushi Kobayashi u_int32_t stat; 20123c60ba66SKatsushi Kobayashi struct fwohci_softc *sc; 20133c60ba66SKatsushi Kobayashi 20143c60ba66SKatsushi Kobayashi 20153c60ba66SKatsushi Kobayashi sc = (struct fwohci_softc *)fc; 20163c60ba66SKatsushi Kobayashi stat = OHCI_INT_DMA_IR | OHCI_INT_DMA_IT | 20173c60ba66SKatsushi Kobayashi OHCI_INT_DMA_PRRS | OHCI_INT_DMA_PRRQ | 20183c60ba66SKatsushi Kobayashi OHCI_INT_DMA_ATRQ | OHCI_INT_DMA_ATRS; 20193c60ba66SKatsushi Kobayashi #if 0 20203c60ba66SKatsushi Kobayashi if (!quick) { 20213c60ba66SKatsushi Kobayashi #else 20223c60ba66SKatsushi Kobayashi if (1) { 20233c60ba66SKatsushi Kobayashi #endif 202477ee030bSHidetoshi Shimokawa stat = fwochi_check_stat(sc); 202577ee030bSHidetoshi Shimokawa if (stat == 0 || stat == 0xffffffff) 20263c60ba66SKatsushi Kobayashi return; 20273c60ba66SKatsushi Kobayashi } 20283c60ba66SKatsushi Kobayashi s = splfw(); 2029783058faSHidetoshi Shimokawa fwohci_intr_body(sc, stat, count); 20303c60ba66SKatsushi Kobayashi splx(s); 20313c60ba66SKatsushi Kobayashi } 20323c60ba66SKatsushi Kobayashi 20333c60ba66SKatsushi Kobayashi static void 20343c60ba66SKatsushi Kobayashi fwohci_set_intr(struct firewire_comm *fc, int enable) 20353c60ba66SKatsushi Kobayashi { 20363c60ba66SKatsushi Kobayashi struct fwohci_softc *sc; 20373c60ba66SKatsushi Kobayashi 20383c60ba66SKatsushi Kobayashi sc = (struct fwohci_softc *)fc; 203917c3d42cSHidetoshi Shimokawa if (bootverbose) 20409339321dSHidetoshi Shimokawa device_printf(sc->fc.dev, "fwohci_set_intr: %d\n", enable); 20413c60ba66SKatsushi Kobayashi if (enable) { 20423c60ba66SKatsushi Kobayashi sc->intmask |= OHCI_INT_EN; 20433c60ba66SKatsushi Kobayashi OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_EN); 20443c60ba66SKatsushi Kobayashi } else { 20453c60ba66SKatsushi Kobayashi sc->intmask &= ~OHCI_INT_EN; 20463c60ba66SKatsushi Kobayashi OWRITE(sc, FWOHCI_INTMASKCLR, OHCI_INT_EN); 20473c60ba66SKatsushi Kobayashi } 20483c60ba66SKatsushi Kobayashi } 20493c60ba66SKatsushi Kobayashi 2050c572b810SHidetoshi Shimokawa static void 2051c572b810SHidetoshi Shimokawa fwohci_tbuf_update(struct fwohci_softc *sc, int dmach) 20523c60ba66SKatsushi Kobayashi { 20533c60ba66SKatsushi Kobayashi struct firewire_comm *fc = &sc->fc; 20545a7ba74dSHidetoshi Shimokawa volatile struct fwohcidb *db; 20555a7ba74dSHidetoshi Shimokawa struct fw_bulkxfer *chunk; 20565a7ba74dSHidetoshi Shimokawa struct fw_xferq *it; 20575a7ba74dSHidetoshi Shimokawa u_int32_t stat, count; 205877ee030bSHidetoshi Shimokawa int s, w=0, ldesc; 20593c60ba66SKatsushi Kobayashi 20605a7ba74dSHidetoshi Shimokawa it = fc->it[dmach]; 206177ee030bSHidetoshi Shimokawa ldesc = sc->it[dmach].ndesc - 1; 20625a7ba74dSHidetoshi Shimokawa s = splfw(); /* unnecessary ? */ 206377ee030bSHidetoshi Shimokawa fwdma_sync_multiseg_all(sc->it[dmach].am, BUS_DMASYNC_POSTREAD); 20645a7ba74dSHidetoshi Shimokawa while ((chunk = STAILQ_FIRST(&it->stdma)) != NULL) { 20655a7ba74dSHidetoshi Shimokawa db = ((struct fwohcidb_tr *)(chunk->end))->db; 206677ee030bSHidetoshi Shimokawa stat = FWOHCI_DMA_READ(db[ldesc].db.desc.res) 206777ee030bSHidetoshi Shimokawa >> OHCI_STATUS_SHIFT; 20685a7ba74dSHidetoshi Shimokawa db = ((struct fwohcidb_tr *)(chunk->start))->db; 206977ee030bSHidetoshi Shimokawa count = FWOHCI_DMA_READ(db[ldesc].db.desc.res) 207077ee030bSHidetoshi Shimokawa & OHCI_COUNT_MASK; 20715a7ba74dSHidetoshi Shimokawa if (stat == 0) 20725a7ba74dSHidetoshi Shimokawa break; 20735a7ba74dSHidetoshi Shimokawa STAILQ_REMOVE_HEAD(&it->stdma, link); 20745a7ba74dSHidetoshi Shimokawa switch (stat & FWOHCIEV_MASK){ 20753c60ba66SKatsushi Kobayashi case FWOHCIEV_ACKCOMPL: 20765a7ba74dSHidetoshi Shimokawa #if 0 20775a7ba74dSHidetoshi Shimokawa device_printf(fc->dev, "0x%08x\n", count); 20780aaa9a23SHidetoshi Shimokawa #endif 20793c60ba66SKatsushi Kobayashi break; 20803c60ba66SKatsushi Kobayashi default: 20815a7ba74dSHidetoshi Shimokawa device_printf(fc->dev, 208277ee030bSHidetoshi Shimokawa "Isochronous transmit err %02x(%s)\n", 208377ee030bSHidetoshi Shimokawa stat, fwohcicode[stat & 0x1f]); 20843c60ba66SKatsushi Kobayashi } 20855a7ba74dSHidetoshi Shimokawa STAILQ_INSERT_TAIL(&it->stfree, chunk, link); 20865a7ba74dSHidetoshi Shimokawa w++; 20875a7ba74dSHidetoshi Shimokawa } 20885a7ba74dSHidetoshi Shimokawa splx(s); 20895a7ba74dSHidetoshi Shimokawa if (w) 20905a7ba74dSHidetoshi Shimokawa wakeup(it); 20913c60ba66SKatsushi Kobayashi } 2092c572b810SHidetoshi Shimokawa 2093c572b810SHidetoshi Shimokawa static void 2094c572b810SHidetoshi Shimokawa fwohci_rbuf_update(struct fwohci_softc *sc, int dmach) 20953c60ba66SKatsushi Kobayashi { 20960aaa9a23SHidetoshi Shimokawa struct firewire_comm *fc = &sc->fc; 209777ee030bSHidetoshi Shimokawa volatile struct fwohcidb_tr *db_tr; 20985a7ba74dSHidetoshi Shimokawa struct fw_bulkxfer *chunk; 20995a7ba74dSHidetoshi Shimokawa struct fw_xferq *ir; 21005a7ba74dSHidetoshi Shimokawa u_int32_t stat; 210177ee030bSHidetoshi Shimokawa int s, w=0, ldesc; 21020aaa9a23SHidetoshi Shimokawa 21035a7ba74dSHidetoshi Shimokawa ir = fc->ir[dmach]; 210477ee030bSHidetoshi Shimokawa ldesc = sc->ir[dmach].ndesc - 1; 210577ee030bSHidetoshi Shimokawa #if 0 210677ee030bSHidetoshi Shimokawa dump_db(sc, dmach); 210777ee030bSHidetoshi Shimokawa #endif 21085a7ba74dSHidetoshi Shimokawa s = splfw(); 210977ee030bSHidetoshi Shimokawa fwdma_sync_multiseg_all(sc->ir[dmach].am, BUS_DMASYNC_POSTREAD); 21105a7ba74dSHidetoshi Shimokawa while ((chunk = STAILQ_FIRST(&ir->stdma)) != NULL) { 211177ee030bSHidetoshi Shimokawa db_tr = (struct fwohcidb_tr *)chunk->end; 211277ee030bSHidetoshi Shimokawa stat = FWOHCI_DMA_READ(db_tr->db[ldesc].db.desc.res) 211377ee030bSHidetoshi Shimokawa >> OHCI_STATUS_SHIFT; 21145a7ba74dSHidetoshi Shimokawa if (stat == 0) 21155a7ba74dSHidetoshi Shimokawa break; 211677ee030bSHidetoshi Shimokawa 211777ee030bSHidetoshi Shimokawa if (chunk->mbuf != NULL) { 211877ee030bSHidetoshi Shimokawa bus_dmamap_sync(sc->ir[dmach].dmat, db_tr->dma_map, 211977ee030bSHidetoshi Shimokawa BUS_DMASYNC_POSTREAD); 212077ee030bSHidetoshi Shimokawa bus_dmamap_unload(sc->ir[dmach].dmat, db_tr->dma_map); 212177ee030bSHidetoshi Shimokawa } else if (ir->buf != NULL) { 212277ee030bSHidetoshi Shimokawa fwdma_sync_multiseg(ir->buf, chunk->poffset, 212377ee030bSHidetoshi Shimokawa ir->bnpacket, BUS_DMASYNC_POSTREAD); 212477ee030bSHidetoshi Shimokawa } else { 212577ee030bSHidetoshi Shimokawa /* XXX */ 212677ee030bSHidetoshi Shimokawa printf("fwohci_rbuf_update: this shouldn't happend\n"); 212777ee030bSHidetoshi Shimokawa } 212877ee030bSHidetoshi Shimokawa 21295a7ba74dSHidetoshi Shimokawa STAILQ_REMOVE_HEAD(&ir->stdma, link); 21305a7ba74dSHidetoshi Shimokawa STAILQ_INSERT_TAIL(&ir->stvalid, chunk, link); 21315a7ba74dSHidetoshi Shimokawa switch (stat & FWOHCIEV_MASK) { 21323c60ba66SKatsushi Kobayashi case FWOHCIEV_ACKCOMPL: 21332b4601d1SHidetoshi Shimokawa chunk->resp = 0; 21343c60ba66SKatsushi Kobayashi break; 21353c60ba66SKatsushi Kobayashi default: 21362b4601d1SHidetoshi Shimokawa chunk->resp = EINVAL; 21375a7ba74dSHidetoshi Shimokawa device_printf(fc->dev, 213877ee030bSHidetoshi Shimokawa "Isochronous receive err %02x(%s)\n", 213977ee030bSHidetoshi Shimokawa stat, fwohcicode[stat & 0x1f]); 21403c60ba66SKatsushi Kobayashi } 21415a7ba74dSHidetoshi Shimokawa w++; 21425a7ba74dSHidetoshi Shimokawa } 21435a7ba74dSHidetoshi Shimokawa splx(s); 21442b4601d1SHidetoshi Shimokawa if (w) { 21452b4601d1SHidetoshi Shimokawa if (ir->flag & FWXFERQ_HANDLER) 21462b4601d1SHidetoshi Shimokawa ir->hand(ir); 21472b4601d1SHidetoshi Shimokawa else 21485a7ba74dSHidetoshi Shimokawa wakeup(ir); 21493c60ba66SKatsushi Kobayashi } 21502b4601d1SHidetoshi Shimokawa } 2151c572b810SHidetoshi Shimokawa 2152c572b810SHidetoshi Shimokawa void 2153c572b810SHidetoshi Shimokawa dump_dma(struct fwohci_softc *sc, u_int32_t ch) 2154c572b810SHidetoshi Shimokawa { 21553c60ba66SKatsushi Kobayashi u_int32_t off, cntl, stat, cmd, match; 21563c60ba66SKatsushi Kobayashi 21573c60ba66SKatsushi Kobayashi if(ch == 0){ 21583c60ba66SKatsushi Kobayashi off = OHCI_ATQOFF; 21593c60ba66SKatsushi Kobayashi }else if(ch == 1){ 21603c60ba66SKatsushi Kobayashi off = OHCI_ATSOFF; 21613c60ba66SKatsushi Kobayashi }else if(ch == 2){ 21623c60ba66SKatsushi Kobayashi off = OHCI_ARQOFF; 21633c60ba66SKatsushi Kobayashi }else if(ch == 3){ 21643c60ba66SKatsushi Kobayashi off = OHCI_ARSOFF; 21653c60ba66SKatsushi Kobayashi }else if(ch < IRX_CH){ 21663c60ba66SKatsushi Kobayashi off = OHCI_ITCTL(ch - ITX_CH); 21673c60ba66SKatsushi Kobayashi }else{ 21683c60ba66SKatsushi Kobayashi off = OHCI_IRCTL(ch - IRX_CH); 21693c60ba66SKatsushi Kobayashi } 21703c60ba66SKatsushi Kobayashi cntl = stat = OREAD(sc, off); 21713c60ba66SKatsushi Kobayashi cmd = OREAD(sc, off + 0xc); 21723c60ba66SKatsushi Kobayashi match = OREAD(sc, off + 0x10); 21733c60ba66SKatsushi Kobayashi 217477ee030bSHidetoshi Shimokawa device_printf(sc->fc.dev, "ch %1x cntl:0x%08x cmd:0x%08x match:0x%08x\n", 21753c60ba66SKatsushi Kobayashi ch, 21763c60ba66SKatsushi Kobayashi cntl, 21773c60ba66SKatsushi Kobayashi cmd, 21783c60ba66SKatsushi Kobayashi match); 21793c60ba66SKatsushi Kobayashi stat &= 0xffff ; 218077ee030bSHidetoshi Shimokawa if (stat) { 21813c60ba66SKatsushi Kobayashi device_printf(sc->fc.dev, "dma %d ch:%s%s%s%s%s%s %s(%x)\n", 21823c60ba66SKatsushi Kobayashi ch, 21833c60ba66SKatsushi Kobayashi stat & OHCI_CNTL_DMA_RUN ? "RUN," : "", 21843c60ba66SKatsushi Kobayashi stat & OHCI_CNTL_DMA_WAKE ? "WAKE," : "", 21853c60ba66SKatsushi Kobayashi stat & OHCI_CNTL_DMA_DEAD ? "DEAD," : "", 21863c60ba66SKatsushi Kobayashi stat & OHCI_CNTL_DMA_ACTIVE ? "ACTIVE," : "", 21873c60ba66SKatsushi Kobayashi stat & OHCI_CNTL_DMA_BT ? "BRANCH," : "", 21883c60ba66SKatsushi Kobayashi stat & OHCI_CNTL_DMA_BAD ? "BADDMA," : "", 21893c60ba66SKatsushi Kobayashi fwohcicode[stat & 0x1f], 21903c60ba66SKatsushi Kobayashi stat & 0x1f 21913c60ba66SKatsushi Kobayashi ); 21923c60ba66SKatsushi Kobayashi }else{ 21933c60ba66SKatsushi Kobayashi device_printf(sc->fc.dev, "dma %d ch: Nostat\n", ch); 21943c60ba66SKatsushi Kobayashi } 21953c60ba66SKatsushi Kobayashi } 2196c572b810SHidetoshi Shimokawa 2197c572b810SHidetoshi Shimokawa void 2198c572b810SHidetoshi Shimokawa dump_db(struct fwohci_softc *sc, u_int32_t ch) 2199c572b810SHidetoshi Shimokawa { 22003c60ba66SKatsushi Kobayashi struct fwohci_dbch *dbch; 220177ee030bSHidetoshi Shimokawa struct fwohcidb_tr *cp = NULL, *pp, *np = NULL; 22023c60ba66SKatsushi Kobayashi volatile struct fwohcidb *curr = NULL, *prev, *next = NULL; 22033c60ba66SKatsushi Kobayashi int idb, jdb; 22043c60ba66SKatsushi Kobayashi u_int32_t cmd, off; 22053c60ba66SKatsushi Kobayashi if(ch == 0){ 22063c60ba66SKatsushi Kobayashi off = OHCI_ATQOFF; 22073c60ba66SKatsushi Kobayashi dbch = &sc->atrq; 22083c60ba66SKatsushi Kobayashi }else if(ch == 1){ 22093c60ba66SKatsushi Kobayashi off = OHCI_ATSOFF; 22103c60ba66SKatsushi Kobayashi dbch = &sc->atrs; 22113c60ba66SKatsushi Kobayashi }else if(ch == 2){ 22123c60ba66SKatsushi Kobayashi off = OHCI_ARQOFF; 22133c60ba66SKatsushi Kobayashi dbch = &sc->arrq; 22143c60ba66SKatsushi Kobayashi }else if(ch == 3){ 22153c60ba66SKatsushi Kobayashi off = OHCI_ARSOFF; 22163c60ba66SKatsushi Kobayashi dbch = &sc->arrs; 22173c60ba66SKatsushi Kobayashi }else if(ch < IRX_CH){ 22183c60ba66SKatsushi Kobayashi off = OHCI_ITCTL(ch - ITX_CH); 22193c60ba66SKatsushi Kobayashi dbch = &sc->it[ch - ITX_CH]; 22203c60ba66SKatsushi Kobayashi }else { 22213c60ba66SKatsushi Kobayashi off = OHCI_IRCTL(ch - IRX_CH); 22223c60ba66SKatsushi Kobayashi dbch = &sc->ir[ch - IRX_CH]; 22233c60ba66SKatsushi Kobayashi } 22243c60ba66SKatsushi Kobayashi cmd = OREAD(sc, off + 0xc); 22253c60ba66SKatsushi Kobayashi 22263c60ba66SKatsushi Kobayashi if( dbch->ndb == 0 ){ 22273c60ba66SKatsushi Kobayashi device_printf(sc->fc.dev, "No DB is attached ch=%d\n", ch); 22283c60ba66SKatsushi Kobayashi return; 22293c60ba66SKatsushi Kobayashi } 22303c60ba66SKatsushi Kobayashi pp = dbch->top; 22313c60ba66SKatsushi Kobayashi prev = pp->db; 22323c60ba66SKatsushi Kobayashi for(idb = 0 ; idb < dbch->ndb ; idb ++ ){ 22333c60ba66SKatsushi Kobayashi if(pp == NULL){ 22343c60ba66SKatsushi Kobayashi curr = NULL; 22353c60ba66SKatsushi Kobayashi goto outdb; 22363c60ba66SKatsushi Kobayashi } 22373c60ba66SKatsushi Kobayashi cp = STAILQ_NEXT(pp, link); 22383c60ba66SKatsushi Kobayashi if(cp == NULL){ 22393c60ba66SKatsushi Kobayashi curr = NULL; 22403c60ba66SKatsushi Kobayashi goto outdb; 22413c60ba66SKatsushi Kobayashi } 22423c60ba66SKatsushi Kobayashi np = STAILQ_NEXT(cp, link); 22433c60ba66SKatsushi Kobayashi for(jdb = 0 ; jdb < dbch->ndesc ; jdb ++ ){ 224477ee030bSHidetoshi Shimokawa if ((cmd & 0xfffffff0) == cp->bus_addr) { 22453c60ba66SKatsushi Kobayashi curr = cp->db; 22463c60ba66SKatsushi Kobayashi if(np != NULL){ 22473c60ba66SKatsushi Kobayashi next = np->db; 22483c60ba66SKatsushi Kobayashi }else{ 22493c60ba66SKatsushi Kobayashi next = NULL; 22503c60ba66SKatsushi Kobayashi } 22513c60ba66SKatsushi Kobayashi goto outdb; 22523c60ba66SKatsushi Kobayashi } 22533c60ba66SKatsushi Kobayashi } 22543c60ba66SKatsushi Kobayashi pp = STAILQ_NEXT(pp, link); 22553c60ba66SKatsushi Kobayashi prev = pp->db; 22563c60ba66SKatsushi Kobayashi } 22573c60ba66SKatsushi Kobayashi outdb: 22583c60ba66SKatsushi Kobayashi if( curr != NULL){ 225977ee030bSHidetoshi Shimokawa #if 0 22603c60ba66SKatsushi Kobayashi printf("Prev DB %d\n", ch); 226177ee030bSHidetoshi Shimokawa print_db(pp, prev, ch, dbch->ndesc); 226277ee030bSHidetoshi Shimokawa #endif 22633c60ba66SKatsushi Kobayashi printf("Current DB %d\n", ch); 226477ee030bSHidetoshi Shimokawa print_db(cp, curr, ch, dbch->ndesc); 226577ee030bSHidetoshi Shimokawa #if 0 22663c60ba66SKatsushi Kobayashi printf("Next DB %d\n", ch); 226777ee030bSHidetoshi Shimokawa print_db(np, next, ch, dbch->ndesc); 226877ee030bSHidetoshi Shimokawa #endif 22693c60ba66SKatsushi Kobayashi }else{ 22703c60ba66SKatsushi Kobayashi printf("dbdump err ch = %d cmd = 0x%08x\n", ch, cmd); 22713c60ba66SKatsushi Kobayashi } 22723c60ba66SKatsushi Kobayashi return; 22733c60ba66SKatsushi Kobayashi } 2274c572b810SHidetoshi Shimokawa 2275c572b810SHidetoshi Shimokawa void 227677ee030bSHidetoshi Shimokawa print_db(struct fwohcidb_tr *db_tr, volatile struct fwohcidb *db, 227777ee030bSHidetoshi Shimokawa u_int32_t ch, u_int32_t max) 2278c572b810SHidetoshi Shimokawa { 22793c60ba66SKatsushi Kobayashi fwohcireg_t stat; 22803c60ba66SKatsushi Kobayashi int i, key; 228177ee030bSHidetoshi Shimokawa u_int32_t cmd, res; 22823c60ba66SKatsushi Kobayashi 22833c60ba66SKatsushi Kobayashi if(db == NULL){ 22843c60ba66SKatsushi Kobayashi printf("No Descriptor is found\n"); 22853c60ba66SKatsushi Kobayashi return; 22863c60ba66SKatsushi Kobayashi } 22873c60ba66SKatsushi Kobayashi 22883c60ba66SKatsushi Kobayashi printf("ch = %d\n%8s %s %s %s %s %4s %8s %8s %4s:%4s\n", 22893c60ba66SKatsushi Kobayashi ch, 22903c60ba66SKatsushi Kobayashi "Current", 22913c60ba66SKatsushi Kobayashi "OP ", 22923c60ba66SKatsushi Kobayashi "KEY", 22933c60ba66SKatsushi Kobayashi "INT", 22943c60ba66SKatsushi Kobayashi "BR ", 22953c60ba66SKatsushi Kobayashi "len", 22963c60ba66SKatsushi Kobayashi "Addr", 22973c60ba66SKatsushi Kobayashi "Depend", 22983c60ba66SKatsushi Kobayashi "Stat", 22993c60ba66SKatsushi Kobayashi "Cnt"); 23003c60ba66SKatsushi Kobayashi for( i = 0 ; i <= max ; i ++){ 230177ee030bSHidetoshi Shimokawa cmd = FWOHCI_DMA_READ(db[i].db.desc.cmd); 230277ee030bSHidetoshi Shimokawa res = FWOHCI_DMA_READ(db[i].db.desc.res); 230377ee030bSHidetoshi Shimokawa key = cmd & OHCI_KEY_MASK; 230477ee030bSHidetoshi Shimokawa stat = res >> OHCI_STATUS_SHIFT; 2305a4239576SHidetoshi Shimokawa #if __FreeBSD_version >= 500000 230670ce30b5SHidetoshi Shimokawa printf("%08tx %s %s %s %s %5d %08x %08x %04x:%04x", 2307a4239576SHidetoshi Shimokawa #else 2308a4239576SHidetoshi Shimokawa printf("%08x %s %s %s %s %5d %08x %08x %04x:%04x", 2309a4239576SHidetoshi Shimokawa #endif 231077ee030bSHidetoshi Shimokawa db_tr->bus_addr, 231177ee030bSHidetoshi Shimokawa dbcode[(cmd >> 28) & 0xf], 231277ee030bSHidetoshi Shimokawa dbkey[(cmd >> 24) & 0x7], 231377ee030bSHidetoshi Shimokawa dbcond[(cmd >> 20) & 0x3], 231477ee030bSHidetoshi Shimokawa dbcond[(cmd >> 18) & 0x3], 231577ee030bSHidetoshi Shimokawa cmd & OHCI_COUNT_MASK, 231677ee030bSHidetoshi Shimokawa FWOHCI_DMA_READ(db[i].db.desc.addr), 231777ee030bSHidetoshi Shimokawa FWOHCI_DMA_READ(db[i].db.desc.depend), 231877ee030bSHidetoshi Shimokawa stat, 231977ee030bSHidetoshi Shimokawa res & OHCI_COUNT_MASK); 23203c60ba66SKatsushi Kobayashi if(stat & 0xff00){ 23213c60ba66SKatsushi Kobayashi printf(" %s%s%s%s%s%s %s(%x)\n", 23223c60ba66SKatsushi Kobayashi stat & OHCI_CNTL_DMA_RUN ? "RUN," : "", 23233c60ba66SKatsushi Kobayashi stat & OHCI_CNTL_DMA_WAKE ? "WAKE," : "", 23243c60ba66SKatsushi Kobayashi stat & OHCI_CNTL_DMA_DEAD ? "DEAD," : "", 23253c60ba66SKatsushi Kobayashi stat & OHCI_CNTL_DMA_ACTIVE ? "ACTIVE," : "", 23263c60ba66SKatsushi Kobayashi stat & OHCI_CNTL_DMA_BT ? "BRANCH," : "", 23273c60ba66SKatsushi Kobayashi stat & OHCI_CNTL_DMA_BAD ? "BADDMA," : "", 23283c60ba66SKatsushi Kobayashi fwohcicode[stat & 0x1f], 23293c60ba66SKatsushi Kobayashi stat & 0x1f 23303c60ba66SKatsushi Kobayashi ); 23313c60ba66SKatsushi Kobayashi }else{ 23323c60ba66SKatsushi Kobayashi printf(" Nostat\n"); 23333c60ba66SKatsushi Kobayashi } 23343c60ba66SKatsushi Kobayashi if(key == OHCI_KEY_ST2 ){ 23353c60ba66SKatsushi Kobayashi printf("0x%08x 0x%08x 0x%08x 0x%08x\n", 233677ee030bSHidetoshi Shimokawa FWOHCI_DMA_READ(db[i+1].db.immed[0]), 233777ee030bSHidetoshi Shimokawa FWOHCI_DMA_READ(db[i+1].db.immed[1]), 233877ee030bSHidetoshi Shimokawa FWOHCI_DMA_READ(db[i+1].db.immed[2]), 233977ee030bSHidetoshi Shimokawa FWOHCI_DMA_READ(db[i+1].db.immed[3])); 23403c60ba66SKatsushi Kobayashi } 23413c60ba66SKatsushi Kobayashi if(key == OHCI_KEY_DEVICE){ 23423c60ba66SKatsushi Kobayashi return; 23433c60ba66SKatsushi Kobayashi } 234477ee030bSHidetoshi Shimokawa if((cmd & OHCI_BRANCH_MASK) 23453c60ba66SKatsushi Kobayashi == OHCI_BRANCH_ALWAYS){ 23463c60ba66SKatsushi Kobayashi return; 23473c60ba66SKatsushi Kobayashi } 234877ee030bSHidetoshi Shimokawa if((cmd & OHCI_CMD_MASK) 23493c60ba66SKatsushi Kobayashi == OHCI_OUTPUT_LAST){ 23503c60ba66SKatsushi Kobayashi return; 23513c60ba66SKatsushi Kobayashi } 235277ee030bSHidetoshi Shimokawa if((cmd & OHCI_CMD_MASK) 23533c60ba66SKatsushi Kobayashi == OHCI_INPUT_LAST){ 23543c60ba66SKatsushi Kobayashi return; 23553c60ba66SKatsushi Kobayashi } 23563c60ba66SKatsushi Kobayashi if(key == OHCI_KEY_ST2 ){ 23573c60ba66SKatsushi Kobayashi i++; 23583c60ba66SKatsushi Kobayashi } 23593c60ba66SKatsushi Kobayashi } 23603c60ba66SKatsushi Kobayashi return; 23613c60ba66SKatsushi Kobayashi } 2362c572b810SHidetoshi Shimokawa 2363c572b810SHidetoshi Shimokawa void 2364c572b810SHidetoshi Shimokawa fwohci_ibr(struct firewire_comm *fc) 23653c60ba66SKatsushi Kobayashi { 23663c60ba66SKatsushi Kobayashi struct fwohci_softc *sc; 23673c60ba66SKatsushi Kobayashi u_int32_t fun; 23683c60ba66SKatsushi Kobayashi 2369864d7e72SHidetoshi Shimokawa device_printf(fc->dev, "Initiate bus reset\n"); 23703c60ba66SKatsushi Kobayashi sc = (struct fwohci_softc *)fc; 2371ac9f6692SHidetoshi Shimokawa 2372ac9f6692SHidetoshi Shimokawa /* 2373ac9f6692SHidetoshi Shimokawa * Set root hold-off bit so that non cyclemaster capable node 2374ac9f6692SHidetoshi Shimokawa * shouldn't became the root node. 2375ac9f6692SHidetoshi Shimokawa */ 23763c60ba66SKatsushi Kobayashi #if 1 23773c60ba66SKatsushi Kobayashi fun = fwphy_rddata(sc, FW_PHY_IBR_REG); 23784ed65ce9SHidetoshi Shimokawa fun |= FW_PHY_IBR | FW_PHY_RHB; 23793c60ba66SKatsushi Kobayashi fun = fwphy_wrdata(sc, FW_PHY_IBR_REG, fun); 23804ed65ce9SHidetoshi Shimokawa #else /* Short bus reset */ 23813c60ba66SKatsushi Kobayashi fun = fwphy_rddata(sc, FW_PHY_ISBR_REG); 23824ed65ce9SHidetoshi Shimokawa fun |= FW_PHY_ISBR | FW_PHY_RHB; 23833c60ba66SKatsushi Kobayashi fun = fwphy_wrdata(sc, FW_PHY_ISBR_REG, fun); 23843c60ba66SKatsushi Kobayashi #endif 23853c60ba66SKatsushi Kobayashi } 2386c572b810SHidetoshi Shimokawa 2387c572b810SHidetoshi Shimokawa void 2388c572b810SHidetoshi Shimokawa fwohci_txbufdb(struct fwohci_softc *sc, int dmach, struct fw_bulkxfer *bulkxfer) 23893c60ba66SKatsushi Kobayashi { 23903c60ba66SKatsushi Kobayashi struct fwohcidb_tr *db_tr, *fdb_tr; 23913c60ba66SKatsushi Kobayashi struct fwohci_dbch *dbch; 239253f1eb86SHidetoshi Shimokawa volatile struct fwohcidb *db; 23933c60ba66SKatsushi Kobayashi struct fw_pkt *fp; 23943c60ba66SKatsushi Kobayashi volatile struct fwohci_txpkthdr *ohcifp; 23953c60ba66SKatsushi Kobayashi unsigned short chtag; 23963c60ba66SKatsushi Kobayashi int idb; 23973c60ba66SKatsushi Kobayashi 23983c60ba66SKatsushi Kobayashi dbch = &sc->it[dmach]; 23993c60ba66SKatsushi Kobayashi chtag = sc->it[dmach].xferq.flag & 0xff; 24003c60ba66SKatsushi Kobayashi 24013c60ba66SKatsushi Kobayashi db_tr = (struct fwohcidb_tr *)(bulkxfer->start); 24023c60ba66SKatsushi Kobayashi fdb_tr = (struct fwohcidb_tr *)(bulkxfer->end); 24033c60ba66SKatsushi Kobayashi /* 240477ee030bSHidetoshi Shimokawa device_printf(sc->fc.dev, "DB %08x %08x %08x\n", bulkxfer, db_tr->bus_addr, fdb_tr->bus_addr); 24053c60ba66SKatsushi Kobayashi */ 240677ee030bSHidetoshi Shimokawa for (idb = 0; idb < dbch->xferq.bnpacket; idb ++) { 240753f1eb86SHidetoshi Shimokawa db = db_tr->db; 24083c60ba66SKatsushi Kobayashi fp = (struct fw_pkt *)db_tr->buf; 240953f1eb86SHidetoshi Shimokawa ohcifp = (volatile struct fwohci_txpkthdr *) db[1].db.immed; 241077ee030bSHidetoshi Shimokawa ohcifp->mode.ld[0] = fp->mode.ld[0]; 241177ee030bSHidetoshi Shimokawa ohcifp->mode.stream.len = fp->mode.stream.len; 24123c60ba66SKatsushi Kobayashi ohcifp->mode.stream.chtag = chtag; 24133c60ba66SKatsushi Kobayashi ohcifp->mode.stream.tcode = 0xa; 24145a7ba74dSHidetoshi Shimokawa ohcifp->mode.stream.spd = 0; 241577ee030bSHidetoshi Shimokawa #if BYTE_ORDER == BIG_ENDIAN 241677ee030bSHidetoshi Shimokawa FWOHCI_DMA_WRITE(db[1].db.immed[0], db[1].db.immed[0]); 241777ee030bSHidetoshi Shimokawa FWOHCI_DMA_WRITE(db[1].db.immed[1], db[1].db.immed[1]); 241877ee030bSHidetoshi Shimokawa #endif 24193c60ba66SKatsushi Kobayashi 242077ee030bSHidetoshi Shimokawa FWOHCI_DMA_CLEAR(db[2].db.desc.cmd, OHCI_COUNT_MASK); 242177ee030bSHidetoshi Shimokawa FWOHCI_DMA_SET(db[2].db.desc.cmd, fp->mode.stream.len); 242277ee030bSHidetoshi Shimokawa FWOHCI_DMA_WRITE(db[2].db.desc.res, 0); 242353f1eb86SHidetoshi Shimokawa #if 0 /* if bulkxfer->npackets changes */ 242477ee030bSHidetoshi Shimokawa db[2].db.desc.cmd = OHCI_OUTPUT_LAST 24253c60ba66SKatsushi Kobayashi | OHCI_UPDATE 242653f1eb86SHidetoshi Shimokawa | OHCI_BRANCH_ALWAYS; 242753f1eb86SHidetoshi Shimokawa db[0].db.desc.depend = 242853f1eb86SHidetoshi Shimokawa = db[dbch->ndesc - 1].db.desc.depend 242977ee030bSHidetoshi Shimokawa = STAILQ_NEXT(db_tr, link)->bus_addr | dbch->ndesc; 243053f1eb86SHidetoshi Shimokawa #else 243177ee030bSHidetoshi Shimokawa FWOHCI_DMA_SET(db[0].db.desc.depend, dbch->ndesc); 243277ee030bSHidetoshi Shimokawa FWOHCI_DMA_SET(db[dbch->ndesc - 1].db.desc.depend, dbch->ndesc); 243353f1eb86SHidetoshi Shimokawa #endif 24343c60ba66SKatsushi Kobayashi bulkxfer->end = (caddr_t)db_tr; 24353c60ba66SKatsushi Kobayashi db_tr = STAILQ_NEXT(db_tr, link); 24363c60ba66SKatsushi Kobayashi } 243753f1eb86SHidetoshi Shimokawa db = ((struct fwohcidb_tr *)bulkxfer->end)->db; 243877ee030bSHidetoshi Shimokawa FWOHCI_DMA_CLEAR(db[0].db.desc.depend, 0xf); 243977ee030bSHidetoshi Shimokawa FWOHCI_DMA_CLEAR(db[dbch->ndesc - 1].db.desc.depend, 0xf); 244053f1eb86SHidetoshi Shimokawa #if 0 /* if bulkxfer->npackets changes */ 244153f1eb86SHidetoshi Shimokawa db[dbch->ndesc - 1].db.desc.control |= OHCI_INTERRUPT_ALWAYS; 24424ed65ce9SHidetoshi Shimokawa /* OHCI 1.1 and above */ 244353f1eb86SHidetoshi Shimokawa db[0].db.desc.control |= OHCI_INTERRUPT_ALWAYS; 244453f1eb86SHidetoshi Shimokawa #endif 244553f1eb86SHidetoshi Shimokawa /* 24463c60ba66SKatsushi Kobayashi db_tr = (struct fwohcidb_tr *)bulkxfer->start; 24473c60ba66SKatsushi Kobayashi fdb_tr = (struct fwohcidb_tr *)bulkxfer->end; 244877ee030bSHidetoshi Shimokawa device_printf(sc->fc.dev, "DB %08x %3d %08x %08x\n", bulkxfer, bulkxfer->npacket, db_tr->bus_addr, fdb_tr->bus_addr); 24493c60ba66SKatsushi Kobayashi */ 24503c60ba66SKatsushi Kobayashi return; 24513c60ba66SKatsushi Kobayashi } 2452c572b810SHidetoshi Shimokawa 2453c572b810SHidetoshi Shimokawa static int 245477ee030bSHidetoshi Shimokawa fwohci_add_tx_buf(struct fwohci_dbch *dbch, struct fwohcidb_tr *db_tr, 245577ee030bSHidetoshi Shimokawa int poffset) 24563c60ba66SKatsushi Kobayashi { 24573c60ba66SKatsushi Kobayashi volatile struct fwohcidb *db = db_tr->db; 245877ee030bSHidetoshi Shimokawa struct fw_xferq *it; 24593c60ba66SKatsushi Kobayashi int err = 0; 246077ee030bSHidetoshi Shimokawa 246177ee030bSHidetoshi Shimokawa it = &dbch->xferq; 246277ee030bSHidetoshi Shimokawa if(it->buf == 0){ 24633c60ba66SKatsushi Kobayashi err = EINVAL; 24643c60ba66SKatsushi Kobayashi return err; 24653c60ba66SKatsushi Kobayashi } 246677ee030bSHidetoshi Shimokawa db_tr->buf = fwdma_v_addr(it->buf, poffset); 24673c60ba66SKatsushi Kobayashi db_tr->dbcnt = 3; 24683c60ba66SKatsushi Kobayashi 246977ee030bSHidetoshi Shimokawa FWOHCI_DMA_WRITE(db[0].db.desc.cmd, 247077ee030bSHidetoshi Shimokawa OHCI_OUTPUT_MORE | OHCI_KEY_ST2 | 8); 247177ee030bSHidetoshi Shimokawa FWOHCI_DMA_WRITE(db[2].db.desc.addr, 247277ee030bSHidetoshi Shimokawa fwdma_bus_addr(it->buf, poffset) + sizeof(u_int32_t)); 247377ee030bSHidetoshi Shimokawa 247477ee030bSHidetoshi Shimokawa FWOHCI_DMA_WRITE(db[2].db.desc.cmd, 247577ee030bSHidetoshi Shimokawa OHCI_OUTPUT_LAST | OHCI_UPDATE | OHCI_BRANCH_ALWAYS); 247653f1eb86SHidetoshi Shimokawa #if 1 247777ee030bSHidetoshi Shimokawa FWOHCI_DMA_WRITE(db[0].db.desc.res, 0); 247877ee030bSHidetoshi Shimokawa FWOHCI_DMA_WRITE(db[2].db.desc.res, 0); 247953f1eb86SHidetoshi Shimokawa #endif 248077ee030bSHidetoshi Shimokawa return 0; 24813c60ba66SKatsushi Kobayashi } 2482c572b810SHidetoshi Shimokawa 2483c572b810SHidetoshi Shimokawa int 248477ee030bSHidetoshi Shimokawa fwohci_add_rx_buf(struct fwohci_dbch *dbch, struct fwohcidb_tr *db_tr, 248577ee030bSHidetoshi Shimokawa int poffset, struct fwdma_alloc *dummy_dma) 24863c60ba66SKatsushi Kobayashi { 24873c60ba66SKatsushi Kobayashi volatile struct fwohcidb *db = db_tr->db; 248877ee030bSHidetoshi Shimokawa struct fw_xferq *ir; 248977ee030bSHidetoshi Shimokawa int i, ldesc; 249077ee030bSHidetoshi Shimokawa bus_addr_t dbuf[2]; 24913c60ba66SKatsushi Kobayashi int dsiz[2]; 24923c60ba66SKatsushi Kobayashi 249377ee030bSHidetoshi Shimokawa ir = &dbch->xferq; 249477ee030bSHidetoshi Shimokawa if (ir->buf == NULL && (dbch->xferq.flag & FWXFERQ_EXTBUF) == 0) { 249577ee030bSHidetoshi Shimokawa db_tr->buf = fwdma_malloc_size(dbch->dmat, &db_tr->dma_map, 249677ee030bSHidetoshi Shimokawa ir->psize, &dbuf[0], BUS_DMA_NOWAIT); 249777ee030bSHidetoshi Shimokawa if (db_tr->buf == NULL) 249877ee030bSHidetoshi Shimokawa return(ENOMEM); 24993c60ba66SKatsushi Kobayashi db_tr->dbcnt = 1; 250077ee030bSHidetoshi Shimokawa dsiz[0] = ir->psize; 250177ee030bSHidetoshi Shimokawa bus_dmamap_sync(dbch->dmat, db_tr->dma_map, 250277ee030bSHidetoshi Shimokawa BUS_DMASYNC_PREREAD); 25033c60ba66SKatsushi Kobayashi } else { 250477ee030bSHidetoshi Shimokawa db_tr->dbcnt = 0; 250577ee030bSHidetoshi Shimokawa if (dummy_dma != NULL) { 250677ee030bSHidetoshi Shimokawa dsiz[db_tr->dbcnt] = sizeof(u_int32_t); 250777ee030bSHidetoshi Shimokawa dbuf[db_tr->dbcnt++] = dummy_dma->bus_addr; 250877ee030bSHidetoshi Shimokawa } 250977ee030bSHidetoshi Shimokawa dsiz[db_tr->dbcnt] = ir->psize; 251077ee030bSHidetoshi Shimokawa if (ir->buf != NULL) { 251177ee030bSHidetoshi Shimokawa db_tr->buf = fwdma_v_addr(ir->buf, poffset); 251277ee030bSHidetoshi Shimokawa dbuf[db_tr->dbcnt] = fwdma_bus_addr( ir->buf, poffset); 251377ee030bSHidetoshi Shimokawa } 251477ee030bSHidetoshi Shimokawa db_tr->dbcnt++; 25153c60ba66SKatsushi Kobayashi } 25163c60ba66SKatsushi Kobayashi for(i = 0 ; i < db_tr->dbcnt ; i++){ 251777ee030bSHidetoshi Shimokawa FWOHCI_DMA_WRITE(db[i].db.desc.addr, dbuf[i]); 251877ee030bSHidetoshi Shimokawa FWOHCI_DMA_WRITE(db[i].db.desc.cmd, OHCI_INPUT_MORE | dsiz[i]); 251977ee030bSHidetoshi Shimokawa if (ir->flag & FWXFERQ_STREAM) { 252077ee030bSHidetoshi Shimokawa FWOHCI_DMA_SET(db[i].db.desc.cmd, OHCI_UPDATE); 25213c60ba66SKatsushi Kobayashi } 252277ee030bSHidetoshi Shimokawa FWOHCI_DMA_WRITE(db[i].db.desc.res, dsiz[i]); 25233c60ba66SKatsushi Kobayashi } 252477ee030bSHidetoshi Shimokawa ldesc = db_tr->dbcnt - 1; 252577ee030bSHidetoshi Shimokawa if (ir->flag & FWXFERQ_STREAM) { 252677ee030bSHidetoshi Shimokawa FWOHCI_DMA_SET(db[ldesc].db.desc.cmd, OHCI_INPUT_LAST); 25273c60ba66SKatsushi Kobayashi } 252877ee030bSHidetoshi Shimokawa FWOHCI_DMA_SET(db[ldesc].db.desc.cmd, OHCI_BRANCH_ALWAYS); 252977ee030bSHidetoshi Shimokawa return 0; 25303c60ba66SKatsushi Kobayashi } 2531c572b810SHidetoshi Shimokawa 253277ee030bSHidetoshi Shimokawa 253377ee030bSHidetoshi Shimokawa static int 253477ee030bSHidetoshi Shimokawa fwohci_arcv_swap(struct fw_pkt *fp, int len) 25353c60ba66SKatsushi Kobayashi { 253677ee030bSHidetoshi Shimokawa struct fw_pkt *fp0; 253777ee030bSHidetoshi Shimokawa u_int32_t ld0; 253877ee030bSHidetoshi Shimokawa int slen; 253977ee030bSHidetoshi Shimokawa #if BYTE_ORDER == BIG_ENDIAN 254077ee030bSHidetoshi Shimokawa int i; 254177ee030bSHidetoshi Shimokawa #endif 25423c60ba66SKatsushi Kobayashi 254377ee030bSHidetoshi Shimokawa ld0 = FWOHCI_DMA_READ(fp->mode.ld[0]); 254477ee030bSHidetoshi Shimokawa #if 0 254577ee030bSHidetoshi Shimokawa printf("ld0: x%08x\n", ld0); 254677ee030bSHidetoshi Shimokawa #endif 254777ee030bSHidetoshi Shimokawa fp0 = (struct fw_pkt *)&ld0; 254877ee030bSHidetoshi Shimokawa switch (fp0->mode.common.tcode) { 254977ee030bSHidetoshi Shimokawa case FWTCODE_RREQQ: 255077ee030bSHidetoshi Shimokawa case FWTCODE_WRES: 255177ee030bSHidetoshi Shimokawa case FWTCODE_WREQQ: 255277ee030bSHidetoshi Shimokawa case FWTCODE_RRESQ: 255377ee030bSHidetoshi Shimokawa case FWOHCITCODE_PHY: 255477ee030bSHidetoshi Shimokawa slen = 12; 25553c60ba66SKatsushi Kobayashi break; 255677ee030bSHidetoshi Shimokawa case FWTCODE_RREQB: 255777ee030bSHidetoshi Shimokawa case FWTCODE_WREQB: 255877ee030bSHidetoshi Shimokawa case FWTCODE_LREQ: 255977ee030bSHidetoshi Shimokawa case FWTCODE_RRESB: 256077ee030bSHidetoshi Shimokawa case FWTCODE_LRES: 256177ee030bSHidetoshi Shimokawa slen = 16; 25623c60ba66SKatsushi Kobayashi break; 25633c60ba66SKatsushi Kobayashi default: 256477ee030bSHidetoshi Shimokawa printf("Unknown tcode %d\n", fp0->mode.common.tcode); 256577ee030bSHidetoshi Shimokawa return(0); 25663c60ba66SKatsushi Kobayashi } 256777ee030bSHidetoshi Shimokawa if (slen > len) { 256877ee030bSHidetoshi Shimokawa if (firewire_debug) 256977ee030bSHidetoshi Shimokawa printf("splitted header\n"); 257077ee030bSHidetoshi Shimokawa return(-slen); 25713c60ba66SKatsushi Kobayashi } 257277ee030bSHidetoshi Shimokawa #if BYTE_ORDER == BIG_ENDIAN 257377ee030bSHidetoshi Shimokawa for(i = 0; i < slen/4; i ++) 257477ee030bSHidetoshi Shimokawa fp->mode.ld[i] = FWOHCI_DMA_READ(fp->mode.ld[i]); 257577ee030bSHidetoshi Shimokawa #endif 257677ee030bSHidetoshi Shimokawa return(slen); 25773c60ba66SKatsushi Kobayashi } 25783c60ba66SKatsushi Kobayashi 257977ee030bSHidetoshi Shimokawa #define PLEN(x) roundup2(x, sizeof(u_int32_t)) 25803c60ba66SKatsushi Kobayashi static int 258177ee030bSHidetoshi Shimokawa fwohci_get_plen(struct fwohci_softc *sc, struct fwohci_dbch *dbch, struct fw_pkt *fp) 25823c60ba66SKatsushi Kobayashi { 258377ee030bSHidetoshi Shimokawa int r; 25843c60ba66SKatsushi Kobayashi 25853c60ba66SKatsushi Kobayashi switch(fp->mode.common.tcode){ 25863c60ba66SKatsushi Kobayashi case FWTCODE_RREQQ: 2587627d85fbSHidetoshi Shimokawa r = sizeof(fp->mode.rreqq) + sizeof(u_int32_t); 2588627d85fbSHidetoshi Shimokawa break; 25893c60ba66SKatsushi Kobayashi case FWTCODE_WRES: 2590627d85fbSHidetoshi Shimokawa r = sizeof(fp->mode.wres) + sizeof(u_int32_t); 2591627d85fbSHidetoshi Shimokawa break; 25923c60ba66SKatsushi Kobayashi case FWTCODE_WREQQ: 2593627d85fbSHidetoshi Shimokawa r = sizeof(fp->mode.wreqq) + sizeof(u_int32_t); 2594627d85fbSHidetoshi Shimokawa break; 25953c60ba66SKatsushi Kobayashi case FWTCODE_RREQB: 2596627d85fbSHidetoshi Shimokawa r = sizeof(fp->mode.rreqb) + sizeof(u_int32_t); 2597627d85fbSHidetoshi Shimokawa break; 25983c60ba66SKatsushi Kobayashi case FWTCODE_RRESQ: 2599627d85fbSHidetoshi Shimokawa r = sizeof(fp->mode.rresq) + sizeof(u_int32_t); 2600627d85fbSHidetoshi Shimokawa break; 26013c60ba66SKatsushi Kobayashi case FWTCODE_WREQB: 2602627d85fbSHidetoshi Shimokawa r = sizeof(struct fw_asyhdr) + PLEN(fp->mode.wreqb.len) 26033c60ba66SKatsushi Kobayashi + sizeof(u_int32_t); 2604627d85fbSHidetoshi Shimokawa break; 26053c60ba66SKatsushi Kobayashi case FWTCODE_LREQ: 2606627d85fbSHidetoshi Shimokawa r = sizeof(struct fw_asyhdr) + PLEN(fp->mode.lreq.len) 26073c60ba66SKatsushi Kobayashi + sizeof(u_int32_t); 2608627d85fbSHidetoshi Shimokawa break; 26093c60ba66SKatsushi Kobayashi case FWTCODE_RRESB: 2610627d85fbSHidetoshi Shimokawa r = sizeof(struct fw_asyhdr) + PLEN(fp->mode.rresb.len) 26113c60ba66SKatsushi Kobayashi + sizeof(u_int32_t); 2612627d85fbSHidetoshi Shimokawa break; 26133c60ba66SKatsushi Kobayashi case FWTCODE_LRES: 2614627d85fbSHidetoshi Shimokawa r = sizeof(struct fw_asyhdr) + PLEN(fp->mode.lres.len) 26153c60ba66SKatsushi Kobayashi + sizeof(u_int32_t); 2616627d85fbSHidetoshi Shimokawa break; 26173c60ba66SKatsushi Kobayashi case FWOHCITCODE_PHY: 2618627d85fbSHidetoshi Shimokawa r = 16; 2619627d85fbSHidetoshi Shimokawa break; 2620627d85fbSHidetoshi Shimokawa default: 2621627d85fbSHidetoshi Shimokawa device_printf(sc->fc.dev, "Unknown tcode %d\n", 2622627d85fbSHidetoshi Shimokawa fp->mode.common.tcode); 2623627d85fbSHidetoshi Shimokawa r = 0; 26243c60ba66SKatsushi Kobayashi } 2625627d85fbSHidetoshi Shimokawa if (r > dbch->xferq.psize) { 2626627d85fbSHidetoshi Shimokawa device_printf(sc->fc.dev, "Invalid packet length %d\n", r); 2627627d85fbSHidetoshi Shimokawa /* panic ? */ 2628627d85fbSHidetoshi Shimokawa } 2629627d85fbSHidetoshi Shimokawa return r; 26303c60ba66SKatsushi Kobayashi } 26313c60ba66SKatsushi Kobayashi 2632c572b810SHidetoshi Shimokawa static void 263377ee030bSHidetoshi Shimokawa fwohci_arcv_free_buf(struct fwohci_dbch *dbch, struct fwohcidb_tr *db_tr) 263477ee030bSHidetoshi Shimokawa { 263577ee030bSHidetoshi Shimokawa volatile struct fwohcidb *db = &db_tr->db[0]; 263677ee030bSHidetoshi Shimokawa 263777ee030bSHidetoshi Shimokawa FWOHCI_DMA_CLEAR(db->db.desc.depend, 0xf); 263877ee030bSHidetoshi Shimokawa FWOHCI_DMA_WRITE(db->db.desc.res, dbch->xferq.psize); 263977ee030bSHidetoshi Shimokawa FWOHCI_DMA_SET(dbch->bottom->db[0].db.desc.depend, 1); 264077ee030bSHidetoshi Shimokawa fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREWRITE); 264177ee030bSHidetoshi Shimokawa dbch->bottom = db_tr; 264277ee030bSHidetoshi Shimokawa } 264377ee030bSHidetoshi Shimokawa 264477ee030bSHidetoshi Shimokawa static void 2645c572b810SHidetoshi Shimokawa fwohci_arcv(struct fwohci_softc *sc, struct fwohci_dbch *dbch, int count) 26463c60ba66SKatsushi Kobayashi { 26473c60ba66SKatsushi Kobayashi struct fwohcidb_tr *db_tr; 264877ee030bSHidetoshi Shimokawa struct iovec vec[2]; 264977ee030bSHidetoshi Shimokawa struct fw_pkt pktbuf; 265077ee030bSHidetoshi Shimokawa int nvec; 26513c60ba66SKatsushi Kobayashi struct fw_pkt *fp; 26523c60ba66SKatsushi Kobayashi u_int8_t *ld; 265377ee030bSHidetoshi Shimokawa u_int32_t stat, off, status; 26543c60ba66SKatsushi Kobayashi u_int spd; 265577ee030bSHidetoshi Shimokawa int len, plen, hlen, pcnt, offset; 26563c60ba66SKatsushi Kobayashi int s; 26573c60ba66SKatsushi Kobayashi caddr_t buf; 26583c60ba66SKatsushi Kobayashi int resCount; 26593c60ba66SKatsushi Kobayashi 26603c60ba66SKatsushi Kobayashi if(&sc->arrq == dbch){ 26613c60ba66SKatsushi Kobayashi off = OHCI_ARQOFF; 26623c60ba66SKatsushi Kobayashi }else if(&sc->arrs == dbch){ 26633c60ba66SKatsushi Kobayashi off = OHCI_ARSOFF; 26643c60ba66SKatsushi Kobayashi }else{ 26653c60ba66SKatsushi Kobayashi return; 26663c60ba66SKatsushi Kobayashi } 26673c60ba66SKatsushi Kobayashi 26683c60ba66SKatsushi Kobayashi s = splfw(); 26693c60ba66SKatsushi Kobayashi db_tr = dbch->top; 26703c60ba66SKatsushi Kobayashi pcnt = 0; 26713c60ba66SKatsushi Kobayashi /* XXX we cannot handle a packet which lies in more than two buf */ 267277ee030bSHidetoshi Shimokawa fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_POSTREAD); 267377ee030bSHidetoshi Shimokawa fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_POSTWRITE); 267477ee030bSHidetoshi Shimokawa status = FWOHCI_DMA_READ(db_tr->db[0].db.desc.res) >> OHCI_STATUS_SHIFT; 267577ee030bSHidetoshi Shimokawa resCount = FWOHCI_DMA_READ(db_tr->db[0].db.desc.res) & OHCI_COUNT_MASK; 267677ee030bSHidetoshi Shimokawa #if 0 267777ee030bSHidetoshi Shimokawa printf("status 0x%04x, resCount 0x%04x\n", status, resCount); 267877ee030bSHidetoshi Shimokawa #endif 267977ee030bSHidetoshi Shimokawa while (status & OHCI_CNTL_DMA_ACTIVE) { 268077ee030bSHidetoshi Shimokawa len = dbch->xferq.psize - resCount; 268177ee030bSHidetoshi Shimokawa ld = (u_int8_t *)db_tr->buf; 268277ee030bSHidetoshi Shimokawa if (dbch->pdb_tr == NULL) { 268377ee030bSHidetoshi Shimokawa len -= dbch->buf_offset; 268477ee030bSHidetoshi Shimokawa ld += dbch->buf_offset; 268577ee030bSHidetoshi Shimokawa } 268677ee030bSHidetoshi Shimokawa if (len > 0) 268777ee030bSHidetoshi Shimokawa bus_dmamap_sync(dbch->dmat, db_tr->dma_map, 268877ee030bSHidetoshi Shimokawa BUS_DMASYNC_POSTREAD); 26893c60ba66SKatsushi Kobayashi while (len > 0 ) { 2690783058faSHidetoshi Shimokawa if (count >= 0 && count-- == 0) 2691783058faSHidetoshi Shimokawa goto out; 269277ee030bSHidetoshi Shimokawa if(dbch->pdb_tr != NULL){ 269377ee030bSHidetoshi Shimokawa /* we have a fragment in previous buffer */ 269477ee030bSHidetoshi Shimokawa int rlen; 26953c60ba66SKatsushi Kobayashi 269677ee030bSHidetoshi Shimokawa offset = dbch->buf_offset; 269777ee030bSHidetoshi Shimokawa if (offset < 0) 269877ee030bSHidetoshi Shimokawa offset = - offset; 269977ee030bSHidetoshi Shimokawa buf = dbch->pdb_tr->buf + offset; 270077ee030bSHidetoshi Shimokawa rlen = dbch->xferq.psize - offset; 270177ee030bSHidetoshi Shimokawa if (firewire_debug) 270277ee030bSHidetoshi Shimokawa printf("rlen=%d, offset=%d\n", 270377ee030bSHidetoshi Shimokawa rlen, dbch->buf_offset); 270477ee030bSHidetoshi Shimokawa if (dbch->buf_offset < 0) { 270577ee030bSHidetoshi Shimokawa /* splitted in header, pull up */ 270677ee030bSHidetoshi Shimokawa char *p; 270777ee030bSHidetoshi Shimokawa 270877ee030bSHidetoshi Shimokawa p = (char *)&pktbuf; 270977ee030bSHidetoshi Shimokawa bcopy(buf, p, rlen); 271077ee030bSHidetoshi Shimokawa p += rlen; 271177ee030bSHidetoshi Shimokawa /* this must be too long but harmless */ 271277ee030bSHidetoshi Shimokawa rlen = sizeof(pktbuf) - rlen; 271377ee030bSHidetoshi Shimokawa if (rlen < 0) 271477ee030bSHidetoshi Shimokawa printf("why rlen < 0\n"); 271577ee030bSHidetoshi Shimokawa bcopy(db_tr->buf, p, rlen); 27163c60ba66SKatsushi Kobayashi ld += rlen; 27173c60ba66SKatsushi Kobayashi len -= rlen; 271877ee030bSHidetoshi Shimokawa hlen = fwohci_arcv_swap(&pktbuf, sizeof(pktbuf)); 271977ee030bSHidetoshi Shimokawa if (hlen < 0) { 272077ee030bSHidetoshi Shimokawa printf("hlen < 0 shouldn't happen"); 27213c60ba66SKatsushi Kobayashi } 272277ee030bSHidetoshi Shimokawa offset = sizeof(pktbuf); 272377ee030bSHidetoshi Shimokawa vec[0].iov_base = (char *)&pktbuf; 272477ee030bSHidetoshi Shimokawa vec[0].iov_len = offset; 27253c60ba66SKatsushi Kobayashi } else { 272677ee030bSHidetoshi Shimokawa /* splitted in payload */ 272777ee030bSHidetoshi Shimokawa offset = rlen; 272877ee030bSHidetoshi Shimokawa vec[0].iov_base = buf; 272977ee030bSHidetoshi Shimokawa vec[0].iov_len = rlen; 273077ee030bSHidetoshi Shimokawa } 273177ee030bSHidetoshi Shimokawa fp=(struct fw_pkt *)vec[0].iov_base; 273277ee030bSHidetoshi Shimokawa nvec = 1; 273377ee030bSHidetoshi Shimokawa } else { 273477ee030bSHidetoshi Shimokawa /* no fragment in previous buffer */ 27353c60ba66SKatsushi Kobayashi fp=(struct fw_pkt *)ld; 273677ee030bSHidetoshi Shimokawa hlen = fwohci_arcv_swap(fp, len); 273777ee030bSHidetoshi Shimokawa if (hlen == 0) 273877ee030bSHidetoshi Shimokawa /* XXX need reset */ 273977ee030bSHidetoshi Shimokawa goto out; 274077ee030bSHidetoshi Shimokawa if (hlen < 0) { 274177ee030bSHidetoshi Shimokawa dbch->pdb_tr = db_tr; 274277ee030bSHidetoshi Shimokawa dbch->buf_offset = - dbch->buf_offset; 274377ee030bSHidetoshi Shimokawa /* sanity check */ 274477ee030bSHidetoshi Shimokawa if (resCount != 0) 274577ee030bSHidetoshi Shimokawa printf("resCount != 0 !?\n"); 27463c60ba66SKatsushi Kobayashi goto out; 27473c60ba66SKatsushi Kobayashi } 274877ee030bSHidetoshi Shimokawa offset = 0; 274977ee030bSHidetoshi Shimokawa nvec = 0; 27503c60ba66SKatsushi Kobayashi } 275177ee030bSHidetoshi Shimokawa plen = fwohci_get_plen(sc, dbch, fp) - offset; 27523c60ba66SKatsushi Kobayashi if (plen < 0) { 275377ee030bSHidetoshi Shimokawa /* minimum header size + trailer 275477ee030bSHidetoshi Shimokawa = sizeof(fw_pkt) so this shouldn't happens */ 275577ee030bSHidetoshi Shimokawa printf("plen is negative! offset=%d\n", offset); 275677ee030bSHidetoshi Shimokawa goto out; 27573c60ba66SKatsushi Kobayashi } 275877ee030bSHidetoshi Shimokawa if (plen > 0) { 275977ee030bSHidetoshi Shimokawa len -= plen; 276077ee030bSHidetoshi Shimokawa if (len < 0) { 276177ee030bSHidetoshi Shimokawa dbch->pdb_tr = db_tr; 276277ee030bSHidetoshi Shimokawa if (firewire_debug) 276377ee030bSHidetoshi Shimokawa printf("splitted payload\n"); 276477ee030bSHidetoshi Shimokawa /* sanity check */ 276577ee030bSHidetoshi Shimokawa if (resCount != 0) 276677ee030bSHidetoshi Shimokawa printf("resCount != 0 !?\n"); 276777ee030bSHidetoshi Shimokawa goto out; 27683c60ba66SKatsushi Kobayashi } 276977ee030bSHidetoshi Shimokawa vec[nvec].iov_base = ld; 277077ee030bSHidetoshi Shimokawa vec[nvec].iov_len = plen; 277177ee030bSHidetoshi Shimokawa nvec ++; 27723c60ba66SKatsushi Kobayashi ld += plen; 27733c60ba66SKatsushi Kobayashi } 277477ee030bSHidetoshi Shimokawa dbch->buf_offset = ld - (u_int8_t *)db_tr->buf; 277577ee030bSHidetoshi Shimokawa if (nvec == 0) 277677ee030bSHidetoshi Shimokawa printf("nvec == 0\n"); 277777ee030bSHidetoshi Shimokawa 27783c60ba66SKatsushi Kobayashi /* DMA result-code will be written at the tail of packet */ 277977ee030bSHidetoshi Shimokawa #if BYTE_ORDER == BIG_ENDIAN 278077ee030bSHidetoshi Shimokawa stat = FWOHCI_DMA_READ(((struct fwohci_trailer *)(ld - sizeof(struct fwohci_trailer)))->stat) >> 16; 278177ee030bSHidetoshi Shimokawa #else 27823c60ba66SKatsushi Kobayashi stat = ((struct fwohci_trailer *)(ld - sizeof(struct fwohci_trailer)))->stat; 278377ee030bSHidetoshi Shimokawa #endif 278477ee030bSHidetoshi Shimokawa #if 0 278577ee030bSHidetoshi Shimokawa printf("plen: %d, stat %x\n", plen ,stat); 278677ee030bSHidetoshi Shimokawa #endif 27873c60ba66SKatsushi Kobayashi spd = (stat >> 5) & 0x3; 27883c60ba66SKatsushi Kobayashi stat &= 0x1f; 27893c60ba66SKatsushi Kobayashi switch(stat){ 27903c60ba66SKatsushi Kobayashi case FWOHCIEV_ACKPEND: 2791864d7e72SHidetoshi Shimokawa #if 0 279273aa55baSHidetoshi Shimokawa printf("fwohci_arcv: ack pending tcode=0x%x..\n", fp->mode.common.tcode); 27933c60ba66SKatsushi Kobayashi #endif 27943c60ba66SKatsushi Kobayashi /* fall through */ 27953c60ba66SKatsushi Kobayashi case FWOHCIEV_ACKCOMPL: 279677ee030bSHidetoshi Shimokawa if ((vec[nvec-1].iov_len -= 279777ee030bSHidetoshi Shimokawa sizeof(struct fwohci_trailer)) == 0) 279877ee030bSHidetoshi Shimokawa nvec--; 279977ee030bSHidetoshi Shimokawa fw_rcv(&sc->fc, vec, nvec, 0, spd); 28003c60ba66SKatsushi Kobayashi break; 28013c60ba66SKatsushi Kobayashi case FWOHCIEV_BUSRST: 28023c60ba66SKatsushi Kobayashi if (sc->fc.status != FWBUSRESET) 28033c60ba66SKatsushi Kobayashi printf("got BUSRST packet!?\n"); 28043c60ba66SKatsushi Kobayashi break; 28053c60ba66SKatsushi Kobayashi default: 28063c60ba66SKatsushi Kobayashi device_printf(sc->fc.dev, "Async DMA Receive error err = %02x %s\n", stat, fwohcicode[stat]); 28073c60ba66SKatsushi Kobayashi #if 0 /* XXX */ 28083c60ba66SKatsushi Kobayashi goto out; 28093c60ba66SKatsushi Kobayashi #endif 28103c60ba66SKatsushi Kobayashi break; 28113c60ba66SKatsushi Kobayashi } 28123c60ba66SKatsushi Kobayashi pcnt ++; 281377ee030bSHidetoshi Shimokawa if (dbch->pdb_tr != NULL) { 281477ee030bSHidetoshi Shimokawa fwohci_arcv_free_buf(dbch, dbch->pdb_tr); 281577ee030bSHidetoshi Shimokawa dbch->pdb_tr = NULL; 281677ee030bSHidetoshi Shimokawa } 281777ee030bSHidetoshi Shimokawa 281877ee030bSHidetoshi Shimokawa } 28193c60ba66SKatsushi Kobayashi out: 28203c60ba66SKatsushi Kobayashi if (resCount == 0) { 28213c60ba66SKatsushi Kobayashi /* done on this buffer */ 282277ee030bSHidetoshi Shimokawa if (dbch->pdb_tr == NULL) { 282377ee030bSHidetoshi Shimokawa fwohci_arcv_free_buf(dbch, db_tr); 28243c60ba66SKatsushi Kobayashi dbch->buf_offset = 0; 282577ee030bSHidetoshi Shimokawa } else 282677ee030bSHidetoshi Shimokawa if (dbch->pdb_tr != db_tr) 282777ee030bSHidetoshi Shimokawa printf("pdb_tr != db_tr\n"); 282877ee030bSHidetoshi Shimokawa db_tr = STAILQ_NEXT(db_tr, link); 282977ee030bSHidetoshi Shimokawa status = FWOHCI_DMA_READ(db_tr->db[0].db.desc.res) 283077ee030bSHidetoshi Shimokawa >> OHCI_STATUS_SHIFT; 283177ee030bSHidetoshi Shimokawa resCount = FWOHCI_DMA_READ(db_tr->db[0].db.desc.res) 283277ee030bSHidetoshi Shimokawa & OHCI_COUNT_MASK; 283377ee030bSHidetoshi Shimokawa /* XXX check buffer overrun */ 283477ee030bSHidetoshi Shimokawa dbch->top = db_tr; 28353c60ba66SKatsushi Kobayashi } else { 28363c60ba66SKatsushi Kobayashi dbch->buf_offset = dbch->xferq.psize - resCount; 28373c60ba66SKatsushi Kobayashi break; 28383c60ba66SKatsushi Kobayashi } 28393c60ba66SKatsushi Kobayashi /* XXX make sure DMA is not dead */ 28403c60ba66SKatsushi Kobayashi } 28413c60ba66SKatsushi Kobayashi #if 0 28423c60ba66SKatsushi Kobayashi if (pcnt < 1) 28433c60ba66SKatsushi Kobayashi printf("fwohci_arcv: no packets\n"); 28443c60ba66SKatsushi Kobayashi #endif 28453c60ba66SKatsushi Kobayashi splx(s); 28463c60ba66SKatsushi Kobayashi } 2847