1 /* 2 * Copyright (c) 2026 Abdelkader Boudih <freebsd@seuros.com> 3 * 4 * SPDX-License-Identifier: BSD-2-Clause 5 */ 6 7 #ifndef _DEV_FIREWIRE_FWDV_H_ 8 #define _DEV_FIREWIRE_FWDV_H_ 9 10 /* FCP (Function Control Protocol) register addresses (IEC 61883-1 9.2) */ 11 #define FCP_COMMAND_ADDR 0xfffff0000b00ULL 12 #define FCP_RESPONSE_ADDR 0xfffff0000d00ULL 13 #define FCP_MAX_FRAME_LEN 512 14 15 /* AV/C command/response type codes (ctype / response, 4-bit) */ 16 #define AVC_CTYPE_CONTROL 0x0 17 #define AVC_CTYPE_STATUS 0x1 18 #define AVC_CTYPE_NOTIFY 0x3 19 20 #define AVC_RESP_NOT_IMPL 0x8 21 #define AVC_RESP_ACCEPTED 0x9 22 #define AVC_RESP_REJECTED 0xa 23 #define AVC_RESP_IN_TRANSITION 0xb 24 #define AVC_RESP_STABLE 0xc 25 #define AVC_RESP_INTERIM 0xf 26 27 /* AV/C subunit types (5-bit) */ 28 #define AVC_SUBUNIT_TAPE 0x04 29 #define AVC_SUBUNIT_UNIT 0x1f 30 31 /* AV/C subunit ID (3-bit) */ 32 #define AVC_SUBUNIT_ID_0 0x00 33 #define AVC_SUBUNIT_ID_IGNORE 0x07 34 35 /* AV/C address byte: subunit_type(5) | subunit_id(3) */ 36 #define AVC_ADDR(type, id) (((type) << 3) | ((id) & 0x07)) 37 #define AVC_ADDR_UNIT AVC_ADDR(AVC_SUBUNIT_UNIT, AVC_SUBUNIT_ID_IGNORE) 38 #define AVC_ADDR_TAPE0 AVC_ADDR(AVC_SUBUNIT_TAPE, AVC_SUBUNIT_ID_0) 39 40 /* AV/C unit commands (opcode) */ 41 #define AVC_OP_UNIT_INFO 0x30 42 #define AVC_OP_SUBUNIT_INFO 0x31 43 #define AVC_OP_VENDOR_DEP 0x00 44 #define AVC_OP_POWER 0xb2 45 46 /* AV/C tape subunit opcodes */ 47 #define AVC_OP_PLAY 0xc3 48 #define AVC_OP_RECORD 0xc2 49 #define AVC_OP_WIND 0xc4 50 #define AVC_OP_TRANSPORT_STATE 0xd0 51 52 /* PLAY operand[0] values */ 53 #define AVC_PLAY_FWD 0x75 54 #define AVC_PLAY_STOP 0x60 55 56 /* WIND operand[0] values */ 57 #define AVC_WIND_FFWD 0x75 58 #define AVC_WIND_REW 0x65 59 #define AVC_WIND_STOP 0x60 60 61 /* TRANSPORT_STATE operand[0] values */ 62 #define AVC_XPORT_PLAY 0x01 63 #define AVC_XPORT_RECORD 0x02 64 #define AVC_XPORT_WIND_FF 0x03 65 #define AVC_XPORT_WIND_REW 0x04 66 #define AVC_XPORT_NO_INFO 0x7f 67 68 /* POWER operand[0] */ 69 #define AVC_POWER_ON 0x70 70 #define AVC_POWER_OFF 0x60 71 72 /* IEEE 1394 CSR register space */ 73 #define CSR_BASE_HI 0xffff 74 #define CSR_BASE_LO 0xf0000000 75 76 /* ISO channel limits */ 77 #define ISO_CHANNEL_MASK 0x3f 78 #define ISO_CHANNEL_MAX 64 79 80 /* IEC 61883 plug control registers (CSR offsets) */ 81 #define PCR_oMPR 0x900 82 #define PCR_oPCR(n) (0x904 + (n) * 4) 83 #define PCR_iMPR 0x980 84 #define PCR_iPCR(n) (0x984 + (n) * 4) 85 86 /* 87 * oPCR register fields (IEC 61883-1 7.5) 88 * 89 * 31 30 29:24 23:16 15:14 13:10 9:0 90 * online bcast n_p2p_conn channel speed overhead_id payload 91 */ 92 #define OPCR_ONLINE (1U << 31) 93 #define OPCR_BCAST (1U << 30) 94 #define OPCR_N_P2P_MASK 0x3f000000 95 #define OPCR_N_P2P_SHIFT 24 96 #define OPCR_CHANNEL_MASK 0x003f0000 97 #define OPCR_CHANNEL_SHIFT 16 98 #define OPCR_SPEED_MASK 0x0000c000 99 #define OPCR_SPEED_SHIFT 14 100 #define OPCR_OVERHEAD_MASK 0x00003c00 101 #define OPCR_OVERHEAD_SHIFT 10 102 #define OPCR_PAYLOAD_MASK 0x000003ff 103 104 /* DV frame sizes */ 105 #define DV_SD_NTSC_FRAME (10 * 150 * 80) /* 120,000 bytes */ 106 #define DV_SD_PAL_FRAME (12 * 150 * 80) /* 144,000 bytes */ 107 #define DV_DVCPRO_HD_FRAME (10 * 250 * 80) /* 200,000 bytes */ 108 109 /* 110 * ioctl interface 111 */ 112 struct fwdv_info { 113 uint8_t state; 114 uint8_t iso_channel; 115 uint8_t dv_system; /* 0=NTSC, 1=PAL, 0xff=unknown */ 116 uint8_t _pad; 117 uint32_t frame_size; 118 uint32_t frame_count; 119 uint32_t frame_dropped; 120 uint32_t eui_hi; /* device EUI-64 high */ 121 uint32_t eui_lo; /* device EUI-64 low */ 122 char vendor[32]; /* from config ROM */ 123 char model[32]; /* from config ROM */ 124 }; 125 126 #define FWDV_GINFO _IOR('D', 1, struct fwdv_info) 127 #define FWDV_PLAY _IO('D', 2) 128 #define FWDV_STOP _IO('D', 3) 129 #define FWDV_FFWD _IO('D', 4) 130 #define FWDV_REW _IO('D', 5) 131 132 /* fwdv state values */ 133 #define FWDV_STATE_IDLE 0 /* no AV/C device found */ 134 #define FWDV_STATE_PROBED 1 /* device found, not streaming */ 135 #define FWDV_STATE_STARTING 2 /* iso_start in progress */ 136 #define FWDV_STATE_STREAMING 3 /* iso receive active */ 137 #define FWDV_STATE_DETACHING 4 138 139 #define DV_DIF_BLOCK_SIZE 80 140 #define FWDV_MAX_FRAME_SIZE DV_DVCPRO_HD_FRAME 141 #define FWDV_ISO_NCHUNK 256 142 #define FWDV_ISO_PKTSIZE 2048 143 #define FWDV_DEFAULT_ISO_CH 63 144 #define FWDV_FCP_XFERS 4 145 146 #ifdef _KERNEL 147 148 struct fwdv_softc { 149 struct firewire_dev_comm fd; 150 struct mtx mtx; 151 struct cdev *cdev; 152 153 struct fw_device *fwdev; 154 uint32_t eui_hi; 155 uint32_t eui_lo; 156 157 struct fw_bind fcp_bind; 158 uint8_t fcp_resp[FCP_MAX_FRAME_LEN]; 159 int fcp_resp_len; 160 int fcp_resp_ready; 161 int avc_busy; 162 163 int iso_active; 164 165 char vendor[32]; 166 char model[32]; 167 168 struct task probe_task; 169 170 int dma_ch; 171 uint8_t iso_channel; 172 173 uint8_t *frame_buf; 174 uint8_t *read_buf; 175 uint32_t frame_size; 176 uint32_t frame_offset; 177 int frame_ready; 178 int read_in_progress; 179 uint32_t frame_count; 180 uint32_t frame_dropped; 181 int open_count; 182 struct selinfo rsel; 183 184 uint8_t dv_system; 185 int dv_detected; 186 187 int state; 188 }; 189 190 #define FWDV_LOCK(sc) mtx_lock(&(sc)->mtx) 191 #define FWDV_UNLOCK(sc) mtx_unlock(&(sc)->mtx) 192 193 #endif /* _KERNEL */ 194 195 #endif /* _DEV_FIREWIRE_FWDV_H_ */ 196