1*23a6997eSAbdelkader Boudih /* 2*23a6997eSAbdelkader Boudih * Copyright (c) 2026 Abdelkader Boudih <freebsd@seuros.com> 3*23a6997eSAbdelkader Boudih * 4*23a6997eSAbdelkader Boudih * SPDX-License-Identifier: BSD-2-Clause 5*23a6997eSAbdelkader Boudih */ 6*23a6997eSAbdelkader Boudih 7*23a6997eSAbdelkader Boudih #ifndef _DEV_FIREWIRE_FWDV_H_ 8*23a6997eSAbdelkader Boudih #define _DEV_FIREWIRE_FWDV_H_ 9*23a6997eSAbdelkader Boudih 10*23a6997eSAbdelkader Boudih /* FCP (Function Control Protocol) register addresses (IEC 61883-1 9.2) */ 11*23a6997eSAbdelkader Boudih #define FCP_COMMAND_ADDR 0xfffff0000b00ULL 12*23a6997eSAbdelkader Boudih #define FCP_RESPONSE_ADDR 0xfffff0000d00ULL 13*23a6997eSAbdelkader Boudih #define FCP_MAX_FRAME_LEN 512 14*23a6997eSAbdelkader Boudih 15*23a6997eSAbdelkader Boudih /* AV/C command/response type codes (ctype / response, 4-bit) */ 16*23a6997eSAbdelkader Boudih #define AVC_CTYPE_CONTROL 0x0 17*23a6997eSAbdelkader Boudih #define AVC_CTYPE_STATUS 0x1 18*23a6997eSAbdelkader Boudih #define AVC_CTYPE_NOTIFY 0x3 19*23a6997eSAbdelkader Boudih 20*23a6997eSAbdelkader Boudih #define AVC_RESP_NOT_IMPL 0x8 21*23a6997eSAbdelkader Boudih #define AVC_RESP_ACCEPTED 0x9 22*23a6997eSAbdelkader Boudih #define AVC_RESP_REJECTED 0xa 23*23a6997eSAbdelkader Boudih #define AVC_RESP_IN_TRANSITION 0xb 24*23a6997eSAbdelkader Boudih #define AVC_RESP_STABLE 0xc 25*23a6997eSAbdelkader Boudih #define AVC_RESP_INTERIM 0xf 26*23a6997eSAbdelkader Boudih 27*23a6997eSAbdelkader Boudih /* AV/C subunit types (5-bit) */ 28*23a6997eSAbdelkader Boudih #define AVC_SUBUNIT_TAPE 0x04 29*23a6997eSAbdelkader Boudih #define AVC_SUBUNIT_UNIT 0x1f 30*23a6997eSAbdelkader Boudih 31*23a6997eSAbdelkader Boudih /* AV/C subunit ID (3-bit) */ 32*23a6997eSAbdelkader Boudih #define AVC_SUBUNIT_ID_0 0x00 33*23a6997eSAbdelkader Boudih #define AVC_SUBUNIT_ID_IGNORE 0x07 34*23a6997eSAbdelkader Boudih 35*23a6997eSAbdelkader Boudih /* AV/C address byte: subunit_type(5) | subunit_id(3) */ 36*23a6997eSAbdelkader Boudih #define AVC_ADDR(type, id) (((type) << 3) | ((id) & 0x07)) 37*23a6997eSAbdelkader Boudih #define AVC_ADDR_UNIT AVC_ADDR(AVC_SUBUNIT_UNIT, AVC_SUBUNIT_ID_IGNORE) 38*23a6997eSAbdelkader Boudih #define AVC_ADDR_TAPE0 AVC_ADDR(AVC_SUBUNIT_TAPE, AVC_SUBUNIT_ID_0) 39*23a6997eSAbdelkader Boudih 40*23a6997eSAbdelkader Boudih /* AV/C unit commands (opcode) */ 41*23a6997eSAbdelkader Boudih #define AVC_OP_UNIT_INFO 0x30 42*23a6997eSAbdelkader Boudih #define AVC_OP_SUBUNIT_INFO 0x31 43*23a6997eSAbdelkader Boudih #define AVC_OP_VENDOR_DEP 0x00 44*23a6997eSAbdelkader Boudih #define AVC_OP_POWER 0xb2 45*23a6997eSAbdelkader Boudih 46*23a6997eSAbdelkader Boudih /* AV/C tape subunit opcodes */ 47*23a6997eSAbdelkader Boudih #define AVC_OP_PLAY 0xc3 48*23a6997eSAbdelkader Boudih #define AVC_OP_RECORD 0xc2 49*23a6997eSAbdelkader Boudih #define AVC_OP_WIND 0xc4 50*23a6997eSAbdelkader Boudih #define AVC_OP_TRANSPORT_STATE 0xd0 51*23a6997eSAbdelkader Boudih 52*23a6997eSAbdelkader Boudih /* PLAY operand[0] values */ 53*23a6997eSAbdelkader Boudih #define AVC_PLAY_FWD 0x75 54*23a6997eSAbdelkader Boudih #define AVC_PLAY_STOP 0x60 55*23a6997eSAbdelkader Boudih 56*23a6997eSAbdelkader Boudih /* WIND operand[0] values */ 57*23a6997eSAbdelkader Boudih #define AVC_WIND_FFWD 0x75 58*23a6997eSAbdelkader Boudih #define AVC_WIND_REW 0x65 59*23a6997eSAbdelkader Boudih #define AVC_WIND_STOP 0x60 60*23a6997eSAbdelkader Boudih 61*23a6997eSAbdelkader Boudih /* TRANSPORT_STATE operand[0] values */ 62*23a6997eSAbdelkader Boudih #define AVC_XPORT_PLAY 0x01 63*23a6997eSAbdelkader Boudih #define AVC_XPORT_RECORD 0x02 64*23a6997eSAbdelkader Boudih #define AVC_XPORT_WIND_FF 0x03 65*23a6997eSAbdelkader Boudih #define AVC_XPORT_WIND_REW 0x04 66*23a6997eSAbdelkader Boudih #define AVC_XPORT_NO_INFO 0x7f 67*23a6997eSAbdelkader Boudih 68*23a6997eSAbdelkader Boudih /* POWER operand[0] */ 69*23a6997eSAbdelkader Boudih #define AVC_POWER_ON 0x70 70*23a6997eSAbdelkader Boudih #define AVC_POWER_OFF 0x60 71*23a6997eSAbdelkader Boudih 72*23a6997eSAbdelkader Boudih /* IEEE 1394 CSR register space */ 73*23a6997eSAbdelkader Boudih #define CSR_BASE_HI 0xffff 74*23a6997eSAbdelkader Boudih #define CSR_BASE_LO 0xf0000000 75*23a6997eSAbdelkader Boudih 76*23a6997eSAbdelkader Boudih /* ISO channel limits */ 77*23a6997eSAbdelkader Boudih #define ISO_CHANNEL_MASK 0x3f 78*23a6997eSAbdelkader Boudih #define ISO_CHANNEL_MAX 64 79*23a6997eSAbdelkader Boudih 80*23a6997eSAbdelkader Boudih /* IEC 61883 plug control registers (CSR offsets) */ 81*23a6997eSAbdelkader Boudih #define PCR_oMPR 0x900 82*23a6997eSAbdelkader Boudih #define PCR_oPCR(n) (0x904 + (n) * 4) 83*23a6997eSAbdelkader Boudih #define PCR_iMPR 0x980 84*23a6997eSAbdelkader Boudih #define PCR_iPCR(n) (0x984 + (n) * 4) 85*23a6997eSAbdelkader Boudih 86*23a6997eSAbdelkader Boudih /* 87*23a6997eSAbdelkader Boudih * oPCR register fields (IEC 61883-1 7.5) 88*23a6997eSAbdelkader Boudih * 89*23a6997eSAbdelkader Boudih * 31 30 29:24 23:16 15:14 13:10 9:0 90*23a6997eSAbdelkader Boudih * online bcast n_p2p_conn channel speed overhead_id payload 91*23a6997eSAbdelkader Boudih */ 92*23a6997eSAbdelkader Boudih #define OPCR_ONLINE (1U << 31) 93*23a6997eSAbdelkader Boudih #define OPCR_BCAST (1U << 30) 94*23a6997eSAbdelkader Boudih #define OPCR_N_P2P_MASK 0x3f000000 95*23a6997eSAbdelkader Boudih #define OPCR_N_P2P_SHIFT 24 96*23a6997eSAbdelkader Boudih #define OPCR_CHANNEL_MASK 0x003f0000 97*23a6997eSAbdelkader Boudih #define OPCR_CHANNEL_SHIFT 16 98*23a6997eSAbdelkader Boudih #define OPCR_SPEED_MASK 0x0000c000 99*23a6997eSAbdelkader Boudih #define OPCR_SPEED_SHIFT 14 100*23a6997eSAbdelkader Boudih #define OPCR_OVERHEAD_MASK 0x00003c00 101*23a6997eSAbdelkader Boudih #define OPCR_OVERHEAD_SHIFT 10 102*23a6997eSAbdelkader Boudih #define OPCR_PAYLOAD_MASK 0x000003ff 103*23a6997eSAbdelkader Boudih 104*23a6997eSAbdelkader Boudih /* DV frame sizes */ 105*23a6997eSAbdelkader Boudih #define DV_SD_NTSC_FRAME (10 * 150 * 80) /* 120,000 bytes */ 106*23a6997eSAbdelkader Boudih #define DV_SD_PAL_FRAME (12 * 150 * 80) /* 144,000 bytes */ 107*23a6997eSAbdelkader Boudih #define DV_DVCPRO_HD_FRAME (10 * 250 * 80) /* 200,000 bytes */ 108*23a6997eSAbdelkader Boudih 109*23a6997eSAbdelkader Boudih /* 110*23a6997eSAbdelkader Boudih * ioctl interface 111*23a6997eSAbdelkader Boudih */ 112*23a6997eSAbdelkader Boudih struct fwdv_info { 113*23a6997eSAbdelkader Boudih uint8_t state; 114*23a6997eSAbdelkader Boudih uint8_t iso_channel; 115*23a6997eSAbdelkader Boudih uint8_t dv_system; /* 0=NTSC, 1=PAL, 0xff=unknown */ 116*23a6997eSAbdelkader Boudih uint8_t _pad; 117*23a6997eSAbdelkader Boudih uint32_t frame_size; 118*23a6997eSAbdelkader Boudih uint32_t frame_count; 119*23a6997eSAbdelkader Boudih uint32_t frame_dropped; 120*23a6997eSAbdelkader Boudih uint32_t eui_hi; /* device EUI-64 high */ 121*23a6997eSAbdelkader Boudih uint32_t eui_lo; /* device EUI-64 low */ 122*23a6997eSAbdelkader Boudih char vendor[32]; /* from config ROM */ 123*23a6997eSAbdelkader Boudih char model[32]; /* from config ROM */ 124*23a6997eSAbdelkader Boudih }; 125*23a6997eSAbdelkader Boudih 126*23a6997eSAbdelkader Boudih #define FWDV_GINFO _IOR('D', 1, struct fwdv_info) 127*23a6997eSAbdelkader Boudih #define FWDV_PLAY _IO('D', 2) 128*23a6997eSAbdelkader Boudih #define FWDV_STOP _IO('D', 3) 129*23a6997eSAbdelkader Boudih #define FWDV_FFWD _IO('D', 4) 130*23a6997eSAbdelkader Boudih #define FWDV_REW _IO('D', 5) 131*23a6997eSAbdelkader Boudih 132*23a6997eSAbdelkader Boudih /* fwdv state values */ 133*23a6997eSAbdelkader Boudih #define FWDV_STATE_IDLE 0 /* no AV/C device found */ 134*23a6997eSAbdelkader Boudih #define FWDV_STATE_PROBED 1 /* device found, not streaming */ 135*23a6997eSAbdelkader Boudih #define FWDV_STATE_STARTING 2 /* iso_start in progress */ 136*23a6997eSAbdelkader Boudih #define FWDV_STATE_STREAMING 3 /* iso receive active */ 137*23a6997eSAbdelkader Boudih #define FWDV_STATE_DETACHING 4 138*23a6997eSAbdelkader Boudih 139*23a6997eSAbdelkader Boudih #define DV_DIF_BLOCK_SIZE 80 140*23a6997eSAbdelkader Boudih #define FWDV_MAX_FRAME_SIZE DV_DVCPRO_HD_FRAME 141*23a6997eSAbdelkader Boudih #define FWDV_ISO_NCHUNK 256 142*23a6997eSAbdelkader Boudih #define FWDV_ISO_PKTSIZE 2048 143*23a6997eSAbdelkader Boudih #define FWDV_DEFAULT_ISO_CH 63 144*23a6997eSAbdelkader Boudih #define FWDV_FCP_XFERS 4 145*23a6997eSAbdelkader Boudih 146*23a6997eSAbdelkader Boudih #ifdef _KERNEL 147*23a6997eSAbdelkader Boudih 148*23a6997eSAbdelkader Boudih struct fwdv_softc { 149*23a6997eSAbdelkader Boudih struct firewire_dev_comm fd; 150*23a6997eSAbdelkader Boudih struct mtx mtx; 151*23a6997eSAbdelkader Boudih struct cdev *cdev; 152*23a6997eSAbdelkader Boudih 153*23a6997eSAbdelkader Boudih struct fw_device *fwdev; 154*23a6997eSAbdelkader Boudih uint32_t eui_hi; 155*23a6997eSAbdelkader Boudih uint32_t eui_lo; 156*23a6997eSAbdelkader Boudih 157*23a6997eSAbdelkader Boudih struct fw_bind fcp_bind; 158*23a6997eSAbdelkader Boudih uint8_t fcp_resp[FCP_MAX_FRAME_LEN]; 159*23a6997eSAbdelkader Boudih int fcp_resp_len; 160*23a6997eSAbdelkader Boudih int fcp_resp_ready; 161*23a6997eSAbdelkader Boudih int avc_busy; 162*23a6997eSAbdelkader Boudih 163*23a6997eSAbdelkader Boudih int iso_active; 164*23a6997eSAbdelkader Boudih 165*23a6997eSAbdelkader Boudih char vendor[32]; 166*23a6997eSAbdelkader Boudih char model[32]; 167*23a6997eSAbdelkader Boudih 168*23a6997eSAbdelkader Boudih struct task probe_task; 169*23a6997eSAbdelkader Boudih 170*23a6997eSAbdelkader Boudih int dma_ch; 171*23a6997eSAbdelkader Boudih uint8_t iso_channel; 172*23a6997eSAbdelkader Boudih 173*23a6997eSAbdelkader Boudih uint8_t *frame_buf; 174*23a6997eSAbdelkader Boudih uint8_t *read_buf; 175*23a6997eSAbdelkader Boudih uint32_t frame_size; 176*23a6997eSAbdelkader Boudih uint32_t frame_offset; 177*23a6997eSAbdelkader Boudih int frame_ready; 178*23a6997eSAbdelkader Boudih int read_in_progress; 179*23a6997eSAbdelkader Boudih uint32_t frame_count; 180*23a6997eSAbdelkader Boudih uint32_t frame_dropped; 181*23a6997eSAbdelkader Boudih int open_count; 182*23a6997eSAbdelkader Boudih struct selinfo rsel; 183*23a6997eSAbdelkader Boudih 184*23a6997eSAbdelkader Boudih uint8_t dv_system; 185*23a6997eSAbdelkader Boudih int dv_detected; 186*23a6997eSAbdelkader Boudih 187*23a6997eSAbdelkader Boudih int state; 188*23a6997eSAbdelkader Boudih }; 189*23a6997eSAbdelkader Boudih 190*23a6997eSAbdelkader Boudih #define FWDV_LOCK(sc) mtx_lock(&(sc)->mtx) 191*23a6997eSAbdelkader Boudih #define FWDV_UNLOCK(sc) mtx_unlock(&(sc)->mtx) 192*23a6997eSAbdelkader Boudih 193*23a6997eSAbdelkader Boudih #endif /* _KERNEL */ 194*23a6997eSAbdelkader Boudih 195*23a6997eSAbdelkader Boudih #endif /* _DEV_FIREWIRE_FWDV_H_ */ 196