1 /*- 2 * Copyright (c) 2013 Ian Lepore <ian@freebsd.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 */ 27 28 #include <sys/cdefs.h> 29 __FBSDID("$FreeBSD$"); 30 31 /* 32 * Driver for Freescale Fast Ethernet Controller, found on imx-series SoCs among 33 * others. Also works for the ENET Gigibit controller found on imx6 and imx28, 34 * but the driver doesn't currently use any of the ENET advanced features other 35 * than enabling gigabit. 36 * 37 * The interface name 'fec' is already taken by netgraph's Fast Etherchannel 38 * (netgraph/ng_fec.c), so we use 'ffec'. 39 * 40 * Requires an FDT entry with at least these properties: 41 * fec: ethernet@02188000 { 42 * compatible = "fsl,imxNN-fec"; 43 * reg = <0x02188000 0x4000>; 44 * interrupts = <150 151>; 45 * phy-mode = "rgmii"; 46 * phy-disable-preamble; // optional 47 * }; 48 * The second interrupt number is for IEEE-1588, and is not currently used; it 49 * need not be present. phy-mode must be one of: "mii", "rmii", "rgmii". 50 * There is also an optional property, phy-disable-preamble, which if present 51 * will disable the preamble bits, cutting the size of each mdio transaction 52 * (and thus the busy-wait time) in half. 53 */ 54 55 #include <sys/param.h> 56 #include <sys/systm.h> 57 #include <sys/bus.h> 58 #include <sys/endian.h> 59 #include <sys/kernel.h> 60 #include <sys/lock.h> 61 #include <sys/malloc.h> 62 #include <sys/mbuf.h> 63 #include <sys/module.h> 64 #include <sys/mutex.h> 65 #include <sys/rman.h> 66 #include <sys/socket.h> 67 #include <sys/sockio.h> 68 #include <sys/sysctl.h> 69 70 #include <machine/bus.h> 71 72 #include <net/bpf.h> 73 #include <net/if.h> 74 #include <net/ethernet.h> 75 #include <net/if_dl.h> 76 #include <net/if_media.h> 77 #include <net/if_types.h> 78 #include <net/if_var.h> 79 #include <net/if_vlan_var.h> 80 81 #include <dev/fdt/fdt_common.h> 82 #include <dev/ffec/if_ffecreg.h> 83 #include <dev/ofw/ofw_bus.h> 84 #include <dev/ofw/ofw_bus_subr.h> 85 #include <dev/mii/mii.h> 86 #include <dev/mii/miivar.h> 87 #include "miibus_if.h" 88 89 /* 90 * There are small differences in the hardware on various SoCs. Not every SoC 91 * we support has its own FECTYPE; most work as GENERIC and only the ones that 92 * need different handling get their own entry. In addition to the types in 93 * this list, there are some flags below that can be ORed into the upper bits. 94 */ 95 enum { 96 FECTYPE_NONE, 97 FECTYPE_GENERIC, 98 FECTYPE_IMX53, 99 FECTYPE_IMX6, 100 FECTYPE_MVF, 101 }; 102 103 /* 104 * Flags that describe general differences between the FEC hardware in various 105 * SoCs. These are ORed into the FECTYPE enum values. 106 */ 107 #define FECTYPE_MASK 0x0000ffff 108 #define FECFLAG_GBE (0x0001 << 16) 109 110 /* 111 * Table of supported FDT compat strings and their associated FECTYPE values. 112 */ 113 static struct ofw_compat_data compat_data[] = { 114 {"fsl,imx51-fec", FECTYPE_GENERIC}, 115 {"fsl,imx53-fec", FECTYPE_IMX53}, 116 {"fsl,imx6q-fec", FECTYPE_IMX6 | FECFLAG_GBE}, 117 {"fsl,imx6ul-fec", FECTYPE_IMX6}, 118 {"fsl,mvf600-fec", FECTYPE_MVF}, 119 {"fsl,mvf-fec", FECTYPE_MVF}, 120 {NULL, FECTYPE_NONE}, 121 }; 122 123 /* 124 * Driver data and defines. 125 */ 126 #define RX_DESC_COUNT 64 127 #define RX_DESC_SIZE (sizeof(struct ffec_hwdesc) * RX_DESC_COUNT) 128 #define TX_DESC_COUNT 64 129 #define TX_DESC_SIZE (sizeof(struct ffec_hwdesc) * TX_DESC_COUNT) 130 131 #define WATCHDOG_TIMEOUT_SECS 5 132 #define STATS_HARVEST_INTERVAL 3 133 134 struct ffec_bufmap { 135 struct mbuf *mbuf; 136 bus_dmamap_t map; 137 }; 138 139 enum { 140 PHY_CONN_UNKNOWN, 141 PHY_CONN_MII, 142 PHY_CONN_RMII, 143 PHY_CONN_RGMII 144 }; 145 146 struct ffec_softc { 147 device_t dev; 148 device_t miibus; 149 struct mii_data * mii_softc; 150 struct ifnet *ifp; 151 int if_flags; 152 struct mtx mtx; 153 struct resource *irq_res; 154 struct resource *mem_res; 155 void * intr_cookie; 156 struct callout ffec_callout; 157 uint8_t phy_conn_type; 158 uint8_t fectype; 159 boolean_t link_is_up; 160 boolean_t is_attached; 161 boolean_t is_detaching; 162 int tx_watchdog_count; 163 int stats_harvest_count; 164 165 bus_dma_tag_t rxdesc_tag; 166 bus_dmamap_t rxdesc_map; 167 struct ffec_hwdesc *rxdesc_ring; 168 bus_addr_t rxdesc_ring_paddr; 169 bus_dma_tag_t rxbuf_tag; 170 struct ffec_bufmap rxbuf_map[RX_DESC_COUNT]; 171 uint32_t rx_idx; 172 173 bus_dma_tag_t txdesc_tag; 174 bus_dmamap_t txdesc_map; 175 struct ffec_hwdesc *txdesc_ring; 176 bus_addr_t txdesc_ring_paddr; 177 bus_dma_tag_t txbuf_tag; 178 struct ffec_bufmap txbuf_map[TX_DESC_COUNT]; 179 uint32_t tx_idx_head; 180 uint32_t tx_idx_tail; 181 int txcount; 182 }; 183 184 #define FFEC_LOCK(sc) mtx_lock(&(sc)->mtx) 185 #define FFEC_UNLOCK(sc) mtx_unlock(&(sc)->mtx) 186 #define FFEC_LOCK_INIT(sc) mtx_init(&(sc)->mtx, \ 187 device_get_nameunit((sc)->dev), MTX_NETWORK_LOCK, MTX_DEF) 188 #define FFEC_LOCK_DESTROY(sc) mtx_destroy(&(sc)->mtx); 189 #define FFEC_ASSERT_LOCKED(sc) mtx_assert(&(sc)->mtx, MA_OWNED); 190 #define FFEC_ASSERT_UNLOCKED(sc) mtx_assert(&(sc)->mtx, MA_NOTOWNED); 191 192 static void ffec_init_locked(struct ffec_softc *sc); 193 static void ffec_stop_locked(struct ffec_softc *sc); 194 static void ffec_txstart_locked(struct ffec_softc *sc); 195 static void ffec_txfinish_locked(struct ffec_softc *sc); 196 197 static inline uint16_t 198 RD2(struct ffec_softc *sc, bus_size_t off) 199 { 200 201 return (bus_read_2(sc->mem_res, off)); 202 } 203 204 static inline void 205 WR2(struct ffec_softc *sc, bus_size_t off, uint16_t val) 206 { 207 208 bus_write_2(sc->mem_res, off, val); 209 } 210 211 static inline uint32_t 212 RD4(struct ffec_softc *sc, bus_size_t off) 213 { 214 215 return (bus_read_4(sc->mem_res, off)); 216 } 217 218 static inline void 219 WR4(struct ffec_softc *sc, bus_size_t off, uint32_t val) 220 { 221 222 bus_write_4(sc->mem_res, off, val); 223 } 224 225 static inline uint32_t 226 next_rxidx(struct ffec_softc *sc, uint32_t curidx) 227 { 228 229 return ((curidx == RX_DESC_COUNT - 1) ? 0 : curidx + 1); 230 } 231 232 static inline uint32_t 233 next_txidx(struct ffec_softc *sc, uint32_t curidx) 234 { 235 236 return ((curidx == TX_DESC_COUNT - 1) ? 0 : curidx + 1); 237 } 238 239 static void 240 ffec_get1paddr(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 241 { 242 243 if (error != 0) 244 return; 245 *(bus_addr_t *)arg = segs[0].ds_addr; 246 } 247 248 static void 249 ffec_miigasket_setup(struct ffec_softc *sc) 250 { 251 uint32_t ifmode; 252 253 /* 254 * We only need the gasket for MII and RMII connections on certain SoCs. 255 */ 256 257 switch (sc->fectype & FECTYPE_MASK) 258 { 259 case FECTYPE_IMX53: 260 break; 261 default: 262 return; 263 } 264 265 switch (sc->phy_conn_type) 266 { 267 case PHY_CONN_MII: 268 ifmode = 0; 269 break; 270 case PHY_CONN_RMII: 271 ifmode = FEC_MIIGSK_CFGR_IF_MODE_RMII; 272 break; 273 default: 274 return; 275 } 276 277 /* 278 * Disable the gasket, configure for either MII or RMII, then enable. 279 */ 280 281 WR2(sc, FEC_MIIGSK_ENR, 0); 282 while (RD2(sc, FEC_MIIGSK_ENR) & FEC_MIIGSK_ENR_READY) 283 continue; 284 285 WR2(sc, FEC_MIIGSK_CFGR, ifmode); 286 287 WR2(sc, FEC_MIIGSK_ENR, FEC_MIIGSK_ENR_EN); 288 while (!(RD2(sc, FEC_MIIGSK_ENR) & FEC_MIIGSK_ENR_READY)) 289 continue; 290 } 291 292 static boolean_t 293 ffec_miibus_iowait(struct ffec_softc *sc) 294 { 295 uint32_t timeout; 296 297 for (timeout = 10000; timeout != 0; --timeout) 298 if (RD4(sc, FEC_IER_REG) & FEC_IER_MII) 299 return (true); 300 301 return (false); 302 } 303 304 static int 305 ffec_miibus_readreg(device_t dev, int phy, int reg) 306 { 307 struct ffec_softc *sc; 308 int val; 309 310 sc = device_get_softc(dev); 311 312 WR4(sc, FEC_IER_REG, FEC_IER_MII); 313 314 WR4(sc, FEC_MMFR_REG, FEC_MMFR_OP_READ | 315 FEC_MMFR_ST_VALUE | FEC_MMFR_TA_VALUE | 316 ((phy << FEC_MMFR_PA_SHIFT) & FEC_MMFR_PA_MASK) | 317 ((reg << FEC_MMFR_RA_SHIFT) & FEC_MMFR_RA_MASK)); 318 319 if (!ffec_miibus_iowait(sc)) { 320 device_printf(dev, "timeout waiting for mii read\n"); 321 return (-1); /* All-ones is a symptom of bad mdio. */ 322 } 323 324 val = RD4(sc, FEC_MMFR_REG) & FEC_MMFR_DATA_MASK; 325 326 return (val); 327 } 328 329 static int 330 ffec_miibus_writereg(device_t dev, int phy, int reg, int val) 331 { 332 struct ffec_softc *sc; 333 334 sc = device_get_softc(dev); 335 336 WR4(sc, FEC_IER_REG, FEC_IER_MII); 337 338 WR4(sc, FEC_MMFR_REG, FEC_MMFR_OP_WRITE | 339 FEC_MMFR_ST_VALUE | FEC_MMFR_TA_VALUE | 340 ((phy << FEC_MMFR_PA_SHIFT) & FEC_MMFR_PA_MASK) | 341 ((reg << FEC_MMFR_RA_SHIFT) & FEC_MMFR_RA_MASK) | 342 (val & FEC_MMFR_DATA_MASK)); 343 344 if (!ffec_miibus_iowait(sc)) { 345 device_printf(dev, "timeout waiting for mii write\n"); 346 return (-1); 347 } 348 349 return (0); 350 } 351 352 static void 353 ffec_miibus_statchg(device_t dev) 354 { 355 struct ffec_softc *sc; 356 struct mii_data *mii; 357 uint32_t ecr, rcr, tcr; 358 359 /* 360 * Called by the MII bus driver when the PHY establishes link to set the 361 * MAC interface registers. 362 */ 363 364 sc = device_get_softc(dev); 365 366 FFEC_ASSERT_LOCKED(sc); 367 368 mii = sc->mii_softc; 369 370 if (mii->mii_media_status & IFM_ACTIVE) 371 sc->link_is_up = true; 372 else 373 sc->link_is_up = false; 374 375 ecr = RD4(sc, FEC_ECR_REG) & ~FEC_ECR_SPEED; 376 rcr = RD4(sc, FEC_RCR_REG) & ~(FEC_RCR_RMII_10T | FEC_RCR_RMII_MODE | 377 FEC_RCR_RGMII_EN | FEC_RCR_DRT | FEC_RCR_FCE); 378 tcr = RD4(sc, FEC_TCR_REG) & ~FEC_TCR_FDEN; 379 380 rcr |= FEC_RCR_MII_MODE; /* Must always be on even for R[G]MII. */ 381 switch (sc->phy_conn_type) { 382 case PHY_CONN_MII: 383 break; 384 case PHY_CONN_RMII: 385 rcr |= FEC_RCR_RMII_MODE; 386 break; 387 case PHY_CONN_RGMII: 388 rcr |= FEC_RCR_RGMII_EN; 389 break; 390 } 391 392 switch (IFM_SUBTYPE(mii->mii_media_active)) { 393 case IFM_1000_T: 394 case IFM_1000_SX: 395 ecr |= FEC_ECR_SPEED; 396 break; 397 case IFM_100_TX: 398 /* Not-FEC_ECR_SPEED + not-FEC_RCR_RMII_10T means 100TX */ 399 break; 400 case IFM_10_T: 401 rcr |= FEC_RCR_RMII_10T; 402 break; 403 case IFM_NONE: 404 sc->link_is_up = false; 405 return; 406 default: 407 sc->link_is_up = false; 408 device_printf(dev, "Unsupported media %u\n", 409 IFM_SUBTYPE(mii->mii_media_active)); 410 return; 411 } 412 413 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) 414 tcr |= FEC_TCR_FDEN; 415 else 416 rcr |= FEC_RCR_DRT; 417 418 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FLOW) != 0) 419 rcr |= FEC_RCR_FCE; 420 421 WR4(sc, FEC_RCR_REG, rcr); 422 WR4(sc, FEC_TCR_REG, tcr); 423 WR4(sc, FEC_ECR_REG, ecr); 424 } 425 426 static void 427 ffec_media_status(struct ifnet * ifp, struct ifmediareq *ifmr) 428 { 429 struct ffec_softc *sc; 430 struct mii_data *mii; 431 432 433 sc = ifp->if_softc; 434 mii = sc->mii_softc; 435 FFEC_LOCK(sc); 436 mii_pollstat(mii); 437 ifmr->ifm_active = mii->mii_media_active; 438 ifmr->ifm_status = mii->mii_media_status; 439 FFEC_UNLOCK(sc); 440 } 441 442 static int 443 ffec_media_change_locked(struct ffec_softc *sc) 444 { 445 446 return (mii_mediachg(sc->mii_softc)); 447 } 448 449 static int 450 ffec_media_change(struct ifnet * ifp) 451 { 452 struct ffec_softc *sc; 453 int error; 454 455 sc = ifp->if_softc; 456 457 FFEC_LOCK(sc); 458 error = ffec_media_change_locked(sc); 459 FFEC_UNLOCK(sc); 460 return (error); 461 } 462 463 static void ffec_clear_stats(struct ffec_softc *sc) 464 { 465 466 WR4(sc, FEC_RMON_R_PACKETS, 0); 467 WR4(sc, FEC_RMON_R_MC_PKT, 0); 468 WR4(sc, FEC_RMON_R_CRC_ALIGN, 0); 469 WR4(sc, FEC_RMON_R_UNDERSIZE, 0); 470 WR4(sc, FEC_RMON_R_OVERSIZE, 0); 471 WR4(sc, FEC_RMON_R_FRAG, 0); 472 WR4(sc, FEC_RMON_R_JAB, 0); 473 WR4(sc, FEC_RMON_T_PACKETS, 0); 474 WR4(sc, FEC_RMON_T_MC_PKT, 0); 475 WR4(sc, FEC_RMON_T_CRC_ALIGN, 0); 476 WR4(sc, FEC_RMON_T_UNDERSIZE, 0); 477 WR4(sc, FEC_RMON_T_OVERSIZE , 0); 478 WR4(sc, FEC_RMON_T_FRAG, 0); 479 WR4(sc, FEC_RMON_T_JAB, 0); 480 WR4(sc, FEC_RMON_T_COL, 0); 481 } 482 483 static void 484 ffec_harvest_stats(struct ffec_softc *sc) 485 { 486 struct ifnet *ifp; 487 488 /* We don't need to harvest too often. */ 489 if (++sc->stats_harvest_count < STATS_HARVEST_INTERVAL) 490 return; 491 492 /* 493 * Try to avoid harvesting unless the IDLE flag is on, but if it has 494 * been too long just go ahead and do it anyway, the worst that'll 495 * happen is we'll lose a packet count or two as we clear at the end. 496 */ 497 if (sc->stats_harvest_count < (2 * STATS_HARVEST_INTERVAL) && 498 ((RD4(sc, FEC_MIBC_REG) & FEC_MIBC_IDLE) == 0)) 499 return; 500 501 sc->stats_harvest_count = 0; 502 ifp = sc->ifp; 503 504 if_inc_counter(ifp, IFCOUNTER_IPACKETS, RD4(sc, FEC_RMON_R_PACKETS)); 505 if_inc_counter(ifp, IFCOUNTER_IMCASTS, RD4(sc, FEC_RMON_R_MC_PKT)); 506 if_inc_counter(ifp, IFCOUNTER_IERRORS, 507 RD4(sc, FEC_RMON_R_CRC_ALIGN) + RD4(sc, FEC_RMON_R_UNDERSIZE) + 508 RD4(sc, FEC_RMON_R_OVERSIZE) + RD4(sc, FEC_RMON_R_FRAG) + 509 RD4(sc, FEC_RMON_R_JAB)); 510 511 if_inc_counter(ifp, IFCOUNTER_OPACKETS, RD4(sc, FEC_RMON_T_PACKETS)); 512 if_inc_counter(ifp, IFCOUNTER_OMCASTS, RD4(sc, FEC_RMON_T_MC_PKT)); 513 if_inc_counter(ifp, IFCOUNTER_OERRORS, 514 RD4(sc, FEC_RMON_T_CRC_ALIGN) + RD4(sc, FEC_RMON_T_UNDERSIZE) + 515 RD4(sc, FEC_RMON_T_OVERSIZE) + RD4(sc, FEC_RMON_T_FRAG) + 516 RD4(sc, FEC_RMON_T_JAB)); 517 518 if_inc_counter(ifp, IFCOUNTER_COLLISIONS, RD4(sc, FEC_RMON_T_COL)); 519 520 ffec_clear_stats(sc); 521 } 522 523 static void 524 ffec_tick(void *arg) 525 { 526 struct ffec_softc *sc; 527 struct ifnet *ifp; 528 int link_was_up; 529 530 sc = arg; 531 532 FFEC_ASSERT_LOCKED(sc); 533 534 ifp = sc->ifp; 535 536 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) 537 return; 538 539 /* 540 * Typical tx watchdog. If this fires it indicates that we enqueued 541 * packets for output and never got a txdone interrupt for them. Maybe 542 * it's a missed interrupt somehow, just pretend we got one. 543 */ 544 if (sc->tx_watchdog_count > 0) { 545 if (--sc->tx_watchdog_count == 0) { 546 ffec_txfinish_locked(sc); 547 } 548 } 549 550 /* Gather stats from hardware counters. */ 551 ffec_harvest_stats(sc); 552 553 /* Check the media status. */ 554 link_was_up = sc->link_is_up; 555 mii_tick(sc->mii_softc); 556 if (sc->link_is_up && !link_was_up) 557 ffec_txstart_locked(sc); 558 559 /* Schedule another check one second from now. */ 560 callout_reset(&sc->ffec_callout, hz, ffec_tick, sc); 561 } 562 563 inline static uint32_t 564 ffec_setup_txdesc(struct ffec_softc *sc, int idx, bus_addr_t paddr, 565 uint32_t len) 566 { 567 uint32_t nidx; 568 uint32_t flags; 569 570 nidx = next_txidx(sc, idx); 571 572 /* Addr/len 0 means we're clearing the descriptor after xmit done. */ 573 if (paddr == 0 || len == 0) { 574 flags = 0; 575 --sc->txcount; 576 } else { 577 flags = FEC_TXDESC_READY | FEC_TXDESC_L | FEC_TXDESC_TC; 578 ++sc->txcount; 579 } 580 if (nidx == 0) 581 flags |= FEC_TXDESC_WRAP; 582 583 /* 584 * The hardware requires 32-bit physical addresses. We set up the dma 585 * tag to indicate that, so the cast to uint32_t should never lose 586 * significant bits. 587 */ 588 sc->txdesc_ring[idx].buf_paddr = (uint32_t)paddr; 589 sc->txdesc_ring[idx].flags_len = flags | len; /* Must be set last! */ 590 591 return (nidx); 592 } 593 594 static int 595 ffec_setup_txbuf(struct ffec_softc *sc, int idx, struct mbuf **mp) 596 { 597 struct mbuf * m; 598 int error, nsegs; 599 struct bus_dma_segment seg; 600 601 if ((m = m_defrag(*mp, M_NOWAIT)) == NULL) 602 return (ENOMEM); 603 *mp = m; 604 605 error = bus_dmamap_load_mbuf_sg(sc->txbuf_tag, sc->txbuf_map[idx].map, 606 m, &seg, &nsegs, 0); 607 if (error != 0) { 608 return (ENOMEM); 609 } 610 bus_dmamap_sync(sc->txbuf_tag, sc->txbuf_map[idx].map, 611 BUS_DMASYNC_PREWRITE); 612 613 sc->txbuf_map[idx].mbuf = m; 614 ffec_setup_txdesc(sc, idx, seg.ds_addr, seg.ds_len); 615 616 return (0); 617 618 } 619 620 static void 621 ffec_txstart_locked(struct ffec_softc *sc) 622 { 623 struct ifnet *ifp; 624 struct mbuf *m; 625 int enqueued; 626 627 FFEC_ASSERT_LOCKED(sc); 628 629 if (!sc->link_is_up) 630 return; 631 632 ifp = sc->ifp; 633 634 if (ifp->if_drv_flags & IFF_DRV_OACTIVE) 635 return; 636 637 enqueued = 0; 638 639 for (;;) { 640 if (sc->txcount == (TX_DESC_COUNT-1)) { 641 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 642 break; 643 } 644 IFQ_DRV_DEQUEUE(&ifp->if_snd, m); 645 if (m == NULL) 646 break; 647 if (ffec_setup_txbuf(sc, sc->tx_idx_head, &m) != 0) { 648 IFQ_DRV_PREPEND(&ifp->if_snd, m); 649 break; 650 } 651 BPF_MTAP(ifp, m); 652 sc->tx_idx_head = next_txidx(sc, sc->tx_idx_head); 653 ++enqueued; 654 } 655 656 if (enqueued != 0) { 657 bus_dmamap_sync(sc->txdesc_tag, sc->txdesc_map, BUS_DMASYNC_PREWRITE); 658 WR4(sc, FEC_TDAR_REG, FEC_TDAR_TDAR); 659 bus_dmamap_sync(sc->txdesc_tag, sc->txdesc_map, BUS_DMASYNC_POSTWRITE); 660 sc->tx_watchdog_count = WATCHDOG_TIMEOUT_SECS; 661 } 662 } 663 664 static void 665 ffec_txstart(struct ifnet *ifp) 666 { 667 struct ffec_softc *sc = ifp->if_softc; 668 669 FFEC_LOCK(sc); 670 ffec_txstart_locked(sc); 671 FFEC_UNLOCK(sc); 672 } 673 674 static void 675 ffec_txfinish_locked(struct ffec_softc *sc) 676 { 677 struct ifnet *ifp; 678 struct ffec_hwdesc *desc; 679 struct ffec_bufmap *bmap; 680 boolean_t retired_buffer; 681 682 FFEC_ASSERT_LOCKED(sc); 683 684 /* XXX Can't set PRE|POST right now, but we need both. */ 685 bus_dmamap_sync(sc->txdesc_tag, sc->txdesc_map, BUS_DMASYNC_PREREAD); 686 bus_dmamap_sync(sc->txdesc_tag, sc->txdesc_map, BUS_DMASYNC_POSTREAD); 687 ifp = sc->ifp; 688 retired_buffer = false; 689 while (sc->tx_idx_tail != sc->tx_idx_head) { 690 desc = &sc->txdesc_ring[sc->tx_idx_tail]; 691 if (desc->flags_len & FEC_TXDESC_READY) 692 break; 693 retired_buffer = true; 694 bmap = &sc->txbuf_map[sc->tx_idx_tail]; 695 bus_dmamap_sync(sc->txbuf_tag, bmap->map, 696 BUS_DMASYNC_POSTWRITE); 697 bus_dmamap_unload(sc->txbuf_tag, bmap->map); 698 m_freem(bmap->mbuf); 699 bmap->mbuf = NULL; 700 ffec_setup_txdesc(sc, sc->tx_idx_tail, 0, 0); 701 sc->tx_idx_tail = next_txidx(sc, sc->tx_idx_tail); 702 } 703 704 /* 705 * If we retired any buffers, there will be open tx slots available in 706 * the descriptor ring, go try to start some new output. 707 */ 708 if (retired_buffer) { 709 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 710 ffec_txstart_locked(sc); 711 } 712 713 /* If there are no buffers outstanding, muzzle the watchdog. */ 714 if (sc->tx_idx_tail == sc->tx_idx_head) { 715 sc->tx_watchdog_count = 0; 716 } 717 } 718 719 inline static uint32_t 720 ffec_setup_rxdesc(struct ffec_softc *sc, int idx, bus_addr_t paddr) 721 { 722 uint32_t nidx; 723 724 /* 725 * The hardware requires 32-bit physical addresses. We set up the dma 726 * tag to indicate that, so the cast to uint32_t should never lose 727 * significant bits. 728 */ 729 nidx = next_rxidx(sc, idx); 730 sc->rxdesc_ring[idx].buf_paddr = (uint32_t)paddr; 731 sc->rxdesc_ring[idx].flags_len = FEC_RXDESC_EMPTY | 732 ((nidx == 0) ? FEC_RXDESC_WRAP : 0); 733 734 return (nidx); 735 } 736 737 static int 738 ffec_setup_rxbuf(struct ffec_softc *sc, int idx, struct mbuf * m) 739 { 740 int error, nsegs; 741 struct bus_dma_segment seg; 742 743 /* 744 * We need to leave at least ETHER_ALIGN bytes free at the beginning of 745 * the buffer to allow the data to be re-aligned after receiving it (by 746 * copying it backwards ETHER_ALIGN bytes in the same buffer). We also 747 * have to ensure that the beginning of the buffer is aligned to the 748 * hardware's requirements. 749 */ 750 m_adj(m, roundup(ETHER_ALIGN, FEC_RXBUF_ALIGN)); 751 752 error = bus_dmamap_load_mbuf_sg(sc->rxbuf_tag, sc->rxbuf_map[idx].map, 753 m, &seg, &nsegs, 0); 754 if (error != 0) { 755 return (error); 756 } 757 758 bus_dmamap_sync(sc->rxbuf_tag, sc->rxbuf_map[idx].map, 759 BUS_DMASYNC_PREREAD); 760 761 sc->rxbuf_map[idx].mbuf = m; 762 ffec_setup_rxdesc(sc, idx, seg.ds_addr); 763 764 return (0); 765 } 766 767 static struct mbuf * 768 ffec_alloc_mbufcl(struct ffec_softc *sc) 769 { 770 struct mbuf *m; 771 772 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 773 m->m_pkthdr.len = m->m_len = m->m_ext.ext_size; 774 775 return (m); 776 } 777 778 static void 779 ffec_rxfinish_onebuf(struct ffec_softc *sc, int len) 780 { 781 struct mbuf *m, *newmbuf; 782 struct ffec_bufmap *bmap; 783 uint8_t *dst, *src; 784 int error; 785 786 /* 787 * First try to get a new mbuf to plug into this slot in the rx ring. 788 * If that fails, drop the current packet and recycle the current 789 * mbuf, which is still mapped and loaded. 790 */ 791 if ((newmbuf = ffec_alloc_mbufcl(sc)) == NULL) { 792 if_inc_counter(sc->ifp, IFCOUNTER_IQDROPS, 1); 793 ffec_setup_rxdesc(sc, sc->rx_idx, 794 sc->rxdesc_ring[sc->rx_idx].buf_paddr); 795 return; 796 } 797 798 /* 799 * Unfortunately, the protocol headers need to be aligned on a 32-bit 800 * boundary for the upper layers. The hardware requires receive 801 * buffers to be 16-byte aligned. The ethernet header is 14 bytes, 802 * leaving the protocol header unaligned. We used m_adj() after 803 * allocating the buffer to leave empty space at the start of the 804 * buffer, now we'll use the alignment agnostic bcopy() routine to 805 * shuffle all the data backwards 2 bytes and adjust m_data. 806 * 807 * XXX imx6 hardware is able to do this 2-byte alignment by setting the 808 * SHIFT16 bit in the RACC register. Older hardware doesn't have that 809 * feature, but for them could we speed this up by copying just the 810 * protocol headers into their own small mbuf then chaining the cluster 811 * to it? That way we'd only need to copy like 64 bytes or whatever 812 * the biggest header is, instead of the whole 1530ish-byte frame. 813 */ 814 815 FFEC_UNLOCK(sc); 816 817 bmap = &sc->rxbuf_map[sc->rx_idx]; 818 len -= ETHER_CRC_LEN; 819 bus_dmamap_sync(sc->rxbuf_tag, bmap->map, BUS_DMASYNC_POSTREAD); 820 bus_dmamap_unload(sc->rxbuf_tag, bmap->map); 821 m = bmap->mbuf; 822 bmap->mbuf = NULL; 823 m->m_len = len; 824 m->m_pkthdr.len = len; 825 m->m_pkthdr.rcvif = sc->ifp; 826 827 src = mtod(m, uint8_t*); 828 dst = src - ETHER_ALIGN; 829 bcopy(src, dst, len); 830 m->m_data = dst; 831 sc->ifp->if_input(sc->ifp, m); 832 833 FFEC_LOCK(sc); 834 835 if ((error = ffec_setup_rxbuf(sc, sc->rx_idx, newmbuf)) != 0) { 836 device_printf(sc->dev, "ffec_setup_rxbuf error %d\n", error); 837 /* XXX Now what? We've got a hole in the rx ring. */ 838 } 839 840 } 841 842 static void 843 ffec_rxfinish_locked(struct ffec_softc *sc) 844 { 845 struct ffec_hwdesc *desc; 846 int len; 847 boolean_t produced_empty_buffer; 848 849 FFEC_ASSERT_LOCKED(sc); 850 851 /* XXX Can't set PRE|POST right now, but we need both. */ 852 bus_dmamap_sync(sc->rxdesc_tag, sc->rxdesc_map, BUS_DMASYNC_PREREAD); 853 bus_dmamap_sync(sc->rxdesc_tag, sc->rxdesc_map, BUS_DMASYNC_POSTREAD); 854 produced_empty_buffer = false; 855 for (;;) { 856 desc = &sc->rxdesc_ring[sc->rx_idx]; 857 if (desc->flags_len & FEC_RXDESC_EMPTY) 858 break; 859 produced_empty_buffer = true; 860 len = (desc->flags_len & FEC_RXDESC_LEN_MASK); 861 if (len < 64) { 862 /* 863 * Just recycle the descriptor and continue. . 864 */ 865 ffec_setup_rxdesc(sc, sc->rx_idx, 866 sc->rxdesc_ring[sc->rx_idx].buf_paddr); 867 } else if ((desc->flags_len & FEC_RXDESC_L) == 0) { 868 /* 869 * The entire frame is not in this buffer. Impossible. 870 * Recycle the descriptor and continue. 871 * 872 * XXX what's the right way to handle this? Probably we 873 * should stop/init the hardware because this should 874 * just really never happen when we have buffers bigger 875 * than the maximum frame size. 876 */ 877 device_printf(sc->dev, 878 "fec_rxfinish: received frame without LAST bit set"); 879 ffec_setup_rxdesc(sc, sc->rx_idx, 880 sc->rxdesc_ring[sc->rx_idx].buf_paddr); 881 } else if (desc->flags_len & FEC_RXDESC_ERROR_BITS) { 882 /* 883 * Something went wrong with receiving the frame, we 884 * don't care what (the hardware has counted the error 885 * in the stats registers already), we just reuse the 886 * same mbuf, which is still dma-mapped, by resetting 887 * the rx descriptor. 888 */ 889 ffec_setup_rxdesc(sc, sc->rx_idx, 890 sc->rxdesc_ring[sc->rx_idx].buf_paddr); 891 } else { 892 /* 893 * Normal case: a good frame all in one buffer. 894 */ 895 ffec_rxfinish_onebuf(sc, len); 896 } 897 sc->rx_idx = next_rxidx(sc, sc->rx_idx); 898 } 899 900 if (produced_empty_buffer) { 901 bus_dmamap_sync(sc->rxdesc_tag, sc->rxdesc_map, BUS_DMASYNC_PREWRITE); 902 WR4(sc, FEC_RDAR_REG, FEC_RDAR_RDAR); 903 bus_dmamap_sync(sc->rxdesc_tag, sc->rxdesc_map, BUS_DMASYNC_POSTWRITE); 904 } 905 } 906 907 static void 908 ffec_get_hwaddr(struct ffec_softc *sc, uint8_t *hwaddr) 909 { 910 uint32_t palr, paur, rnd; 911 912 /* 913 * Try to recover a MAC address from the running hardware. If there's 914 * something non-zero there, assume the bootloader did the right thing 915 * and just use it. 916 * 917 * Otherwise, set the address to a convenient locally assigned address, 918 * 'bsd' + random 24 low-order bits. 'b' is 0x62, which has the locally 919 * assigned bit set, and the broadcast/multicast bit clear. 920 */ 921 palr = RD4(sc, FEC_PALR_REG); 922 paur = RD4(sc, FEC_PAUR_REG) & FEC_PAUR_PADDR2_MASK; 923 if ((palr | paur) != 0) { 924 hwaddr[0] = palr >> 24; 925 hwaddr[1] = palr >> 16; 926 hwaddr[2] = palr >> 8; 927 hwaddr[3] = palr >> 0; 928 hwaddr[4] = paur >> 24; 929 hwaddr[5] = paur >> 16; 930 } else { 931 rnd = arc4random() & 0x00ffffff; 932 hwaddr[0] = 'b'; 933 hwaddr[1] = 's'; 934 hwaddr[2] = 'd'; 935 hwaddr[3] = rnd >> 16; 936 hwaddr[4] = rnd >> 8; 937 hwaddr[5] = rnd >> 0; 938 } 939 940 if (bootverbose) { 941 device_printf(sc->dev, 942 "MAC address %02x:%02x:%02x:%02x:%02x:%02x:\n", 943 hwaddr[0], hwaddr[1], hwaddr[2], 944 hwaddr[3], hwaddr[4], hwaddr[5]); 945 } 946 } 947 948 static void 949 ffec_setup_rxfilter(struct ffec_softc *sc) 950 { 951 struct ifnet *ifp; 952 struct ifmultiaddr *ifma; 953 uint8_t *eaddr; 954 uint32_t crc; 955 uint64_t ghash, ihash; 956 957 FFEC_ASSERT_LOCKED(sc); 958 959 ifp = sc->ifp; 960 961 /* 962 * Set the multicast (group) filter hash. 963 */ 964 if ((ifp->if_flags & IFF_ALLMULTI)) 965 ghash = 0xffffffffffffffffLLU; 966 else { 967 ghash = 0; 968 if_maddr_rlock(ifp); 969 TAILQ_FOREACH(ifma, &sc->ifp->if_multiaddrs, ifma_link) { 970 if (ifma->ifma_addr->sa_family != AF_LINK) 971 continue; 972 /* 6 bits from MSB in LE CRC32 are used for hash. */ 973 crc = ether_crc32_le(LLADDR((struct sockaddr_dl *) 974 ifma->ifma_addr), ETHER_ADDR_LEN); 975 ghash |= 1LLU << (((uint8_t *)&crc)[3] >> 2); 976 } 977 if_maddr_runlock(ifp); 978 } 979 WR4(sc, FEC_GAUR_REG, (uint32_t)(ghash >> 32)); 980 WR4(sc, FEC_GALR_REG, (uint32_t)ghash); 981 982 /* 983 * Set the individual address filter hash. 984 * 985 * XXX Is 0 the right value when promiscuous is off? This hw feature 986 * seems to support the concept of MAC address aliases, does such a 987 * thing even exist? 988 */ 989 if ((ifp->if_flags & IFF_PROMISC)) 990 ihash = 0xffffffffffffffffLLU; 991 else { 992 ihash = 0; 993 } 994 WR4(sc, FEC_IAUR_REG, (uint32_t)(ihash >> 32)); 995 WR4(sc, FEC_IALR_REG, (uint32_t)ihash); 996 997 /* 998 * Set the primary address. 999 */ 1000 eaddr = IF_LLADDR(ifp); 1001 WR4(sc, FEC_PALR_REG, (eaddr[0] << 24) | (eaddr[1] << 16) | 1002 (eaddr[2] << 8) | eaddr[3]); 1003 WR4(sc, FEC_PAUR_REG, (eaddr[4] << 24) | (eaddr[5] << 16)); 1004 } 1005 1006 static void 1007 ffec_stop_locked(struct ffec_softc *sc) 1008 { 1009 struct ifnet *ifp; 1010 struct ffec_hwdesc *desc; 1011 struct ffec_bufmap *bmap; 1012 int idx; 1013 1014 FFEC_ASSERT_LOCKED(sc); 1015 1016 ifp = sc->ifp; 1017 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 1018 sc->tx_watchdog_count = 0; 1019 sc->stats_harvest_count = 0; 1020 1021 /* 1022 * Stop the hardware, mask all interrupts, and clear all current 1023 * interrupt status bits. 1024 */ 1025 WR4(sc, FEC_ECR_REG, RD4(sc, FEC_ECR_REG) & ~FEC_ECR_ETHEREN); 1026 WR4(sc, FEC_IEM_REG, 0x00000000); 1027 WR4(sc, FEC_IER_REG, 0xffffffff); 1028 1029 /* 1030 * Stop the media-check callout. Do not use callout_drain() because 1031 * we're holding a mutex the callout acquires, and if it's currently 1032 * waiting to acquire it, we'd deadlock. If it is waiting now, the 1033 * ffec_tick() routine will return without doing anything when it sees 1034 * that IFF_DRV_RUNNING is not set, so avoiding callout_drain() is safe. 1035 */ 1036 callout_stop(&sc->ffec_callout); 1037 1038 /* 1039 * Discard all untransmitted buffers. Each buffer is simply freed; 1040 * it's as if the bits were transmitted and then lost on the wire. 1041 * 1042 * XXX Is this right? Or should we use IFQ_DRV_PREPEND() to put them 1043 * back on the queue for when we get restarted later? 1044 */ 1045 idx = sc->tx_idx_tail; 1046 while (idx != sc->tx_idx_head) { 1047 desc = &sc->txdesc_ring[idx]; 1048 bmap = &sc->txbuf_map[idx]; 1049 if (desc->buf_paddr != 0) { 1050 bus_dmamap_unload(sc->txbuf_tag, bmap->map); 1051 m_freem(bmap->mbuf); 1052 bmap->mbuf = NULL; 1053 ffec_setup_txdesc(sc, idx, 0, 0); 1054 } 1055 idx = next_txidx(sc, idx); 1056 } 1057 1058 /* 1059 * Discard all unprocessed receive buffers. This amounts to just 1060 * pretending that nothing ever got received into them. We reuse the 1061 * mbuf already mapped for each desc, simply turning the EMPTY flags 1062 * back on so they'll get reused when we start up again. 1063 */ 1064 for (idx = 0; idx < RX_DESC_COUNT; ++idx) { 1065 desc = &sc->rxdesc_ring[idx]; 1066 ffec_setup_rxdesc(sc, idx, desc->buf_paddr); 1067 } 1068 } 1069 1070 static void 1071 ffec_init_locked(struct ffec_softc *sc) 1072 { 1073 struct ifnet *ifp = sc->ifp; 1074 uint32_t maxbuf, maxfl, regval; 1075 1076 FFEC_ASSERT_LOCKED(sc); 1077 1078 /* 1079 * The hardware has a limit of 0x7ff as the max frame length (see 1080 * comments for MRBR below), and we use mbuf clusters as receive 1081 * buffers, and we currently are designed to receive an entire frame 1082 * into a single buffer. 1083 * 1084 * We start with a MCLBYTES-sized cluster, but we have to offset into 1085 * the buffer by ETHER_ALIGN to make room for post-receive re-alignment, 1086 * and then that value has to be rounded up to the hardware's DMA 1087 * alignment requirements, so all in all our buffer is that much smaller 1088 * than MCLBYTES. 1089 * 1090 * The resulting value is used as the frame truncation length and the 1091 * max buffer receive buffer size for now. It'll become more complex 1092 * when we support jumbo frames and receiving fragments of them into 1093 * separate buffers. 1094 */ 1095 maxbuf = MCLBYTES - roundup(ETHER_ALIGN, FEC_RXBUF_ALIGN); 1096 maxfl = min(maxbuf, 0x7ff); 1097 1098 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 1099 return; 1100 1101 /* Mask all interrupts and clear all current interrupt status bits. */ 1102 WR4(sc, FEC_IEM_REG, 0x00000000); 1103 WR4(sc, FEC_IER_REG, 0xffffffff); 1104 1105 /* 1106 * Go set up palr/puar, galr/gaur, ialr/iaur. 1107 */ 1108 ffec_setup_rxfilter(sc); 1109 1110 /* 1111 * TFWR - Transmit FIFO watermark register. 1112 * 1113 * Set the transmit fifo watermark register to "store and forward" mode 1114 * and also set a threshold of 128 bytes in the fifo before transmission 1115 * of a frame begins (to avoid dma underruns). Recent FEC hardware 1116 * supports STRFWD and when that bit is set, the watermark level in the 1117 * low bits is ignored. Older hardware doesn't have STRFWD, but writing 1118 * to that bit is innocuous, and the TWFR bits get used instead. 1119 */ 1120 WR4(sc, FEC_TFWR_REG, FEC_TFWR_STRFWD | FEC_TFWR_TWFR_128BYTE); 1121 1122 /* RCR - Receive control register. 1123 * 1124 * Set max frame length + clean out anything left from u-boot. 1125 */ 1126 WR4(sc, FEC_RCR_REG, (maxfl << FEC_RCR_MAX_FL_SHIFT)); 1127 1128 /* 1129 * TCR - Transmit control register. 1130 * 1131 * Clean out anything left from u-boot. Any necessary values are set in 1132 * ffec_miibus_statchg() based on the media type. 1133 */ 1134 WR4(sc, FEC_TCR_REG, 0); 1135 1136 /* 1137 * OPD - Opcode/pause duration. 1138 * 1139 * XXX These magic numbers come from u-boot. 1140 */ 1141 WR4(sc, FEC_OPD_REG, 0x00010020); 1142 1143 /* 1144 * FRSR - Fifo receive start register. 1145 * 1146 * This register does not exist on imx6, it is present on earlier 1147 * hardware. The u-boot code sets this to a non-default value that's 32 1148 * bytes larger than the default, with no clue as to why. The default 1149 * value should work fine, so there's no code to init it here. 1150 */ 1151 1152 /* 1153 * MRBR - Max RX buffer size. 1154 * 1155 * Note: For hardware prior to imx6 this value cannot exceed 0x07ff, 1156 * but the datasheet says no such thing for imx6. On the imx6, setting 1157 * this to 2K without setting EN1588 resulted in a crazy runaway 1158 * receive loop in the hardware, where every rx descriptor in the ring 1159 * had its EMPTY flag cleared, no completion or error flags set, and a 1160 * length of zero. I think maybe you can only exceed it when EN1588 is 1161 * set, like maybe that's what enables jumbo frames, because in general 1162 * the EN1588 flag seems to be the "enable new stuff" vs. "be legacy- 1163 * compatible" flag. 1164 */ 1165 WR4(sc, FEC_MRBR_REG, maxfl << FEC_MRBR_R_BUF_SIZE_SHIFT); 1166 1167 /* 1168 * FTRL - Frame truncation length. 1169 * 1170 * Must be greater than or equal to the value set in FEC_RCR_MAXFL. 1171 */ 1172 WR4(sc, FEC_FTRL_REG, maxfl); 1173 1174 /* 1175 * RDSR / TDSR descriptor ring pointers. 1176 * 1177 * When we turn on ECR_ETHEREN at the end, the hardware zeroes its 1178 * internal current descriptor index values for both rings, so we zero 1179 * our index values as well. 1180 */ 1181 sc->rx_idx = 0; 1182 sc->tx_idx_head = sc->tx_idx_tail = 0; 1183 sc->txcount = 0; 1184 WR4(sc, FEC_RDSR_REG, sc->rxdesc_ring_paddr); 1185 WR4(sc, FEC_TDSR_REG, sc->txdesc_ring_paddr); 1186 1187 /* 1188 * EIM - interrupt mask register. 1189 * 1190 * We always enable the same set of interrupts while running; unlike 1191 * some drivers there's no need to change the mask on the fly depending 1192 * on what operations are in progress. 1193 */ 1194 WR4(sc, FEC_IEM_REG, FEC_IER_TXF | FEC_IER_RXF | FEC_IER_EBERR); 1195 1196 /* 1197 * MIBC - MIB control (hardware stats). 1198 */ 1199 regval = RD4(sc, FEC_MIBC_REG); 1200 WR4(sc, FEC_MIBC_REG, regval | FEC_MIBC_DIS); 1201 ffec_clear_stats(sc); 1202 WR4(sc, FEC_MIBC_REG, regval & ~FEC_MIBC_DIS); 1203 1204 /* 1205 * ECR - Ethernet control register. 1206 * 1207 * This must happen after all the other config registers are set. If 1208 * we're running on little-endian hardware, also set the flag for byte- 1209 * swapping descriptor ring entries. This flag doesn't exist on older 1210 * hardware, but it can be safely set -- the bit position it occupies 1211 * was unused. 1212 */ 1213 regval = RD4(sc, FEC_ECR_REG); 1214 #if _BYTE_ORDER == _LITTLE_ENDIAN 1215 regval |= FEC_ECR_DBSWP; 1216 #endif 1217 regval |= FEC_ECR_ETHEREN; 1218 WR4(sc, FEC_ECR_REG, regval); 1219 1220 ifp->if_drv_flags |= IFF_DRV_RUNNING; 1221 1222 /* 1223 * Call mii_mediachg() which will call back into ffec_miibus_statchg() to 1224 * set up the remaining config registers based on the current media. 1225 */ 1226 mii_mediachg(sc->mii_softc); 1227 callout_reset(&sc->ffec_callout, hz, ffec_tick, sc); 1228 1229 /* 1230 * Tell the hardware that receive buffers are available. They were made 1231 * available in ffec_attach() or ffec_stop(). 1232 */ 1233 WR4(sc, FEC_RDAR_REG, FEC_RDAR_RDAR); 1234 } 1235 1236 static void 1237 ffec_init(void *if_softc) 1238 { 1239 struct ffec_softc *sc = if_softc; 1240 1241 FFEC_LOCK(sc); 1242 ffec_init_locked(sc); 1243 FFEC_UNLOCK(sc); 1244 } 1245 1246 static void 1247 ffec_intr(void *arg) 1248 { 1249 struct ffec_softc *sc; 1250 uint32_t ier; 1251 1252 sc = arg; 1253 1254 FFEC_LOCK(sc); 1255 1256 ier = RD4(sc, FEC_IER_REG); 1257 1258 if (ier & FEC_IER_TXF) { 1259 WR4(sc, FEC_IER_REG, FEC_IER_TXF); 1260 ffec_txfinish_locked(sc); 1261 } 1262 1263 if (ier & FEC_IER_RXF) { 1264 WR4(sc, FEC_IER_REG, FEC_IER_RXF); 1265 ffec_rxfinish_locked(sc); 1266 } 1267 1268 /* 1269 * We actually don't care about most errors, because the hardware copes 1270 * with them just fine, discarding the incoming bad frame, or forcing a 1271 * bad CRC onto an outgoing bad frame, and counting the errors in the 1272 * stats registers. The one that really matters is EBERR (DMA bus 1273 * error) because the hardware automatically clears ECR[ETHEREN] and we 1274 * have to restart it here. It should never happen. 1275 */ 1276 if (ier & FEC_IER_EBERR) { 1277 WR4(sc, FEC_IER_REG, FEC_IER_EBERR); 1278 device_printf(sc->dev, 1279 "Ethernet DMA error, restarting controller.\n"); 1280 ffec_stop_locked(sc); 1281 ffec_init_locked(sc); 1282 } 1283 1284 FFEC_UNLOCK(sc); 1285 1286 } 1287 1288 static int 1289 ffec_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 1290 { 1291 struct ffec_softc *sc; 1292 struct mii_data *mii; 1293 struct ifreq *ifr; 1294 int mask, error; 1295 1296 sc = ifp->if_softc; 1297 ifr = (struct ifreq *)data; 1298 1299 error = 0; 1300 switch (cmd) { 1301 case SIOCSIFFLAGS: 1302 FFEC_LOCK(sc); 1303 if (ifp->if_flags & IFF_UP) { 1304 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 1305 if ((ifp->if_flags ^ sc->if_flags) & 1306 (IFF_PROMISC | IFF_ALLMULTI)) 1307 ffec_setup_rxfilter(sc); 1308 } else { 1309 if (!sc->is_detaching) 1310 ffec_init_locked(sc); 1311 } 1312 } else { 1313 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 1314 ffec_stop_locked(sc); 1315 } 1316 sc->if_flags = ifp->if_flags; 1317 FFEC_UNLOCK(sc); 1318 break; 1319 1320 case SIOCADDMULTI: 1321 case SIOCDELMULTI: 1322 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 1323 FFEC_LOCK(sc); 1324 ffec_setup_rxfilter(sc); 1325 FFEC_UNLOCK(sc); 1326 } 1327 break; 1328 1329 case SIOCSIFMEDIA: 1330 case SIOCGIFMEDIA: 1331 mii = sc->mii_softc; 1332 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd); 1333 break; 1334 1335 case SIOCSIFCAP: 1336 mask = ifp->if_capenable ^ ifr->ifr_reqcap; 1337 if (mask & IFCAP_VLAN_MTU) { 1338 /* No work to do except acknowledge the change took. */ 1339 ifp->if_capenable ^= IFCAP_VLAN_MTU; 1340 } 1341 break; 1342 1343 default: 1344 error = ether_ioctl(ifp, cmd, data); 1345 break; 1346 } 1347 1348 return (error); 1349 } 1350 1351 static int 1352 ffec_detach(device_t dev) 1353 { 1354 struct ffec_softc *sc; 1355 bus_dmamap_t map; 1356 int idx; 1357 1358 /* 1359 * NB: This function can be called internally to unwind a failure to 1360 * attach. Make sure a resource got allocated/created before destroying. 1361 */ 1362 1363 sc = device_get_softc(dev); 1364 1365 if (sc->is_attached) { 1366 FFEC_LOCK(sc); 1367 sc->is_detaching = true; 1368 ffec_stop_locked(sc); 1369 FFEC_UNLOCK(sc); 1370 callout_drain(&sc->ffec_callout); 1371 ether_ifdetach(sc->ifp); 1372 } 1373 1374 /* XXX no miibus detach? */ 1375 1376 /* Clean up RX DMA resources and free mbufs. */ 1377 for (idx = 0; idx < RX_DESC_COUNT; ++idx) { 1378 if ((map = sc->rxbuf_map[idx].map) != NULL) { 1379 bus_dmamap_unload(sc->rxbuf_tag, map); 1380 bus_dmamap_destroy(sc->rxbuf_tag, map); 1381 m_freem(sc->rxbuf_map[idx].mbuf); 1382 } 1383 } 1384 if (sc->rxbuf_tag != NULL) 1385 bus_dma_tag_destroy(sc->rxbuf_tag); 1386 if (sc->rxdesc_map != NULL) { 1387 bus_dmamap_unload(sc->rxdesc_tag, sc->rxdesc_map); 1388 bus_dmamap_destroy(sc->rxdesc_tag, sc->rxdesc_map); 1389 } 1390 if (sc->rxdesc_tag != NULL) 1391 bus_dma_tag_destroy(sc->rxdesc_tag); 1392 1393 /* Clean up TX DMA resources. */ 1394 for (idx = 0; idx < TX_DESC_COUNT; ++idx) { 1395 if ((map = sc->txbuf_map[idx].map) != NULL) { 1396 /* TX maps are already unloaded. */ 1397 bus_dmamap_destroy(sc->txbuf_tag, map); 1398 } 1399 } 1400 if (sc->txbuf_tag != NULL) 1401 bus_dma_tag_destroy(sc->txbuf_tag); 1402 if (sc->txdesc_map != NULL) { 1403 bus_dmamap_unload(sc->txdesc_tag, sc->txdesc_map); 1404 bus_dmamap_destroy(sc->txdesc_tag, sc->txdesc_map); 1405 } 1406 if (sc->txdesc_tag != NULL) 1407 bus_dma_tag_destroy(sc->txdesc_tag); 1408 1409 /* Release bus resources. */ 1410 if (sc->intr_cookie) 1411 bus_teardown_intr(dev, sc->irq_res, sc->intr_cookie); 1412 1413 if (sc->irq_res != NULL) 1414 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->irq_res); 1415 1416 if (sc->mem_res != NULL) 1417 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->mem_res); 1418 1419 FFEC_LOCK_DESTROY(sc); 1420 return (0); 1421 } 1422 1423 static int 1424 ffec_attach(device_t dev) 1425 { 1426 struct ffec_softc *sc; 1427 struct ifnet *ifp = NULL; 1428 struct mbuf *m; 1429 void *dummy; 1430 phandle_t ofw_node; 1431 int error, phynum, rid; 1432 uint8_t eaddr[ETHER_ADDR_LEN]; 1433 char phy_conn_name[32]; 1434 uint32_t idx, mscr; 1435 1436 sc = device_get_softc(dev); 1437 sc->dev = dev; 1438 1439 FFEC_LOCK_INIT(sc); 1440 1441 /* 1442 * There are differences in the implementation and features of the FEC 1443 * hardware on different SoCs, so figure out what type we are. 1444 */ 1445 sc->fectype = ofw_bus_search_compatible(dev, compat_data)->ocd_data; 1446 1447 /* 1448 * We have to be told what kind of electrical connection exists between 1449 * the MAC and PHY or we can't operate correctly. 1450 */ 1451 if ((ofw_node = ofw_bus_get_node(dev)) == -1) { 1452 device_printf(dev, "Impossible: Can't find ofw bus node\n"); 1453 error = ENXIO; 1454 goto out; 1455 } 1456 if (OF_searchprop(ofw_node, "phy-mode", 1457 phy_conn_name, sizeof(phy_conn_name)) != -1) { 1458 if (strcasecmp(phy_conn_name, "mii") == 0) 1459 sc->phy_conn_type = PHY_CONN_MII; 1460 else if (strcasecmp(phy_conn_name, "rmii") == 0) 1461 sc->phy_conn_type = PHY_CONN_RMII; 1462 else if (strcasecmp(phy_conn_name, "rgmii") == 0) 1463 sc->phy_conn_type = PHY_CONN_RGMII; 1464 } 1465 if (sc->phy_conn_type == PHY_CONN_UNKNOWN) { 1466 device_printf(sc->dev, "No valid 'phy-mode' " 1467 "property found in FDT data for device.\n"); 1468 error = ENOATTR; 1469 goto out; 1470 } 1471 1472 callout_init_mtx(&sc->ffec_callout, &sc->mtx, 0); 1473 1474 /* Allocate bus resources for accessing the hardware. */ 1475 rid = 0; 1476 sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 1477 RF_ACTIVE); 1478 if (sc->mem_res == NULL) { 1479 device_printf(dev, "could not allocate memory resources.\n"); 1480 error = ENOMEM; 1481 goto out; 1482 } 1483 rid = 0; 1484 sc->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 1485 RF_ACTIVE); 1486 if (sc->irq_res == NULL) { 1487 device_printf(dev, "could not allocate interrupt resources.\n"); 1488 error = ENOMEM; 1489 goto out; 1490 } 1491 1492 /* 1493 * Set up TX descriptor ring, descriptors, and dma maps. 1494 */ 1495 error = bus_dma_tag_create( 1496 bus_get_dma_tag(dev), /* Parent tag. */ 1497 FEC_DESC_RING_ALIGN, 0, /* alignment, boundary */ 1498 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 1499 BUS_SPACE_MAXADDR, /* highaddr */ 1500 NULL, NULL, /* filter, filterarg */ 1501 TX_DESC_SIZE, 1, /* maxsize, nsegments */ 1502 TX_DESC_SIZE, /* maxsegsize */ 1503 0, /* flags */ 1504 NULL, NULL, /* lockfunc, lockarg */ 1505 &sc->txdesc_tag); 1506 if (error != 0) { 1507 device_printf(sc->dev, 1508 "could not create TX ring DMA tag.\n"); 1509 goto out; 1510 } 1511 1512 error = bus_dmamem_alloc(sc->txdesc_tag, (void**)&sc->txdesc_ring, 1513 BUS_DMA_COHERENT | BUS_DMA_WAITOK | BUS_DMA_ZERO, &sc->txdesc_map); 1514 if (error != 0) { 1515 device_printf(sc->dev, 1516 "could not allocate TX descriptor ring.\n"); 1517 goto out; 1518 } 1519 1520 error = bus_dmamap_load(sc->txdesc_tag, sc->txdesc_map, sc->txdesc_ring, 1521 TX_DESC_SIZE, ffec_get1paddr, &sc->txdesc_ring_paddr, 0); 1522 if (error != 0) { 1523 device_printf(sc->dev, 1524 "could not load TX descriptor ring map.\n"); 1525 goto out; 1526 } 1527 1528 error = bus_dma_tag_create( 1529 bus_get_dma_tag(dev), /* Parent tag. */ 1530 FEC_TXBUF_ALIGN, 0, /* alignment, boundary */ 1531 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 1532 BUS_SPACE_MAXADDR, /* highaddr */ 1533 NULL, NULL, /* filter, filterarg */ 1534 MCLBYTES, 1, /* maxsize, nsegments */ 1535 MCLBYTES, /* maxsegsize */ 1536 0, /* flags */ 1537 NULL, NULL, /* lockfunc, lockarg */ 1538 &sc->txbuf_tag); 1539 if (error != 0) { 1540 device_printf(sc->dev, 1541 "could not create TX ring DMA tag.\n"); 1542 goto out; 1543 } 1544 1545 for (idx = 0; idx < TX_DESC_COUNT; ++idx) { 1546 error = bus_dmamap_create(sc->txbuf_tag, 0, 1547 &sc->txbuf_map[idx].map); 1548 if (error != 0) { 1549 device_printf(sc->dev, 1550 "could not create TX buffer DMA map.\n"); 1551 goto out; 1552 } 1553 ffec_setup_txdesc(sc, idx, 0, 0); 1554 } 1555 1556 /* 1557 * Set up RX descriptor ring, descriptors, dma maps, and mbufs. 1558 */ 1559 error = bus_dma_tag_create( 1560 bus_get_dma_tag(dev), /* Parent tag. */ 1561 FEC_DESC_RING_ALIGN, 0, /* alignment, boundary */ 1562 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 1563 BUS_SPACE_MAXADDR, /* highaddr */ 1564 NULL, NULL, /* filter, filterarg */ 1565 RX_DESC_SIZE, 1, /* maxsize, nsegments */ 1566 RX_DESC_SIZE, /* maxsegsize */ 1567 0, /* flags */ 1568 NULL, NULL, /* lockfunc, lockarg */ 1569 &sc->rxdesc_tag); 1570 if (error != 0) { 1571 device_printf(sc->dev, 1572 "could not create RX ring DMA tag.\n"); 1573 goto out; 1574 } 1575 1576 error = bus_dmamem_alloc(sc->rxdesc_tag, (void **)&sc->rxdesc_ring, 1577 BUS_DMA_COHERENT | BUS_DMA_WAITOK | BUS_DMA_ZERO, &sc->rxdesc_map); 1578 if (error != 0) { 1579 device_printf(sc->dev, 1580 "could not allocate RX descriptor ring.\n"); 1581 goto out; 1582 } 1583 1584 error = bus_dmamap_load(sc->rxdesc_tag, sc->rxdesc_map, sc->rxdesc_ring, 1585 RX_DESC_SIZE, ffec_get1paddr, &sc->rxdesc_ring_paddr, 0); 1586 if (error != 0) { 1587 device_printf(sc->dev, 1588 "could not load RX descriptor ring map.\n"); 1589 goto out; 1590 } 1591 1592 error = bus_dma_tag_create( 1593 bus_get_dma_tag(dev), /* Parent tag. */ 1594 1, 0, /* alignment, boundary */ 1595 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 1596 BUS_SPACE_MAXADDR, /* highaddr */ 1597 NULL, NULL, /* filter, filterarg */ 1598 MCLBYTES, 1, /* maxsize, nsegments */ 1599 MCLBYTES, /* maxsegsize */ 1600 0, /* flags */ 1601 NULL, NULL, /* lockfunc, lockarg */ 1602 &sc->rxbuf_tag); 1603 if (error != 0) { 1604 device_printf(sc->dev, 1605 "could not create RX buf DMA tag.\n"); 1606 goto out; 1607 } 1608 1609 for (idx = 0; idx < RX_DESC_COUNT; ++idx) { 1610 error = bus_dmamap_create(sc->rxbuf_tag, 0, 1611 &sc->rxbuf_map[idx].map); 1612 if (error != 0) { 1613 device_printf(sc->dev, 1614 "could not create RX buffer DMA map.\n"); 1615 goto out; 1616 } 1617 if ((m = ffec_alloc_mbufcl(sc)) == NULL) { 1618 device_printf(dev, "Could not alloc mbuf\n"); 1619 error = ENOMEM; 1620 goto out; 1621 } 1622 if ((error = ffec_setup_rxbuf(sc, idx, m)) != 0) { 1623 device_printf(sc->dev, 1624 "could not create new RX buffer.\n"); 1625 goto out; 1626 } 1627 } 1628 1629 /* Try to get the MAC address from the hardware before resetting it. */ 1630 ffec_get_hwaddr(sc, eaddr); 1631 1632 /* Reset the hardware. Disables all interrupts. */ 1633 WR4(sc, FEC_ECR_REG, FEC_ECR_RESET); 1634 1635 /* Setup interrupt handler. */ 1636 error = bus_setup_intr(dev, sc->irq_res, INTR_TYPE_NET | INTR_MPSAFE, 1637 NULL, ffec_intr, sc, &sc->intr_cookie); 1638 if (error != 0) { 1639 device_printf(dev, "could not setup interrupt handler.\n"); 1640 goto out; 1641 } 1642 1643 /* 1644 * Set up the PHY control register. 1645 * 1646 * Speed formula for ENET is md_clock = mac_clock / ((N + 1) * 2). 1647 * Speed formula for FEC is md_clock = mac_clock / (N * 2) 1648 * 1649 * XXX - Revisit this... 1650 * 1651 * For a Wandboard imx6 (ENET) I was originally using 4, but the uboot 1652 * code uses 10. Both values seem to work, but I suspect many modern 1653 * PHY parts can do mdio at speeds far above the standard 2.5 MHz. 1654 * 1655 * Different imx manuals use confusingly different terminology (things 1656 * like "system clock" and "internal module clock") with examples that 1657 * use frequencies that have nothing to do with ethernet, giving the 1658 * vague impression that maybe the clock in question is the periphclock 1659 * or something. In fact, on an imx53 development board (FEC), 1660 * measuring the mdio clock at the pin on the PHY and playing with 1661 * various divisors showed that the root speed was 66 MHz (clk_ipg_root 1662 * aka periphclock) and 13 was the right divisor. 1663 * 1664 * All in all, it seems likely that 13 is a safe divisor for now, 1665 * because if we really do need to base it on the peripheral clock 1666 * speed, then we need a platform-independant get-clock-freq API. 1667 */ 1668 mscr = 13 << FEC_MSCR_MII_SPEED_SHIFT; 1669 if (OF_hasprop(ofw_node, "phy-disable-preamble")) { 1670 mscr |= FEC_MSCR_DIS_PRE; 1671 if (bootverbose) 1672 device_printf(dev, "PHY preamble disabled\n"); 1673 } 1674 WR4(sc, FEC_MSCR_REG, mscr); 1675 1676 /* Set up the ethernet interface. */ 1677 sc->ifp = ifp = if_alloc(IFT_ETHER); 1678 1679 ifp->if_softc = sc; 1680 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1681 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1682 ifp->if_capabilities = IFCAP_VLAN_MTU; 1683 ifp->if_capenable = ifp->if_capabilities; 1684 ifp->if_start = ffec_txstart; 1685 ifp->if_ioctl = ffec_ioctl; 1686 ifp->if_init = ffec_init; 1687 IFQ_SET_MAXLEN(&ifp->if_snd, TX_DESC_COUNT - 1); 1688 ifp->if_snd.ifq_drv_maxlen = TX_DESC_COUNT - 1; 1689 IFQ_SET_READY(&ifp->if_snd); 1690 ifp->if_hdrlen = sizeof(struct ether_vlan_header); 1691 1692 #if 0 /* XXX The hardware keeps stats we could use for these. */ 1693 ifp->if_linkmib = &sc->mibdata; 1694 ifp->if_linkmiblen = sizeof(sc->mibdata); 1695 #endif 1696 1697 /* Set up the miigasket hardware (if any). */ 1698 ffec_miigasket_setup(sc); 1699 1700 /* Attach the mii driver. */ 1701 if (fdt_get_phyaddr(ofw_node, dev, &phynum, &dummy) != 0) { 1702 phynum = MII_PHY_ANY; 1703 } 1704 error = mii_attach(dev, &sc->miibus, ifp, ffec_media_change, 1705 ffec_media_status, BMSR_DEFCAPMASK, phynum, MII_OFFSET_ANY, 1706 (sc->fectype & FECTYPE_MVF) ? MIIF_FORCEANEG : 0); 1707 if (error != 0) { 1708 device_printf(dev, "PHY attach failed\n"); 1709 goto out; 1710 } 1711 sc->mii_softc = device_get_softc(sc->miibus); 1712 1713 /* All ready to run, attach the ethernet interface. */ 1714 ether_ifattach(ifp, eaddr); 1715 sc->is_attached = true; 1716 1717 error = 0; 1718 out: 1719 1720 if (error != 0) 1721 ffec_detach(dev); 1722 1723 return (error); 1724 } 1725 1726 static int 1727 ffec_probe(device_t dev) 1728 { 1729 uintptr_t fectype; 1730 1731 if (!ofw_bus_status_okay(dev)) 1732 return (ENXIO); 1733 1734 fectype = ofw_bus_search_compatible(dev, compat_data)->ocd_data; 1735 if (fectype == FECTYPE_NONE) 1736 return (ENXIO); 1737 1738 device_set_desc(dev, (fectype & FECFLAG_GBE) ? 1739 "Freescale Gigabit Ethernet Controller" : 1740 "Freescale Fast Ethernet Controller"); 1741 1742 return (BUS_PROBE_DEFAULT); 1743 } 1744 1745 1746 static device_method_t ffec_methods[] = { 1747 /* Device interface. */ 1748 DEVMETHOD(device_probe, ffec_probe), 1749 DEVMETHOD(device_attach, ffec_attach), 1750 DEVMETHOD(device_detach, ffec_detach), 1751 1752 /* 1753 DEVMETHOD(device_shutdown, ffec_shutdown), 1754 DEVMETHOD(device_suspend, ffec_suspend), 1755 DEVMETHOD(device_resume, ffec_resume), 1756 */ 1757 1758 /* MII interface. */ 1759 DEVMETHOD(miibus_readreg, ffec_miibus_readreg), 1760 DEVMETHOD(miibus_writereg, ffec_miibus_writereg), 1761 DEVMETHOD(miibus_statchg, ffec_miibus_statchg), 1762 1763 DEVMETHOD_END 1764 }; 1765 1766 static driver_t ffec_driver = { 1767 "ffec", 1768 ffec_methods, 1769 sizeof(struct ffec_softc) 1770 }; 1771 1772 static devclass_t ffec_devclass; 1773 1774 DRIVER_MODULE(ffec, simplebus, ffec_driver, ffec_devclass, 0, 0); 1775 DRIVER_MODULE(miibus, ffec, miibus_driver, miibus_devclass, 0, 0); 1776 1777 MODULE_DEPEND(ffec, ether, 1, 1, 1); 1778 MODULE_DEPEND(ffec, miibus, 1, 1, 1); 1779