xref: /freebsd/sys/dev/ffec/if_ffec.c (revision 4c9e27bd0a5f7fda85b0c0bf750575aee300a172)
1 /*-
2  * Copyright (c) 2013 Ian Lepore <ian@freebsd.org>
3  * All rights reserved.
4  *
5  * Redistribution and use in source and binary forms, with or without
6  * modification, are permitted provided that the following conditions
7  * are met:
8  * 1. Redistributions of source code must retain the above copyright
9  *    notice, this list of conditions and the following disclaimer.
10  * 2. Redistributions in binary form must reproduce the above copyright
11  *    notice, this list of conditions and the following disclaimer in the
12  *    documentation and/or other materials provided with the distribution.
13  *
14  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24  * SUCH DAMAGE.
25  *
26  */
27 
28 #include <sys/cdefs.h>
29 __FBSDID("$FreeBSD$");
30 
31 /*
32  * Driver for Freescale Fast Ethernet Controller, found on imx-series SoCs among
33  * others.  Also works for the ENET Gigibit controller found on imx6 and imx28,
34  * but the driver doesn't currently use any of the ENET advanced features other
35  * than enabling gigabit.
36  *
37  * The interface name 'fec' is already taken by netgraph's Fast Etherchannel
38  * (netgraph/ng_fec.c), so we use 'ffec'.
39  *
40  * Requires an FDT entry with at least these properties:
41  *   fec: ethernet@02188000 {
42  *      compatible = "fsl,imxNN-fec";
43  *      reg = <0x02188000 0x4000>;
44  *      interrupts = <150 151>;
45  *      phy-mode = "rgmii";
46  *      phy-disable-preamble; // optional
47  *   };
48  * The second interrupt number is for IEEE-1588, and is not currently used; it
49  * need not be present.  phy-mode must be one of: "mii", "rmii", "rgmii".
50  * There is also an optional property, phy-disable-preamble, which if present
51  * will disable the preamble bits, cutting the size of each mdio transaction
52  * (and thus the busy-wait time) in half.
53  */
54 
55 #include <sys/param.h>
56 #include <sys/systm.h>
57 #include <sys/bus.h>
58 #include <sys/endian.h>
59 #include <sys/kernel.h>
60 #include <sys/lock.h>
61 #include <sys/malloc.h>
62 #include <sys/mbuf.h>
63 #include <sys/module.h>
64 #include <sys/mutex.h>
65 #include <sys/rman.h>
66 #include <sys/socket.h>
67 #include <sys/sockio.h>
68 #include <sys/sysctl.h>
69 
70 #include <machine/bus.h>
71 
72 #include <net/bpf.h>
73 #include <net/if.h>
74 #include <net/ethernet.h>
75 #include <net/if_dl.h>
76 #include <net/if_media.h>
77 #include <net/if_types.h>
78 #include <net/if_var.h>
79 #include <net/if_vlan_var.h>
80 
81 #include <dev/ffec/if_ffecreg.h>
82 #include <dev/ofw/ofw_bus.h>
83 #include <dev/ofw/ofw_bus_subr.h>
84 #include <dev/mii/mii.h>
85 #include <dev/mii/miivar.h>
86 #include "miibus_if.h"
87 
88 /*
89  * There are small differences in the hardware on various SoCs.  Not every SoC
90  * we support has its own FECTYPE; most work as GENERIC and only the ones that
91  * need different handling get their own entry.  In addition to the types in
92  * this list, there are some flags below that can be ORed into the upper bits.
93  */
94 enum {
95 	FECTYPE_NONE,
96 	FECTYPE_GENERIC,
97 	FECTYPE_IMX53,
98 	FECTYPE_IMX6,
99 };
100 
101 /*
102  * Flags that describe general differences between the FEC hardware in various
103  * SoCs.  These are ORed into the FECTYPE enum values.
104  */
105 #define	FECTYPE_MASK		0x0000ffff
106 #define	FECFLAG_GBE		(0x0001 << 16)
107 
108 /*
109  * Table of supported FDT compat strings and their associated FECTYPE values.
110  */
111 static struct ofw_compat_data compat_data[] = {
112 	{"fsl,imx51-fec",	FECTYPE_GENERIC},
113 	{"fsl,imx53-fec",	FECTYPE_IMX53},
114 	{"fsl,imx6q-fec",	FECTYPE_IMX6 | FECFLAG_GBE},
115 	{"fsl,mvf600-fec",	FECTYPE_GENERIC},
116 	{"fsl,vf-fec",		FECTYPE_GENERIC},
117 	{NULL,		 	FECTYPE_NONE},
118 };
119 
120 /*
121  * Driver data and defines.
122  */
123 #define	RX_DESC_COUNT	64
124 #define	RX_DESC_SIZE	(sizeof(struct ffec_hwdesc) * RX_DESC_COUNT)
125 #define	TX_DESC_COUNT	64
126 #define	TX_DESC_SIZE	(sizeof(struct ffec_hwdesc) * TX_DESC_COUNT)
127 
128 #define	WATCHDOG_TIMEOUT_SECS	5
129 #define	STATS_HARVEST_INTERVAL	3
130 
131 struct ffec_bufmap {
132 	struct mbuf	*mbuf;
133 	bus_dmamap_t	map;
134 };
135 
136 enum {
137 	PHY_CONN_UNKNOWN,
138 	PHY_CONN_MII,
139 	PHY_CONN_RMII,
140 	PHY_CONN_RGMII
141 };
142 
143 struct ffec_softc {
144 	device_t		dev;
145 	device_t		miibus;
146 	struct mii_data *	mii_softc;
147 	struct ifnet		*ifp;
148 	int			if_flags;
149 	struct mtx		mtx;
150 	struct resource		*irq_res;
151 	struct resource		*mem_res;
152 	void *			intr_cookie;
153 	struct callout		ffec_callout;
154 	uint8_t			phy_conn_type;
155 	uint8_t			fectype;
156 	boolean_t		link_is_up;
157 	boolean_t		is_attached;
158 	boolean_t		is_detaching;
159 	int			tx_watchdog_count;
160 	int			stats_harvest_count;
161 
162 	bus_dma_tag_t		rxdesc_tag;
163 	bus_dmamap_t		rxdesc_map;
164 	struct ffec_hwdesc	*rxdesc_ring;
165 	bus_addr_t		rxdesc_ring_paddr;
166 	bus_dma_tag_t		rxbuf_tag;
167 	struct ffec_bufmap	rxbuf_map[RX_DESC_COUNT];
168 	uint32_t		rx_idx;
169 
170 	bus_dma_tag_t		txdesc_tag;
171 	bus_dmamap_t		txdesc_map;
172 	struct ffec_hwdesc	*txdesc_ring;
173 	bus_addr_t		txdesc_ring_paddr;
174 	bus_dma_tag_t		txbuf_tag;
175 	struct ffec_bufmap	txbuf_map[RX_DESC_COUNT];
176 	uint32_t		tx_idx_head;
177 	uint32_t		tx_idx_tail;
178 	int			txcount;
179 };
180 
181 #define	FFEC_LOCK(sc)			mtx_lock(&(sc)->mtx)
182 #define	FFEC_UNLOCK(sc)			mtx_unlock(&(sc)->mtx)
183 #define	FFEC_LOCK_INIT(sc)		mtx_init(&(sc)->mtx, \
184 	    device_get_nameunit((sc)->dev), MTX_NETWORK_LOCK, MTX_DEF)
185 #define	FFEC_LOCK_DESTROY(sc)		mtx_destroy(&(sc)->mtx);
186 #define	FFEC_ASSERT_LOCKED(sc)		mtx_assert(&(sc)->mtx, MA_OWNED);
187 #define	FFEC_ASSERT_UNLOCKED(sc)	mtx_assert(&(sc)->mtx, MA_NOTOWNED);
188 
189 static void ffec_init_locked(struct ffec_softc *sc);
190 static void ffec_stop_locked(struct ffec_softc *sc);
191 static void ffec_txstart_locked(struct ffec_softc *sc);
192 static void ffec_txfinish_locked(struct ffec_softc *sc);
193 
194 static inline uint16_t
195 RD2(struct ffec_softc *sc, bus_size_t off)
196 {
197 
198 	return (bus_read_2(sc->mem_res, off));
199 }
200 
201 static inline void
202 WR2(struct ffec_softc *sc, bus_size_t off, uint16_t val)
203 {
204 
205 	bus_write_2(sc->mem_res, off, val);
206 }
207 
208 static inline uint32_t
209 RD4(struct ffec_softc *sc, bus_size_t off)
210 {
211 
212 	return (bus_read_4(sc->mem_res, off));
213 }
214 
215 static inline void
216 WR4(struct ffec_softc *sc, bus_size_t off, uint32_t val)
217 {
218 
219 	bus_write_4(sc->mem_res, off, val);
220 }
221 
222 static inline uint32_t
223 next_rxidx(struct ffec_softc *sc, uint32_t curidx)
224 {
225 
226 	return ((curidx == RX_DESC_COUNT - 1) ? 0 : curidx + 1);
227 }
228 
229 static inline uint32_t
230 next_txidx(struct ffec_softc *sc, uint32_t curidx)
231 {
232 
233 	return ((curidx == TX_DESC_COUNT - 1) ? 0 : curidx + 1);
234 }
235 
236 static void
237 ffec_get1paddr(void *arg, bus_dma_segment_t *segs, int nsegs, int error)
238 {
239 
240 	if (error != 0)
241 		return;
242 	*(bus_addr_t *)arg = segs[0].ds_addr;
243 }
244 
245 static void
246 ffec_miigasket_setup(struct ffec_softc *sc)
247 {
248 	uint32_t ifmode;
249 
250 	/*
251 	 * We only need the gasket for MII and RMII connections on certain SoCs.
252 	 */
253 
254 	switch (sc->fectype & FECTYPE_MASK)
255 	{
256 	case FECTYPE_IMX53:
257 		break;
258 	default:
259 		return;
260 	}
261 
262 	switch (sc->phy_conn_type)
263 	{
264 	case PHY_CONN_MII:
265 		ifmode = 0;
266 		break;
267 	case PHY_CONN_RMII:
268 		ifmode = FEC_MIIGSK_CFGR_IF_MODE_RMII;
269 		break;
270 	default:
271 		return;
272 	}
273 
274 	/*
275 	 * Disable the gasket, configure for either MII or RMII, then enable.
276 	 */
277 
278 	WR2(sc, FEC_MIIGSK_ENR, 0);
279 	while (RD2(sc, FEC_MIIGSK_ENR) & FEC_MIIGSK_ENR_READY)
280 		continue;
281 
282 	WR2(sc, FEC_MIIGSK_CFGR, ifmode);
283 
284 	WR2(sc, FEC_MIIGSK_ENR, FEC_MIIGSK_ENR_EN);
285 	while (!(RD2(sc, FEC_MIIGSK_ENR) & FEC_MIIGSK_ENR_READY))
286 		continue;
287 }
288 
289 static boolean_t
290 ffec_miibus_iowait(struct ffec_softc *sc)
291 {
292 	uint32_t timeout;
293 
294 	for (timeout = 10000; timeout != 0; --timeout)
295 		if (RD4(sc, FEC_IER_REG) & FEC_IER_MII)
296 			return (true);
297 
298 	return (false);
299 }
300 
301 static int
302 ffec_miibus_readreg(device_t dev, int phy, int reg)
303 {
304 	struct ffec_softc *sc;
305 	int val;
306 
307 	sc = device_get_softc(dev);
308 
309 	WR4(sc, FEC_IER_REG, FEC_IER_MII);
310 
311 	WR4(sc, FEC_MMFR_REG, FEC_MMFR_OP_READ |
312 	    FEC_MMFR_ST_VALUE | FEC_MMFR_TA_VALUE |
313 	    ((phy << FEC_MMFR_PA_SHIFT) & FEC_MMFR_PA_MASK) |
314 	    ((reg << FEC_MMFR_RA_SHIFT) & FEC_MMFR_RA_MASK));
315 
316 	if (!ffec_miibus_iowait(sc)) {
317 		device_printf(dev, "timeout waiting for mii read\n");
318 		return (-1); /* All-ones is a symptom of bad mdio. */
319 	}
320 
321 	val = RD4(sc, FEC_MMFR_REG) & FEC_MMFR_DATA_MASK;
322 
323 	return (val);
324 }
325 
326 static int
327 ffec_miibus_writereg(device_t dev, int phy, int reg, int val)
328 {
329 	struct ffec_softc *sc;
330 
331 	sc = device_get_softc(dev);
332 
333 	WR4(sc, FEC_IER_REG, FEC_IER_MII);
334 
335 	WR4(sc, FEC_MMFR_REG, FEC_MMFR_OP_WRITE |
336 	    FEC_MMFR_ST_VALUE | FEC_MMFR_TA_VALUE |
337 	    ((phy << FEC_MMFR_PA_SHIFT) & FEC_MMFR_PA_MASK) |
338 	    ((reg << FEC_MMFR_RA_SHIFT) & FEC_MMFR_RA_MASK) |
339 	    (val & FEC_MMFR_DATA_MASK));
340 
341 	if (!ffec_miibus_iowait(sc)) {
342 		device_printf(dev, "timeout waiting for mii write\n");
343 		return (-1);
344 	}
345 
346 	return (0);
347 }
348 
349 static void
350 ffec_miibus_statchg(device_t dev)
351 {
352 	struct ffec_softc *sc;
353 	struct mii_data *mii;
354 	uint32_t ecr, rcr, tcr;
355 
356 	/*
357 	 * Called by the MII bus driver when the PHY establishes link to set the
358 	 * MAC interface registers.
359 	 */
360 
361 	sc = device_get_softc(dev);
362 
363 	FFEC_ASSERT_LOCKED(sc);
364 
365 	mii = sc->mii_softc;
366 
367 	if (mii->mii_media_status & IFM_ACTIVE)
368 		sc->link_is_up = true;
369 	else
370 		sc->link_is_up = false;
371 
372 	ecr = RD4(sc, FEC_ECR_REG) & ~FEC_ECR_SPEED;
373 	rcr = RD4(sc, FEC_RCR_REG) & ~(FEC_RCR_RMII_10T | FEC_RCR_RMII_MODE |
374 	    FEC_RCR_RGMII_EN | FEC_RCR_DRT | FEC_RCR_FCE);
375 	tcr = RD4(sc, FEC_TCR_REG) & ~FEC_TCR_FDEN;
376 
377 	rcr |= FEC_RCR_MII_MODE; /* Must always be on even for R[G]MII. */
378 	switch (sc->phy_conn_type) {
379 	case PHY_CONN_MII:
380 		break;
381 	case PHY_CONN_RMII:
382 		rcr |= FEC_RCR_RMII_MODE;
383 		break;
384 	case PHY_CONN_RGMII:
385 		rcr |= FEC_RCR_RGMII_EN;
386 		break;
387 	}
388 
389 	switch (IFM_SUBTYPE(mii->mii_media_active)) {
390 	case IFM_1000_T:
391 	case IFM_1000_SX:
392 		ecr |= FEC_ECR_SPEED;
393 		break;
394 	case IFM_100_TX:
395 		/* Not-FEC_ECR_SPEED + not-FEC_RCR_RMII_10T means 100TX */
396 		break;
397 	case IFM_10_T:
398 		rcr |= FEC_RCR_RMII_10T;
399 		break;
400 	case IFM_NONE:
401 		sc->link_is_up = false;
402 		return;
403 	default:
404 		sc->link_is_up = false;
405 		device_printf(dev, "Unsupported media %u\n",
406 		    IFM_SUBTYPE(mii->mii_media_active));
407 		return;
408 	}
409 
410 	if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0)
411 		tcr |= FEC_TCR_FDEN;
412 	else
413 		rcr |= FEC_RCR_DRT;
414 
415 	if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FLOW) != 0)
416 		rcr |= FEC_RCR_FCE;
417 
418 	WR4(sc, FEC_RCR_REG, rcr);
419 	WR4(sc, FEC_TCR_REG, tcr);
420 	WR4(sc, FEC_ECR_REG, ecr);
421 }
422 
423 static void
424 ffec_media_status(struct ifnet * ifp, struct ifmediareq *ifmr)
425 {
426 	struct ffec_softc *sc;
427 	struct mii_data *mii;
428 
429 
430 	sc = ifp->if_softc;
431 	mii = sc->mii_softc;
432 	FFEC_LOCK(sc);
433 	mii_pollstat(mii);
434 	ifmr->ifm_active = mii->mii_media_active;
435 	ifmr->ifm_status = mii->mii_media_status;
436 	FFEC_UNLOCK(sc);
437 }
438 
439 static int
440 ffec_media_change_locked(struct ffec_softc *sc)
441 {
442 
443 	return (mii_mediachg(sc->mii_softc));
444 }
445 
446 static int
447 ffec_media_change(struct ifnet * ifp)
448 {
449 	struct ffec_softc *sc;
450 	int error;
451 
452 	sc = ifp->if_softc;
453 
454 	FFEC_LOCK(sc);
455 	error = ffec_media_change_locked(sc);
456 	FFEC_UNLOCK(sc);
457 	return (error);
458 }
459 
460 static void ffec_clear_stats(struct ffec_softc *sc)
461 {
462 
463 	WR4(sc, FEC_RMON_R_PACKETS, 0);
464 	WR4(sc, FEC_RMON_R_MC_PKT, 0);
465 	WR4(sc, FEC_RMON_R_CRC_ALIGN, 0);
466 	WR4(sc, FEC_RMON_R_UNDERSIZE, 0);
467 	WR4(sc, FEC_RMON_R_OVERSIZE, 0);
468 	WR4(sc, FEC_RMON_R_FRAG, 0);
469 	WR4(sc, FEC_RMON_R_JAB, 0);
470 	WR4(sc, FEC_RMON_T_PACKETS, 0);
471 	WR4(sc, FEC_RMON_T_MC_PKT, 0);
472 	WR4(sc, FEC_RMON_T_CRC_ALIGN, 0);
473 	WR4(sc, FEC_RMON_T_UNDERSIZE, 0);
474 	WR4(sc, FEC_RMON_T_OVERSIZE , 0);
475 	WR4(sc, FEC_RMON_T_FRAG, 0);
476 	WR4(sc, FEC_RMON_T_JAB, 0);
477 	WR4(sc, FEC_RMON_T_COL, 0);
478 }
479 
480 static void
481 ffec_harvest_stats(struct ffec_softc *sc)
482 {
483 	struct ifnet *ifp;
484 
485 	/* We don't need to harvest too often. */
486 	if (++sc->stats_harvest_count < STATS_HARVEST_INTERVAL)
487 		return;
488 
489 	/*
490 	 * Try to avoid harvesting unless the IDLE flag is on, but if it has
491 	 * been too long just go ahead and do it anyway, the worst that'll
492 	 * happen is we'll lose a packet count or two as we clear at the end.
493 	 */
494 	if (sc->stats_harvest_count < (2 * STATS_HARVEST_INTERVAL) &&
495 	    ((RD4(sc, FEC_MIBC_REG) & FEC_MIBC_IDLE) == 0))
496 		return;
497 
498 	sc->stats_harvest_count = 0;
499 	ifp = sc->ifp;
500 
501 	ifp->if_ipackets   += RD4(sc, FEC_RMON_R_PACKETS);
502 	ifp->if_imcasts    += RD4(sc, FEC_RMON_R_MC_PKT);
503 	ifp->if_ierrors    += RD4(sc, FEC_RMON_R_CRC_ALIGN);
504 	ifp->if_ierrors    += RD4(sc, FEC_RMON_R_UNDERSIZE);
505 	ifp->if_ierrors    += RD4(sc, FEC_RMON_R_OVERSIZE);
506 	ifp->if_ierrors    += RD4(sc, FEC_RMON_R_FRAG);
507 	ifp->if_ierrors    += RD4(sc, FEC_RMON_R_JAB);
508 
509 	ifp->if_opackets   += RD4(sc, FEC_RMON_T_PACKETS);
510 	ifp->if_omcasts    += RD4(sc, FEC_RMON_T_MC_PKT);
511 	ifp->if_oerrors    += RD4(sc, FEC_RMON_T_CRC_ALIGN);
512 	ifp->if_oerrors    += RD4(sc, FEC_RMON_T_UNDERSIZE);
513 	ifp->if_oerrors    += RD4(sc, FEC_RMON_T_OVERSIZE );
514 	ifp->if_oerrors    += RD4(sc, FEC_RMON_T_FRAG);
515 	ifp->if_oerrors    += RD4(sc, FEC_RMON_T_JAB);
516 
517 	ifp->if_collisions += RD4(sc, FEC_RMON_T_COL);
518 
519 	ffec_clear_stats(sc);
520 }
521 
522 static void
523 ffec_tick(void *arg)
524 {
525 	struct ffec_softc *sc;
526 	struct ifnet *ifp;
527 	int link_was_up;
528 
529 	sc = arg;
530 
531 	FFEC_ASSERT_LOCKED(sc);
532 
533 	ifp = sc->ifp;
534 
535 	if (!(ifp->if_drv_flags & IFF_DRV_RUNNING))
536 	    return;
537 
538 	/*
539 	 * Typical tx watchdog.  If this fires it indicates that we enqueued
540 	 * packets for output and never got a txdone interrupt for them.  Maybe
541 	 * it's a missed interrupt somehow, just pretend we got one.
542 	 */
543 	if (sc->tx_watchdog_count > 0) {
544 		if (--sc->tx_watchdog_count == 0) {
545 			ffec_txfinish_locked(sc);
546 		}
547 	}
548 
549 	/* Gather stats from hardware counters. */
550 	ffec_harvest_stats(sc);
551 
552 	/* Check the media status. */
553 	link_was_up = sc->link_is_up;
554 	mii_tick(sc->mii_softc);
555 	if (sc->link_is_up && !link_was_up)
556 		ffec_txstart_locked(sc);
557 
558 	/* Schedule another check one second from now. */
559 	callout_reset(&sc->ffec_callout, hz, ffec_tick, sc);
560 }
561 
562 inline static uint32_t
563 ffec_setup_txdesc(struct ffec_softc *sc, int idx, bus_addr_t paddr,
564     uint32_t len)
565 {
566 	uint32_t nidx;
567 	uint32_t flags;
568 
569 	nidx = next_txidx(sc, idx);
570 
571 	/* Addr/len 0 means we're clearing the descriptor after xmit done. */
572 	if (paddr == 0 || len == 0) {
573 		flags = 0;
574 		--sc->txcount;
575 	} else {
576 		flags = FEC_TXDESC_READY | FEC_TXDESC_L | FEC_TXDESC_TC;
577 		++sc->txcount;
578 	}
579 	if (nidx == 0)
580 		flags |= FEC_TXDESC_WRAP;
581 
582 	/*
583 	 * The hardware requires 32-bit physical addresses.  We set up the dma
584 	 * tag to indicate that, so the cast to uint32_t should never lose
585 	 * significant bits.
586 	 */
587 	sc->txdesc_ring[idx].buf_paddr = (uint32_t)paddr;
588 	sc->txdesc_ring[idx].flags_len = flags | len; /* Must be set last! */
589 
590 	return (nidx);
591 }
592 
593 static int
594 ffec_setup_txbuf(struct ffec_softc *sc, int idx, struct mbuf **mp)
595 {
596 	struct mbuf * m;
597 	int error, nsegs;
598 	struct bus_dma_segment seg;
599 
600 	if ((m = m_defrag(*mp, M_NOWAIT)) == NULL)
601 		return (ENOMEM);
602 	*mp = m;
603 
604 	error = bus_dmamap_load_mbuf_sg(sc->txbuf_tag, sc->txbuf_map[idx].map,
605 	    m, &seg, &nsegs, 0);
606 	if (error != 0) {
607 		return (ENOMEM);
608 	}
609 	bus_dmamap_sync(sc->txbuf_tag, sc->txbuf_map[idx].map,
610 	    BUS_DMASYNC_PREWRITE);
611 
612 	sc->txbuf_map[idx].mbuf = m;
613 	ffec_setup_txdesc(sc, idx, seg.ds_addr, seg.ds_len);
614 
615 	return (0);
616 
617 }
618 
619 static void
620 ffec_txstart_locked(struct ffec_softc *sc)
621 {
622 	struct ifnet *ifp;
623 	struct mbuf *m;
624 	int enqueued;
625 
626 	FFEC_ASSERT_LOCKED(sc);
627 
628 	if (!sc->link_is_up)
629 		return;
630 
631 	ifp = sc->ifp;
632 
633 	if (ifp->if_drv_flags & IFF_DRV_OACTIVE)
634 		return;
635 
636 	enqueued = 0;
637 
638 	for (;;) {
639 		if (sc->txcount == (TX_DESC_COUNT-1)) {
640 			ifp->if_drv_flags |= IFF_DRV_OACTIVE;
641 			break;
642 		}
643 		IFQ_DRV_DEQUEUE(&ifp->if_snd, m);
644 		if (m == NULL)
645 			break;
646 		if (ffec_setup_txbuf(sc, sc->tx_idx_head, &m) != 0) {
647 			IFQ_DRV_PREPEND(&ifp->if_snd, m);
648 			break;
649 		}
650 		BPF_MTAP(ifp, m);
651 		sc->tx_idx_head = next_txidx(sc, sc->tx_idx_head);
652 		++enqueued;
653 	}
654 
655 	if (enqueued != 0) {
656 		WR4(sc, FEC_TDAR_REG, FEC_TDAR_TDAR);
657 		sc->tx_watchdog_count = WATCHDOG_TIMEOUT_SECS;
658 	}
659 }
660 
661 static void
662 ffec_txstart(struct ifnet *ifp)
663 {
664 	struct ffec_softc *sc = ifp->if_softc;
665 
666 	FFEC_LOCK(sc);
667 	ffec_txstart_locked(sc);
668 	FFEC_UNLOCK(sc);
669 }
670 
671 static void
672 ffec_txfinish_locked(struct ffec_softc *sc)
673 {
674 	struct ifnet *ifp;
675 	struct ffec_hwdesc *desc;
676 	struct ffec_bufmap *bmap;
677 	boolean_t retired_buffer;
678 
679 	FFEC_ASSERT_LOCKED(sc);
680 
681 	ifp = sc->ifp;
682 	retired_buffer = false;
683 	while (sc->tx_idx_tail != sc->tx_idx_head) {
684 		desc = &sc->txdesc_ring[sc->tx_idx_tail];
685 		if (desc->flags_len & FEC_TXDESC_READY)
686 			break;
687 		retired_buffer = true;
688 		bmap = &sc->txbuf_map[sc->tx_idx_tail];
689 		bus_dmamap_sync(sc->txbuf_tag, bmap->map,
690 		    BUS_DMASYNC_POSTWRITE);
691 		bus_dmamap_unload(sc->txbuf_tag, bmap->map);
692 		m_freem(bmap->mbuf);
693 		bmap->mbuf = NULL;
694 		ffec_setup_txdesc(sc, sc->tx_idx_tail, 0, 0);
695 		sc->tx_idx_tail = next_txidx(sc, sc->tx_idx_tail);
696 	}
697 
698 	/*
699 	 * If we retired any buffers, there will be open tx slots available in
700 	 * the descriptor ring, go try to start some new output.
701 	 */
702 	if (retired_buffer) {
703 		ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
704 		ffec_txstart_locked(sc);
705 	}
706 
707 	/* If there are no buffers outstanding, muzzle the watchdog. */
708 	if (sc->tx_idx_tail == sc->tx_idx_head) {
709 		sc->tx_watchdog_count = 0;
710 	}
711 }
712 
713 inline static uint32_t
714 ffec_setup_rxdesc(struct ffec_softc *sc, int idx, bus_addr_t paddr)
715 {
716 	uint32_t nidx;
717 
718 	/*
719 	 * The hardware requires 32-bit physical addresses.  We set up the dma
720 	 * tag to indicate that, so the cast to uint32_t should never lose
721 	 * significant bits.
722 	 */
723 	nidx = next_rxidx(sc, idx);
724 	sc->rxdesc_ring[idx].buf_paddr = (uint32_t)paddr;
725 	sc->rxdesc_ring[idx].flags_len = FEC_RXDESC_EMPTY |
726 		((nidx == 0) ? FEC_RXDESC_WRAP : 0);
727 
728 	return (nidx);
729 }
730 
731 static int
732 ffec_setup_rxbuf(struct ffec_softc *sc, int idx, struct mbuf * m)
733 {
734 	int error, nsegs;
735 	struct bus_dma_segment seg;
736 
737 	/*
738 	 * We need to leave at least ETHER_ALIGN bytes free at the beginning of
739 	 * the buffer to allow the data to be re-aligned after receiving it (by
740 	 * copying it backwards ETHER_ALIGN bytes in the same buffer).  We also
741 	 * have to ensure that the beginning of the buffer is aligned to the
742 	 * hardware's requirements.
743 	 */
744 	m_adj(m, roundup(ETHER_ALIGN, FEC_RXBUF_ALIGN));
745 
746 	error = bus_dmamap_load_mbuf_sg(sc->rxbuf_tag, sc->rxbuf_map[idx].map,
747 	    m, &seg, &nsegs, 0);
748 	if (error != 0) {
749 		return (error);
750 	}
751 
752 	bus_dmamap_sync(sc->rxbuf_tag, sc->rxbuf_map[idx].map,
753 	    BUS_DMASYNC_PREREAD);
754 
755 	sc->rxbuf_map[idx].mbuf = m;
756 	ffec_setup_rxdesc(sc, idx, seg.ds_addr);
757 
758 	return (0);
759 }
760 
761 static struct mbuf *
762 ffec_alloc_mbufcl(struct ffec_softc *sc)
763 {
764 	struct mbuf *m;
765 
766 	m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR);
767 	m->m_pkthdr.len = m->m_len = m->m_ext.ext_size;
768 
769 	return (m);
770 }
771 
772 static void
773 ffec_rxfinish_onebuf(struct ffec_softc *sc, int len)
774 {
775 	struct mbuf *m, *newmbuf;
776 	struct ffec_bufmap *bmap;
777 	uint8_t *dst, *src;
778 	int error;
779 
780 	/*
781 	 *  First try to get a new mbuf to plug into this slot in the rx ring.
782 	 *  If that fails, drop the current packet and recycle the current
783 	 *  mbuf, which is still mapped and loaded.
784 	 */
785 	if ((newmbuf = ffec_alloc_mbufcl(sc)) == NULL) {
786 		++sc->ifp->if_iqdrops;
787 		ffec_setup_rxdesc(sc, sc->rx_idx,
788 		    sc->rxdesc_ring[sc->rx_idx].buf_paddr);
789 		return;
790 	}
791 
792 	/*
793 	 *  Unfortunately, the protocol headers need to be aligned on a 32-bit
794 	 *  boundary for the upper layers.  The hardware requires receive
795 	 *  buffers to be 16-byte aligned.  The ethernet header is 14 bytes,
796 	 *  leaving the protocol header unaligned.  We used m_adj() after
797 	 *  allocating the buffer to leave empty space at the start of the
798 	 *  buffer, now we'll use the alignment agnostic bcopy() routine to
799 	 *  shuffle all the data backwards 2 bytes and adjust m_data.
800 	 *
801 	 *  XXX imx6 hardware is able to do this 2-byte alignment by setting the
802 	 *  SHIFT16 bit in the RACC register.  Older hardware doesn't have that
803 	 *  feature, but for them could we speed this up by copying just the
804 	 *  protocol headers into their own small mbuf then chaining the cluster
805 	 *  to it?  That way we'd only need to copy like 64 bytes or whatever
806 	 *  the biggest header is, instead of the whole 1530ish-byte frame.
807 	 */
808 
809 	FFEC_UNLOCK(sc);
810 
811 	bmap = &sc->rxbuf_map[sc->rx_idx];
812 	len -= ETHER_CRC_LEN;
813 	bus_dmamap_sync(sc->rxbuf_tag, bmap->map, BUS_DMASYNC_POSTREAD);
814 	bus_dmamap_unload(sc->rxbuf_tag, bmap->map);
815 	m = bmap->mbuf;
816 	bmap->mbuf = NULL;
817 	m->m_len = len;
818 	m->m_pkthdr.len = len;
819 	m->m_pkthdr.rcvif = sc->ifp;
820 
821 	src = mtod(m, uint8_t*);
822 	dst = src - ETHER_ALIGN;
823 	bcopy(src, dst, len);
824 	m->m_data = dst;
825 	sc->ifp->if_input(sc->ifp, m);
826 
827 	FFEC_LOCK(sc);
828 
829 	if ((error = ffec_setup_rxbuf(sc, sc->rx_idx, newmbuf)) != 0) {
830 		device_printf(sc->dev, "ffec_setup_rxbuf error %d\n", error);
831 		/* XXX Now what?  We've got a hole in the rx ring. */
832 	}
833 
834 }
835 
836 static void
837 ffec_rxfinish_locked(struct ffec_softc *sc)
838 {
839 	struct ffec_hwdesc *desc;
840 	int len;
841 	boolean_t produced_empty_buffer;
842 
843 	FFEC_ASSERT_LOCKED(sc);
844 
845 	produced_empty_buffer = false;
846 	for (;;) {
847 		desc = &sc->rxdesc_ring[sc->rx_idx];
848 		if (desc->flags_len & FEC_RXDESC_EMPTY)
849 			break;
850 		produced_empty_buffer = true;
851 		len = (desc->flags_len & FEC_RXDESC_LEN_MASK);
852 		if (len < 64) {
853 			/*
854 			 * Just recycle the descriptor and continue.           .
855 			 */
856 			ffec_setup_rxdesc(sc, sc->rx_idx,
857 			    sc->rxdesc_ring[sc->rx_idx].buf_paddr);
858 		} else if ((desc->flags_len & FEC_RXDESC_L) == 0) {
859 			/*
860 			 * The entire frame is not in this buffer.  Impossible.
861 			 * Recycle the descriptor and continue.
862 			 *
863 			 * XXX what's the right way to handle this? Probably we
864 			 * should stop/init the hardware because this should
865 			 * just really never happen when we have buffers bigger
866 			 * than the maximum frame size.
867 			 */
868 			device_printf(sc->dev,
869 			    "fec_rxfinish: received frame without LAST bit set");
870 			ffec_setup_rxdesc(sc, sc->rx_idx,
871 			    sc->rxdesc_ring[sc->rx_idx].buf_paddr);
872 		} else if (desc->flags_len & FEC_RXDESC_ERROR_BITS) {
873 			/*
874 			 *  Something went wrong with receiving the frame, we
875 			 *  don't care what (the hardware has counted the error
876 			 *  in the stats registers already), we just reuse the
877 			 *  same mbuf, which is still dma-mapped, by resetting
878 			 *  the rx descriptor.
879 			 */
880 			ffec_setup_rxdesc(sc, sc->rx_idx,
881 			    sc->rxdesc_ring[sc->rx_idx].buf_paddr);
882 		} else {
883 			/*
884 			 *  Normal case: a good frame all in one buffer.
885 			 */
886 			ffec_rxfinish_onebuf(sc, len);
887 		}
888 		sc->rx_idx = next_rxidx(sc, sc->rx_idx);
889 	}
890 
891 	if (produced_empty_buffer) {
892 		WR4(sc, FEC_RDAR_REG, FEC_RDAR_RDAR);
893 	}
894 }
895 
896 static void
897 ffec_get_hwaddr(struct ffec_softc *sc, uint8_t *hwaddr)
898 {
899 	uint32_t palr, paur, rnd;
900 
901 	/*
902 	 * Try to recover a MAC address from the running hardware. If there's
903 	 * something non-zero there, assume the bootloader did the right thing
904 	 * and just use it.
905 	 *
906 	 * Otherwise, set the address to a convenient locally assigned address,
907 	 * 'bsd' + random 24 low-order bits.  'b' is 0x62, which has the locally
908 	 * assigned bit set, and the broadcast/multicast bit clear.
909 	 */
910 	palr = RD4(sc, FEC_PALR_REG);
911 	paur = RD4(sc, FEC_PAUR_REG) & FEC_PAUR_PADDR2_MASK;
912 	if ((palr | paur) != 0) {
913 		hwaddr[0] = palr >> 24;
914 		hwaddr[1] = palr >> 16;
915 		hwaddr[2] = palr >>  8;
916 		hwaddr[3] = palr >>  0;
917 		hwaddr[4] = paur >> 24;
918 		hwaddr[5] = paur >> 16;
919 	} else {
920 		rnd = arc4random() & 0x00ffffff;
921 		hwaddr[0] = 'b';
922 		hwaddr[1] = 's';
923 		hwaddr[2] = 'd';
924 		hwaddr[3] = rnd >> 16;
925 		hwaddr[4] = rnd >>  8;
926 		hwaddr[5] = rnd >>  0;
927 	}
928 
929 	if (bootverbose) {
930 		device_printf(sc->dev,
931 		    "MAC address %02x:%02x:%02x:%02x:%02x:%02x:\n",
932 		    hwaddr[0], hwaddr[1], hwaddr[2],
933 		    hwaddr[3], hwaddr[4], hwaddr[5]);
934 	}
935 }
936 
937 static void
938 ffec_setup_rxfilter(struct ffec_softc *sc)
939 {
940 	struct ifnet *ifp;
941 	struct ifmultiaddr *ifma;
942 	uint8_t *eaddr;
943 	uint32_t crc;
944 	uint64_t ghash, ihash;
945 
946 	FFEC_ASSERT_LOCKED(sc);
947 
948 	ifp = sc->ifp;
949 
950 	/*
951 	 * Set the multicast (group) filter hash.
952 	 */
953 	if ((ifp->if_flags & IFF_ALLMULTI))
954 		ghash = 0xffffffffffffffffLLU;
955 	else {
956 		ghash = 0;
957 		if_maddr_rlock(ifp);
958 		TAILQ_FOREACH(ifma, &sc->ifp->if_multiaddrs, ifma_link) {
959 			if (ifma->ifma_addr->sa_family != AF_LINK)
960 				continue;
961 			crc = ether_crc32_be(LLADDR((struct sockaddr_dl *)
962 			    ifma->ifma_addr), ETHER_ADDR_LEN);
963 			ghash |= 1 << (crc & 0x3f);
964 		}
965 		if_maddr_runlock(ifp);
966 	}
967 	WR4(sc, FEC_GAUR_REG, (uint32_t)(ghash >> 32));
968 	WR4(sc, FEC_GALR_REG, (uint32_t)ghash);
969 
970 	/*
971 	 * Set the individual address filter hash.
972 	 *
973 	 * XXX Is 0 the right value when promiscuous is off?  This hw feature
974 	 * seems to support the concept of MAC address aliases, does such a
975 	 * thing even exist?
976 	 */
977 	if ((ifp->if_flags & IFF_PROMISC))
978 		ihash = 0xffffffffffffffffLLU;
979 	else {
980 		ihash = 0;
981 	}
982 	WR4(sc, FEC_IAUR_REG, (uint32_t)(ihash >> 32));
983 	WR4(sc, FEC_IALR_REG, (uint32_t)ihash);
984 
985 	/*
986 	 * Set the primary address.
987 	 */
988 	eaddr = IF_LLADDR(ifp);
989 	WR4(sc, FEC_PALR_REG, (eaddr[0] << 24) | (eaddr[1] << 16) |
990 	    (eaddr[2] <<  8) | eaddr[3]);
991 	WR4(sc, FEC_PAUR_REG, (eaddr[4] << 24) | (eaddr[5] << 16));
992 }
993 
994 static void
995 ffec_stop_locked(struct ffec_softc *sc)
996 {
997 	struct ifnet *ifp;
998 	struct ffec_hwdesc *desc;
999 	struct ffec_bufmap *bmap;
1000 	int idx;
1001 
1002 	FFEC_ASSERT_LOCKED(sc);
1003 
1004 	ifp = sc->ifp;
1005 	ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
1006 	sc->tx_watchdog_count = 0;
1007 	sc->stats_harvest_count = 0;
1008 
1009 	/*
1010 	 * Stop the hardware, mask all interrupts, and clear all current
1011 	 * interrupt status bits.
1012 	 */
1013 	WR4(sc, FEC_ECR_REG, RD4(sc, FEC_ECR_REG) & ~FEC_ECR_ETHEREN);
1014 	WR4(sc, FEC_IEM_REG, 0x00000000);
1015 	WR4(sc, FEC_IER_REG, 0xffffffff);
1016 
1017 	/*
1018 	 * Stop the media-check callout.  Do not use callout_drain() because
1019 	 * we're holding a mutex the callout acquires, and if it's currently
1020 	 * waiting to acquire it, we'd deadlock.  If it is waiting now, the
1021 	 * ffec_tick() routine will return without doing anything when it sees
1022 	 * that IFF_DRV_RUNNING is not set, so avoiding callout_drain() is safe.
1023 	 */
1024 	callout_stop(&sc->ffec_callout);
1025 
1026 	/*
1027 	 * Discard all untransmitted buffers.  Each buffer is simply freed;
1028 	 * it's as if the bits were transmitted and then lost on the wire.
1029 	 *
1030 	 * XXX Is this right?  Or should we use IFQ_DRV_PREPEND() to put them
1031 	 * back on the queue for when we get restarted later?
1032 	 */
1033 	idx = sc->tx_idx_tail;
1034 	while (idx != sc->tx_idx_head) {
1035 		desc = &sc->txdesc_ring[idx];
1036 		bmap = &sc->txbuf_map[idx];
1037 		if (desc->buf_paddr != 0) {
1038 			bus_dmamap_unload(sc->txbuf_tag, bmap->map);
1039 			m_freem(bmap->mbuf);
1040 			bmap->mbuf = NULL;
1041 			ffec_setup_txdesc(sc, idx, 0, 0);
1042 		}
1043 		idx = next_txidx(sc, idx);
1044 	}
1045 
1046 	/*
1047 	 * Discard all unprocessed receive buffers.  This amounts to just
1048 	 * pretending that nothing ever got received into them.  We reuse the
1049 	 * mbuf already mapped for each desc, simply turning the EMPTY flags
1050 	 * back on so they'll get reused when we start up again.
1051 	 */
1052 	for (idx = 0; idx < RX_DESC_COUNT; ++idx) {
1053 		desc = &sc->rxdesc_ring[idx];
1054 		ffec_setup_rxdesc(sc, idx, desc->buf_paddr);
1055 	}
1056 }
1057 
1058 static void
1059 ffec_init_locked(struct ffec_softc *sc)
1060 {
1061 	struct ifnet *ifp = sc->ifp;
1062 	uint32_t maxbuf, maxfl, regval;
1063 
1064 	FFEC_ASSERT_LOCKED(sc);
1065 
1066 	/*
1067 	 * The hardware has a limit of 0x7ff as the max frame length (see
1068 	 * comments for MRBR below), and we use mbuf clusters as receive
1069 	 * buffers, and we currently are designed to receive an entire frame
1070 	 * into a single buffer.
1071 	 *
1072 	 * We start with a MCLBYTES-sized cluster, but we have to offset into
1073 	 * the buffer by ETHER_ALIGN to make room for post-receive re-alignment,
1074 	 * and then that value has to be rounded up to the hardware's DMA
1075 	 * alignment requirements, so all in all our buffer is that much smaller
1076 	 * than MCLBYTES.
1077 	 *
1078 	 * The resulting value is used as the frame truncation length and the
1079 	 * max buffer receive buffer size for now.  It'll become more complex
1080 	 * when we support jumbo frames and receiving fragments of them into
1081 	 * separate buffers.
1082 	 */
1083 	maxbuf = MCLBYTES - roundup(ETHER_ALIGN, FEC_RXBUF_ALIGN);
1084 	maxfl = min(maxbuf, 0x7ff);
1085 
1086 	if (ifp->if_drv_flags & IFF_DRV_RUNNING)
1087 		return;
1088 
1089 	/* Mask all interrupts and clear all current interrupt status bits. */
1090 	WR4(sc, FEC_IEM_REG, 0x00000000);
1091 	WR4(sc, FEC_IER_REG, 0xffffffff);
1092 
1093 	/*
1094 	 * Go set up palr/puar, galr/gaur, ialr/iaur.
1095 	 */
1096 	ffec_setup_rxfilter(sc);
1097 
1098 	/*
1099 	 * TFWR - Transmit FIFO watermark register.
1100 	 *
1101 	 * Set the transmit fifo watermark register to "store and forward" mode
1102 	 * and also set a threshold of 128 bytes in the fifo before transmission
1103 	 * of a frame begins (to avoid dma underruns).  Recent FEC hardware
1104 	 * supports STRFWD and when that bit is set, the watermark level in the
1105 	 * low bits is ignored.  Older hardware doesn't have STRFWD, but writing
1106 	 * to that bit is innocuous, and the TWFR bits get used instead.
1107 	 */
1108 	WR4(sc, FEC_TFWR_REG, FEC_TFWR_STRFWD | FEC_TFWR_TWFR_128BYTE);
1109 
1110 	/* RCR - Receive control register.
1111 	 *
1112 	 * Set max frame length + clean out anything left from u-boot.
1113 	 */
1114 	WR4(sc, FEC_RCR_REG, (maxfl << FEC_RCR_MAX_FL_SHIFT));
1115 
1116 	/*
1117 	 * TCR - Transmit control register.
1118 	 *
1119 	 * Clean out anything left from u-boot.  Any necessary values are set in
1120 	 * ffec_miibus_statchg() based on the media type.
1121 	 */
1122 	WR4(sc, FEC_TCR_REG, 0);
1123 
1124 	/*
1125 	 * OPD - Opcode/pause duration.
1126 	 *
1127 	 * XXX These magic numbers come from u-boot.
1128 	 */
1129 	WR4(sc, FEC_OPD_REG, 0x00010020);
1130 
1131 	/*
1132 	 * FRSR - Fifo receive start register.
1133 	 *
1134 	 * This register does not exist on imx6, it is present on earlier
1135 	 * hardware. The u-boot code sets this to a non-default value that's 32
1136 	 * bytes larger than the default, with no clue as to why.  The default
1137 	 * value should work fine, so there's no code to init it here.
1138 	 */
1139 
1140 	/*
1141 	 *  MRBR - Max RX buffer size.
1142 	 *
1143 	 *  Note: For hardware prior to imx6 this value cannot exceed 0x07ff,
1144 	 *  but the datasheet says no such thing for imx6.  On the imx6, setting
1145 	 *  this to 2K without setting EN1588 resulted in a crazy runaway
1146 	 *  receive loop in the hardware, where every rx descriptor in the ring
1147 	 *  had its EMPTY flag cleared, no completion or error flags set, and a
1148 	 *  length of zero.  I think maybe you can only exceed it when EN1588 is
1149 	 *  set, like maybe that's what enables jumbo frames, because in general
1150 	 *  the EN1588 flag seems to be the "enable new stuff" vs. "be legacy-
1151 	 *  compatible" flag.
1152 	 */
1153 	WR4(sc, FEC_MRBR_REG, maxfl << FEC_MRBR_R_BUF_SIZE_SHIFT);
1154 
1155 	/*
1156 	 * FTRL - Frame truncation length.
1157 	 *
1158 	 * Must be greater than or equal to the value set in FEC_RCR_MAXFL.
1159 	 */
1160 	WR4(sc, FEC_FTRL_REG, maxfl);
1161 
1162 	/*
1163 	 * RDSR / TDSR descriptor ring pointers.
1164 	 *
1165 	 * When we turn on ECR_ETHEREN at the end, the hardware zeroes its
1166 	 * internal current descriptor index values for both rings, so we zero
1167 	 * our index values as well.
1168 	 */
1169 	sc->rx_idx = 0;
1170 	sc->tx_idx_head = sc->tx_idx_tail = 0;
1171 	sc->txcount = 0;
1172 	WR4(sc, FEC_RDSR_REG, sc->rxdesc_ring_paddr);
1173 	WR4(sc, FEC_TDSR_REG, sc->txdesc_ring_paddr);
1174 
1175 	/*
1176 	 * EIM - interrupt mask register.
1177 	 *
1178 	 * We always enable the same set of interrupts while running; unlike
1179 	 * some drivers there's no need to change the mask on the fly depending
1180 	 * on what operations are in progress.
1181 	 */
1182 	WR4(sc, FEC_IEM_REG, FEC_IER_TXF | FEC_IER_RXF | FEC_IER_EBERR);
1183 
1184 	/*
1185 	 * MIBC - MIB control (hardware stats).
1186 	 */
1187 	regval = RD4(sc, FEC_MIBC_REG);
1188 	WR4(sc, FEC_MIBC_REG, regval | FEC_MIBC_DIS);
1189 	ffec_clear_stats(sc);
1190 	WR4(sc, FEC_MIBC_REG, regval & ~FEC_MIBC_DIS);
1191 
1192 	/*
1193 	 * ECR - Ethernet control register.
1194 	 *
1195 	 * This must happen after all the other config registers are set.  If
1196 	 * we're running on little-endian hardware, also set the flag for byte-
1197 	 * swapping descriptor ring entries.  This flag doesn't exist on older
1198 	 * hardware, but it can be safely set -- the bit position it occupies
1199 	 * was unused.
1200 	 */
1201 	regval = RD4(sc, FEC_ECR_REG);
1202 #if _BYTE_ORDER == _LITTLE_ENDIAN
1203 	regval |= FEC_ECR_DBSWP;
1204 #endif
1205 	regval |= FEC_ECR_ETHEREN;
1206 	WR4(sc, FEC_ECR_REG, regval);
1207 
1208 	ifp->if_drv_flags |= IFF_DRV_RUNNING;
1209 
1210        /*
1211 	* Call mii_mediachg() which will call back into ffec_miibus_statchg() to
1212 	* set up the remaining config registers based on the current media.
1213 	*/
1214 	mii_mediachg(sc->mii_softc);
1215 	callout_reset(&sc->ffec_callout, hz, ffec_tick, sc);
1216 
1217 	/*
1218 	 * Tell the hardware that receive buffers are available.  They were made
1219 	 * available in ffec_attach() or ffec_stop().
1220 	 */
1221 	WR4(sc, FEC_RDAR_REG, FEC_RDAR_RDAR);
1222 }
1223 
1224 static void
1225 ffec_init(void *if_softc)
1226 {
1227 	struct ffec_softc *sc = if_softc;
1228 
1229 	FFEC_LOCK(sc);
1230 	ffec_init_locked(sc);
1231 	FFEC_UNLOCK(sc);
1232 }
1233 
1234 static void
1235 ffec_intr(void *arg)
1236 {
1237 	struct ffec_softc *sc;
1238 	uint32_t ier;
1239 
1240 	sc = arg;
1241 
1242 	FFEC_LOCK(sc);
1243 
1244 	ier = RD4(sc, FEC_IER_REG);
1245 
1246 	if (ier & FEC_IER_TXF) {
1247 		WR4(sc, FEC_IER_REG, FEC_IER_TXF);
1248 		ffec_txfinish_locked(sc);
1249 	}
1250 
1251 	if (ier & FEC_IER_RXF) {
1252 		WR4(sc, FEC_IER_REG, FEC_IER_RXF);
1253 		ffec_rxfinish_locked(sc);
1254 	}
1255 
1256 	/*
1257 	 * We actually don't care about most errors, because the hardware copes
1258 	 * with them just fine, discarding the incoming bad frame, or forcing a
1259 	 * bad CRC onto an outgoing bad frame, and counting the errors in the
1260 	 * stats registers.  The one that really matters is EBERR (DMA bus
1261 	 * error) because the hardware automatically clears ECR[ETHEREN] and we
1262 	 * have to restart it here.  It should never happen.
1263 	 */
1264 	if (ier & FEC_IER_EBERR) {
1265 		WR4(sc, FEC_IER_REG, FEC_IER_EBERR);
1266 		device_printf(sc->dev,
1267 		    "Ethernet DMA error, restarting controller.\n");
1268 		ffec_stop_locked(sc);
1269 		ffec_init_locked(sc);
1270 	}
1271 
1272 	FFEC_UNLOCK(sc);
1273 
1274 }
1275 
1276 static int
1277 ffec_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data)
1278 {
1279 	struct ffec_softc *sc;
1280 	struct mii_data *mii;
1281 	struct ifreq *ifr;
1282 	int mask, error;
1283 
1284 	sc = ifp->if_softc;
1285 	ifr = (struct ifreq *)data;
1286 
1287 	error = 0;
1288 	switch (cmd) {
1289 	case SIOCSIFFLAGS:
1290 		FFEC_LOCK(sc);
1291 		if (ifp->if_flags & IFF_UP) {
1292 			if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
1293 				if ((ifp->if_flags ^ sc->if_flags) &
1294 				    (IFF_PROMISC | IFF_ALLMULTI))
1295 					ffec_setup_rxfilter(sc);
1296 			} else {
1297 				if (!sc->is_detaching)
1298 					ffec_init_locked(sc);
1299 			}
1300 		} else {
1301 			if (ifp->if_drv_flags & IFF_DRV_RUNNING)
1302 				ffec_stop_locked(sc);
1303 		}
1304 		sc->if_flags = ifp->if_flags;
1305 		FFEC_UNLOCK(sc);
1306 		break;
1307 
1308 	case SIOCADDMULTI:
1309 	case SIOCDELMULTI:
1310 		if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
1311 			FFEC_LOCK(sc);
1312 			ffec_setup_rxfilter(sc);
1313 			FFEC_UNLOCK(sc);
1314 		}
1315 		break;
1316 
1317 	case SIOCSIFMEDIA:
1318 	case SIOCGIFMEDIA:
1319 		mii = sc->mii_softc;
1320 		error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd);
1321 		break;
1322 
1323 	case SIOCSIFCAP:
1324 		mask = ifp->if_capenable ^ ifr->ifr_reqcap;
1325 		if (mask & IFCAP_VLAN_MTU) {
1326 			/* No work to do except acknowledge the change took. */
1327 			ifp->if_capenable ^= IFCAP_VLAN_MTU;
1328 		}
1329 		break;
1330 
1331 	default:
1332 		error = ether_ioctl(ifp, cmd, data);
1333 		break;
1334 	}
1335 
1336 	return (error);
1337 }
1338 
1339 static int
1340 ffec_detach(device_t dev)
1341 {
1342 	struct ffec_softc *sc;
1343 	bus_dmamap_t map;
1344 	int idx;
1345 
1346 	/*
1347 	 * NB: This function can be called internally to unwind a failure to
1348 	 * attach. Make sure a resource got allocated/created before destroying.
1349 	 */
1350 
1351 	sc = device_get_softc(dev);
1352 
1353 	if (sc->is_attached) {
1354 		FFEC_LOCK(sc);
1355 		sc->is_detaching = true;
1356 		ffec_stop_locked(sc);
1357 		FFEC_UNLOCK(sc);
1358 		callout_drain(&sc->ffec_callout);
1359 		ether_ifdetach(sc->ifp);
1360 	}
1361 
1362 	/* XXX no miibus detach? */
1363 
1364 	/* Clean up RX DMA resources and free mbufs. */
1365 	for (idx = 0; idx < RX_DESC_COUNT; ++idx) {
1366 		if ((map = sc->rxbuf_map[idx].map) != NULL) {
1367 			bus_dmamap_unload(sc->rxbuf_tag, map);
1368 			bus_dmamap_destroy(sc->rxbuf_tag, map);
1369 			m_freem(sc->rxbuf_map[idx].mbuf);
1370 		}
1371 	}
1372 	if (sc->rxbuf_tag != NULL)
1373 		bus_dma_tag_destroy(sc->rxbuf_tag);
1374 	if (sc->rxdesc_map != NULL) {
1375 		bus_dmamap_unload(sc->rxdesc_tag, sc->rxdesc_map);
1376 		bus_dmamap_destroy(sc->rxdesc_tag, sc->rxdesc_map);
1377 	}
1378 	if (sc->rxdesc_tag != NULL)
1379 	bus_dma_tag_destroy(sc->rxdesc_tag);
1380 
1381 	/* Clean up TX DMA resources. */
1382 	for (idx = 0; idx < TX_DESC_COUNT; ++idx) {
1383 		if ((map = sc->txbuf_map[idx].map) != NULL) {
1384 			/* TX maps are already unloaded. */
1385 			bus_dmamap_destroy(sc->txbuf_tag, map);
1386 		}
1387 	}
1388 	if (sc->txbuf_tag != NULL)
1389 		bus_dma_tag_destroy(sc->txbuf_tag);
1390 	if (sc->txdesc_map != NULL) {
1391 		bus_dmamap_unload(sc->txdesc_tag, sc->txdesc_map);
1392 		bus_dmamap_destroy(sc->txdesc_tag, sc->txdesc_map);
1393 	}
1394 	if (sc->txdesc_tag != NULL)
1395 	bus_dma_tag_destroy(sc->txdesc_tag);
1396 
1397 	/* Release bus resources. */
1398 	if (sc->intr_cookie)
1399 		bus_teardown_intr(dev, sc->irq_res, sc->intr_cookie);
1400 
1401 	if (sc->irq_res != NULL)
1402 		bus_release_resource(dev, SYS_RES_IRQ, 0, sc->irq_res);
1403 
1404 	if (sc->mem_res != NULL)
1405 		bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->mem_res);
1406 
1407 	FFEC_LOCK_DESTROY(sc);
1408 	return (0);
1409 }
1410 
1411 static int
1412 ffec_attach(device_t dev)
1413 {
1414 	struct ffec_softc *sc;
1415 	struct ifnet *ifp = NULL;
1416 	struct mbuf *m;
1417 	phandle_t ofw_node;
1418 	int error, rid;
1419 	uint8_t eaddr[ETHER_ADDR_LEN];
1420 	char phy_conn_name[32];
1421 	uint32_t idx, mscr;
1422 
1423 	sc = device_get_softc(dev);
1424 	sc->dev = dev;
1425 
1426 	FFEC_LOCK_INIT(sc);
1427 
1428 	/*
1429 	 * There are differences in the implementation and features of the FEC
1430 	 * hardware on different SoCs, so figure out what type we are.
1431 	 */
1432 	sc->fectype = ofw_bus_search_compatible(dev, compat_data)->ocd_data;
1433 
1434 	/*
1435 	 * We have to be told what kind of electrical connection exists between
1436 	 * the MAC and PHY or we can't operate correctly.
1437 	 */
1438 	if ((ofw_node = ofw_bus_get_node(dev)) == -1) {
1439 		device_printf(dev, "Impossible: Can't find ofw bus node\n");
1440 		error = ENXIO;
1441 		goto out;
1442 	}
1443 	if (OF_searchprop(ofw_node, "phy-mode",
1444 	    phy_conn_name, sizeof(phy_conn_name)) != -1) {
1445 		if (strcasecmp(phy_conn_name, "mii") == 0)
1446 			sc->phy_conn_type = PHY_CONN_MII;
1447 		else if (strcasecmp(phy_conn_name, "rmii") == 0)
1448 			sc->phy_conn_type = PHY_CONN_RMII;
1449 		else if (strcasecmp(phy_conn_name, "rgmii") == 0)
1450 			sc->phy_conn_type = PHY_CONN_RGMII;
1451 	}
1452 	if (sc->phy_conn_type == PHY_CONN_UNKNOWN) {
1453 		device_printf(sc->dev, "No valid 'phy-mode' "
1454 		    "property found in FDT data for device.\n");
1455 		error = ENOATTR;
1456 		goto out;
1457 	}
1458 
1459 	callout_init_mtx(&sc->ffec_callout, &sc->mtx, 0);
1460 
1461 	/* Allocate bus resources for accessing the hardware. */
1462 	rid = 0;
1463 	sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
1464 	    RF_ACTIVE);
1465 	if (sc->mem_res == NULL) {
1466 		device_printf(dev, "could not allocate memory resources.\n");
1467 		error = ENOMEM;
1468 		goto out;
1469 	}
1470 	rid = 0;
1471 	sc->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
1472 	    RF_ACTIVE);
1473 	if (sc->irq_res == NULL) {
1474 		device_printf(dev, "could not allocate interrupt resources.\n");
1475 		error = ENOMEM;
1476 		goto out;
1477 	}
1478 
1479 	/*
1480 	 * Set up TX descriptor ring, descriptors, and dma maps.
1481 	 */
1482 	error = bus_dma_tag_create(
1483 	    bus_get_dma_tag(dev),	/* Parent tag. */
1484 	    FEC_DESC_RING_ALIGN, 0,	/* alignment, boundary */
1485 	    BUS_SPACE_MAXADDR_32BIT,	/* lowaddr */
1486 	    BUS_SPACE_MAXADDR,		/* highaddr */
1487 	    NULL, NULL,			/* filter, filterarg */
1488 	    TX_DESC_SIZE, 1, 		/* maxsize, nsegments */
1489 	    TX_DESC_SIZE,		/* maxsegsize */
1490 	    0,				/* flags */
1491 	    NULL, NULL,			/* lockfunc, lockarg */
1492 	    &sc->txdesc_tag);
1493 	if (error != 0) {
1494 		device_printf(sc->dev,
1495 		    "could not create TX ring DMA tag.\n");
1496 		goto out;
1497 	}
1498 
1499 	error = bus_dmamem_alloc(sc->txdesc_tag, (void**)&sc->txdesc_ring,
1500 	    BUS_DMA_COHERENT | BUS_DMA_WAITOK | BUS_DMA_ZERO, &sc->txdesc_map);
1501 	if (error != 0) {
1502 		device_printf(sc->dev,
1503 		    "could not allocate TX descriptor ring.\n");
1504 		goto out;
1505 	}
1506 
1507 	error = bus_dmamap_load(sc->txdesc_tag, sc->txdesc_map, sc->txdesc_ring,
1508 	    TX_DESC_SIZE, ffec_get1paddr, &sc->txdesc_ring_paddr, 0);
1509 	if (error != 0) {
1510 		device_printf(sc->dev,
1511 		    "could not load TX descriptor ring map.\n");
1512 		goto out;
1513 	}
1514 
1515 	error = bus_dma_tag_create(
1516 	    bus_get_dma_tag(dev),	/* Parent tag. */
1517 	    FEC_TXBUF_ALIGN, 0,		/* alignment, boundary */
1518 	    BUS_SPACE_MAXADDR_32BIT,	/* lowaddr */
1519 	    BUS_SPACE_MAXADDR,		/* highaddr */
1520 	    NULL, NULL,			/* filter, filterarg */
1521 	    MCLBYTES, 1, 		/* maxsize, nsegments */
1522 	    MCLBYTES,			/* maxsegsize */
1523 	    0,				/* flags */
1524 	    NULL, NULL,			/* lockfunc, lockarg */
1525 	    &sc->txbuf_tag);
1526 	if (error != 0) {
1527 		device_printf(sc->dev,
1528 		    "could not create TX ring DMA tag.\n");
1529 		goto out;
1530 	}
1531 
1532 	for (idx = 0; idx < TX_DESC_COUNT; ++idx) {
1533 		error = bus_dmamap_create(sc->txbuf_tag, 0,
1534 		    &sc->txbuf_map[idx].map);
1535 		if (error != 0) {
1536 			device_printf(sc->dev,
1537 			    "could not create TX buffer DMA map.\n");
1538 			goto out;
1539 		}
1540 		ffec_setup_txdesc(sc, idx, 0, 0);
1541 	}
1542 
1543 	/*
1544 	 * Set up RX descriptor ring, descriptors, dma maps, and mbufs.
1545 	 */
1546 	error = bus_dma_tag_create(
1547 	    bus_get_dma_tag(dev),	/* Parent tag. */
1548 	    FEC_DESC_RING_ALIGN, 0,	/* alignment, boundary */
1549 	    BUS_SPACE_MAXADDR_32BIT,	/* lowaddr */
1550 	    BUS_SPACE_MAXADDR,		/* highaddr */
1551 	    NULL, NULL,			/* filter, filterarg */
1552 	    RX_DESC_SIZE, 1, 		/* maxsize, nsegments */
1553 	    RX_DESC_SIZE,		/* maxsegsize */
1554 	    0,				/* flags */
1555 	    NULL, NULL,			/* lockfunc, lockarg */
1556 	    &sc->rxdesc_tag);
1557 	if (error != 0) {
1558 		device_printf(sc->dev,
1559 		    "could not create RX ring DMA tag.\n");
1560 		goto out;
1561 	}
1562 
1563 	error = bus_dmamem_alloc(sc->rxdesc_tag, (void **)&sc->rxdesc_ring,
1564 	    BUS_DMA_COHERENT | BUS_DMA_WAITOK | BUS_DMA_ZERO, &sc->rxdesc_map);
1565 	if (error != 0) {
1566 		device_printf(sc->dev,
1567 		    "could not allocate RX descriptor ring.\n");
1568 		goto out;
1569 	}
1570 
1571 	error = bus_dmamap_load(sc->rxdesc_tag, sc->rxdesc_map, sc->rxdesc_ring,
1572 	    RX_DESC_SIZE, ffec_get1paddr, &sc->rxdesc_ring_paddr, 0);
1573 	if (error != 0) {
1574 		device_printf(sc->dev,
1575 		    "could not load RX descriptor ring map.\n");
1576 		goto out;
1577 	}
1578 
1579 	error = bus_dma_tag_create(
1580 	    bus_get_dma_tag(dev),	/* Parent tag. */
1581 	    1, 0,			/* alignment, boundary */
1582 	    BUS_SPACE_MAXADDR_32BIT,	/* lowaddr */
1583 	    BUS_SPACE_MAXADDR,		/* highaddr */
1584 	    NULL, NULL,			/* filter, filterarg */
1585 	    MCLBYTES, 1, 		/* maxsize, nsegments */
1586 	    MCLBYTES,			/* maxsegsize */
1587 	    0,				/* flags */
1588 	    NULL, NULL,			/* lockfunc, lockarg */
1589 	    &sc->rxbuf_tag);
1590 	if (error != 0) {
1591 		device_printf(sc->dev,
1592 		    "could not create RX buf DMA tag.\n");
1593 		goto out;
1594 	}
1595 
1596 	for (idx = 0; idx < RX_DESC_COUNT; ++idx) {
1597 		error = bus_dmamap_create(sc->rxbuf_tag, 0,
1598 		    &sc->rxbuf_map[idx].map);
1599 		if (error != 0) {
1600 			device_printf(sc->dev,
1601 			    "could not create RX buffer DMA map.\n");
1602 			goto out;
1603 		}
1604 		if ((m = ffec_alloc_mbufcl(sc)) == NULL) {
1605 			device_printf(dev, "Could not alloc mbuf\n");
1606 			error = ENOMEM;
1607 			goto out;
1608 		}
1609 		if ((error = ffec_setup_rxbuf(sc, idx, m)) != 0) {
1610 			device_printf(sc->dev,
1611 			    "could not create new RX buffer.\n");
1612 			goto out;
1613 		}
1614 	}
1615 
1616 	/* Try to get the MAC address from the hardware before resetting it. */
1617 	ffec_get_hwaddr(sc, eaddr);
1618 
1619 	/* Reset the hardware.  Disables all interrupts. */
1620 	WR4(sc, FEC_ECR_REG, FEC_ECR_RESET);
1621 
1622 	/* Setup interrupt handler. */
1623 	error = bus_setup_intr(dev, sc->irq_res, INTR_TYPE_NET | INTR_MPSAFE,
1624 	    NULL, ffec_intr, sc, &sc->intr_cookie);
1625 	if (error != 0) {
1626 		device_printf(dev, "could not setup interrupt handler.\n");
1627 		goto out;
1628 	}
1629 
1630 	/*
1631 	 * Set up the PHY control register.
1632 	 *
1633 	 * Speed formula for ENET is md_clock = mac_clock / ((N + 1) * 2).
1634 	 * Speed formula for FEC is  md_clock = mac_clock / (N * 2)
1635 	 *
1636 	 * XXX - Revisit this...
1637 	 *
1638 	 * For a Wandboard imx6 (ENET) I was originally using 4, but the uboot
1639 	 * code uses 10.  Both values seem to work, but I suspect many modern
1640 	 * PHY parts can do mdio at speeds far above the standard 2.5 MHz.
1641 	 *
1642 	 * Different imx manuals use confusingly different terminology (things
1643 	 * like "system clock" and "internal module clock") with examples that
1644 	 * use frequencies that have nothing to do with ethernet, giving the
1645 	 * vague impression that maybe the clock in question is the periphclock
1646 	 * or something.  In fact, on an imx53 development board (FEC),
1647 	 * measuring the mdio clock at the pin on the PHY and playing with
1648 	 * various divisors showed that the root speed was 66 MHz (clk_ipg_root
1649 	 * aka periphclock) and 13 was the right divisor.
1650 	 *
1651 	 * All in all, it seems likely that 13 is a safe divisor for now,
1652 	 * because if we really do need to base it on the peripheral clock
1653 	 * speed, then we need a platform-independant get-clock-freq API.
1654 	 */
1655 	mscr = 13 << FEC_MSCR_MII_SPEED_SHIFT;
1656 	if (OF_hasprop(ofw_node, "phy-disable-preamble")) {
1657 		mscr |= FEC_MSCR_DIS_PRE;
1658 		if (bootverbose)
1659 			device_printf(dev, "PHY preamble disabled\n");
1660 	}
1661 	WR4(sc, FEC_MSCR_REG, mscr);
1662 
1663 	/* Set up the ethernet interface. */
1664 	sc->ifp = ifp = if_alloc(IFT_ETHER);
1665 
1666 	ifp->if_softc = sc;
1667 	if_initname(ifp, device_get_name(dev), device_get_unit(dev));
1668 	ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1669 	ifp->if_capabilities = IFCAP_VLAN_MTU;
1670 	ifp->if_capenable = ifp->if_capabilities;
1671 	ifp->if_start = ffec_txstart;
1672 	ifp->if_ioctl = ffec_ioctl;
1673 	ifp->if_init = ffec_init;
1674 	IFQ_SET_MAXLEN(&ifp->if_snd, TX_DESC_COUNT - 1);
1675 	ifp->if_snd.ifq_drv_maxlen = TX_DESC_COUNT - 1;
1676 	IFQ_SET_READY(&ifp->if_snd);
1677 	ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
1678 
1679 #if 0 /* XXX The hardware keeps stats we could use for these. */
1680 	ifp->if_linkmib = &sc->mibdata;
1681 	ifp->if_linkmiblen = sizeof(sc->mibdata);
1682 #endif
1683 
1684 	/* Set up the miigasket hardware (if any). */
1685 	ffec_miigasket_setup(sc);
1686 
1687 	/* Attach the mii driver. */
1688 	error = mii_attach(dev, &sc->miibus, ifp, ffec_media_change,
1689 	    ffec_media_status, BMSR_DEFCAPMASK, MII_PHY_ANY, MII_OFFSET_ANY, 0);
1690 	if (error != 0) {
1691 		device_printf(dev, "PHY attach failed\n");
1692 		goto out;
1693 	}
1694 	sc->mii_softc = device_get_softc(sc->miibus);
1695 
1696 	/* All ready to run, attach the ethernet interface. */
1697 	ether_ifattach(ifp, eaddr);
1698 	sc->is_attached = true;
1699 
1700 	error = 0;
1701 out:
1702 
1703 	if (error != 0)
1704 		ffec_detach(dev);
1705 
1706 	return (error);
1707 }
1708 
1709 static int
1710 ffec_probe(device_t dev)
1711 {
1712 	uintptr_t fectype;
1713 
1714 	fectype = ofw_bus_search_compatible(dev, compat_data)->ocd_data;
1715 	if (fectype == FECTYPE_NONE)
1716 		return (ENXIO);
1717 
1718 	device_set_desc(dev, (fectype & FECFLAG_GBE) ?
1719 	    "Freescale Gigabit Ethernet Controller" :
1720 	    "Freescale Fast Ethernet Controller");
1721 
1722 	return (BUS_PROBE_DEFAULT);
1723 }
1724 
1725 
1726 static device_method_t ffec_methods[] = {
1727 	/* Device interface. */
1728 	DEVMETHOD(device_probe,		ffec_probe),
1729 	DEVMETHOD(device_attach,	ffec_attach),
1730 	DEVMETHOD(device_detach,	ffec_detach),
1731 
1732 /*
1733 	DEVMETHOD(device_shutdown,	ffec_shutdown),
1734 	DEVMETHOD(device_suspend,	ffec_suspend),
1735 	DEVMETHOD(device_resume,	ffec_resume),
1736 */
1737 
1738 	/* MII interface. */
1739 	DEVMETHOD(miibus_readreg,	ffec_miibus_readreg),
1740 	DEVMETHOD(miibus_writereg,	ffec_miibus_writereg),
1741 	DEVMETHOD(miibus_statchg,	ffec_miibus_statchg),
1742 
1743 	DEVMETHOD_END
1744 };
1745 
1746 static driver_t ffec_driver = {
1747 	"ffec",
1748 	ffec_methods,
1749 	sizeof(struct ffec_softc)
1750 };
1751 
1752 static devclass_t ffec_devclass;
1753 
1754 DRIVER_MODULE(ffec, simplebus, ffec_driver, ffec_devclass, 0, 0);
1755 DRIVER_MODULE(miibus, ffec, miibus_driver, miibus_devclass, 0, 0);
1756 
1757 MODULE_DEPEND(ffec, ether, 1, 1, 1);
1758 MODULE_DEPEND(ffec, miibus, 1, 1, 1);
1759