1 /*- 2 * Copyright (c) 2013 Ian Lepore <ian@freebsd.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 */ 27 28 #include <sys/cdefs.h> 29 __FBSDID("$FreeBSD$"); 30 31 /* 32 * Driver for Freescale Fast Ethernet Controller, found on imx-series SoCs among 33 * others. Also works for the ENET Gigibit controller found on imx6 and imx28, 34 * but the driver doesn't currently use any of the ENET advanced features other 35 * than enabling gigabit. 36 * 37 * The interface name 'fec' is already taken by netgraph's Fast Etherchannel 38 * (netgraph/ng_fec.c), so we use 'ffec'. 39 * 40 * Requires an FDT entry with at least these properties: 41 * fec: ethernet@02188000 { 42 * compatible = "fsl,imxNN-fec"; 43 * reg = <0x02188000 0x4000>; 44 * interrupts = <150 151>; 45 * phy-mode = "rgmii"; 46 * phy-disable-preamble; // optional 47 * }; 48 * The second interrupt number is for IEEE-1588, and is not currently used; it 49 * need not be present. phy-mode must be one of: "mii", "rmii", "rgmii". 50 * There is also an optional property, phy-disable-preamble, which if present 51 * will disable the preamble bits, cutting the size of each mdio transaction 52 * (and thus the busy-wait time) in half. 53 */ 54 55 #include <sys/param.h> 56 #include <sys/systm.h> 57 #include <sys/bus.h> 58 #include <sys/endian.h> 59 #include <sys/kernel.h> 60 #include <sys/lock.h> 61 #include <sys/malloc.h> 62 #include <sys/mbuf.h> 63 #include <sys/module.h> 64 #include <sys/mutex.h> 65 #include <sys/rman.h> 66 #include <sys/socket.h> 67 #include <sys/sockio.h> 68 #include <sys/sysctl.h> 69 70 #include <machine/bus.h> 71 72 #include <net/bpf.h> 73 #include <net/if.h> 74 #include <net/ethernet.h> 75 #include <net/if_dl.h> 76 #include <net/if_media.h> 77 #include <net/if_types.h> 78 #include <net/if_var.h> 79 #include <net/if_vlan_var.h> 80 81 #include <dev/ffec/if_ffecreg.h> 82 #include <dev/ofw/ofw_bus.h> 83 #include <dev/ofw/ofw_bus_subr.h> 84 #include <dev/mii/mii.h> 85 #include <dev/mii/miivar.h> 86 #include "miibus_if.h" 87 88 /* 89 * There are small differences in the hardware on various SoCs. Not every SoC 90 * we support has its own FECTYPE; most work as GENERIC and only the ones that 91 * need different handling get their own entry. In addition to the types in 92 * this list, there are some flags below that can be ORed into the upper bits. 93 */ 94 enum { 95 FECTYPE_NONE, 96 FECTYPE_GENERIC, 97 FECTYPE_IMX53, 98 FECTYPE_IMX6, 99 FECTYPE_MVF, 100 }; 101 102 /* 103 * Flags that describe general differences between the FEC hardware in various 104 * SoCs. These are ORed into the FECTYPE enum values. 105 */ 106 #define FECTYPE_MASK 0x0000ffff 107 #define FECFLAG_GBE (0x0001 << 16) 108 109 /* 110 * Table of supported FDT compat strings and their associated FECTYPE values. 111 */ 112 static struct ofw_compat_data compat_data[] = { 113 {"fsl,imx51-fec", FECTYPE_GENERIC}, 114 {"fsl,imx53-fec", FECTYPE_IMX53}, 115 {"fsl,imx6q-fec", FECTYPE_IMX6 | FECFLAG_GBE}, 116 {"fsl,mvf600-fec", FECTYPE_MVF}, 117 {"fsl,mvf-fec", FECTYPE_MVF}, 118 {NULL, FECTYPE_NONE}, 119 }; 120 121 /* 122 * Driver data and defines. 123 */ 124 #define RX_DESC_COUNT 64 125 #define RX_DESC_SIZE (sizeof(struct ffec_hwdesc) * RX_DESC_COUNT) 126 #define TX_DESC_COUNT 64 127 #define TX_DESC_SIZE (sizeof(struct ffec_hwdesc) * TX_DESC_COUNT) 128 129 #define WATCHDOG_TIMEOUT_SECS 5 130 #define STATS_HARVEST_INTERVAL 3 131 132 struct ffec_bufmap { 133 struct mbuf *mbuf; 134 bus_dmamap_t map; 135 }; 136 137 enum { 138 PHY_CONN_UNKNOWN, 139 PHY_CONN_MII, 140 PHY_CONN_RMII, 141 PHY_CONN_RGMII 142 }; 143 144 struct ffec_softc { 145 device_t dev; 146 device_t miibus; 147 struct mii_data * mii_softc; 148 struct ifnet *ifp; 149 int if_flags; 150 struct mtx mtx; 151 struct resource *irq_res; 152 struct resource *mem_res; 153 void * intr_cookie; 154 struct callout ffec_callout; 155 uint8_t phy_conn_type; 156 uint8_t fectype; 157 boolean_t link_is_up; 158 boolean_t is_attached; 159 boolean_t is_detaching; 160 int tx_watchdog_count; 161 int stats_harvest_count; 162 163 bus_dma_tag_t rxdesc_tag; 164 bus_dmamap_t rxdesc_map; 165 struct ffec_hwdesc *rxdesc_ring; 166 bus_addr_t rxdesc_ring_paddr; 167 bus_dma_tag_t rxbuf_tag; 168 struct ffec_bufmap rxbuf_map[RX_DESC_COUNT]; 169 uint32_t rx_idx; 170 171 bus_dma_tag_t txdesc_tag; 172 bus_dmamap_t txdesc_map; 173 struct ffec_hwdesc *txdesc_ring; 174 bus_addr_t txdesc_ring_paddr; 175 bus_dma_tag_t txbuf_tag; 176 struct ffec_bufmap txbuf_map[RX_DESC_COUNT]; 177 uint32_t tx_idx_head; 178 uint32_t tx_idx_tail; 179 int txcount; 180 }; 181 182 #define FFEC_LOCK(sc) mtx_lock(&(sc)->mtx) 183 #define FFEC_UNLOCK(sc) mtx_unlock(&(sc)->mtx) 184 #define FFEC_LOCK_INIT(sc) mtx_init(&(sc)->mtx, \ 185 device_get_nameunit((sc)->dev), MTX_NETWORK_LOCK, MTX_DEF) 186 #define FFEC_LOCK_DESTROY(sc) mtx_destroy(&(sc)->mtx); 187 #define FFEC_ASSERT_LOCKED(sc) mtx_assert(&(sc)->mtx, MA_OWNED); 188 #define FFEC_ASSERT_UNLOCKED(sc) mtx_assert(&(sc)->mtx, MA_NOTOWNED); 189 190 static void ffec_init_locked(struct ffec_softc *sc); 191 static void ffec_stop_locked(struct ffec_softc *sc); 192 static void ffec_txstart_locked(struct ffec_softc *sc); 193 static void ffec_txfinish_locked(struct ffec_softc *sc); 194 195 static inline uint16_t 196 RD2(struct ffec_softc *sc, bus_size_t off) 197 { 198 199 return (bus_read_2(sc->mem_res, off)); 200 } 201 202 static inline void 203 WR2(struct ffec_softc *sc, bus_size_t off, uint16_t val) 204 { 205 206 bus_write_2(sc->mem_res, off, val); 207 } 208 209 static inline uint32_t 210 RD4(struct ffec_softc *sc, bus_size_t off) 211 { 212 213 return (bus_read_4(sc->mem_res, off)); 214 } 215 216 static inline void 217 WR4(struct ffec_softc *sc, bus_size_t off, uint32_t val) 218 { 219 220 bus_write_4(sc->mem_res, off, val); 221 } 222 223 static inline uint32_t 224 next_rxidx(struct ffec_softc *sc, uint32_t curidx) 225 { 226 227 return ((curidx == RX_DESC_COUNT - 1) ? 0 : curidx + 1); 228 } 229 230 static inline uint32_t 231 next_txidx(struct ffec_softc *sc, uint32_t curidx) 232 { 233 234 return ((curidx == TX_DESC_COUNT - 1) ? 0 : curidx + 1); 235 } 236 237 static void 238 ffec_get1paddr(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 239 { 240 241 if (error != 0) 242 return; 243 *(bus_addr_t *)arg = segs[0].ds_addr; 244 } 245 246 static void 247 ffec_miigasket_setup(struct ffec_softc *sc) 248 { 249 uint32_t ifmode; 250 251 /* 252 * We only need the gasket for MII and RMII connections on certain SoCs. 253 */ 254 255 switch (sc->fectype & FECTYPE_MASK) 256 { 257 case FECTYPE_IMX53: 258 break; 259 default: 260 return; 261 } 262 263 switch (sc->phy_conn_type) 264 { 265 case PHY_CONN_MII: 266 ifmode = 0; 267 break; 268 case PHY_CONN_RMII: 269 ifmode = FEC_MIIGSK_CFGR_IF_MODE_RMII; 270 break; 271 default: 272 return; 273 } 274 275 /* 276 * Disable the gasket, configure for either MII or RMII, then enable. 277 */ 278 279 WR2(sc, FEC_MIIGSK_ENR, 0); 280 while (RD2(sc, FEC_MIIGSK_ENR) & FEC_MIIGSK_ENR_READY) 281 continue; 282 283 WR2(sc, FEC_MIIGSK_CFGR, ifmode); 284 285 WR2(sc, FEC_MIIGSK_ENR, FEC_MIIGSK_ENR_EN); 286 while (!(RD2(sc, FEC_MIIGSK_ENR) & FEC_MIIGSK_ENR_READY)) 287 continue; 288 } 289 290 static boolean_t 291 ffec_miibus_iowait(struct ffec_softc *sc) 292 { 293 uint32_t timeout; 294 295 for (timeout = 10000; timeout != 0; --timeout) 296 if (RD4(sc, FEC_IER_REG) & FEC_IER_MII) 297 return (true); 298 299 return (false); 300 } 301 302 static int 303 ffec_miibus_readreg(device_t dev, int phy, int reg) 304 { 305 struct ffec_softc *sc; 306 int val; 307 308 sc = device_get_softc(dev); 309 310 WR4(sc, FEC_IER_REG, FEC_IER_MII); 311 312 WR4(sc, FEC_MMFR_REG, FEC_MMFR_OP_READ | 313 FEC_MMFR_ST_VALUE | FEC_MMFR_TA_VALUE | 314 ((phy << FEC_MMFR_PA_SHIFT) & FEC_MMFR_PA_MASK) | 315 ((reg << FEC_MMFR_RA_SHIFT) & FEC_MMFR_RA_MASK)); 316 317 if (!ffec_miibus_iowait(sc)) { 318 device_printf(dev, "timeout waiting for mii read\n"); 319 return (-1); /* All-ones is a symptom of bad mdio. */ 320 } 321 322 val = RD4(sc, FEC_MMFR_REG) & FEC_MMFR_DATA_MASK; 323 324 return (val); 325 } 326 327 static int 328 ffec_miibus_writereg(device_t dev, int phy, int reg, int val) 329 { 330 struct ffec_softc *sc; 331 332 sc = device_get_softc(dev); 333 334 WR4(sc, FEC_IER_REG, FEC_IER_MII); 335 336 WR4(sc, FEC_MMFR_REG, FEC_MMFR_OP_WRITE | 337 FEC_MMFR_ST_VALUE | FEC_MMFR_TA_VALUE | 338 ((phy << FEC_MMFR_PA_SHIFT) & FEC_MMFR_PA_MASK) | 339 ((reg << FEC_MMFR_RA_SHIFT) & FEC_MMFR_RA_MASK) | 340 (val & FEC_MMFR_DATA_MASK)); 341 342 if (!ffec_miibus_iowait(sc)) { 343 device_printf(dev, "timeout waiting for mii write\n"); 344 return (-1); 345 } 346 347 return (0); 348 } 349 350 static void 351 ffec_miibus_statchg(device_t dev) 352 { 353 struct ffec_softc *sc; 354 struct mii_data *mii; 355 uint32_t ecr, rcr, tcr; 356 357 /* 358 * Called by the MII bus driver when the PHY establishes link to set the 359 * MAC interface registers. 360 */ 361 362 sc = device_get_softc(dev); 363 364 FFEC_ASSERT_LOCKED(sc); 365 366 mii = sc->mii_softc; 367 368 if (mii->mii_media_status & IFM_ACTIVE) 369 sc->link_is_up = true; 370 else 371 sc->link_is_up = false; 372 373 ecr = RD4(sc, FEC_ECR_REG) & ~FEC_ECR_SPEED; 374 rcr = RD4(sc, FEC_RCR_REG) & ~(FEC_RCR_RMII_10T | FEC_RCR_RMII_MODE | 375 FEC_RCR_RGMII_EN | FEC_RCR_DRT | FEC_RCR_FCE); 376 tcr = RD4(sc, FEC_TCR_REG) & ~FEC_TCR_FDEN; 377 378 rcr |= FEC_RCR_MII_MODE; /* Must always be on even for R[G]MII. */ 379 switch (sc->phy_conn_type) { 380 case PHY_CONN_MII: 381 break; 382 case PHY_CONN_RMII: 383 rcr |= FEC_RCR_RMII_MODE; 384 break; 385 case PHY_CONN_RGMII: 386 rcr |= FEC_RCR_RGMII_EN; 387 break; 388 } 389 390 switch (IFM_SUBTYPE(mii->mii_media_active)) { 391 case IFM_1000_T: 392 case IFM_1000_SX: 393 ecr |= FEC_ECR_SPEED; 394 break; 395 case IFM_100_TX: 396 /* Not-FEC_ECR_SPEED + not-FEC_RCR_RMII_10T means 100TX */ 397 break; 398 case IFM_10_T: 399 rcr |= FEC_RCR_RMII_10T; 400 break; 401 case IFM_NONE: 402 sc->link_is_up = false; 403 return; 404 default: 405 sc->link_is_up = false; 406 device_printf(dev, "Unsupported media %u\n", 407 IFM_SUBTYPE(mii->mii_media_active)); 408 return; 409 } 410 411 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) 412 tcr |= FEC_TCR_FDEN; 413 else 414 rcr |= FEC_RCR_DRT; 415 416 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FLOW) != 0) 417 rcr |= FEC_RCR_FCE; 418 419 WR4(sc, FEC_RCR_REG, rcr); 420 WR4(sc, FEC_TCR_REG, tcr); 421 WR4(sc, FEC_ECR_REG, ecr); 422 } 423 424 static void 425 ffec_media_status(struct ifnet * ifp, struct ifmediareq *ifmr) 426 { 427 struct ffec_softc *sc; 428 struct mii_data *mii; 429 430 431 sc = ifp->if_softc; 432 mii = sc->mii_softc; 433 FFEC_LOCK(sc); 434 mii_pollstat(mii); 435 ifmr->ifm_active = mii->mii_media_active; 436 ifmr->ifm_status = mii->mii_media_status; 437 FFEC_UNLOCK(sc); 438 } 439 440 static int 441 ffec_media_change_locked(struct ffec_softc *sc) 442 { 443 444 return (mii_mediachg(sc->mii_softc)); 445 } 446 447 static int 448 ffec_media_change(struct ifnet * ifp) 449 { 450 struct ffec_softc *sc; 451 int error; 452 453 sc = ifp->if_softc; 454 455 FFEC_LOCK(sc); 456 error = ffec_media_change_locked(sc); 457 FFEC_UNLOCK(sc); 458 return (error); 459 } 460 461 static void ffec_clear_stats(struct ffec_softc *sc) 462 { 463 464 WR4(sc, FEC_RMON_R_PACKETS, 0); 465 WR4(sc, FEC_RMON_R_MC_PKT, 0); 466 WR4(sc, FEC_RMON_R_CRC_ALIGN, 0); 467 WR4(sc, FEC_RMON_R_UNDERSIZE, 0); 468 WR4(sc, FEC_RMON_R_OVERSIZE, 0); 469 WR4(sc, FEC_RMON_R_FRAG, 0); 470 WR4(sc, FEC_RMON_R_JAB, 0); 471 WR4(sc, FEC_RMON_T_PACKETS, 0); 472 WR4(sc, FEC_RMON_T_MC_PKT, 0); 473 WR4(sc, FEC_RMON_T_CRC_ALIGN, 0); 474 WR4(sc, FEC_RMON_T_UNDERSIZE, 0); 475 WR4(sc, FEC_RMON_T_OVERSIZE , 0); 476 WR4(sc, FEC_RMON_T_FRAG, 0); 477 WR4(sc, FEC_RMON_T_JAB, 0); 478 WR4(sc, FEC_RMON_T_COL, 0); 479 } 480 481 static void 482 ffec_harvest_stats(struct ffec_softc *sc) 483 { 484 struct ifnet *ifp; 485 486 /* We don't need to harvest too often. */ 487 if (++sc->stats_harvest_count < STATS_HARVEST_INTERVAL) 488 return; 489 490 /* 491 * Try to avoid harvesting unless the IDLE flag is on, but if it has 492 * been too long just go ahead and do it anyway, the worst that'll 493 * happen is we'll lose a packet count or two as we clear at the end. 494 */ 495 if (sc->stats_harvest_count < (2 * STATS_HARVEST_INTERVAL) && 496 ((RD4(sc, FEC_MIBC_REG) & FEC_MIBC_IDLE) == 0)) 497 return; 498 499 sc->stats_harvest_count = 0; 500 ifp = sc->ifp; 501 502 ifp->if_ipackets += RD4(sc, FEC_RMON_R_PACKETS); 503 ifp->if_imcasts += RD4(sc, FEC_RMON_R_MC_PKT); 504 ifp->if_ierrors += RD4(sc, FEC_RMON_R_CRC_ALIGN); 505 ifp->if_ierrors += RD4(sc, FEC_RMON_R_UNDERSIZE); 506 ifp->if_ierrors += RD4(sc, FEC_RMON_R_OVERSIZE); 507 ifp->if_ierrors += RD4(sc, FEC_RMON_R_FRAG); 508 ifp->if_ierrors += RD4(sc, FEC_RMON_R_JAB); 509 510 ifp->if_opackets += RD4(sc, FEC_RMON_T_PACKETS); 511 ifp->if_omcasts += RD4(sc, FEC_RMON_T_MC_PKT); 512 ifp->if_oerrors += RD4(sc, FEC_RMON_T_CRC_ALIGN); 513 ifp->if_oerrors += RD4(sc, FEC_RMON_T_UNDERSIZE); 514 ifp->if_oerrors += RD4(sc, FEC_RMON_T_OVERSIZE ); 515 ifp->if_oerrors += RD4(sc, FEC_RMON_T_FRAG); 516 ifp->if_oerrors += RD4(sc, FEC_RMON_T_JAB); 517 518 ifp->if_collisions += RD4(sc, FEC_RMON_T_COL); 519 520 ffec_clear_stats(sc); 521 } 522 523 static void 524 ffec_tick(void *arg) 525 { 526 struct ffec_softc *sc; 527 struct ifnet *ifp; 528 int link_was_up; 529 530 sc = arg; 531 532 FFEC_ASSERT_LOCKED(sc); 533 534 ifp = sc->ifp; 535 536 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) 537 return; 538 539 /* 540 * Typical tx watchdog. If this fires it indicates that we enqueued 541 * packets for output and never got a txdone interrupt for them. Maybe 542 * it's a missed interrupt somehow, just pretend we got one. 543 */ 544 if (sc->tx_watchdog_count > 0) { 545 if (--sc->tx_watchdog_count == 0) { 546 ffec_txfinish_locked(sc); 547 } 548 } 549 550 /* Gather stats from hardware counters. */ 551 ffec_harvest_stats(sc); 552 553 /* Check the media status. */ 554 link_was_up = sc->link_is_up; 555 mii_tick(sc->mii_softc); 556 if (sc->link_is_up && !link_was_up) 557 ffec_txstart_locked(sc); 558 559 /* Schedule another check one second from now. */ 560 callout_reset(&sc->ffec_callout, hz, ffec_tick, sc); 561 } 562 563 inline static uint32_t 564 ffec_setup_txdesc(struct ffec_softc *sc, int idx, bus_addr_t paddr, 565 uint32_t len) 566 { 567 uint32_t nidx; 568 uint32_t flags; 569 570 nidx = next_txidx(sc, idx); 571 572 /* Addr/len 0 means we're clearing the descriptor after xmit done. */ 573 if (paddr == 0 || len == 0) { 574 flags = 0; 575 --sc->txcount; 576 } else { 577 flags = FEC_TXDESC_READY | FEC_TXDESC_L | FEC_TXDESC_TC; 578 ++sc->txcount; 579 } 580 if (nidx == 0) 581 flags |= FEC_TXDESC_WRAP; 582 583 /* 584 * The hardware requires 32-bit physical addresses. We set up the dma 585 * tag to indicate that, so the cast to uint32_t should never lose 586 * significant bits. 587 */ 588 sc->txdesc_ring[idx].buf_paddr = (uint32_t)paddr; 589 sc->txdesc_ring[idx].flags_len = flags | len; /* Must be set last! */ 590 591 return (nidx); 592 } 593 594 static int 595 ffec_setup_txbuf(struct ffec_softc *sc, int idx, struct mbuf **mp) 596 { 597 struct mbuf * m; 598 int error, nsegs; 599 struct bus_dma_segment seg; 600 601 if ((m = m_defrag(*mp, M_NOWAIT)) == NULL) 602 return (ENOMEM); 603 *mp = m; 604 605 error = bus_dmamap_load_mbuf_sg(sc->txbuf_tag, sc->txbuf_map[idx].map, 606 m, &seg, &nsegs, 0); 607 if (error != 0) { 608 return (ENOMEM); 609 } 610 bus_dmamap_sync(sc->txbuf_tag, sc->txbuf_map[idx].map, 611 BUS_DMASYNC_PREWRITE); 612 613 sc->txbuf_map[idx].mbuf = m; 614 ffec_setup_txdesc(sc, idx, seg.ds_addr, seg.ds_len); 615 616 return (0); 617 618 } 619 620 static void 621 ffec_txstart_locked(struct ffec_softc *sc) 622 { 623 struct ifnet *ifp; 624 struct mbuf *m; 625 int enqueued; 626 627 FFEC_ASSERT_LOCKED(sc); 628 629 if (!sc->link_is_up) 630 return; 631 632 ifp = sc->ifp; 633 634 if (ifp->if_drv_flags & IFF_DRV_OACTIVE) 635 return; 636 637 enqueued = 0; 638 639 for (;;) { 640 if (sc->txcount == (TX_DESC_COUNT-1)) { 641 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 642 break; 643 } 644 IFQ_DRV_DEQUEUE(&ifp->if_snd, m); 645 if (m == NULL) 646 break; 647 if (ffec_setup_txbuf(sc, sc->tx_idx_head, &m) != 0) { 648 IFQ_DRV_PREPEND(&ifp->if_snd, m); 649 break; 650 } 651 BPF_MTAP(ifp, m); 652 sc->tx_idx_head = next_txidx(sc, sc->tx_idx_head); 653 ++enqueued; 654 } 655 656 if (enqueued != 0) { 657 WR4(sc, FEC_TDAR_REG, FEC_TDAR_TDAR); 658 sc->tx_watchdog_count = WATCHDOG_TIMEOUT_SECS; 659 } 660 } 661 662 static void 663 ffec_txstart(struct ifnet *ifp) 664 { 665 struct ffec_softc *sc = ifp->if_softc; 666 667 FFEC_LOCK(sc); 668 ffec_txstart_locked(sc); 669 FFEC_UNLOCK(sc); 670 } 671 672 static void 673 ffec_txfinish_locked(struct ffec_softc *sc) 674 { 675 struct ifnet *ifp; 676 struct ffec_hwdesc *desc; 677 struct ffec_bufmap *bmap; 678 boolean_t retired_buffer; 679 680 FFEC_ASSERT_LOCKED(sc); 681 682 ifp = sc->ifp; 683 retired_buffer = false; 684 while (sc->tx_idx_tail != sc->tx_idx_head) { 685 desc = &sc->txdesc_ring[sc->tx_idx_tail]; 686 if (desc->flags_len & FEC_TXDESC_READY) 687 break; 688 retired_buffer = true; 689 bmap = &sc->txbuf_map[sc->tx_idx_tail]; 690 bus_dmamap_sync(sc->txbuf_tag, bmap->map, 691 BUS_DMASYNC_POSTWRITE); 692 bus_dmamap_unload(sc->txbuf_tag, bmap->map); 693 m_freem(bmap->mbuf); 694 bmap->mbuf = NULL; 695 ffec_setup_txdesc(sc, sc->tx_idx_tail, 0, 0); 696 sc->tx_idx_tail = next_txidx(sc, sc->tx_idx_tail); 697 } 698 699 /* 700 * If we retired any buffers, there will be open tx slots available in 701 * the descriptor ring, go try to start some new output. 702 */ 703 if (retired_buffer) { 704 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 705 ffec_txstart_locked(sc); 706 } 707 708 /* If there are no buffers outstanding, muzzle the watchdog. */ 709 if (sc->tx_idx_tail == sc->tx_idx_head) { 710 sc->tx_watchdog_count = 0; 711 } 712 } 713 714 inline static uint32_t 715 ffec_setup_rxdesc(struct ffec_softc *sc, int idx, bus_addr_t paddr) 716 { 717 uint32_t nidx; 718 719 /* 720 * The hardware requires 32-bit physical addresses. We set up the dma 721 * tag to indicate that, so the cast to uint32_t should never lose 722 * significant bits. 723 */ 724 nidx = next_rxidx(sc, idx); 725 sc->rxdesc_ring[idx].buf_paddr = (uint32_t)paddr; 726 sc->rxdesc_ring[idx].flags_len = FEC_RXDESC_EMPTY | 727 ((nidx == 0) ? FEC_RXDESC_WRAP : 0); 728 729 return (nidx); 730 } 731 732 static int 733 ffec_setup_rxbuf(struct ffec_softc *sc, int idx, struct mbuf * m) 734 { 735 int error, nsegs; 736 struct bus_dma_segment seg; 737 738 /* 739 * We need to leave at least ETHER_ALIGN bytes free at the beginning of 740 * the buffer to allow the data to be re-aligned after receiving it (by 741 * copying it backwards ETHER_ALIGN bytes in the same buffer). We also 742 * have to ensure that the beginning of the buffer is aligned to the 743 * hardware's requirements. 744 */ 745 m_adj(m, roundup(ETHER_ALIGN, FEC_RXBUF_ALIGN)); 746 747 error = bus_dmamap_load_mbuf_sg(sc->rxbuf_tag, sc->rxbuf_map[idx].map, 748 m, &seg, &nsegs, 0); 749 if (error != 0) { 750 return (error); 751 } 752 753 bus_dmamap_sync(sc->rxbuf_tag, sc->rxbuf_map[idx].map, 754 BUS_DMASYNC_PREREAD); 755 756 sc->rxbuf_map[idx].mbuf = m; 757 ffec_setup_rxdesc(sc, idx, seg.ds_addr); 758 759 return (0); 760 } 761 762 static struct mbuf * 763 ffec_alloc_mbufcl(struct ffec_softc *sc) 764 { 765 struct mbuf *m; 766 767 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 768 m->m_pkthdr.len = m->m_len = m->m_ext.ext_size; 769 770 return (m); 771 } 772 773 static void 774 ffec_rxfinish_onebuf(struct ffec_softc *sc, int len) 775 { 776 struct mbuf *m, *newmbuf; 777 struct ffec_bufmap *bmap; 778 uint8_t *dst, *src; 779 int error; 780 781 /* 782 * First try to get a new mbuf to plug into this slot in the rx ring. 783 * If that fails, drop the current packet and recycle the current 784 * mbuf, which is still mapped and loaded. 785 */ 786 if ((newmbuf = ffec_alloc_mbufcl(sc)) == NULL) { 787 ++sc->ifp->if_iqdrops; 788 ffec_setup_rxdesc(sc, sc->rx_idx, 789 sc->rxdesc_ring[sc->rx_idx].buf_paddr); 790 return; 791 } 792 793 /* 794 * Unfortunately, the protocol headers need to be aligned on a 32-bit 795 * boundary for the upper layers. The hardware requires receive 796 * buffers to be 16-byte aligned. The ethernet header is 14 bytes, 797 * leaving the protocol header unaligned. We used m_adj() after 798 * allocating the buffer to leave empty space at the start of the 799 * buffer, now we'll use the alignment agnostic bcopy() routine to 800 * shuffle all the data backwards 2 bytes and adjust m_data. 801 * 802 * XXX imx6 hardware is able to do this 2-byte alignment by setting the 803 * SHIFT16 bit in the RACC register. Older hardware doesn't have that 804 * feature, but for them could we speed this up by copying just the 805 * protocol headers into their own small mbuf then chaining the cluster 806 * to it? That way we'd only need to copy like 64 bytes or whatever 807 * the biggest header is, instead of the whole 1530ish-byte frame. 808 */ 809 810 FFEC_UNLOCK(sc); 811 812 bmap = &sc->rxbuf_map[sc->rx_idx]; 813 len -= ETHER_CRC_LEN; 814 bus_dmamap_sync(sc->rxbuf_tag, bmap->map, BUS_DMASYNC_POSTREAD); 815 bus_dmamap_unload(sc->rxbuf_tag, bmap->map); 816 m = bmap->mbuf; 817 bmap->mbuf = NULL; 818 m->m_len = len; 819 m->m_pkthdr.len = len; 820 m->m_pkthdr.rcvif = sc->ifp; 821 822 src = mtod(m, uint8_t*); 823 dst = src - ETHER_ALIGN; 824 bcopy(src, dst, len); 825 m->m_data = dst; 826 sc->ifp->if_input(sc->ifp, m); 827 828 FFEC_LOCK(sc); 829 830 if ((error = ffec_setup_rxbuf(sc, sc->rx_idx, newmbuf)) != 0) { 831 device_printf(sc->dev, "ffec_setup_rxbuf error %d\n", error); 832 /* XXX Now what? We've got a hole in the rx ring. */ 833 } 834 835 } 836 837 static void 838 ffec_rxfinish_locked(struct ffec_softc *sc) 839 { 840 struct ffec_hwdesc *desc; 841 int len; 842 boolean_t produced_empty_buffer; 843 844 FFEC_ASSERT_LOCKED(sc); 845 846 produced_empty_buffer = false; 847 for (;;) { 848 desc = &sc->rxdesc_ring[sc->rx_idx]; 849 if (desc->flags_len & FEC_RXDESC_EMPTY) 850 break; 851 produced_empty_buffer = true; 852 len = (desc->flags_len & FEC_RXDESC_LEN_MASK); 853 if (len < 64) { 854 /* 855 * Just recycle the descriptor and continue. . 856 */ 857 ffec_setup_rxdesc(sc, sc->rx_idx, 858 sc->rxdesc_ring[sc->rx_idx].buf_paddr); 859 } else if ((desc->flags_len & FEC_RXDESC_L) == 0) { 860 /* 861 * The entire frame is not in this buffer. Impossible. 862 * Recycle the descriptor and continue. 863 * 864 * XXX what's the right way to handle this? Probably we 865 * should stop/init the hardware because this should 866 * just really never happen when we have buffers bigger 867 * than the maximum frame size. 868 */ 869 device_printf(sc->dev, 870 "fec_rxfinish: received frame without LAST bit set"); 871 ffec_setup_rxdesc(sc, sc->rx_idx, 872 sc->rxdesc_ring[sc->rx_idx].buf_paddr); 873 } else if (desc->flags_len & FEC_RXDESC_ERROR_BITS) { 874 /* 875 * Something went wrong with receiving the frame, we 876 * don't care what (the hardware has counted the error 877 * in the stats registers already), we just reuse the 878 * same mbuf, which is still dma-mapped, by resetting 879 * the rx descriptor. 880 */ 881 ffec_setup_rxdesc(sc, sc->rx_idx, 882 sc->rxdesc_ring[sc->rx_idx].buf_paddr); 883 } else { 884 /* 885 * Normal case: a good frame all in one buffer. 886 */ 887 ffec_rxfinish_onebuf(sc, len); 888 } 889 sc->rx_idx = next_rxidx(sc, sc->rx_idx); 890 } 891 892 if (produced_empty_buffer) { 893 WR4(sc, FEC_RDAR_REG, FEC_RDAR_RDAR); 894 } 895 } 896 897 static void 898 ffec_get_hwaddr(struct ffec_softc *sc, uint8_t *hwaddr) 899 { 900 uint32_t palr, paur, rnd; 901 902 /* 903 * Try to recover a MAC address from the running hardware. If there's 904 * something non-zero there, assume the bootloader did the right thing 905 * and just use it. 906 * 907 * Otherwise, set the address to a convenient locally assigned address, 908 * 'bsd' + random 24 low-order bits. 'b' is 0x62, which has the locally 909 * assigned bit set, and the broadcast/multicast bit clear. 910 */ 911 palr = RD4(sc, FEC_PALR_REG); 912 paur = RD4(sc, FEC_PAUR_REG) & FEC_PAUR_PADDR2_MASK; 913 if ((palr | paur) != 0) { 914 hwaddr[0] = palr >> 24; 915 hwaddr[1] = palr >> 16; 916 hwaddr[2] = palr >> 8; 917 hwaddr[3] = palr >> 0; 918 hwaddr[4] = paur >> 24; 919 hwaddr[5] = paur >> 16; 920 } else { 921 rnd = arc4random() & 0x00ffffff; 922 hwaddr[0] = 'b'; 923 hwaddr[1] = 's'; 924 hwaddr[2] = 'd'; 925 hwaddr[3] = rnd >> 16; 926 hwaddr[4] = rnd >> 8; 927 hwaddr[5] = rnd >> 0; 928 } 929 930 if (bootverbose) { 931 device_printf(sc->dev, 932 "MAC address %02x:%02x:%02x:%02x:%02x:%02x:\n", 933 hwaddr[0], hwaddr[1], hwaddr[2], 934 hwaddr[3], hwaddr[4], hwaddr[5]); 935 } 936 } 937 938 static void 939 ffec_setup_rxfilter(struct ffec_softc *sc) 940 { 941 struct ifnet *ifp; 942 struct ifmultiaddr *ifma; 943 uint8_t *eaddr; 944 uint32_t crc; 945 uint64_t ghash, ihash; 946 947 FFEC_ASSERT_LOCKED(sc); 948 949 ifp = sc->ifp; 950 951 /* 952 * Set the multicast (group) filter hash. 953 */ 954 if ((ifp->if_flags & IFF_ALLMULTI)) 955 ghash = 0xffffffffffffffffLLU; 956 else { 957 ghash = 0; 958 if_maddr_rlock(ifp); 959 TAILQ_FOREACH(ifma, &sc->ifp->if_multiaddrs, ifma_link) { 960 if (ifma->ifma_addr->sa_family != AF_LINK) 961 continue; 962 /* 6 bits from MSB in LE CRC32 are used for hash. */ 963 crc = ether_crc32_le(LLADDR((struct sockaddr_dl *) 964 ifma->ifma_addr), ETHER_ADDR_LEN); 965 ghash |= 1LLU << (((uint8_t *)&crc)[3] >> 2); 966 } 967 if_maddr_runlock(ifp); 968 } 969 WR4(sc, FEC_GAUR_REG, (uint32_t)(ghash >> 32)); 970 WR4(sc, FEC_GALR_REG, (uint32_t)ghash); 971 972 /* 973 * Set the individual address filter hash. 974 * 975 * XXX Is 0 the right value when promiscuous is off? This hw feature 976 * seems to support the concept of MAC address aliases, does such a 977 * thing even exist? 978 */ 979 if ((ifp->if_flags & IFF_PROMISC)) 980 ihash = 0xffffffffffffffffLLU; 981 else { 982 ihash = 0; 983 } 984 WR4(sc, FEC_IAUR_REG, (uint32_t)(ihash >> 32)); 985 WR4(sc, FEC_IALR_REG, (uint32_t)ihash); 986 987 /* 988 * Set the primary address. 989 */ 990 eaddr = IF_LLADDR(ifp); 991 WR4(sc, FEC_PALR_REG, (eaddr[0] << 24) | (eaddr[1] << 16) | 992 (eaddr[2] << 8) | eaddr[3]); 993 WR4(sc, FEC_PAUR_REG, (eaddr[4] << 24) | (eaddr[5] << 16)); 994 } 995 996 static void 997 ffec_stop_locked(struct ffec_softc *sc) 998 { 999 struct ifnet *ifp; 1000 struct ffec_hwdesc *desc; 1001 struct ffec_bufmap *bmap; 1002 int idx; 1003 1004 FFEC_ASSERT_LOCKED(sc); 1005 1006 ifp = sc->ifp; 1007 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 1008 sc->tx_watchdog_count = 0; 1009 sc->stats_harvest_count = 0; 1010 1011 /* 1012 * Stop the hardware, mask all interrupts, and clear all current 1013 * interrupt status bits. 1014 */ 1015 WR4(sc, FEC_ECR_REG, RD4(sc, FEC_ECR_REG) & ~FEC_ECR_ETHEREN); 1016 WR4(sc, FEC_IEM_REG, 0x00000000); 1017 WR4(sc, FEC_IER_REG, 0xffffffff); 1018 1019 /* 1020 * Stop the media-check callout. Do not use callout_drain() because 1021 * we're holding a mutex the callout acquires, and if it's currently 1022 * waiting to acquire it, we'd deadlock. If it is waiting now, the 1023 * ffec_tick() routine will return without doing anything when it sees 1024 * that IFF_DRV_RUNNING is not set, so avoiding callout_drain() is safe. 1025 */ 1026 callout_stop(&sc->ffec_callout); 1027 1028 /* 1029 * Discard all untransmitted buffers. Each buffer is simply freed; 1030 * it's as if the bits were transmitted and then lost on the wire. 1031 * 1032 * XXX Is this right? Or should we use IFQ_DRV_PREPEND() to put them 1033 * back on the queue for when we get restarted later? 1034 */ 1035 idx = sc->tx_idx_tail; 1036 while (idx != sc->tx_idx_head) { 1037 desc = &sc->txdesc_ring[idx]; 1038 bmap = &sc->txbuf_map[idx]; 1039 if (desc->buf_paddr != 0) { 1040 bus_dmamap_unload(sc->txbuf_tag, bmap->map); 1041 m_freem(bmap->mbuf); 1042 bmap->mbuf = NULL; 1043 ffec_setup_txdesc(sc, idx, 0, 0); 1044 } 1045 idx = next_txidx(sc, idx); 1046 } 1047 1048 /* 1049 * Discard all unprocessed receive buffers. This amounts to just 1050 * pretending that nothing ever got received into them. We reuse the 1051 * mbuf already mapped for each desc, simply turning the EMPTY flags 1052 * back on so they'll get reused when we start up again. 1053 */ 1054 for (idx = 0; idx < RX_DESC_COUNT; ++idx) { 1055 desc = &sc->rxdesc_ring[idx]; 1056 ffec_setup_rxdesc(sc, idx, desc->buf_paddr); 1057 } 1058 } 1059 1060 static void 1061 ffec_init_locked(struct ffec_softc *sc) 1062 { 1063 struct ifnet *ifp = sc->ifp; 1064 uint32_t maxbuf, maxfl, regval; 1065 1066 FFEC_ASSERT_LOCKED(sc); 1067 1068 /* 1069 * The hardware has a limit of 0x7ff as the max frame length (see 1070 * comments for MRBR below), and we use mbuf clusters as receive 1071 * buffers, and we currently are designed to receive an entire frame 1072 * into a single buffer. 1073 * 1074 * We start with a MCLBYTES-sized cluster, but we have to offset into 1075 * the buffer by ETHER_ALIGN to make room for post-receive re-alignment, 1076 * and then that value has to be rounded up to the hardware's DMA 1077 * alignment requirements, so all in all our buffer is that much smaller 1078 * than MCLBYTES. 1079 * 1080 * The resulting value is used as the frame truncation length and the 1081 * max buffer receive buffer size for now. It'll become more complex 1082 * when we support jumbo frames and receiving fragments of them into 1083 * separate buffers. 1084 */ 1085 maxbuf = MCLBYTES - roundup(ETHER_ALIGN, FEC_RXBUF_ALIGN); 1086 maxfl = min(maxbuf, 0x7ff); 1087 1088 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 1089 return; 1090 1091 /* Mask all interrupts and clear all current interrupt status bits. */ 1092 WR4(sc, FEC_IEM_REG, 0x00000000); 1093 WR4(sc, FEC_IER_REG, 0xffffffff); 1094 1095 /* 1096 * Go set up palr/puar, galr/gaur, ialr/iaur. 1097 */ 1098 ffec_setup_rxfilter(sc); 1099 1100 /* 1101 * TFWR - Transmit FIFO watermark register. 1102 * 1103 * Set the transmit fifo watermark register to "store and forward" mode 1104 * and also set a threshold of 128 bytes in the fifo before transmission 1105 * of a frame begins (to avoid dma underruns). Recent FEC hardware 1106 * supports STRFWD and when that bit is set, the watermark level in the 1107 * low bits is ignored. Older hardware doesn't have STRFWD, but writing 1108 * to that bit is innocuous, and the TWFR bits get used instead. 1109 */ 1110 WR4(sc, FEC_TFWR_REG, FEC_TFWR_STRFWD | FEC_TFWR_TWFR_128BYTE); 1111 1112 /* RCR - Receive control register. 1113 * 1114 * Set max frame length + clean out anything left from u-boot. 1115 */ 1116 WR4(sc, FEC_RCR_REG, (maxfl << FEC_RCR_MAX_FL_SHIFT)); 1117 1118 /* 1119 * TCR - Transmit control register. 1120 * 1121 * Clean out anything left from u-boot. Any necessary values are set in 1122 * ffec_miibus_statchg() based on the media type. 1123 */ 1124 WR4(sc, FEC_TCR_REG, 0); 1125 1126 /* 1127 * OPD - Opcode/pause duration. 1128 * 1129 * XXX These magic numbers come from u-boot. 1130 */ 1131 WR4(sc, FEC_OPD_REG, 0x00010020); 1132 1133 /* 1134 * FRSR - Fifo receive start register. 1135 * 1136 * This register does not exist on imx6, it is present on earlier 1137 * hardware. The u-boot code sets this to a non-default value that's 32 1138 * bytes larger than the default, with no clue as to why. The default 1139 * value should work fine, so there's no code to init it here. 1140 */ 1141 1142 /* 1143 * MRBR - Max RX buffer size. 1144 * 1145 * Note: For hardware prior to imx6 this value cannot exceed 0x07ff, 1146 * but the datasheet says no such thing for imx6. On the imx6, setting 1147 * this to 2K without setting EN1588 resulted in a crazy runaway 1148 * receive loop in the hardware, where every rx descriptor in the ring 1149 * had its EMPTY flag cleared, no completion or error flags set, and a 1150 * length of zero. I think maybe you can only exceed it when EN1588 is 1151 * set, like maybe that's what enables jumbo frames, because in general 1152 * the EN1588 flag seems to be the "enable new stuff" vs. "be legacy- 1153 * compatible" flag. 1154 */ 1155 WR4(sc, FEC_MRBR_REG, maxfl << FEC_MRBR_R_BUF_SIZE_SHIFT); 1156 1157 /* 1158 * FTRL - Frame truncation length. 1159 * 1160 * Must be greater than or equal to the value set in FEC_RCR_MAXFL. 1161 */ 1162 WR4(sc, FEC_FTRL_REG, maxfl); 1163 1164 /* 1165 * RDSR / TDSR descriptor ring pointers. 1166 * 1167 * When we turn on ECR_ETHEREN at the end, the hardware zeroes its 1168 * internal current descriptor index values for both rings, so we zero 1169 * our index values as well. 1170 */ 1171 sc->rx_idx = 0; 1172 sc->tx_idx_head = sc->tx_idx_tail = 0; 1173 sc->txcount = 0; 1174 WR4(sc, FEC_RDSR_REG, sc->rxdesc_ring_paddr); 1175 WR4(sc, FEC_TDSR_REG, sc->txdesc_ring_paddr); 1176 1177 /* 1178 * EIM - interrupt mask register. 1179 * 1180 * We always enable the same set of interrupts while running; unlike 1181 * some drivers there's no need to change the mask on the fly depending 1182 * on what operations are in progress. 1183 */ 1184 WR4(sc, FEC_IEM_REG, FEC_IER_TXF | FEC_IER_RXF | FEC_IER_EBERR); 1185 1186 /* 1187 * MIBC - MIB control (hardware stats). 1188 */ 1189 regval = RD4(sc, FEC_MIBC_REG); 1190 WR4(sc, FEC_MIBC_REG, regval | FEC_MIBC_DIS); 1191 ffec_clear_stats(sc); 1192 WR4(sc, FEC_MIBC_REG, regval & ~FEC_MIBC_DIS); 1193 1194 /* 1195 * ECR - Ethernet control register. 1196 * 1197 * This must happen after all the other config registers are set. If 1198 * we're running on little-endian hardware, also set the flag for byte- 1199 * swapping descriptor ring entries. This flag doesn't exist on older 1200 * hardware, but it can be safely set -- the bit position it occupies 1201 * was unused. 1202 */ 1203 regval = RD4(sc, FEC_ECR_REG); 1204 #if _BYTE_ORDER == _LITTLE_ENDIAN 1205 regval |= FEC_ECR_DBSWP; 1206 #endif 1207 regval |= FEC_ECR_ETHEREN; 1208 WR4(sc, FEC_ECR_REG, regval); 1209 1210 ifp->if_drv_flags |= IFF_DRV_RUNNING; 1211 1212 /* 1213 * Call mii_mediachg() which will call back into ffec_miibus_statchg() to 1214 * set up the remaining config registers based on the current media. 1215 */ 1216 mii_mediachg(sc->mii_softc); 1217 callout_reset(&sc->ffec_callout, hz, ffec_tick, sc); 1218 1219 /* 1220 * Tell the hardware that receive buffers are available. They were made 1221 * available in ffec_attach() or ffec_stop(). 1222 */ 1223 WR4(sc, FEC_RDAR_REG, FEC_RDAR_RDAR); 1224 } 1225 1226 static void 1227 ffec_init(void *if_softc) 1228 { 1229 struct ffec_softc *sc = if_softc; 1230 1231 FFEC_LOCK(sc); 1232 ffec_init_locked(sc); 1233 FFEC_UNLOCK(sc); 1234 } 1235 1236 static void 1237 ffec_intr(void *arg) 1238 { 1239 struct ffec_softc *sc; 1240 uint32_t ier; 1241 1242 sc = arg; 1243 1244 FFEC_LOCK(sc); 1245 1246 ier = RD4(sc, FEC_IER_REG); 1247 1248 if (ier & FEC_IER_TXF) { 1249 WR4(sc, FEC_IER_REG, FEC_IER_TXF); 1250 ffec_txfinish_locked(sc); 1251 } 1252 1253 if (ier & FEC_IER_RXF) { 1254 WR4(sc, FEC_IER_REG, FEC_IER_RXF); 1255 ffec_rxfinish_locked(sc); 1256 } 1257 1258 /* 1259 * We actually don't care about most errors, because the hardware copes 1260 * with them just fine, discarding the incoming bad frame, or forcing a 1261 * bad CRC onto an outgoing bad frame, and counting the errors in the 1262 * stats registers. The one that really matters is EBERR (DMA bus 1263 * error) because the hardware automatically clears ECR[ETHEREN] and we 1264 * have to restart it here. It should never happen. 1265 */ 1266 if (ier & FEC_IER_EBERR) { 1267 WR4(sc, FEC_IER_REG, FEC_IER_EBERR); 1268 device_printf(sc->dev, 1269 "Ethernet DMA error, restarting controller.\n"); 1270 ffec_stop_locked(sc); 1271 ffec_init_locked(sc); 1272 } 1273 1274 FFEC_UNLOCK(sc); 1275 1276 } 1277 1278 static int 1279 ffec_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 1280 { 1281 struct ffec_softc *sc; 1282 struct mii_data *mii; 1283 struct ifreq *ifr; 1284 int mask, error; 1285 1286 sc = ifp->if_softc; 1287 ifr = (struct ifreq *)data; 1288 1289 error = 0; 1290 switch (cmd) { 1291 case SIOCSIFFLAGS: 1292 FFEC_LOCK(sc); 1293 if (ifp->if_flags & IFF_UP) { 1294 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 1295 if ((ifp->if_flags ^ sc->if_flags) & 1296 (IFF_PROMISC | IFF_ALLMULTI)) 1297 ffec_setup_rxfilter(sc); 1298 } else { 1299 if (!sc->is_detaching) 1300 ffec_init_locked(sc); 1301 } 1302 } else { 1303 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 1304 ffec_stop_locked(sc); 1305 } 1306 sc->if_flags = ifp->if_flags; 1307 FFEC_UNLOCK(sc); 1308 break; 1309 1310 case SIOCADDMULTI: 1311 case SIOCDELMULTI: 1312 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 1313 FFEC_LOCK(sc); 1314 ffec_setup_rxfilter(sc); 1315 FFEC_UNLOCK(sc); 1316 } 1317 break; 1318 1319 case SIOCSIFMEDIA: 1320 case SIOCGIFMEDIA: 1321 mii = sc->mii_softc; 1322 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd); 1323 break; 1324 1325 case SIOCSIFCAP: 1326 mask = ifp->if_capenable ^ ifr->ifr_reqcap; 1327 if (mask & IFCAP_VLAN_MTU) { 1328 /* No work to do except acknowledge the change took. */ 1329 ifp->if_capenable ^= IFCAP_VLAN_MTU; 1330 } 1331 break; 1332 1333 default: 1334 error = ether_ioctl(ifp, cmd, data); 1335 break; 1336 } 1337 1338 return (error); 1339 } 1340 1341 static int 1342 ffec_detach(device_t dev) 1343 { 1344 struct ffec_softc *sc; 1345 bus_dmamap_t map; 1346 int idx; 1347 1348 /* 1349 * NB: This function can be called internally to unwind a failure to 1350 * attach. Make sure a resource got allocated/created before destroying. 1351 */ 1352 1353 sc = device_get_softc(dev); 1354 1355 if (sc->is_attached) { 1356 FFEC_LOCK(sc); 1357 sc->is_detaching = true; 1358 ffec_stop_locked(sc); 1359 FFEC_UNLOCK(sc); 1360 callout_drain(&sc->ffec_callout); 1361 ether_ifdetach(sc->ifp); 1362 } 1363 1364 /* XXX no miibus detach? */ 1365 1366 /* Clean up RX DMA resources and free mbufs. */ 1367 for (idx = 0; idx < RX_DESC_COUNT; ++idx) { 1368 if ((map = sc->rxbuf_map[idx].map) != NULL) { 1369 bus_dmamap_unload(sc->rxbuf_tag, map); 1370 bus_dmamap_destroy(sc->rxbuf_tag, map); 1371 m_freem(sc->rxbuf_map[idx].mbuf); 1372 } 1373 } 1374 if (sc->rxbuf_tag != NULL) 1375 bus_dma_tag_destroy(sc->rxbuf_tag); 1376 if (sc->rxdesc_map != NULL) { 1377 bus_dmamap_unload(sc->rxdesc_tag, sc->rxdesc_map); 1378 bus_dmamap_destroy(sc->rxdesc_tag, sc->rxdesc_map); 1379 } 1380 if (sc->rxdesc_tag != NULL) 1381 bus_dma_tag_destroy(sc->rxdesc_tag); 1382 1383 /* Clean up TX DMA resources. */ 1384 for (idx = 0; idx < TX_DESC_COUNT; ++idx) { 1385 if ((map = sc->txbuf_map[idx].map) != NULL) { 1386 /* TX maps are already unloaded. */ 1387 bus_dmamap_destroy(sc->txbuf_tag, map); 1388 } 1389 } 1390 if (sc->txbuf_tag != NULL) 1391 bus_dma_tag_destroy(sc->txbuf_tag); 1392 if (sc->txdesc_map != NULL) { 1393 bus_dmamap_unload(sc->txdesc_tag, sc->txdesc_map); 1394 bus_dmamap_destroy(sc->txdesc_tag, sc->txdesc_map); 1395 } 1396 if (sc->txdesc_tag != NULL) 1397 bus_dma_tag_destroy(sc->txdesc_tag); 1398 1399 /* Release bus resources. */ 1400 if (sc->intr_cookie) 1401 bus_teardown_intr(dev, sc->irq_res, sc->intr_cookie); 1402 1403 if (sc->irq_res != NULL) 1404 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->irq_res); 1405 1406 if (sc->mem_res != NULL) 1407 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->mem_res); 1408 1409 FFEC_LOCK_DESTROY(sc); 1410 return (0); 1411 } 1412 1413 static int 1414 ffec_attach(device_t dev) 1415 { 1416 struct ffec_softc *sc; 1417 struct ifnet *ifp = NULL; 1418 struct mbuf *m; 1419 phandle_t ofw_node; 1420 int error, rid; 1421 uint8_t eaddr[ETHER_ADDR_LEN]; 1422 char phy_conn_name[32]; 1423 uint32_t idx, mscr; 1424 1425 sc = device_get_softc(dev); 1426 sc->dev = dev; 1427 1428 FFEC_LOCK_INIT(sc); 1429 1430 /* 1431 * There are differences in the implementation and features of the FEC 1432 * hardware on different SoCs, so figure out what type we are. 1433 */ 1434 sc->fectype = ofw_bus_search_compatible(dev, compat_data)->ocd_data; 1435 1436 /* 1437 * We have to be told what kind of electrical connection exists between 1438 * the MAC and PHY or we can't operate correctly. 1439 */ 1440 if ((ofw_node = ofw_bus_get_node(dev)) == -1) { 1441 device_printf(dev, "Impossible: Can't find ofw bus node\n"); 1442 error = ENXIO; 1443 goto out; 1444 } 1445 if (OF_searchprop(ofw_node, "phy-mode", 1446 phy_conn_name, sizeof(phy_conn_name)) != -1) { 1447 if (strcasecmp(phy_conn_name, "mii") == 0) 1448 sc->phy_conn_type = PHY_CONN_MII; 1449 else if (strcasecmp(phy_conn_name, "rmii") == 0) 1450 sc->phy_conn_type = PHY_CONN_RMII; 1451 else if (strcasecmp(phy_conn_name, "rgmii") == 0) 1452 sc->phy_conn_type = PHY_CONN_RGMII; 1453 } 1454 if (sc->phy_conn_type == PHY_CONN_UNKNOWN) { 1455 device_printf(sc->dev, "No valid 'phy-mode' " 1456 "property found in FDT data for device.\n"); 1457 error = ENOATTR; 1458 goto out; 1459 } 1460 1461 callout_init_mtx(&sc->ffec_callout, &sc->mtx, 0); 1462 1463 /* Allocate bus resources for accessing the hardware. */ 1464 rid = 0; 1465 sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 1466 RF_ACTIVE); 1467 if (sc->mem_res == NULL) { 1468 device_printf(dev, "could not allocate memory resources.\n"); 1469 error = ENOMEM; 1470 goto out; 1471 } 1472 rid = 0; 1473 sc->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 1474 RF_ACTIVE); 1475 if (sc->irq_res == NULL) { 1476 device_printf(dev, "could not allocate interrupt resources.\n"); 1477 error = ENOMEM; 1478 goto out; 1479 } 1480 1481 /* 1482 * Set up TX descriptor ring, descriptors, and dma maps. 1483 */ 1484 error = bus_dma_tag_create( 1485 bus_get_dma_tag(dev), /* Parent tag. */ 1486 FEC_DESC_RING_ALIGN, 0, /* alignment, boundary */ 1487 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 1488 BUS_SPACE_MAXADDR, /* highaddr */ 1489 NULL, NULL, /* filter, filterarg */ 1490 TX_DESC_SIZE, 1, /* maxsize, nsegments */ 1491 TX_DESC_SIZE, /* maxsegsize */ 1492 0, /* flags */ 1493 NULL, NULL, /* lockfunc, lockarg */ 1494 &sc->txdesc_tag); 1495 if (error != 0) { 1496 device_printf(sc->dev, 1497 "could not create TX ring DMA tag.\n"); 1498 goto out; 1499 } 1500 1501 error = bus_dmamem_alloc(sc->txdesc_tag, (void**)&sc->txdesc_ring, 1502 BUS_DMA_COHERENT | BUS_DMA_WAITOK | BUS_DMA_ZERO, &sc->txdesc_map); 1503 if (error != 0) { 1504 device_printf(sc->dev, 1505 "could not allocate TX descriptor ring.\n"); 1506 goto out; 1507 } 1508 1509 error = bus_dmamap_load(sc->txdesc_tag, sc->txdesc_map, sc->txdesc_ring, 1510 TX_DESC_SIZE, ffec_get1paddr, &sc->txdesc_ring_paddr, 0); 1511 if (error != 0) { 1512 device_printf(sc->dev, 1513 "could not load TX descriptor ring map.\n"); 1514 goto out; 1515 } 1516 1517 error = bus_dma_tag_create( 1518 bus_get_dma_tag(dev), /* Parent tag. */ 1519 FEC_TXBUF_ALIGN, 0, /* alignment, boundary */ 1520 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 1521 BUS_SPACE_MAXADDR, /* highaddr */ 1522 NULL, NULL, /* filter, filterarg */ 1523 MCLBYTES, 1, /* maxsize, nsegments */ 1524 MCLBYTES, /* maxsegsize */ 1525 0, /* flags */ 1526 NULL, NULL, /* lockfunc, lockarg */ 1527 &sc->txbuf_tag); 1528 if (error != 0) { 1529 device_printf(sc->dev, 1530 "could not create TX ring DMA tag.\n"); 1531 goto out; 1532 } 1533 1534 for (idx = 0; idx < TX_DESC_COUNT; ++idx) { 1535 error = bus_dmamap_create(sc->txbuf_tag, 0, 1536 &sc->txbuf_map[idx].map); 1537 if (error != 0) { 1538 device_printf(sc->dev, 1539 "could not create TX buffer DMA map.\n"); 1540 goto out; 1541 } 1542 ffec_setup_txdesc(sc, idx, 0, 0); 1543 } 1544 1545 /* 1546 * Set up RX descriptor ring, descriptors, dma maps, and mbufs. 1547 */ 1548 error = bus_dma_tag_create( 1549 bus_get_dma_tag(dev), /* Parent tag. */ 1550 FEC_DESC_RING_ALIGN, 0, /* alignment, boundary */ 1551 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 1552 BUS_SPACE_MAXADDR, /* highaddr */ 1553 NULL, NULL, /* filter, filterarg */ 1554 RX_DESC_SIZE, 1, /* maxsize, nsegments */ 1555 RX_DESC_SIZE, /* maxsegsize */ 1556 0, /* flags */ 1557 NULL, NULL, /* lockfunc, lockarg */ 1558 &sc->rxdesc_tag); 1559 if (error != 0) { 1560 device_printf(sc->dev, 1561 "could not create RX ring DMA tag.\n"); 1562 goto out; 1563 } 1564 1565 error = bus_dmamem_alloc(sc->rxdesc_tag, (void **)&sc->rxdesc_ring, 1566 BUS_DMA_COHERENT | BUS_DMA_WAITOK | BUS_DMA_ZERO, &sc->rxdesc_map); 1567 if (error != 0) { 1568 device_printf(sc->dev, 1569 "could not allocate RX descriptor ring.\n"); 1570 goto out; 1571 } 1572 1573 error = bus_dmamap_load(sc->rxdesc_tag, sc->rxdesc_map, sc->rxdesc_ring, 1574 RX_DESC_SIZE, ffec_get1paddr, &sc->rxdesc_ring_paddr, 0); 1575 if (error != 0) { 1576 device_printf(sc->dev, 1577 "could not load RX descriptor ring map.\n"); 1578 goto out; 1579 } 1580 1581 error = bus_dma_tag_create( 1582 bus_get_dma_tag(dev), /* Parent tag. */ 1583 1, 0, /* alignment, boundary */ 1584 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 1585 BUS_SPACE_MAXADDR, /* highaddr */ 1586 NULL, NULL, /* filter, filterarg */ 1587 MCLBYTES, 1, /* maxsize, nsegments */ 1588 MCLBYTES, /* maxsegsize */ 1589 0, /* flags */ 1590 NULL, NULL, /* lockfunc, lockarg */ 1591 &sc->rxbuf_tag); 1592 if (error != 0) { 1593 device_printf(sc->dev, 1594 "could not create RX buf DMA tag.\n"); 1595 goto out; 1596 } 1597 1598 for (idx = 0; idx < RX_DESC_COUNT; ++idx) { 1599 error = bus_dmamap_create(sc->rxbuf_tag, 0, 1600 &sc->rxbuf_map[idx].map); 1601 if (error != 0) { 1602 device_printf(sc->dev, 1603 "could not create RX buffer DMA map.\n"); 1604 goto out; 1605 } 1606 if ((m = ffec_alloc_mbufcl(sc)) == NULL) { 1607 device_printf(dev, "Could not alloc mbuf\n"); 1608 error = ENOMEM; 1609 goto out; 1610 } 1611 if ((error = ffec_setup_rxbuf(sc, idx, m)) != 0) { 1612 device_printf(sc->dev, 1613 "could not create new RX buffer.\n"); 1614 goto out; 1615 } 1616 } 1617 1618 /* Try to get the MAC address from the hardware before resetting it. */ 1619 ffec_get_hwaddr(sc, eaddr); 1620 1621 /* Reset the hardware. Disables all interrupts. */ 1622 WR4(sc, FEC_ECR_REG, FEC_ECR_RESET); 1623 1624 /* Setup interrupt handler. */ 1625 error = bus_setup_intr(dev, sc->irq_res, INTR_TYPE_NET | INTR_MPSAFE, 1626 NULL, ffec_intr, sc, &sc->intr_cookie); 1627 if (error != 0) { 1628 device_printf(dev, "could not setup interrupt handler.\n"); 1629 goto out; 1630 } 1631 1632 /* 1633 * Set up the PHY control register. 1634 * 1635 * Speed formula for ENET is md_clock = mac_clock / ((N + 1) * 2). 1636 * Speed formula for FEC is md_clock = mac_clock / (N * 2) 1637 * 1638 * XXX - Revisit this... 1639 * 1640 * For a Wandboard imx6 (ENET) I was originally using 4, but the uboot 1641 * code uses 10. Both values seem to work, but I suspect many modern 1642 * PHY parts can do mdio at speeds far above the standard 2.5 MHz. 1643 * 1644 * Different imx manuals use confusingly different terminology (things 1645 * like "system clock" and "internal module clock") with examples that 1646 * use frequencies that have nothing to do with ethernet, giving the 1647 * vague impression that maybe the clock in question is the periphclock 1648 * or something. In fact, on an imx53 development board (FEC), 1649 * measuring the mdio clock at the pin on the PHY and playing with 1650 * various divisors showed that the root speed was 66 MHz (clk_ipg_root 1651 * aka periphclock) and 13 was the right divisor. 1652 * 1653 * All in all, it seems likely that 13 is a safe divisor for now, 1654 * because if we really do need to base it on the peripheral clock 1655 * speed, then we need a platform-independant get-clock-freq API. 1656 */ 1657 mscr = 13 << FEC_MSCR_MII_SPEED_SHIFT; 1658 if (OF_hasprop(ofw_node, "phy-disable-preamble")) { 1659 mscr |= FEC_MSCR_DIS_PRE; 1660 if (bootverbose) 1661 device_printf(dev, "PHY preamble disabled\n"); 1662 } 1663 WR4(sc, FEC_MSCR_REG, mscr); 1664 1665 /* Set up the ethernet interface. */ 1666 sc->ifp = ifp = if_alloc(IFT_ETHER); 1667 1668 ifp->if_softc = sc; 1669 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1670 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1671 ifp->if_capabilities = IFCAP_VLAN_MTU; 1672 ifp->if_capenable = ifp->if_capabilities; 1673 ifp->if_start = ffec_txstart; 1674 ifp->if_ioctl = ffec_ioctl; 1675 ifp->if_init = ffec_init; 1676 IFQ_SET_MAXLEN(&ifp->if_snd, TX_DESC_COUNT - 1); 1677 ifp->if_snd.ifq_drv_maxlen = TX_DESC_COUNT - 1; 1678 IFQ_SET_READY(&ifp->if_snd); 1679 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 1680 1681 #if 0 /* XXX The hardware keeps stats we could use for these. */ 1682 ifp->if_linkmib = &sc->mibdata; 1683 ifp->if_linkmiblen = sizeof(sc->mibdata); 1684 #endif 1685 1686 /* Set up the miigasket hardware (if any). */ 1687 ffec_miigasket_setup(sc); 1688 1689 /* Attach the mii driver. */ 1690 error = mii_attach(dev, &sc->miibus, ifp, ffec_media_change, 1691 ffec_media_status, BMSR_DEFCAPMASK, MII_PHY_ANY, MII_OFFSET_ANY, 1692 (sc->fectype & FECTYPE_MVF) ? MIIF_FORCEANEG : 0); 1693 if (error != 0) { 1694 device_printf(dev, "PHY attach failed\n"); 1695 goto out; 1696 } 1697 sc->mii_softc = device_get_softc(sc->miibus); 1698 1699 /* All ready to run, attach the ethernet interface. */ 1700 ether_ifattach(ifp, eaddr); 1701 sc->is_attached = true; 1702 1703 error = 0; 1704 out: 1705 1706 if (error != 0) 1707 ffec_detach(dev); 1708 1709 return (error); 1710 } 1711 1712 static int 1713 ffec_probe(device_t dev) 1714 { 1715 uintptr_t fectype; 1716 1717 if (!ofw_bus_status_okay(dev)) 1718 return (ENXIO); 1719 1720 fectype = ofw_bus_search_compatible(dev, compat_data)->ocd_data; 1721 if (fectype == FECTYPE_NONE) 1722 return (ENXIO); 1723 1724 device_set_desc(dev, (fectype & FECFLAG_GBE) ? 1725 "Freescale Gigabit Ethernet Controller" : 1726 "Freescale Fast Ethernet Controller"); 1727 1728 return (BUS_PROBE_DEFAULT); 1729 } 1730 1731 1732 static device_method_t ffec_methods[] = { 1733 /* Device interface. */ 1734 DEVMETHOD(device_probe, ffec_probe), 1735 DEVMETHOD(device_attach, ffec_attach), 1736 DEVMETHOD(device_detach, ffec_detach), 1737 1738 /* 1739 DEVMETHOD(device_shutdown, ffec_shutdown), 1740 DEVMETHOD(device_suspend, ffec_suspend), 1741 DEVMETHOD(device_resume, ffec_resume), 1742 */ 1743 1744 /* MII interface. */ 1745 DEVMETHOD(miibus_readreg, ffec_miibus_readreg), 1746 DEVMETHOD(miibus_writereg, ffec_miibus_writereg), 1747 DEVMETHOD(miibus_statchg, ffec_miibus_statchg), 1748 1749 DEVMETHOD_END 1750 }; 1751 1752 static driver_t ffec_driver = { 1753 "ffec", 1754 ffec_methods, 1755 sizeof(struct ffec_softc) 1756 }; 1757 1758 static devclass_t ffec_devclass; 1759 1760 DRIVER_MODULE(ffec, simplebus, ffec_driver, ffec_devclass, 0, 0); 1761 DRIVER_MODULE(miibus, ffec, miibus_driver, miibus_devclass, 0, 0); 1762 1763 MODULE_DEPEND(ffec, ether, 1, 1, 1); 1764 MODULE_DEPEND(ffec, miibus, 1, 1, 1); 1765