1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2013 Ian Lepore <ian@freebsd.org> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 * 28 */ 29 30 #include <sys/cdefs.h> 31 /* 32 * Driver for Freescale Fast Ethernet Controller, found on imx-series SoCs among 33 * others. Also works for the ENET Gigibit controller found on imx6 and imx28, 34 * but the driver doesn't currently use any of the ENET advanced features other 35 * than enabling gigabit. 36 * 37 * The interface name 'fec' is already taken by netgraph's Fast Etherchannel 38 * (netgraph/ng_fec.c), so we use 'ffec'. 39 * 40 * Requires an FDT entry with at least these properties: 41 * fec: ethernet@02188000 { 42 * compatible = "fsl,imxNN-fec"; 43 * reg = <0x02188000 0x4000>; 44 * interrupts = <150 151>; 45 * phy-mode = "rgmii"; 46 * phy-disable-preamble; // optional 47 * }; 48 * The second interrupt number is for IEEE-1588, and is not currently used; it 49 * need not be present. phy-mode must be one of: "mii", "rmii", "rgmii". 50 * There is also an optional property, phy-disable-preamble, which if present 51 * will disable the preamble bits, cutting the size of each mdio transaction 52 * (and thus the busy-wait time) in half. 53 */ 54 55 #include <sys/param.h> 56 #include <sys/systm.h> 57 #include <sys/bus.h> 58 #include <sys/endian.h> 59 #include <sys/kernel.h> 60 #include <sys/lock.h> 61 #include <sys/malloc.h> 62 #include <sys/mbuf.h> 63 #include <sys/module.h> 64 #include <sys/mutex.h> 65 #include <sys/rman.h> 66 #include <sys/socket.h> 67 #include <sys/sockio.h> 68 #include <sys/sysctl.h> 69 70 #include <machine/bus.h> 71 72 #include <net/bpf.h> 73 #include <net/if.h> 74 #include <net/ethernet.h> 75 #include <net/if_dl.h> 76 #include <net/if_media.h> 77 #include <net/if_types.h> 78 #include <net/if_var.h> 79 #include <net/if_vlan_var.h> 80 81 #include <dev/fdt/fdt_common.h> 82 #include <dev/ffec/if_ffecreg.h> 83 #include <dev/ofw/ofw_bus.h> 84 #include <dev/ofw/ofw_bus_subr.h> 85 #include <dev/mii/mii.h> 86 #include <dev/mii/miivar.h> 87 #include <dev/mii/mii_fdt.h> 88 #include "miibus_if.h" 89 90 /* 91 * There are small differences in the hardware on various SoCs. Not every SoC 92 * we support has its own FECTYPE; most work as GENERIC and only the ones that 93 * need different handling get their own entry. In addition to the types in 94 * this list, there are some flags below that can be ORed into the upper bits. 95 */ 96 enum { 97 FECTYPE_NONE, 98 FECTYPE_GENERIC, 99 FECTYPE_IMX53, 100 FECTYPE_IMX6, /* imx6 and imx7 */ 101 FECTYPE_MVF, 102 }; 103 104 /* 105 * Flags that describe general differences between the FEC hardware in various 106 * SoCs. These are ORed into the FECTYPE enum values in the ofw_compat_data, so 107 * the low 8 bits are reserved for the type enum. In the softc, the type and 108 * flags are put into separate members, so that you don't need to mask the flags 109 * out of the type to compare it. 110 */ 111 #define FECTYPE_MASK 0x000000ff 112 #define FECFLAG_GBE (1 << 8) 113 #define FECFLAG_AVB (1 << 9) 114 #define FECFLAG_RACC (1 << 10) 115 116 /* 117 * Table of supported FDT compat strings and their associated FECTYPE values. 118 */ 119 static struct ofw_compat_data compat_data[] = { 120 {"fsl,imx51-fec", FECTYPE_GENERIC}, 121 {"fsl,imx53-fec", FECTYPE_IMX53}, 122 {"fsl,imx6q-fec", FECTYPE_IMX6 | FECFLAG_RACC | FECFLAG_GBE }, 123 {"fsl,imx6ul-fec", FECTYPE_IMX6 | FECFLAG_RACC }, 124 {"fsl,imx6sx-fec", FECTYPE_IMX6 | FECFLAG_RACC }, 125 {"fsl,imx7d-fec", FECTYPE_IMX6 | FECFLAG_RACC | FECFLAG_GBE | 126 FECFLAG_AVB }, 127 {"fsl,mvf600-fec", FECTYPE_MVF | FECFLAG_RACC }, 128 {"fsl,mvf-fec", FECTYPE_MVF}, 129 {NULL, FECTYPE_NONE}, 130 }; 131 132 /* 133 * Driver data and defines. 134 */ 135 #define RX_DESC_COUNT 64 136 #define RX_DESC_SIZE (sizeof(struct ffec_hwdesc) * RX_DESC_COUNT) 137 #define TX_DESC_COUNT 64 138 #define TX_DESC_SIZE (sizeof(struct ffec_hwdesc) * TX_DESC_COUNT) 139 140 #define WATCHDOG_TIMEOUT_SECS 5 141 142 #define MAX_IRQ_COUNT 3 143 144 struct ffec_bufmap { 145 struct mbuf *mbuf; 146 bus_dmamap_t map; 147 }; 148 149 struct ffec_softc { 150 device_t dev; 151 device_t miibus; 152 struct mii_data * mii_softc; 153 if_t ifp; 154 int if_flags; 155 struct mtx mtx; 156 struct resource *irq_res[MAX_IRQ_COUNT]; 157 struct resource *mem_res; 158 void * intr_cookie[MAX_IRQ_COUNT]; 159 struct callout ffec_callout; 160 mii_contype_t phy_conn_type; 161 uint32_t fecflags; 162 uint8_t fectype; 163 boolean_t link_is_up; 164 boolean_t is_attached; 165 boolean_t is_detaching; 166 int tx_watchdog_count; 167 int rxbuf_align; 168 int txbuf_align; 169 170 bus_dma_tag_t rxdesc_tag; 171 bus_dmamap_t rxdesc_map; 172 struct ffec_hwdesc *rxdesc_ring; 173 bus_addr_t rxdesc_ring_paddr; 174 bus_dma_tag_t rxbuf_tag; 175 struct ffec_bufmap rxbuf_map[RX_DESC_COUNT]; 176 uint32_t rx_idx; 177 178 bus_dma_tag_t txdesc_tag; 179 bus_dmamap_t txdesc_map; 180 struct ffec_hwdesc *txdesc_ring; 181 bus_addr_t txdesc_ring_paddr; 182 bus_dma_tag_t txbuf_tag; 183 struct ffec_bufmap txbuf_map[TX_DESC_COUNT]; 184 uint32_t tx_idx_head; 185 uint32_t tx_idx_tail; 186 int txcount; 187 }; 188 189 static struct resource_spec irq_res_spec[MAX_IRQ_COUNT + 1] = { 190 { SYS_RES_IRQ, 0, RF_ACTIVE }, 191 { SYS_RES_IRQ, 1, RF_ACTIVE | RF_OPTIONAL }, 192 { SYS_RES_IRQ, 2, RF_ACTIVE | RF_OPTIONAL }, 193 RESOURCE_SPEC_END 194 }; 195 196 #define FFEC_LOCK(sc) mtx_lock(&(sc)->mtx) 197 #define FFEC_UNLOCK(sc) mtx_unlock(&(sc)->mtx) 198 #define FFEC_LOCK_INIT(sc) mtx_init(&(sc)->mtx, \ 199 device_get_nameunit((sc)->dev), MTX_NETWORK_LOCK, MTX_DEF) 200 #define FFEC_LOCK_DESTROY(sc) mtx_destroy(&(sc)->mtx); 201 #define FFEC_ASSERT_LOCKED(sc) mtx_assert(&(sc)->mtx, MA_OWNED); 202 #define FFEC_ASSERT_UNLOCKED(sc) mtx_assert(&(sc)->mtx, MA_NOTOWNED); 203 204 static void ffec_init_locked(struct ffec_softc *sc); 205 static void ffec_stop_locked(struct ffec_softc *sc); 206 static void ffec_txstart_locked(struct ffec_softc *sc); 207 static void ffec_txfinish_locked(struct ffec_softc *sc); 208 209 static inline uint16_t 210 RD2(struct ffec_softc *sc, bus_size_t off) 211 { 212 213 return (bus_read_2(sc->mem_res, off)); 214 } 215 216 static inline void 217 WR2(struct ffec_softc *sc, bus_size_t off, uint16_t val) 218 { 219 220 bus_write_2(sc->mem_res, off, val); 221 } 222 223 static inline uint32_t 224 RD4(struct ffec_softc *sc, bus_size_t off) 225 { 226 227 return (bus_read_4(sc->mem_res, off)); 228 } 229 230 static inline void 231 WR4(struct ffec_softc *sc, bus_size_t off, uint32_t val) 232 { 233 234 bus_write_4(sc->mem_res, off, val); 235 } 236 237 static inline uint32_t 238 next_rxidx(struct ffec_softc *sc, uint32_t curidx) 239 { 240 241 return ((curidx == RX_DESC_COUNT - 1) ? 0 : curidx + 1); 242 } 243 244 static inline uint32_t 245 next_txidx(struct ffec_softc *sc, uint32_t curidx) 246 { 247 248 return ((curidx == TX_DESC_COUNT - 1) ? 0 : curidx + 1); 249 } 250 251 static void 252 ffec_get1paddr(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 253 { 254 255 if (error != 0) 256 return; 257 *(bus_addr_t *)arg = segs[0].ds_addr; 258 } 259 260 static void 261 ffec_miigasket_setup(struct ffec_softc *sc) 262 { 263 uint32_t ifmode; 264 265 /* 266 * We only need the gasket for MII and RMII connections on certain SoCs. 267 */ 268 269 switch (sc->fectype) 270 { 271 case FECTYPE_IMX53: 272 break; 273 default: 274 return; 275 } 276 277 switch (sc->phy_conn_type) 278 { 279 case MII_CONTYPE_MII: 280 ifmode = 0; 281 break; 282 case MII_CONTYPE_RMII: 283 ifmode = FEC_MIIGSK_CFGR_IF_MODE_RMII; 284 break; 285 default: 286 return; 287 } 288 289 /* 290 * Disable the gasket, configure for either MII or RMII, then enable. 291 */ 292 293 WR2(sc, FEC_MIIGSK_ENR, 0); 294 while (RD2(sc, FEC_MIIGSK_ENR) & FEC_MIIGSK_ENR_READY) 295 continue; 296 297 WR2(sc, FEC_MIIGSK_CFGR, ifmode); 298 299 WR2(sc, FEC_MIIGSK_ENR, FEC_MIIGSK_ENR_EN); 300 while (!(RD2(sc, FEC_MIIGSK_ENR) & FEC_MIIGSK_ENR_READY)) 301 continue; 302 } 303 304 static boolean_t 305 ffec_miibus_iowait(struct ffec_softc *sc) 306 { 307 uint32_t timeout; 308 309 for (timeout = 10000; timeout != 0; --timeout) 310 if (RD4(sc, FEC_IER_REG) & FEC_IER_MII) 311 return (true); 312 313 return (false); 314 } 315 316 static int 317 ffec_miibus_readreg(device_t dev, int phy, int reg) 318 { 319 struct ffec_softc *sc; 320 int val; 321 322 sc = device_get_softc(dev); 323 324 WR4(sc, FEC_IER_REG, FEC_IER_MII); 325 326 WR4(sc, FEC_MMFR_REG, FEC_MMFR_OP_READ | 327 FEC_MMFR_ST_VALUE | FEC_MMFR_TA_VALUE | 328 ((phy << FEC_MMFR_PA_SHIFT) & FEC_MMFR_PA_MASK) | 329 ((reg << FEC_MMFR_RA_SHIFT) & FEC_MMFR_RA_MASK)); 330 331 if (!ffec_miibus_iowait(sc)) { 332 device_printf(dev, "timeout waiting for mii read\n"); 333 return (-1); /* All-ones is a symptom of bad mdio. */ 334 } 335 336 val = RD4(sc, FEC_MMFR_REG) & FEC_MMFR_DATA_MASK; 337 338 return (val); 339 } 340 341 static int 342 ffec_miibus_writereg(device_t dev, int phy, int reg, int val) 343 { 344 struct ffec_softc *sc; 345 346 sc = device_get_softc(dev); 347 348 WR4(sc, FEC_IER_REG, FEC_IER_MII); 349 350 WR4(sc, FEC_MMFR_REG, FEC_MMFR_OP_WRITE | 351 FEC_MMFR_ST_VALUE | FEC_MMFR_TA_VALUE | 352 ((phy << FEC_MMFR_PA_SHIFT) & FEC_MMFR_PA_MASK) | 353 ((reg << FEC_MMFR_RA_SHIFT) & FEC_MMFR_RA_MASK) | 354 (val & FEC_MMFR_DATA_MASK)); 355 356 if (!ffec_miibus_iowait(sc)) { 357 device_printf(dev, "timeout waiting for mii write\n"); 358 return (-1); 359 } 360 361 return (0); 362 } 363 364 static void 365 ffec_miibus_statchg(device_t dev) 366 { 367 struct ffec_softc *sc; 368 struct mii_data *mii; 369 uint32_t ecr, rcr, tcr; 370 371 /* 372 * Called by the MII bus driver when the PHY establishes link to set the 373 * MAC interface registers. 374 */ 375 376 sc = device_get_softc(dev); 377 378 FFEC_ASSERT_LOCKED(sc); 379 380 mii = sc->mii_softc; 381 382 if (mii->mii_media_status & IFM_ACTIVE) 383 sc->link_is_up = true; 384 else 385 sc->link_is_up = false; 386 387 ecr = RD4(sc, FEC_ECR_REG) & ~FEC_ECR_SPEED; 388 rcr = RD4(sc, FEC_RCR_REG) & ~(FEC_RCR_RMII_10T | FEC_RCR_RMII_MODE | 389 FEC_RCR_RGMII_EN | FEC_RCR_DRT | FEC_RCR_FCE); 390 tcr = RD4(sc, FEC_TCR_REG) & ~FEC_TCR_FDEN; 391 392 rcr |= FEC_RCR_MII_MODE; /* Must always be on even for R[G]MII. */ 393 switch (sc->phy_conn_type) { 394 case MII_CONTYPE_RMII: 395 rcr |= FEC_RCR_RMII_MODE; 396 break; 397 case MII_CONTYPE_RGMII: 398 case MII_CONTYPE_RGMII_ID: 399 case MII_CONTYPE_RGMII_RXID: 400 case MII_CONTYPE_RGMII_TXID: 401 rcr |= FEC_RCR_RGMII_EN; 402 break; 403 default: 404 break; 405 } 406 407 switch (IFM_SUBTYPE(mii->mii_media_active)) { 408 case IFM_1000_T: 409 case IFM_1000_SX: 410 ecr |= FEC_ECR_SPEED; 411 break; 412 case IFM_100_TX: 413 /* Not-FEC_ECR_SPEED + not-FEC_RCR_RMII_10T means 100TX */ 414 break; 415 case IFM_10_T: 416 rcr |= FEC_RCR_RMII_10T; 417 break; 418 case IFM_NONE: 419 sc->link_is_up = false; 420 return; 421 default: 422 sc->link_is_up = false; 423 device_printf(dev, "Unsupported media %u\n", 424 IFM_SUBTYPE(mii->mii_media_active)); 425 return; 426 } 427 428 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) 429 tcr |= FEC_TCR_FDEN; 430 else 431 rcr |= FEC_RCR_DRT; 432 433 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FLOW) != 0) 434 rcr |= FEC_RCR_FCE; 435 436 WR4(sc, FEC_RCR_REG, rcr); 437 WR4(sc, FEC_TCR_REG, tcr); 438 WR4(sc, FEC_ECR_REG, ecr); 439 } 440 441 static void 442 ffec_media_status(if_t ifp, struct ifmediareq *ifmr) 443 { 444 struct ffec_softc *sc; 445 struct mii_data *mii; 446 447 448 sc = if_getsoftc(ifp); 449 mii = sc->mii_softc; 450 FFEC_LOCK(sc); 451 mii_pollstat(mii); 452 ifmr->ifm_active = mii->mii_media_active; 453 ifmr->ifm_status = mii->mii_media_status; 454 FFEC_UNLOCK(sc); 455 } 456 457 static int 458 ffec_media_change_locked(struct ffec_softc *sc) 459 { 460 461 return (mii_mediachg(sc->mii_softc)); 462 } 463 464 static int 465 ffec_media_change(if_t ifp) 466 { 467 struct ffec_softc *sc; 468 int error; 469 470 sc = if_getsoftc(ifp); 471 472 FFEC_LOCK(sc); 473 error = ffec_media_change_locked(sc); 474 FFEC_UNLOCK(sc); 475 return (error); 476 } 477 478 static void ffec_clear_stats(struct ffec_softc *sc) 479 { 480 uint32_t mibc; 481 482 mibc = RD4(sc, FEC_MIBC_REG); 483 484 /* 485 * On newer hardware the statistic regs are cleared by toggling a bit in 486 * the mib control register. On older hardware the clear procedure is 487 * to disable statistics collection, zero the regs, then re-enable. 488 */ 489 if (sc->fectype == FECTYPE_IMX6 || sc->fectype == FECTYPE_MVF) { 490 WR4(sc, FEC_MIBC_REG, mibc | FEC_MIBC_CLEAR); 491 WR4(sc, FEC_MIBC_REG, mibc & ~FEC_MIBC_CLEAR); 492 } else { 493 WR4(sc, FEC_MIBC_REG, mibc | FEC_MIBC_DIS); 494 495 WR4(sc, FEC_IEEE_R_DROP, 0); 496 WR4(sc, FEC_IEEE_R_MACERR, 0); 497 WR4(sc, FEC_RMON_R_CRC_ALIGN, 0); 498 WR4(sc, FEC_RMON_R_FRAG, 0); 499 WR4(sc, FEC_RMON_R_JAB, 0); 500 WR4(sc, FEC_RMON_R_MC_PKT, 0); 501 WR4(sc, FEC_RMON_R_OVERSIZE, 0); 502 WR4(sc, FEC_RMON_R_PACKETS, 0); 503 WR4(sc, FEC_RMON_R_UNDERSIZE, 0); 504 WR4(sc, FEC_RMON_T_COL, 0); 505 WR4(sc, FEC_RMON_T_CRC_ALIGN, 0); 506 WR4(sc, FEC_RMON_T_FRAG, 0); 507 WR4(sc, FEC_RMON_T_JAB, 0); 508 WR4(sc, FEC_RMON_T_MC_PKT, 0); 509 WR4(sc, FEC_RMON_T_OVERSIZE , 0); 510 WR4(sc, FEC_RMON_T_PACKETS, 0); 511 WR4(sc, FEC_RMON_T_UNDERSIZE, 0); 512 513 WR4(sc, FEC_MIBC_REG, mibc); 514 } 515 } 516 517 static void 518 ffec_harvest_stats(struct ffec_softc *sc) 519 { 520 if_t ifp; 521 522 ifp = sc->ifp; 523 524 /* 525 * - FEC_IEEE_R_DROP is "dropped due to invalid start frame delimiter" 526 * so it's really just another type of input error. 527 * - FEC_IEEE_R_MACERR is "no receive fifo space"; count as input drops. 528 */ 529 if_inc_counter(ifp, IFCOUNTER_IPACKETS, RD4(sc, FEC_RMON_R_PACKETS)); 530 if_inc_counter(ifp, IFCOUNTER_IMCASTS, RD4(sc, FEC_RMON_R_MC_PKT)); 531 if_inc_counter(ifp, IFCOUNTER_IERRORS, 532 RD4(sc, FEC_RMON_R_CRC_ALIGN) + RD4(sc, FEC_RMON_R_UNDERSIZE) + 533 RD4(sc, FEC_RMON_R_OVERSIZE) + RD4(sc, FEC_RMON_R_FRAG) + 534 RD4(sc, FEC_RMON_R_JAB) + RD4(sc, FEC_IEEE_R_DROP)); 535 536 if_inc_counter(ifp, IFCOUNTER_IQDROPS, RD4(sc, FEC_IEEE_R_MACERR)); 537 538 if_inc_counter(ifp, IFCOUNTER_OPACKETS, RD4(sc, FEC_RMON_T_PACKETS)); 539 if_inc_counter(ifp, IFCOUNTER_OMCASTS, RD4(sc, FEC_RMON_T_MC_PKT)); 540 if_inc_counter(ifp, IFCOUNTER_OERRORS, 541 RD4(sc, FEC_RMON_T_CRC_ALIGN) + RD4(sc, FEC_RMON_T_UNDERSIZE) + 542 RD4(sc, FEC_RMON_T_OVERSIZE) + RD4(sc, FEC_RMON_T_FRAG) + 543 RD4(sc, FEC_RMON_T_JAB)); 544 545 if_inc_counter(ifp, IFCOUNTER_COLLISIONS, RD4(sc, FEC_RMON_T_COL)); 546 547 ffec_clear_stats(sc); 548 } 549 550 static void 551 ffec_tick(void *arg) 552 { 553 struct ffec_softc *sc; 554 if_t ifp; 555 int link_was_up; 556 557 sc = arg; 558 559 FFEC_ASSERT_LOCKED(sc); 560 561 ifp = sc->ifp; 562 563 if (!(if_getdrvflags(ifp) & IFF_DRV_RUNNING)) 564 return; 565 566 /* 567 * Typical tx watchdog. If this fires it indicates that we enqueued 568 * packets for output and never got a txdone interrupt for them. Maybe 569 * it's a missed interrupt somehow, just pretend we got one. 570 */ 571 if (sc->tx_watchdog_count > 0) { 572 if (--sc->tx_watchdog_count == 0) { 573 ffec_txfinish_locked(sc); 574 } 575 } 576 577 /* Gather stats from hardware counters. */ 578 ffec_harvest_stats(sc); 579 580 /* Check the media status. */ 581 link_was_up = sc->link_is_up; 582 mii_tick(sc->mii_softc); 583 if (sc->link_is_up && !link_was_up) 584 ffec_txstart_locked(sc); 585 586 /* Schedule another check one second from now. */ 587 callout_reset(&sc->ffec_callout, hz, ffec_tick, sc); 588 } 589 590 inline static uint32_t 591 ffec_setup_txdesc(struct ffec_softc *sc, int idx, bus_addr_t paddr, 592 uint32_t len) 593 { 594 uint32_t nidx; 595 uint32_t flags; 596 597 nidx = next_txidx(sc, idx); 598 599 /* Addr/len 0 means we're clearing the descriptor after xmit done. */ 600 if (paddr == 0 || len == 0) { 601 flags = 0; 602 --sc->txcount; 603 } else { 604 flags = FEC_TXDESC_READY | FEC_TXDESC_L | FEC_TXDESC_TC; 605 ++sc->txcount; 606 } 607 if (nidx == 0) 608 flags |= FEC_TXDESC_WRAP; 609 610 /* 611 * The hardware requires 32-bit physical addresses. We set up the dma 612 * tag to indicate that, so the cast to uint32_t should never lose 613 * significant bits. 614 */ 615 sc->txdesc_ring[idx].buf_paddr = (uint32_t)paddr; 616 sc->txdesc_ring[idx].flags_len = flags | len; /* Must be set last! */ 617 618 return (nidx); 619 } 620 621 static int 622 ffec_setup_txbuf(struct ffec_softc *sc, int idx, struct mbuf **mp) 623 { 624 struct mbuf * m; 625 int error, nsegs; 626 struct bus_dma_segment seg; 627 628 if ((m = m_defrag(*mp, M_NOWAIT)) == NULL) 629 return (ENOMEM); 630 *mp = m; 631 632 error = bus_dmamap_load_mbuf_sg(sc->txbuf_tag, sc->txbuf_map[idx].map, 633 m, &seg, &nsegs, 0); 634 if (error != 0) { 635 return (ENOMEM); 636 } 637 bus_dmamap_sync(sc->txbuf_tag, sc->txbuf_map[idx].map, 638 BUS_DMASYNC_PREWRITE); 639 640 sc->txbuf_map[idx].mbuf = m; 641 ffec_setup_txdesc(sc, idx, seg.ds_addr, seg.ds_len); 642 643 return (0); 644 645 } 646 647 static void 648 ffec_txstart_locked(struct ffec_softc *sc) 649 { 650 if_t ifp; 651 struct mbuf *m; 652 int enqueued; 653 654 FFEC_ASSERT_LOCKED(sc); 655 656 if (!sc->link_is_up) 657 return; 658 659 ifp = sc->ifp; 660 661 if (if_getdrvflags(ifp) & IFF_DRV_OACTIVE) 662 return; 663 664 enqueued = 0; 665 666 for (;;) { 667 if (sc->txcount == (TX_DESC_COUNT-1)) { 668 if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, 0); 669 break; 670 } 671 m = if_dequeue(ifp); 672 if (m == NULL) 673 break; 674 if (ffec_setup_txbuf(sc, sc->tx_idx_head, &m) != 0) { 675 if_sendq_prepend(ifp, m); 676 break; 677 } 678 BPF_MTAP(ifp, m); 679 sc->tx_idx_head = next_txidx(sc, sc->tx_idx_head); 680 ++enqueued; 681 } 682 683 if (enqueued != 0) { 684 bus_dmamap_sync(sc->txdesc_tag, sc->txdesc_map, BUS_DMASYNC_PREWRITE); 685 WR4(sc, FEC_TDAR_REG, FEC_TDAR_TDAR); 686 bus_dmamap_sync(sc->txdesc_tag, sc->txdesc_map, BUS_DMASYNC_POSTWRITE); 687 sc->tx_watchdog_count = WATCHDOG_TIMEOUT_SECS; 688 } 689 } 690 691 static void 692 ffec_txstart(if_t ifp) 693 { 694 struct ffec_softc *sc = if_getsoftc(ifp); 695 696 FFEC_LOCK(sc); 697 ffec_txstart_locked(sc); 698 FFEC_UNLOCK(sc); 699 } 700 701 static void 702 ffec_txfinish_locked(struct ffec_softc *sc) 703 { 704 if_t ifp; 705 struct ffec_hwdesc *desc; 706 struct ffec_bufmap *bmap; 707 boolean_t retired_buffer; 708 709 FFEC_ASSERT_LOCKED(sc); 710 711 /* XXX Can't set PRE|POST right now, but we need both. */ 712 bus_dmamap_sync(sc->txdesc_tag, sc->txdesc_map, BUS_DMASYNC_PREREAD); 713 bus_dmamap_sync(sc->txdesc_tag, sc->txdesc_map, BUS_DMASYNC_POSTREAD); 714 ifp = sc->ifp; 715 retired_buffer = false; 716 while (sc->tx_idx_tail != sc->tx_idx_head) { 717 desc = &sc->txdesc_ring[sc->tx_idx_tail]; 718 if (desc->flags_len & FEC_TXDESC_READY) 719 break; 720 retired_buffer = true; 721 bmap = &sc->txbuf_map[sc->tx_idx_tail]; 722 bus_dmamap_sync(sc->txbuf_tag, bmap->map, 723 BUS_DMASYNC_POSTWRITE); 724 bus_dmamap_unload(sc->txbuf_tag, bmap->map); 725 m_freem(bmap->mbuf); 726 bmap->mbuf = NULL; 727 ffec_setup_txdesc(sc, sc->tx_idx_tail, 0, 0); 728 sc->tx_idx_tail = next_txidx(sc, sc->tx_idx_tail); 729 } 730 731 /* 732 * If we retired any buffers, there will be open tx slots available in 733 * the descriptor ring, go try to start some new output. 734 */ 735 if (retired_buffer) { 736 if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE); 737 ffec_txstart_locked(sc); 738 } 739 740 /* If there are no buffers outstanding, muzzle the watchdog. */ 741 if (sc->tx_idx_tail == sc->tx_idx_head) { 742 sc->tx_watchdog_count = 0; 743 } 744 } 745 746 inline static uint32_t 747 ffec_setup_rxdesc(struct ffec_softc *sc, int idx, bus_addr_t paddr) 748 { 749 uint32_t nidx; 750 751 /* 752 * The hardware requires 32-bit physical addresses. We set up the dma 753 * tag to indicate that, so the cast to uint32_t should never lose 754 * significant bits. 755 */ 756 nidx = next_rxidx(sc, idx); 757 sc->rxdesc_ring[idx].buf_paddr = (uint32_t)paddr; 758 sc->rxdesc_ring[idx].flags_len = FEC_RXDESC_EMPTY | 759 ((nidx == 0) ? FEC_RXDESC_WRAP : 0); 760 761 return (nidx); 762 } 763 764 static int 765 ffec_setup_rxbuf(struct ffec_softc *sc, int idx, struct mbuf * m) 766 { 767 int error, nsegs; 768 struct bus_dma_segment seg; 769 770 if (!(sc->fecflags & FECFLAG_RACC)) { 771 /* 772 * The RACC[SHIFT16] feature is not available. So, we need to 773 * leave at least ETHER_ALIGN bytes free at the beginning of the 774 * buffer to allow the data to be re-aligned after receiving it 775 * (by copying it backwards ETHER_ALIGN bytes in the same 776 * buffer). We also have to ensure that the beginning of the 777 * buffer is aligned to the hardware's requirements. 778 */ 779 m_adj(m, roundup(ETHER_ALIGN, sc->rxbuf_align)); 780 } 781 782 error = bus_dmamap_load_mbuf_sg(sc->rxbuf_tag, sc->rxbuf_map[idx].map, 783 m, &seg, &nsegs, 0); 784 if (error != 0) { 785 return (error); 786 } 787 788 bus_dmamap_sync(sc->rxbuf_tag, sc->rxbuf_map[idx].map, 789 BUS_DMASYNC_PREREAD); 790 791 sc->rxbuf_map[idx].mbuf = m; 792 ffec_setup_rxdesc(sc, idx, seg.ds_addr); 793 794 return (0); 795 } 796 797 static struct mbuf * 798 ffec_alloc_mbufcl(struct ffec_softc *sc) 799 { 800 struct mbuf *m; 801 802 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 803 if (m != NULL) 804 m->m_pkthdr.len = m->m_len = m->m_ext.ext_size; 805 806 return (m); 807 } 808 809 static void 810 ffec_rxfinish_onebuf(struct ffec_softc *sc, int len) 811 { 812 struct mbuf *m, *newmbuf; 813 struct ffec_bufmap *bmap; 814 uint8_t *dst, *src; 815 int error; 816 817 /* 818 * First try to get a new mbuf to plug into this slot in the rx ring. 819 * If that fails, drop the current packet and recycle the current 820 * mbuf, which is still mapped and loaded. 821 */ 822 if ((newmbuf = ffec_alloc_mbufcl(sc)) == NULL) { 823 if_inc_counter(sc->ifp, IFCOUNTER_IQDROPS, 1); 824 ffec_setup_rxdesc(sc, sc->rx_idx, 825 sc->rxdesc_ring[sc->rx_idx].buf_paddr); 826 return; 827 } 828 829 FFEC_UNLOCK(sc); 830 831 bmap = &sc->rxbuf_map[sc->rx_idx]; 832 len -= ETHER_CRC_LEN; 833 bus_dmamap_sync(sc->rxbuf_tag, bmap->map, BUS_DMASYNC_POSTREAD); 834 bus_dmamap_unload(sc->rxbuf_tag, bmap->map); 835 m = bmap->mbuf; 836 bmap->mbuf = NULL; 837 m->m_len = len; 838 m->m_pkthdr.len = len; 839 m->m_pkthdr.rcvif = sc->ifp; 840 841 /* 842 * Align the protocol headers in the receive buffer on a 32-bit 843 * boundary. Newer hardware does the alignment for us. On hardware 844 * that doesn't support this feature, we have to copy-align the data. 845 * 846 * XXX for older hardware, could we speed this up by copying just the 847 * protocol headers into their own small mbuf then chaining the cluster 848 * to it? That way we'd only need to copy like 64 bytes or whatever the 849 * biggest header is, instead of the whole 1530ish-byte frame. 850 */ 851 if (sc->fecflags & FECFLAG_RACC) { 852 m->m_data = mtod(m, uint8_t *) + 2; 853 } else { 854 src = mtod(m, uint8_t*); 855 dst = src - ETHER_ALIGN; 856 bcopy(src, dst, len); 857 m->m_data = dst; 858 } 859 if_input(sc->ifp, m); 860 861 FFEC_LOCK(sc); 862 863 if ((error = ffec_setup_rxbuf(sc, sc->rx_idx, newmbuf)) != 0) { 864 device_printf(sc->dev, "ffec_setup_rxbuf error %d\n", error); 865 /* XXX Now what? We've got a hole in the rx ring. */ 866 } 867 868 } 869 870 static void 871 ffec_rxfinish_locked(struct ffec_softc *sc) 872 { 873 struct ffec_hwdesc *desc; 874 int len; 875 boolean_t produced_empty_buffer; 876 877 FFEC_ASSERT_LOCKED(sc); 878 879 /* XXX Can't set PRE|POST right now, but we need both. */ 880 bus_dmamap_sync(sc->rxdesc_tag, sc->rxdesc_map, BUS_DMASYNC_PREREAD); 881 bus_dmamap_sync(sc->rxdesc_tag, sc->rxdesc_map, BUS_DMASYNC_POSTREAD); 882 produced_empty_buffer = false; 883 for (;;) { 884 desc = &sc->rxdesc_ring[sc->rx_idx]; 885 if (desc->flags_len & FEC_RXDESC_EMPTY) 886 break; 887 produced_empty_buffer = true; 888 len = (desc->flags_len & FEC_RXDESC_LEN_MASK); 889 if (len < 64) { 890 /* 891 * Just recycle the descriptor and continue. . 892 */ 893 ffec_setup_rxdesc(sc, sc->rx_idx, 894 sc->rxdesc_ring[sc->rx_idx].buf_paddr); 895 } else if ((desc->flags_len & FEC_RXDESC_L) == 0) { 896 /* 897 * The entire frame is not in this buffer. Impossible. 898 * Recycle the descriptor and continue. 899 * 900 * XXX what's the right way to handle this? Probably we 901 * should stop/init the hardware because this should 902 * just really never happen when we have buffers bigger 903 * than the maximum frame size. 904 */ 905 device_printf(sc->dev, 906 "fec_rxfinish: received frame without LAST bit set"); 907 ffec_setup_rxdesc(sc, sc->rx_idx, 908 sc->rxdesc_ring[sc->rx_idx].buf_paddr); 909 } else if (desc->flags_len & FEC_RXDESC_ERROR_BITS) { 910 /* 911 * Something went wrong with receiving the frame, we 912 * don't care what (the hardware has counted the error 913 * in the stats registers already), we just reuse the 914 * same mbuf, which is still dma-mapped, by resetting 915 * the rx descriptor. 916 */ 917 ffec_setup_rxdesc(sc, sc->rx_idx, 918 sc->rxdesc_ring[sc->rx_idx].buf_paddr); 919 } else { 920 /* 921 * Normal case: a good frame all in one buffer. 922 */ 923 ffec_rxfinish_onebuf(sc, len); 924 } 925 sc->rx_idx = next_rxidx(sc, sc->rx_idx); 926 } 927 928 if (produced_empty_buffer) { 929 bus_dmamap_sync(sc->rxdesc_tag, sc->rxdesc_map, BUS_DMASYNC_PREWRITE); 930 WR4(sc, FEC_RDAR_REG, FEC_RDAR_RDAR); 931 bus_dmamap_sync(sc->rxdesc_tag, sc->rxdesc_map, BUS_DMASYNC_POSTWRITE); 932 } 933 } 934 935 static void 936 ffec_get_hwaddr(struct ffec_softc *sc, uint8_t *hwaddr) 937 { 938 uint32_t palr, paur, rnd; 939 940 /* 941 * Try to recover a MAC address from the running hardware. If there's 942 * something non-zero there, assume the bootloader did the right thing 943 * and just use it. 944 * 945 * Otherwise, set the address to a convenient locally assigned address, 946 * 'bsd' + random 24 low-order bits. 'b' is 0x62, which has the locally 947 * assigned bit set, and the broadcast/multicast bit clear. 948 */ 949 palr = RD4(sc, FEC_PALR_REG); 950 paur = RD4(sc, FEC_PAUR_REG) & FEC_PAUR_PADDR2_MASK; 951 if ((palr | paur) != 0) { 952 hwaddr[0] = palr >> 24; 953 hwaddr[1] = palr >> 16; 954 hwaddr[2] = palr >> 8; 955 hwaddr[3] = palr >> 0; 956 hwaddr[4] = paur >> 24; 957 hwaddr[5] = paur >> 16; 958 } else { 959 rnd = arc4random() & 0x00ffffff; 960 hwaddr[0] = 'b'; 961 hwaddr[1] = 's'; 962 hwaddr[2] = 'd'; 963 hwaddr[3] = rnd >> 16; 964 hwaddr[4] = rnd >> 8; 965 hwaddr[5] = rnd >> 0; 966 } 967 968 if (bootverbose) { 969 device_printf(sc->dev, 970 "MAC address %02x:%02x:%02x:%02x:%02x:%02x:\n", 971 hwaddr[0], hwaddr[1], hwaddr[2], 972 hwaddr[3], hwaddr[4], hwaddr[5]); 973 } 974 } 975 976 static u_int 977 ffec_hash_maddr(void *arg, struct sockaddr_dl *sdl, u_int cnt) 978 { 979 uint64_t *ghash = arg; 980 uint32_t crc; 981 982 /* 6 bits from MSB in LE CRC32 are used for hash. */ 983 crc = ether_crc32_le(LLADDR(sdl), ETHER_ADDR_LEN); 984 *ghash |= 1LLU << (((uint8_t *)&crc)[3] >> 2); 985 986 return (1); 987 } 988 989 static void 990 ffec_setup_rxfilter(struct ffec_softc *sc) 991 { 992 if_t ifp; 993 uint8_t *eaddr; 994 uint64_t ghash, ihash; 995 996 FFEC_ASSERT_LOCKED(sc); 997 998 ifp = sc->ifp; 999 1000 /* 1001 * Set the multicast (group) filter hash. 1002 */ 1003 if ((if_getflags(ifp) & IFF_ALLMULTI)) 1004 ghash = 0xffffffffffffffffLLU; 1005 else { 1006 ghash = 0; 1007 if_foreach_llmaddr(ifp, ffec_hash_maddr, &ghash); 1008 } 1009 WR4(sc, FEC_GAUR_REG, (uint32_t)(ghash >> 32)); 1010 WR4(sc, FEC_GALR_REG, (uint32_t)ghash); 1011 1012 /* 1013 * Set the individual address filter hash. 1014 * 1015 * XXX Is 0 the right value when promiscuous is off? This hw feature 1016 * seems to support the concept of MAC address aliases, does such a 1017 * thing even exist? 1018 */ 1019 if ((if_getflags(ifp) & IFF_PROMISC)) 1020 ihash = 0xffffffffffffffffLLU; 1021 else { 1022 ihash = 0; 1023 } 1024 WR4(sc, FEC_IAUR_REG, (uint32_t)(ihash >> 32)); 1025 WR4(sc, FEC_IALR_REG, (uint32_t)ihash); 1026 1027 /* 1028 * Set the primary address. 1029 */ 1030 eaddr = if_getlladdr(ifp); 1031 WR4(sc, FEC_PALR_REG, (eaddr[0] << 24) | (eaddr[1] << 16) | 1032 (eaddr[2] << 8) | eaddr[3]); 1033 WR4(sc, FEC_PAUR_REG, (eaddr[4] << 24) | (eaddr[5] << 16)); 1034 } 1035 1036 static void 1037 ffec_stop_locked(struct ffec_softc *sc) 1038 { 1039 if_t ifp; 1040 struct ffec_hwdesc *desc; 1041 struct ffec_bufmap *bmap; 1042 int idx; 1043 1044 FFEC_ASSERT_LOCKED(sc); 1045 1046 ifp = sc->ifp; 1047 if_setdrvflagbits(ifp, 0, (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)); 1048 sc->tx_watchdog_count = 0; 1049 1050 /* 1051 * Stop the hardware, mask all interrupts, and clear all current 1052 * interrupt status bits. 1053 */ 1054 WR4(sc, FEC_ECR_REG, RD4(sc, FEC_ECR_REG) & ~FEC_ECR_ETHEREN); 1055 WR4(sc, FEC_IEM_REG, 0x00000000); 1056 WR4(sc, FEC_IER_REG, 0xffffffff); 1057 1058 /* 1059 * Stop the media-check callout. Do not use callout_drain() because 1060 * we're holding a mutex the callout acquires, and if it's currently 1061 * waiting to acquire it, we'd deadlock. If it is waiting now, the 1062 * ffec_tick() routine will return without doing anything when it sees 1063 * that IFF_DRV_RUNNING is not set, so avoiding callout_drain() is safe. 1064 */ 1065 callout_stop(&sc->ffec_callout); 1066 1067 /* 1068 * Discard all untransmitted buffers. Each buffer is simply freed; 1069 * it's as if the bits were transmitted and then lost on the wire. 1070 * 1071 * XXX Is this right? Or should we use IFQ_DRV_PREPEND() to put them 1072 * back on the queue for when we get restarted later? 1073 */ 1074 idx = sc->tx_idx_tail; 1075 while (idx != sc->tx_idx_head) { 1076 desc = &sc->txdesc_ring[idx]; 1077 bmap = &sc->txbuf_map[idx]; 1078 if (desc->buf_paddr != 0) { 1079 bus_dmamap_unload(sc->txbuf_tag, bmap->map); 1080 m_freem(bmap->mbuf); 1081 bmap->mbuf = NULL; 1082 ffec_setup_txdesc(sc, idx, 0, 0); 1083 } 1084 idx = next_txidx(sc, idx); 1085 } 1086 1087 /* 1088 * Discard all unprocessed receive buffers. This amounts to just 1089 * pretending that nothing ever got received into them. We reuse the 1090 * mbuf already mapped for each desc, simply turning the EMPTY flags 1091 * back on so they'll get reused when we start up again. 1092 */ 1093 for (idx = 0; idx < RX_DESC_COUNT; ++idx) { 1094 desc = &sc->rxdesc_ring[idx]; 1095 ffec_setup_rxdesc(sc, idx, desc->buf_paddr); 1096 } 1097 } 1098 1099 static void 1100 ffec_init_locked(struct ffec_softc *sc) 1101 { 1102 if_t ifp = sc->ifp; 1103 uint32_t maxbuf, maxfl, regval; 1104 1105 FFEC_ASSERT_LOCKED(sc); 1106 1107 /* 1108 * The hardware has a limit of 0x7ff as the max frame length (see 1109 * comments for MRBR below), and we use mbuf clusters as receive 1110 * buffers, and we currently are designed to receive an entire frame 1111 * into a single buffer. 1112 * 1113 * We start with a MCLBYTES-sized cluster, but we have to offset into 1114 * the buffer by ETHER_ALIGN to make room for post-receive re-alignment, 1115 * and then that value has to be rounded up to the hardware's DMA 1116 * alignment requirements, so all in all our buffer is that much smaller 1117 * than MCLBYTES. 1118 * 1119 * The resulting value is used as the frame truncation length and the 1120 * max buffer receive buffer size for now. It'll become more complex 1121 * when we support jumbo frames and receiving fragments of them into 1122 * separate buffers. 1123 */ 1124 maxbuf = MCLBYTES - roundup(ETHER_ALIGN, sc->rxbuf_align); 1125 maxfl = min(maxbuf, 0x7ff); 1126 1127 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) 1128 return; 1129 1130 /* Mask all interrupts and clear all current interrupt status bits. */ 1131 WR4(sc, FEC_IEM_REG, 0x00000000); 1132 WR4(sc, FEC_IER_REG, 0xffffffff); 1133 1134 /* 1135 * Go set up palr/puar, galr/gaur, ialr/iaur. 1136 */ 1137 ffec_setup_rxfilter(sc); 1138 1139 /* 1140 * TFWR - Transmit FIFO watermark register. 1141 * 1142 * Set the transmit fifo watermark register to "store and forward" mode 1143 * and also set a threshold of 128 bytes in the fifo before transmission 1144 * of a frame begins (to avoid dma underruns). Recent FEC hardware 1145 * supports STRFWD and when that bit is set, the watermark level in the 1146 * low bits is ignored. Older hardware doesn't have STRFWD, but writing 1147 * to that bit is innocuous, and the TWFR bits get used instead. 1148 */ 1149 WR4(sc, FEC_TFWR_REG, FEC_TFWR_STRFWD | FEC_TFWR_TWFR_128BYTE); 1150 1151 /* RCR - Receive control register. 1152 * 1153 * Set max frame length + clean out anything left from u-boot. 1154 */ 1155 WR4(sc, FEC_RCR_REG, (maxfl << FEC_RCR_MAX_FL_SHIFT)); 1156 1157 /* 1158 * TCR - Transmit control register. 1159 * 1160 * Clean out anything left from u-boot. Any necessary values are set in 1161 * ffec_miibus_statchg() based on the media type. 1162 */ 1163 WR4(sc, FEC_TCR_REG, 0); 1164 1165 /* 1166 * OPD - Opcode/pause duration. 1167 * 1168 * XXX These magic numbers come from u-boot. 1169 */ 1170 WR4(sc, FEC_OPD_REG, 0x00010020); 1171 1172 /* 1173 * FRSR - Fifo receive start register. 1174 * 1175 * This register does not exist on imx6, it is present on earlier 1176 * hardware. The u-boot code sets this to a non-default value that's 32 1177 * bytes larger than the default, with no clue as to why. The default 1178 * value should work fine, so there's no code to init it here. 1179 */ 1180 1181 /* 1182 * MRBR - Max RX buffer size. 1183 * 1184 * Note: For hardware prior to imx6 this value cannot exceed 0x07ff, 1185 * but the datasheet says no such thing for imx6. On the imx6, setting 1186 * this to 2K without setting EN1588 resulted in a crazy runaway 1187 * receive loop in the hardware, where every rx descriptor in the ring 1188 * had its EMPTY flag cleared, no completion or error flags set, and a 1189 * length of zero. I think maybe you can only exceed it when EN1588 is 1190 * set, like maybe that's what enables jumbo frames, because in general 1191 * the EN1588 flag seems to be the "enable new stuff" vs. "be legacy- 1192 * compatible" flag. 1193 */ 1194 WR4(sc, FEC_MRBR_REG, maxfl << FEC_MRBR_R_BUF_SIZE_SHIFT); 1195 1196 /* 1197 * FTRL - Frame truncation length. 1198 * 1199 * Must be greater than or equal to the value set in FEC_RCR_MAXFL. 1200 */ 1201 WR4(sc, FEC_FTRL_REG, maxfl); 1202 1203 /* 1204 * RDSR / TDSR descriptor ring pointers. 1205 * 1206 * When we turn on ECR_ETHEREN at the end, the hardware zeroes its 1207 * internal current descriptor index values for both rings, so we zero 1208 * our index values as well. 1209 */ 1210 sc->rx_idx = 0; 1211 sc->tx_idx_head = sc->tx_idx_tail = 0; 1212 sc->txcount = 0; 1213 WR4(sc, FEC_RDSR_REG, sc->rxdesc_ring_paddr); 1214 WR4(sc, FEC_TDSR_REG, sc->txdesc_ring_paddr); 1215 1216 /* 1217 * EIM - interrupt mask register. 1218 * 1219 * We always enable the same set of interrupts while running; unlike 1220 * some drivers there's no need to change the mask on the fly depending 1221 * on what operations are in progress. 1222 */ 1223 WR4(sc, FEC_IEM_REG, FEC_IER_TXF | FEC_IER_RXF | FEC_IER_EBERR); 1224 1225 /* 1226 * MIBC - MIB control (hardware stats); clear all statistics regs, then 1227 * enable collection of statistics. 1228 */ 1229 regval = RD4(sc, FEC_MIBC_REG); 1230 WR4(sc, FEC_MIBC_REG, regval | FEC_MIBC_DIS); 1231 ffec_clear_stats(sc); 1232 WR4(sc, FEC_MIBC_REG, regval & ~FEC_MIBC_DIS); 1233 1234 if (sc->fecflags & FECFLAG_RACC) { 1235 /* 1236 * RACC - Receive Accelerator Function Configuration. 1237 */ 1238 regval = RD4(sc, FEC_RACC_REG); 1239 WR4(sc, FEC_RACC_REG, regval | FEC_RACC_SHIFT16); 1240 } 1241 1242 /* 1243 * ECR - Ethernet control register. 1244 * 1245 * This must happen after all the other config registers are set. If 1246 * we're running on little-endian hardware, also set the flag for byte- 1247 * swapping descriptor ring entries. This flag doesn't exist on older 1248 * hardware, but it can be safely set -- the bit position it occupies 1249 * was unused. 1250 */ 1251 regval = RD4(sc, FEC_ECR_REG); 1252 #if _BYTE_ORDER == _LITTLE_ENDIAN 1253 regval |= FEC_ECR_DBSWP; 1254 #endif 1255 regval |= FEC_ECR_ETHEREN; 1256 WR4(sc, FEC_ECR_REG, regval); 1257 1258 if_setdrvflagbits(ifp, IFF_DRV_RUNNING, 0); 1259 1260 /* 1261 * Call mii_mediachg() which will call back into ffec_miibus_statchg() to 1262 * set up the remaining config registers based on the current media. 1263 */ 1264 mii_mediachg(sc->mii_softc); 1265 callout_reset(&sc->ffec_callout, hz, ffec_tick, sc); 1266 1267 /* 1268 * Tell the hardware that receive buffers are available. They were made 1269 * available in ffec_attach() or ffec_stop(). 1270 */ 1271 WR4(sc, FEC_RDAR_REG, FEC_RDAR_RDAR); 1272 } 1273 1274 static void 1275 ffec_init(void *if_softc) 1276 { 1277 struct ffec_softc *sc = if_softc; 1278 1279 FFEC_LOCK(sc); 1280 ffec_init_locked(sc); 1281 FFEC_UNLOCK(sc); 1282 } 1283 1284 static void 1285 ffec_intr(void *arg) 1286 { 1287 struct ffec_softc *sc; 1288 uint32_t ier; 1289 1290 sc = arg; 1291 1292 FFEC_LOCK(sc); 1293 1294 ier = RD4(sc, FEC_IER_REG); 1295 1296 if (ier & FEC_IER_TXF) { 1297 WR4(sc, FEC_IER_REG, FEC_IER_TXF); 1298 ffec_txfinish_locked(sc); 1299 } 1300 1301 if (ier & FEC_IER_RXF) { 1302 WR4(sc, FEC_IER_REG, FEC_IER_RXF); 1303 ffec_rxfinish_locked(sc); 1304 } 1305 1306 /* 1307 * We actually don't care about most errors, because the hardware copes 1308 * with them just fine, discarding the incoming bad frame, or forcing a 1309 * bad CRC onto an outgoing bad frame, and counting the errors in the 1310 * stats registers. The one that really matters is EBERR (DMA bus 1311 * error) because the hardware automatically clears ECR[ETHEREN] and we 1312 * have to restart it here. It should never happen. 1313 */ 1314 if (ier & FEC_IER_EBERR) { 1315 WR4(sc, FEC_IER_REG, FEC_IER_EBERR); 1316 device_printf(sc->dev, 1317 "Ethernet DMA error, restarting controller.\n"); 1318 ffec_stop_locked(sc); 1319 ffec_init_locked(sc); 1320 } 1321 1322 FFEC_UNLOCK(sc); 1323 1324 } 1325 1326 static int 1327 ffec_ioctl(if_t ifp, u_long cmd, caddr_t data) 1328 { 1329 struct ffec_softc *sc; 1330 struct mii_data *mii; 1331 struct ifreq *ifr; 1332 int mask, error; 1333 1334 sc = if_getsoftc(ifp); 1335 ifr = (struct ifreq *)data; 1336 1337 error = 0; 1338 switch (cmd) { 1339 case SIOCSIFFLAGS: 1340 FFEC_LOCK(sc); 1341 if (if_getflags(ifp) & IFF_UP) { 1342 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 1343 if ((if_getflags(ifp) ^ sc->if_flags) & 1344 (IFF_PROMISC | IFF_ALLMULTI)) 1345 ffec_setup_rxfilter(sc); 1346 } else { 1347 if (!sc->is_detaching) 1348 ffec_init_locked(sc); 1349 } 1350 } else { 1351 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) 1352 ffec_stop_locked(sc); 1353 } 1354 sc->if_flags = if_getflags(ifp); 1355 FFEC_UNLOCK(sc); 1356 break; 1357 1358 case SIOCADDMULTI: 1359 case SIOCDELMULTI: 1360 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 1361 FFEC_LOCK(sc); 1362 ffec_setup_rxfilter(sc); 1363 FFEC_UNLOCK(sc); 1364 } 1365 break; 1366 1367 case SIOCSIFMEDIA: 1368 case SIOCGIFMEDIA: 1369 mii = sc->mii_softc; 1370 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd); 1371 break; 1372 1373 case SIOCSIFCAP: 1374 mask = if_getcapenable(ifp) ^ ifr->ifr_reqcap; 1375 if (mask & IFCAP_VLAN_MTU) { 1376 /* No work to do except acknowledge the change took. */ 1377 if_togglecapenable(ifp, IFCAP_VLAN_MTU); 1378 } 1379 break; 1380 1381 default: 1382 error = ether_ioctl(ifp, cmd, data); 1383 break; 1384 } 1385 1386 return (error); 1387 } 1388 1389 static int 1390 ffec_detach(device_t dev) 1391 { 1392 struct ffec_softc *sc; 1393 bus_dmamap_t map; 1394 int idx, irq; 1395 1396 /* 1397 * NB: This function can be called internally to unwind a failure to 1398 * attach. Make sure a resource got allocated/created before destroying. 1399 */ 1400 1401 sc = device_get_softc(dev); 1402 1403 if (sc->is_attached) { 1404 FFEC_LOCK(sc); 1405 sc->is_detaching = true; 1406 ffec_stop_locked(sc); 1407 FFEC_UNLOCK(sc); 1408 callout_drain(&sc->ffec_callout); 1409 ether_ifdetach(sc->ifp); 1410 } 1411 1412 /* XXX no miibus detach? */ 1413 1414 /* Clean up RX DMA resources and free mbufs. */ 1415 for (idx = 0; idx < RX_DESC_COUNT; ++idx) { 1416 if ((map = sc->rxbuf_map[idx].map) != NULL) { 1417 bus_dmamap_unload(sc->rxbuf_tag, map); 1418 bus_dmamap_destroy(sc->rxbuf_tag, map); 1419 m_freem(sc->rxbuf_map[idx].mbuf); 1420 } 1421 } 1422 if (sc->rxbuf_tag != NULL) 1423 bus_dma_tag_destroy(sc->rxbuf_tag); 1424 if (sc->rxdesc_map != NULL) { 1425 bus_dmamap_unload(sc->rxdesc_tag, sc->rxdesc_map); 1426 bus_dmamem_free(sc->rxdesc_tag, sc->rxdesc_ring, 1427 sc->rxdesc_map); 1428 } 1429 if (sc->rxdesc_tag != NULL) 1430 bus_dma_tag_destroy(sc->rxdesc_tag); 1431 1432 /* Clean up TX DMA resources. */ 1433 for (idx = 0; idx < TX_DESC_COUNT; ++idx) { 1434 if ((map = sc->txbuf_map[idx].map) != NULL) { 1435 /* TX maps are already unloaded. */ 1436 bus_dmamap_destroy(sc->txbuf_tag, map); 1437 } 1438 } 1439 if (sc->txbuf_tag != NULL) 1440 bus_dma_tag_destroy(sc->txbuf_tag); 1441 if (sc->txdesc_map != NULL) { 1442 bus_dmamap_unload(sc->txdesc_tag, sc->txdesc_map); 1443 bus_dmamem_free(sc->txdesc_tag, sc->txdesc_ring, 1444 sc->txdesc_map); 1445 } 1446 if (sc->txdesc_tag != NULL) 1447 bus_dma_tag_destroy(sc->txdesc_tag); 1448 1449 /* Release bus resources. */ 1450 for (irq = 0; irq < MAX_IRQ_COUNT; ++irq) { 1451 if (sc->intr_cookie[irq] != NULL) { 1452 bus_teardown_intr(dev, sc->irq_res[irq], 1453 sc->intr_cookie[irq]); 1454 } 1455 } 1456 bus_release_resources(dev, irq_res_spec, sc->irq_res); 1457 1458 if (sc->mem_res != NULL) 1459 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->mem_res); 1460 1461 FFEC_LOCK_DESTROY(sc); 1462 return (0); 1463 } 1464 1465 static int 1466 ffec_attach(device_t dev) 1467 { 1468 struct ffec_softc *sc; 1469 if_t ifp = NULL; 1470 struct mbuf *m; 1471 void *dummy; 1472 uintptr_t typeflags; 1473 phandle_t ofw_node; 1474 uint32_t idx, mscr; 1475 int error, phynum, rid, irq; 1476 uint8_t eaddr[ETHER_ADDR_LEN]; 1477 1478 sc = device_get_softc(dev); 1479 sc->dev = dev; 1480 1481 FFEC_LOCK_INIT(sc); 1482 1483 /* 1484 * There are differences in the implementation and features of the FEC 1485 * hardware on different SoCs, so figure out what type we are. 1486 */ 1487 typeflags = ofw_bus_search_compatible(dev, compat_data)->ocd_data; 1488 sc->fectype = (uint8_t)(typeflags & FECTYPE_MASK); 1489 sc->fecflags = (uint32_t)(typeflags & ~FECTYPE_MASK); 1490 1491 if (sc->fecflags & FECFLAG_AVB) { 1492 sc->rxbuf_align = 64; 1493 sc->txbuf_align = 1; 1494 } else { 1495 sc->rxbuf_align = 16; 1496 sc->txbuf_align = 16; 1497 } 1498 1499 /* 1500 * We have to be told what kind of electrical connection exists between 1501 * the MAC and PHY or we can't operate correctly. 1502 */ 1503 if ((ofw_node = ofw_bus_get_node(dev)) == -1) { 1504 device_printf(dev, "Impossible: Can't find ofw bus node\n"); 1505 error = ENXIO; 1506 goto out; 1507 } 1508 sc->phy_conn_type = mii_fdt_get_contype(ofw_node); 1509 if (sc->phy_conn_type == MII_CONTYPE_UNKNOWN) { 1510 device_printf(sc->dev, "No valid 'phy-mode' " 1511 "property found in FDT data for device.\n"); 1512 error = ENOATTR; 1513 goto out; 1514 } 1515 1516 callout_init_mtx(&sc->ffec_callout, &sc->mtx, 0); 1517 1518 /* Allocate bus resources for accessing the hardware. */ 1519 rid = 0; 1520 sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 1521 RF_ACTIVE); 1522 if (sc->mem_res == NULL) { 1523 device_printf(dev, "could not allocate memory resources.\n"); 1524 error = ENOMEM; 1525 goto out; 1526 } 1527 1528 error = bus_alloc_resources(dev, irq_res_spec, sc->irq_res); 1529 if (error != 0) { 1530 device_printf(dev, "could not allocate interrupt resources\n"); 1531 goto out; 1532 } 1533 1534 /* 1535 * Set up TX descriptor ring, descriptors, and dma maps. 1536 */ 1537 error = bus_dma_tag_create( 1538 bus_get_dma_tag(dev), /* Parent tag. */ 1539 FEC_DESC_RING_ALIGN, 0, /* alignment, boundary */ 1540 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 1541 BUS_SPACE_MAXADDR, /* highaddr */ 1542 NULL, NULL, /* filter, filterarg */ 1543 TX_DESC_SIZE, 1, /* maxsize, nsegments */ 1544 TX_DESC_SIZE, /* maxsegsize */ 1545 0, /* flags */ 1546 NULL, NULL, /* lockfunc, lockarg */ 1547 &sc->txdesc_tag); 1548 if (error != 0) { 1549 device_printf(sc->dev, 1550 "could not create TX ring DMA tag.\n"); 1551 goto out; 1552 } 1553 1554 error = bus_dmamem_alloc(sc->txdesc_tag, (void**)&sc->txdesc_ring, 1555 BUS_DMA_COHERENT | BUS_DMA_WAITOK | BUS_DMA_ZERO, &sc->txdesc_map); 1556 if (error != 0) { 1557 device_printf(sc->dev, 1558 "could not allocate TX descriptor ring.\n"); 1559 goto out; 1560 } 1561 1562 error = bus_dmamap_load(sc->txdesc_tag, sc->txdesc_map, sc->txdesc_ring, 1563 TX_DESC_SIZE, ffec_get1paddr, &sc->txdesc_ring_paddr, 0); 1564 if (error != 0) { 1565 device_printf(sc->dev, 1566 "could not load TX descriptor ring map.\n"); 1567 goto out; 1568 } 1569 1570 error = bus_dma_tag_create( 1571 bus_get_dma_tag(dev), /* Parent tag. */ 1572 sc->txbuf_align, 0, /* alignment, boundary */ 1573 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 1574 BUS_SPACE_MAXADDR, /* highaddr */ 1575 NULL, NULL, /* filter, filterarg */ 1576 MCLBYTES, 1, /* maxsize, nsegments */ 1577 MCLBYTES, /* maxsegsize */ 1578 0, /* flags */ 1579 NULL, NULL, /* lockfunc, lockarg */ 1580 &sc->txbuf_tag); 1581 if (error != 0) { 1582 device_printf(sc->dev, 1583 "could not create TX ring DMA tag.\n"); 1584 goto out; 1585 } 1586 1587 for (idx = 0; idx < TX_DESC_COUNT; ++idx) { 1588 error = bus_dmamap_create(sc->txbuf_tag, 0, 1589 &sc->txbuf_map[idx].map); 1590 if (error != 0) { 1591 device_printf(sc->dev, 1592 "could not create TX buffer DMA map.\n"); 1593 goto out; 1594 } 1595 ffec_setup_txdesc(sc, idx, 0, 0); 1596 } 1597 1598 /* 1599 * Set up RX descriptor ring, descriptors, dma maps, and mbufs. 1600 */ 1601 error = bus_dma_tag_create( 1602 bus_get_dma_tag(dev), /* Parent tag. */ 1603 FEC_DESC_RING_ALIGN, 0, /* alignment, boundary */ 1604 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 1605 BUS_SPACE_MAXADDR, /* highaddr */ 1606 NULL, NULL, /* filter, filterarg */ 1607 RX_DESC_SIZE, 1, /* maxsize, nsegments */ 1608 RX_DESC_SIZE, /* maxsegsize */ 1609 0, /* flags */ 1610 NULL, NULL, /* lockfunc, lockarg */ 1611 &sc->rxdesc_tag); 1612 if (error != 0) { 1613 device_printf(sc->dev, 1614 "could not create RX ring DMA tag.\n"); 1615 goto out; 1616 } 1617 1618 error = bus_dmamem_alloc(sc->rxdesc_tag, (void **)&sc->rxdesc_ring, 1619 BUS_DMA_COHERENT | BUS_DMA_WAITOK | BUS_DMA_ZERO, &sc->rxdesc_map); 1620 if (error != 0) { 1621 device_printf(sc->dev, 1622 "could not allocate RX descriptor ring.\n"); 1623 goto out; 1624 } 1625 1626 error = bus_dmamap_load(sc->rxdesc_tag, sc->rxdesc_map, sc->rxdesc_ring, 1627 RX_DESC_SIZE, ffec_get1paddr, &sc->rxdesc_ring_paddr, 0); 1628 if (error != 0) { 1629 device_printf(sc->dev, 1630 "could not load RX descriptor ring map.\n"); 1631 goto out; 1632 } 1633 1634 error = bus_dma_tag_create( 1635 bus_get_dma_tag(dev), /* Parent tag. */ 1636 1, 0, /* alignment, boundary */ 1637 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 1638 BUS_SPACE_MAXADDR, /* highaddr */ 1639 NULL, NULL, /* filter, filterarg */ 1640 MCLBYTES, 1, /* maxsize, nsegments */ 1641 MCLBYTES, /* maxsegsize */ 1642 0, /* flags */ 1643 NULL, NULL, /* lockfunc, lockarg */ 1644 &sc->rxbuf_tag); 1645 if (error != 0) { 1646 device_printf(sc->dev, 1647 "could not create RX buf DMA tag.\n"); 1648 goto out; 1649 } 1650 1651 for (idx = 0; idx < RX_DESC_COUNT; ++idx) { 1652 error = bus_dmamap_create(sc->rxbuf_tag, 0, 1653 &sc->rxbuf_map[idx].map); 1654 if (error != 0) { 1655 device_printf(sc->dev, 1656 "could not create RX buffer DMA map.\n"); 1657 goto out; 1658 } 1659 if ((m = ffec_alloc_mbufcl(sc)) == NULL) { 1660 device_printf(dev, "Could not alloc mbuf\n"); 1661 error = ENOMEM; 1662 goto out; 1663 } 1664 if ((error = ffec_setup_rxbuf(sc, idx, m)) != 0) { 1665 device_printf(sc->dev, 1666 "could not create new RX buffer.\n"); 1667 goto out; 1668 } 1669 } 1670 1671 /* Try to get the MAC address from the hardware before resetting it. */ 1672 ffec_get_hwaddr(sc, eaddr); 1673 1674 /* 1675 * Reset the hardware. Disables all interrupts. 1676 * 1677 * When the FEC is connected to the AXI bus (indicated by AVB flag), a 1678 * MAC reset while a bus transaction is pending can hang the bus. 1679 * Instead of resetting, turn off the ENABLE bit, which allows the 1680 * hardware to complete any in-progress transfers (appending a bad CRC 1681 * to any partial packet) and release the AXI bus. This could probably 1682 * be done unconditionally for all hardware variants, but that hasn't 1683 * been tested. 1684 */ 1685 if (sc->fecflags & FECFLAG_AVB) 1686 WR4(sc, FEC_ECR_REG, 0); 1687 else 1688 WR4(sc, FEC_ECR_REG, FEC_ECR_RESET); 1689 1690 /* Setup interrupt handler. */ 1691 for (irq = 0; irq < MAX_IRQ_COUNT; ++irq) { 1692 if (sc->irq_res[irq] != NULL) { 1693 error = bus_setup_intr(dev, sc->irq_res[irq], 1694 INTR_TYPE_NET | INTR_MPSAFE, NULL, ffec_intr, sc, 1695 &sc->intr_cookie[irq]); 1696 if (error != 0) { 1697 device_printf(dev, 1698 "could not setup interrupt handler.\n"); 1699 goto out; 1700 } 1701 } 1702 } 1703 1704 /* 1705 * Set up the PHY control register. 1706 * 1707 * Speed formula for ENET is md_clock = mac_clock / ((N + 1) * 2). 1708 * Speed formula for FEC is md_clock = mac_clock / (N * 2) 1709 * 1710 * XXX - Revisit this... 1711 * 1712 * For a Wandboard imx6 (ENET) I was originally using 4, but the uboot 1713 * code uses 10. Both values seem to work, but I suspect many modern 1714 * PHY parts can do mdio at speeds far above the standard 2.5 MHz. 1715 * 1716 * Different imx manuals use confusingly different terminology (things 1717 * like "system clock" and "internal module clock") with examples that 1718 * use frequencies that have nothing to do with ethernet, giving the 1719 * vague impression that maybe the clock in question is the periphclock 1720 * or something. In fact, on an imx53 development board (FEC), 1721 * measuring the mdio clock at the pin on the PHY and playing with 1722 * various divisors showed that the root speed was 66 MHz (clk_ipg_root 1723 * aka periphclock) and 13 was the right divisor. 1724 * 1725 * All in all, it seems likely that 13 is a safe divisor for now, 1726 * because if we really do need to base it on the peripheral clock 1727 * speed, then we need a platform-independent get-clock-freq API. 1728 */ 1729 mscr = 13 << FEC_MSCR_MII_SPEED_SHIFT; 1730 if (OF_hasprop(ofw_node, "phy-disable-preamble")) { 1731 mscr |= FEC_MSCR_DIS_PRE; 1732 if (bootverbose) 1733 device_printf(dev, "PHY preamble disabled\n"); 1734 } 1735 WR4(sc, FEC_MSCR_REG, mscr); 1736 1737 /* Set up the ethernet interface. */ 1738 sc->ifp = ifp = if_alloc(IFT_ETHER); 1739 1740 if_setsoftc(ifp, sc); 1741 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1742 if_setflags(ifp, IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST); 1743 if_setcapabilities(ifp, IFCAP_VLAN_MTU); 1744 if_setcapenable(ifp, if_getcapabilities(ifp)); 1745 if_setstartfn(ifp, ffec_txstart); 1746 if_setioctlfn(ifp, ffec_ioctl); 1747 if_setinitfn(ifp, ffec_init); 1748 if_setsendqlen(ifp, TX_DESC_COUNT - 1); 1749 if_setsendqready(ifp); 1750 if_setifheaderlen(ifp, sizeof(struct ether_vlan_header)); 1751 1752 #if 0 /* XXX The hardware keeps stats we could use for these. */ 1753 if_setlinkmib(ifp, &sc->mibdata); 1754 if_setlinkmiblen(ifp, sizeof(sc->mibdata)); 1755 #endif 1756 1757 /* Set up the miigasket hardware (if any). */ 1758 ffec_miigasket_setup(sc); 1759 1760 /* Attach the mii driver. */ 1761 if (fdt_get_phyaddr(ofw_node, dev, &phynum, &dummy) != 0) { 1762 phynum = MII_PHY_ANY; 1763 } 1764 error = mii_attach(dev, &sc->miibus, ifp, ffec_media_change, 1765 ffec_media_status, BMSR_DEFCAPMASK, phynum, MII_OFFSET_ANY, 1766 (sc->fecflags & FECTYPE_MVF) ? MIIF_FORCEANEG : 0); 1767 if (error != 0) { 1768 device_printf(dev, "PHY attach failed\n"); 1769 goto out; 1770 } 1771 sc->mii_softc = device_get_softc(sc->miibus); 1772 1773 /* All ready to run, attach the ethernet interface. */ 1774 ether_ifattach(ifp, eaddr); 1775 sc->is_attached = true; 1776 1777 error = 0; 1778 out: 1779 1780 if (error != 0) 1781 ffec_detach(dev); 1782 1783 return (error); 1784 } 1785 1786 static int 1787 ffec_probe(device_t dev) 1788 { 1789 uintptr_t fectype; 1790 1791 if (!ofw_bus_status_okay(dev)) 1792 return (ENXIO); 1793 1794 fectype = ofw_bus_search_compatible(dev, compat_data)->ocd_data; 1795 if (fectype == FECTYPE_NONE) 1796 return (ENXIO); 1797 1798 device_set_desc(dev, (fectype & FECFLAG_GBE) ? 1799 "Freescale Gigabit Ethernet Controller" : 1800 "Freescale Fast Ethernet Controller"); 1801 1802 return (BUS_PROBE_DEFAULT); 1803 } 1804 1805 1806 static device_method_t ffec_methods[] = { 1807 /* Device interface. */ 1808 DEVMETHOD(device_probe, ffec_probe), 1809 DEVMETHOD(device_attach, ffec_attach), 1810 DEVMETHOD(device_detach, ffec_detach), 1811 1812 /* 1813 DEVMETHOD(device_shutdown, ffec_shutdown), 1814 DEVMETHOD(device_suspend, ffec_suspend), 1815 DEVMETHOD(device_resume, ffec_resume), 1816 */ 1817 1818 /* MII interface. */ 1819 DEVMETHOD(miibus_readreg, ffec_miibus_readreg), 1820 DEVMETHOD(miibus_writereg, ffec_miibus_writereg), 1821 DEVMETHOD(miibus_statchg, ffec_miibus_statchg), 1822 1823 DEVMETHOD_END 1824 }; 1825 1826 static driver_t ffec_driver = { 1827 "ffec", 1828 ffec_methods, 1829 sizeof(struct ffec_softc) 1830 }; 1831 1832 DRIVER_MODULE(ffec, simplebus, ffec_driver, 0, 0); 1833 DRIVER_MODULE(miibus, ffec, miibus_driver, 0, 0); 1834 1835 MODULE_DEPEND(ffec, ether, 1, 1, 1); 1836 MODULE_DEPEND(ffec, miibus, 1, 1, 1); 1837