1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2013 Ian Lepore <ian@freebsd.org> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 * 28 */ 29 30 #include <sys/cdefs.h> 31 /* 32 * Driver for Freescale Fast Ethernet Controller, found on imx-series SoCs among 33 * others. Also works for the ENET Gigibit controller found on imx6 and imx28, 34 * but the driver doesn't currently use any of the ENET advanced features other 35 * than enabling gigabit. 36 * 37 * The interface name 'fec' is already taken by netgraph's Fast Etherchannel 38 * (netgraph/ng_fec.c), so we use 'ffec'. 39 * 40 * Requires an FDT entry with at least these properties: 41 * fec: ethernet@02188000 { 42 * compatible = "fsl,imxNN-fec"; 43 * reg = <0x02188000 0x4000>; 44 * interrupts = <150 151>; 45 * phy-mode = "rgmii"; 46 * phy-disable-preamble; // optional 47 * }; 48 * The second interrupt number is for IEEE-1588, and is not currently used; it 49 * need not be present. phy-mode must be one of: "mii", "rmii", "rgmii". 50 * There is also an optional property, phy-disable-preamble, which if present 51 * will disable the preamble bits, cutting the size of each mdio transaction 52 * (and thus the busy-wait time) in half. 53 */ 54 55 #include <sys/param.h> 56 #include <sys/systm.h> 57 #include <sys/bus.h> 58 #include <sys/endian.h> 59 #include <sys/kernel.h> 60 #include <sys/lock.h> 61 #include <sys/malloc.h> 62 #include <sys/mbuf.h> 63 #include <sys/module.h> 64 #include <sys/mutex.h> 65 #include <sys/rman.h> 66 #include <sys/socket.h> 67 #include <sys/sockio.h> 68 #include <sys/sysctl.h> 69 70 #include <machine/bus.h> 71 72 #include <net/bpf.h> 73 #include <net/if.h> 74 #include <net/ethernet.h> 75 #include <net/if_dl.h> 76 #include <net/if_media.h> 77 #include <net/if_types.h> 78 #include <net/if_var.h> 79 #include <net/if_vlan_var.h> 80 81 #include <dev/fdt/fdt_common.h> 82 #include <dev/ffec/if_ffecreg.h> 83 #include <dev/ofw/ofw_bus.h> 84 #include <dev/ofw/ofw_bus_subr.h> 85 #include <dev/mii/mii.h> 86 #include <dev/mii/miivar.h> 87 #include <dev/mii/mii_fdt.h> 88 #include "miibus_if.h" 89 90 /* 91 * There are small differences in the hardware on various SoCs. Not every SoC 92 * we support has its own FECTYPE; most work as GENERIC and only the ones that 93 * need different handling get their own entry. In addition to the types in 94 * this list, there are some flags below that can be ORed into the upper bits. 95 */ 96 enum { 97 FECTYPE_NONE, 98 FECTYPE_GENERIC, 99 FECTYPE_IMX53, 100 FECTYPE_IMX6, /* imx6 and imx7 */ 101 FECTYPE_MVF, 102 }; 103 104 /* 105 * Flags that describe general differences between the FEC hardware in various 106 * SoCs. These are ORed into the FECTYPE enum values in the ofw_compat_data, so 107 * the low 8 bits are reserved for the type enum. In the softc, the type and 108 * flags are put into separate members, so that you don't need to mask the flags 109 * out of the type to compare it. 110 */ 111 #define FECTYPE_MASK 0x000000ff 112 #define FECFLAG_GBE (1 << 8) 113 #define FECFLAG_AVB (1 << 9) 114 #define FECFLAG_RACC (1 << 10) 115 116 /* 117 * Table of supported FDT compat strings and their associated FECTYPE values. 118 */ 119 static struct ofw_compat_data compat_data[] = { 120 {"fsl,imx51-fec", FECTYPE_GENERIC}, 121 {"fsl,imx53-fec", FECTYPE_IMX53}, 122 {"fsl,imx6q-fec", FECTYPE_IMX6 | FECFLAG_RACC | FECFLAG_GBE }, 123 {"fsl,imx6ul-fec", FECTYPE_IMX6 | FECFLAG_RACC }, 124 {"fsl,imx6sx-fec", FECTYPE_IMX6 | FECFLAG_RACC | FECFLAG_GBE | 125 FECFLAG_AVB }, 126 {"fsl,imx7d-fec", FECTYPE_IMX6 | FECFLAG_RACC | FECFLAG_GBE | 127 FECFLAG_AVB }, 128 {"fsl,mvf600-fec", FECTYPE_MVF | FECFLAG_RACC }, 129 {"fsl,mvf-fec", FECTYPE_MVF}, 130 {NULL, FECTYPE_NONE}, 131 }; 132 133 /* 134 * Driver data and defines. 135 */ 136 #define RX_DESC_COUNT 64 137 #define RX_DESC_SIZE (sizeof(struct ffec_hwdesc) * RX_DESC_COUNT) 138 #define TX_DESC_COUNT 64 139 #define TX_DESC_SIZE (sizeof(struct ffec_hwdesc) * TX_DESC_COUNT) 140 141 #define WATCHDOG_TIMEOUT_SECS 5 142 143 #define MAX_IRQ_COUNT 3 144 145 struct ffec_bufmap { 146 struct mbuf *mbuf; 147 bus_dmamap_t map; 148 }; 149 150 struct ffec_softc { 151 device_t dev; 152 device_t miibus; 153 struct mii_data * mii_softc; 154 if_t ifp; 155 int if_flags; 156 struct mtx mtx; 157 struct resource *irq_res[MAX_IRQ_COUNT]; 158 struct resource *mem_res; 159 void * intr_cookie[MAX_IRQ_COUNT]; 160 struct callout ffec_callout; 161 mii_contype_t phy_conn_type; 162 uint32_t fecflags; 163 uint8_t fectype; 164 boolean_t link_is_up; 165 boolean_t is_attached; 166 boolean_t is_detaching; 167 int tx_watchdog_count; 168 int rxbuf_align; 169 int txbuf_align; 170 171 bus_dma_tag_t rxdesc_tag; 172 bus_dmamap_t rxdesc_map; 173 struct ffec_hwdesc *rxdesc_ring; 174 bus_addr_t rxdesc_ring_paddr; 175 bus_dma_tag_t rxbuf_tag; 176 struct ffec_bufmap rxbuf_map[RX_DESC_COUNT]; 177 uint32_t rx_idx; 178 179 bus_dma_tag_t txdesc_tag; 180 bus_dmamap_t txdesc_map; 181 struct ffec_hwdesc *txdesc_ring; 182 bus_addr_t txdesc_ring_paddr; 183 bus_dma_tag_t txbuf_tag; 184 struct ffec_bufmap txbuf_map[TX_DESC_COUNT]; 185 uint32_t tx_idx_head; 186 uint32_t tx_idx_tail; 187 int txcount; 188 }; 189 190 static struct resource_spec irq_res_spec[MAX_IRQ_COUNT + 1] = { 191 { SYS_RES_IRQ, 0, RF_ACTIVE }, 192 { SYS_RES_IRQ, 1, RF_ACTIVE | RF_OPTIONAL }, 193 { SYS_RES_IRQ, 2, RF_ACTIVE | RF_OPTIONAL }, 194 RESOURCE_SPEC_END 195 }; 196 197 #define FFEC_LOCK(sc) mtx_lock(&(sc)->mtx) 198 #define FFEC_UNLOCK(sc) mtx_unlock(&(sc)->mtx) 199 #define FFEC_LOCK_INIT(sc) mtx_init(&(sc)->mtx, \ 200 device_get_nameunit((sc)->dev), MTX_NETWORK_LOCK, MTX_DEF) 201 #define FFEC_LOCK_DESTROY(sc) mtx_destroy(&(sc)->mtx); 202 #define FFEC_ASSERT_LOCKED(sc) mtx_assert(&(sc)->mtx, MA_OWNED); 203 #define FFEC_ASSERT_UNLOCKED(sc) mtx_assert(&(sc)->mtx, MA_NOTOWNED); 204 205 static void ffec_init_locked(struct ffec_softc *sc); 206 static void ffec_stop_locked(struct ffec_softc *sc); 207 static void ffec_txstart_locked(struct ffec_softc *sc); 208 static void ffec_txfinish_locked(struct ffec_softc *sc); 209 210 static inline uint16_t 211 RD2(struct ffec_softc *sc, bus_size_t off) 212 { 213 214 return (bus_read_2(sc->mem_res, off)); 215 } 216 217 static inline void 218 WR2(struct ffec_softc *sc, bus_size_t off, uint16_t val) 219 { 220 221 bus_write_2(sc->mem_res, off, val); 222 } 223 224 static inline uint32_t 225 RD4(struct ffec_softc *sc, bus_size_t off) 226 { 227 228 return (bus_read_4(sc->mem_res, off)); 229 } 230 231 static inline void 232 WR4(struct ffec_softc *sc, bus_size_t off, uint32_t val) 233 { 234 235 bus_write_4(sc->mem_res, off, val); 236 } 237 238 static inline uint32_t 239 next_rxidx(struct ffec_softc *sc, uint32_t curidx) 240 { 241 242 return ((curidx == RX_DESC_COUNT - 1) ? 0 : curidx + 1); 243 } 244 245 static inline uint32_t 246 next_txidx(struct ffec_softc *sc, uint32_t curidx) 247 { 248 249 return ((curidx == TX_DESC_COUNT - 1) ? 0 : curidx + 1); 250 } 251 252 static void 253 ffec_get1paddr(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 254 { 255 256 if (error != 0) 257 return; 258 *(bus_addr_t *)arg = segs[0].ds_addr; 259 } 260 261 static void 262 ffec_miigasket_setup(struct ffec_softc *sc) 263 { 264 uint32_t ifmode; 265 266 /* 267 * We only need the gasket for MII and RMII connections on certain SoCs. 268 */ 269 270 switch (sc->fectype) 271 { 272 case FECTYPE_IMX53: 273 break; 274 default: 275 return; 276 } 277 278 switch (sc->phy_conn_type) 279 { 280 case MII_CONTYPE_MII: 281 ifmode = 0; 282 break; 283 case MII_CONTYPE_RMII: 284 ifmode = FEC_MIIGSK_CFGR_IF_MODE_RMII; 285 break; 286 default: 287 return; 288 } 289 290 /* 291 * Disable the gasket, configure for either MII or RMII, then enable. 292 */ 293 294 WR2(sc, FEC_MIIGSK_ENR, 0); 295 while (RD2(sc, FEC_MIIGSK_ENR) & FEC_MIIGSK_ENR_READY) 296 continue; 297 298 WR2(sc, FEC_MIIGSK_CFGR, ifmode); 299 300 WR2(sc, FEC_MIIGSK_ENR, FEC_MIIGSK_ENR_EN); 301 while (!(RD2(sc, FEC_MIIGSK_ENR) & FEC_MIIGSK_ENR_READY)) 302 continue; 303 } 304 305 static boolean_t 306 ffec_miibus_iowait(struct ffec_softc *sc) 307 { 308 uint32_t timeout; 309 310 for (timeout = 10000; timeout != 0; --timeout) 311 if (RD4(sc, FEC_IER_REG) & FEC_IER_MII) 312 return (true); 313 314 return (false); 315 } 316 317 static int 318 ffec_miibus_readreg(device_t dev, int phy, int reg) 319 { 320 struct ffec_softc *sc; 321 int val; 322 323 sc = device_get_softc(dev); 324 325 WR4(sc, FEC_IER_REG, FEC_IER_MII); 326 327 WR4(sc, FEC_MMFR_REG, FEC_MMFR_OP_READ | 328 FEC_MMFR_ST_VALUE | FEC_MMFR_TA_VALUE | 329 ((phy << FEC_MMFR_PA_SHIFT) & FEC_MMFR_PA_MASK) | 330 ((reg << FEC_MMFR_RA_SHIFT) & FEC_MMFR_RA_MASK)); 331 332 if (!ffec_miibus_iowait(sc)) { 333 device_printf(dev, "timeout waiting for mii read\n"); 334 return (-1); /* All-ones is a symptom of bad mdio. */ 335 } 336 337 val = RD4(sc, FEC_MMFR_REG) & FEC_MMFR_DATA_MASK; 338 339 return (val); 340 } 341 342 static int 343 ffec_miibus_writereg(device_t dev, int phy, int reg, int val) 344 { 345 struct ffec_softc *sc; 346 347 sc = device_get_softc(dev); 348 349 WR4(sc, FEC_IER_REG, FEC_IER_MII); 350 351 WR4(sc, FEC_MMFR_REG, FEC_MMFR_OP_WRITE | 352 FEC_MMFR_ST_VALUE | FEC_MMFR_TA_VALUE | 353 ((phy << FEC_MMFR_PA_SHIFT) & FEC_MMFR_PA_MASK) | 354 ((reg << FEC_MMFR_RA_SHIFT) & FEC_MMFR_RA_MASK) | 355 (val & FEC_MMFR_DATA_MASK)); 356 357 if (!ffec_miibus_iowait(sc)) { 358 device_printf(dev, "timeout waiting for mii write\n"); 359 return (-1); 360 } 361 362 return (0); 363 } 364 365 static void 366 ffec_miibus_statchg(device_t dev) 367 { 368 struct ffec_softc *sc; 369 struct mii_data *mii; 370 uint32_t ecr, rcr, tcr; 371 372 /* 373 * Called by the MII bus driver when the PHY establishes link to set the 374 * MAC interface registers. 375 */ 376 377 sc = device_get_softc(dev); 378 379 FFEC_ASSERT_LOCKED(sc); 380 381 mii = sc->mii_softc; 382 383 if (mii->mii_media_status & IFM_ACTIVE) 384 sc->link_is_up = true; 385 else 386 sc->link_is_up = false; 387 388 ecr = RD4(sc, FEC_ECR_REG) & ~FEC_ECR_SPEED; 389 rcr = RD4(sc, FEC_RCR_REG) & ~(FEC_RCR_RMII_10T | FEC_RCR_RMII_MODE | 390 FEC_RCR_RGMII_EN | FEC_RCR_DRT | FEC_RCR_FCE); 391 tcr = RD4(sc, FEC_TCR_REG) & ~FEC_TCR_FDEN; 392 393 rcr |= FEC_RCR_MII_MODE; /* Must always be on even for R[G]MII. */ 394 switch (sc->phy_conn_type) { 395 case MII_CONTYPE_RMII: 396 rcr |= FEC_RCR_RMII_MODE; 397 break; 398 case MII_CONTYPE_RGMII: 399 case MII_CONTYPE_RGMII_ID: 400 case MII_CONTYPE_RGMII_RXID: 401 case MII_CONTYPE_RGMII_TXID: 402 rcr |= FEC_RCR_RGMII_EN; 403 break; 404 default: 405 break; 406 } 407 408 switch (IFM_SUBTYPE(mii->mii_media_active)) { 409 case IFM_1000_T: 410 case IFM_1000_SX: 411 ecr |= FEC_ECR_SPEED; 412 break; 413 case IFM_100_TX: 414 /* Not-FEC_ECR_SPEED + not-FEC_RCR_RMII_10T means 100TX */ 415 break; 416 case IFM_10_T: 417 rcr |= FEC_RCR_RMII_10T; 418 break; 419 case IFM_NONE: 420 sc->link_is_up = false; 421 return; 422 default: 423 sc->link_is_up = false; 424 device_printf(dev, "Unsupported media %u\n", 425 IFM_SUBTYPE(mii->mii_media_active)); 426 return; 427 } 428 429 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) 430 tcr |= FEC_TCR_FDEN; 431 else 432 rcr |= FEC_RCR_DRT; 433 434 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FLOW) != 0) 435 rcr |= FEC_RCR_FCE; 436 437 WR4(sc, FEC_RCR_REG, rcr); 438 WR4(sc, FEC_TCR_REG, tcr); 439 WR4(sc, FEC_ECR_REG, ecr); 440 } 441 442 static void 443 ffec_media_status(if_t ifp, struct ifmediareq *ifmr) 444 { 445 struct ffec_softc *sc; 446 struct mii_data *mii; 447 448 449 sc = if_getsoftc(ifp); 450 mii = sc->mii_softc; 451 FFEC_LOCK(sc); 452 mii_pollstat(mii); 453 ifmr->ifm_active = mii->mii_media_active; 454 ifmr->ifm_status = mii->mii_media_status; 455 FFEC_UNLOCK(sc); 456 } 457 458 static int 459 ffec_media_change_locked(struct ffec_softc *sc) 460 { 461 462 return (mii_mediachg(sc->mii_softc)); 463 } 464 465 static int 466 ffec_media_change(if_t ifp) 467 { 468 struct ffec_softc *sc; 469 int error; 470 471 sc = if_getsoftc(ifp); 472 473 FFEC_LOCK(sc); 474 error = ffec_media_change_locked(sc); 475 FFEC_UNLOCK(sc); 476 return (error); 477 } 478 479 static void ffec_clear_stats(struct ffec_softc *sc) 480 { 481 uint32_t mibc; 482 483 mibc = RD4(sc, FEC_MIBC_REG); 484 485 /* 486 * On newer hardware the statistic regs are cleared by toggling a bit in 487 * the mib control register. On older hardware the clear procedure is 488 * to disable statistics collection, zero the regs, then re-enable. 489 */ 490 if (sc->fectype == FECTYPE_IMX6 || sc->fectype == FECTYPE_MVF) { 491 WR4(sc, FEC_MIBC_REG, mibc | FEC_MIBC_CLEAR); 492 WR4(sc, FEC_MIBC_REG, mibc & ~FEC_MIBC_CLEAR); 493 } else { 494 WR4(sc, FEC_MIBC_REG, mibc | FEC_MIBC_DIS); 495 496 WR4(sc, FEC_IEEE_R_DROP, 0); 497 WR4(sc, FEC_IEEE_R_MACERR, 0); 498 WR4(sc, FEC_RMON_R_CRC_ALIGN, 0); 499 WR4(sc, FEC_RMON_R_FRAG, 0); 500 WR4(sc, FEC_RMON_R_JAB, 0); 501 WR4(sc, FEC_RMON_R_MC_PKT, 0); 502 WR4(sc, FEC_RMON_R_OVERSIZE, 0); 503 WR4(sc, FEC_RMON_R_PACKETS, 0); 504 WR4(sc, FEC_RMON_R_UNDERSIZE, 0); 505 WR4(sc, FEC_RMON_T_COL, 0); 506 WR4(sc, FEC_RMON_T_CRC_ALIGN, 0); 507 WR4(sc, FEC_RMON_T_FRAG, 0); 508 WR4(sc, FEC_RMON_T_JAB, 0); 509 WR4(sc, FEC_RMON_T_MC_PKT, 0); 510 WR4(sc, FEC_RMON_T_OVERSIZE , 0); 511 WR4(sc, FEC_RMON_T_PACKETS, 0); 512 WR4(sc, FEC_RMON_T_UNDERSIZE, 0); 513 514 WR4(sc, FEC_MIBC_REG, mibc); 515 } 516 } 517 518 static void 519 ffec_harvest_stats(struct ffec_softc *sc) 520 { 521 if_t ifp; 522 523 ifp = sc->ifp; 524 525 /* 526 * - FEC_IEEE_R_DROP is "dropped due to invalid start frame delimiter" 527 * so it's really just another type of input error. 528 * - FEC_IEEE_R_MACERR is "no receive fifo space"; count as input drops. 529 */ 530 if_inc_counter(ifp, IFCOUNTER_IPACKETS, RD4(sc, FEC_RMON_R_PACKETS)); 531 if_inc_counter(ifp, IFCOUNTER_IMCASTS, RD4(sc, FEC_RMON_R_MC_PKT)); 532 if_inc_counter(ifp, IFCOUNTER_IERRORS, 533 RD4(sc, FEC_RMON_R_CRC_ALIGN) + RD4(sc, FEC_RMON_R_UNDERSIZE) + 534 RD4(sc, FEC_RMON_R_OVERSIZE) + RD4(sc, FEC_RMON_R_FRAG) + 535 RD4(sc, FEC_RMON_R_JAB) + RD4(sc, FEC_IEEE_R_DROP)); 536 537 if_inc_counter(ifp, IFCOUNTER_IQDROPS, RD4(sc, FEC_IEEE_R_MACERR)); 538 539 if_inc_counter(ifp, IFCOUNTER_OPACKETS, RD4(sc, FEC_RMON_T_PACKETS)); 540 if_inc_counter(ifp, IFCOUNTER_OMCASTS, RD4(sc, FEC_RMON_T_MC_PKT)); 541 if_inc_counter(ifp, IFCOUNTER_OERRORS, 542 RD4(sc, FEC_RMON_T_CRC_ALIGN) + RD4(sc, FEC_RMON_T_UNDERSIZE) + 543 RD4(sc, FEC_RMON_T_OVERSIZE) + RD4(sc, FEC_RMON_T_FRAG) + 544 RD4(sc, FEC_RMON_T_JAB)); 545 546 if_inc_counter(ifp, IFCOUNTER_COLLISIONS, RD4(sc, FEC_RMON_T_COL)); 547 548 ffec_clear_stats(sc); 549 } 550 551 static void 552 ffec_tick(void *arg) 553 { 554 struct ffec_softc *sc; 555 if_t ifp; 556 int link_was_up; 557 558 sc = arg; 559 560 FFEC_ASSERT_LOCKED(sc); 561 562 ifp = sc->ifp; 563 564 if (!(if_getdrvflags(ifp) & IFF_DRV_RUNNING)) 565 return; 566 567 /* 568 * Typical tx watchdog. If this fires it indicates that we enqueued 569 * packets for output and never got a txdone interrupt for them. Maybe 570 * it's a missed interrupt somehow, just pretend we got one. 571 */ 572 if (sc->tx_watchdog_count > 0) { 573 if (--sc->tx_watchdog_count == 0) { 574 ffec_txfinish_locked(sc); 575 } 576 } 577 578 /* Gather stats from hardware counters. */ 579 ffec_harvest_stats(sc); 580 581 /* Check the media status. */ 582 link_was_up = sc->link_is_up; 583 mii_tick(sc->mii_softc); 584 if (sc->link_is_up && !link_was_up) 585 ffec_txstart_locked(sc); 586 587 /* Schedule another check one second from now. */ 588 callout_reset(&sc->ffec_callout, hz, ffec_tick, sc); 589 } 590 591 inline static uint32_t 592 ffec_setup_txdesc(struct ffec_softc *sc, int idx, bus_addr_t paddr, 593 uint32_t len) 594 { 595 uint32_t nidx; 596 uint32_t flags; 597 598 nidx = next_txidx(sc, idx); 599 600 /* Addr/len 0 means we're clearing the descriptor after xmit done. */ 601 if (paddr == 0 || len == 0) { 602 flags = 0; 603 --sc->txcount; 604 } else { 605 flags = FEC_TXDESC_READY | FEC_TXDESC_L | FEC_TXDESC_TC; 606 ++sc->txcount; 607 } 608 if (nidx == 0) 609 flags |= FEC_TXDESC_WRAP; 610 611 /* 612 * The hardware requires 32-bit physical addresses. We set up the dma 613 * tag to indicate that, so the cast to uint32_t should never lose 614 * significant bits. 615 */ 616 sc->txdesc_ring[idx].buf_paddr = (uint32_t)paddr; 617 sc->txdesc_ring[idx].flags_len = flags | len; /* Must be set last! */ 618 619 return (nidx); 620 } 621 622 static int 623 ffec_setup_txbuf(struct ffec_softc *sc, int idx, struct mbuf **mp) 624 { 625 struct mbuf * m; 626 int error, nsegs; 627 struct bus_dma_segment seg; 628 629 if ((m = m_defrag(*mp, M_NOWAIT)) == NULL) 630 return (ENOMEM); 631 *mp = m; 632 633 error = bus_dmamap_load_mbuf_sg(sc->txbuf_tag, sc->txbuf_map[idx].map, 634 m, &seg, &nsegs, 0); 635 if (error != 0) { 636 return (ENOMEM); 637 } 638 bus_dmamap_sync(sc->txbuf_tag, sc->txbuf_map[idx].map, 639 BUS_DMASYNC_PREWRITE); 640 641 sc->txbuf_map[idx].mbuf = m; 642 ffec_setup_txdesc(sc, idx, seg.ds_addr, seg.ds_len); 643 644 return (0); 645 646 } 647 648 static void 649 ffec_txstart_locked(struct ffec_softc *sc) 650 { 651 if_t ifp; 652 struct mbuf *m; 653 int enqueued; 654 655 FFEC_ASSERT_LOCKED(sc); 656 657 if (!sc->link_is_up) 658 return; 659 660 ifp = sc->ifp; 661 662 if (if_getdrvflags(ifp) & IFF_DRV_OACTIVE) 663 return; 664 665 enqueued = 0; 666 667 for (;;) { 668 if (sc->txcount == (TX_DESC_COUNT-1)) { 669 if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, 0); 670 break; 671 } 672 m = if_dequeue(ifp); 673 if (m == NULL) 674 break; 675 if (ffec_setup_txbuf(sc, sc->tx_idx_head, &m) != 0) { 676 if_sendq_prepend(ifp, m); 677 break; 678 } 679 BPF_MTAP(ifp, m); 680 sc->tx_idx_head = next_txidx(sc, sc->tx_idx_head); 681 ++enqueued; 682 } 683 684 if (enqueued != 0) { 685 bus_dmamap_sync(sc->txdesc_tag, sc->txdesc_map, BUS_DMASYNC_PREWRITE); 686 WR4(sc, FEC_TDAR_REG, FEC_TDAR_TDAR); 687 bus_dmamap_sync(sc->txdesc_tag, sc->txdesc_map, BUS_DMASYNC_POSTWRITE); 688 sc->tx_watchdog_count = WATCHDOG_TIMEOUT_SECS; 689 } 690 } 691 692 static void 693 ffec_txstart(if_t ifp) 694 { 695 struct ffec_softc *sc = if_getsoftc(ifp); 696 697 FFEC_LOCK(sc); 698 ffec_txstart_locked(sc); 699 FFEC_UNLOCK(sc); 700 } 701 702 static void 703 ffec_txfinish_locked(struct ffec_softc *sc) 704 { 705 if_t ifp; 706 struct ffec_hwdesc *desc; 707 struct ffec_bufmap *bmap; 708 boolean_t retired_buffer; 709 710 FFEC_ASSERT_LOCKED(sc); 711 712 /* XXX Can't set PRE|POST right now, but we need both. */ 713 bus_dmamap_sync(sc->txdesc_tag, sc->txdesc_map, BUS_DMASYNC_PREREAD); 714 bus_dmamap_sync(sc->txdesc_tag, sc->txdesc_map, BUS_DMASYNC_POSTREAD); 715 ifp = sc->ifp; 716 retired_buffer = false; 717 while (sc->tx_idx_tail != sc->tx_idx_head) { 718 desc = &sc->txdesc_ring[sc->tx_idx_tail]; 719 if (desc->flags_len & FEC_TXDESC_READY) 720 break; 721 retired_buffer = true; 722 bmap = &sc->txbuf_map[sc->tx_idx_tail]; 723 bus_dmamap_sync(sc->txbuf_tag, bmap->map, 724 BUS_DMASYNC_POSTWRITE); 725 bus_dmamap_unload(sc->txbuf_tag, bmap->map); 726 m_freem(bmap->mbuf); 727 bmap->mbuf = NULL; 728 ffec_setup_txdesc(sc, sc->tx_idx_tail, 0, 0); 729 sc->tx_idx_tail = next_txidx(sc, sc->tx_idx_tail); 730 } 731 732 /* 733 * If we retired any buffers, there will be open tx slots available in 734 * the descriptor ring, go try to start some new output. 735 */ 736 if (retired_buffer) { 737 if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE); 738 ffec_txstart_locked(sc); 739 } 740 741 /* If there are no buffers outstanding, muzzle the watchdog. */ 742 if (sc->tx_idx_tail == sc->tx_idx_head) { 743 sc->tx_watchdog_count = 0; 744 } 745 } 746 747 inline static uint32_t 748 ffec_setup_rxdesc(struct ffec_softc *sc, int idx, bus_addr_t paddr) 749 { 750 uint32_t nidx; 751 752 /* 753 * The hardware requires 32-bit physical addresses. We set up the dma 754 * tag to indicate that, so the cast to uint32_t should never lose 755 * significant bits. 756 */ 757 nidx = next_rxidx(sc, idx); 758 sc->rxdesc_ring[idx].buf_paddr = (uint32_t)paddr; 759 sc->rxdesc_ring[idx].flags_len = FEC_RXDESC_EMPTY | 760 ((nidx == 0) ? FEC_RXDESC_WRAP : 0); 761 762 return (nidx); 763 } 764 765 static int 766 ffec_setup_rxbuf(struct ffec_softc *sc, int idx, struct mbuf * m) 767 { 768 int error, nsegs; 769 struct bus_dma_segment seg; 770 771 if (!(sc->fecflags & FECFLAG_RACC)) { 772 /* 773 * The RACC[SHIFT16] feature is not available. So, we need to 774 * leave at least ETHER_ALIGN bytes free at the beginning of the 775 * buffer to allow the data to be re-aligned after receiving it 776 * (by copying it backwards ETHER_ALIGN bytes in the same 777 * buffer). We also have to ensure that the beginning of the 778 * buffer is aligned to the hardware's requirements. 779 */ 780 m_adj(m, roundup(ETHER_ALIGN, sc->rxbuf_align)); 781 } 782 783 error = bus_dmamap_load_mbuf_sg(sc->rxbuf_tag, sc->rxbuf_map[idx].map, 784 m, &seg, &nsegs, 0); 785 if (error != 0) { 786 return (error); 787 } 788 789 bus_dmamap_sync(sc->rxbuf_tag, sc->rxbuf_map[idx].map, 790 BUS_DMASYNC_PREREAD); 791 792 sc->rxbuf_map[idx].mbuf = m; 793 ffec_setup_rxdesc(sc, idx, seg.ds_addr); 794 795 return (0); 796 } 797 798 static struct mbuf * 799 ffec_alloc_mbufcl(struct ffec_softc *sc) 800 { 801 struct mbuf *m; 802 803 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 804 if (m != NULL) 805 m->m_pkthdr.len = m->m_len = m->m_ext.ext_size; 806 807 return (m); 808 } 809 810 static void 811 ffec_rxfinish_onebuf(struct ffec_softc *sc, int len) 812 { 813 struct mbuf *m, *newmbuf; 814 struct ffec_bufmap *bmap; 815 uint8_t *dst, *src; 816 int error; 817 818 /* 819 * First try to get a new mbuf to plug into this slot in the rx ring. 820 * If that fails, drop the current packet and recycle the current 821 * mbuf, which is still mapped and loaded. 822 */ 823 if ((newmbuf = ffec_alloc_mbufcl(sc)) == NULL) { 824 if_inc_counter(sc->ifp, IFCOUNTER_IQDROPS, 1); 825 ffec_setup_rxdesc(sc, sc->rx_idx, 826 sc->rxdesc_ring[sc->rx_idx].buf_paddr); 827 return; 828 } 829 830 FFEC_UNLOCK(sc); 831 832 bmap = &sc->rxbuf_map[sc->rx_idx]; 833 len -= ETHER_CRC_LEN; 834 bus_dmamap_sync(sc->rxbuf_tag, bmap->map, BUS_DMASYNC_POSTREAD); 835 bus_dmamap_unload(sc->rxbuf_tag, bmap->map); 836 m = bmap->mbuf; 837 bmap->mbuf = NULL; 838 m->m_len = len; 839 m->m_pkthdr.len = len; 840 m->m_pkthdr.rcvif = sc->ifp; 841 842 /* 843 * Align the protocol headers in the receive buffer on a 32-bit 844 * boundary. Newer hardware does the alignment for us. On hardware 845 * that doesn't support this feature, we have to copy-align the data. 846 * 847 * XXX for older hardware, could we speed this up by copying just the 848 * protocol headers into their own small mbuf then chaining the cluster 849 * to it? That way we'd only need to copy like 64 bytes or whatever the 850 * biggest header is, instead of the whole 1530ish-byte frame. 851 */ 852 if (sc->fecflags & FECFLAG_RACC) { 853 m->m_data = mtod(m, uint8_t *) + 2; 854 } else { 855 src = mtod(m, uint8_t*); 856 dst = src - ETHER_ALIGN; 857 bcopy(src, dst, len); 858 m->m_data = dst; 859 } 860 if_input(sc->ifp, m); 861 862 FFEC_LOCK(sc); 863 864 if ((error = ffec_setup_rxbuf(sc, sc->rx_idx, newmbuf)) != 0) { 865 device_printf(sc->dev, "ffec_setup_rxbuf error %d\n", error); 866 /* XXX Now what? We've got a hole in the rx ring. */ 867 } 868 869 } 870 871 static void 872 ffec_rxfinish_locked(struct ffec_softc *sc) 873 { 874 struct ffec_hwdesc *desc; 875 int len; 876 boolean_t produced_empty_buffer; 877 878 FFEC_ASSERT_LOCKED(sc); 879 880 /* XXX Can't set PRE|POST right now, but we need both. */ 881 bus_dmamap_sync(sc->rxdesc_tag, sc->rxdesc_map, BUS_DMASYNC_PREREAD); 882 bus_dmamap_sync(sc->rxdesc_tag, sc->rxdesc_map, BUS_DMASYNC_POSTREAD); 883 produced_empty_buffer = false; 884 for (;;) { 885 desc = &sc->rxdesc_ring[sc->rx_idx]; 886 if (desc->flags_len & FEC_RXDESC_EMPTY) 887 break; 888 produced_empty_buffer = true; 889 len = (desc->flags_len & FEC_RXDESC_LEN_MASK); 890 if (len < 64) { 891 /* 892 * Just recycle the descriptor and continue. . 893 */ 894 ffec_setup_rxdesc(sc, sc->rx_idx, 895 sc->rxdesc_ring[sc->rx_idx].buf_paddr); 896 } else if ((desc->flags_len & FEC_RXDESC_L) == 0) { 897 /* 898 * The entire frame is not in this buffer. Impossible. 899 * Recycle the descriptor and continue. 900 * 901 * XXX what's the right way to handle this? Probably we 902 * should stop/init the hardware because this should 903 * just really never happen when we have buffers bigger 904 * than the maximum frame size. 905 */ 906 device_printf(sc->dev, 907 "fec_rxfinish: received frame without LAST bit set"); 908 ffec_setup_rxdesc(sc, sc->rx_idx, 909 sc->rxdesc_ring[sc->rx_idx].buf_paddr); 910 } else if (desc->flags_len & FEC_RXDESC_ERROR_BITS) { 911 /* 912 * Something went wrong with receiving the frame, we 913 * don't care what (the hardware has counted the error 914 * in the stats registers already), we just reuse the 915 * same mbuf, which is still dma-mapped, by resetting 916 * the rx descriptor. 917 */ 918 ffec_setup_rxdesc(sc, sc->rx_idx, 919 sc->rxdesc_ring[sc->rx_idx].buf_paddr); 920 } else { 921 /* 922 * Normal case: a good frame all in one buffer. 923 */ 924 ffec_rxfinish_onebuf(sc, len); 925 } 926 sc->rx_idx = next_rxidx(sc, sc->rx_idx); 927 } 928 929 if (produced_empty_buffer) { 930 bus_dmamap_sync(sc->rxdesc_tag, sc->rxdesc_map, BUS_DMASYNC_PREWRITE); 931 WR4(sc, FEC_RDAR_REG, FEC_RDAR_RDAR); 932 bus_dmamap_sync(sc->rxdesc_tag, sc->rxdesc_map, BUS_DMASYNC_POSTWRITE); 933 } 934 } 935 936 static void 937 ffec_get_hwaddr(struct ffec_softc *sc, uint8_t *hwaddr) 938 { 939 uint32_t palr, paur, rnd; 940 941 /* 942 * Try to recover a MAC address from the running hardware. If there's 943 * something non-zero there, assume the bootloader did the right thing 944 * and just use it. 945 * 946 * Otherwise, set the address to a convenient locally assigned address, 947 * 'bsd' + random 24 low-order bits. 'b' is 0x62, which has the locally 948 * assigned bit set, and the broadcast/multicast bit clear. 949 */ 950 palr = RD4(sc, FEC_PALR_REG); 951 paur = RD4(sc, FEC_PAUR_REG) & FEC_PAUR_PADDR2_MASK; 952 if ((palr | paur) != 0) { 953 hwaddr[0] = palr >> 24; 954 hwaddr[1] = palr >> 16; 955 hwaddr[2] = palr >> 8; 956 hwaddr[3] = palr >> 0; 957 hwaddr[4] = paur >> 24; 958 hwaddr[5] = paur >> 16; 959 } else { 960 rnd = arc4random() & 0x00ffffff; 961 hwaddr[0] = 'b'; 962 hwaddr[1] = 's'; 963 hwaddr[2] = 'd'; 964 hwaddr[3] = rnd >> 16; 965 hwaddr[4] = rnd >> 8; 966 hwaddr[5] = rnd >> 0; 967 } 968 969 if (bootverbose) { 970 device_printf(sc->dev, 971 "MAC address %02x:%02x:%02x:%02x:%02x:%02x\n", 972 hwaddr[0], hwaddr[1], hwaddr[2], 973 hwaddr[3], hwaddr[4], hwaddr[5]); 974 } 975 } 976 977 static u_int 978 ffec_hash_maddr(void *arg, struct sockaddr_dl *sdl, u_int cnt) 979 { 980 uint64_t *ghash = arg; 981 uint32_t crc; 982 983 /* 6 bits from MSB in LE CRC32 are used for hash. */ 984 crc = ether_crc32_le(LLADDR(sdl), ETHER_ADDR_LEN); 985 *ghash |= 1LLU << (((uint8_t *)&crc)[3] >> 2); 986 987 return (1); 988 } 989 990 static void 991 ffec_setup_rxfilter(struct ffec_softc *sc) 992 { 993 if_t ifp; 994 uint8_t *eaddr; 995 uint64_t ghash, ihash; 996 997 FFEC_ASSERT_LOCKED(sc); 998 999 ifp = sc->ifp; 1000 1001 /* 1002 * Set the multicast (group) filter hash. 1003 */ 1004 if ((if_getflags(ifp) & IFF_ALLMULTI)) 1005 ghash = 0xffffffffffffffffLLU; 1006 else { 1007 ghash = 0; 1008 if_foreach_llmaddr(ifp, ffec_hash_maddr, &ghash); 1009 } 1010 WR4(sc, FEC_GAUR_REG, (uint32_t)(ghash >> 32)); 1011 WR4(sc, FEC_GALR_REG, (uint32_t)ghash); 1012 1013 /* 1014 * Set the individual address filter hash. 1015 * 1016 * XXX Is 0 the right value when promiscuous is off? This hw feature 1017 * seems to support the concept of MAC address aliases, does such a 1018 * thing even exist? 1019 */ 1020 if ((if_getflags(ifp) & IFF_PROMISC)) 1021 ihash = 0xffffffffffffffffLLU; 1022 else { 1023 ihash = 0; 1024 } 1025 WR4(sc, FEC_IAUR_REG, (uint32_t)(ihash >> 32)); 1026 WR4(sc, FEC_IALR_REG, (uint32_t)ihash); 1027 1028 /* 1029 * Set the primary address. 1030 */ 1031 eaddr = if_getlladdr(ifp); 1032 WR4(sc, FEC_PALR_REG, (eaddr[0] << 24) | (eaddr[1] << 16) | 1033 (eaddr[2] << 8) | eaddr[3]); 1034 WR4(sc, FEC_PAUR_REG, (eaddr[4] << 24) | (eaddr[5] << 16)); 1035 } 1036 1037 static void 1038 ffec_stop_locked(struct ffec_softc *sc) 1039 { 1040 if_t ifp; 1041 struct ffec_hwdesc *desc; 1042 struct ffec_bufmap *bmap; 1043 int idx; 1044 1045 FFEC_ASSERT_LOCKED(sc); 1046 1047 ifp = sc->ifp; 1048 if_setdrvflagbits(ifp, 0, (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)); 1049 sc->tx_watchdog_count = 0; 1050 1051 /* 1052 * Stop the hardware, mask all interrupts, and clear all current 1053 * interrupt status bits. 1054 */ 1055 WR4(sc, FEC_ECR_REG, RD4(sc, FEC_ECR_REG) & ~FEC_ECR_ETHEREN); 1056 WR4(sc, FEC_IEM_REG, 0x00000000); 1057 WR4(sc, FEC_IER_REG, 0xffffffff); 1058 1059 /* 1060 * Stop the media-check callout. Do not use callout_drain() because 1061 * we're holding a mutex the callout acquires, and if it's currently 1062 * waiting to acquire it, we'd deadlock. If it is waiting now, the 1063 * ffec_tick() routine will return without doing anything when it sees 1064 * that IFF_DRV_RUNNING is not set, so avoiding callout_drain() is safe. 1065 */ 1066 callout_stop(&sc->ffec_callout); 1067 1068 /* 1069 * Discard all untransmitted buffers. Each buffer is simply freed; 1070 * it's as if the bits were transmitted and then lost on the wire. 1071 * 1072 * XXX Is this right? Or should we use IFQ_DRV_PREPEND() to put them 1073 * back on the queue for when we get restarted later? 1074 */ 1075 idx = sc->tx_idx_tail; 1076 while (idx != sc->tx_idx_head) { 1077 desc = &sc->txdesc_ring[idx]; 1078 bmap = &sc->txbuf_map[idx]; 1079 if (desc->buf_paddr != 0) { 1080 bus_dmamap_unload(sc->txbuf_tag, bmap->map); 1081 m_freem(bmap->mbuf); 1082 bmap->mbuf = NULL; 1083 ffec_setup_txdesc(sc, idx, 0, 0); 1084 } 1085 idx = next_txidx(sc, idx); 1086 } 1087 1088 /* 1089 * Discard all unprocessed receive buffers. This amounts to just 1090 * pretending that nothing ever got received into them. We reuse the 1091 * mbuf already mapped for each desc, simply turning the EMPTY flags 1092 * back on so they'll get reused when we start up again. 1093 */ 1094 for (idx = 0; idx < RX_DESC_COUNT; ++idx) { 1095 desc = &sc->rxdesc_ring[idx]; 1096 ffec_setup_rxdesc(sc, idx, desc->buf_paddr); 1097 } 1098 } 1099 1100 static void 1101 ffec_init_locked(struct ffec_softc *sc) 1102 { 1103 if_t ifp = sc->ifp; 1104 uint32_t maxbuf, maxfl, regval; 1105 1106 FFEC_ASSERT_LOCKED(sc); 1107 1108 /* 1109 * The hardware has a limit of 0x7ff as the max frame length (see 1110 * comments for MRBR below), and we use mbuf clusters as receive 1111 * buffers, and we currently are designed to receive an entire frame 1112 * into a single buffer. 1113 * 1114 * We start with a MCLBYTES-sized cluster, but we have to offset into 1115 * the buffer by ETHER_ALIGN to make room for post-receive re-alignment, 1116 * and then that value has to be rounded up to the hardware's DMA 1117 * alignment requirements, so all in all our buffer is that much smaller 1118 * than MCLBYTES. 1119 * 1120 * The resulting value is used as the frame truncation length and the 1121 * max buffer receive buffer size for now. It'll become more complex 1122 * when we support jumbo frames and receiving fragments of them into 1123 * separate buffers. 1124 */ 1125 maxbuf = MCLBYTES - roundup(ETHER_ALIGN, sc->rxbuf_align); 1126 maxfl = min(maxbuf, 0x7ff); 1127 1128 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) 1129 return; 1130 1131 /* Mask all interrupts and clear all current interrupt status bits. */ 1132 WR4(sc, FEC_IEM_REG, 0x00000000); 1133 WR4(sc, FEC_IER_REG, 0xffffffff); 1134 1135 /* 1136 * Go set up palr/puar, galr/gaur, ialr/iaur. 1137 */ 1138 ffec_setup_rxfilter(sc); 1139 1140 /* 1141 * TFWR - Transmit FIFO watermark register. 1142 * 1143 * Set the transmit fifo watermark register to "store and forward" mode 1144 * and also set a threshold of 128 bytes in the fifo before transmission 1145 * of a frame begins (to avoid dma underruns). Recent FEC hardware 1146 * supports STRFWD and when that bit is set, the watermark level in the 1147 * low bits is ignored. Older hardware doesn't have STRFWD, but writing 1148 * to that bit is innocuous, and the TWFR bits get used instead. 1149 */ 1150 WR4(sc, FEC_TFWR_REG, FEC_TFWR_STRFWD | FEC_TFWR_TWFR_128BYTE); 1151 1152 /* RCR - Receive control register. 1153 * 1154 * Set max frame length + clean out anything left from u-boot. 1155 */ 1156 WR4(sc, FEC_RCR_REG, (maxfl << FEC_RCR_MAX_FL_SHIFT)); 1157 1158 /* 1159 * TCR - Transmit control register. 1160 * 1161 * Clean out anything left from u-boot. Any necessary values are set in 1162 * ffec_miibus_statchg() based on the media type. 1163 */ 1164 WR4(sc, FEC_TCR_REG, 0); 1165 1166 /* 1167 * OPD - Opcode/pause duration. 1168 * 1169 * XXX These magic numbers come from u-boot. 1170 */ 1171 WR4(sc, FEC_OPD_REG, 0x00010020); 1172 1173 /* 1174 * FRSR - Fifo receive start register. 1175 * 1176 * This register does not exist on imx6, it is present on earlier 1177 * hardware. The u-boot code sets this to a non-default value that's 32 1178 * bytes larger than the default, with no clue as to why. The default 1179 * value should work fine, so there's no code to init it here. 1180 */ 1181 1182 /* 1183 * MRBR - Max RX buffer size. 1184 * 1185 * Note: For hardware prior to imx6 this value cannot exceed 0x07ff, 1186 * but the datasheet says no such thing for imx6. On the imx6, setting 1187 * this to 2K without setting EN1588 resulted in a crazy runaway 1188 * receive loop in the hardware, where every rx descriptor in the ring 1189 * had its EMPTY flag cleared, no completion or error flags set, and a 1190 * length of zero. I think maybe you can only exceed it when EN1588 is 1191 * set, like maybe that's what enables jumbo frames, because in general 1192 * the EN1588 flag seems to be the "enable new stuff" vs. "be legacy- 1193 * compatible" flag. 1194 */ 1195 WR4(sc, FEC_MRBR_REG, maxfl << FEC_MRBR_R_BUF_SIZE_SHIFT); 1196 1197 /* 1198 * FTRL - Frame truncation length. 1199 * 1200 * Must be greater than or equal to the value set in FEC_RCR_MAXFL. 1201 */ 1202 WR4(sc, FEC_FTRL_REG, maxfl); 1203 1204 /* 1205 * RDSR / TDSR descriptor ring pointers. 1206 * 1207 * When we turn on ECR_ETHEREN at the end, the hardware zeroes its 1208 * internal current descriptor index values for both rings, so we zero 1209 * our index values as well. 1210 */ 1211 sc->rx_idx = 0; 1212 sc->tx_idx_head = sc->tx_idx_tail = 0; 1213 sc->txcount = 0; 1214 WR4(sc, FEC_RDSR_REG, sc->rxdesc_ring_paddr); 1215 WR4(sc, FEC_TDSR_REG, sc->txdesc_ring_paddr); 1216 1217 /* 1218 * EIM - interrupt mask register. 1219 * 1220 * We always enable the same set of interrupts while running; unlike 1221 * some drivers there's no need to change the mask on the fly depending 1222 * on what operations are in progress. 1223 */ 1224 WR4(sc, FEC_IEM_REG, FEC_IER_TXF | FEC_IER_RXF | FEC_IER_EBERR); 1225 1226 /* 1227 * MIBC - MIB control (hardware stats); clear all statistics regs, then 1228 * enable collection of statistics. 1229 */ 1230 regval = RD4(sc, FEC_MIBC_REG); 1231 WR4(sc, FEC_MIBC_REG, regval | FEC_MIBC_DIS); 1232 ffec_clear_stats(sc); 1233 WR4(sc, FEC_MIBC_REG, regval & ~FEC_MIBC_DIS); 1234 1235 if (sc->fecflags & FECFLAG_RACC) { 1236 /* 1237 * RACC - Receive Accelerator Function Configuration. 1238 */ 1239 regval = RD4(sc, FEC_RACC_REG); 1240 WR4(sc, FEC_RACC_REG, regval | FEC_RACC_SHIFT16); 1241 } 1242 1243 /* 1244 * ECR - Ethernet control register. 1245 * 1246 * This must happen after all the other config registers are set. If 1247 * we're running on little-endian hardware, also set the flag for byte- 1248 * swapping descriptor ring entries. This flag doesn't exist on older 1249 * hardware, but it can be safely set -- the bit position it occupies 1250 * was unused. 1251 */ 1252 regval = RD4(sc, FEC_ECR_REG); 1253 #if _BYTE_ORDER == _LITTLE_ENDIAN 1254 regval |= FEC_ECR_DBSWP; 1255 #endif 1256 regval |= FEC_ECR_ETHEREN; 1257 WR4(sc, FEC_ECR_REG, regval); 1258 1259 if_setdrvflagbits(ifp, IFF_DRV_RUNNING, 0); 1260 1261 /* 1262 * Call mii_mediachg() which will call back into ffec_miibus_statchg() to 1263 * set up the remaining config registers based on the current media. 1264 */ 1265 mii_mediachg(sc->mii_softc); 1266 callout_reset(&sc->ffec_callout, hz, ffec_tick, sc); 1267 1268 /* 1269 * Tell the hardware that receive buffers are available. They were made 1270 * available in ffec_attach() or ffec_stop(). 1271 */ 1272 WR4(sc, FEC_RDAR_REG, FEC_RDAR_RDAR); 1273 } 1274 1275 static void 1276 ffec_init(void *if_softc) 1277 { 1278 struct ffec_softc *sc = if_softc; 1279 1280 FFEC_LOCK(sc); 1281 ffec_init_locked(sc); 1282 FFEC_UNLOCK(sc); 1283 } 1284 1285 static void 1286 ffec_intr(void *arg) 1287 { 1288 struct ffec_softc *sc; 1289 uint32_t ier; 1290 1291 sc = arg; 1292 1293 FFEC_LOCK(sc); 1294 1295 ier = RD4(sc, FEC_IER_REG); 1296 1297 if (ier & FEC_IER_TXF) { 1298 WR4(sc, FEC_IER_REG, FEC_IER_TXF); 1299 ffec_txfinish_locked(sc); 1300 } 1301 1302 if (ier & FEC_IER_RXF) { 1303 WR4(sc, FEC_IER_REG, FEC_IER_RXF); 1304 ffec_rxfinish_locked(sc); 1305 } 1306 1307 /* 1308 * We actually don't care about most errors, because the hardware copes 1309 * with them just fine, discarding the incoming bad frame, or forcing a 1310 * bad CRC onto an outgoing bad frame, and counting the errors in the 1311 * stats registers. The one that really matters is EBERR (DMA bus 1312 * error) because the hardware automatically clears ECR[ETHEREN] and we 1313 * have to restart it here. It should never happen. 1314 */ 1315 if (ier & FEC_IER_EBERR) { 1316 WR4(sc, FEC_IER_REG, FEC_IER_EBERR); 1317 device_printf(sc->dev, 1318 "Ethernet DMA error, restarting controller.\n"); 1319 ffec_stop_locked(sc); 1320 ffec_init_locked(sc); 1321 } 1322 1323 FFEC_UNLOCK(sc); 1324 1325 } 1326 1327 static int 1328 ffec_ioctl(if_t ifp, u_long cmd, caddr_t data) 1329 { 1330 struct ffec_softc *sc; 1331 struct mii_data *mii; 1332 struct ifreq *ifr; 1333 int mask, error; 1334 1335 sc = if_getsoftc(ifp); 1336 ifr = (struct ifreq *)data; 1337 1338 error = 0; 1339 switch (cmd) { 1340 case SIOCSIFFLAGS: 1341 FFEC_LOCK(sc); 1342 if (if_getflags(ifp) & IFF_UP) { 1343 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 1344 if ((if_getflags(ifp) ^ sc->if_flags) & 1345 (IFF_PROMISC | IFF_ALLMULTI)) 1346 ffec_setup_rxfilter(sc); 1347 } else { 1348 if (!sc->is_detaching) 1349 ffec_init_locked(sc); 1350 } 1351 } else { 1352 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) 1353 ffec_stop_locked(sc); 1354 } 1355 sc->if_flags = if_getflags(ifp); 1356 FFEC_UNLOCK(sc); 1357 break; 1358 1359 case SIOCADDMULTI: 1360 case SIOCDELMULTI: 1361 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 1362 FFEC_LOCK(sc); 1363 ffec_setup_rxfilter(sc); 1364 FFEC_UNLOCK(sc); 1365 } 1366 break; 1367 1368 case SIOCSIFMEDIA: 1369 case SIOCGIFMEDIA: 1370 mii = sc->mii_softc; 1371 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd); 1372 break; 1373 1374 case SIOCSIFCAP: 1375 mask = if_getcapenable(ifp) ^ ifr->ifr_reqcap; 1376 if (mask & IFCAP_VLAN_MTU) { 1377 /* No work to do except acknowledge the change took. */ 1378 if_togglecapenable(ifp, IFCAP_VLAN_MTU); 1379 } 1380 break; 1381 1382 default: 1383 error = ether_ioctl(ifp, cmd, data); 1384 break; 1385 } 1386 1387 return (error); 1388 } 1389 1390 static int 1391 ffec_detach(device_t dev) 1392 { 1393 struct ffec_softc *sc; 1394 bus_dmamap_t map; 1395 int idx, irq; 1396 1397 /* 1398 * NB: This function can be called internally to unwind a failure to 1399 * attach. Make sure a resource got allocated/created before destroying. 1400 */ 1401 1402 sc = device_get_softc(dev); 1403 1404 if (sc->is_attached) { 1405 FFEC_LOCK(sc); 1406 sc->is_detaching = true; 1407 ffec_stop_locked(sc); 1408 FFEC_UNLOCK(sc); 1409 callout_drain(&sc->ffec_callout); 1410 ether_ifdetach(sc->ifp); 1411 } 1412 1413 /* XXX no miibus detach? */ 1414 1415 /* Clean up RX DMA resources and free mbufs. */ 1416 for (idx = 0; idx < RX_DESC_COUNT; ++idx) { 1417 if ((map = sc->rxbuf_map[idx].map) != NULL) { 1418 bus_dmamap_unload(sc->rxbuf_tag, map); 1419 bus_dmamap_destroy(sc->rxbuf_tag, map); 1420 m_freem(sc->rxbuf_map[idx].mbuf); 1421 } 1422 } 1423 if (sc->rxbuf_tag != NULL) 1424 bus_dma_tag_destroy(sc->rxbuf_tag); 1425 if (sc->rxdesc_map != NULL) { 1426 bus_dmamap_unload(sc->rxdesc_tag, sc->rxdesc_map); 1427 bus_dmamem_free(sc->rxdesc_tag, sc->rxdesc_ring, 1428 sc->rxdesc_map); 1429 } 1430 if (sc->rxdesc_tag != NULL) 1431 bus_dma_tag_destroy(sc->rxdesc_tag); 1432 1433 /* Clean up TX DMA resources. */ 1434 for (idx = 0; idx < TX_DESC_COUNT; ++idx) { 1435 if ((map = sc->txbuf_map[idx].map) != NULL) { 1436 /* TX maps are already unloaded. */ 1437 bus_dmamap_destroy(sc->txbuf_tag, map); 1438 } 1439 } 1440 if (sc->txbuf_tag != NULL) 1441 bus_dma_tag_destroy(sc->txbuf_tag); 1442 if (sc->txdesc_map != NULL) { 1443 bus_dmamap_unload(sc->txdesc_tag, sc->txdesc_map); 1444 bus_dmamem_free(sc->txdesc_tag, sc->txdesc_ring, 1445 sc->txdesc_map); 1446 } 1447 if (sc->txdesc_tag != NULL) 1448 bus_dma_tag_destroy(sc->txdesc_tag); 1449 1450 /* Release bus resources. */ 1451 for (irq = 0; irq < MAX_IRQ_COUNT; ++irq) { 1452 if (sc->intr_cookie[irq] != NULL) { 1453 bus_teardown_intr(dev, sc->irq_res[irq], 1454 sc->intr_cookie[irq]); 1455 } 1456 } 1457 bus_release_resources(dev, irq_res_spec, sc->irq_res); 1458 1459 if (sc->mem_res != NULL) 1460 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->mem_res); 1461 1462 FFEC_LOCK_DESTROY(sc); 1463 return (0); 1464 } 1465 1466 static int 1467 ffec_attach(device_t dev) 1468 { 1469 struct ffec_softc *sc; 1470 if_t ifp = NULL; 1471 struct mbuf *m; 1472 void *dummy; 1473 uintptr_t typeflags; 1474 phandle_t ofw_node; 1475 uint32_t idx, mscr; 1476 int error, phynum, rid, irq; 1477 uint8_t eaddr[ETHER_ADDR_LEN]; 1478 1479 sc = device_get_softc(dev); 1480 sc->dev = dev; 1481 1482 FFEC_LOCK_INIT(sc); 1483 1484 /* 1485 * There are differences in the implementation and features of the FEC 1486 * hardware on different SoCs, so figure out what type we are. 1487 */ 1488 typeflags = ofw_bus_search_compatible(dev, compat_data)->ocd_data; 1489 sc->fectype = (uint8_t)(typeflags & FECTYPE_MASK); 1490 sc->fecflags = (uint32_t)(typeflags & ~FECTYPE_MASK); 1491 1492 if (sc->fecflags & FECFLAG_AVB) { 1493 sc->rxbuf_align = 64; 1494 sc->txbuf_align = 1; 1495 } else { 1496 sc->rxbuf_align = 16; 1497 sc->txbuf_align = 16; 1498 } 1499 1500 /* 1501 * We have to be told what kind of electrical connection exists between 1502 * the MAC and PHY or we can't operate correctly. 1503 */ 1504 if ((ofw_node = ofw_bus_get_node(dev)) == -1) { 1505 device_printf(dev, "Impossible: Can't find ofw bus node\n"); 1506 error = ENXIO; 1507 goto out; 1508 } 1509 sc->phy_conn_type = mii_fdt_get_contype(ofw_node); 1510 if (sc->phy_conn_type == MII_CONTYPE_UNKNOWN) { 1511 device_printf(sc->dev, "No valid 'phy-mode' " 1512 "property found in FDT data for device.\n"); 1513 error = ENOATTR; 1514 goto out; 1515 } 1516 1517 callout_init_mtx(&sc->ffec_callout, &sc->mtx, 0); 1518 1519 /* Allocate bus resources for accessing the hardware. */ 1520 rid = 0; 1521 sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 1522 RF_ACTIVE); 1523 if (sc->mem_res == NULL) { 1524 device_printf(dev, "could not allocate memory resources.\n"); 1525 error = ENOMEM; 1526 goto out; 1527 } 1528 1529 error = bus_alloc_resources(dev, irq_res_spec, sc->irq_res); 1530 if (error != 0) { 1531 device_printf(dev, "could not allocate interrupt resources\n"); 1532 goto out; 1533 } 1534 1535 /* 1536 * Set up TX descriptor ring, descriptors, and dma maps. 1537 */ 1538 error = bus_dma_tag_create( 1539 bus_get_dma_tag(dev), /* Parent tag. */ 1540 FEC_DESC_RING_ALIGN, 0, /* alignment, boundary */ 1541 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 1542 BUS_SPACE_MAXADDR, /* highaddr */ 1543 NULL, NULL, /* filter, filterarg */ 1544 TX_DESC_SIZE, 1, /* maxsize, nsegments */ 1545 TX_DESC_SIZE, /* maxsegsize */ 1546 0, /* flags */ 1547 NULL, NULL, /* lockfunc, lockarg */ 1548 &sc->txdesc_tag); 1549 if (error != 0) { 1550 device_printf(sc->dev, 1551 "could not create TX ring DMA tag.\n"); 1552 goto out; 1553 } 1554 1555 error = bus_dmamem_alloc(sc->txdesc_tag, (void**)&sc->txdesc_ring, 1556 BUS_DMA_COHERENT | BUS_DMA_WAITOK | BUS_DMA_ZERO, &sc->txdesc_map); 1557 if (error != 0) { 1558 device_printf(sc->dev, 1559 "could not allocate TX descriptor ring.\n"); 1560 goto out; 1561 } 1562 1563 error = bus_dmamap_load(sc->txdesc_tag, sc->txdesc_map, sc->txdesc_ring, 1564 TX_DESC_SIZE, ffec_get1paddr, &sc->txdesc_ring_paddr, 0); 1565 if (error != 0) { 1566 device_printf(sc->dev, 1567 "could not load TX descriptor ring map.\n"); 1568 goto out; 1569 } 1570 1571 error = bus_dma_tag_create( 1572 bus_get_dma_tag(dev), /* Parent tag. */ 1573 sc->txbuf_align, 0, /* alignment, boundary */ 1574 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 1575 BUS_SPACE_MAXADDR, /* highaddr */ 1576 NULL, NULL, /* filter, filterarg */ 1577 MCLBYTES, 1, /* maxsize, nsegments */ 1578 MCLBYTES, /* maxsegsize */ 1579 0, /* flags */ 1580 NULL, NULL, /* lockfunc, lockarg */ 1581 &sc->txbuf_tag); 1582 if (error != 0) { 1583 device_printf(sc->dev, 1584 "could not create TX ring DMA tag.\n"); 1585 goto out; 1586 } 1587 1588 for (idx = 0; idx < TX_DESC_COUNT; ++idx) { 1589 error = bus_dmamap_create(sc->txbuf_tag, 0, 1590 &sc->txbuf_map[idx].map); 1591 if (error != 0) { 1592 device_printf(sc->dev, 1593 "could not create TX buffer DMA map.\n"); 1594 goto out; 1595 } 1596 ffec_setup_txdesc(sc, idx, 0, 0); 1597 } 1598 1599 /* 1600 * Set up RX descriptor ring, descriptors, dma maps, and mbufs. 1601 */ 1602 error = bus_dma_tag_create( 1603 bus_get_dma_tag(dev), /* Parent tag. */ 1604 FEC_DESC_RING_ALIGN, 0, /* alignment, boundary */ 1605 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 1606 BUS_SPACE_MAXADDR, /* highaddr */ 1607 NULL, NULL, /* filter, filterarg */ 1608 RX_DESC_SIZE, 1, /* maxsize, nsegments */ 1609 RX_DESC_SIZE, /* maxsegsize */ 1610 0, /* flags */ 1611 NULL, NULL, /* lockfunc, lockarg */ 1612 &sc->rxdesc_tag); 1613 if (error != 0) { 1614 device_printf(sc->dev, 1615 "could not create RX ring DMA tag.\n"); 1616 goto out; 1617 } 1618 1619 error = bus_dmamem_alloc(sc->rxdesc_tag, (void **)&sc->rxdesc_ring, 1620 BUS_DMA_COHERENT | BUS_DMA_WAITOK | BUS_DMA_ZERO, &sc->rxdesc_map); 1621 if (error != 0) { 1622 device_printf(sc->dev, 1623 "could not allocate RX descriptor ring.\n"); 1624 goto out; 1625 } 1626 1627 error = bus_dmamap_load(sc->rxdesc_tag, sc->rxdesc_map, sc->rxdesc_ring, 1628 RX_DESC_SIZE, ffec_get1paddr, &sc->rxdesc_ring_paddr, 0); 1629 if (error != 0) { 1630 device_printf(sc->dev, 1631 "could not load RX descriptor ring map.\n"); 1632 goto out; 1633 } 1634 1635 error = bus_dma_tag_create( 1636 bus_get_dma_tag(dev), /* Parent tag. */ 1637 1, 0, /* alignment, boundary */ 1638 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 1639 BUS_SPACE_MAXADDR, /* highaddr */ 1640 NULL, NULL, /* filter, filterarg */ 1641 MCLBYTES, 1, /* maxsize, nsegments */ 1642 MCLBYTES, /* maxsegsize */ 1643 0, /* flags */ 1644 NULL, NULL, /* lockfunc, lockarg */ 1645 &sc->rxbuf_tag); 1646 if (error != 0) { 1647 device_printf(sc->dev, 1648 "could not create RX buf DMA tag.\n"); 1649 goto out; 1650 } 1651 1652 for (idx = 0; idx < RX_DESC_COUNT; ++idx) { 1653 error = bus_dmamap_create(sc->rxbuf_tag, 0, 1654 &sc->rxbuf_map[idx].map); 1655 if (error != 0) { 1656 device_printf(sc->dev, 1657 "could not create RX buffer DMA map.\n"); 1658 goto out; 1659 } 1660 if ((m = ffec_alloc_mbufcl(sc)) == NULL) { 1661 device_printf(dev, "Could not alloc mbuf\n"); 1662 error = ENOMEM; 1663 goto out; 1664 } 1665 if ((error = ffec_setup_rxbuf(sc, idx, m)) != 0) { 1666 device_printf(sc->dev, 1667 "could not create new RX buffer.\n"); 1668 goto out; 1669 } 1670 } 1671 1672 /* Try to get the MAC address from the hardware before resetting it. */ 1673 ffec_get_hwaddr(sc, eaddr); 1674 1675 /* 1676 * Reset the hardware. Disables all interrupts. 1677 * 1678 * When the FEC is connected to the AXI bus (indicated by AVB flag), a 1679 * MAC reset while a bus transaction is pending can hang the bus. 1680 * Instead of resetting, turn off the ENABLE bit, which allows the 1681 * hardware to complete any in-progress transfers (appending a bad CRC 1682 * to any partial packet) and release the AXI bus. This could probably 1683 * be done unconditionally for all hardware variants, but that hasn't 1684 * been tested. 1685 */ 1686 if (sc->fecflags & FECFLAG_AVB) 1687 WR4(sc, FEC_ECR_REG, 0); 1688 else 1689 WR4(sc, FEC_ECR_REG, FEC_ECR_RESET); 1690 1691 /* Setup interrupt handler. */ 1692 for (irq = 0; irq < MAX_IRQ_COUNT; ++irq) { 1693 if (sc->irq_res[irq] != NULL) { 1694 error = bus_setup_intr(dev, sc->irq_res[irq], 1695 INTR_TYPE_NET | INTR_MPSAFE, NULL, ffec_intr, sc, 1696 &sc->intr_cookie[irq]); 1697 if (error != 0) { 1698 device_printf(dev, 1699 "could not setup interrupt handler.\n"); 1700 goto out; 1701 } 1702 } 1703 } 1704 1705 /* 1706 * Set up the PHY control register. 1707 * 1708 * Speed formula for ENET is md_clock = mac_clock / ((N + 1) * 2). 1709 * Speed formula for FEC is md_clock = mac_clock / (N * 2) 1710 * 1711 * XXX - Revisit this... 1712 * 1713 * For a Wandboard imx6 (ENET) I was originally using 4, but the uboot 1714 * code uses 10. Both values seem to work, but I suspect many modern 1715 * PHY parts can do mdio at speeds far above the standard 2.5 MHz. 1716 * 1717 * Different imx manuals use confusingly different terminology (things 1718 * like "system clock" and "internal module clock") with examples that 1719 * use frequencies that have nothing to do with ethernet, giving the 1720 * vague impression that maybe the clock in question is the periphclock 1721 * or something. In fact, on an imx53 development board (FEC), 1722 * measuring the mdio clock at the pin on the PHY and playing with 1723 * various divisors showed that the root speed was 66 MHz (clk_ipg_root 1724 * aka periphclock) and 13 was the right divisor. 1725 * 1726 * All in all, it seems likely that 13 is a safe divisor for now, 1727 * because if we really do need to base it on the peripheral clock 1728 * speed, then we need a platform-independent get-clock-freq API. 1729 */ 1730 mscr = 13 << FEC_MSCR_MII_SPEED_SHIFT; 1731 if (OF_hasprop(ofw_node, "phy-disable-preamble")) { 1732 mscr |= FEC_MSCR_DIS_PRE; 1733 if (bootverbose) 1734 device_printf(dev, "PHY preamble disabled\n"); 1735 } 1736 WR4(sc, FEC_MSCR_REG, mscr); 1737 1738 /* Set up the ethernet interface. */ 1739 sc->ifp = ifp = if_alloc(IFT_ETHER); 1740 1741 if_setsoftc(ifp, sc); 1742 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1743 if_setflags(ifp, IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST); 1744 if_setcapabilities(ifp, IFCAP_VLAN_MTU); 1745 if_setcapenable(ifp, if_getcapabilities(ifp)); 1746 if_setstartfn(ifp, ffec_txstart); 1747 if_setioctlfn(ifp, ffec_ioctl); 1748 if_setinitfn(ifp, ffec_init); 1749 if_setsendqlen(ifp, TX_DESC_COUNT - 1); 1750 if_setsendqready(ifp); 1751 if_setifheaderlen(ifp, sizeof(struct ether_vlan_header)); 1752 1753 #if 0 /* XXX The hardware keeps stats we could use for these. */ 1754 if_setlinkmib(ifp, &sc->mibdata); 1755 if_setlinkmiblen(ifp, sizeof(sc->mibdata)); 1756 #endif 1757 1758 /* Set up the miigasket hardware (if any). */ 1759 ffec_miigasket_setup(sc); 1760 1761 /* Attach the mii driver. */ 1762 if (fdt_get_phyaddr(ofw_node, dev, &phynum, &dummy) != 0) { 1763 phynum = MII_PHY_ANY; 1764 } 1765 error = mii_attach(dev, &sc->miibus, ifp, ffec_media_change, 1766 ffec_media_status, BMSR_DEFCAPMASK, phynum, MII_OFFSET_ANY, 1767 (sc->fecflags & FECTYPE_MVF) ? MIIF_FORCEANEG : 0); 1768 if (error != 0) { 1769 device_printf(dev, "PHY attach failed\n"); 1770 goto out; 1771 } 1772 sc->mii_softc = device_get_softc(sc->miibus); 1773 1774 /* All ready to run, attach the ethernet interface. */ 1775 ether_ifattach(ifp, eaddr); 1776 sc->is_attached = true; 1777 1778 error = 0; 1779 out: 1780 1781 if (error != 0) 1782 ffec_detach(dev); 1783 1784 return (error); 1785 } 1786 1787 static int 1788 ffec_probe(device_t dev) 1789 { 1790 uintptr_t fectype; 1791 1792 if (!ofw_bus_status_okay(dev)) 1793 return (ENXIO); 1794 1795 fectype = ofw_bus_search_compatible(dev, compat_data)->ocd_data; 1796 if (fectype == FECTYPE_NONE) 1797 return (ENXIO); 1798 1799 device_set_desc(dev, (fectype & FECFLAG_GBE) ? 1800 "Freescale Gigabit Ethernet Controller" : 1801 "Freescale Fast Ethernet Controller"); 1802 1803 return (BUS_PROBE_DEFAULT); 1804 } 1805 1806 1807 static device_method_t ffec_methods[] = { 1808 /* Device interface. */ 1809 DEVMETHOD(device_probe, ffec_probe), 1810 DEVMETHOD(device_attach, ffec_attach), 1811 DEVMETHOD(device_detach, ffec_detach), 1812 1813 /* 1814 DEVMETHOD(device_shutdown, ffec_shutdown), 1815 DEVMETHOD(device_suspend, ffec_suspend), 1816 DEVMETHOD(device_resume, ffec_resume), 1817 */ 1818 1819 /* MII interface. */ 1820 DEVMETHOD(miibus_readreg, ffec_miibus_readreg), 1821 DEVMETHOD(miibus_writereg, ffec_miibus_writereg), 1822 DEVMETHOD(miibus_statchg, ffec_miibus_statchg), 1823 1824 DEVMETHOD_END 1825 }; 1826 1827 static driver_t ffec_driver = { 1828 "ffec", 1829 ffec_methods, 1830 sizeof(struct ffec_softc) 1831 }; 1832 1833 DRIVER_MODULE(ffec, simplebus, ffec_driver, 0, 0); 1834 DRIVER_MODULE(miibus, ffec, miibus_driver, 0, 0); 1835 1836 MODULE_DEPEND(ffec, ether, 1, 1, 1); 1837 MODULE_DEPEND(ffec, miibus, 1, 1, 1); 1838