xref: /freebsd/sys/dev/etherswitch/rtl8366/rtl8366rbvar.h (revision ccb59683b98360afaf5b5bb641a68fea22c68d0b)
1 /*-
2  * SPDX-License-Identifier: BSD-2-Clause
3  *
4  * Copyright (c) 2015-2016 Hiroki Mori.
5  * Copyright (c) 2011-2012 Stefan Bethke.
6  * All rights reserved.
7  *
8  * Redistribution and use in source and binary forms, with or without
9  * modification, are permitted provided that the following conditions
10  * are met:
11  * 1. Redistributions of source code must retain the above copyright
12  *    notice, this list of conditions and the following disclaimer.
13  * 2. Redistributions in binary form must reproduce the above copyright
14  *    notice, this list of conditions and the following disclaimer in the
15  *    documentation and/or other materials provided with the distribution.
16  *
17  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
18  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
21  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27  * SUCH DAMAGE.
28  *
29  * $FreeBSD$
30  */
31 
32 #ifndef _DEV_ETHERSWITCH_RTL8366RBVAR_H_
33 #define	_DEV_ETHERSWITCH_RTL8366RBVAR_H_
34 
35 #define	RTL8366RB		0
36 #define	RTL8366SR		1
37 
38 #define RTL8366_IIC_ADDR	0xa8
39 #define RTL_IICBUS_TIMEOUT	100	/* us */
40 #define RTL_IICBUS_READ		1
41 #define	RTL_IICBUS_WRITE	0
42 /* number of times to try and select the chip on the I2C bus */
43 #define RTL_IICBUS_RETRIES	3
44 #define RTL_IICBUS_RETRY_SLEEP	(hz/1000)
45 
46 /* Register definitions */
47 
48 /* Switch Global Configuration */
49 #define RTL8366_SGCR				0x0000
50 #define RTL8366_SGCR_EN_BC_STORM_CTRL		0x0001
51 #define RTL8366_SGCR_MAX_LENGTH_MASK		0x0030
52 #define RTL8366_SGCR_MAX_LENGTH_1522		0x0000
53 #define RTL8366_SGCR_MAX_LENGTH_1536		0x0010
54 #define RTL8366_SGCR_MAX_LENGTH_1552		0x0020
55 #define RTL8366_SGCR_MAX_LENGTH_9216		0x0030
56 #define RTL8366_SGCR_EN_VLAN			0x2000
57 #define RTL8366_SGCR_EN_VLAN_4KTB		0x4000
58 #define RTL8366_SGCR_EN_QOS			0x8000
59 
60 /* Port Enable Control: DISABLE_PORT[5:0] */
61 #define RTL8366_PECR				0x0001
62 
63 /* Switch Security Control 0: DIS_LEARN[5:0] */
64 #define RTL8366_SSCR0				0x0002
65 
66 /* Switch Security Control 1: DIS_AGE[5:0] */
67 #define RTL8366_SSCR1				0x0003
68 
69 /* Switch Security Control 2 */
70 #define RTL8366_SSCR2				0x0004
71 #define RTL8366_SSCR2_DROP_UNKNOWN_DA		0x0001
72 
73 /* Port Link Status: two ports per register */
74 #define RTL8366_PLSR_BASE			(sc->chip_type == 0 ? 0x0014 : 0x0060)
75 #define RTL8366_PLSR_SPEED_MASK	0x03
76 #define RTL8366_PLSR_SPEED_10		0x00
77 #define RTL8366_PLSR_SPEED_100	0x01
78 #define RTL8366_PLSR_SPEED_1000	0x02
79 #define RTL8366_PLSR_FULLDUPLEX	0x04
80 #define RTL8366_PLSR_LINK		0x10
81 #define RTL8366_PLSR_TXPAUSE		0x20
82 #define RTL8366_PLSR_RXPAUSE		0x40
83 #define RTL8366_PLSR_NO_AUTO		0x80
84 
85 /* VLAN Member Configuration, 3 or 2 registers per VLAN */
86 #define RTL8366_VMCR_BASE			(sc->chip_type == 0 ? 0x0020 : 0x0016)
87 #define RTL8366_VMCR_MULT		(sc->chip_type == 0 ? 3 : 2)
88 #define RTL8366_VMCR_DOT1Q_REG	0
89 #define RTL8366_VMCR_DOT1Q_VID_SHIFT	0
90 #define RTL8366_VMCR_DOT1Q_VID_MASK	0x0fff
91 #define RTL8366_VMCR_DOT1Q_PCP_SHIFT	12
92 #define RTL8366_VMCR_DOT1Q_PCP_MASK	0x7000
93 #define RTL8366_VMCR_MU_REG		1
94 #define RTL8366_VMCR_MU_MEMBER_SHIFT	0
95 #define RTL8366_VMCR_MU_MEMBER_MASK	(sc->chip_type == 0 ? 0x00ff : 0x003f)
96 #define RTL8366_VMCR_MU_UNTAG_SHIFT	(sc->chip_type == 0 ? 8 : 6)
97 #define RTL8366_VMCR_MU_UNTAG_MASK	(sc->chip_type == 0 ? 0xff00 : 0x0fc0)
98 #define RTL8366_VMCR_FID_REG		(sc->chip_type == 0 ? 2 : 1)
99 #define RTL8366_VMCR_FID_FID_SHIFT	(sc->chip_type == 0 ? 0 : 12)
100 #define RTL8366_VMCR_FID_FID_MASK	(sc->chip_type == 0 ? 0x0007 : 0x7000)
101 #define RTL8366_VMCR(_reg, _vlan) \
102 	(RTL8366_VMCR_BASE + _reg + _vlan * RTL8366_VMCR_MULT)
103 /* VLAN Identifier */
104 #define RTL8366_VMCR_VID(_r) \
105 	(_r[RTL8366_VMCR_DOT1Q_REG] & RTL8366_VMCR_DOT1Q_VID_MASK)
106 /* Priority Code Point */
107 #define RTL8366_VMCR_PCP(_r) \
108 	((_r[RTL8366_VMCR_DOT1Q_REG] & RTL8366_VMCR_DOT1Q_PCP_MASK) \
109 	>> RTL8366_VMCR_DOT1Q_PCP_SHIFT)
110 /* Member ports */
111 #define RTL8366_VMCR_MEMBER(_r) \
112 	(_r[RTL8366_VMCR_MU_REG] & RTL8366_VMCR_MU_MEMBER_MASK)
113 /* Untagged ports */
114 #define RTL8366_VMCR_UNTAG(_r) \
115 	((_r[RTL8366_VMCR_MU_REG] & RTL8366_VMCR_MU_UNTAG_MASK) \
116 	>> RTL8366_VMCR_MU_UNTAG_SHIFT)
117 /* Forwarding ID */
118 #define RTL8366_VMCR_FID(_r) \
119 	(sc->chip_type == 0 ? (_r[RTL8366_VMCR_FID_REG] & RTL8366_VMCR_FID_FID_MASK) : \
120 		((_r[RTL8366_VMCR_FID_REG] & RTL8366_VMCR_FID_FID_MASK) \
121 		>> RTL8366_VMCR_FID_FID_SHIFT))
122 
123 /*
124  * Port VLAN Control, 4 ports per register
125  * Determines the VID for untagged ingress frames through
126  * index into VMC.
127  */
128 #define RTL8366_PVCR_BASE			(sc->chip_type == 0 ? 0x0063 : 0x0058)
129 #define RTL8366_PVCR_PORT_SHIFT	4
130 #define RTL8366_PVCR_PORT_PERREG	(16 / RTL8366_PVCR_PORT_SHIFT)
131 #define RTL8366_PVCR_PORT_MASK	0x000f
132 #define RTL8366_PVCR_REG(_port) \
133 	(RTL8366_PVCR_BASE + _port / (RTL8366_PVCR_PORT_PERREG))
134 #define RTL8366_PVCR_VAL(_port, _pvlan) \
135 	((_pvlan & RTL8366_PVCR_PORT_MASK) << \
136 	((_port % RTL8366_PVCR_PORT_PERREG) * RTL8366_PVCR_PORT_SHIFT))
137 #define RTL8366_PVCR_GET(_port, _val) \
138 	(((_val) >> ((_port % RTL8366_PVCR_PORT_PERREG) * RTL8366_PVCR_PORT_SHIFT)) & RTL8366_PVCR_PORT_MASK)
139 
140 /* Reset Control */
141 #define RTL8366_RCR				0x0100
142 #define RTL8366_RCR_HARD_RESET	0x0001
143 #define RTL8366_RCR_SOFT_RESET	0x0002
144 
145 /* Chip Version Control: CHIP_VER[3:0] */
146 #define RTL8366_CVCR				(sc->chip_type == 0 ? 0x050A : 0x0104)
147 /* Chip Identifier */
148 #define RTL8366RB_CIR				0x0509
149 #define RTL8366RB_CIR_ID8366RB		0x5937
150 #define RTL8366SR_CIR				0x0105
151 #define RTL8366SR_CIR_ID8366SR		0x8366
152 
153 /* VLAN Ingress Control 2: [5:0] */
154 #define RTL8366_VIC2R				0x037f
155 
156 /* MIB registers */
157 #define RTL8366_MCNT_BASE			0x1000
158 #define RTL8366_MCTLR				(sc->chip_type == 0 ? 0x13f0 : 0x11F0)
159 #define RTL8366_MCTLR_BUSY		0x0001
160 #define RTL8366_MCTLR_RESET		0x0002
161 #define RTL8366_MCTLR_RESET_PORT_MASK	0x00fc
162 #define RTL8366_MCTLR_RESET_ALL	0x0800
163 
164 #define RTL8366_MCNT(_port, _r) \
165 	(RTL8366_MCNT_BASE + 0x50 * (_port) + (_r))
166 #define RTL8366_MCTLR_RESET_PORT(_p) \
167 	(1 << ((_p) + 2))
168 
169 /* PHY Access Control */
170 #define RTL8366_PACR				(sc->chip_type == 0 ? 0x8000 : 0x8028)
171 #define RTL8366_PACR_WRITE		0x0000
172 #define RTL8366_PACR_READ			0x0001
173 
174 /* PHY Access Data */
175 #define	RTL8366_PADR				(sc->chip_type == 0 ? 0x8002 : 0x8029)
176 
177 #define RTL8366_PHYREG(phy, page, reg) \
178 	(0x8000 | (1 << (((phy) & 0x1f) + 9)) | (((page) & (sc->chip_type == 0 ? 0xf : 0x7)) << 5) | ((reg) & 0x1f))
179 
180 /* general characteristics of the chip */
181 #define	RTL8366_NUM_PHYS			5
182 #define	RTL8366_NUM_VLANS			16
183 #define	RTL8366_NUM_PHY_REG			32
184 
185 #endif
186