1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2015-2016 Hiroki Mori. 5 * Copyright (c) 2011-2012 Stefan Bethke. 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 * 29 * $FreeBSD$ 30 */ 31 32 #include "opt_etherswitch.h" 33 34 #include <sys/param.h> 35 #include <sys/bus.h> 36 #include <sys/errno.h> 37 #include <sys/kernel.h> 38 #include <sys/lock.h> 39 #include <sys/malloc.h> 40 #include <sys/module.h> 41 #include <sys/mutex.h> 42 #include <sys/socket.h> 43 #include <sys/sockio.h> 44 #include <sys/sysctl.h> 45 #include <sys/systm.h> 46 47 #include <net/if.h> 48 #include <net/if_var.h> 49 #include <net/ethernet.h> 50 #include <net/if_media.h> 51 #include <net/if_types.h> 52 53 #include <machine/bus.h> 54 #include <dev/iicbus/iic.h> 55 #include <dev/iicbus/iiconf.h> 56 #include <dev/iicbus/iicbus.h> 57 #include <dev/mii/mii.h> 58 #include <dev/mii/miivar.h> 59 #include <dev/mdio/mdio.h> 60 61 #include <dev/etherswitch/etherswitch.h> 62 #include <dev/etherswitch/rtl8366/rtl8366rbvar.h> 63 64 #include "mdio_if.h" 65 #include "iicbus_if.h" 66 #include "miibus_if.h" 67 #include "etherswitch_if.h" 68 69 70 struct rtl8366rb_softc { 71 struct mtx sc_mtx; /* serialize access to softc */ 72 int smi_acquired; /* serialize access to SMI/I2C bus */ 73 struct mtx callout_mtx; /* serialize callout */ 74 device_t dev; 75 int vid[RTL8366_NUM_VLANS]; 76 char *ifname[RTL8366_NUM_PHYS]; 77 device_t miibus[RTL8366_NUM_PHYS]; 78 struct ifnet *ifp[RTL8366_NUM_PHYS]; 79 struct callout callout_tick; 80 etherswitch_info_t info; 81 int chip_type; 82 int phy4cpu; 83 int numphys; 84 }; 85 86 #define RTL_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx) 87 #define RTL_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx) 88 #define RTL_LOCK_ASSERT(_sc, _what) mtx_assert(&(_s)c->sc_mtx, (_what)) 89 #define RTL_TRYLOCK(_sc) mtx_trylock(&(_sc)->sc_mtx) 90 91 #define RTL_WAITOK 0 92 #define RTL_NOWAIT 1 93 94 #define RTL_SMI_ACQUIRED 1 95 #define RTL_SMI_ACQUIRED_ASSERT(_sc) \ 96 KASSERT((_sc)->smi_acquired == RTL_SMI_ACQUIRED, ("smi must be acquired @%s", __FUNCTION__)) 97 98 #if defined(DEBUG) 99 #define DPRINTF(dev, args...) device_printf(dev, args) 100 #define DEVERR(dev, err, fmt, args...) do { \ 101 if (err != 0) device_printf(dev, fmt, err, args); \ 102 } while (0) 103 #define DEBUG_INCRVAR(var) do { \ 104 var++; \ 105 } while (0) 106 107 static int callout_blocked = 0; 108 static int iic_select_retries = 0; 109 static int phy_access_retries = 0; 110 static SYSCTL_NODE(_debug, OID_AUTO, rtl8366rb, CTLFLAG_RD, 0, "rtl8366rb"); 111 SYSCTL_INT(_debug_rtl8366rb, OID_AUTO, callout_blocked, CTLFLAG_RW, &callout_blocked, 0, 112 "number of times the callout couldn't acquire the bus"); 113 SYSCTL_INT(_debug_rtl8366rb, OID_AUTO, iic_select_retries, CTLFLAG_RW, &iic_select_retries, 0, 114 "number of times the I2C bus selection had to be retried"); 115 SYSCTL_INT(_debug_rtl8366rb, OID_AUTO, phy_access_retries, CTLFLAG_RW, &phy_access_retries, 0, 116 "number of times PHY register access had to be retried"); 117 #else 118 #define DPRINTF(dev, args...) 119 #define DEVERR(dev, err, fmt, args...) 120 #define DEBUG_INCRVAR(var) 121 #endif 122 123 static int smi_probe(device_t dev); 124 static int smi_read(device_t dev, uint16_t addr, uint16_t *data, int sleep); 125 static int smi_write(device_t dev, uint16_t addr, uint16_t data, int sleep); 126 static int smi_rmw(device_t dev, uint16_t addr, uint16_t mask, uint16_t data, int sleep); 127 static void rtl8366rb_tick(void *arg); 128 static int rtl8366rb_ifmedia_upd(struct ifnet *); 129 static void rtl8366rb_ifmedia_sts(struct ifnet *, struct ifmediareq *); 130 131 static void 132 rtl8366rb_identify(driver_t *driver, device_t parent) 133 { 134 device_t child; 135 struct iicbus_ivar *devi; 136 137 if (device_find_child(parent, "rtl8366rb", -1) == NULL) { 138 child = BUS_ADD_CHILD(parent, 0, "rtl8366rb", -1); 139 devi = IICBUS_IVAR(child); 140 devi->addr = RTL8366_IIC_ADDR; 141 } 142 } 143 144 static int 145 rtl8366rb_probe(device_t dev) 146 { 147 struct rtl8366rb_softc *sc; 148 149 sc = device_get_softc(dev); 150 151 bzero(sc, sizeof(*sc)); 152 if (smi_probe(dev) != 0) 153 return (ENXIO); 154 if (sc->chip_type == RTL8366RB) 155 device_set_desc(dev, "RTL8366RB Ethernet Switch Controller"); 156 else 157 device_set_desc(dev, "RTL8366SR Ethernet Switch Controller"); 158 return (BUS_PROBE_DEFAULT); 159 } 160 161 static void 162 rtl8366rb_init(device_t dev) 163 { 164 struct rtl8366rb_softc *sc; 165 int i; 166 167 sc = device_get_softc(dev); 168 169 /* Initialisation for TL-WR1043ND */ 170 #ifdef RTL8366_SOFT_RESET 171 smi_rmw(dev, RTL8366_RCR, 172 RTL8366_RCR_SOFT_RESET, 173 RTL8366_RCR_SOFT_RESET, RTL_WAITOK); 174 #else 175 smi_rmw(dev, RTL8366_RCR, 176 RTL8366_RCR_HARD_RESET, 177 RTL8366_RCR_HARD_RESET, RTL_WAITOK); 178 #endif 179 /* hard reset not return ack */ 180 DELAY(100000); 181 /* Enable 16 VLAN mode */ 182 smi_rmw(dev, RTL8366_SGCR, 183 RTL8366_SGCR_EN_VLAN | RTL8366_SGCR_EN_VLAN_4KTB, 184 RTL8366_SGCR_EN_VLAN, RTL_WAITOK); 185 /* Initialize our vlan table. */ 186 for (i = 0; i <= 1; i++) 187 sc->vid[i] = (i + 1) | ETHERSWITCH_VID_VALID; 188 /* Remove port 0 from VLAN 1. */ 189 smi_rmw(dev, RTL8366_VMCR(RTL8366_VMCR_MU_REG, 0), 190 (1 << 0), 0, RTL_WAITOK); 191 /* Add port 0 untagged and port 5 tagged to VLAN 2. */ 192 smi_rmw(dev, RTL8366_VMCR(RTL8366_VMCR_MU_REG, 1), 193 ((1 << 5 | 1 << 0) << RTL8366_VMCR_MU_MEMBER_SHIFT) 194 | ((1 << 5 | 1 << 0) << RTL8366_VMCR_MU_UNTAG_SHIFT), 195 ((1 << 5 | 1 << 0) << RTL8366_VMCR_MU_MEMBER_SHIFT 196 | ((1 << 0) << RTL8366_VMCR_MU_UNTAG_SHIFT)), 197 RTL_WAITOK); 198 /* Set PVID 2 for port 0. */ 199 smi_rmw(dev, RTL8366_PVCR_REG(0), 200 RTL8366_PVCR_VAL(0, RTL8366_PVCR_PORT_MASK), 201 RTL8366_PVCR_VAL(0, 1), RTL_WAITOK); 202 } 203 204 static int 205 rtl8366rb_attach(device_t dev) 206 { 207 struct rtl8366rb_softc *sc; 208 uint16_t rev = 0; 209 char name[IFNAMSIZ]; 210 int err = 0; 211 int i; 212 213 sc = device_get_softc(dev); 214 215 sc->dev = dev; 216 mtx_init(&sc->sc_mtx, "rtl8366rb", NULL, MTX_DEF); 217 sc->smi_acquired = 0; 218 mtx_init(&sc->callout_mtx, "rtl8366rbcallout", NULL, MTX_DEF); 219 220 rtl8366rb_init(dev); 221 smi_read(dev, RTL8366_CVCR, &rev, RTL_WAITOK); 222 device_printf(dev, "rev. %d\n", rev & 0x000f); 223 224 sc->phy4cpu = 0; 225 (void) resource_int_value(device_get_name(dev), device_get_unit(dev), 226 "phy4cpu", &sc->phy4cpu); 227 228 sc->numphys = sc->phy4cpu ? RTL8366_NUM_PHYS - 1 : RTL8366_NUM_PHYS; 229 230 sc->info.es_nports = sc->numphys + 1; 231 sc->info.es_nvlangroups = RTL8366_NUM_VLANS; 232 sc->info.es_vlan_caps = ETHERSWITCH_VLAN_DOT1Q; 233 if (sc->chip_type == RTL8366RB) 234 sprintf(sc->info.es_name, "Realtek RTL8366RB"); 235 else 236 sprintf(sc->info.es_name, "Realtek RTL8366SR"); 237 238 /* attach miibus and phys */ 239 /* PHYs need an interface, so we generate a dummy one */ 240 for (i = 0; i < sc->numphys; i++) { 241 sc->ifp[i] = if_alloc(IFT_ETHER); 242 sc->ifp[i]->if_softc = sc; 243 sc->ifp[i]->if_flags |= IFF_UP | IFF_BROADCAST | IFF_DRV_RUNNING 244 | IFF_SIMPLEX; 245 snprintf(name, IFNAMSIZ, "%sport", device_get_nameunit(dev)); 246 sc->ifname[i] = malloc(strlen(name)+1, M_DEVBUF, M_WAITOK); 247 bcopy(name, sc->ifname[i], strlen(name)+1); 248 if_initname(sc->ifp[i], sc->ifname[i], i); 249 err = mii_attach(dev, &sc->miibus[i], sc->ifp[i], rtl8366rb_ifmedia_upd, \ 250 rtl8366rb_ifmedia_sts, BMSR_DEFCAPMASK, \ 251 i, MII_OFFSET_ANY, 0); 252 if (err != 0) { 253 device_printf(dev, "attaching PHY %d failed\n", i); 254 return (err); 255 } 256 } 257 258 bus_generic_probe(dev); 259 bus_enumerate_hinted_children(dev); 260 err = bus_generic_attach(dev); 261 if (err != 0) 262 return (err); 263 264 callout_init_mtx(&sc->callout_tick, &sc->callout_mtx, 0); 265 rtl8366rb_tick(sc); 266 267 return (err); 268 } 269 270 static int 271 rtl8366rb_detach(device_t dev) 272 { 273 struct rtl8366rb_softc *sc; 274 int i; 275 276 sc = device_get_softc(dev); 277 278 for (i=0; i < sc->numphys; i++) { 279 if (sc->miibus[i]) 280 device_delete_child(dev, sc->miibus[i]); 281 if (sc->ifp[i] != NULL) 282 if_free(sc->ifp[i]); 283 free(sc->ifname[i], M_DEVBUF); 284 } 285 bus_generic_detach(dev); 286 callout_drain(&sc->callout_tick); 287 mtx_destroy(&sc->callout_mtx); 288 mtx_destroy(&sc->sc_mtx); 289 290 return (0); 291 } 292 293 static void 294 rtl8366rb_update_ifmedia(int portstatus, u_int *media_status, u_int *media_active) 295 { 296 *media_active = IFM_ETHER; 297 *media_status = IFM_AVALID; 298 if ((portstatus & RTL8366_PLSR_LINK) != 0) 299 *media_status |= IFM_ACTIVE; 300 else { 301 *media_active |= IFM_NONE; 302 return; 303 } 304 switch (portstatus & RTL8366_PLSR_SPEED_MASK) { 305 case RTL8366_PLSR_SPEED_10: 306 *media_active |= IFM_10_T; 307 break; 308 case RTL8366_PLSR_SPEED_100: 309 *media_active |= IFM_100_TX; 310 break; 311 case RTL8366_PLSR_SPEED_1000: 312 *media_active |= IFM_1000_T; 313 break; 314 } 315 if ((portstatus & RTL8366_PLSR_FULLDUPLEX) != 0) 316 *media_active |= IFM_FDX; 317 else 318 *media_active |= IFM_HDX; 319 if ((portstatus & RTL8366_PLSR_TXPAUSE) != 0) 320 *media_active |= IFM_ETH_TXPAUSE; 321 if ((portstatus & RTL8366_PLSR_RXPAUSE) != 0) 322 *media_active |= IFM_ETH_RXPAUSE; 323 } 324 325 static void 326 rtl833rb_miipollstat(struct rtl8366rb_softc *sc) 327 { 328 int i; 329 struct mii_data *mii; 330 struct mii_softc *miisc; 331 uint16_t value; 332 int portstatus; 333 334 for (i = 0; i < sc->numphys; i++) { 335 mii = device_get_softc(sc->miibus[i]); 336 if ((i % 2) == 0) { 337 if (smi_read(sc->dev, RTL8366_PLSR_BASE + i/2, &value, RTL_NOWAIT) != 0) { 338 DEBUG_INCRVAR(callout_blocked); 339 return; 340 } 341 portstatus = value & 0xff; 342 } else { 343 portstatus = (value >> 8) & 0xff; 344 } 345 rtl8366rb_update_ifmedia(portstatus, &mii->mii_media_status, &mii->mii_media_active); 346 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) { 347 if (IFM_INST(mii->mii_media.ifm_cur->ifm_media) != miisc->mii_inst) 348 continue; 349 mii_phy_update(miisc, MII_POLLSTAT); 350 } 351 } 352 } 353 354 static void 355 rtl8366rb_tick(void *arg) 356 { 357 struct rtl8366rb_softc *sc; 358 359 sc = arg; 360 361 rtl833rb_miipollstat(sc); 362 callout_reset(&sc->callout_tick, hz, rtl8366rb_tick, sc); 363 } 364 365 static int 366 smi_probe(device_t dev) 367 { 368 struct rtl8366rb_softc *sc; 369 device_t iicbus, iicha; 370 int err, i, j; 371 uint16_t chipid; 372 char bytes[2]; 373 int xferd; 374 375 sc = device_get_softc(dev); 376 377 iicbus = device_get_parent(dev); 378 iicha = device_get_parent(iicbus); 379 380 for (i = 0; i < 2; ++i) { 381 iicbus_reset(iicbus, IIC_FASTEST, RTL8366_IIC_ADDR, NULL); 382 for (j=3; j--; ) { 383 IICBUS_STOP(iicha); 384 /* 385 * we go directly to the host adapter because iicbus.c 386 * only issues a stop on a bus that was successfully started. 387 */ 388 } 389 err = iicbus_request_bus(iicbus, dev, IIC_WAIT); 390 if (err != 0) 391 goto out; 392 err = iicbus_start(iicbus, RTL8366_IIC_ADDR | RTL_IICBUS_READ, RTL_IICBUS_TIMEOUT); 393 if (err != 0) 394 goto out; 395 if (i == 0) { 396 bytes[0] = RTL8366RB_CIR & 0xff; 397 bytes[1] = (RTL8366RB_CIR >> 8) & 0xff; 398 } else { 399 bytes[0] = RTL8366SR_CIR & 0xff; 400 bytes[1] = (RTL8366SR_CIR >> 8) & 0xff; 401 } 402 err = iicbus_write(iicbus, bytes, 2, &xferd, RTL_IICBUS_TIMEOUT); 403 if (err != 0) 404 goto out; 405 err = iicbus_read(iicbus, bytes, 2, &xferd, IIC_LAST_READ, 0); 406 if (err != 0) 407 goto out; 408 chipid = ((bytes[1] & 0xff) << 8) | (bytes[0] & 0xff); 409 if (i == 0 && chipid == RTL8366RB_CIR_ID8366RB) { 410 DPRINTF(dev, "chip id 0x%04x\n", chipid); 411 sc->chip_type = RTL8366RB; 412 err = 0; 413 break; 414 } 415 if (i == 1 && chipid == RTL8366SR_CIR_ID8366SR) { 416 DPRINTF(dev, "chip id 0x%04x\n", chipid); 417 sc->chip_type = RTL8366SR; 418 err = 0; 419 break; 420 } 421 if (i == 0) { 422 iicbus_stop(iicbus); 423 iicbus_release_bus(iicbus, dev); 424 } 425 } 426 if (i == 2) 427 err = ENXIO; 428 out: 429 iicbus_stop(iicbus); 430 iicbus_release_bus(iicbus, dev); 431 return (err == 0 ? 0 : ENXIO); 432 } 433 434 static int 435 smi_acquire(struct rtl8366rb_softc *sc, int sleep) 436 { 437 int r = 0; 438 if (sleep == RTL_WAITOK) 439 RTL_LOCK(sc); 440 else 441 if (RTL_TRYLOCK(sc) == 0) 442 return (EWOULDBLOCK); 443 if (sc->smi_acquired == RTL_SMI_ACQUIRED) 444 r = EBUSY; 445 else { 446 r = iicbus_request_bus(device_get_parent(sc->dev), sc->dev, \ 447 sleep == RTL_WAITOK ? IIC_WAIT : IIC_DONTWAIT); 448 if (r == 0) 449 sc->smi_acquired = RTL_SMI_ACQUIRED; 450 } 451 RTL_UNLOCK(sc); 452 return (r); 453 } 454 455 static int 456 smi_release(struct rtl8366rb_softc *sc, int sleep) 457 { 458 if (sleep == RTL_WAITOK) 459 RTL_LOCK(sc); 460 else 461 if (RTL_TRYLOCK(sc) == 0) 462 return (EWOULDBLOCK); 463 RTL_SMI_ACQUIRED_ASSERT(sc); 464 iicbus_release_bus(device_get_parent(sc->dev), sc->dev); 465 sc->smi_acquired = 0; 466 RTL_UNLOCK(sc); 467 return (0); 468 } 469 470 static int 471 smi_select(device_t dev, int op, int sleep) 472 { 473 struct rtl8366rb_softc *sc; 474 int err, i; 475 device_t iicbus; 476 struct iicbus_ivar *devi; 477 int slave; 478 479 sc = device_get_softc(dev); 480 481 iicbus = device_get_parent(dev); 482 devi = IICBUS_IVAR(dev); 483 slave = devi->addr; 484 485 RTL_SMI_ACQUIRED_ASSERT((struct rtl8366rb_softc *)device_get_softc(dev)); 486 487 if (sc->chip_type == RTL8366SR) { // RTL8366SR work around 488 // this is same work around at probe 489 for (int i=3; i--; ) 490 IICBUS_STOP(device_get_parent(device_get_parent(dev))); 491 } 492 /* 493 * The chip does not use clock stretching when it is busy, 494 * instead ignoring the command. Retry a few times. 495 */ 496 for (i = RTL_IICBUS_RETRIES; i--; ) { 497 err = iicbus_start(iicbus, slave | op, RTL_IICBUS_TIMEOUT); 498 if (err != IIC_ENOACK) 499 break; 500 if (sleep == RTL_WAITOK) { 501 DEBUG_INCRVAR(iic_select_retries); 502 pause("smi_select", RTL_IICBUS_RETRY_SLEEP); 503 } else 504 break; 505 } 506 return (err); 507 } 508 509 static int 510 smi_read_locked(struct rtl8366rb_softc *sc, uint16_t addr, uint16_t *data, int sleep) 511 { 512 int err; 513 device_t iicbus; 514 char bytes[2]; 515 int xferd; 516 517 iicbus = device_get_parent(sc->dev); 518 519 RTL_SMI_ACQUIRED_ASSERT(sc); 520 bytes[0] = addr & 0xff; 521 bytes[1] = (addr >> 8) & 0xff; 522 err = smi_select(sc->dev, RTL_IICBUS_READ, sleep); 523 if (err != 0) 524 goto out; 525 err = iicbus_write(iicbus, bytes, 2, &xferd, RTL_IICBUS_TIMEOUT); 526 if (err != 0) 527 goto out; 528 err = iicbus_read(iicbus, bytes, 2, &xferd, IIC_LAST_READ, 0); 529 if (err != 0) 530 goto out; 531 *data = ((bytes[1] & 0xff) << 8) | (bytes[0] & 0xff); 532 533 out: 534 iicbus_stop(iicbus); 535 return (err); 536 } 537 538 static int 539 smi_write_locked(struct rtl8366rb_softc *sc, uint16_t addr, uint16_t data, int sleep) 540 { 541 int err; 542 device_t iicbus; 543 char bytes[4]; 544 int xferd; 545 546 iicbus = device_get_parent(sc->dev); 547 548 RTL_SMI_ACQUIRED_ASSERT(sc); 549 bytes[0] = addr & 0xff; 550 bytes[1] = (addr >> 8) & 0xff; 551 bytes[2] = data & 0xff; 552 bytes[3] = (data >> 8) & 0xff; 553 554 err = smi_select(sc->dev, RTL_IICBUS_WRITE, sleep); 555 if (err == 0) 556 err = iicbus_write(iicbus, bytes, 4, &xferd, RTL_IICBUS_TIMEOUT); 557 iicbus_stop(iicbus); 558 559 return (err); 560 } 561 562 static int 563 smi_read(device_t dev, uint16_t addr, uint16_t *data, int sleep) 564 { 565 struct rtl8366rb_softc *sc; 566 int err; 567 568 sc = device_get_softc(dev); 569 570 err = smi_acquire(sc, sleep); 571 if (err != 0) 572 return (EBUSY); 573 err = smi_read_locked(sc, addr, data, sleep); 574 smi_release(sc, sleep); 575 DEVERR(dev, err, "smi_read()=%d: addr=%04x\n", addr); 576 return (err == 0 ? 0 : EIO); 577 } 578 579 static int 580 smi_write(device_t dev, uint16_t addr, uint16_t data, int sleep) 581 { 582 struct rtl8366rb_softc *sc; 583 int err; 584 585 sc = device_get_softc(dev); 586 587 err = smi_acquire(sc, sleep); 588 if (err != 0) 589 return (EBUSY); 590 err = smi_write_locked(sc, addr, data, sleep); 591 smi_release(sc, sleep); 592 DEVERR(dev, err, "smi_write()=%d: addr=%04x\n", addr); 593 return (err == 0 ? 0 : EIO); 594 } 595 596 static int 597 smi_rmw(device_t dev, uint16_t addr, uint16_t mask, uint16_t data, int sleep) 598 { 599 struct rtl8366rb_softc *sc; 600 int err; 601 uint16_t oldv, newv; 602 603 sc = device_get_softc(dev); 604 605 err = smi_acquire(sc, sleep); 606 if (err != 0) 607 return (EBUSY); 608 if (err == 0) { 609 err = smi_read_locked(sc, addr, &oldv, sleep); 610 if (err == 0) { 611 newv = oldv & ~mask; 612 newv |= data & mask; 613 if (newv != oldv) 614 err = smi_write_locked(sc, addr, newv, sleep); 615 } 616 } 617 smi_release(sc, sleep); 618 DEVERR(dev, err, "smi_rmw()=%d: addr=%04x\n", addr); 619 return (err == 0 ? 0 : EIO); 620 } 621 622 static etherswitch_info_t * 623 rtl_getinfo(device_t dev) 624 { 625 struct rtl8366rb_softc *sc; 626 627 sc = device_get_softc(dev); 628 629 return (&sc->info); 630 } 631 632 static int 633 rtl_readreg(device_t dev, int reg) 634 { 635 uint16_t data; 636 637 data = 0; 638 639 smi_read(dev, reg, &data, RTL_WAITOK); 640 return (data); 641 } 642 643 static int 644 rtl_writereg(device_t dev, int reg, int value) 645 { 646 return (smi_write(dev, reg, value, RTL_WAITOK)); 647 } 648 649 static int 650 rtl_getport(device_t dev, etherswitch_port_t *p) 651 { 652 struct rtl8366rb_softc *sc; 653 struct ifmedia *ifm; 654 struct mii_data *mii; 655 struct ifmediareq *ifmr; 656 uint16_t v; 657 int err, vlangroup; 658 659 sc = device_get_softc(dev); 660 661 ifmr = &p->es_ifmr; 662 663 if (p->es_port < 0 || p->es_port >= (sc->numphys + 1)) 664 return (ENXIO); 665 if (sc->phy4cpu && p->es_port == sc->numphys) { 666 vlangroup = RTL8366_PVCR_GET(p->es_port + 1, 667 rtl_readreg(dev, RTL8366_PVCR_REG(p->es_port + 1))); 668 } else { 669 vlangroup = RTL8366_PVCR_GET(p->es_port, 670 rtl_readreg(dev, RTL8366_PVCR_REG(p->es_port))); 671 } 672 p->es_pvid = sc->vid[vlangroup] & ETHERSWITCH_VID_MASK; 673 674 if (p->es_port < sc->numphys) { 675 mii = device_get_softc(sc->miibus[p->es_port]); 676 ifm = &mii->mii_media; 677 err = ifmedia_ioctl(sc->ifp[p->es_port], &p->es_ifr, ifm, SIOCGIFMEDIA); 678 if (err) 679 return (err); 680 } else { 681 /* fill in fixed values for CPU port */ 682 p->es_flags |= ETHERSWITCH_PORT_CPU; 683 smi_read(dev, RTL8366_PLSR_BASE + (RTL8366_NUM_PHYS)/2, &v, RTL_WAITOK); 684 v = v >> (8 * ((RTL8366_NUM_PHYS) % 2)); 685 rtl8366rb_update_ifmedia(v, &ifmr->ifm_status, &ifmr->ifm_active); 686 ifmr->ifm_current = ifmr->ifm_active; 687 ifmr->ifm_mask = 0; 688 ifmr->ifm_status = IFM_ACTIVE | IFM_AVALID; 689 /* Return our static media list. */ 690 if (ifmr->ifm_count > 0) { 691 ifmr->ifm_count = 1; 692 ifmr->ifm_ulist[0] = IFM_MAKEWORD(IFM_ETHER, IFM_1000_T, 693 IFM_FDX, 0); 694 } else 695 ifmr->ifm_count = 0; 696 } 697 return (0); 698 } 699 700 static int 701 rtl_setport(device_t dev, etherswitch_port_t *p) 702 { 703 struct rtl8366rb_softc *sc; 704 int i, err, vlangroup; 705 struct ifmedia *ifm; 706 struct mii_data *mii; 707 int port; 708 709 sc = device_get_softc(dev); 710 711 if (p->es_port < 0 || p->es_port >= (sc->numphys + 1)) 712 return (ENXIO); 713 vlangroup = -1; 714 for (i = 0; i < RTL8366_NUM_VLANS; i++) { 715 if ((sc->vid[i] & ETHERSWITCH_VID_MASK) == p->es_pvid) { 716 vlangroup = i; 717 break; 718 } 719 } 720 if (vlangroup == -1) 721 return (ENXIO); 722 if (sc->phy4cpu && p->es_port == sc->numphys) { 723 port = p->es_port + 1; 724 } else { 725 port = p->es_port; 726 } 727 err = smi_rmw(dev, RTL8366_PVCR_REG(port), 728 RTL8366_PVCR_VAL(port, RTL8366_PVCR_PORT_MASK), 729 RTL8366_PVCR_VAL(port, vlangroup), RTL_WAITOK); 730 if (err) 731 return (err); 732 /* CPU Port */ 733 if (p->es_port == sc->numphys) 734 return (0); 735 mii = device_get_softc(sc->miibus[p->es_port]); 736 ifm = &mii->mii_media; 737 err = ifmedia_ioctl(sc->ifp[p->es_port], &p->es_ifr, ifm, SIOCSIFMEDIA); 738 return (err); 739 } 740 741 static int 742 rtl_getvgroup(device_t dev, etherswitch_vlangroup_t *vg) 743 { 744 struct rtl8366rb_softc *sc; 745 uint16_t vmcr[3]; 746 int i; 747 int member, untagged; 748 749 sc = device_get_softc(dev); 750 751 for (i=0; i<RTL8366_VMCR_MULT; i++) 752 vmcr[i] = rtl_readreg(dev, RTL8366_VMCR(i, vg->es_vlangroup)); 753 754 vg->es_vid = sc->vid[vg->es_vlangroup]; 755 member = RTL8366_VMCR_MEMBER(vmcr); 756 untagged = RTL8366_VMCR_UNTAG(vmcr); 757 if (sc->phy4cpu) { 758 vg->es_member_ports = ((member & 0x20) >> 1) | (member & 0x0f); 759 vg->es_untagged_ports = ((untagged & 0x20) >> 1) | (untagged & 0x0f); 760 } else { 761 vg->es_member_ports = member; 762 vg->es_untagged_ports = untagged; 763 } 764 vg->es_fid = RTL8366_VMCR_FID(vmcr); 765 return (0); 766 } 767 768 static int 769 rtl_setvgroup(device_t dev, etherswitch_vlangroup_t *vg) 770 { 771 struct rtl8366rb_softc *sc; 772 int g; 773 int member, untagged; 774 775 sc = device_get_softc(dev); 776 777 g = vg->es_vlangroup; 778 779 sc->vid[g] = vg->es_vid; 780 /* VLAN group disabled ? */ 781 if (vg->es_member_ports == 0 && vg->es_untagged_ports == 0 && vg->es_vid == 0) 782 return (0); 783 sc->vid[g] |= ETHERSWITCH_VID_VALID; 784 rtl_writereg(dev, RTL8366_VMCR(RTL8366_VMCR_DOT1Q_REG, g), 785 (vg->es_vid << RTL8366_VMCR_DOT1Q_VID_SHIFT) & RTL8366_VMCR_DOT1Q_VID_MASK); 786 if (sc->phy4cpu) { 787 /* add space at phy4 */ 788 member = (vg->es_member_ports & 0x0f) | 789 ((vg->es_member_ports & 0x10) << 1); 790 untagged = (vg->es_untagged_ports & 0x0f) | 791 ((vg->es_untagged_ports & 0x10) << 1); 792 } else { 793 member = vg->es_member_ports; 794 untagged = vg->es_untagged_ports; 795 } 796 if (sc->chip_type == RTL8366RB) { 797 rtl_writereg(dev, RTL8366_VMCR(RTL8366_VMCR_MU_REG, g), 798 ((member << RTL8366_VMCR_MU_MEMBER_SHIFT) & RTL8366_VMCR_MU_MEMBER_MASK) | 799 ((untagged << RTL8366_VMCR_MU_UNTAG_SHIFT) & RTL8366_VMCR_MU_UNTAG_MASK)); 800 rtl_writereg(dev, RTL8366_VMCR(RTL8366_VMCR_FID_REG, g), 801 vg->es_fid); 802 } else { 803 rtl_writereg(dev, RTL8366_VMCR(RTL8366_VMCR_MU_REG, g), 804 ((member << RTL8366_VMCR_MU_MEMBER_SHIFT) & RTL8366_VMCR_MU_MEMBER_MASK) | 805 ((untagged << RTL8366_VMCR_MU_UNTAG_SHIFT) & RTL8366_VMCR_MU_UNTAG_MASK) | 806 ((vg->es_fid << RTL8366_VMCR_FID_FID_SHIFT) & RTL8366_VMCR_FID_FID_MASK)); 807 } 808 return (0); 809 } 810 811 static int 812 rtl_getconf(device_t dev, etherswitch_conf_t *conf) 813 { 814 815 /* Return the VLAN mode. */ 816 conf->cmd = ETHERSWITCH_CONF_VLAN_MODE; 817 conf->vlan_mode = ETHERSWITCH_VLAN_DOT1Q; 818 819 return (0); 820 } 821 822 static int 823 rtl_readphy(device_t dev, int phy, int reg) 824 { 825 struct rtl8366rb_softc *sc; 826 uint16_t data; 827 int err, i, sleep; 828 829 sc = device_get_softc(dev); 830 831 data = 0; 832 833 if (phy < 0 || phy >= RTL8366_NUM_PHYS) 834 return (ENXIO); 835 if (reg < 0 || reg >= RTL8366_NUM_PHY_REG) 836 return (ENXIO); 837 sleep = RTL_WAITOK; 838 err = smi_acquire(sc, sleep); 839 if (err != 0) 840 return (EBUSY); 841 for (i = RTL_IICBUS_RETRIES; i--; ) { 842 err = smi_write_locked(sc, RTL8366_PACR, RTL8366_PACR_READ, sleep); 843 if (err == 0) 844 err = smi_write_locked(sc, RTL8366_PHYREG(phy, 0, reg), 0, sleep); 845 if (err == 0) { 846 err = smi_read_locked(sc, RTL8366_PADR, &data, sleep); 847 break; 848 } 849 DEBUG_INCRVAR(phy_access_retries); 850 DPRINTF(dev, "rtl_readphy(): chip not responsive, retrying %d more times\n", i); 851 pause("rtl_readphy", RTL_IICBUS_RETRY_SLEEP); 852 } 853 smi_release(sc, sleep); 854 DEVERR(dev, err, "rtl_readphy()=%d: phy=%d.%02x\n", phy, reg); 855 return (data); 856 } 857 858 static int 859 rtl_writephy(device_t dev, int phy, int reg, int data) 860 { 861 struct rtl8366rb_softc *sc; 862 int err, i, sleep; 863 864 sc = device_get_softc(dev); 865 866 if (phy < 0 || phy >= RTL8366_NUM_PHYS) 867 return (ENXIO); 868 if (reg < 0 || reg >= RTL8366_NUM_PHY_REG) 869 return (ENXIO); 870 sleep = RTL_WAITOK; 871 err = smi_acquire(sc, sleep); 872 if (err != 0) 873 return (EBUSY); 874 for (i = RTL_IICBUS_RETRIES; i--; ) { 875 err = smi_write_locked(sc, RTL8366_PACR, RTL8366_PACR_WRITE, sleep); 876 if (err == 0) 877 err = smi_write_locked(sc, RTL8366_PHYREG(phy, 0, reg), data, sleep); 878 if (err == 0) { 879 break; 880 } 881 DEBUG_INCRVAR(phy_access_retries); 882 DPRINTF(dev, "rtl_writephy(): chip not responsive, retrying %d more tiems\n", i); 883 pause("rtl_writephy", RTL_IICBUS_RETRY_SLEEP); 884 } 885 smi_release(sc, sleep); 886 DEVERR(dev, err, "rtl_writephy()=%d: phy=%d.%02x\n", phy, reg); 887 return (err == 0 ? 0 : EIO); 888 } 889 890 static int 891 rtl8366rb_ifmedia_upd(struct ifnet *ifp) 892 { 893 struct rtl8366rb_softc *sc; 894 struct mii_data *mii; 895 896 sc = ifp->if_softc; 897 mii = device_get_softc(sc->miibus[ifp->if_dunit]); 898 899 mii_mediachg(mii); 900 return (0); 901 } 902 903 static void 904 rtl8366rb_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 905 { 906 struct rtl8366rb_softc *sc; 907 struct mii_data *mii; 908 909 sc = ifp->if_softc; 910 mii = device_get_softc(sc->miibus[ifp->if_dunit]); 911 912 mii_pollstat(mii); 913 ifmr->ifm_active = mii->mii_media_active; 914 ifmr->ifm_status = mii->mii_media_status; 915 } 916 917 918 static device_method_t rtl8366rb_methods[] = { 919 /* Device interface */ 920 DEVMETHOD(device_identify, rtl8366rb_identify), 921 DEVMETHOD(device_probe, rtl8366rb_probe), 922 DEVMETHOD(device_attach, rtl8366rb_attach), 923 DEVMETHOD(device_detach, rtl8366rb_detach), 924 925 /* bus interface */ 926 DEVMETHOD(bus_add_child, device_add_child_ordered), 927 928 /* MII interface */ 929 DEVMETHOD(miibus_readreg, rtl_readphy), 930 DEVMETHOD(miibus_writereg, rtl_writephy), 931 932 /* MDIO interface */ 933 DEVMETHOD(mdio_readreg, rtl_readphy), 934 DEVMETHOD(mdio_writereg, rtl_writephy), 935 936 /* etherswitch interface */ 937 DEVMETHOD(etherswitch_getconf, rtl_getconf), 938 DEVMETHOD(etherswitch_getinfo, rtl_getinfo), 939 DEVMETHOD(etherswitch_readreg, rtl_readreg), 940 DEVMETHOD(etherswitch_writereg, rtl_writereg), 941 DEVMETHOD(etherswitch_readphyreg, rtl_readphy), 942 DEVMETHOD(etherswitch_writephyreg, rtl_writephy), 943 DEVMETHOD(etherswitch_getport, rtl_getport), 944 DEVMETHOD(etherswitch_setport, rtl_setport), 945 DEVMETHOD(etherswitch_getvgroup, rtl_getvgroup), 946 DEVMETHOD(etherswitch_setvgroup, rtl_setvgroup), 947 948 DEVMETHOD_END 949 }; 950 951 DEFINE_CLASS_0(rtl8366rb, rtl8366rb_driver, rtl8366rb_methods, 952 sizeof(struct rtl8366rb_softc)); 953 static devclass_t rtl8366rb_devclass; 954 955 DRIVER_MODULE(rtl8366rb, iicbus, rtl8366rb_driver, rtl8366rb_devclass, 0, 0); 956 DRIVER_MODULE(miibus, rtl8366rb, miibus_driver, miibus_devclass, 0, 0); 957 DRIVER_MODULE(mdio, rtl8366rb, mdio_driver, mdio_devclass, 0, 0); 958 DRIVER_MODULE(etherswitch, rtl8366rb, etherswitch_driver, etherswitch_devclass, 0, 0); 959 MODULE_VERSION(rtl8366rb, 1); 960 MODULE_DEPEND(rtl8366rb, iicbus, 1, 1, 1); /* XXX which versions? */ 961 MODULE_DEPEND(rtl8366rb, miibus, 1, 1, 1); /* XXX which versions? */ 962 MODULE_DEPEND(rtl8366rb, etherswitch, 1, 1, 1); /* XXX which versions? */ 963