1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2015-2016 Hiroki Mori. 5 * Copyright (c) 2011-2012 Stefan Bethke. 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30 #include "opt_etherswitch.h" 31 32 #include <sys/param.h> 33 #include <sys/bus.h> 34 #include <sys/errno.h> 35 #include <sys/kernel.h> 36 #include <sys/lock.h> 37 #include <sys/malloc.h> 38 #include <sys/module.h> 39 #include <sys/mutex.h> 40 #include <sys/socket.h> 41 #include <sys/sockio.h> 42 #include <sys/sysctl.h> 43 #include <sys/systm.h> 44 45 #include <net/if.h> 46 #include <net/if_var.h> 47 #include <net/ethernet.h> 48 #include <net/if_media.h> 49 #include <net/if_types.h> 50 51 #include <machine/bus.h> 52 #include <dev/iicbus/iic.h> 53 #include <dev/iicbus/iiconf.h> 54 #include <dev/iicbus/iicbus.h> 55 #include <dev/mii/mii.h> 56 #include <dev/mii/miivar.h> 57 #include <dev/mdio/mdio.h> 58 59 #include <dev/etherswitch/etherswitch.h> 60 #include <dev/etherswitch/rtl8366/rtl8366rbvar.h> 61 62 #include "mdio_if.h" 63 #include "iicbus_if.h" 64 #include "miibus_if.h" 65 #include "etherswitch_if.h" 66 67 68 struct rtl8366rb_softc { 69 struct mtx sc_mtx; /* serialize access to softc */ 70 int smi_acquired; /* serialize access to SMI/I2C bus */ 71 struct mtx callout_mtx; /* serialize callout */ 72 device_t dev; 73 int vid[RTL8366_NUM_VLANS]; 74 char *ifname[RTL8366_NUM_PHYS]; 75 device_t miibus[RTL8366_NUM_PHYS]; 76 if_t ifp[RTL8366_NUM_PHYS]; 77 struct callout callout_tick; 78 etherswitch_info_t info; 79 int chip_type; 80 int phy4cpu; 81 int numphys; 82 }; 83 84 #define RTL_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx) 85 #define RTL_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx) 86 #define RTL_LOCK_ASSERT(_sc, _what) mtx_assert(&(_s)c->sc_mtx, (_what)) 87 #define RTL_TRYLOCK(_sc) mtx_trylock(&(_sc)->sc_mtx) 88 89 #define RTL_WAITOK 0 90 #define RTL_NOWAIT 1 91 92 #define RTL_SMI_ACQUIRED 1 93 #define RTL_SMI_ACQUIRED_ASSERT(_sc) \ 94 KASSERT((_sc)->smi_acquired == RTL_SMI_ACQUIRED, ("smi must be acquired @%s", __FUNCTION__)) 95 96 #if defined(DEBUG) 97 #define DPRINTF(dev, args...) device_printf(dev, args) 98 #define DEVERR(dev, err, fmt, args...) do { \ 99 if (err != 0) device_printf(dev, fmt, err, args); \ 100 } while (0) 101 #define DEBUG_INCRVAR(var) do { \ 102 var++; \ 103 } while (0) 104 105 static int callout_blocked = 0; 106 static int iic_select_retries = 0; 107 static int phy_access_retries = 0; 108 static SYSCTL_NODE(_debug, OID_AUTO, rtl8366rb, CTLFLAG_RD | CTLFLAG_MPSAFE, 0, 109 "rtl8366rb"); 110 SYSCTL_INT(_debug_rtl8366rb, OID_AUTO, callout_blocked, CTLFLAG_RW, &callout_blocked, 0, 111 "number of times the callout couldn't acquire the bus"); 112 SYSCTL_INT(_debug_rtl8366rb, OID_AUTO, iic_select_retries, CTLFLAG_RW, &iic_select_retries, 0, 113 "number of times the I2C bus selection had to be retried"); 114 SYSCTL_INT(_debug_rtl8366rb, OID_AUTO, phy_access_retries, CTLFLAG_RW, &phy_access_retries, 0, 115 "number of times PHY register access had to be retried"); 116 #else 117 #define DPRINTF(dev, args...) 118 #define DEVERR(dev, err, fmt, args...) 119 #define DEBUG_INCRVAR(var) 120 #endif 121 122 static int smi_probe(device_t dev); 123 static int smi_read(device_t dev, uint16_t addr, uint16_t *data, int sleep); 124 static int smi_write(device_t dev, uint16_t addr, uint16_t data, int sleep); 125 static int smi_rmw(device_t dev, uint16_t addr, uint16_t mask, uint16_t data, int sleep); 126 static void rtl8366rb_tick(void *arg); 127 static int rtl8366rb_ifmedia_upd(if_t); 128 static void rtl8366rb_ifmedia_sts(if_t, struct ifmediareq *); 129 130 static void 131 rtl8366rb_identify(driver_t *driver, device_t parent) 132 { 133 device_t child; 134 struct iicbus_ivar *devi; 135 136 if (device_find_child(parent, "rtl8366rb", -1) == NULL) { 137 child = BUS_ADD_CHILD(parent, 0, "rtl8366rb", DEVICE_UNIT_ANY); 138 devi = IICBUS_IVAR(child); 139 devi->addr = RTL8366_IIC_ADDR; 140 } 141 } 142 143 static int 144 rtl8366rb_probe(device_t dev) 145 { 146 struct rtl8366rb_softc *sc; 147 148 sc = device_get_softc(dev); 149 150 bzero(sc, sizeof(*sc)); 151 if (smi_probe(dev) != 0) 152 return (ENXIO); 153 if (sc->chip_type == RTL8366RB) 154 device_set_desc(dev, "RTL8366RB Ethernet Switch Controller"); 155 else 156 device_set_desc(dev, "RTL8366SR Ethernet Switch Controller"); 157 return (BUS_PROBE_DEFAULT); 158 } 159 160 static void 161 rtl8366rb_init(device_t dev) 162 { 163 struct rtl8366rb_softc *sc; 164 int i; 165 166 sc = device_get_softc(dev); 167 168 /* Initialisation for TL-WR1043ND */ 169 #ifdef RTL8366_SOFT_RESET 170 smi_rmw(dev, RTL8366_RCR, 171 RTL8366_RCR_SOFT_RESET, 172 RTL8366_RCR_SOFT_RESET, RTL_WAITOK); 173 #else 174 smi_rmw(dev, RTL8366_RCR, 175 RTL8366_RCR_HARD_RESET, 176 RTL8366_RCR_HARD_RESET, RTL_WAITOK); 177 #endif 178 /* hard reset not return ack */ 179 DELAY(100000); 180 /* Enable 16 VLAN mode */ 181 smi_rmw(dev, RTL8366_SGCR, 182 RTL8366_SGCR_EN_VLAN | RTL8366_SGCR_EN_VLAN_4KTB, 183 RTL8366_SGCR_EN_VLAN, RTL_WAITOK); 184 /* Initialize our vlan table. */ 185 for (i = 0; i <= 1; i++) 186 sc->vid[i] = (i + 1) | ETHERSWITCH_VID_VALID; 187 /* Remove port 0 from VLAN 1. */ 188 smi_rmw(dev, RTL8366_VMCR(RTL8366_VMCR_MU_REG, 0), 189 (1 << 0), 0, RTL_WAITOK); 190 /* Add port 0 untagged and port 5 tagged to VLAN 2. */ 191 smi_rmw(dev, RTL8366_VMCR(RTL8366_VMCR_MU_REG, 1), 192 ((1 << 5 | 1 << 0) << RTL8366_VMCR_MU_MEMBER_SHIFT) 193 | ((1 << 5 | 1 << 0) << RTL8366_VMCR_MU_UNTAG_SHIFT), 194 ((1 << 5 | 1 << 0) << RTL8366_VMCR_MU_MEMBER_SHIFT 195 | ((1 << 0) << RTL8366_VMCR_MU_UNTAG_SHIFT)), 196 RTL_WAITOK); 197 /* Set PVID 2 for port 0. */ 198 smi_rmw(dev, RTL8366_PVCR_REG(0), 199 RTL8366_PVCR_VAL(0, RTL8366_PVCR_PORT_MASK), 200 RTL8366_PVCR_VAL(0, 1), RTL_WAITOK); 201 } 202 203 static int 204 rtl8366rb_attach(device_t dev) 205 { 206 struct rtl8366rb_softc *sc; 207 uint16_t rev = 0; 208 char name[IFNAMSIZ]; 209 int err = 0; 210 int i; 211 212 sc = device_get_softc(dev); 213 214 sc->dev = dev; 215 mtx_init(&sc->sc_mtx, "rtl8366rb", NULL, MTX_DEF); 216 sc->smi_acquired = 0; 217 mtx_init(&sc->callout_mtx, "rtl8366rbcallout", NULL, MTX_DEF); 218 219 rtl8366rb_init(dev); 220 smi_read(dev, RTL8366_CVCR, &rev, RTL_WAITOK); 221 device_printf(dev, "rev. %d\n", rev & 0x000f); 222 223 sc->phy4cpu = 0; 224 (void) resource_int_value(device_get_name(dev), device_get_unit(dev), 225 "phy4cpu", &sc->phy4cpu); 226 227 sc->numphys = sc->phy4cpu ? RTL8366_NUM_PHYS - 1 : RTL8366_NUM_PHYS; 228 229 sc->info.es_nports = sc->numphys + 1; 230 sc->info.es_nvlangroups = RTL8366_NUM_VLANS; 231 sc->info.es_vlan_caps = ETHERSWITCH_VLAN_DOT1Q; 232 if (sc->chip_type == RTL8366RB) 233 sprintf(sc->info.es_name, "Realtek RTL8366RB"); 234 else 235 sprintf(sc->info.es_name, "Realtek RTL8366SR"); 236 237 /* attach miibus and phys */ 238 /* PHYs need an interface, so we generate a dummy one */ 239 for (i = 0; i < sc->numphys; i++) { 240 sc->ifp[i] = if_alloc(IFT_ETHER); 241 if_setsoftc(sc->ifp[i], sc); 242 if_setflagbits(sc->ifp[i], IFF_UP | IFF_BROADCAST | IFF_DRV_RUNNING 243 | IFF_SIMPLEX, 0); 244 snprintf(name, IFNAMSIZ, "%sport", device_get_nameunit(dev)); 245 sc->ifname[i] = malloc(strlen(name)+1, M_DEVBUF, M_WAITOK); 246 bcopy(name, sc->ifname[i], strlen(name)+1); 247 if_initname(sc->ifp[i], sc->ifname[i], i); 248 err = mii_attach(dev, &sc->miibus[i], sc->ifp[i], rtl8366rb_ifmedia_upd, \ 249 rtl8366rb_ifmedia_sts, BMSR_DEFCAPMASK, \ 250 i, MII_OFFSET_ANY, 0); 251 if (err != 0) { 252 device_printf(dev, "attaching PHY %d failed\n", i); 253 return (err); 254 } 255 } 256 257 bus_identify_children(dev); 258 bus_enumerate_hinted_children(dev); 259 bus_attach_children(dev); 260 261 callout_init_mtx(&sc->callout_tick, &sc->callout_mtx, 0); 262 rtl8366rb_tick(sc); 263 264 return (err); 265 } 266 267 static int 268 rtl8366rb_detach(device_t dev) 269 { 270 struct rtl8366rb_softc *sc; 271 int i; 272 273 sc = device_get_softc(dev); 274 275 for (i=0; i < sc->numphys; i++) { 276 if (sc->miibus[i]) 277 device_delete_child(dev, sc->miibus[i]); 278 if (sc->ifp[i] != NULL) 279 if_free(sc->ifp[i]); 280 free(sc->ifname[i], M_DEVBUF); 281 } 282 bus_generic_detach(dev); 283 callout_drain(&sc->callout_tick); 284 mtx_destroy(&sc->callout_mtx); 285 mtx_destroy(&sc->sc_mtx); 286 287 return (0); 288 } 289 290 static void 291 rtl8366rb_update_ifmedia(int portstatus, u_int *media_status, u_int *media_active) 292 { 293 *media_active = IFM_ETHER; 294 *media_status = IFM_AVALID; 295 if ((portstatus & RTL8366_PLSR_LINK) != 0) 296 *media_status |= IFM_ACTIVE; 297 else { 298 *media_active |= IFM_NONE; 299 return; 300 } 301 switch (portstatus & RTL8366_PLSR_SPEED_MASK) { 302 case RTL8366_PLSR_SPEED_10: 303 *media_active |= IFM_10_T; 304 break; 305 case RTL8366_PLSR_SPEED_100: 306 *media_active |= IFM_100_TX; 307 break; 308 case RTL8366_PLSR_SPEED_1000: 309 *media_active |= IFM_1000_T; 310 break; 311 } 312 if ((portstatus & RTL8366_PLSR_FULLDUPLEX) != 0) 313 *media_active |= IFM_FDX; 314 else 315 *media_active |= IFM_HDX; 316 if ((portstatus & RTL8366_PLSR_TXPAUSE) != 0) 317 *media_active |= IFM_ETH_TXPAUSE; 318 if ((portstatus & RTL8366_PLSR_RXPAUSE) != 0) 319 *media_active |= IFM_ETH_RXPAUSE; 320 } 321 322 static void 323 rtl833rb_miipollstat(struct rtl8366rb_softc *sc) 324 { 325 int i; 326 struct mii_data *mii; 327 struct mii_softc *miisc; 328 uint16_t value; 329 int portstatus; 330 331 for (i = 0; i < sc->numphys; i++) { 332 mii = device_get_softc(sc->miibus[i]); 333 if ((i % 2) == 0) { 334 if (smi_read(sc->dev, RTL8366_PLSR_BASE + i/2, &value, RTL_NOWAIT) != 0) { 335 DEBUG_INCRVAR(callout_blocked); 336 return; 337 } 338 portstatus = value & 0xff; 339 } else { 340 portstatus = (value >> 8) & 0xff; 341 } 342 rtl8366rb_update_ifmedia(portstatus, &mii->mii_media_status, &mii->mii_media_active); 343 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) { 344 if (IFM_INST(mii->mii_media.ifm_cur->ifm_media) != miisc->mii_inst) 345 continue; 346 mii_phy_update(miisc, MII_POLLSTAT); 347 } 348 } 349 } 350 351 static void 352 rtl8366rb_tick(void *arg) 353 { 354 struct rtl8366rb_softc *sc; 355 356 sc = arg; 357 358 rtl833rb_miipollstat(sc); 359 callout_reset(&sc->callout_tick, hz, rtl8366rb_tick, sc); 360 } 361 362 static int 363 smi_probe(device_t dev) 364 { 365 struct rtl8366rb_softc *sc; 366 device_t iicbus, iicha; 367 int err, i, j; 368 uint16_t chipid; 369 char bytes[2]; 370 int xferd; 371 372 sc = device_get_softc(dev); 373 374 iicbus = device_get_parent(dev); 375 iicha = device_get_parent(iicbus); 376 377 for (i = 0; i < 2; ++i) { 378 iicbus_reset(iicbus, IIC_FASTEST, RTL8366_IIC_ADDR, NULL); 379 for (j=3; j--; ) { 380 IICBUS_STOP(iicha); 381 /* 382 * we go directly to the host adapter because iicbus.c 383 * only issues a stop on a bus that was successfully started. 384 */ 385 } 386 err = iicbus_request_bus(iicbus, dev, IIC_WAIT); 387 if (err != 0) 388 goto out; 389 err = iicbus_start(iicbus, RTL8366_IIC_ADDR | RTL_IICBUS_READ, RTL_IICBUS_TIMEOUT); 390 if (err != 0) 391 goto out; 392 if (i == 0) { 393 bytes[0] = RTL8366RB_CIR & 0xff; 394 bytes[1] = (RTL8366RB_CIR >> 8) & 0xff; 395 } else { 396 bytes[0] = RTL8366SR_CIR & 0xff; 397 bytes[1] = (RTL8366SR_CIR >> 8) & 0xff; 398 } 399 err = iicbus_write(iicbus, bytes, 2, &xferd, RTL_IICBUS_TIMEOUT); 400 if (err != 0) 401 goto out; 402 err = iicbus_read(iicbus, bytes, 2, &xferd, IIC_LAST_READ, 0); 403 if (err != 0) 404 goto out; 405 chipid = ((bytes[1] & 0xff) << 8) | (bytes[0] & 0xff); 406 if (i == 0 && chipid == RTL8366RB_CIR_ID8366RB) { 407 DPRINTF(dev, "chip id 0x%04x\n", chipid); 408 sc->chip_type = RTL8366RB; 409 err = 0; 410 break; 411 } 412 if (i == 1 && chipid == RTL8366SR_CIR_ID8366SR) { 413 DPRINTF(dev, "chip id 0x%04x\n", chipid); 414 sc->chip_type = RTL8366SR; 415 err = 0; 416 break; 417 } 418 if (i == 0) { 419 iicbus_stop(iicbus); 420 iicbus_release_bus(iicbus, dev); 421 } 422 } 423 if (i == 2) 424 err = ENXIO; 425 out: 426 iicbus_stop(iicbus); 427 iicbus_release_bus(iicbus, dev); 428 return (err == 0 ? 0 : ENXIO); 429 } 430 431 static int 432 smi_acquire(struct rtl8366rb_softc *sc, int sleep) 433 { 434 int r = 0; 435 if (sleep == RTL_WAITOK) 436 RTL_LOCK(sc); 437 else 438 if (RTL_TRYLOCK(sc) == 0) 439 return (EWOULDBLOCK); 440 if (sc->smi_acquired == RTL_SMI_ACQUIRED) 441 r = EBUSY; 442 else { 443 r = iicbus_request_bus(device_get_parent(sc->dev), sc->dev, \ 444 sleep == RTL_WAITOK ? IIC_WAIT : IIC_DONTWAIT); 445 if (r == 0) 446 sc->smi_acquired = RTL_SMI_ACQUIRED; 447 } 448 RTL_UNLOCK(sc); 449 return (r); 450 } 451 452 static int 453 smi_release(struct rtl8366rb_softc *sc, int sleep) 454 { 455 if (sleep == RTL_WAITOK) 456 RTL_LOCK(sc); 457 else 458 if (RTL_TRYLOCK(sc) == 0) 459 return (EWOULDBLOCK); 460 RTL_SMI_ACQUIRED_ASSERT(sc); 461 iicbus_release_bus(device_get_parent(sc->dev), sc->dev); 462 sc->smi_acquired = 0; 463 RTL_UNLOCK(sc); 464 return (0); 465 } 466 467 static int 468 smi_select(device_t dev, int op, int sleep) 469 { 470 struct rtl8366rb_softc *sc; 471 int err, i; 472 device_t iicbus; 473 struct iicbus_ivar *devi; 474 int slave; 475 476 sc = device_get_softc(dev); 477 478 iicbus = device_get_parent(dev); 479 devi = IICBUS_IVAR(dev); 480 slave = devi->addr; 481 482 RTL_SMI_ACQUIRED_ASSERT((struct rtl8366rb_softc *)device_get_softc(dev)); 483 484 if (sc->chip_type == RTL8366SR) { // RTL8366SR work around 485 // this is same work around at probe 486 for (int i=3; i--; ) 487 IICBUS_STOP(device_get_parent(device_get_parent(dev))); 488 } 489 /* 490 * The chip does not use clock stretching when it is busy, 491 * instead ignoring the command. Retry a few times. 492 */ 493 for (i = RTL_IICBUS_RETRIES; i--; ) { 494 err = iicbus_start(iicbus, slave | op, RTL_IICBUS_TIMEOUT); 495 if (err != IIC_ENOACK) 496 break; 497 if (sleep == RTL_WAITOK) { 498 DEBUG_INCRVAR(iic_select_retries); 499 pause("smi_select", RTL_IICBUS_RETRY_SLEEP); 500 } else 501 break; 502 } 503 return (err); 504 } 505 506 static int 507 smi_read_locked(struct rtl8366rb_softc *sc, uint16_t addr, uint16_t *data, int sleep) 508 { 509 int err; 510 device_t iicbus; 511 char bytes[2]; 512 int xferd; 513 514 iicbus = device_get_parent(sc->dev); 515 516 RTL_SMI_ACQUIRED_ASSERT(sc); 517 bytes[0] = addr & 0xff; 518 bytes[1] = (addr >> 8) & 0xff; 519 err = smi_select(sc->dev, RTL_IICBUS_READ, sleep); 520 if (err != 0) 521 goto out; 522 err = iicbus_write(iicbus, bytes, 2, &xferd, RTL_IICBUS_TIMEOUT); 523 if (err != 0) 524 goto out; 525 err = iicbus_read(iicbus, bytes, 2, &xferd, IIC_LAST_READ, 0); 526 if (err != 0) 527 goto out; 528 *data = ((bytes[1] & 0xff) << 8) | (bytes[0] & 0xff); 529 530 out: 531 iicbus_stop(iicbus); 532 return (err); 533 } 534 535 static int 536 smi_write_locked(struct rtl8366rb_softc *sc, uint16_t addr, uint16_t data, int sleep) 537 { 538 int err; 539 device_t iicbus; 540 char bytes[4]; 541 int xferd; 542 543 iicbus = device_get_parent(sc->dev); 544 545 RTL_SMI_ACQUIRED_ASSERT(sc); 546 bytes[0] = addr & 0xff; 547 bytes[1] = (addr >> 8) & 0xff; 548 bytes[2] = data & 0xff; 549 bytes[3] = (data >> 8) & 0xff; 550 551 err = smi_select(sc->dev, RTL_IICBUS_WRITE, sleep); 552 if (err == 0) 553 err = iicbus_write(iicbus, bytes, 4, &xferd, RTL_IICBUS_TIMEOUT); 554 iicbus_stop(iicbus); 555 556 return (err); 557 } 558 559 static int 560 smi_read(device_t dev, uint16_t addr, uint16_t *data, int sleep) 561 { 562 struct rtl8366rb_softc *sc; 563 int err; 564 565 sc = device_get_softc(dev); 566 567 err = smi_acquire(sc, sleep); 568 if (err != 0) 569 return (EBUSY); 570 err = smi_read_locked(sc, addr, data, sleep); 571 smi_release(sc, sleep); 572 DEVERR(dev, err, "smi_read()=%d: addr=%04x\n", addr); 573 return (err == 0 ? 0 : EIO); 574 } 575 576 static int 577 smi_write(device_t dev, uint16_t addr, uint16_t data, int sleep) 578 { 579 struct rtl8366rb_softc *sc; 580 int err; 581 582 sc = device_get_softc(dev); 583 584 err = smi_acquire(sc, sleep); 585 if (err != 0) 586 return (EBUSY); 587 err = smi_write_locked(sc, addr, data, sleep); 588 smi_release(sc, sleep); 589 DEVERR(dev, err, "smi_write()=%d: addr=%04x\n", addr); 590 return (err == 0 ? 0 : EIO); 591 } 592 593 static int 594 smi_rmw(device_t dev, uint16_t addr, uint16_t mask, uint16_t data, int sleep) 595 { 596 struct rtl8366rb_softc *sc; 597 int err; 598 uint16_t oldv, newv; 599 600 sc = device_get_softc(dev); 601 602 err = smi_acquire(sc, sleep); 603 if (err != 0) 604 return (EBUSY); 605 if (err == 0) { 606 err = smi_read_locked(sc, addr, &oldv, sleep); 607 if (err == 0) { 608 newv = oldv & ~mask; 609 newv |= data & mask; 610 if (newv != oldv) 611 err = smi_write_locked(sc, addr, newv, sleep); 612 } 613 } 614 smi_release(sc, sleep); 615 DEVERR(dev, err, "smi_rmw()=%d: addr=%04x\n", addr); 616 return (err == 0 ? 0 : EIO); 617 } 618 619 static etherswitch_info_t * 620 rtl_getinfo(device_t dev) 621 { 622 struct rtl8366rb_softc *sc; 623 624 sc = device_get_softc(dev); 625 626 return (&sc->info); 627 } 628 629 static int 630 rtl_readreg(device_t dev, int reg) 631 { 632 uint16_t data; 633 634 data = 0; 635 636 smi_read(dev, reg, &data, RTL_WAITOK); 637 return (data); 638 } 639 640 static int 641 rtl_writereg(device_t dev, int reg, int value) 642 { 643 return (smi_write(dev, reg, value, RTL_WAITOK)); 644 } 645 646 static int 647 rtl_getport(device_t dev, etherswitch_port_t *p) 648 { 649 struct rtl8366rb_softc *sc; 650 struct ifmedia *ifm; 651 struct mii_data *mii; 652 struct ifmediareq *ifmr; 653 uint16_t v; 654 int err, vlangroup; 655 656 sc = device_get_softc(dev); 657 658 ifmr = &p->es_ifmr; 659 660 if (p->es_port < 0 || p->es_port >= (sc->numphys + 1)) 661 return (ENXIO); 662 if (sc->phy4cpu && p->es_port == sc->numphys) { 663 vlangroup = RTL8366_PVCR_GET(p->es_port + 1, 664 rtl_readreg(dev, RTL8366_PVCR_REG(p->es_port + 1))); 665 } else { 666 vlangroup = RTL8366_PVCR_GET(p->es_port, 667 rtl_readreg(dev, RTL8366_PVCR_REG(p->es_port))); 668 } 669 p->es_pvid = sc->vid[vlangroup] & ETHERSWITCH_VID_MASK; 670 671 if (p->es_port < sc->numphys) { 672 mii = device_get_softc(sc->miibus[p->es_port]); 673 ifm = &mii->mii_media; 674 err = ifmedia_ioctl(sc->ifp[p->es_port], &p->es_ifr, ifm, SIOCGIFMEDIA); 675 if (err) 676 return (err); 677 } else { 678 /* fill in fixed values for CPU port */ 679 p->es_flags |= ETHERSWITCH_PORT_CPU; 680 smi_read(dev, RTL8366_PLSR_BASE + (RTL8366_NUM_PHYS)/2, &v, RTL_WAITOK); 681 v = v >> (8 * ((RTL8366_NUM_PHYS) % 2)); 682 rtl8366rb_update_ifmedia(v, &ifmr->ifm_status, &ifmr->ifm_active); 683 ifmr->ifm_current = ifmr->ifm_active; 684 ifmr->ifm_mask = 0; 685 ifmr->ifm_status = IFM_ACTIVE | IFM_AVALID; 686 /* Return our static media list. */ 687 if (ifmr->ifm_count > 0) { 688 ifmr->ifm_count = 1; 689 ifmr->ifm_ulist[0] = IFM_MAKEWORD(IFM_ETHER, IFM_1000_T, 690 IFM_FDX, 0); 691 } else 692 ifmr->ifm_count = 0; 693 } 694 return (0); 695 } 696 697 static int 698 rtl_setport(device_t dev, etherswitch_port_t *p) 699 { 700 struct rtl8366rb_softc *sc; 701 int i, err, vlangroup; 702 struct ifmedia *ifm; 703 struct mii_data *mii; 704 int port; 705 706 sc = device_get_softc(dev); 707 708 if (p->es_port < 0 || p->es_port >= (sc->numphys + 1)) 709 return (ENXIO); 710 vlangroup = -1; 711 for (i = 0; i < RTL8366_NUM_VLANS; i++) { 712 if ((sc->vid[i] & ETHERSWITCH_VID_MASK) == p->es_pvid) { 713 vlangroup = i; 714 break; 715 } 716 } 717 if (vlangroup == -1) 718 return (ENXIO); 719 if (sc->phy4cpu && p->es_port == sc->numphys) { 720 port = p->es_port + 1; 721 } else { 722 port = p->es_port; 723 } 724 err = smi_rmw(dev, RTL8366_PVCR_REG(port), 725 RTL8366_PVCR_VAL(port, RTL8366_PVCR_PORT_MASK), 726 RTL8366_PVCR_VAL(port, vlangroup), RTL_WAITOK); 727 if (err) 728 return (err); 729 /* CPU Port */ 730 if (p->es_port == sc->numphys) 731 return (0); 732 mii = device_get_softc(sc->miibus[p->es_port]); 733 ifm = &mii->mii_media; 734 err = ifmedia_ioctl(sc->ifp[p->es_port], &p->es_ifr, ifm, SIOCSIFMEDIA); 735 return (err); 736 } 737 738 static int 739 rtl_getvgroup(device_t dev, etherswitch_vlangroup_t *vg) 740 { 741 struct rtl8366rb_softc *sc; 742 uint16_t vmcr[3]; 743 int i; 744 int member, untagged; 745 746 sc = device_get_softc(dev); 747 748 for (i=0; i<RTL8366_VMCR_MULT; i++) 749 vmcr[i] = rtl_readreg(dev, RTL8366_VMCR(i, vg->es_vlangroup)); 750 751 vg->es_vid = sc->vid[vg->es_vlangroup]; 752 member = RTL8366_VMCR_MEMBER(vmcr); 753 untagged = RTL8366_VMCR_UNTAG(vmcr); 754 if (sc->phy4cpu) { 755 vg->es_member_ports = ((member & 0x20) >> 1) | (member & 0x0f); 756 vg->es_untagged_ports = ((untagged & 0x20) >> 1) | (untagged & 0x0f); 757 } else { 758 vg->es_member_ports = member; 759 vg->es_untagged_ports = untagged; 760 } 761 vg->es_fid = RTL8366_VMCR_FID(vmcr); 762 return (0); 763 } 764 765 static int 766 rtl_setvgroup(device_t dev, etherswitch_vlangroup_t *vg) 767 { 768 struct rtl8366rb_softc *sc; 769 int g; 770 int member, untagged; 771 772 sc = device_get_softc(dev); 773 774 g = vg->es_vlangroup; 775 776 sc->vid[g] = vg->es_vid; 777 /* VLAN group disabled ? */ 778 if (vg->es_member_ports == 0 && vg->es_untagged_ports == 0 && vg->es_vid == 0) 779 return (0); 780 sc->vid[g] |= ETHERSWITCH_VID_VALID; 781 rtl_writereg(dev, RTL8366_VMCR(RTL8366_VMCR_DOT1Q_REG, g), 782 (vg->es_vid << RTL8366_VMCR_DOT1Q_VID_SHIFT) & RTL8366_VMCR_DOT1Q_VID_MASK); 783 if (sc->phy4cpu) { 784 /* add space at phy4 */ 785 member = (vg->es_member_ports & 0x0f) | 786 ((vg->es_member_ports & 0x10) << 1); 787 untagged = (vg->es_untagged_ports & 0x0f) | 788 ((vg->es_untagged_ports & 0x10) << 1); 789 } else { 790 member = vg->es_member_ports; 791 untagged = vg->es_untagged_ports; 792 } 793 if (sc->chip_type == RTL8366RB) { 794 rtl_writereg(dev, RTL8366_VMCR(RTL8366_VMCR_MU_REG, g), 795 ((member << RTL8366_VMCR_MU_MEMBER_SHIFT) & RTL8366_VMCR_MU_MEMBER_MASK) | 796 ((untagged << RTL8366_VMCR_MU_UNTAG_SHIFT) & RTL8366_VMCR_MU_UNTAG_MASK)); 797 rtl_writereg(dev, RTL8366_VMCR(RTL8366_VMCR_FID_REG, g), 798 vg->es_fid); 799 } else { 800 rtl_writereg(dev, RTL8366_VMCR(RTL8366_VMCR_MU_REG, g), 801 ((member << RTL8366_VMCR_MU_MEMBER_SHIFT) & RTL8366_VMCR_MU_MEMBER_MASK) | 802 ((untagged << RTL8366_VMCR_MU_UNTAG_SHIFT) & RTL8366_VMCR_MU_UNTAG_MASK) | 803 ((vg->es_fid << RTL8366_VMCR_FID_FID_SHIFT) & RTL8366_VMCR_FID_FID_MASK)); 804 } 805 return (0); 806 } 807 808 static int 809 rtl_getconf(device_t dev, etherswitch_conf_t *conf) 810 { 811 812 /* Return the VLAN mode. */ 813 conf->cmd = ETHERSWITCH_CONF_VLAN_MODE; 814 conf->vlan_mode = ETHERSWITCH_VLAN_DOT1Q; 815 816 return (0); 817 } 818 819 static int 820 rtl_readphy(device_t dev, int phy, int reg) 821 { 822 struct rtl8366rb_softc *sc; 823 uint16_t data; 824 int err, i, sleep; 825 826 sc = device_get_softc(dev); 827 828 data = 0; 829 830 if (phy < 0 || phy >= RTL8366_NUM_PHYS) 831 return (ENXIO); 832 if (reg < 0 || reg >= RTL8366_NUM_PHY_REG) 833 return (ENXIO); 834 sleep = RTL_WAITOK; 835 err = smi_acquire(sc, sleep); 836 if (err != 0) 837 return (EBUSY); 838 for (i = RTL_IICBUS_RETRIES; i--; ) { 839 err = smi_write_locked(sc, RTL8366_PACR, RTL8366_PACR_READ, sleep); 840 if (err == 0) 841 err = smi_write_locked(sc, RTL8366_PHYREG(phy, 0, reg), 0, sleep); 842 if (err == 0) { 843 err = smi_read_locked(sc, RTL8366_PADR, &data, sleep); 844 break; 845 } 846 DEBUG_INCRVAR(phy_access_retries); 847 DPRINTF(dev, "rtl_readphy(): chip not responsive, retrying %d more times\n", i); 848 pause("rtl_readphy", RTL_IICBUS_RETRY_SLEEP); 849 } 850 smi_release(sc, sleep); 851 DEVERR(dev, err, "rtl_readphy()=%d: phy=%d.%02x\n", phy, reg); 852 return (data); 853 } 854 855 static int 856 rtl_writephy(device_t dev, int phy, int reg, int data) 857 { 858 struct rtl8366rb_softc *sc; 859 int err, i, sleep; 860 861 sc = device_get_softc(dev); 862 863 if (phy < 0 || phy >= RTL8366_NUM_PHYS) 864 return (ENXIO); 865 if (reg < 0 || reg >= RTL8366_NUM_PHY_REG) 866 return (ENXIO); 867 sleep = RTL_WAITOK; 868 err = smi_acquire(sc, sleep); 869 if (err != 0) 870 return (EBUSY); 871 for (i = RTL_IICBUS_RETRIES; i--; ) { 872 err = smi_write_locked(sc, RTL8366_PACR, RTL8366_PACR_WRITE, sleep); 873 if (err == 0) 874 err = smi_write_locked(sc, RTL8366_PHYREG(phy, 0, reg), data, sleep); 875 if (err == 0) { 876 break; 877 } 878 DEBUG_INCRVAR(phy_access_retries); 879 DPRINTF(dev, "rtl_writephy(): chip not responsive, retrying %d more tiems\n", i); 880 pause("rtl_writephy", RTL_IICBUS_RETRY_SLEEP); 881 } 882 smi_release(sc, sleep); 883 DEVERR(dev, err, "rtl_writephy()=%d: phy=%d.%02x\n", phy, reg); 884 return (err == 0 ? 0 : EIO); 885 } 886 887 static int 888 rtl8366rb_ifmedia_upd(if_t ifp) 889 { 890 struct rtl8366rb_softc *sc; 891 struct mii_data *mii; 892 893 sc = if_getsoftc(ifp); 894 mii = device_get_softc(sc->miibus[if_getdunit(ifp)]); 895 896 mii_mediachg(mii); 897 return (0); 898 } 899 900 static void 901 rtl8366rb_ifmedia_sts(if_t ifp, struct ifmediareq *ifmr) 902 { 903 struct rtl8366rb_softc *sc; 904 struct mii_data *mii; 905 906 sc = if_getsoftc(ifp); 907 mii = device_get_softc(sc->miibus[if_getdunit(ifp)]); 908 909 mii_pollstat(mii); 910 ifmr->ifm_active = mii->mii_media_active; 911 ifmr->ifm_status = mii->mii_media_status; 912 } 913 914 915 static device_method_t rtl8366rb_methods[] = { 916 /* Device interface */ 917 DEVMETHOD(device_identify, rtl8366rb_identify), 918 DEVMETHOD(device_probe, rtl8366rb_probe), 919 DEVMETHOD(device_attach, rtl8366rb_attach), 920 DEVMETHOD(device_detach, rtl8366rb_detach), 921 922 /* bus interface */ 923 DEVMETHOD(bus_add_child, device_add_child_ordered), 924 925 /* MII interface */ 926 DEVMETHOD(miibus_readreg, rtl_readphy), 927 DEVMETHOD(miibus_writereg, rtl_writephy), 928 929 /* MDIO interface */ 930 DEVMETHOD(mdio_readreg, rtl_readphy), 931 DEVMETHOD(mdio_writereg, rtl_writephy), 932 933 /* etherswitch interface */ 934 DEVMETHOD(etherswitch_getconf, rtl_getconf), 935 DEVMETHOD(etherswitch_getinfo, rtl_getinfo), 936 DEVMETHOD(etherswitch_readreg, rtl_readreg), 937 DEVMETHOD(etherswitch_writereg, rtl_writereg), 938 DEVMETHOD(etherswitch_readphyreg, rtl_readphy), 939 DEVMETHOD(etherswitch_writephyreg, rtl_writephy), 940 DEVMETHOD(etherswitch_getport, rtl_getport), 941 DEVMETHOD(etherswitch_setport, rtl_setport), 942 DEVMETHOD(etherswitch_getvgroup, rtl_getvgroup), 943 DEVMETHOD(etherswitch_setvgroup, rtl_setvgroup), 944 945 DEVMETHOD_END 946 }; 947 948 DEFINE_CLASS_0(rtl8366rb, rtl8366rb_driver, rtl8366rb_methods, 949 sizeof(struct rtl8366rb_softc)); 950 951 DRIVER_MODULE(rtl8366rb, iicbus, rtl8366rb_driver, 0, 0); 952 DRIVER_MODULE(miibus, rtl8366rb, miibus_driver, 0, 0); 953 DRIVER_MODULE(mdio, rtl8366rb, mdio_driver, 0, 0); 954 DRIVER_MODULE(etherswitch, rtl8366rb, etherswitch_driver, 0, 0); 955 MODULE_VERSION(rtl8366rb, 1); 956 MODULE_DEPEND(rtl8366rb, iicbus, 1, 1, 1); /* XXX which versions? */ 957 MODULE_DEPEND(rtl8366rb, miibus, 1, 1, 1); /* XXX which versions? */ 958 MODULE_DEPEND(rtl8366rb, etherswitch, 1, 1, 1); /* XXX which versions? */ 959