1 /*- 2 * Copyright (c) 2016 Stanislav Galabov. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27 #ifndef __MTKSWITCH_MT7620_H__ 28 #define __MTKSWITCH_MT7620_H__ 29 30 #define MTKSWITCH_ATC 0x0080 31 #define ATC_BUSY (1u<<15) 32 #define ATC_AC_MAT_NON_STATIC_MACS (4u<<8) 33 #define ATC_AC_CMD_CLEAN (2u<<0) 34 35 #define MTKSWITCH_VTCR 0x0090 36 #define VTCR_BUSY (1u<<31) 37 #define VTCR_FUNC_VID_READ (0u<<12) 38 #define VTCR_FUNC_VID_WRITE (1u<<12) 39 #define VTCR_FUNC_VID_INVALID (2u<<12) 40 #define VTCR_FUNC_VID_VALID (3u<<12) 41 #define VTCR_IDX_INVALID (1u<<16) 42 #define VTCR_VID_MASK 0xfff 43 44 #define MTKSWITCH_VAWD1 0x0094 45 #define VAWD1_IVL_MAC (1u<<30) 46 #define VAWD1_VTAG_EN (1u<<28) 47 #define VAWD1_PORT_MEMBER(p) ((1u<<16)<<(p)) 48 #define VAWD1_MEMBER_OFF 16 49 #define VAWD1_MEMBER_MASK 0xff 50 #define VAWD1_FID_OFFSET 1 51 #define VAWD1_VALID (1u<<0) 52 53 #define MTKSWITCH_VAWD2 0x0098 54 #define VAWD2_PORT_UNTAGGED(p) (0u<<((p)*2)) 55 #define VAWD2_PORT_TAGGED(p) (2u<<((p)*2)) 56 #define VAWD2_PORT_MASK(p) (3u<<((p)*2)) 57 58 #define MTKSWITCH_VTIM(v) ((((v) >> 1) * 4) + 0x100) 59 #define VTIM_OFF(v) (((v) & 1) ? 12 : 0) 60 #define VTIM_MASK 0xfff 61 62 #define MTKSWITCH_PIAC 0x7004 63 #define PIAC_PHY_ACS_ST (1u<<31) 64 #define PIAC_MDIO_REG_ADDR_OFF 25 65 #define PIAC_MDIO_PHY_ADDR_OFF 20 66 #define PIAC_MDIO_CMD_WRITE (1u<<18) 67 #define PIAC_MDIO_CMD_READ (2u<<18) 68 #define PIAC_MDIO_ST (1u<<16) 69 #define PIAC_MDIO_RW_DATA_MASK 0xffff 70 71 #define MTKSWITCH_PORTREG(r, p) ((r) + ((p) * 0x100)) 72 73 #define MTKSWITCH_PCR(x) MTKSWITCH_PORTREG(0x2004, (x)) 74 #define PCR_PORT_VLAN_SECURE (3u<<0) 75 76 #define MTKSWITCH_PVC(x) MTKSWITCH_PORTREG(0x2010, (x)) 77 #define PVC_VLAN_ATTR_MASK (3u<<6) 78 79 #define MTKSWITCH_PPBV1(x) MTKSWITCH_PORTREG(0x2014, (x)) 80 #define MTKSWITCH_PPBV2(x) MTKSWITCH_PORTREG(0x2018, (x)) 81 #define PPBV_VID(v) (((v)<<16) | (v)) 82 #define PPBV_VID_FROM_REG(x) ((x) & 0xfff) 83 #define PPBV_VID_MASK 0xfff 84 85 #define MTKSWITCH_PMCR(x) MTKSWITCH_PORTREG(0x3000, (x)) 86 #define PMCR_FORCE_LINK (1u<<0) 87 #define PMCR_FORCE_DPX (1u<<1) 88 #define PMCR_FORCE_SPD_1000 (2u<<2) 89 #define PMCR_FORCE_TX_FC (1u<<4) 90 #define PMCR_FORCE_RX_FC (1u<<5) 91 #define PMCR_BACKPR_EN (1u<<8) 92 #define PMCR_BKOFF_EN (1u<<9) 93 #define PMCR_MAC_RX_EN (1u<<13) 94 #define PMCR_MAC_TX_EN (1u<<14) 95 #define PMCR_FORCE_MODE (1u<<15) 96 #define PMCR_RES_1 (1u<<16) 97 #define PMCR_IPG_CFG_RND (1u<<18) 98 #define PMCR_CFG_DEFAULT (PMCR_BACKPR_EN | PMCR_BKOFF_EN | \ 99 PMCR_MAC_RX_EN | PMCR_MAC_TX_EN | PMCR_IPG_CFG_RND | \ 100 PMCR_FORCE_RX_FC | PMCR_FORCE_TX_FC | PMCR_RES_1) 101 102 #define MTKSWITCH_PMSR(x) MTKSWITCH_PORTREG(0x3008, (x)) 103 #define PMSR_MAC_LINK_STS (1u<<0) 104 #define PMSR_MAC_DPX_STS (1u<<1) 105 #define PMSR_MAC_SPD_STS (3u<<2) 106 #define PMSR_MAC_SPD(x) (((x)>>2) & 0x3) 107 #define PMSR_MAC_SPD_10 0 108 #define PMSR_MAC_SPD_100 1 109 #define PMSR_MAC_SPD_1000 2 110 #define PMSR_TX_FC_STS (1u<<4) 111 #define PMSR_RX_FC_STS (1u<<5) 112 113 #define MTKSWITCH_REG_ADDR(r) (((r) >> 6) & 0x3ff) 114 #define MTKSWITCH_REG_LO(r) (((r) >> 2) & 0xf) 115 #define MTKSWITCH_REG_HI(r) (1 << 4) 116 #define MTKSWITCH_VAL_LO(v) ((v) & 0xffff) 117 #define MTKSWITCH_VAL_HI(v) (((v) >> 16) & 0xffff) 118 #define MTKSWITCH_GLOBAL_PHY 31 119 #define MTKSWITCH_GLOBAL_REG 31 120 121 #define MTKSWITCH_LAN_VID 0x001 122 #define MTKSWITCH_WAN_VID 0x002 123 #define MTKSWITCH_INVALID_VID 0xfff 124 125 #define MTKSWITCH_LAN_FID 1 126 #define MTKSWITCH_WAN_FID 2 127 128 #endif /* __MTKSWITCH_MT7620_H__ */ 129