1 /*- 2 * Copyright (c) 2016 Hiroki Mori 3 * Copyright (c) 2013 Luiz Otavio O Souza. 4 * Copyright (c) 2011-2012 Stefan Bethke. 5 * Copyright (c) 2012 Adrian Chadd. 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30 /* 31 * This is Micrel KSZ8995MA driver code. KSZ8995MA use SPI bus on control. 32 * This code development on @SRCHACK's ksz8995ma board and FON2100 with 33 * gpiospi. 34 * etherswitchcfg command port option support addtag, ingress, striptag, 35 * dropuntagged. 36 */ 37 38 #include <sys/param.h> 39 #include <sys/bus.h> 40 #include <sys/errno.h> 41 #include <sys/kernel.h> 42 #include <sys/lock.h> 43 #include <sys/malloc.h> 44 #include <sys/module.h> 45 #include <sys/mutex.h> 46 #include <sys/socket.h> 47 #include <sys/sockio.h> 48 #include <sys/sysctl.h> 49 #include <sys/systm.h> 50 51 #include <net/if.h> 52 #include <net/if_var.h> 53 #include <net/ethernet.h> 54 #include <net/if_media.h> 55 #include <net/if_types.h> 56 57 #include <machine/bus.h> 58 #include <dev/mii/mii.h> 59 #include <dev/mii/miivar.h> 60 61 #include <dev/etherswitch/etherswitch.h> 62 63 #include <dev/spibus/spi.h> 64 65 #include "spibus_if.h" 66 #include "miibus_if.h" 67 #include "etherswitch_if.h" 68 69 #define KSZ8995MA_SPI_READ 0x03 70 #define KSZ8995MA_SPI_WRITE 0x02 71 72 #define KSZ8995MA_CID0 0x00 73 #define KSZ8995MA_CID1 0x01 74 75 #define KSZ8995MA_GC0 0x02 76 #define KSZ8995MA_GC1 0x03 77 #define KSZ8995MA_GC2 0x04 78 #define KSZ8995MA_GC3 0x05 79 80 #define KSZ8995MA_PORT_SIZE 0x10 81 82 #define KSZ8995MA_PC0_BASE 0x10 83 #define KSZ8995MA_PC1_BASE 0x11 84 #define KSZ8995MA_PC2_BASE 0x12 85 #define KSZ8995MA_PC3_BASE 0x13 86 #define KSZ8995MA_PC4_BASE 0x14 87 #define KSZ8995MA_PC5_BASE 0x15 88 #define KSZ8995MA_PC6_BASE 0x16 89 #define KSZ8995MA_PC7_BASE 0x17 90 #define KSZ8995MA_PC8_BASE 0x18 91 #define KSZ8995MA_PC9_BASE 0x19 92 #define KSZ8995MA_PC10_BASE 0x1a 93 #define KSZ8995MA_PC11_BASE 0x1b 94 #define KSZ8995MA_PC12_BASE 0x1c 95 #define KSZ8995MA_PC13_BASE 0x1d 96 97 #define KSZ8995MA_PS0_BASE 0x1e 98 99 #define KSZ8995MA_PC14_BASE 0x1f 100 101 #define KSZ8995MA_IAC0 0x6e 102 #define KSZ8995MA_IAC1 0x6f 103 #define KSZ8995MA_IDR8 0x70 104 #define KSZ8995MA_IDR7 0x71 105 #define KSZ8995MA_IDR6 0x72 106 #define KSZ8995MA_IDR5 0x73 107 #define KSZ8995MA_IDR4 0x74 108 #define KSZ8995MA_IDR3 0x75 109 #define KSZ8995MA_IDR2 0x76 110 #define KSZ8995MA_IDR1 0x77 111 #define KSZ8995MA_IDR0 0x78 112 113 #define KSZ8995MA_FAMILI_ID 0x95 114 #define KSZ8995MA_CHIP_ID 0x00 115 #define KSZ8995MA_CHIP_ID_MASK 0xf0 116 #define KSZ8995MA_START 0x01 117 #define KSZ8995MA_VLAN_ENABLE 0x80 118 #define KSZ8995MA_TAG_INS 0x04 119 #define KSZ8995MA_TAG_RM 0x02 120 #define KSZ8995MA_INGR_FILT 0x40 121 #define KSZ8995MA_DROP_NONPVID 0x20 122 123 #define KSZ8995MA_PDOWN 0x08 124 #define KSZ8995MA_STARTNEG 0x20 125 126 #define KSZ8995MA_MII_STAT 0x7808 127 #define KSZ8995MA_MII_PHYID_H 0x0022 128 #define KSZ8995MA_MII_PHYID_L 0x1450 129 #define KSZ8995MA_MII_AA 0x0401 130 131 #define KSZ8995MA_VLAN_TABLE_VALID 0x20 132 #define KSZ8995MA_VLAN_TABLE_READ 0x14 133 #define KSZ8995MA_VLAN_TABLE_WRITE 0x04 134 135 #define KSZ8995MA_MAX_PORT 5 136 137 MALLOC_DECLARE(M_KSZ8995MA); 138 MALLOC_DEFINE(M_KSZ8995MA, "ksz8995ma", "ksz8995ma data structures"); 139 140 struct ksz8995ma_softc { 141 struct mtx sc_mtx; /* serialize access to softc */ 142 device_t sc_dev; 143 int vlan_mode; 144 int media; /* cpu port media */ 145 int cpuport; /* which PHY is connected to the CPU */ 146 int phymask; /* PHYs we manage */ 147 int numports; /* number of ports */ 148 int ifpport[KSZ8995MA_MAX_PORT]; 149 int *portphy; 150 char **ifname; 151 device_t **miibus; 152 if_t *ifp; 153 struct callout callout_tick; 154 etherswitch_info_t info; 155 }; 156 157 #define KSZ8995MA_LOCK(_sc) \ 158 mtx_lock(&(_sc)->sc_mtx) 159 #define KSZ8995MA_UNLOCK(_sc) \ 160 mtx_unlock(&(_sc)->sc_mtx) 161 #define KSZ8995MA_LOCK_ASSERT(_sc, _what) \ 162 mtx_assert(&(_sc)->sc_mtx, (_what)) 163 #define KSZ8995MA_TRYLOCK(_sc) \ 164 mtx_trylock(&(_sc)->sc_mtx) 165 166 #if defined(DEBUG) 167 #define DPRINTF(dev, args...) device_printf(dev, args) 168 #else 169 #define DPRINTF(dev, args...) 170 #endif 171 172 static inline int ksz8995ma_portforphy(struct ksz8995ma_softc *, int); 173 static void ksz8995ma_tick(void *); 174 static int ksz8995ma_ifmedia_upd(if_t); 175 static void ksz8995ma_ifmedia_sts(if_t, struct ifmediareq *); 176 static int ksz8995ma_readreg(device_t dev, int addr); 177 static int ksz8995ma_writereg(device_t dev, int addr, int value); 178 static void ksz8995ma_portvlanreset(device_t dev); 179 180 static int 181 ksz8995ma_probe(device_t dev) 182 { 183 int id0, id1; 184 struct ksz8995ma_softc *sc; 185 186 sc = device_get_softc(dev); 187 bzero(sc, sizeof(*sc)); 188 189 id0 = ksz8995ma_readreg(dev, KSZ8995MA_CID0); 190 id1 = ksz8995ma_readreg(dev, KSZ8995MA_CID1); 191 if (bootverbose) 192 device_printf(dev,"Chip Identifier Register %x %x\n", id0, id1); 193 194 /* check Product Code */ 195 if (id0 != KSZ8995MA_FAMILI_ID || (id1 & KSZ8995MA_CHIP_ID_MASK) != 196 KSZ8995MA_CHIP_ID) { 197 return (ENXIO); 198 } 199 200 device_set_desc(dev, "Micrel KSZ8995MA SPI switch driver"); 201 return (BUS_PROBE_DEFAULT); 202 } 203 204 static int 205 ksz8995ma_attach_phys(struct ksz8995ma_softc *sc) 206 { 207 int phy, port, err; 208 char name[IFNAMSIZ]; 209 210 port = 0; 211 err = 0; 212 /* PHYs need an interface, so we generate a dummy one */ 213 snprintf(name, IFNAMSIZ, "%sport", device_get_nameunit(sc->sc_dev)); 214 for (phy = 0; phy < sc->numports; phy++) { 215 if (phy == sc->cpuport) 216 continue; 217 if (((1 << phy) & sc->phymask) == 0) 218 continue; 219 sc->ifpport[phy] = port; 220 sc->portphy[port] = phy; 221 sc->ifp[port] = if_alloc(IFT_ETHER); 222 sc->ifp[port]->if_softc = sc; 223 sc->ifp[port]->if_flags |= IFF_UP | IFF_BROADCAST | 224 IFF_DRV_RUNNING | IFF_SIMPLEX; 225 if_initname(sc->ifp[port], name, port); 226 sc->miibus[port] = malloc(sizeof(device_t), M_KSZ8995MA, 227 M_WAITOK | M_ZERO); 228 if (sc->miibus[port] == NULL) { 229 err = ENOMEM; 230 goto failed; 231 } 232 err = mii_attach(sc->sc_dev, sc->miibus[port], sc->ifp[port], 233 ksz8995ma_ifmedia_upd, ksz8995ma_ifmedia_sts, \ 234 BMSR_DEFCAPMASK, phy, MII_OFFSET_ANY, 0); 235 DPRINTF(sc->sc_dev, "%s attached to pseudo interface %s\n", 236 device_get_nameunit(*sc->miibus[port]), 237 sc->ifp[port]->if_xname); 238 if (err != 0) { 239 device_printf(sc->sc_dev, 240 "attaching PHY %d failed\n", 241 phy); 242 goto failed; 243 } 244 ++port; 245 } 246 sc->info.es_nports = port; 247 if (sc->cpuport != -1) { 248 /* cpu port is MAC5 on ksz8995ma */ 249 sc->ifpport[sc->cpuport] = port; 250 sc->portphy[port] = sc->cpuport; 251 ++sc->info.es_nports; 252 } 253 254 return (0); 255 256 failed: 257 for (phy = 0; phy < sc->numports; phy++) { 258 if (((1 << phy) & sc->phymask) == 0) 259 continue; 260 port = ksz8995ma_portforphy(sc, phy); 261 if (sc->miibus[port] != NULL) 262 device_delete_child(sc->sc_dev, (*sc->miibus[port])); 263 if (sc->ifp[port] != NULL) 264 if_free(sc->ifp[port]); 265 if (sc->ifname[port] != NULL) 266 free(sc->ifname[port], M_KSZ8995MA); 267 if (sc->miibus[port] != NULL) 268 free(sc->miibus[port], M_KSZ8995MA); 269 } 270 return (err); 271 } 272 273 static int 274 ksz8995ma_attach(device_t dev) 275 { 276 struct ksz8995ma_softc *sc; 277 int err, reg; 278 279 err = 0; 280 sc = device_get_softc(dev); 281 282 sc->sc_dev = dev; 283 mtx_init(&sc->sc_mtx, "ksz8995ma", NULL, MTX_DEF); 284 strlcpy(sc->info.es_name, device_get_desc(dev), 285 sizeof(sc->info.es_name)); 286 287 /* KSZ8995MA Defaults */ 288 sc->numports = KSZ8995MA_MAX_PORT; 289 sc->phymask = (1 << (KSZ8995MA_MAX_PORT + 1)) - 1; 290 sc->cpuport = -1; 291 sc->media = 100; 292 293 (void) resource_int_value(device_get_name(dev), device_get_unit(dev), 294 "cpuport", &sc->cpuport); 295 296 sc->info.es_nvlangroups = 16; 297 sc->info.es_vlan_caps = ETHERSWITCH_VLAN_PORT | ETHERSWITCH_VLAN_DOT1Q; 298 299 sc->ifp = malloc(sizeof(if_t) * sc->numports, M_KSZ8995MA, 300 M_WAITOK | M_ZERO); 301 sc->ifname = malloc(sizeof(char *) * sc->numports, M_KSZ8995MA, 302 M_WAITOK | M_ZERO); 303 sc->miibus = malloc(sizeof(device_t *) * sc->numports, M_KSZ8995MA, 304 M_WAITOK | M_ZERO); 305 sc->portphy = malloc(sizeof(int) * sc->numports, M_KSZ8995MA, 306 M_WAITOK | M_ZERO); 307 308 if (sc->ifp == NULL || sc->ifname == NULL || sc->miibus == NULL || 309 sc->portphy == NULL) { 310 err = ENOMEM; 311 goto failed; 312 } 313 314 /* 315 * Attach the PHYs and complete the bus enumeration. 316 */ 317 err = ksz8995ma_attach_phys(sc); 318 if (err != 0) 319 goto failed; 320 321 bus_generic_probe(dev); 322 bus_enumerate_hinted_children(dev); 323 err = bus_generic_attach(dev); 324 if (err != 0) 325 goto failed; 326 327 callout_init(&sc->callout_tick, 0); 328 329 ksz8995ma_tick(sc); 330 331 /* start switch */ 332 sc->vlan_mode = 0; 333 reg = ksz8995ma_readreg(dev, KSZ8995MA_GC3); 334 ksz8995ma_writereg(dev, KSZ8995MA_GC3, 335 reg & ~KSZ8995MA_VLAN_ENABLE); 336 ksz8995ma_portvlanreset(dev); 337 ksz8995ma_writereg(dev, KSZ8995MA_CID1, KSZ8995MA_START); 338 339 return (0); 340 341 failed: 342 if (sc->portphy != NULL) 343 free(sc->portphy, M_KSZ8995MA); 344 if (sc->miibus != NULL) 345 free(sc->miibus, M_KSZ8995MA); 346 if (sc->ifname != NULL) 347 free(sc->ifname, M_KSZ8995MA); 348 if (sc->ifp != NULL) 349 free(sc->ifp, M_KSZ8995MA); 350 351 return (err); 352 } 353 354 static int 355 ksz8995ma_detach(device_t dev) 356 { 357 struct ksz8995ma_softc *sc; 358 int i, port; 359 360 sc = device_get_softc(dev); 361 362 callout_drain(&sc->callout_tick); 363 364 for (i = 0; i < KSZ8995MA_MAX_PORT; i++) { 365 if (((1 << i) & sc->phymask) == 0) 366 continue; 367 port = ksz8995ma_portforphy(sc, i); 368 if (sc->miibus[port] != NULL) 369 device_delete_child(dev, (*sc->miibus[port])); 370 if (sc->ifp[port] != NULL) 371 if_free(sc->ifp[port]); 372 free(sc->ifname[port], M_KSZ8995MA); 373 free(sc->miibus[port], M_KSZ8995MA); 374 } 375 376 free(sc->portphy, M_KSZ8995MA); 377 free(sc->miibus, M_KSZ8995MA); 378 free(sc->ifname, M_KSZ8995MA); 379 free(sc->ifp, M_KSZ8995MA); 380 381 bus_generic_detach(dev); 382 mtx_destroy(&sc->sc_mtx); 383 384 return (0); 385 } 386 387 /* 388 * Convert PHY number to port number. 389 */ 390 static inline int 391 ksz8995ma_portforphy(struct ksz8995ma_softc *sc, int phy) 392 { 393 394 return (sc->ifpport[phy]); 395 } 396 397 static inline struct mii_data * 398 ksz8995ma_miiforport(struct ksz8995ma_softc *sc, int port) 399 { 400 401 if (port < 0 || port > sc->numports) 402 return (NULL); 403 if (port == sc->cpuport) 404 return (NULL); 405 return (device_get_softc(*sc->miibus[port])); 406 } 407 408 static inline if_t 409 ksz8995ma_ifpforport(struct ksz8995ma_softc *sc, int port) 410 { 411 412 if (port < 0 || port > sc->numports) 413 return (NULL); 414 return (sc->ifp[port]); 415 } 416 417 /* 418 * Poll the status for all PHYs. 419 */ 420 static void 421 ksz8995ma_miipollstat(struct ksz8995ma_softc *sc) 422 { 423 int i, port; 424 struct mii_data *mii; 425 struct mii_softc *miisc; 426 427 KSZ8995MA_LOCK_ASSERT(sc, MA_NOTOWNED); 428 429 for (i = 0; i < KSZ8995MA_MAX_PORT; i++) { 430 if (i == sc->cpuport) 431 continue; 432 if (((1 << i) & sc->phymask) == 0) 433 continue; 434 port = ksz8995ma_portforphy(sc, i); 435 if ((*sc->miibus[port]) == NULL) 436 continue; 437 mii = device_get_softc(*sc->miibus[port]); 438 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) { 439 if (IFM_INST(mii->mii_media.ifm_cur->ifm_media) != 440 miisc->mii_inst) 441 continue; 442 ukphy_status(miisc); 443 mii_phy_update(miisc, MII_POLLSTAT); 444 } 445 } 446 } 447 448 static void 449 ksz8995ma_tick(void *arg) 450 { 451 struct ksz8995ma_softc *sc; 452 453 sc = arg; 454 455 ksz8995ma_miipollstat(sc); 456 callout_reset(&sc->callout_tick, hz, ksz8995ma_tick, sc); 457 } 458 459 static void 460 ksz8995ma_lock(device_t dev) 461 { 462 struct ksz8995ma_softc *sc; 463 464 sc = device_get_softc(dev); 465 466 KSZ8995MA_LOCK_ASSERT(sc, MA_NOTOWNED); 467 KSZ8995MA_LOCK(sc); 468 } 469 470 static void 471 ksz8995ma_unlock(device_t dev) 472 { 473 struct ksz8995ma_softc *sc; 474 475 sc = device_get_softc(dev); 476 477 KSZ8995MA_LOCK_ASSERT(sc, MA_OWNED); 478 KSZ8995MA_UNLOCK(sc); 479 } 480 481 static etherswitch_info_t * 482 ksz8995ma_getinfo(device_t dev) 483 { 484 struct ksz8995ma_softc *sc; 485 486 sc = device_get_softc(dev); 487 488 return (&sc->info); 489 } 490 491 static int 492 ksz8995ma_getport(device_t dev, etherswitch_port_t *p) 493 { 494 struct ksz8995ma_softc *sc; 495 struct mii_data *mii; 496 struct ifmediareq *ifmr; 497 int phy, err; 498 int tag1, tag2, portreg; 499 500 sc = device_get_softc(dev); 501 ifmr = &p->es_ifmr; 502 503 if (p->es_port < 0 || p->es_port >= sc->numports) 504 return (ENXIO); 505 506 if (sc->vlan_mode == ETHERSWITCH_VLAN_DOT1Q) { 507 tag1 = ksz8995ma_readreg(dev, KSZ8995MA_PC3_BASE + 508 KSZ8995MA_PORT_SIZE * p->es_port); 509 tag2 = ksz8995ma_readreg(dev, KSZ8995MA_PC4_BASE + 510 KSZ8995MA_PORT_SIZE * p->es_port); 511 p->es_pvid = (tag1 & 0x0f) << 8 | tag2; 512 513 portreg = ksz8995ma_readreg(dev, KSZ8995MA_PC0_BASE + 514 KSZ8995MA_PORT_SIZE * p->es_port); 515 if (portreg & KSZ8995MA_TAG_INS) 516 p->es_flags |= ETHERSWITCH_PORT_ADDTAG; 517 if (portreg & KSZ8995MA_TAG_RM) 518 p->es_flags |= ETHERSWITCH_PORT_STRIPTAG; 519 520 portreg = ksz8995ma_readreg(dev, KSZ8995MA_PC2_BASE + 521 KSZ8995MA_PORT_SIZE * p->es_port); 522 if (portreg & KSZ8995MA_DROP_NONPVID) 523 p->es_flags |= ETHERSWITCH_PORT_DROPUNTAGGED; 524 if (portreg & KSZ8995MA_INGR_FILT) 525 p->es_flags |= ETHERSWITCH_PORT_INGRESS; 526 } 527 528 phy = sc->portphy[p->es_port]; 529 mii = ksz8995ma_miiforport(sc, p->es_port); 530 if (sc->cpuport != -1 && phy == sc->cpuport) { 531 /* fill in fixed values for CPU port */ 532 p->es_flags |= ETHERSWITCH_PORT_CPU; 533 ifmr->ifm_count = 0; 534 if (sc->media == 100) 535 ifmr->ifm_current = ifmr->ifm_active = 536 IFM_ETHER | IFM_100_TX | IFM_FDX; 537 else 538 ifmr->ifm_current = ifmr->ifm_active = 539 IFM_ETHER | IFM_1000_T | IFM_FDX; 540 ifmr->ifm_mask = 0; 541 ifmr->ifm_status = IFM_ACTIVE | IFM_AVALID; 542 } else if (mii != NULL) { 543 err = ifmedia_ioctl(mii->mii_ifp, &p->es_ifr, 544 &mii->mii_media, SIOCGIFMEDIA); 545 if (err) 546 return (err); 547 } else { 548 return (ENXIO); 549 } 550 551 return (0); 552 } 553 554 static int 555 ksz8995ma_setport(device_t dev, etherswitch_port_t *p) 556 { 557 struct ksz8995ma_softc *sc; 558 struct mii_data *mii; 559 struct ifmedia *ifm; 560 if_t ifp; 561 int phy, err; 562 int portreg; 563 564 sc = device_get_softc(dev); 565 566 if (p->es_port < 0 || p->es_port >= sc->numports) 567 return (ENXIO); 568 569 if (sc->vlan_mode == ETHERSWITCH_VLAN_DOT1Q) { 570 ksz8995ma_writereg(dev, KSZ8995MA_PC4_BASE + 571 KSZ8995MA_PORT_SIZE * p->es_port, p->es_pvid & 0xff); 572 portreg = ksz8995ma_readreg(dev, KSZ8995MA_PC3_BASE + 573 KSZ8995MA_PORT_SIZE * p->es_port); 574 ksz8995ma_writereg(dev, KSZ8995MA_PC3_BASE + 575 KSZ8995MA_PORT_SIZE * p->es_port, 576 (portreg & 0xf0) | ((p->es_pvid >> 8) & 0x0f)); 577 578 portreg = ksz8995ma_readreg(dev, KSZ8995MA_PC0_BASE + 579 KSZ8995MA_PORT_SIZE * p->es_port); 580 if (p->es_flags & ETHERSWITCH_PORT_ADDTAG) 581 portreg |= KSZ8995MA_TAG_INS; 582 else 583 portreg &= ~KSZ8995MA_TAG_INS; 584 if (p->es_flags & ETHERSWITCH_PORT_STRIPTAG) 585 portreg |= KSZ8995MA_TAG_RM; 586 else 587 portreg &= ~KSZ8995MA_TAG_RM; 588 ksz8995ma_writereg(dev, KSZ8995MA_PC0_BASE + 589 KSZ8995MA_PORT_SIZE * p->es_port, portreg); 590 591 portreg = ksz8995ma_readreg(dev, KSZ8995MA_PC2_BASE + 592 KSZ8995MA_PORT_SIZE * p->es_port); 593 if (p->es_flags & ETHERSWITCH_PORT_DROPUNTAGGED) 594 portreg |= KSZ8995MA_DROP_NONPVID; 595 else 596 portreg &= ~KSZ8995MA_DROP_NONPVID; 597 if (p->es_flags & ETHERSWITCH_PORT_INGRESS) 598 portreg |= KSZ8995MA_INGR_FILT; 599 else 600 portreg &= ~KSZ8995MA_INGR_FILT; 601 ksz8995ma_writereg(dev, KSZ8995MA_PC2_BASE + 602 KSZ8995MA_PORT_SIZE * p->es_port, portreg); 603 } 604 605 phy = sc->portphy[p->es_port]; 606 mii = ksz8995ma_miiforport(sc, p->es_port); 607 if (phy != sc->cpuport) { 608 if (mii == NULL) 609 return (ENXIO); 610 ifp = ksz8995ma_ifpforport(sc, p->es_port); 611 ifm = &mii->mii_media; 612 err = ifmedia_ioctl(ifp, &p->es_ifr, ifm, SIOCSIFMEDIA); 613 } 614 return (0); 615 } 616 617 static int 618 ksz8995ma_getvgroup(device_t dev, etherswitch_vlangroup_t *vg) 619 { 620 int data0, data1, data2; 621 int vlantab; 622 struct ksz8995ma_softc *sc; 623 624 sc = device_get_softc(dev); 625 626 if (sc->vlan_mode == ETHERSWITCH_VLAN_PORT) { 627 if (vg->es_vlangroup < sc->numports) { 628 vg->es_vid = ETHERSWITCH_VID_VALID; 629 vg->es_vid |= vg->es_vlangroup; 630 data0 = ksz8995ma_readreg(dev, KSZ8995MA_PC1_BASE + 631 KSZ8995MA_PORT_SIZE * vg->es_vlangroup); 632 vg->es_member_ports = data0 & 0x1f; 633 vg->es_untagged_ports = vg->es_member_ports; 634 vg->es_fid = 0; 635 } else { 636 vg->es_vid = 0; 637 } 638 } else if (sc->vlan_mode == ETHERSWITCH_VLAN_DOT1Q) { 639 ksz8995ma_writereg(dev, KSZ8995MA_IAC0, 640 KSZ8995MA_VLAN_TABLE_READ); 641 ksz8995ma_writereg(dev, KSZ8995MA_IAC1, vg->es_vlangroup); 642 data2 = ksz8995ma_readreg(dev, KSZ8995MA_IDR2); 643 data1 = ksz8995ma_readreg(dev, KSZ8995MA_IDR1); 644 data0 = ksz8995ma_readreg(dev, KSZ8995MA_IDR0); 645 vlantab = data2 << 16 | data1 << 8 | data0; 646 if (data2 & KSZ8995MA_VLAN_TABLE_VALID) { 647 vg->es_vid = ETHERSWITCH_VID_VALID; 648 vg->es_vid |= vlantab & 0xfff; 649 vg->es_member_ports = (vlantab >> 16) & 0x1f; 650 vg->es_untagged_ports = vg->es_member_ports; 651 vg->es_fid = (vlantab >> 12) & 0x0f; 652 } else { 653 vg->es_fid = 0; 654 } 655 } 656 657 return (0); 658 } 659 660 static int 661 ksz8995ma_setvgroup(device_t dev, etherswitch_vlangroup_t *vg) 662 { 663 struct ksz8995ma_softc *sc; 664 int data0; 665 666 sc = device_get_softc(dev); 667 668 if (sc->vlan_mode == ETHERSWITCH_VLAN_PORT) { 669 data0 = ksz8995ma_readreg(dev, KSZ8995MA_PC1_BASE + 670 KSZ8995MA_PORT_SIZE * vg->es_vlangroup); 671 ksz8995ma_writereg(dev, KSZ8995MA_PC1_BASE + 672 KSZ8995MA_PORT_SIZE * vg->es_vlangroup, 673 (data0 & 0xe0) | (vg->es_member_ports & 0x1f)); 674 } else if (sc->vlan_mode == ETHERSWITCH_VLAN_DOT1Q) { 675 if (vg->es_member_ports != 0) { 676 ksz8995ma_writereg(dev, KSZ8995MA_IDR2, 677 KSZ8995MA_VLAN_TABLE_VALID | 678 (vg->es_member_ports & 0x1f)); 679 ksz8995ma_writereg(dev, KSZ8995MA_IDR1, 680 vg->es_fid << 4 | vg->es_vid >> 8); 681 ksz8995ma_writereg(dev, KSZ8995MA_IDR0, 682 vg->es_vid & 0xff); 683 } else { 684 ksz8995ma_writereg(dev, KSZ8995MA_IDR2, 0); 685 ksz8995ma_writereg(dev, KSZ8995MA_IDR1, 0); 686 ksz8995ma_writereg(dev, KSZ8995MA_IDR0, 0); 687 } 688 ksz8995ma_writereg(dev, KSZ8995MA_IAC0, 689 KSZ8995MA_VLAN_TABLE_WRITE); 690 ksz8995ma_writereg(dev, KSZ8995MA_IAC1, vg->es_vlangroup); 691 } 692 693 return (0); 694 } 695 696 static int 697 ksz8995ma_getconf(device_t dev, etherswitch_conf_t *conf) 698 { 699 struct ksz8995ma_softc *sc; 700 701 sc = device_get_softc(dev); 702 703 /* Return the VLAN mode. */ 704 conf->cmd = ETHERSWITCH_CONF_VLAN_MODE; 705 conf->vlan_mode = sc->vlan_mode; 706 707 return (0); 708 } 709 710 static void 711 ksz8995ma_portvlanreset(device_t dev) 712 { 713 int i, data; 714 struct ksz8995ma_softc *sc; 715 716 sc = device_get_softc(dev); 717 718 for (i = 0; i < sc->numports; ++i) { 719 data = ksz8995ma_readreg(dev, KSZ8995MA_PC1_BASE + 720 KSZ8995MA_PORT_SIZE * i); 721 ksz8995ma_writereg(dev, KSZ8995MA_PC1_BASE + 722 KSZ8995MA_PORT_SIZE * i, (data & 0xe0) | 0x1f); 723 } 724 } 725 726 static int 727 ksz8995ma_setconf(device_t dev, etherswitch_conf_t *conf) 728 { 729 int reg; 730 struct ksz8995ma_softc *sc; 731 732 sc = device_get_softc(dev); 733 734 if ((conf->cmd & ETHERSWITCH_CONF_VLAN_MODE) == 0) 735 return (0); 736 737 if (conf->vlan_mode == ETHERSWITCH_VLAN_PORT) { 738 sc->vlan_mode = ETHERSWITCH_VLAN_PORT; 739 reg = ksz8995ma_readreg(dev, KSZ8995MA_GC3); 740 ksz8995ma_writereg(dev, KSZ8995MA_GC3, 741 reg & ~KSZ8995MA_VLAN_ENABLE); 742 ksz8995ma_portvlanreset(dev); 743 } else if (conf->vlan_mode == ETHERSWITCH_VLAN_DOT1Q) { 744 sc->vlan_mode = ETHERSWITCH_VLAN_DOT1Q; 745 reg = ksz8995ma_readreg(dev, KSZ8995MA_GC3); 746 ksz8995ma_writereg(dev, KSZ8995MA_GC3, 747 reg | KSZ8995MA_VLAN_ENABLE); 748 } else { 749 sc->vlan_mode = 0; 750 reg = ksz8995ma_readreg(dev, KSZ8995MA_GC3); 751 ksz8995ma_writereg(dev, KSZ8995MA_GC3, 752 reg & ~KSZ8995MA_VLAN_ENABLE); 753 ksz8995ma_portvlanreset(dev); 754 } 755 return (0); 756 } 757 758 static void 759 ksz8995ma_statchg(device_t dev) 760 { 761 762 DPRINTF(dev, "%s\n", __func__); 763 } 764 765 static int 766 ksz8995ma_ifmedia_upd(if_t ifp) 767 { 768 struct ksz8995ma_softc *sc; 769 struct mii_data *mii; 770 771 sc = if_getsoftc(ifp); 772 mii = ksz8995ma_miiforport(sc, if_getdunit(ifp)); 773 774 DPRINTF(sc->sc_dev, "%s\n", __func__); 775 if (mii == NULL) 776 return (ENXIO); 777 mii_mediachg(mii); 778 return (0); 779 } 780 781 static void 782 ksz8995ma_ifmedia_sts(if_t ifp, struct ifmediareq *ifmr) 783 { 784 struct ksz8995ma_softc *sc; 785 struct mii_data *mii; 786 787 sc = if_getsoftc(ifp); 788 mii = ksz8995ma_miiforport(sc, if_getdunit(ifp)); 789 790 DPRINTF(sc->sc_dev, "%s\n", __func__); 791 792 if (mii == NULL) 793 return; 794 mii_pollstat(mii); 795 ifmr->ifm_active = mii->mii_media_active; 796 ifmr->ifm_status = mii->mii_media_status; 797 } 798 799 static int 800 ksz8995ma_readphy(device_t dev, int phy, int reg) 801 { 802 int portreg; 803 804 /* 805 * This is no mdio/mdc connection code. 806 * simulate MIIM Registers via the SPI interface 807 */ 808 if (reg == MII_BMSR) { 809 portreg = ksz8995ma_readreg(dev, KSZ8995MA_PS0_BASE + 810 KSZ8995MA_PORT_SIZE * phy); 811 return (KSZ8995MA_MII_STAT | 812 (portreg & 0x20 ? BMSR_LINK : 0x00) | 813 (portreg & 0x40 ? BMSR_ACOMP : 0x00)); 814 } else if (reg == MII_PHYIDR1) { 815 return (KSZ8995MA_MII_PHYID_H); 816 } else if (reg == MII_PHYIDR2) { 817 return (KSZ8995MA_MII_PHYID_L); 818 } else if (reg == MII_ANAR) { 819 portreg = ksz8995ma_readreg(dev, KSZ8995MA_PC12_BASE + 820 KSZ8995MA_PORT_SIZE * phy); 821 return (KSZ8995MA_MII_AA | (portreg & 0x0f) << 5); 822 } else if (reg == MII_ANLPAR) { 823 portreg = ksz8995ma_readreg(dev, KSZ8995MA_PS0_BASE + 824 KSZ8995MA_PORT_SIZE * phy); 825 return (((portreg & 0x0f) << 5) | 0x01); 826 } 827 828 return (0); 829 } 830 831 static int 832 ksz8995ma_writephy(device_t dev, int phy, int reg, int data) 833 { 834 int portreg; 835 836 /* 837 * This is no mdio/mdc connection code. 838 * simulate MIIM Registers via the SPI interface 839 */ 840 if (reg == MII_BMCR) { 841 portreg = ksz8995ma_readreg(dev, KSZ8995MA_PC13_BASE + 842 KSZ8995MA_PORT_SIZE * phy); 843 if (data & BMCR_PDOWN) 844 portreg |= KSZ8995MA_PDOWN; 845 else 846 portreg &= ~KSZ8995MA_PDOWN; 847 if (data & BMCR_STARTNEG) 848 portreg |= KSZ8995MA_STARTNEG; 849 else 850 portreg &= ~KSZ8995MA_STARTNEG; 851 ksz8995ma_writereg(dev, KSZ8995MA_PC13_BASE + 852 KSZ8995MA_PORT_SIZE * phy, portreg); 853 } else if (reg == MII_ANAR) { 854 portreg = ksz8995ma_readreg(dev, KSZ8995MA_PC12_BASE + 855 KSZ8995MA_PORT_SIZE * phy); 856 portreg &= 0xf; 857 portreg |= ((data >> 5) & 0x0f); 858 ksz8995ma_writereg(dev, KSZ8995MA_PC12_BASE + 859 KSZ8995MA_PORT_SIZE * phy, portreg); 860 } 861 return (0); 862 } 863 864 static int 865 ksz8995ma_readreg(device_t dev, int addr) 866 { 867 uint8_t txBuf[8], rxBuf[8]; 868 struct spi_command cmd; 869 int err; 870 871 memset(&cmd, 0, sizeof(cmd)); 872 memset(txBuf, 0, sizeof(txBuf)); 873 memset(rxBuf, 0, sizeof(rxBuf)); 874 875 /* read spi */ 876 txBuf[0] = KSZ8995MA_SPI_READ; 877 txBuf[1] = addr; 878 cmd.tx_cmd = &txBuf; 879 cmd.rx_cmd = &rxBuf; 880 cmd.tx_cmd_sz = 3; 881 cmd.rx_cmd_sz = 3; 882 err = SPIBUS_TRANSFER(device_get_parent(dev), dev, &cmd); 883 if (err) 884 return(0); 885 886 return (rxBuf[2]); 887 } 888 889 static int 890 ksz8995ma_writereg(device_t dev, int addr, int value) 891 { 892 uint8_t txBuf[8], rxBuf[8]; 893 struct spi_command cmd; 894 int err; 895 896 memset(&cmd, 0, sizeof(cmd)); 897 memset(txBuf, 0, sizeof(txBuf)); 898 memset(rxBuf, 0, sizeof(rxBuf)); 899 900 /* write spi */ 901 txBuf[0] = KSZ8995MA_SPI_WRITE; 902 txBuf[1] = addr; 903 txBuf[2] = value; 904 cmd.tx_cmd = &txBuf; 905 cmd.rx_cmd = &rxBuf; 906 cmd.tx_cmd_sz = 3; 907 cmd.rx_cmd_sz = 3; 908 err = SPIBUS_TRANSFER(device_get_parent(dev), dev, &cmd); 909 if (err) 910 return(0); 911 912 return (0); 913 } 914 915 static device_method_t ksz8995ma_methods[] = { 916 /* Device interface */ 917 DEVMETHOD(device_probe, ksz8995ma_probe), 918 DEVMETHOD(device_attach, ksz8995ma_attach), 919 DEVMETHOD(device_detach, ksz8995ma_detach), 920 921 /* bus interface */ 922 DEVMETHOD(bus_add_child, device_add_child_ordered), 923 924 /* MII interface */ 925 DEVMETHOD(miibus_readreg, ksz8995ma_readphy), 926 DEVMETHOD(miibus_writereg, ksz8995ma_writephy), 927 DEVMETHOD(miibus_statchg, ksz8995ma_statchg), 928 929 /* etherswitch interface */ 930 DEVMETHOD(etherswitch_lock, ksz8995ma_lock), 931 DEVMETHOD(etherswitch_unlock, ksz8995ma_unlock), 932 DEVMETHOD(etherswitch_getinfo, ksz8995ma_getinfo), 933 DEVMETHOD(etherswitch_readreg, ksz8995ma_readreg), 934 DEVMETHOD(etherswitch_writereg, ksz8995ma_writereg), 935 DEVMETHOD(etherswitch_readphyreg, ksz8995ma_readphy), 936 DEVMETHOD(etherswitch_writephyreg, ksz8995ma_writephy), 937 DEVMETHOD(etherswitch_getport, ksz8995ma_getport), 938 DEVMETHOD(etherswitch_setport, ksz8995ma_setport), 939 DEVMETHOD(etherswitch_getvgroup, ksz8995ma_getvgroup), 940 DEVMETHOD(etherswitch_setvgroup, ksz8995ma_setvgroup), 941 DEVMETHOD(etherswitch_setconf, ksz8995ma_setconf), 942 DEVMETHOD(etherswitch_getconf, ksz8995ma_getconf), 943 944 DEVMETHOD_END 945 }; 946 947 DEFINE_CLASS_0(ksz8995ma, ksz8995ma_driver, ksz8995ma_methods, 948 sizeof(struct ksz8995ma_softc)); 949 950 DRIVER_MODULE(ksz8995ma, spibus, ksz8995ma_driver, 0, 0); 951 DRIVER_MODULE(miibus, ksz8995ma, miibus_driver, 0, 0); 952 DRIVER_MODULE(etherswitch, ksz8995ma, etherswitch_driver, 0, 0); 953 MODULE_VERSION(ksz8995ma, 1); 954 MODULE_DEPEND(ksz8995ma, spibus, 1, 1, 1); /* XXX which versions? */ 955 MODULE_DEPEND(ksz8995ma, miibus, 1, 1, 1); /* XXX which versions? */ 956 MODULE_DEPEND(ksz8995ma, etherswitch, 1, 1, 1); /* XXX which versions? */ 957