1d3bafe1dSMichael Zhilin /*- 2d3bafe1dSMichael Zhilin * Copyright (c) 2016 Hiroki Mori 3d3bafe1dSMichael Zhilin * Copyright (c) 2013 Luiz Otavio O Souza. 4d3bafe1dSMichael Zhilin * Copyright (c) 2011-2012 Stefan Bethke. 5d3bafe1dSMichael Zhilin * Copyright (c) 2012 Adrian Chadd. 6d3bafe1dSMichael Zhilin * All rights reserved. 7d3bafe1dSMichael Zhilin * 8d3bafe1dSMichael Zhilin * Redistribution and use in source and binary forms, with or without 9d3bafe1dSMichael Zhilin * modification, are permitted provided that the following conditions 10d3bafe1dSMichael Zhilin * are met: 11d3bafe1dSMichael Zhilin * 1. Redistributions of source code must retain the above copyright 12d3bafe1dSMichael Zhilin * notice, this list of conditions and the following disclaimer. 13d3bafe1dSMichael Zhilin * 2. Redistributions in binary form must reproduce the above copyright 14d3bafe1dSMichael Zhilin * notice, this list of conditions and the following disclaimer in the 15d3bafe1dSMichael Zhilin * documentation and/or other materials provided with the distribution. 16d3bafe1dSMichael Zhilin * 17d3bafe1dSMichael Zhilin * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18d3bafe1dSMichael Zhilin * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19d3bafe1dSMichael Zhilin * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20d3bafe1dSMichael Zhilin * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21d3bafe1dSMichael Zhilin * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22d3bafe1dSMichael Zhilin * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23d3bafe1dSMichael Zhilin * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24d3bafe1dSMichael Zhilin * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25d3bafe1dSMichael Zhilin * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26d3bafe1dSMichael Zhilin * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27d3bafe1dSMichael Zhilin * SUCH DAMAGE. 28d3bafe1dSMichael Zhilin */ 29d3bafe1dSMichael Zhilin 30d3bafe1dSMichael Zhilin /* 31d3bafe1dSMichael Zhilin * This is Micrel KSZ8995MA driver code. KSZ8995MA use SPI bus on control. 32d3bafe1dSMichael Zhilin * This code development on @SRCHACK's ksz8995ma board and FON2100 with 33d3bafe1dSMichael Zhilin * gpiospi. 34d3bafe1dSMichael Zhilin * etherswitchcfg command port option support addtag, ingress, striptag, 35d3bafe1dSMichael Zhilin * dropuntagged. 36d3bafe1dSMichael Zhilin */ 37d3bafe1dSMichael Zhilin 38d3bafe1dSMichael Zhilin #include <sys/param.h> 39d3bafe1dSMichael Zhilin #include <sys/bus.h> 40d3bafe1dSMichael Zhilin #include <sys/errno.h> 41d3bafe1dSMichael Zhilin #include <sys/kernel.h> 42d3bafe1dSMichael Zhilin #include <sys/lock.h> 43d3bafe1dSMichael Zhilin #include <sys/malloc.h> 44d3bafe1dSMichael Zhilin #include <sys/module.h> 45d3bafe1dSMichael Zhilin #include <sys/mutex.h> 46d3bafe1dSMichael Zhilin #include <sys/socket.h> 47d3bafe1dSMichael Zhilin #include <sys/sockio.h> 48d3bafe1dSMichael Zhilin #include <sys/sysctl.h> 49d3bafe1dSMichael Zhilin #include <sys/systm.h> 50d3bafe1dSMichael Zhilin 51d3bafe1dSMichael Zhilin #include <net/if.h> 52d3bafe1dSMichael Zhilin #include <net/if_var.h> 53d3bafe1dSMichael Zhilin #include <net/ethernet.h> 54d3bafe1dSMichael Zhilin #include <net/if_media.h> 55d3bafe1dSMichael Zhilin #include <net/if_types.h> 56d3bafe1dSMichael Zhilin 57d3bafe1dSMichael Zhilin #include <machine/bus.h> 58d3bafe1dSMichael Zhilin #include <dev/mii/mii.h> 59d3bafe1dSMichael Zhilin #include <dev/mii/miivar.h> 60d3bafe1dSMichael Zhilin 61d3bafe1dSMichael Zhilin #include <dev/etherswitch/etherswitch.h> 62d3bafe1dSMichael Zhilin 63d3bafe1dSMichael Zhilin #include <dev/spibus/spi.h> 64d3bafe1dSMichael Zhilin 65d3bafe1dSMichael Zhilin #include "spibus_if.h" 66d3bafe1dSMichael Zhilin #include "miibus_if.h" 67d3bafe1dSMichael Zhilin #include "etherswitch_if.h" 68d3bafe1dSMichael Zhilin 69d3bafe1dSMichael Zhilin #define KSZ8995MA_SPI_READ 0x03 70d3bafe1dSMichael Zhilin #define KSZ8995MA_SPI_WRITE 0x02 71d3bafe1dSMichael Zhilin 72d3bafe1dSMichael Zhilin #define KSZ8995MA_CID0 0x00 73d3bafe1dSMichael Zhilin #define KSZ8995MA_CID1 0x01 74d3bafe1dSMichael Zhilin 75d3bafe1dSMichael Zhilin #define KSZ8995MA_GC0 0x02 76d3bafe1dSMichael Zhilin #define KSZ8995MA_GC1 0x03 77d3bafe1dSMichael Zhilin #define KSZ8995MA_GC2 0x04 78d3bafe1dSMichael Zhilin #define KSZ8995MA_GC3 0x05 79d3bafe1dSMichael Zhilin 80d3bafe1dSMichael Zhilin #define KSZ8995MA_PORT_SIZE 0x10 81d3bafe1dSMichael Zhilin 82d3bafe1dSMichael Zhilin #define KSZ8995MA_PC0_BASE 0x10 83d3bafe1dSMichael Zhilin #define KSZ8995MA_PC1_BASE 0x11 84d3bafe1dSMichael Zhilin #define KSZ8995MA_PC2_BASE 0x12 85d3bafe1dSMichael Zhilin #define KSZ8995MA_PC3_BASE 0x13 86d3bafe1dSMichael Zhilin #define KSZ8995MA_PC4_BASE 0x14 87d3bafe1dSMichael Zhilin #define KSZ8995MA_PC5_BASE 0x15 88d3bafe1dSMichael Zhilin #define KSZ8995MA_PC6_BASE 0x16 89d3bafe1dSMichael Zhilin #define KSZ8995MA_PC7_BASE 0x17 90d3bafe1dSMichael Zhilin #define KSZ8995MA_PC8_BASE 0x18 91d3bafe1dSMichael Zhilin #define KSZ8995MA_PC9_BASE 0x19 92d3bafe1dSMichael Zhilin #define KSZ8995MA_PC10_BASE 0x1a 93d3bafe1dSMichael Zhilin #define KSZ8995MA_PC11_BASE 0x1b 94d3bafe1dSMichael Zhilin #define KSZ8995MA_PC12_BASE 0x1c 95d3bafe1dSMichael Zhilin #define KSZ8995MA_PC13_BASE 0x1d 96d3bafe1dSMichael Zhilin 97d3bafe1dSMichael Zhilin #define KSZ8995MA_PS0_BASE 0x1e 98d3bafe1dSMichael Zhilin 99d3bafe1dSMichael Zhilin #define KSZ8995MA_PC14_BASE 0x1f 100d3bafe1dSMichael Zhilin 101d3bafe1dSMichael Zhilin #define KSZ8995MA_IAC0 0x6e 102d3bafe1dSMichael Zhilin #define KSZ8995MA_IAC1 0x6f 103d3bafe1dSMichael Zhilin #define KSZ8995MA_IDR8 0x70 104d3bafe1dSMichael Zhilin #define KSZ8995MA_IDR7 0x71 105d3bafe1dSMichael Zhilin #define KSZ8995MA_IDR6 0x72 106d3bafe1dSMichael Zhilin #define KSZ8995MA_IDR5 0x73 107d3bafe1dSMichael Zhilin #define KSZ8995MA_IDR4 0x74 108d3bafe1dSMichael Zhilin #define KSZ8995MA_IDR3 0x75 109d3bafe1dSMichael Zhilin #define KSZ8995MA_IDR2 0x76 110d3bafe1dSMichael Zhilin #define KSZ8995MA_IDR1 0x77 111d3bafe1dSMichael Zhilin #define KSZ8995MA_IDR0 0x78 112d3bafe1dSMichael Zhilin 113d3bafe1dSMichael Zhilin #define KSZ8995MA_FAMILI_ID 0x95 114d3bafe1dSMichael Zhilin #define KSZ8995MA_CHIP_ID 0x00 115d3bafe1dSMichael Zhilin #define KSZ8995MA_CHIP_ID_MASK 0xf0 116d3bafe1dSMichael Zhilin #define KSZ8995MA_START 0x01 117d3bafe1dSMichael Zhilin #define KSZ8995MA_VLAN_ENABLE 0x80 118d3bafe1dSMichael Zhilin #define KSZ8995MA_TAG_INS 0x04 119d3bafe1dSMichael Zhilin #define KSZ8995MA_TAG_RM 0x02 120d3bafe1dSMichael Zhilin #define KSZ8995MA_INGR_FILT 0x40 121d3bafe1dSMichael Zhilin #define KSZ8995MA_DROP_NONPVID 0x20 122d3bafe1dSMichael Zhilin 123d3bafe1dSMichael Zhilin #define KSZ8995MA_PDOWN 0x08 124d3bafe1dSMichael Zhilin #define KSZ8995MA_STARTNEG 0x20 125d3bafe1dSMichael Zhilin 126d3bafe1dSMichael Zhilin #define KSZ8995MA_MII_STAT 0x7808 127d3bafe1dSMichael Zhilin #define KSZ8995MA_MII_PHYID_H 0x0022 128d3bafe1dSMichael Zhilin #define KSZ8995MA_MII_PHYID_L 0x1450 129d3bafe1dSMichael Zhilin #define KSZ8995MA_MII_AA 0x0401 130d3bafe1dSMichael Zhilin 131d3bafe1dSMichael Zhilin #define KSZ8995MA_VLAN_TABLE_VALID 0x20 132d3bafe1dSMichael Zhilin #define KSZ8995MA_VLAN_TABLE_READ 0x14 133d3bafe1dSMichael Zhilin #define KSZ8995MA_VLAN_TABLE_WRITE 0x04 134d3bafe1dSMichael Zhilin 135d3bafe1dSMichael Zhilin #define KSZ8995MA_MAX_PORT 5 136d3bafe1dSMichael Zhilin 137d3bafe1dSMichael Zhilin MALLOC_DECLARE(M_KSZ8995MA); 138d3bafe1dSMichael Zhilin MALLOC_DEFINE(M_KSZ8995MA, "ksz8995ma", "ksz8995ma data structures"); 139d3bafe1dSMichael Zhilin 140d3bafe1dSMichael Zhilin struct ksz8995ma_softc { 141d3bafe1dSMichael Zhilin struct mtx sc_mtx; /* serialize access to softc */ 142d3bafe1dSMichael Zhilin device_t sc_dev; 143d3bafe1dSMichael Zhilin int vlan_mode; 144d3bafe1dSMichael Zhilin int media; /* cpu port media */ 145d3bafe1dSMichael Zhilin int cpuport; /* which PHY is connected to the CPU */ 146d3bafe1dSMichael Zhilin int phymask; /* PHYs we manage */ 147d3bafe1dSMichael Zhilin int numports; /* number of ports */ 148d3bafe1dSMichael Zhilin int ifpport[KSZ8995MA_MAX_PORT]; 149d3bafe1dSMichael Zhilin int *portphy; 150d3bafe1dSMichael Zhilin char **ifname; 151d3bafe1dSMichael Zhilin device_t **miibus; 1522e6a8c1aSJustin Hibbits if_t *ifp; 153d3bafe1dSMichael Zhilin struct callout callout_tick; 154d3bafe1dSMichael Zhilin etherswitch_info_t info; 155d3bafe1dSMichael Zhilin }; 156d3bafe1dSMichael Zhilin 157d3bafe1dSMichael Zhilin #define KSZ8995MA_LOCK(_sc) \ 158d3bafe1dSMichael Zhilin mtx_lock(&(_sc)->sc_mtx) 159d3bafe1dSMichael Zhilin #define KSZ8995MA_UNLOCK(_sc) \ 160d3bafe1dSMichael Zhilin mtx_unlock(&(_sc)->sc_mtx) 161d3bafe1dSMichael Zhilin #define KSZ8995MA_LOCK_ASSERT(_sc, _what) \ 162d3bafe1dSMichael Zhilin mtx_assert(&(_sc)->sc_mtx, (_what)) 163d3bafe1dSMichael Zhilin #define KSZ8995MA_TRYLOCK(_sc) \ 164d3bafe1dSMichael Zhilin mtx_trylock(&(_sc)->sc_mtx) 165d3bafe1dSMichael Zhilin 166d3bafe1dSMichael Zhilin #if defined(DEBUG) 167d3bafe1dSMichael Zhilin #define DPRINTF(dev, args...) device_printf(dev, args) 168d3bafe1dSMichael Zhilin #else 169d3bafe1dSMichael Zhilin #define DPRINTF(dev, args...) 170d3bafe1dSMichael Zhilin #endif 171d3bafe1dSMichael Zhilin 172d3bafe1dSMichael Zhilin static inline int ksz8995ma_portforphy(struct ksz8995ma_softc *, int); 173d3bafe1dSMichael Zhilin static void ksz8995ma_tick(void *); 1742e6a8c1aSJustin Hibbits static int ksz8995ma_ifmedia_upd(if_t); 1752e6a8c1aSJustin Hibbits static void ksz8995ma_ifmedia_sts(if_t, struct ifmediareq *); 176d3bafe1dSMichael Zhilin static int ksz8995ma_readreg(device_t dev, int addr); 177d3bafe1dSMichael Zhilin static int ksz8995ma_writereg(device_t dev, int addr, int value); 178d3bafe1dSMichael Zhilin static void ksz8995ma_portvlanreset(device_t dev); 179d3bafe1dSMichael Zhilin 180d3bafe1dSMichael Zhilin static int 181d3bafe1dSMichael Zhilin ksz8995ma_probe(device_t dev) 182d3bafe1dSMichael Zhilin { 183d3bafe1dSMichael Zhilin int id0, id1; 184d3bafe1dSMichael Zhilin struct ksz8995ma_softc *sc; 185d3bafe1dSMichael Zhilin 186d3bafe1dSMichael Zhilin sc = device_get_softc(dev); 187d3bafe1dSMichael Zhilin bzero(sc, sizeof(*sc)); 188d3bafe1dSMichael Zhilin 189d3bafe1dSMichael Zhilin id0 = ksz8995ma_readreg(dev, KSZ8995MA_CID0); 190d3bafe1dSMichael Zhilin id1 = ksz8995ma_readreg(dev, KSZ8995MA_CID1); 191d3bafe1dSMichael Zhilin if (bootverbose) 192d3bafe1dSMichael Zhilin device_printf(dev,"Chip Identifier Register %x %x\n", id0, id1); 193d3bafe1dSMichael Zhilin 194d3bafe1dSMichael Zhilin /* check Product Code */ 195d3bafe1dSMichael Zhilin if (id0 != KSZ8995MA_FAMILI_ID || (id1 & KSZ8995MA_CHIP_ID_MASK) != 196d3bafe1dSMichael Zhilin KSZ8995MA_CHIP_ID) { 197d3bafe1dSMichael Zhilin return (ENXIO); 198d3bafe1dSMichael Zhilin } 199d3bafe1dSMichael Zhilin 20054482989SMark Johnston device_set_desc(dev, "Micrel KSZ8995MA SPI switch driver"); 201d3bafe1dSMichael Zhilin return (BUS_PROBE_DEFAULT); 202d3bafe1dSMichael Zhilin } 203d3bafe1dSMichael Zhilin 204d3bafe1dSMichael Zhilin static int 205d3bafe1dSMichael Zhilin ksz8995ma_attach_phys(struct ksz8995ma_softc *sc) 206d3bafe1dSMichael Zhilin { 207d3bafe1dSMichael Zhilin int phy, port, err; 208d3bafe1dSMichael Zhilin char name[IFNAMSIZ]; 209d3bafe1dSMichael Zhilin 210d3bafe1dSMichael Zhilin port = 0; 211d3bafe1dSMichael Zhilin err = 0; 212d3bafe1dSMichael Zhilin /* PHYs need an interface, so we generate a dummy one */ 213d3bafe1dSMichael Zhilin snprintf(name, IFNAMSIZ, "%sport", device_get_nameunit(sc->sc_dev)); 214d3bafe1dSMichael Zhilin for (phy = 0; phy < sc->numports; phy++) { 215d3bafe1dSMichael Zhilin if (phy == sc->cpuport) 216d3bafe1dSMichael Zhilin continue; 217d3bafe1dSMichael Zhilin if (((1 << phy) & sc->phymask) == 0) 218d3bafe1dSMichael Zhilin continue; 219d3bafe1dSMichael Zhilin sc->ifpport[phy] = port; 220d3bafe1dSMichael Zhilin sc->portphy[port] = phy; 221d3bafe1dSMichael Zhilin sc->ifp[port] = if_alloc(IFT_ETHER); 222d3bafe1dSMichael Zhilin sc->ifp[port]->if_softc = sc; 223d3bafe1dSMichael Zhilin sc->ifp[port]->if_flags |= IFF_UP | IFF_BROADCAST | 224d3bafe1dSMichael Zhilin IFF_DRV_RUNNING | IFF_SIMPLEX; 225d3bafe1dSMichael Zhilin if_initname(sc->ifp[port], name, port); 226d3bafe1dSMichael Zhilin sc->miibus[port] = malloc(sizeof(device_t), M_KSZ8995MA, 227d3bafe1dSMichael Zhilin M_WAITOK | M_ZERO); 228d3bafe1dSMichael Zhilin err = mii_attach(sc->sc_dev, sc->miibus[port], sc->ifp[port], 229d3bafe1dSMichael Zhilin ksz8995ma_ifmedia_upd, ksz8995ma_ifmedia_sts, \ 230d3bafe1dSMichael Zhilin BMSR_DEFCAPMASK, phy, MII_OFFSET_ANY, 0); 231d3bafe1dSMichael Zhilin DPRINTF(sc->sc_dev, "%s attached to pseudo interface %s\n", 232d3bafe1dSMichael Zhilin device_get_nameunit(*sc->miibus[port]), 233d3bafe1dSMichael Zhilin sc->ifp[port]->if_xname); 234d3bafe1dSMichael Zhilin if (err != 0) { 235d3bafe1dSMichael Zhilin device_printf(sc->sc_dev, 236d3bafe1dSMichael Zhilin "attaching PHY %d failed\n", 237d3bafe1dSMichael Zhilin phy); 238d3bafe1dSMichael Zhilin goto failed; 239d3bafe1dSMichael Zhilin } 240d3bafe1dSMichael Zhilin ++port; 241d3bafe1dSMichael Zhilin } 242d3bafe1dSMichael Zhilin sc->info.es_nports = port; 243d3bafe1dSMichael Zhilin if (sc->cpuport != -1) { 244d3bafe1dSMichael Zhilin /* cpu port is MAC5 on ksz8995ma */ 245d3bafe1dSMichael Zhilin sc->ifpport[sc->cpuport] = port; 246d3bafe1dSMichael Zhilin sc->portphy[port] = sc->cpuport; 247d3bafe1dSMichael Zhilin ++sc->info.es_nports; 248d3bafe1dSMichael Zhilin } 249d3bafe1dSMichael Zhilin 250d3bafe1dSMichael Zhilin return (0); 251d3bafe1dSMichael Zhilin 252d3bafe1dSMichael Zhilin failed: 253d3bafe1dSMichael Zhilin for (phy = 0; phy < sc->numports; phy++) { 254d3bafe1dSMichael Zhilin if (((1 << phy) & sc->phymask) == 0) 255d3bafe1dSMichael Zhilin continue; 256d3bafe1dSMichael Zhilin port = ksz8995ma_portforphy(sc, phy); 257d3bafe1dSMichael Zhilin if (sc->miibus[port] != NULL) 258d3bafe1dSMichael Zhilin device_delete_child(sc->sc_dev, (*sc->miibus[port])); 259d3bafe1dSMichael Zhilin if (sc->ifp[port] != NULL) 260d3bafe1dSMichael Zhilin if_free(sc->ifp[port]); 261d3bafe1dSMichael Zhilin if (sc->ifname[port] != NULL) 262d3bafe1dSMichael Zhilin free(sc->ifname[port], M_KSZ8995MA); 263d3bafe1dSMichael Zhilin if (sc->miibus[port] != NULL) 264d3bafe1dSMichael Zhilin free(sc->miibus[port], M_KSZ8995MA); 265d3bafe1dSMichael Zhilin } 266d3bafe1dSMichael Zhilin return (err); 267d3bafe1dSMichael Zhilin } 268d3bafe1dSMichael Zhilin 269d3bafe1dSMichael Zhilin static int 270d3bafe1dSMichael Zhilin ksz8995ma_attach(device_t dev) 271d3bafe1dSMichael Zhilin { 272d3bafe1dSMichael Zhilin struct ksz8995ma_softc *sc; 273d3bafe1dSMichael Zhilin int err, reg; 274d3bafe1dSMichael Zhilin 275d3bafe1dSMichael Zhilin err = 0; 276d3bafe1dSMichael Zhilin sc = device_get_softc(dev); 277d3bafe1dSMichael Zhilin 278d3bafe1dSMichael Zhilin sc->sc_dev = dev; 279d3bafe1dSMichael Zhilin mtx_init(&sc->sc_mtx, "ksz8995ma", NULL, MTX_DEF); 280d3bafe1dSMichael Zhilin strlcpy(sc->info.es_name, device_get_desc(dev), 281d3bafe1dSMichael Zhilin sizeof(sc->info.es_name)); 282d3bafe1dSMichael Zhilin 283d3bafe1dSMichael Zhilin /* KSZ8995MA Defaults */ 284d3bafe1dSMichael Zhilin sc->numports = KSZ8995MA_MAX_PORT; 285d3bafe1dSMichael Zhilin sc->phymask = (1 << (KSZ8995MA_MAX_PORT + 1)) - 1; 286d3bafe1dSMichael Zhilin sc->cpuport = -1; 287d3bafe1dSMichael Zhilin sc->media = 100; 288d3bafe1dSMichael Zhilin 289d3bafe1dSMichael Zhilin (void) resource_int_value(device_get_name(dev), device_get_unit(dev), 290d3bafe1dSMichael Zhilin "cpuport", &sc->cpuport); 291d3bafe1dSMichael Zhilin 292d3bafe1dSMichael Zhilin sc->info.es_nvlangroups = 16; 293d3bafe1dSMichael Zhilin sc->info.es_vlan_caps = ETHERSWITCH_VLAN_PORT | ETHERSWITCH_VLAN_DOT1Q; 294d3bafe1dSMichael Zhilin 2952e6a8c1aSJustin Hibbits sc->ifp = malloc(sizeof(if_t) * sc->numports, M_KSZ8995MA, 296d3bafe1dSMichael Zhilin M_WAITOK | M_ZERO); 297d3bafe1dSMichael Zhilin sc->ifname = malloc(sizeof(char *) * sc->numports, M_KSZ8995MA, 298d3bafe1dSMichael Zhilin M_WAITOK | M_ZERO); 299d3bafe1dSMichael Zhilin sc->miibus = malloc(sizeof(device_t *) * sc->numports, M_KSZ8995MA, 300d3bafe1dSMichael Zhilin M_WAITOK | M_ZERO); 301d3bafe1dSMichael Zhilin sc->portphy = malloc(sizeof(int) * sc->numports, M_KSZ8995MA, 302d3bafe1dSMichael Zhilin M_WAITOK | M_ZERO); 303d3bafe1dSMichael Zhilin 304d3bafe1dSMichael Zhilin /* 305d3bafe1dSMichael Zhilin * Attach the PHYs and complete the bus enumeration. 306d3bafe1dSMichael Zhilin */ 307d3bafe1dSMichael Zhilin err = ksz8995ma_attach_phys(sc); 308d3bafe1dSMichael Zhilin if (err != 0) 309d3bafe1dSMichael Zhilin goto failed; 310d3bafe1dSMichael Zhilin 311723da5d9SJohn Baldwin bus_identify_children(dev); 312d3bafe1dSMichael Zhilin bus_enumerate_hinted_children(dev); 313*18250ec6SJohn Baldwin bus_attach_children(dev); 314d3bafe1dSMichael Zhilin 315d3bafe1dSMichael Zhilin callout_init(&sc->callout_tick, 0); 316d3bafe1dSMichael Zhilin 317d3bafe1dSMichael Zhilin ksz8995ma_tick(sc); 318d3bafe1dSMichael Zhilin 319d3bafe1dSMichael Zhilin /* start switch */ 320d3bafe1dSMichael Zhilin sc->vlan_mode = 0; 321d3bafe1dSMichael Zhilin reg = ksz8995ma_readreg(dev, KSZ8995MA_GC3); 322d3bafe1dSMichael Zhilin ksz8995ma_writereg(dev, KSZ8995MA_GC3, 323d3bafe1dSMichael Zhilin reg & ~KSZ8995MA_VLAN_ENABLE); 324d3bafe1dSMichael Zhilin ksz8995ma_portvlanreset(dev); 325d3bafe1dSMichael Zhilin ksz8995ma_writereg(dev, KSZ8995MA_CID1, KSZ8995MA_START); 326d3bafe1dSMichael Zhilin 327d3bafe1dSMichael Zhilin return (0); 328d3bafe1dSMichael Zhilin 329d3bafe1dSMichael Zhilin failed: 330d3bafe1dSMichael Zhilin free(sc->portphy, M_KSZ8995MA); 331d3bafe1dSMichael Zhilin free(sc->miibus, M_KSZ8995MA); 332d3bafe1dSMichael Zhilin free(sc->ifname, M_KSZ8995MA); 333d3bafe1dSMichael Zhilin free(sc->ifp, M_KSZ8995MA); 334d3bafe1dSMichael Zhilin 335d3bafe1dSMichael Zhilin return (err); 336d3bafe1dSMichael Zhilin } 337d3bafe1dSMichael Zhilin 338d3bafe1dSMichael Zhilin static int 339d3bafe1dSMichael Zhilin ksz8995ma_detach(device_t dev) 340d3bafe1dSMichael Zhilin { 341d3bafe1dSMichael Zhilin struct ksz8995ma_softc *sc; 342d3bafe1dSMichael Zhilin int i, port; 343d3bafe1dSMichael Zhilin 344d3bafe1dSMichael Zhilin sc = device_get_softc(dev); 345d3bafe1dSMichael Zhilin 346d3bafe1dSMichael Zhilin callout_drain(&sc->callout_tick); 347d3bafe1dSMichael Zhilin 348d3bafe1dSMichael Zhilin for (i = 0; i < KSZ8995MA_MAX_PORT; i++) { 349d3bafe1dSMichael Zhilin if (((1 << i) & sc->phymask) == 0) 350d3bafe1dSMichael Zhilin continue; 351d3bafe1dSMichael Zhilin port = ksz8995ma_portforphy(sc, i); 352d3bafe1dSMichael Zhilin if (sc->miibus[port] != NULL) 353d3bafe1dSMichael Zhilin device_delete_child(dev, (*sc->miibus[port])); 354d3bafe1dSMichael Zhilin if (sc->ifp[port] != NULL) 355d3bafe1dSMichael Zhilin if_free(sc->ifp[port]); 356d3bafe1dSMichael Zhilin free(sc->ifname[port], M_KSZ8995MA); 357d3bafe1dSMichael Zhilin free(sc->miibus[port], M_KSZ8995MA); 358d3bafe1dSMichael Zhilin } 359d3bafe1dSMichael Zhilin 360d3bafe1dSMichael Zhilin free(sc->portphy, M_KSZ8995MA); 361d3bafe1dSMichael Zhilin free(sc->miibus, M_KSZ8995MA); 362d3bafe1dSMichael Zhilin free(sc->ifname, M_KSZ8995MA); 363d3bafe1dSMichael Zhilin free(sc->ifp, M_KSZ8995MA); 364d3bafe1dSMichael Zhilin 365d3bafe1dSMichael Zhilin bus_generic_detach(dev); 366d3bafe1dSMichael Zhilin mtx_destroy(&sc->sc_mtx); 367d3bafe1dSMichael Zhilin 368d3bafe1dSMichael Zhilin return (0); 369d3bafe1dSMichael Zhilin } 370d3bafe1dSMichael Zhilin 371d3bafe1dSMichael Zhilin /* 372d3bafe1dSMichael Zhilin * Convert PHY number to port number. 373d3bafe1dSMichael Zhilin */ 374d3bafe1dSMichael Zhilin static inline int 375d3bafe1dSMichael Zhilin ksz8995ma_portforphy(struct ksz8995ma_softc *sc, int phy) 376d3bafe1dSMichael Zhilin { 377d3bafe1dSMichael Zhilin 378d3bafe1dSMichael Zhilin return (sc->ifpport[phy]); 379d3bafe1dSMichael Zhilin } 380d3bafe1dSMichael Zhilin 381d3bafe1dSMichael Zhilin static inline struct mii_data * 382d3bafe1dSMichael Zhilin ksz8995ma_miiforport(struct ksz8995ma_softc *sc, int port) 383d3bafe1dSMichael Zhilin { 384d3bafe1dSMichael Zhilin 385d3bafe1dSMichael Zhilin if (port < 0 || port > sc->numports) 386d3bafe1dSMichael Zhilin return (NULL); 387d3bafe1dSMichael Zhilin if (port == sc->cpuport) 388d3bafe1dSMichael Zhilin return (NULL); 389d3bafe1dSMichael Zhilin return (device_get_softc(*sc->miibus[port])); 390d3bafe1dSMichael Zhilin } 391d3bafe1dSMichael Zhilin 3922e6a8c1aSJustin Hibbits static inline if_t 393d3bafe1dSMichael Zhilin ksz8995ma_ifpforport(struct ksz8995ma_softc *sc, int port) 394d3bafe1dSMichael Zhilin { 395d3bafe1dSMichael Zhilin 396d3bafe1dSMichael Zhilin if (port < 0 || port > sc->numports) 397d3bafe1dSMichael Zhilin return (NULL); 398d3bafe1dSMichael Zhilin return (sc->ifp[port]); 399d3bafe1dSMichael Zhilin } 400d3bafe1dSMichael Zhilin 401d3bafe1dSMichael Zhilin /* 402d3bafe1dSMichael Zhilin * Poll the status for all PHYs. 403d3bafe1dSMichael Zhilin */ 404d3bafe1dSMichael Zhilin static void 405d3bafe1dSMichael Zhilin ksz8995ma_miipollstat(struct ksz8995ma_softc *sc) 406d3bafe1dSMichael Zhilin { 407d3bafe1dSMichael Zhilin int i, port; 408d3bafe1dSMichael Zhilin struct mii_data *mii; 409d3bafe1dSMichael Zhilin struct mii_softc *miisc; 410d3bafe1dSMichael Zhilin 411d3bafe1dSMichael Zhilin KSZ8995MA_LOCK_ASSERT(sc, MA_NOTOWNED); 412d3bafe1dSMichael Zhilin 413d3bafe1dSMichael Zhilin for (i = 0; i < KSZ8995MA_MAX_PORT; i++) { 414d3bafe1dSMichael Zhilin if (i == sc->cpuport) 415d3bafe1dSMichael Zhilin continue; 416d3bafe1dSMichael Zhilin if (((1 << i) & sc->phymask) == 0) 417d3bafe1dSMichael Zhilin continue; 418d3bafe1dSMichael Zhilin port = ksz8995ma_portforphy(sc, i); 419d3bafe1dSMichael Zhilin if ((*sc->miibus[port]) == NULL) 420d3bafe1dSMichael Zhilin continue; 421d3bafe1dSMichael Zhilin mii = device_get_softc(*sc->miibus[port]); 422d3bafe1dSMichael Zhilin LIST_FOREACH(miisc, &mii->mii_phys, mii_list) { 423d3bafe1dSMichael Zhilin if (IFM_INST(mii->mii_media.ifm_cur->ifm_media) != 424d3bafe1dSMichael Zhilin miisc->mii_inst) 425d3bafe1dSMichael Zhilin continue; 426d3bafe1dSMichael Zhilin ukphy_status(miisc); 427d3bafe1dSMichael Zhilin mii_phy_update(miisc, MII_POLLSTAT); 428d3bafe1dSMichael Zhilin } 429d3bafe1dSMichael Zhilin } 430d3bafe1dSMichael Zhilin } 431d3bafe1dSMichael Zhilin 432d3bafe1dSMichael Zhilin static void 433d3bafe1dSMichael Zhilin ksz8995ma_tick(void *arg) 434d3bafe1dSMichael Zhilin { 435d3bafe1dSMichael Zhilin struct ksz8995ma_softc *sc; 436d3bafe1dSMichael Zhilin 437d3bafe1dSMichael Zhilin sc = arg; 438d3bafe1dSMichael Zhilin 439d3bafe1dSMichael Zhilin ksz8995ma_miipollstat(sc); 440d3bafe1dSMichael Zhilin callout_reset(&sc->callout_tick, hz, ksz8995ma_tick, sc); 441d3bafe1dSMichael Zhilin } 442d3bafe1dSMichael Zhilin 443d3bafe1dSMichael Zhilin static void 444d3bafe1dSMichael Zhilin ksz8995ma_lock(device_t dev) 445d3bafe1dSMichael Zhilin { 446d3bafe1dSMichael Zhilin struct ksz8995ma_softc *sc; 447d3bafe1dSMichael Zhilin 448d3bafe1dSMichael Zhilin sc = device_get_softc(dev); 449d3bafe1dSMichael Zhilin 450d3bafe1dSMichael Zhilin KSZ8995MA_LOCK_ASSERT(sc, MA_NOTOWNED); 451d3bafe1dSMichael Zhilin KSZ8995MA_LOCK(sc); 452d3bafe1dSMichael Zhilin } 453d3bafe1dSMichael Zhilin 454d3bafe1dSMichael Zhilin static void 455d3bafe1dSMichael Zhilin ksz8995ma_unlock(device_t dev) 456d3bafe1dSMichael Zhilin { 457d3bafe1dSMichael Zhilin struct ksz8995ma_softc *sc; 458d3bafe1dSMichael Zhilin 459d3bafe1dSMichael Zhilin sc = device_get_softc(dev); 460d3bafe1dSMichael Zhilin 461d3bafe1dSMichael Zhilin KSZ8995MA_LOCK_ASSERT(sc, MA_OWNED); 462d3bafe1dSMichael Zhilin KSZ8995MA_UNLOCK(sc); 463d3bafe1dSMichael Zhilin } 464d3bafe1dSMichael Zhilin 465d3bafe1dSMichael Zhilin static etherswitch_info_t * 466d3bafe1dSMichael Zhilin ksz8995ma_getinfo(device_t dev) 467d3bafe1dSMichael Zhilin { 468d3bafe1dSMichael Zhilin struct ksz8995ma_softc *sc; 469d3bafe1dSMichael Zhilin 470d3bafe1dSMichael Zhilin sc = device_get_softc(dev); 471d3bafe1dSMichael Zhilin 472d3bafe1dSMichael Zhilin return (&sc->info); 473d3bafe1dSMichael Zhilin } 474d3bafe1dSMichael Zhilin 475d3bafe1dSMichael Zhilin static int 476d3bafe1dSMichael Zhilin ksz8995ma_getport(device_t dev, etherswitch_port_t *p) 477d3bafe1dSMichael Zhilin { 478d3bafe1dSMichael Zhilin struct ksz8995ma_softc *sc; 479d3bafe1dSMichael Zhilin struct mii_data *mii; 480d3bafe1dSMichael Zhilin struct ifmediareq *ifmr; 481d3bafe1dSMichael Zhilin int phy, err; 482d3bafe1dSMichael Zhilin int tag1, tag2, portreg; 483d3bafe1dSMichael Zhilin 484d3bafe1dSMichael Zhilin sc = device_get_softc(dev); 485d3bafe1dSMichael Zhilin ifmr = &p->es_ifmr; 486d3bafe1dSMichael Zhilin 487d3bafe1dSMichael Zhilin if (p->es_port < 0 || p->es_port >= sc->numports) 488d3bafe1dSMichael Zhilin return (ENXIO); 489d3bafe1dSMichael Zhilin 490d3bafe1dSMichael Zhilin if (sc->vlan_mode == ETHERSWITCH_VLAN_DOT1Q) { 491d3bafe1dSMichael Zhilin tag1 = ksz8995ma_readreg(dev, KSZ8995MA_PC3_BASE + 492d3bafe1dSMichael Zhilin KSZ8995MA_PORT_SIZE * p->es_port); 493d3bafe1dSMichael Zhilin tag2 = ksz8995ma_readreg(dev, KSZ8995MA_PC4_BASE + 494d3bafe1dSMichael Zhilin KSZ8995MA_PORT_SIZE * p->es_port); 495d3bafe1dSMichael Zhilin p->es_pvid = (tag1 & 0x0f) << 8 | tag2; 496d3bafe1dSMichael Zhilin 497d3bafe1dSMichael Zhilin portreg = ksz8995ma_readreg(dev, KSZ8995MA_PC0_BASE + 498d3bafe1dSMichael Zhilin KSZ8995MA_PORT_SIZE * p->es_port); 499d3bafe1dSMichael Zhilin if (portreg & KSZ8995MA_TAG_INS) 500d3bafe1dSMichael Zhilin p->es_flags |= ETHERSWITCH_PORT_ADDTAG; 501d3bafe1dSMichael Zhilin if (portreg & KSZ8995MA_TAG_RM) 502d3bafe1dSMichael Zhilin p->es_flags |= ETHERSWITCH_PORT_STRIPTAG; 503d3bafe1dSMichael Zhilin 504d3bafe1dSMichael Zhilin portreg = ksz8995ma_readreg(dev, KSZ8995MA_PC2_BASE + 505d3bafe1dSMichael Zhilin KSZ8995MA_PORT_SIZE * p->es_port); 506d3bafe1dSMichael Zhilin if (portreg & KSZ8995MA_DROP_NONPVID) 507d3bafe1dSMichael Zhilin p->es_flags |= ETHERSWITCH_PORT_DROPUNTAGGED; 508d3bafe1dSMichael Zhilin if (portreg & KSZ8995MA_INGR_FILT) 509d3bafe1dSMichael Zhilin p->es_flags |= ETHERSWITCH_PORT_INGRESS; 510d3bafe1dSMichael Zhilin } 511d3bafe1dSMichael Zhilin 512d3bafe1dSMichael Zhilin phy = sc->portphy[p->es_port]; 513d3bafe1dSMichael Zhilin mii = ksz8995ma_miiforport(sc, p->es_port); 514d3bafe1dSMichael Zhilin if (sc->cpuport != -1 && phy == sc->cpuport) { 515d3bafe1dSMichael Zhilin /* fill in fixed values for CPU port */ 516d3bafe1dSMichael Zhilin p->es_flags |= ETHERSWITCH_PORT_CPU; 517d3bafe1dSMichael Zhilin ifmr->ifm_count = 0; 518d3bafe1dSMichael Zhilin if (sc->media == 100) 519d3bafe1dSMichael Zhilin ifmr->ifm_current = ifmr->ifm_active = 520d3bafe1dSMichael Zhilin IFM_ETHER | IFM_100_TX | IFM_FDX; 521d3bafe1dSMichael Zhilin else 522d3bafe1dSMichael Zhilin ifmr->ifm_current = ifmr->ifm_active = 523d3bafe1dSMichael Zhilin IFM_ETHER | IFM_1000_T | IFM_FDX; 524d3bafe1dSMichael Zhilin ifmr->ifm_mask = 0; 525d3bafe1dSMichael Zhilin ifmr->ifm_status = IFM_ACTIVE | IFM_AVALID; 526d3bafe1dSMichael Zhilin } else if (mii != NULL) { 527d3bafe1dSMichael Zhilin err = ifmedia_ioctl(mii->mii_ifp, &p->es_ifr, 528d3bafe1dSMichael Zhilin &mii->mii_media, SIOCGIFMEDIA); 529d3bafe1dSMichael Zhilin if (err) 530d3bafe1dSMichael Zhilin return (err); 531d3bafe1dSMichael Zhilin } else { 532d3bafe1dSMichael Zhilin return (ENXIO); 533d3bafe1dSMichael Zhilin } 534d3bafe1dSMichael Zhilin 535d3bafe1dSMichael Zhilin return (0); 536d3bafe1dSMichael Zhilin } 537d3bafe1dSMichael Zhilin 538d3bafe1dSMichael Zhilin static int 539d3bafe1dSMichael Zhilin ksz8995ma_setport(device_t dev, etherswitch_port_t *p) 540d3bafe1dSMichael Zhilin { 541d3bafe1dSMichael Zhilin struct ksz8995ma_softc *sc; 542d3bafe1dSMichael Zhilin struct mii_data *mii; 543d3bafe1dSMichael Zhilin struct ifmedia *ifm; 5442e6a8c1aSJustin Hibbits if_t ifp; 545d3bafe1dSMichael Zhilin int phy, err; 546d3bafe1dSMichael Zhilin int portreg; 547d3bafe1dSMichael Zhilin 548d3bafe1dSMichael Zhilin sc = device_get_softc(dev); 549d3bafe1dSMichael Zhilin 550d3bafe1dSMichael Zhilin if (p->es_port < 0 || p->es_port >= sc->numports) 551d3bafe1dSMichael Zhilin return (ENXIO); 552d3bafe1dSMichael Zhilin 553d3bafe1dSMichael Zhilin if (sc->vlan_mode == ETHERSWITCH_VLAN_DOT1Q) { 554d3bafe1dSMichael Zhilin ksz8995ma_writereg(dev, KSZ8995MA_PC4_BASE + 555d3bafe1dSMichael Zhilin KSZ8995MA_PORT_SIZE * p->es_port, p->es_pvid & 0xff); 556d3bafe1dSMichael Zhilin portreg = ksz8995ma_readreg(dev, KSZ8995MA_PC3_BASE + 557d3bafe1dSMichael Zhilin KSZ8995MA_PORT_SIZE * p->es_port); 558d3bafe1dSMichael Zhilin ksz8995ma_writereg(dev, KSZ8995MA_PC3_BASE + 559d3bafe1dSMichael Zhilin KSZ8995MA_PORT_SIZE * p->es_port, 560d3bafe1dSMichael Zhilin (portreg & 0xf0) | ((p->es_pvid >> 8) & 0x0f)); 561d3bafe1dSMichael Zhilin 562d3bafe1dSMichael Zhilin portreg = ksz8995ma_readreg(dev, KSZ8995MA_PC0_BASE + 563d3bafe1dSMichael Zhilin KSZ8995MA_PORT_SIZE * p->es_port); 564d3bafe1dSMichael Zhilin if (p->es_flags & ETHERSWITCH_PORT_ADDTAG) 565d3bafe1dSMichael Zhilin portreg |= KSZ8995MA_TAG_INS; 566d3bafe1dSMichael Zhilin else 567d3bafe1dSMichael Zhilin portreg &= ~KSZ8995MA_TAG_INS; 568d3bafe1dSMichael Zhilin if (p->es_flags & ETHERSWITCH_PORT_STRIPTAG) 569d3bafe1dSMichael Zhilin portreg |= KSZ8995MA_TAG_RM; 570d3bafe1dSMichael Zhilin else 571d3bafe1dSMichael Zhilin portreg &= ~KSZ8995MA_TAG_RM; 572d3bafe1dSMichael Zhilin ksz8995ma_writereg(dev, KSZ8995MA_PC0_BASE + 573d3bafe1dSMichael Zhilin KSZ8995MA_PORT_SIZE * p->es_port, portreg); 574d3bafe1dSMichael Zhilin 575d3bafe1dSMichael Zhilin portreg = ksz8995ma_readreg(dev, KSZ8995MA_PC2_BASE + 576d3bafe1dSMichael Zhilin KSZ8995MA_PORT_SIZE * p->es_port); 577d3bafe1dSMichael Zhilin if (p->es_flags & ETHERSWITCH_PORT_DROPUNTAGGED) 578d3bafe1dSMichael Zhilin portreg |= KSZ8995MA_DROP_NONPVID; 579d3bafe1dSMichael Zhilin else 580d3bafe1dSMichael Zhilin portreg &= ~KSZ8995MA_DROP_NONPVID; 581d3bafe1dSMichael Zhilin if (p->es_flags & ETHERSWITCH_PORT_INGRESS) 582d3bafe1dSMichael Zhilin portreg |= KSZ8995MA_INGR_FILT; 583d3bafe1dSMichael Zhilin else 584d3bafe1dSMichael Zhilin portreg &= ~KSZ8995MA_INGR_FILT; 585d3bafe1dSMichael Zhilin ksz8995ma_writereg(dev, KSZ8995MA_PC2_BASE + 586d3bafe1dSMichael Zhilin KSZ8995MA_PORT_SIZE * p->es_port, portreg); 587d3bafe1dSMichael Zhilin } 588d3bafe1dSMichael Zhilin 589d3bafe1dSMichael Zhilin phy = sc->portphy[p->es_port]; 590d3bafe1dSMichael Zhilin mii = ksz8995ma_miiforport(sc, p->es_port); 591d3bafe1dSMichael Zhilin if (phy != sc->cpuport) { 592d3bafe1dSMichael Zhilin if (mii == NULL) 593d3bafe1dSMichael Zhilin return (ENXIO); 594d3bafe1dSMichael Zhilin ifp = ksz8995ma_ifpforport(sc, p->es_port); 595d3bafe1dSMichael Zhilin ifm = &mii->mii_media; 596d3bafe1dSMichael Zhilin err = ifmedia_ioctl(ifp, &p->es_ifr, ifm, SIOCSIFMEDIA); 597d3bafe1dSMichael Zhilin } 598d3bafe1dSMichael Zhilin return (0); 599d3bafe1dSMichael Zhilin } 600d3bafe1dSMichael Zhilin 601d3bafe1dSMichael Zhilin static int 602d3bafe1dSMichael Zhilin ksz8995ma_getvgroup(device_t dev, etherswitch_vlangroup_t *vg) 603d3bafe1dSMichael Zhilin { 604d3bafe1dSMichael Zhilin int data0, data1, data2; 605d3bafe1dSMichael Zhilin int vlantab; 606d3bafe1dSMichael Zhilin struct ksz8995ma_softc *sc; 607d3bafe1dSMichael Zhilin 608d3bafe1dSMichael Zhilin sc = device_get_softc(dev); 609d3bafe1dSMichael Zhilin 610d3bafe1dSMichael Zhilin if (sc->vlan_mode == ETHERSWITCH_VLAN_PORT) { 611d3bafe1dSMichael Zhilin if (vg->es_vlangroup < sc->numports) { 612d3bafe1dSMichael Zhilin vg->es_vid = ETHERSWITCH_VID_VALID; 613d3bafe1dSMichael Zhilin vg->es_vid |= vg->es_vlangroup; 614d3bafe1dSMichael Zhilin data0 = ksz8995ma_readreg(dev, KSZ8995MA_PC1_BASE + 615d3bafe1dSMichael Zhilin KSZ8995MA_PORT_SIZE * vg->es_vlangroup); 616d3bafe1dSMichael Zhilin vg->es_member_ports = data0 & 0x1f; 617d3bafe1dSMichael Zhilin vg->es_untagged_ports = vg->es_member_ports; 618d3bafe1dSMichael Zhilin vg->es_fid = 0; 619d3bafe1dSMichael Zhilin } else { 620d3bafe1dSMichael Zhilin vg->es_vid = 0; 621d3bafe1dSMichael Zhilin } 622d3bafe1dSMichael Zhilin } else if (sc->vlan_mode == ETHERSWITCH_VLAN_DOT1Q) { 623d3bafe1dSMichael Zhilin ksz8995ma_writereg(dev, KSZ8995MA_IAC0, 624d3bafe1dSMichael Zhilin KSZ8995MA_VLAN_TABLE_READ); 625d3bafe1dSMichael Zhilin ksz8995ma_writereg(dev, KSZ8995MA_IAC1, vg->es_vlangroup); 626d3bafe1dSMichael Zhilin data2 = ksz8995ma_readreg(dev, KSZ8995MA_IDR2); 627d3bafe1dSMichael Zhilin data1 = ksz8995ma_readreg(dev, KSZ8995MA_IDR1); 628d3bafe1dSMichael Zhilin data0 = ksz8995ma_readreg(dev, KSZ8995MA_IDR0); 629d3bafe1dSMichael Zhilin vlantab = data2 << 16 | data1 << 8 | data0; 630d3bafe1dSMichael Zhilin if (data2 & KSZ8995MA_VLAN_TABLE_VALID) { 631d3bafe1dSMichael Zhilin vg->es_vid = ETHERSWITCH_VID_VALID; 632d3bafe1dSMichael Zhilin vg->es_vid |= vlantab & 0xfff; 633d3bafe1dSMichael Zhilin vg->es_member_ports = (vlantab >> 16) & 0x1f; 634d3bafe1dSMichael Zhilin vg->es_untagged_ports = vg->es_member_ports; 635d3bafe1dSMichael Zhilin vg->es_fid = (vlantab >> 12) & 0x0f; 636d3bafe1dSMichael Zhilin } else { 637d3bafe1dSMichael Zhilin vg->es_fid = 0; 638d3bafe1dSMichael Zhilin } 639d3bafe1dSMichael Zhilin } 640d3bafe1dSMichael Zhilin 641d3bafe1dSMichael Zhilin return (0); 642d3bafe1dSMichael Zhilin } 643d3bafe1dSMichael Zhilin 644d3bafe1dSMichael Zhilin static int 645d3bafe1dSMichael Zhilin ksz8995ma_setvgroup(device_t dev, etherswitch_vlangroup_t *vg) 646d3bafe1dSMichael Zhilin { 647d3bafe1dSMichael Zhilin struct ksz8995ma_softc *sc; 648d3bafe1dSMichael Zhilin int data0; 649d3bafe1dSMichael Zhilin 650d3bafe1dSMichael Zhilin sc = device_get_softc(dev); 651d3bafe1dSMichael Zhilin 652d3bafe1dSMichael Zhilin if (sc->vlan_mode == ETHERSWITCH_VLAN_PORT) { 653d3bafe1dSMichael Zhilin data0 = ksz8995ma_readreg(dev, KSZ8995MA_PC1_BASE + 654d3bafe1dSMichael Zhilin KSZ8995MA_PORT_SIZE * vg->es_vlangroup); 655d3bafe1dSMichael Zhilin ksz8995ma_writereg(dev, KSZ8995MA_PC1_BASE + 656d3bafe1dSMichael Zhilin KSZ8995MA_PORT_SIZE * vg->es_vlangroup, 657d3bafe1dSMichael Zhilin (data0 & 0xe0) | (vg->es_member_ports & 0x1f)); 658d3bafe1dSMichael Zhilin } else if (sc->vlan_mode == ETHERSWITCH_VLAN_DOT1Q) { 659d3bafe1dSMichael Zhilin if (vg->es_member_ports != 0) { 660d3bafe1dSMichael Zhilin ksz8995ma_writereg(dev, KSZ8995MA_IDR2, 661d3bafe1dSMichael Zhilin KSZ8995MA_VLAN_TABLE_VALID | 662d3bafe1dSMichael Zhilin (vg->es_member_ports & 0x1f)); 663d3bafe1dSMichael Zhilin ksz8995ma_writereg(dev, KSZ8995MA_IDR1, 664d3bafe1dSMichael Zhilin vg->es_fid << 4 | vg->es_vid >> 8); 665d3bafe1dSMichael Zhilin ksz8995ma_writereg(dev, KSZ8995MA_IDR0, 666d3bafe1dSMichael Zhilin vg->es_vid & 0xff); 667d3bafe1dSMichael Zhilin } else { 668d3bafe1dSMichael Zhilin ksz8995ma_writereg(dev, KSZ8995MA_IDR2, 0); 669d3bafe1dSMichael Zhilin ksz8995ma_writereg(dev, KSZ8995MA_IDR1, 0); 670d3bafe1dSMichael Zhilin ksz8995ma_writereg(dev, KSZ8995MA_IDR0, 0); 671d3bafe1dSMichael Zhilin } 672d3bafe1dSMichael Zhilin ksz8995ma_writereg(dev, KSZ8995MA_IAC0, 673d3bafe1dSMichael Zhilin KSZ8995MA_VLAN_TABLE_WRITE); 674d3bafe1dSMichael Zhilin ksz8995ma_writereg(dev, KSZ8995MA_IAC1, vg->es_vlangroup); 675d3bafe1dSMichael Zhilin } 676d3bafe1dSMichael Zhilin 677d3bafe1dSMichael Zhilin return (0); 678d3bafe1dSMichael Zhilin } 679d3bafe1dSMichael Zhilin 680d3bafe1dSMichael Zhilin static int 681d3bafe1dSMichael Zhilin ksz8995ma_getconf(device_t dev, etherswitch_conf_t *conf) 682d3bafe1dSMichael Zhilin { 683d3bafe1dSMichael Zhilin struct ksz8995ma_softc *sc; 684d3bafe1dSMichael Zhilin 685d3bafe1dSMichael Zhilin sc = device_get_softc(dev); 686d3bafe1dSMichael Zhilin 687d3bafe1dSMichael Zhilin /* Return the VLAN mode. */ 688d3bafe1dSMichael Zhilin conf->cmd = ETHERSWITCH_CONF_VLAN_MODE; 689d3bafe1dSMichael Zhilin conf->vlan_mode = sc->vlan_mode; 690d3bafe1dSMichael Zhilin 691d3bafe1dSMichael Zhilin return (0); 692d3bafe1dSMichael Zhilin } 693d3bafe1dSMichael Zhilin 694d3bafe1dSMichael Zhilin static void 695d3bafe1dSMichael Zhilin ksz8995ma_portvlanreset(device_t dev) 696d3bafe1dSMichael Zhilin { 697d3bafe1dSMichael Zhilin int i, data; 698d3bafe1dSMichael Zhilin struct ksz8995ma_softc *sc; 699d3bafe1dSMichael Zhilin 700d3bafe1dSMichael Zhilin sc = device_get_softc(dev); 701d3bafe1dSMichael Zhilin 702d3bafe1dSMichael Zhilin for (i = 0; i < sc->numports; ++i) { 703d3bafe1dSMichael Zhilin data = ksz8995ma_readreg(dev, KSZ8995MA_PC1_BASE + 704d3bafe1dSMichael Zhilin KSZ8995MA_PORT_SIZE * i); 705d3bafe1dSMichael Zhilin ksz8995ma_writereg(dev, KSZ8995MA_PC1_BASE + 706d3bafe1dSMichael Zhilin KSZ8995MA_PORT_SIZE * i, (data & 0xe0) | 0x1f); 707d3bafe1dSMichael Zhilin } 708d3bafe1dSMichael Zhilin } 709d3bafe1dSMichael Zhilin 710d3bafe1dSMichael Zhilin static int 711d3bafe1dSMichael Zhilin ksz8995ma_setconf(device_t dev, etherswitch_conf_t *conf) 712d3bafe1dSMichael Zhilin { 713d3bafe1dSMichael Zhilin int reg; 714d3bafe1dSMichael Zhilin struct ksz8995ma_softc *sc; 715d3bafe1dSMichael Zhilin 716d3bafe1dSMichael Zhilin sc = device_get_softc(dev); 717d3bafe1dSMichael Zhilin 718d3bafe1dSMichael Zhilin if ((conf->cmd & ETHERSWITCH_CONF_VLAN_MODE) == 0) 719d3bafe1dSMichael Zhilin return (0); 720d3bafe1dSMichael Zhilin 721d3bafe1dSMichael Zhilin if (conf->vlan_mode == ETHERSWITCH_VLAN_PORT) { 722d3bafe1dSMichael Zhilin sc->vlan_mode = ETHERSWITCH_VLAN_PORT; 723d3bafe1dSMichael Zhilin reg = ksz8995ma_readreg(dev, KSZ8995MA_GC3); 724d3bafe1dSMichael Zhilin ksz8995ma_writereg(dev, KSZ8995MA_GC3, 725d3bafe1dSMichael Zhilin reg & ~KSZ8995MA_VLAN_ENABLE); 726d3bafe1dSMichael Zhilin ksz8995ma_portvlanreset(dev); 727d3bafe1dSMichael Zhilin } else if (conf->vlan_mode == ETHERSWITCH_VLAN_DOT1Q) { 728d3bafe1dSMichael Zhilin sc->vlan_mode = ETHERSWITCH_VLAN_DOT1Q; 729d3bafe1dSMichael Zhilin reg = ksz8995ma_readreg(dev, KSZ8995MA_GC3); 730d3bafe1dSMichael Zhilin ksz8995ma_writereg(dev, KSZ8995MA_GC3, 731d3bafe1dSMichael Zhilin reg | KSZ8995MA_VLAN_ENABLE); 732d3bafe1dSMichael Zhilin } else { 733d3bafe1dSMichael Zhilin sc->vlan_mode = 0; 734d3bafe1dSMichael Zhilin reg = ksz8995ma_readreg(dev, KSZ8995MA_GC3); 735d3bafe1dSMichael Zhilin ksz8995ma_writereg(dev, KSZ8995MA_GC3, 736d3bafe1dSMichael Zhilin reg & ~KSZ8995MA_VLAN_ENABLE); 737d3bafe1dSMichael Zhilin ksz8995ma_portvlanreset(dev); 738d3bafe1dSMichael Zhilin } 739d3bafe1dSMichael Zhilin return (0); 740d3bafe1dSMichael Zhilin } 741d3bafe1dSMichael Zhilin 742d3bafe1dSMichael Zhilin static void 743d3bafe1dSMichael Zhilin ksz8995ma_statchg(device_t dev) 744d3bafe1dSMichael Zhilin { 745d3bafe1dSMichael Zhilin 746d3bafe1dSMichael Zhilin DPRINTF(dev, "%s\n", __func__); 747d3bafe1dSMichael Zhilin } 748d3bafe1dSMichael Zhilin 749d3bafe1dSMichael Zhilin static int 7502e6a8c1aSJustin Hibbits ksz8995ma_ifmedia_upd(if_t ifp) 751d3bafe1dSMichael Zhilin { 752d3bafe1dSMichael Zhilin struct ksz8995ma_softc *sc; 753d3bafe1dSMichael Zhilin struct mii_data *mii; 754d3bafe1dSMichael Zhilin 7552e6a8c1aSJustin Hibbits sc = if_getsoftc(ifp); 756b29549c7SJustin Hibbits mii = ksz8995ma_miiforport(sc, if_getdunit(ifp)); 757d3bafe1dSMichael Zhilin 758d3bafe1dSMichael Zhilin DPRINTF(sc->sc_dev, "%s\n", __func__); 759d3bafe1dSMichael Zhilin if (mii == NULL) 760d3bafe1dSMichael Zhilin return (ENXIO); 761d3bafe1dSMichael Zhilin mii_mediachg(mii); 762d3bafe1dSMichael Zhilin return (0); 763d3bafe1dSMichael Zhilin } 764d3bafe1dSMichael Zhilin 765d3bafe1dSMichael Zhilin static void 7662e6a8c1aSJustin Hibbits ksz8995ma_ifmedia_sts(if_t ifp, struct ifmediareq *ifmr) 767d3bafe1dSMichael Zhilin { 768d3bafe1dSMichael Zhilin struct ksz8995ma_softc *sc; 769d3bafe1dSMichael Zhilin struct mii_data *mii; 770d3bafe1dSMichael Zhilin 7712e6a8c1aSJustin Hibbits sc = if_getsoftc(ifp); 772b29549c7SJustin Hibbits mii = ksz8995ma_miiforport(sc, if_getdunit(ifp)); 773d3bafe1dSMichael Zhilin 774d3bafe1dSMichael Zhilin DPRINTF(sc->sc_dev, "%s\n", __func__); 775d3bafe1dSMichael Zhilin 776d3bafe1dSMichael Zhilin if (mii == NULL) 777d3bafe1dSMichael Zhilin return; 778d3bafe1dSMichael Zhilin mii_pollstat(mii); 779d3bafe1dSMichael Zhilin ifmr->ifm_active = mii->mii_media_active; 780d3bafe1dSMichael Zhilin ifmr->ifm_status = mii->mii_media_status; 781d3bafe1dSMichael Zhilin } 782d3bafe1dSMichael Zhilin 783d3bafe1dSMichael Zhilin static int 784d3bafe1dSMichael Zhilin ksz8995ma_readphy(device_t dev, int phy, int reg) 785d3bafe1dSMichael Zhilin { 786d3bafe1dSMichael Zhilin int portreg; 787d3bafe1dSMichael Zhilin 788d3bafe1dSMichael Zhilin /* 789d3bafe1dSMichael Zhilin * This is no mdio/mdc connection code. 790d3bafe1dSMichael Zhilin * simulate MIIM Registers via the SPI interface 791d3bafe1dSMichael Zhilin */ 792d3bafe1dSMichael Zhilin if (reg == MII_BMSR) { 793d3bafe1dSMichael Zhilin portreg = ksz8995ma_readreg(dev, KSZ8995MA_PS0_BASE + 794d3bafe1dSMichael Zhilin KSZ8995MA_PORT_SIZE * phy); 795d3bafe1dSMichael Zhilin return (KSZ8995MA_MII_STAT | 796d3bafe1dSMichael Zhilin (portreg & 0x20 ? BMSR_LINK : 0x00) | 797d3bafe1dSMichael Zhilin (portreg & 0x40 ? BMSR_ACOMP : 0x00)); 798d3bafe1dSMichael Zhilin } else if (reg == MII_PHYIDR1) { 799d3bafe1dSMichael Zhilin return (KSZ8995MA_MII_PHYID_H); 800d3bafe1dSMichael Zhilin } else if (reg == MII_PHYIDR2) { 801d3bafe1dSMichael Zhilin return (KSZ8995MA_MII_PHYID_L); 802d3bafe1dSMichael Zhilin } else if (reg == MII_ANAR) { 803d3bafe1dSMichael Zhilin portreg = ksz8995ma_readreg(dev, KSZ8995MA_PC12_BASE + 804d3bafe1dSMichael Zhilin KSZ8995MA_PORT_SIZE * phy); 805d3bafe1dSMichael Zhilin return (KSZ8995MA_MII_AA | (portreg & 0x0f) << 5); 806d3bafe1dSMichael Zhilin } else if (reg == MII_ANLPAR) { 807d3bafe1dSMichael Zhilin portreg = ksz8995ma_readreg(dev, KSZ8995MA_PS0_BASE + 808d3bafe1dSMichael Zhilin KSZ8995MA_PORT_SIZE * phy); 809d3bafe1dSMichael Zhilin return (((portreg & 0x0f) << 5) | 0x01); 810d3bafe1dSMichael Zhilin } 811d3bafe1dSMichael Zhilin 812d3bafe1dSMichael Zhilin return (0); 813d3bafe1dSMichael Zhilin } 814d3bafe1dSMichael Zhilin 815d3bafe1dSMichael Zhilin static int 816d3bafe1dSMichael Zhilin ksz8995ma_writephy(device_t dev, int phy, int reg, int data) 817d3bafe1dSMichael Zhilin { 818d3bafe1dSMichael Zhilin int portreg; 819d3bafe1dSMichael Zhilin 820d3bafe1dSMichael Zhilin /* 821d3bafe1dSMichael Zhilin * This is no mdio/mdc connection code. 822d3bafe1dSMichael Zhilin * simulate MIIM Registers via the SPI interface 823d3bafe1dSMichael Zhilin */ 824d3bafe1dSMichael Zhilin if (reg == MII_BMCR) { 825d3bafe1dSMichael Zhilin portreg = ksz8995ma_readreg(dev, KSZ8995MA_PC13_BASE + 826d3bafe1dSMichael Zhilin KSZ8995MA_PORT_SIZE * phy); 827d3bafe1dSMichael Zhilin if (data & BMCR_PDOWN) 828d3bafe1dSMichael Zhilin portreg |= KSZ8995MA_PDOWN; 829d3bafe1dSMichael Zhilin else 830d3bafe1dSMichael Zhilin portreg &= ~KSZ8995MA_PDOWN; 831d3bafe1dSMichael Zhilin if (data & BMCR_STARTNEG) 832d3bafe1dSMichael Zhilin portreg |= KSZ8995MA_STARTNEG; 833d3bafe1dSMichael Zhilin else 834d3bafe1dSMichael Zhilin portreg &= ~KSZ8995MA_STARTNEG; 835d3bafe1dSMichael Zhilin ksz8995ma_writereg(dev, KSZ8995MA_PC13_BASE + 836d3bafe1dSMichael Zhilin KSZ8995MA_PORT_SIZE * phy, portreg); 837d3bafe1dSMichael Zhilin } else if (reg == MII_ANAR) { 838d3bafe1dSMichael Zhilin portreg = ksz8995ma_readreg(dev, KSZ8995MA_PC12_BASE + 839d3bafe1dSMichael Zhilin KSZ8995MA_PORT_SIZE * phy); 840d3bafe1dSMichael Zhilin portreg &= 0xf; 841d3bafe1dSMichael Zhilin portreg |= ((data >> 5) & 0x0f); 842d3bafe1dSMichael Zhilin ksz8995ma_writereg(dev, KSZ8995MA_PC12_BASE + 843d3bafe1dSMichael Zhilin KSZ8995MA_PORT_SIZE * phy, portreg); 844d3bafe1dSMichael Zhilin } 845d3bafe1dSMichael Zhilin return (0); 846d3bafe1dSMichael Zhilin } 847d3bafe1dSMichael Zhilin 848d3bafe1dSMichael Zhilin static int 849d3bafe1dSMichael Zhilin ksz8995ma_readreg(device_t dev, int addr) 850d3bafe1dSMichael Zhilin { 851d3bafe1dSMichael Zhilin uint8_t txBuf[8], rxBuf[8]; 852d3bafe1dSMichael Zhilin struct spi_command cmd; 853d3bafe1dSMichael Zhilin int err; 854d3bafe1dSMichael Zhilin 855d3bafe1dSMichael Zhilin memset(&cmd, 0, sizeof(cmd)); 856d3bafe1dSMichael Zhilin memset(txBuf, 0, sizeof(txBuf)); 857d3bafe1dSMichael Zhilin memset(rxBuf, 0, sizeof(rxBuf)); 858d3bafe1dSMichael Zhilin 859d3bafe1dSMichael Zhilin /* read spi */ 860d3bafe1dSMichael Zhilin txBuf[0] = KSZ8995MA_SPI_READ; 861d3bafe1dSMichael Zhilin txBuf[1] = addr; 862d3bafe1dSMichael Zhilin cmd.tx_cmd = &txBuf; 863d3bafe1dSMichael Zhilin cmd.rx_cmd = &rxBuf; 864d3bafe1dSMichael Zhilin cmd.tx_cmd_sz = 3; 865d3bafe1dSMichael Zhilin cmd.rx_cmd_sz = 3; 866d3bafe1dSMichael Zhilin err = SPIBUS_TRANSFER(device_get_parent(dev), dev, &cmd); 867d3bafe1dSMichael Zhilin if (err) 868d3bafe1dSMichael Zhilin return(0); 869d3bafe1dSMichael Zhilin 870d3bafe1dSMichael Zhilin return (rxBuf[2]); 871d3bafe1dSMichael Zhilin } 872d3bafe1dSMichael Zhilin 873d3bafe1dSMichael Zhilin static int 874d3bafe1dSMichael Zhilin ksz8995ma_writereg(device_t dev, int addr, int value) 875d3bafe1dSMichael Zhilin { 876d3bafe1dSMichael Zhilin uint8_t txBuf[8], rxBuf[8]; 877d3bafe1dSMichael Zhilin struct spi_command cmd; 878d3bafe1dSMichael Zhilin int err; 879d3bafe1dSMichael Zhilin 880d3bafe1dSMichael Zhilin memset(&cmd, 0, sizeof(cmd)); 881d3bafe1dSMichael Zhilin memset(txBuf, 0, sizeof(txBuf)); 882d3bafe1dSMichael Zhilin memset(rxBuf, 0, sizeof(rxBuf)); 883d3bafe1dSMichael Zhilin 884d3bafe1dSMichael Zhilin /* write spi */ 885d3bafe1dSMichael Zhilin txBuf[0] = KSZ8995MA_SPI_WRITE; 886d3bafe1dSMichael Zhilin txBuf[1] = addr; 887d3bafe1dSMichael Zhilin txBuf[2] = value; 888d3bafe1dSMichael Zhilin cmd.tx_cmd = &txBuf; 889d3bafe1dSMichael Zhilin cmd.rx_cmd = &rxBuf; 890d3bafe1dSMichael Zhilin cmd.tx_cmd_sz = 3; 891d3bafe1dSMichael Zhilin cmd.rx_cmd_sz = 3; 892d3bafe1dSMichael Zhilin err = SPIBUS_TRANSFER(device_get_parent(dev), dev, &cmd); 893d3bafe1dSMichael Zhilin if (err) 894d3bafe1dSMichael Zhilin return(0); 895d3bafe1dSMichael Zhilin 896d3bafe1dSMichael Zhilin return (0); 897d3bafe1dSMichael Zhilin } 898d3bafe1dSMichael Zhilin 899d3bafe1dSMichael Zhilin static device_method_t ksz8995ma_methods[] = { 900d3bafe1dSMichael Zhilin /* Device interface */ 901d3bafe1dSMichael Zhilin DEVMETHOD(device_probe, ksz8995ma_probe), 902d3bafe1dSMichael Zhilin DEVMETHOD(device_attach, ksz8995ma_attach), 903d3bafe1dSMichael Zhilin DEVMETHOD(device_detach, ksz8995ma_detach), 904d3bafe1dSMichael Zhilin 905d3bafe1dSMichael Zhilin /* bus interface */ 906d3bafe1dSMichael Zhilin DEVMETHOD(bus_add_child, device_add_child_ordered), 907d3bafe1dSMichael Zhilin 908d3bafe1dSMichael Zhilin /* MII interface */ 909d3bafe1dSMichael Zhilin DEVMETHOD(miibus_readreg, ksz8995ma_readphy), 910d3bafe1dSMichael Zhilin DEVMETHOD(miibus_writereg, ksz8995ma_writephy), 911d3bafe1dSMichael Zhilin DEVMETHOD(miibus_statchg, ksz8995ma_statchg), 912d3bafe1dSMichael Zhilin 913d3bafe1dSMichael Zhilin /* etherswitch interface */ 914d3bafe1dSMichael Zhilin DEVMETHOD(etherswitch_lock, ksz8995ma_lock), 915d3bafe1dSMichael Zhilin DEVMETHOD(etherswitch_unlock, ksz8995ma_unlock), 916d3bafe1dSMichael Zhilin DEVMETHOD(etherswitch_getinfo, ksz8995ma_getinfo), 917d3bafe1dSMichael Zhilin DEVMETHOD(etherswitch_readreg, ksz8995ma_readreg), 918d3bafe1dSMichael Zhilin DEVMETHOD(etherswitch_writereg, ksz8995ma_writereg), 919d3bafe1dSMichael Zhilin DEVMETHOD(etherswitch_readphyreg, ksz8995ma_readphy), 920d3bafe1dSMichael Zhilin DEVMETHOD(etherswitch_writephyreg, ksz8995ma_writephy), 921d3bafe1dSMichael Zhilin DEVMETHOD(etherswitch_getport, ksz8995ma_getport), 922d3bafe1dSMichael Zhilin DEVMETHOD(etherswitch_setport, ksz8995ma_setport), 923d3bafe1dSMichael Zhilin DEVMETHOD(etherswitch_getvgroup, ksz8995ma_getvgroup), 924d3bafe1dSMichael Zhilin DEVMETHOD(etherswitch_setvgroup, ksz8995ma_setvgroup), 925d3bafe1dSMichael Zhilin DEVMETHOD(etherswitch_setconf, ksz8995ma_setconf), 926d3bafe1dSMichael Zhilin DEVMETHOD(etherswitch_getconf, ksz8995ma_getconf), 927d3bafe1dSMichael Zhilin 928d3bafe1dSMichael Zhilin DEVMETHOD_END 929d3bafe1dSMichael Zhilin }; 930d3bafe1dSMichael Zhilin 931d3bafe1dSMichael Zhilin DEFINE_CLASS_0(ksz8995ma, ksz8995ma_driver, ksz8995ma_methods, 932d3bafe1dSMichael Zhilin sizeof(struct ksz8995ma_softc)); 933d3bafe1dSMichael Zhilin 93442726c2fSJohn Baldwin DRIVER_MODULE(ksz8995ma, spibus, ksz8995ma_driver, 0, 0); 9353e38757dSJohn Baldwin DRIVER_MODULE(miibus, ksz8995ma, miibus_driver, 0, 0); 936829a13faSJohn Baldwin DRIVER_MODULE(etherswitch, ksz8995ma, etherswitch_driver, 0, 0); 937d3bafe1dSMichael Zhilin MODULE_VERSION(ksz8995ma, 1); 938d3bafe1dSMichael Zhilin MODULE_DEPEND(ksz8995ma, spibus, 1, 1, 1); /* XXX which versions? */ 939d3bafe1dSMichael Zhilin MODULE_DEPEND(ksz8995ma, miibus, 1, 1, 1); /* XXX which versions? */ 940d3bafe1dSMichael Zhilin MODULE_DEPEND(ksz8995ma, etherswitch, 1, 1, 1); /* XXX which versions? */ 941