1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2021 Alstom Group. 5 * Copyright (c) 2021 Semihalf. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #ifndef _FELIX_REG_H_ 30 #define _FELIX_REG_H_ 31 32 #define BIT(x) (1UL << (x)) 33 34 #define FELIX_MDIO_BASE 0x1C00 35 36 #define FELIX_DEVCPU_GCB_RST 0x70004 37 #define FELIX_DEVCPU_GCB_RST_EN BIT(0) 38 39 #define FELIX_ANA_VT 0x287F34 40 #define FELIX_ANA_VT_PORTMASK_SHIFT 2 41 #define FELIX_ANA_VT_PORTMASK_MASK 0x7F 42 #define FELIX_ANA_VT_STS (BIT(0) | BIT(1)) 43 #define FELIX_ANA_VT_RESET (BIT(0) | BIT(1)) 44 #define FELIX_ANA_VT_WRITE BIT(1) 45 #define FELIX_ANA_VT_READ BIT(0) 46 #define FELIX_ANA_VT_IDLE 0 47 #define FELIX_ANA_VTIDX 0x287F38 48 49 #define FELIX_ANA_PORT_BASE 0x287800 50 #define FELIX_ANA_PORT_OFFSET 0x100 51 #define FELIX_ANA_PORT_VLAN_CFG 0x0 52 #define FELIX_ANA_PORT_VLAN_CFG_VID_MASK 0xFFF 53 #define FELIX_ANA_PORT_VLAN_CFG_POP BIT(18) 54 #define FELIX_ANA_PORT_VLAN_CFG_VID_AWARE BIT(20) 55 #define FELIX_ANA_PORT_DROP_CFG 0x4 56 #define FELIX_ANA_PORT_DROP_CFG_MULTI BIT(0) 57 #define FELIX_ANA_PORT_DROP_CFG_NULL BIT(1) /* SRC, or DST MAC == 0 */ 58 #define FELIX_ANA_PORT_DROP_CFG_CTAGGED_PRIO BIT(2) /* 0x8100, VID == 0 */ 59 #define FELIX_ANA_PORT_DROP_CFG_STAGGED_PRIO BIT(3) /* 0x88A8, VID == 0 */ 60 #define FELIX_ANA_PORT_DROP_CFG_CTAGGED BIT(4) /* 0x8100 */ 61 #define FELIX_ANA_PORT_DROP_CFG_STAGGED BIT(5) /* 0x88A8 */ 62 #define FELIX_ANA_PORT_DROP_CFG_UNTAGGED BIT(6) 63 #define FELIX_ANA_PORT_DROP_CFG_TAGGED \ 64 (FELIX_ANA_PORT_DROP_CFG_CTAGGED_PRIO | \ 65 FELIX_ANA_PORT_DROP_CFG_STAGGED_PRIO | \ 66 FELIX_ANA_PORT_DROP_CFG_CTAGGED | \ 67 FELIX_ANA_PORT_DROP_CFG_STAGGED) 68 69 #define FELIX_DEVGMII_BASE 0x100000 70 #define FELIX_DEVGMII_PORT_OFFSET 0x010000 71 72 #define FELIX_DEVGMII_CLK_CFG 0x0 73 #define FELIX_DEVGMII_CLK_CFG_SPEED_1000 1 74 #define FELIX_DEVGMII_CLK_CFG_SPEED_100 2 75 #define FELIX_DEVGMII_CLK_CFG_SPEED_10 3 76 77 #define FELIX_DEVGMII_MAC_CFG 0x1c 78 #define FELIX_DEVGMII_MAC_CFG_TX_ENA BIT(0) 79 #define FELIX_DEVGMII_MAC_CFG_RX_ENA BIT(4) 80 81 #define FELIX_DEVGMII_VLAN_CFG 0x28 82 #define FELIX_DEVGMII_VLAN_CFG_ENA BIT(0) /* Accept 0x8100 only. */ 83 #define FELIX_DEVGMII_VLAN_CFG_DOUBLE_ENA BIT(1) /* Inner tag can only be 0x8100. */ 84 #define FELIX_DEVGMII_VLAN_CFG_LEN_ENA BIT(2) /* Enable VLANMTU. */ 85 86 #define FELIX_REW_PORT_BASE 0x030000 87 #define FELIX_REW_PORT_OFFSET 0x80 88 #define FELIX_REW_PORT_TAG_CFG 0x4 89 #define FELIX_REW_PORT_TAG_CFG_MASK (BIT(7) | BIT(8)) 90 #define FELIX_REW_PORT_TAG_CFG_DIS (0 << 7) /* Port tagging disabled */ 91 #define FELIX_REW_PORT_TAG_CFG_ALL (2 << 7) /* Tag frames if pvid != 0 */ 92 93 #define FELIX_SYS_RAM_CTRL 0x10F24 94 #define FELIX_SYS_RAM_CTRL_INIT BIT(1) 95 96 #define FELIX_SYS_CFG 0x10E00 97 #define FELIX_SYS_CFG_CORE_EN BIT(0) 98 99 #define FELIX_QSYS_PORT_MODE(port) (0x20F480 + 4*(port)) 100 #define FELIX_QSYS_PORT_MODE_PORT_ENA BIT(14) 101 102 #endif 103