1 /*- 2 * Copyright (c) 2015 Semihalf 3 * Copyright (c) 2015 Stormshield 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 * 27 */ 28 29 #ifndef _E6000SWREG_H_ 30 #define _E6000SWREG_H_ 31 32 struct atu_opt { 33 uint16_t mac_01; 34 uint16_t mac_23; 35 uint16_t mac_45; 36 uint16_t fid; 37 }; 38 39 /* 40 * Definitions for the Marvell 88E6000 series Ethernet Switch. 41 */ 42 43 /* Switch IDs. */ 44 #define MV88E6141 0x3400 45 #define MV88E6341 0x3410 46 #define MV88E6352 0x3520 47 #define MV88E6172 0x1720 48 #define MV88E6176 0x1760 49 #define MV88E6190 0x1900 50 51 #define MVSWITCH(_sc, id) ((_sc)->swid == (id)) 52 #define MVSWITCH_MULTICHIP(_sc) ((_sc)->sw_addr != 0) 53 54 /* 55 * Switch Registers 56 */ 57 #define REG_GLOBAL 0x1b 58 #define REG_GLOBAL2 0x1c 59 #define REG_PORT(_sc, p) ((MVSWITCH((_sc), MV88E6190) ? 0 : 0x10) + (p)) 60 61 #define REG_NUM_MAX 31 62 63 /* 64 * Per-Port Switch Registers 65 */ 66 #define PORT_STATUS 0x0 67 #define PORT_STATUS_SPEED_MASK 0x300 68 #define PORT_STATUS_SPEED_10 0 69 #define PORT_STATUS_SPEED_100 1 70 #define PORT_STATUS_SPEED_1000 2 71 #define PORT_STATUS_DUPLEX_MASK (1 << 10) 72 #define PORT_STATUS_LINK_MASK (1 << 11) 73 #define PORT_STATUS_PHY_DETECT_MASK (1 << 12) 74 75 #define PSC_CONTROL 0x1 76 #define PSC_CONTROL_FORCED_SPD (1 << 13) 77 #define PSC_CONTROL_ALT_SPD (1 << 12) 78 #define PSC_CONTROL_EEE_ON (1 << 9) 79 #define PSC_CONTROL_FORCED_EEE (1 << 8) 80 #define PSC_CONTROL_FC_ON (1 << 7) 81 #define PSC_CONTROL_FORCED_FC (1 << 6) 82 #define PSC_CONTROL_LINK_UP (1 << 5) 83 #define PSC_CONTROL_FORCED_LINK (1 << 4) 84 #define PSC_CONTROL_FULLDPX (1 << 3) 85 #define PSC_CONTROL_FORCED_DPX (1 << 2) 86 #define PSC_CONTROL_SPD10G 0x3 87 #define PSC_CONTROL_SPD2500 PSC_CONTROL_SPD10G 88 #define PSC_CONTROL_SPD1000 0x2 89 #define SWITCH_ID 0x3 90 #define PORT_CONTROL 0x4 91 #define PORT_CONTROL1 0x5 92 #define PORT_CONTROL1_LAG_PORT (1 << 14) 93 #define PORT_CONTROL1_LAG_ID_MASK 0xf 94 #define PORT_CONTROL1_LAG_ID_SHIFT 8 95 #define PORT_CONTROL1_FID_MASK 0xf 96 #define PORT_VLAN_MAP 0x6 97 #define PORT_VID 0x7 98 #define PORT_CONTROL2 0x8 99 #define PORT_ASSOCIATION_VECTOR 0xb 100 #define PORT_ATU_CTRL 0xc 101 #define RX_COUNTER 0x12 102 #define TX_COUNTER 0x13 103 104 #define PORT_MASK(_sc) 0x7f 105 #define PORT_VID_DEF_VID 0 106 #define PORT_VID_DEF_VID_MASK 0xfff 107 #define PORT_VID_PRIORITY_MASK 0xc00 108 109 #define PORT_CONTROL_DISABLED 0 110 #define PORT_CONTROL_BLOCKING 1 111 #define PORT_CONTROL_LEARNING 2 112 #define PORT_CONTROL_FORWARDING 3 113 #define PORT_CONTROL_ENABLE 3 114 #define PORT_CONTROL_FRAME 0x0300 115 #define PORT_CONTROL_EGRESS 0x3000 116 #define PORT_CONTROL2_DOT1Q 0x0c00 117 #define PORT_CONTROL2_DISC_TAGGED (1 << 9) 118 #define PORT_CONTROL2_DISC_UNTAGGED (1 << 8) 119 120 /* PORT_VLAN fields */ 121 #define PORT_VLAN_MAP_FID 12 122 #define PORT_VLAN_MAP_FID_MASK 0xf000 123 124 /* 125 * Switch Global Register 1 accessed via REG_GLOBAL_ADDR 126 */ 127 #define SWITCH_GLOBAL_STATUS 0 128 #define SWITCH_GLOBAL_STATUS_IR (1 << 11) 129 #define SWITCH_GLOBAL_CONTROL 4 130 #define SWITCH_GLOBAL_CONTROL2 28 131 132 #define MONITOR_CONTROL 26 133 134 /* VTU operation */ 135 #define VTU_FID 2 136 #define VTU_OPERATION 5 137 #define VTU_VID 6 138 #define VTU_DATA 7 139 #define VTU_DATA2 8 140 141 #define VTU_FID_MASK(_sc) (MVSWITCH((_sc), MV88E6190) ? 0xfff : 0xff) 142 #define VTU_FID_POLICY (1 << 12) 143 #define VTU_PORT_UNMODIFIED 0 144 #define VTU_PORT_UNTAGGED 1 145 #define VTU_PORT_TAGGED 2 146 #define VTU_PORT_DISCARD 3 147 #define VTU_PPREG(_sc) (MVSWITCH((_sc), MV88E6190) ? 8 : 4) 148 #define VTU_PORT(_sc, p) (((p) % VTU_PPREG(_sc)) * (16 / VTU_PPREG(_sc))) 149 #define VTU_PORT_MASK 3 150 #define VTU_BUSY (1 << 15) 151 #define VTU_VID_VALID (1 << 12) 152 #define VTU_VID_MASK 0xfff 153 154 /* VTU opcodes */ 155 #define VTU_OP_MASK (7 << 12) 156 #define VTU_NOP (0 << 12) 157 #define VTU_FLUSH (1 << 12) 158 #define VTU_LOAD (3 << 12) 159 #define VTU_PURGE (3 << 12) 160 #define VTU_GET_NEXT (4 << 12) 161 #define STU_LOAD (5 << 12) 162 #define STU_PURGE (5 << 12) 163 #define STU_GET_NEXT (6 << 12) 164 #define VTU_GET_VIOLATION_DATA (7 << 12) 165 #define VTU_CLEAR_VIOLATION_DATA (7 << 12) 166 167 /* ATU operation */ 168 #define ATU_FID 1 169 #define ATU_CONTROL 10 170 #define ATU_OPERATION 11 171 #define ATU_DATA 12 172 #define ATU_MAC_ADDR01 13 173 #define ATU_MAC_ADDR23 14 174 #define ATU_MAC_ADDR45 15 175 176 #define ATU_DATA_LAG (1 << 15) 177 #define ATU_PORT_MASK(_sc) (MVSWITCH((_sc), MV88E6190) ? 0xfff0 : 0xff0) 178 #define ATU_PORT_SHIFT 4 179 #define ATU_LAG_MASK 0xf0 180 #define ATU_LAG_SHIFT 4 181 #define ATU_STATE_MASK 0xf 182 #define ATU_UNIT_BUSY (1 << 15) 183 #define ENTRY_STATE 0xf 184 185 /* ATU_CONTROL fields */ 186 #define ATU_CONTROL_AGETIME 4 187 #define ATU_CONTROL_AGETIME_MASK 0xff0 188 #define ATU_CONTROL_LEARN2ALL 3 189 190 /* ATU opcode */ 191 #define ATU_OP_MASK (7 << 12) 192 #define NO_OPERATION (0 << 12) 193 #define FLUSH_ALL (1 << 12) 194 #define FLUSH_NON_STATIC (2 << 12) 195 #define LOAD_FROM_FIB (3 << 12) 196 #define PURGE_FROM_FIB (3 << 12) 197 #define GET_NEXT_IN_FIB (4 << 12) 198 #define FLUSH_ALL_IN_FIB (5 << 12) 199 #define FLUSH_NON_STATIC_IN_FIB (6 << 12) 200 #define GET_VIOLATION_DATA (7 << 12) 201 #define CLEAR_VIOLATION_DATA (7 << 12) 202 203 /* ATU Stats */ 204 #define COUNT_ALL (0 << 0) 205 206 /* 207 * Switch Global Register 2 accessed via REG_GLOBAL2_ADDR 208 */ 209 #define MGMT_EN_2x 2 210 #define MGMT_EN_0x 3 211 #define SWITCH_MGMT 5 212 #define LAG_MASK 7 213 #define LAG_MAPPING 8 214 #define ATU_STATS 14 215 216 #define MGMT_EN_ALL 0xffff 217 #define LAG_UPDATE (1 << 15) 218 #define LAG_MASKNUM_SHIFT 12 219 #define LAGID_SHIFT 11 220 221 /* SWITCH_MGMT fields */ 222 223 #define SWITCH_MGMT_PRI 0 224 #define SWITCH_MGMT_PRI_MASK 7 225 #define SWITCH_MGMT_RSVD2CPU 3 226 #define SWITCH_MGMT_FC_PRI 4 227 #define SWITCH_MGMT_FC_PRI_MASK (7 << 4) 228 #define SWITCH_MGMT_FORCEFLOW 7 229 230 /* ATU_STATS fields */ 231 232 #define ATU_STATS_BIN 14 233 #define ATU_STATS_FLAG 12 234 235 /* Offset of SMI registers in multi-chip setup. */ 236 #define SMI_CMD 0 237 #define SMI_DATA 1 238 239 /* 240 * 'Switch Global Registers 2' (REG_GLOBAL2). 241 */ 242 243 /* EEPROM registers */ 244 #define EEPROM_CMD 0x14 245 #define EEPROM_BUSY (1 << 15) 246 #define EEPROM_READ_CMD (4 << 12) 247 #define EEPROM_WRITE_CMD (3 << 12) 248 #define EEPROM_WRITE_EN (1 << 10) 249 #define EEPROM_DATA_MASK 0xff 250 #define EEPROM_ADDR 0x15 251 252 /* PHY registers */ 253 #define SMI_PHY_CMD_REG 0x18 254 #define SMI_CMD_BUSY (1 << 15) 255 #define SMI_CMD_MODE_C22 (1 << 12) 256 #define SMI_CMD_C22_WRITE (1 << 10) 257 #define SMI_CMD_C22_READ (2 << 10) 258 #define SMI_CMD_OP_C22_WRITE \ 259 (SMI_CMD_C22_WRITE | SMI_CMD_BUSY | SMI_CMD_MODE_C22) 260 #define SMI_CMD_OP_C22_READ \ 261 (SMI_CMD_C22_READ | SMI_CMD_BUSY | SMI_CMD_MODE_C22) 262 #define SMI_CMD_C45 (0 << 12) 263 #define SMI_CMD_C45_ADDR (0 << 10) 264 #define SMI_CMD_C45_WRITE (1 << 10) 265 #define SMI_CMD_C45_READ (3 << 10) 266 #define SMI_CMD_OP_C45_ADDR \ 267 (SMI_CMD_C45_ADDR | SMI_CMD_BUSY | SMI_CMD_C45) 268 #define SMI_CMD_OP_C45_WRITE \ 269 (SMI_CMD_C45_WRITE | SMI_CMD_BUSY | SMI_CMD_C45) 270 #define SMI_CMD_OP_C45_READ \ 271 (SMI_CMD_C45_READ | SMI_CMD_BUSY | SMI_CMD_C45) 272 #define SMI_CMD_DEV_ADDR 5 273 #define SMI_CMD_DEV_ADDR_MASK 0x3e0 274 #define SMI_CMD_REG_ADDR_MASK 0x1f 275 #define SMI_PHY_DATA_REG 0x19 276 #define PHY_DATA_MASK 0xffff 277 278 #define PHY_PAGE_REG 22 279 280 /* 281 * Scratch and Misc register accessed via 282 * 'Switch Global Registers' (REG_GLOBAL2) 283 */ 284 #define SCR_AND_MISC_REG 0x1a 285 286 #define SCR_AND_MISC_PTR_CFG 0x7000 287 #define SCR_AND_MISC_DATA_CFG_MASK 0xf0 288 289 /* SERDES registers. */ 290 #define E6000SW_SERDES_DEV 4 291 #define E6000SW_SERDES_PCS_CTL1 0x1000 292 #define E6000SW_SERDES_SGMII_CTL 0x2000 293 #define E6000SW_SERDES_PDOWN (1 << 11) 294 295 #define E6000SW_NUM_VLANS 128 296 #define E6000SW_NUM_LAGMASK 8 297 #define E6000SW_NUM_PHY_REGS 29 298 #define E6000SW_MAX_PORTS 11 299 #define E6000SW_DEFAULT_AGETIME 20 300 #define E6000SW_RETRIES 100 301 #define E6000SW_SMI_TIMEOUT 16 302 303 #endif /* _E6000SWREG_H_ */ 304